diff --git a/.travis.yml b/.travis.yml index fdb5520c3a8..40d81b43e76 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,3 +1,6 @@ +language: python +python: + '2.7' env: global: @@ -11,13 +14,22 @@ env: "target_url": "https://travis-ci.org/$TRAVIS_REPO_SLUG/jobs/$TRAVIS_JOB_ID" }\nDATA' +cache: + pip: true + directories: + - $HOME/.cache/apt + - $HOME/gcc-arm-none-eabi-6-2017-q2-update + before_install: - bash -c "$STATUS" pending "Local $NAME testing is in progress" # Make sure pipefail - set -o pipefail + # Setup apt to cache + - mkdir -p $HOME/.cache/apt/partial + - sudo rm -rf /var/cache/apt/archives + - sudo ln -s $HOME/.cache/apt /var/cache/apt/archives # Setup ppa to make sure arm-none-eabi-gcc is correct version - sudo add-apt-repository -y ppa:team-gcc-arm-embedded/ppa - - sudo add-apt-repository -y ppa:libreoffice/libreoffice-4-2 - sudo apt-get update -qq after_success: @@ -28,22 +40,12 @@ after_failure: matrix: include: - - python: '2.7' - env: - - NAME=tools + - env: + - NAME=docs install: # Install dependencies - - sudo apt-get install gcc-arm-embedded doxygen - - pip install --user -r requirements.txt - - pip install --user pytest - - pip install --user pylint - - pip install --user hypothesis - - pip install --user mock - - pip install --user coverage - - pip install --user coveralls + - sudo apt-get install doxygen # Print versions we use - - arm-none-eabi-gcc --version - - python --version - doxygen --version before_script: # Create BUILD directory for tests @@ -52,24 +54,38 @@ matrix: # Assert that the Doxygen build produced no warnings. # The strange command below asserts that the Doxygen command had an # output of zero length - - | - doxygen doxyfile_options 2>&1 | tee BUILD/doxygen.out && [ ! -s BUILD/doxygen.out ] + - > + doxygen doxyfile_options 2>&1 | + tee BUILD/doxygen.out && [ ! -s BUILD/doxygen.out ] # Assert that all binary libraries are named correctly - # The strange command below asserts that there are exactly 0 libraries that do - # not start with lib - - | - find "(" -name "*.a" -or -name "*.ar" ")" -and -not -name "lib*" | tee BUILD/badlibs | sed -e "s/^/Bad library name found: /" && [ ! -s BUILD/badlibs ] + # The strange command below asserts that there are exactly 0 libraries + # that do not start with lib + - > + find "(" -name "*.a" -or -name "*.ar" ")" -and -not -name "lib*" | + tee BUILD/badlibs | + sed -e "s/^/Bad library name found: /" && [ ! -s BUILD/badlibs ] # Assert that all assebler files are named correctly - # The strange command below asserts that there are exactly 0 libraries that do - # end with .s - - | - find -name "*.s" | tee BUILD/badasm | sed -e "s/^/Bad Assembler file name found: /" && [ ! -s BUILD/badasm ] + # The strange command below asserts that there are exactly 0 libraries + # that do end with .s + - > + find -name "*.s" | tee BUILD/badasm | + sed -e "s/^/Bad Assembler file name found: /" && [ ! -s BUILD/badasm ] + + - env: + - NAME=tools + install: + # Install dependencies + - sudo apt-get install gcc-arm-embedded + - pip install -r requirements.txt + - pip install pytest pylint hypothesis mock coverage coveralls + # Print versions we use + - arm-none-eabi-gcc --version + - python --version + script: # Run local testing on tools - # Note: These take ~40 minutes to run - PYTHONPATH=. coverage run -a -m pytest tools/test - python2 tools/test/pylint.py - coverage run -a tools/project.py -S | sed -n '/^Total/p' - # - python2 -u tools/build_travis.py | sed -n '/^Executing/p' - coverage html after_success: # Coverage for tools @@ -77,14 +93,13 @@ matrix: # Report success since we have overridden default behaviour - bash -c "$STATUS" success "Local $NAME testing has passed" - - python: '2.7' - env: + - env: - NAME=events - EVENTS=events install: # Install dependencies - sudo apt-get install gcc-arm-embedded - - pip install --user -r requirements.txt + - pip install -r requirements.txt # Print versions we use - arm-none-eabi-gcc --version - gcc --version @@ -96,14 +111,13 @@ matrix: # Run local equeue tests - make -C $EVENTS/equeue test - - python: '2.7' - env: + - env: - NAME=littlefs - LITTLEFS=features/filesystem/littlefs install: # Install dependencies - sudo apt-get install gcc-arm-embedded fuse libfuse-dev - - pip install --user -r requirements.txt + - pip install -r requirements.txt - git clone https://github.com/armmbed/spiflash-driver.git # Print versions - arm-none-eabi-gcc --version @@ -128,11 +142,10 @@ matrix: # Run local littlefs tests - CFLAGS="-Wno-format" make -C$LITTLEFS/littlefs test QUIET=1 # Run local littlefs tests with set of variations - - CFLAGS="-Wno-format -DLFS_READ_SIZE=64 -DLFS_PROG_SIZE=64" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_BLOCK_COUNT=1023" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_LOOKAHEAD=2048" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_READ_SIZE=64 -DLFS_PROG_SIZE=64" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_BLOCK_COUNT=1023 -DLFS_LOOKAHEAD=2048" make -C$LITTLEFS/littlefs test QUIET=1 # Self-hosting littlefs fuzz test with littlefs-fuse - make -Clittlefs_fuse - littlefs_fuse/lfs --format /dev/loop0 @@ -143,13 +156,16 @@ matrix: - ls MOUNT/littlefs - CFLAGS="-Wno-format" make -CMOUNT/littlefs -B test_dirs QUIET=1 - - python: '2.7' - env: - - NAME=mbed2 + - &mbed-2 + env: NAME=mbed2-NXP install: # Install dependencies - - sudo apt-get install gcc-arm-embedded - - pip install --user -r requirements.txt + - export GCC_DIR=$HOME/gcc-arm-none-eabi-6-2017-q2-update + - export GCC_ARCHIVE=$HOME/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 + - export GCC_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/6-2017q2/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2?revision=2cc92fb5-3e0e-402d-9197-bdfc8224d8a5?product=GNU%20Arm%20Embedded%20Toolchain,64-bit,,Linux,6-2017-q2-update + - if [ ! -e $GCC_DIR/bin/arm-none-eabi-gcc ]; then wget $GCC_URL -O $GCC_ARCHIVE; tar xfj $GCC_ARCHIVE -C $HOME; fi + - export PATH=$PATH:$GCC_DIR/bin + - pip install -r requirements.txt # Print versions we use - arm-none-eabi-gcc --version - python --version @@ -158,6 +174,18 @@ matrix: - mkdir BUILD script: # Run local mbed 2 testing - # Note: These take ~40 minutes to run - - python2 -u tools/build_travis.py | sed -n '/^Executing/p' - + - python2 -u tools/build_travis.py --vendor "${NAME#mbed2-}" + - <<: *mbed-2 + env: NAME=mbed2-STM + - <<: *mbed-2 + env: NAME=mbed2-NORDIC + - <<: *mbed-2 + env: NAME=mbed2-SILICON_LABS + - <<: *mbed-2 + env: NAME=mbed2-MAXIM + - <<: *mbed-2 + env: NAME=mbed2-ATMEL + - <<: *mbed-2 + env: NAME=mbed2-NUVOTON + - <<: *mbed-2 + env: NAME=mbed2-RENESAS diff --git a/README.md b/README.md index ee51e5fd6e1..68b9acaaf0d 100644 --- a/README.md +++ b/README.md @@ -1,32 +1,35 @@ -# ARM mbed OS +[![Mbed OS][mbed-os-logo]][mbed-os-link] + +[![Build status release][mbed-travis-release-svg]][mbed-travis-release] +[![Build status master][mbed-travis-master-svg]][mbed-travis-master] +[![Tools coverage status][mbed-coveralls-tools-svg]][mbed-coveralls-tools] +[![PR progress][mbed-waffle-svg]][mbed-waffle] + +[mbed-os-logo]: logo.png +[mbed-os-link]: https://www.mbed.com/en/platform/mbed-os/ +[mbed-travis-master]: https://travis-ci.org/ARMmbed/mbed-os +[mbed-travis-master-svg]: https://travis-ci.org/ARMmbed/mbed-os.svg?branch=master +[mbed-travis-release]: https://travis-ci.org/ARMmbed/mbed-os/branches +[mbed-travis-release-svg]: https://travis-ci.org/ARMmbed/mbed-os.svg?branch=latest +[mbed-coveralls-tools]: https://coveralls.io/github/ARMmbed/mbed-os?branch=master +[mbed-coveralls-tools-svg]: https://coveralls.io/repos/github/ARMmbed/mbed-os/badge.svg?branch=master +[mbed-waffle]: https://waffle.io/ARMmbed/mbed-os +[mbed-waffle-svg]: https://badge.waffle.io/ARMmbed/mbed-os.svg?columns=all + +Arm Mbed OS is an open source embedded operating system designed specifically for the "things" in the Internet of Things. It includes all the features you need to develop a connected product based on an Arm Cortex-M microcontroller, including security, connectivity, an RTOS and drivers for sensors and I/O devices. + +Mbed OS provides a platform that includes: +* Security foundations. +* Cloud management services. +* Drivers for sensors, I/O devices and connectivity. + +## Release notes +The [release notes](https://os.mbed.com/releases) detail the current release. You can also find information about previous versions. + +## Getting started for developers -mbed OS is an open-source embedded operating system designed for the "things" in the Internet of Things (IoT). mbed OS includes the features you need to develop a connected product using an ARM Cortex-M microcontroller. - -mbed OS provides a platform that includes: - - Security foundations. - - Cloud management services. - - Drivers for sensors, I/O devices and connectivity. - -mbed OS is modular, configurable software that you can customize it to your device and to reduce memory requirements by excluding unused software. - - -## Release Notes - -The [Release Notes](https://docs.mbed.com/docs/mbed-os-release-notes/en/latest/) detail the current release and previous versions. - -## Continuous Integration Status - -We run continuous integration on all of our branches and pull requests to verify the stability of mbed OS. The following are the Travis CI indicators for mbed OS. - - - Master branch [![Master Branch CI Badge](https://travis-ci.org/ARMmbed/mbed-os.svg?branch=master)](https://travis-ci.org/ARMmbed/mbed-os) - - Latest release [![Latest Tag CI Badge](https://travis-ci.org/ARMmbed/mbed-os.svg?branch=latest)](https://travis-ci.org/ARMmbed/mbed-os/branches) - -Tools coverage [![Coverage Status](https://coveralls.io/repos/github/ARMmbed/mbed-os/badge.svg?branch=master)](https://coveralls.io/github/ARMmbed/mbed-os?branch=master) - -## Getting Started for Developers - -You need [mbed CLI](https://github.com/ARMmbed/mbed-cli) to build mbed OS. For more details, read the [mbed OS Handbook](https://docs.mbed.com/docs/mbed-os-handbook/en/latest/). +We have a [developer website](https://os.mbed.com) for asking questions, engaging with others, finding information on boards and components, using an online IDE and compiler, reading the documentation and learning about what's new and what's coming next in Mbed OS. -## Getting Started for Contributors +## Getting started for contributors -We have a [Contributing and Publishing Guide](https://docs.mbed.com/docs/mbed-os-handbook/en/latest/cont/contributing/) in the mbed OS Handbook. +We also have a [contributing and publishing guide](https://os.mbed.com/contributing/) that covers licensing, contributor agreements and style guidelines. diff --git a/TESTS/host_tests/rtc_calc_auto.py b/TESTS/host_tests/rtc_calc_auto.py new file mode 100644 index 00000000000..77b52a0abc0 --- /dev/null +++ b/TESTS/host_tests/rtc_calc_auto.py @@ -0,0 +1,140 @@ +""" +mbed SDK +Copyright (c) 2011-2013 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +from mbed_host_tests import BaseHostTest +import time +import calendar +import datetime + +class RTC_time_calc_test(BaseHostTest): + """ + This is the host part of the test to verify if: + - _rtc_mktime function converts a calendar time into time since UNIX epoch as a time_t, + - _rtc_localtime function converts a given time in seconds since epoch into calendar time. + + The same algoritm to generate next calendar time to be tested is used by both parts of the test. + We will check if correct time since UNIX epoch is calculated for the first and the last day + of each month and across valid years. + + Mbed part of the test sends calculated time since UNIX epoch. + This part validates given value and responds to indicate pass or fail. + Additionally it sends also encoded day of week and day of year which + will be needed to verify _rtc_localtime. + + Support for both types of RTC devices is provided: + - RTCs which handles all leap years in the mentioned year range correctly. Leap year is determined by checking if + the year counter value is divisible by 400, 100, and 4. No problem here. + - RTCs which handles leap years correctly up to 2100. The RTC does a simple bit comparison to see if the two + lowest order bits of the year counter are zero. In this case 2100 year will be considered + incorrectly as a leap year, so the last valid point in time will be 28.02.2100 23:59:59 and next day will be + 29.02.2100 (invalid). So after 28.02.2100 the day counter will be off by a day. + + """ + + edge_date = datetime.datetime(2100, 2, 28, 0, 0, 0) + + # Test the following years: + # - first - 1970 + # - example not leap year (not divisible by 4) + # - example leap year (divisible by 4 and by 100 and by 400) + # - example leap year (divisible by 4 and not by 100) + # - example not leap year (divisible by 4 and by 100) + # - last fully supported - 2105 + years = [1970, 1971, 2000, 2096, 2100, 2105] + year_id = 0 + + + + full_leap_year_support = False + + RTC_FULL_LEAP_YEAR_SUPPORT = 0 + RTC_PARTIAL_LEAP_YEAR_SUPPORT = 1 + + def _set_leap_year_support(self, key, value, timestamp): + if (int(value) == self.RTC_FULL_LEAP_YEAR_SUPPORT): + self.full_leap_year_support = True + else: + self.full_leap_year_support = False + + self.first = True + self.date = datetime.datetime(1970, 1, 1, 23, 0, 0) + self.year_id = 0 + + def _verify_timestamp(self, key, value, timestamp): + # week day in python is counted from sunday(0) and on mbed side week day is counted from monday(0). + # year day in python is counted from 1 and on mbed side year day is counted from 0. + week_day = ((self.date.timetuple().tm_wday + 1) % 7) + year_day = self.date.timetuple().tm_yday - 1 + + # Fix for RTC which not have full leap year support. + if (not self.full_leap_year_support): + if self.date >= self.edge_date: + # After 28.02.2100 we should be one day off - add this day and store original + date_org = self.date + self.date += datetime.timedelta(days = 1) + + # Adjust week day. + week_day = ((self.date.timetuple().tm_wday + 1) % 7) + + # Adjust year day. + if (self.date.year == 2100): + year_day = self.date.timetuple().tm_yday - 1 + else: + year_day = date_org.timetuple().tm_yday - 1 + + # Last day in year + if (self.date.month == 1 and self.date.day == 1): + if (self.date.year == 2101): + # Exception for year 2100 - ivalid handled by RTC without full leap year support + year_day = 365 + else: + year_day = date_org.timetuple().tm_yday - 1 + + t = (self.date.year , self.date.month, self.date.day, self.date.hour, self.date.minute, self.date.second, 0, 0, 0) + + expected_timestamp = calendar.timegm(t) + actual_timestamp = int(value) & 0xffffffff # convert to unsigned int + + # encode week day and year day in the response + response = (week_day << 16) | year_day + + if (actual_timestamp == expected_timestamp): + # response contains encoded week day and year day + self.send_kv("passed", str(response)) + else: + self.send_kv("failed", 0) + print "expected = %d, result = %d" % (expected_timestamp , actual_timestamp) + + # calculate next date + if (self.first): + days_range = calendar.monthrange(self.date.year, self.date.month) + self.date = self.date.replace(day = days_range[1], minute = 59, second = 59) + self.first = not self.first + else: + self.date += datetime.timedelta(days = 1) + if (self.date.month == 1): + self.year_id += 1 + if (len(self.years) == self.year_id): + # All years were processed, no need to calc next date + return + self.date = self.date.replace(year = self.years[self.year_id]) + self.date = self.date.replace(day = 1, minute = 0, second = 0) + self.first = not self.first + + def setup(self): + self.register_callback('timestamp', self._verify_timestamp) + self.register_callback('leap_year_setup', self._set_leap_year_support) diff --git a/TESTS/mbed_drivers/lp_timer/main.cpp b/TESTS/mbed_drivers/lp_timer/main.cpp index bf3f09639e8..a7232149a30 100644 --- a/TESTS/mbed_drivers/lp_timer/main.cpp +++ b/TESTS/mbed_drivers/lp_timer/main.cpp @@ -51,13 +51,17 @@ extern uint32_t SystemCoreClock; * For K64F DELTA = (80000 / 120000000) * 1000000 = 666[us] * For NUCLEO_F070RB DELTA = (80000 / 48000000) * 1000000 = 1666[us] * For NRF51_DK DELTA = (80000 / 16000000) * 1000000 = 5000[us] + * + * As low power timer cannot be too much accurate, this DELTA should not be more precise than 500us, + * which corresponds to a maximum CPU clock around 130MHz */ #define US_PER_SEC 1000000 #define US_PER_MSEC 1000 #define TOLERANCE_FACTOR 80000.0f #define US_FACTOR 1000000.0f +#define CLOCK_MAX 130000000 -static const int delta_sys_clk_us = ((int) (TOLERANCE_FACTOR / (float) SystemCoreClock * US_FACTOR)); +static const int delta_sys_clk_us = (SystemCoreClock < CLOCK_MAX? ((int) (TOLERANCE_FACTOR / (float) SystemCoreClock * US_FACTOR)):((int) (TOLERANCE_FACTOR / (float) CLOCK_MAX * US_FACTOR))); /* When test performs time measurement using Timer in sequence, then measurement error accumulates * in the successive attempts. */ diff --git a/TESTS/mbed_drivers/mem_trace/main.cpp b/TESTS/mbed_drivers/mem_trace/main.cpp index 5b10b45a621..286be0377b0 100644 --- a/TESTS/mbed_drivers/mem_trace/main.cpp +++ b/TESTS/mbed_drivers/mem_trace/main.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -28,15 +28,27 @@ #error [NOT_SUPPORTED] test not supported #endif -using namespace utest::v1; +using utest::v1::Case; + /******************************************************************************/ /* Helper functions and data structures */ /******************************************************************************/ +#define THREAD_STACK_SIZE 384 +#define NUM_TEST_THREADS 3 + +template +class TestThread : public Thread { + uint8_t stack[STACK_SIZE]; +public: + TestThread() : Thread(PRIORITY, STACK_SIZE, stack) { } +}; + // This structure keeps data about the various memory allocation operations, // as traced by 'test_trace_cb' below. #define TEST_MAX_MEMORY_OPS 10 + // Trace results for all possible operations typedef struct { uint8_t op; @@ -58,24 +70,28 @@ typedef struct { } free_info; }; } mem_trace_data_t; + // Memory operation statistics typedef struct { mem_trace_data_t op_data[TEST_MAX_MEMORY_OPS]; uint32_t total_ops; bool invalid_op, overflow; } stats_t; + static stats_t stats; + // Clear all the memory statistics -static void test_clear_stats() { +static void test_clear_stats() +{ memset(&stats, 0, sizeof(stats)); } // Memory tracer callback that records each operation in "stats" (above) -extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) { +extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) +{ va_list va; mem_trace_data_t *pmem = stats.op_data + stats.total_ops; - if (stats.total_ops >= TEST_MAX_MEMORY_OPS) { stats.overflow = true; return; @@ -110,180 +126,305 @@ extern "C" void test_trace_cb(uint8_t op, void *res, void *caller, ...) { } // Generic sanity checks for the tracer -static void check_sanity(uint32_t expected_ops) { +static void check_sanity(uint32_t expected_ops) +{ TEST_ASSERT_FALSE(stats.overflow); TEST_ASSERT_FALSE(stats.invalid_op); - TEST_ASSERT_EQUAL_UINT32(stats.total_ops, expected_ops); + TEST_ASSERT_EQUAL_UINT32(expected_ops, stats.total_ops); } // Check a "malloc" operation -static void check_malloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_size) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_MALLOC); - TEST_ASSERT_EQUAL_PTR(p->res, expected_res); - TEST_ASSERT_EQUAL_UINT32(p->malloc_info.arg_size, expected_arg_size); +static void check_malloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_size) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_MALLOC, p->op); + TEST_ASSERT_EQUAL_PTR(expected_res, p->res); + TEST_ASSERT_EQUAL_UINT32(expected_arg_size, p->malloc_info.arg_size); } // Check a "free" operation -static void check_free_op(const mem_trace_data_t *p, void *expected_arg_ptr) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_FREE); - TEST_ASSERT_EQUAL_PTR(p->free_info.arg_ptr, expected_arg_ptr); +static void check_free_op(const mem_trace_data_t *p, void *expected_arg_ptr) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_FREE, p->op); + TEST_ASSERT_EQUAL_PTR(expected_arg_ptr, p->free_info.arg_ptr); } // Check a "realloc" operation -static void check_realloc_op(const mem_trace_data_t *p, void *expected_res, void *expected_arg_ptr, size_t expected_arg_size) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_REALLOC); - TEST_ASSERT_EQUAL_PTR(p->res, expected_res); - TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_ptr, expected_arg_ptr); - TEST_ASSERT_EQUAL_UINT32(p->realloc_info.arg_size, expected_arg_size); +static void check_realloc_op(const mem_trace_data_t *p, void *expected_res, void *expected_arg_ptr, size_t expected_arg_size) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_REALLOC, p->op); + TEST_ASSERT_EQUAL_PTR(expected_res, p->res); + TEST_ASSERT_EQUAL_UINT32(expected_arg_ptr, p->realloc_info.arg_ptr); + TEST_ASSERT_EQUAL_UINT32(expected_arg_size, p->realloc_info.arg_size); } // Check a "calloc" operation -static void check_calloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_nmemb, size_t expected_arg_size) { - TEST_ASSERT_EQUAL_UINT8(p->op, MBED_MEM_TRACE_CALLOC); - TEST_ASSERT_EQUAL_PTR(p->res, expected_res); - TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_nmemb, expected_arg_nmemb); - TEST_ASSERT_EQUAL_UINT32(p->calloc_info.arg_size, expected_arg_size); +static void check_calloc_op(const mem_trace_data_t *p, void *expected_res, size_t expected_arg_nmemb, size_t expected_arg_size) +{ + TEST_ASSERT_EQUAL_UINT8(MBED_MEM_TRACE_CALLOC, p->op); + TEST_ASSERT_EQUAL_PTR(expected_res, p->res); + TEST_ASSERT_EQUAL_UINT32(expected_arg_nmemb, p->calloc_info.arg_nmemb); + TEST_ASSERT_EQUAL_UINT32(expected_arg_size, p->calloc_info.arg_size); } -/******************************************************************************/ -/* Tests */ -/******************************************************************************/ +// Memory tracer callback to test thread safety +extern "C" void test_trace_cb_multithread(uint8_t op, void *res, void *caller, ...) +{ + volatile static int trace_guard = 0; + trace_guard++; + TEST_ASSERT_TRUE_MESSAGE(trace_guard == 1, "Race condition occurred !!!!"); + trace_guard--; +} -// Allocate a single buffer, then free it. Check that tracing matches the operations. -static void test_case_single_malloc_free() { +// Thread function +void malloc_free(volatile bool *thread_continue) +{ + const size_t block_size = 126; + + while(*thread_continue) { + void *p = malloc(block_size); + TEST_ASSERT_NOT_EQUAL(p, NULL); + free(p); + } +} + + +/** Test single malloc/free tracing + * + * Given a memory trace mechanism + * When perform single memory allocation/deallocation using malloc/free + * Then tracing matches the operations + * + */ +static void test_case_single_malloc_free() +{ + const uint32_t num_op = 2; const size_t block_size = 126; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a single memory block void *p = malloc(block_size); TEST_ASSERT_NOT_EQUAL(p, NULL); + // Free the memory block free(p); + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(2); - check_malloc_op(pmem ++, p, block_size); + check_sanity(num_op); + check_malloc_op(pmem++, p, block_size); check_free_op(pmem, p); } -// Test all memory operations (malloc, realloc, free, calloc) -static void test_case_all_memory_ops() { + +/** Test all memory operations (malloc, realloc, free, calloc) tracing + * + * Given a memory trace mechanism + * When perform all memory operations + * Then tracing matches the operations + * + */ +static void test_case_all_memory_ops() +{ + const uint32_t num_op = 5; const size_t malloc_size = 40, realloc_size = 80, nmemb = 25, size = 10; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a single memory block, the realloc it void *p_malloc = malloc(malloc_size); TEST_ASSERT_NOT_EQUAL(p_malloc, NULL); void *p_realloc = realloc(p_malloc, realloc_size); TEST_ASSERT_NOT_EQUAL(p_realloc, NULL); + // Use calloc() now void *p_calloc = calloc(nmemb, size); - //TEST_ASSERT_NOT_EQUAL(p_calloc, NULL); + TEST_ASSERT_NOT_EQUAL(p_calloc, NULL); + // Free the realloc() pointer first, then the calloc() one free(p_realloc); free(p_calloc); + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(6); - check_malloc_op(pmem ++, p_malloc, malloc_size); - check_realloc_op(pmem ++, p_realloc, p_malloc, realloc_size); - // calloc() calls malloc() internally - check_malloc_op(pmem ++, p_calloc, nmemb * size); - check_calloc_op(pmem ++, p_calloc, nmemb, size); - check_free_op(pmem ++, p_realloc); + check_sanity(num_op); + check_malloc_op(pmem++, p_malloc, malloc_size); + check_realloc_op(pmem++, p_realloc, p_malloc, realloc_size); + check_calloc_op(pmem++, p_calloc, nmemb, size); + check_free_op(pmem++, p_realloc); check_free_op(pmem, p_calloc); } -// Test that tracing is off when using a NULL callback -static void test_case_trace_off() { + +/** Test that tracing is off when using a NULL callback + * + * Given a memory trace mechanism + * When tracing is turned off + * Then performed memory operations doesn't report any tracing + * + */ +static void test_case_trace_off() +{ + const uint32_t num_op = 0; const size_t malloc_size = 10; test_clear_stats(); // We don't want any tracing mbed_mem_trace_set_callback(NULL); + // Allocate a buffer and free it void *p_malloc = malloc(malloc_size); TEST_ASSERT_NOT_EQUAL(p_malloc, NULL); free(p_malloc); + // Check that we didn't trace anything - check_sanity(0); + check_sanity(num_op); } -// Test partial tracing (start tracing, stop tracing, restart later) -static void test_case_partial_trace() { + +/** Test partial tracing + * + * Given a memory trace mechanism + * When perform memory operations while tracing is on then off and on again + * Then tracing report only part of operations + * + */ +static void test_case_partial_trace() +{ + const uint32_t num_op = 2; const size_t malloc_size_1 = 20, malloc_size_2 = 30; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); + // Start tracing mbed_mem_trace_set_callback(test_trace_cb); + // Allocate a buffer void *p_malloc_1 = malloc(malloc_size_1); TEST_ASSERT_NOT_EQUAL(p_malloc_1, NULL); + // Disable tracing before freeing the first buffer mbed_mem_trace_set_callback(NULL); free(p_malloc_1); + // Allocate another buffer (still not traced) void *p_malloc_2 = malloc(malloc_size_2); TEST_ASSERT_NOT_EQUAL(p_malloc_2, NULL); + // Re-enable tracing mbed_mem_trace_set_callback(test_trace_cb); + // And free the second buffer (this operation should be tracer) free(p_malloc_2); + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(2); - check_malloc_op(pmem ++, p_malloc_1, malloc_size_1); + check_sanity(num_op); + check_malloc_op(pmem++, p_malloc_1, malloc_size_1); check_free_op(pmem, p_malloc_2); } -// Test new/delete tracing -static void test_case_new_delete() { + +/** Test new/delete tracing + * + * Given a memory trace mechanism + * When memory allocation/deallocation is performed using new/delete + * Then tracing matches the operations + * + */ +static void test_case_new_delete() +{ + const uint32_t num_op = 4; const mem_trace_data_t *pmem = stats.op_data; test_clear_stats(); + // Start tracing mbed_mem_trace_set_callback(test_trace_cb); + // Test new, new[], delete and delete[] int *p_int = new int; int *p_int_array = new int[10]; delete p_int; delete[] p_int_array; + // Stop tracing mbed_mem_trace_set_callback(NULL); + // Check tracer result - check_sanity(4); - check_malloc_op(pmem ++, p_int, sizeof(int)); - check_malloc_op(pmem ++, p_int_array, 10 * sizeof(int)); - check_free_op(pmem ++, p_int); - check_free_op(pmem ++, p_int_array); + check_sanity(num_op); + check_malloc_op(pmem++, p_int, sizeof(int)); + check_malloc_op(pmem++, p_int_array, 10 * sizeof(int)); + check_free_op(pmem++, p_int); + check_free_op(pmem, p_int_array); } -static Case cases[] = { - Case("single malloc/free", test_case_single_malloc_free), - Case("all memory operations", test_case_all_memory_ops), - Case("trace off", test_case_trace_off), - Case("partial trace", test_case_partial_trace), - Case("test new/delete", test_case_new_delete) + +/** Test tracing thread safety + * + * Given a memory trace mechanism and multiple threads are started in parallel + * When each of the threads perform memory allocation/deallocation (thus uses memory trace mechanisms) + * Then tracing is protected against simultaneous multithreaded access + * + */ +static void test_case_multithread_malloc_free() +{ + const uint32_t wait_time_us = 10000; + volatile bool threads_continue; + TestThread threads[NUM_TEST_THREADS]; + + mbed_mem_trace_set_callback(test_trace_cb_multithread); + + threads_continue = true; + for (int i = 0; i < NUM_TEST_THREADS; i++) { + threads[i].start(callback(malloc_free, &threads_continue)); + } + + Thread::wait(wait_time_us); + threads_continue = false; + + for (int i = 0; i < NUM_TEST_THREADS; i++) { + threads[i].join(); + } + + mbed_mem_trace_set_callback(NULL); +} + + + +static Case cases[] = +{ + Case("Test single malloc/free trace", test_case_single_malloc_free), + Case("Test all memory operations trace", test_case_all_memory_ops), + Case("Test trace off", test_case_trace_off), + Case("Test partial trace", test_case_partial_trace), + Case("Test new/delete trace", test_case_new_delete), + Case("Test multithreaded trace", test_case_multithread_malloc_free) }; -static status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(20, "default_auto"); - return greentea_test_setup_handler(number_of_cases); +static utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(15, "default_auto"); + return utest::v1::greentea_test_setup_handler(number_of_cases); } -static Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); +static utest::v1::Specification specification(greentea_test_setup, cases, utest::v1::greentea_test_teardown_handler); -int main() { +int main() +{ // Disable stdout buffering to prevent any unwanted allocations setvbuf(stdout, NULL, _IONBF, 0); - Harness::run(specification); -} + return !utest::v1::Harness::run(specification); +} diff --git a/TESTS/mbed_drivers/race_test/main.cpp b/TESTS/mbed_drivers/race_test/main.cpp index f4753f9bf40..48ce06a6f70 100644 --- a/TESTS/mbed_drivers/race_test/main.cpp +++ b/TESTS/mbed_drivers/race_test/main.cpp @@ -58,11 +58,13 @@ static SingletonPtr test_class; static void main_func_race() { get_test_class(); + TEST_ASSERT_EQUAL_UINT32(1, instance_count); } static void main_class_race() { test_class->do_something(); + TEST_ASSERT_EQUAL_UINT32(1, instance_count); } void test_case_func_race() diff --git a/TESTS/mbed_hal/device_key/main.cpp b/TESTS/mbed_hal/device_key/main.cpp new file mode 100644 index 00000000000..c9351dd4b94 --- /dev/null +++ b/TESTS/mbed_hal/device_key/main.cpp @@ -0,0 +1,97 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "utest/utest.h" +#include "unity/unity.h" +#include "greentea-client/test_env.h" + +#include "mbed.h" +#include "device_key_api.h" + + + +#ifndef DEVICE_DEVKEY +#error [NOT_SUPPORTED] DEVICE_KEY needs to be enabled for this test +#endif + +using namespace utest::v1; + +enum DeviceKeyType{ + + DEVICE_KEY_16BYTE=16, + DEVICE_KEY_32BYTE=32 +}; + + +//check if the size of the expected key is same us the api declare it. +void device_key_get_size_test() +{ + size_t len = device_key_get_size_in_bytes(); + TEST_ASSERT_FALSE_MESSAGE(DEVICE_KEY_16BYTE != len && DEVICE_KEY_32BYTE != len, "Device key length is not 16 or 32 Byte long"); +} + +void device_key_get_key_length_test() +{ + size_t expected = device_key_get_size_in_bytes(); + size_t len=expected; + uint32_t buffer[DEVICE_KEY_32BYTE]; + memset(buffer, 0, DEVICE_KEY_32BYTE); + int status = device_key_get_value(buffer, &len); + + TEST_ASSERT_EQUAL_INT32(0, status); + + TEST_ASSERT_EQUAL_INT32(expected, len); + +} + +void device_key_check_consistency_key_test() +{ + uint32_t buffer1[DEVICE_KEY_32BYTE]; + uint32_t buffer2[DEVICE_KEY_32BYTE]; + size_t len1=DEVICE_KEY_32BYTE; + size_t len2=DEVICE_KEY_32BYTE; + + memset(buffer1, 0, DEVICE_KEY_32BYTE*sizeof(uint32_t)); + int status = device_key_get_value(buffer1, &len1); + TEST_ASSERT_EQUAL_INT32(0, status); + + for (int i=0; i<100; i++) + { + memset(buffer2, 0, DEVICE_KEY_32BYTE*sizeof(uint32_t)); + status = device_key_get_value(buffer2, &len2); + TEST_ASSERT_EQUAL_INT32(0, status); + TEST_ASSERT_EQUAL_INT32_ARRAY(buffer1,buffer2,DEVICE_KEY_32BYTE); + len2=DEVICE_KEY_32BYTE; + } +} + +Case cases[] = { + Case("Device Key - get size", device_key_get_size_test), + Case("Device Key - get key length", device_key_get_key_length_test), + Case("Device Key - check consistency key", device_key_check_consistency_key_test) +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { + GREENTEA_SETUP(20, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() +{ + return Harness::run(specification); +} diff --git a/TESTS/mbed_hal/flash/functional_tests/main.cpp b/TESTS/mbed_hal/flash/functional_tests/main.cpp index 156899410a2..0170d2255e9 100644 --- a/TESTS/mbed_hal/flash/functional_tests/main.cpp +++ b/TESTS/mbed_hal/flash/functional_tests/main.cpp @@ -28,7 +28,7 @@ using namespace utest::v1; #define TEST_CYCLES 1000000 -#define ALLOWED_DRIFT_PPM 1000 //0.1% +#define ALLOWED_DRIFT_PPM 5000 //0.5% /* return values to be checked are documented at: diff --git a/TESTS/mbed_hal/rtc_time/main.cpp b/TESTS/mbed_hal/rtc_time/main.cpp index 3791b4751a0..c101e19b625 100644 --- a/TESTS/mbed_hal/rtc_time/main.cpp +++ b/TESTS/mbed_hal/rtc_time/main.cpp @@ -21,23 +21,15 @@ #include "mbed.h" #include "mbed_mktime.h" -// Limit the test range to 1935 for IAR only. From the IAR C/C++ Development Guide: -// "The 32-bit interface supports years from 1900 up to 2035 and uses a 32-bit integer -// for time_t." -#ifdef __ICCARM__ -#define LOCALTIME_MAX 2082758400 // 1st of january 2036 at 00:00:00 -#define MKTIME_YR_MAX 136 -#else -#define LOCALTIME_MAX INT_MAX -#define MKTIME_YR_MAX 137 -#endif +#define LAST_VALID_YEAR 206 using namespace utest::v1; -/* - * regular is_leap_year, see platform/mbed_mktime.c for the optimized version - */ -bool is_leap_year(int year) { +static rtc_leap_year_support_t rtc_leap_year_support; + +/* Regular is_leap_year, see platform/mbed_mktime.c for the optimised version. */ +bool is_leap_year(int year) +{ year = 1900 + year; if (year % 4) { return false; @@ -49,212 +41,173 @@ bool is_leap_year(int year) { return true; } -/* - * Test the optimized version of _rtc_is_leap_year against the generic version. +/* Test the optimised version of _rtc_is_leap_year() against the generic version. + * + * Note: This test case is designed for both types of RTC devices: + * - RTC devices which handle correctly leap years in whole range (1970 - 2106). + * - RTC devices which does not handle correctly leap years in whole range (1970 - 2106). + * This RTC devices uses simpler leap year detection and incorrectly treat 2100 as a leap year. + * rtc_leap_year_support variable specifies which device is tested. + * + * Given is year in valid range. + * When _rtc_is_leap_year() function is called. + * Then _rtc_is_leap_year() returns true if given year is a leap year; false otherwise. */ -void test_is_leap_year() { - for (int i = 70; i < 138; ++i) { +void test_is_leap_year() +{ + for (int i = 70; i <= LAST_VALID_YEAR; ++i) { bool expected = is_leap_year(i); - bool actual_value = _rtc_is_leap_year(i); - if (expected != actual_value) { - printf ("leap year failed with i = %d\r\n", i); + /* Add exception for year 2100. */ + if (rtc_leap_year_support == RTC_4_YEAR_LEAP_YEAR_SUPPORT && i == 200) { + expected = true; + } + + bool actual_value = _rtc_is_leap_year(i, rtc_leap_year_support); + + if (expected != actual_value) { + printf("Leap year failed with i = %d\r\n", i); } TEST_ASSERT_EQUAL(expected, actual_value); } } -struct tm make_time_info(int year, int month, int day, int hours, int minutes, int seconds) { - struct tm timeinfo = { - seconds, // tm_sec - minutes, // tm_min - hours, // tm_hour - day, // tm_mday - month, // tm_mon - year, // tm_year - 0, // tm_wday - 0, // tm_yday - 0, // tm_isdst - }; - return timeinfo; -} +/* Structure to test border values for _rtc_maketime(). */ +typedef struct +{ + struct tm timeinfo; + time_t exp_seconds; // if result is false then exp_seconds is irrelevant + bool result; +} test_mk_time_struct; + +/* Array which contains data to test boundary values for the RTC devices which handles correctly leap years in + * whole range (1970 - 2106). + * Expected range: the 1st of January 1970 at 00:00:00 (seconds: 0) to the 7th of February 2106 at 06:28:15 (seconds: UINT_MAX). + */ +test_mk_time_struct test_mk_time_arr_full[] = { + {{ 0, 0, 0, 1, 0, 70, 0, 0, 0 }, (time_t) 0, true}, // valid lower bound - the 1st of January 1970 at 00:00:00 + {{ 59, 59, 23, 31, 11, 59, 0, 0, 0 }, (time_t) 0, false }, // invalid lower bound - the 31st of December 1969 at 23:59:59 + + {{ 15, 28, 6, 7, 1, 206, 0, 0, 0 }, (time_t)(UINT_MAX), true }, // valid upper bound - the 7th of February 2106 at 06:28:15 + {{ 16, 28, 6, 7, 1, 206, 0, 0, 0 }, (time_t) 0, false }, // invalid upper bound - the 7th of February 2106 at 06:28:16 +}; -/* - * test out of range values for _rtc_mktime. - * The function operates from the 1st of january 1970 at 00:00:00 to the 19th - * of january 2038 at 03:14:07. +/* Array which contains data to test boundary values for the RTC devices which does not handle correctly leap years in + * whole range (1970 - 2106). On this platforms we will be one day off after 28.02.2100 since 2100 year will be + * incorrectly treated as a leap year. + * Expected range: the 1st of January 1970 at 00:00:00 (seconds: 0) to the 6th of February 2106 at 06:28:15 (seconds: UINT_MAX). */ -void test_mk_time_out_of_range() { - tm invalid_lower_bound = make_time_info( - 69, - 11, - 31, - 23, - 59, - 59 - ); - - tm valid_lower_bound = make_time_info( - 70, - 0, - 1, - 0, - 0, - 0 - ); - - tm valid_upper_bound = make_time_info( - 138, - 0, - 19, - 3, - 14, - 7 - ); - - tm invalid_upper_bound = make_time_info( - 138, - 0, - 19, - 3, - 14, - 8 - ); - - TEST_ASSERT_EQUAL_INT(((time_t) -1), _rtc_mktime(&invalid_lower_bound)); - TEST_ASSERT_EQUAL_INT(((time_t) 0), _rtc_mktime(&valid_lower_bound)); - TEST_ASSERT_EQUAL_INT(((time_t) INT_MAX), _rtc_mktime(&valid_upper_bound)); - TEST_ASSERT_EQUAL_INT(((time_t) -1), _rtc_mktime(&invalid_upper_bound)); -} +test_mk_time_struct test_mk_time_arr_partial[] = { + {{ 0, 0, 0, 1, 0, 70, 0, 0, 0 }, (time_t) 0, true}, // valid lower bound - the 1st of January 1970 at 00:00:00 + {{ 59, 59, 23, 31, 11, 59, 0, 0, 0 }, (time_t) 0, false }, // invalid lower bound - the 31st of December 1969 at 23:59:59 -/* - * test mktime over a large set of values + {{ 15, 28, 6, 6, 1, 206, 0, 0, 0 }, (time_t)(UINT_MAX), true }, // valid upper bound - the 6th of February 2106 at 06:28:15 + {{ 16, 28, 6, 6, 1, 206, 0, 0, 0 }, (time_t) 0, false }, // invalid upper bound - the 6th of February 2106 at 06:28:16 +}; + +/* Test boundary values for _rtc_maketime(). + * + * Note: This test case is designed for both types of RTC devices: + * - RTC devices which handle correctly leap years in whole range (1970 - 2106). + * - RTC devices which does not handle correctly leap years in whole range (1970 - 2106). + * This RTC devices uses simpler leap year detection and incorrectly treat 2100 as a leap year. + * rtc_leap_year_support variable specifies which device is tested. + * + * Given is boundary calendar time. + * When _rtc_maketime() function is called to convert the calendar time into timestamp. + * Then if given calendar time is valid function returns true and conversion result, otherwise returns false. */ -void test_mk_time() { - for (size_t year = 70; year < MKTIME_YR_MAX; ++year) { - for (size_t month = 0; month < 12; ++month) { - for (size_t day = 1; day < 32; ++day) { - if (month == 1 && is_leap_year(year) && day == 29) { - break; - } else if(month == 1 && !is_leap_year(year) && day == 28) { - break; - } else if ( - day == 31 && - (month == 3 || month == 5 || month == 8 || month == 10) - ) { - break; - } - - for (size_t hour = 0; hour < 24; ++hour) { - tm time_info = make_time_info( - year, - month, - day, - hour, - hour % 2 ? 59 : 0, - hour % 2 ? 59 : 0 - ); - - time_t expected = mktime(&time_info); - time_t actual_value = _rtc_mktime(&time_info); - - char msg[128] = ""; - if (expected != actual_value) { - snprintf( - msg, sizeof(msg), - "year = %d, month = %d, day = %d, diff = %ld", - year, month, day, expected - actual_value - ); - } - - TEST_ASSERT_EQUAL_UINT32_MESSAGE(expected, actual_value, msg); - } - } +void test_mk_time_boundary() +{ + test_mk_time_struct *pTestCases; + + /* Select array with test cases. */ + if (rtc_leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT) { + pTestCases = test_mk_time_arr_full; + } else { + pTestCases = test_mk_time_arr_partial; + } + + for (int i = 0; i < (sizeof(test_mk_time_arr_full) / (sizeof(test_mk_time_struct))); i++) { + time_t seconds; + bool result = _rtc_maketime(&pTestCases[i].timeinfo, &seconds, rtc_leap_year_support); + + TEST_ASSERT_EQUAL(pTestCases[i].result, result); + + /* If the result is false, then we have conversion error - skip checking seconds. */ + if (pTestCases[i].result) { + TEST_ASSERT_EQUAL_UINT32(pTestCases[i].exp_seconds, seconds); } } } -/* - * test value out of range for localtime +/* Test _rtc_maketime() function - call with invalid parameters. + * + * Given is _rtc_maketime() function. + * When _rtc_maketime() function is called with invalid parameter. + * Then _rtc_maketime() function returns false. */ -void test_local_time_limit() { - struct tm dummy_value; - TEST_ASSERT_FALSE(_rtc_localtime((time_t) -1, &dummy_value)); - TEST_ASSERT_FALSE(_rtc_localtime((time_t) INT_MIN, &dummy_value)); +void test_mk_time_invalid_param() +{ + time_t seconds; + struct tm timeinfo; + + TEST_ASSERT_EQUAL(false, _rtc_maketime(NULL, &seconds, RTC_FULL_LEAP_YEAR_SUPPORT )); + TEST_ASSERT_EQUAL(false, _rtc_maketime(NULL, &seconds, RTC_4_YEAR_LEAP_YEAR_SUPPORT )); + TEST_ASSERT_EQUAL(false, _rtc_maketime(&timeinfo, NULL, RTC_FULL_LEAP_YEAR_SUPPORT )); + TEST_ASSERT_EQUAL(false, _rtc_maketime(&timeinfo, NULL, RTC_4_YEAR_LEAP_YEAR_SUPPORT )); } -/* - * test _rtc_localtime over a large set of values. +/* Test _rtc_localtime() function - call with invalid parameters. + * + * Given is _rtc_localtime() function. + * When _rtc_localtime() function is called with invalid parameter. + * Then _rtc_localtime() function returns false. */ -void test_local_time() { - for (uint32_t i = 0; i < LOCALTIME_MAX; i += 3451) { - time_t copy = (time_t) i; - struct tm* expected = localtime(©); - struct tm actual_value; - bool result = _rtc_localtime((time_t) i, &actual_value); - - if ( - expected->tm_sec != actual_value.tm_sec || - expected->tm_min != actual_value.tm_min || - expected->tm_hour != actual_value.tm_hour || - expected->tm_mday != actual_value.tm_mday || - expected->tm_mon != actual_value.tm_mon || - expected->tm_year != actual_value.tm_year || - expected->tm_wday != actual_value.tm_wday || - expected->tm_yday != actual_value.tm_yday || - result == false - ) { - printf("error: i = %lu\r\n", i); - } +void test_local_time_invalid_param() +{ + TEST_ASSERT_EQUAL(false, _rtc_localtime(1, NULL, RTC_FULL_LEAP_YEAR_SUPPORT )); + TEST_ASSERT_EQUAL(false, _rtc_localtime(1, NULL, RTC_4_YEAR_LEAP_YEAR_SUPPORT )); +} - TEST_ASSERT_TRUE(result); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_sec, actual_value.tm_sec, "invalid seconds" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_min, actual_value.tm_min, "invalid minutes" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_hour, actual_value.tm_hour, "invalid hours" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_mday, actual_value.tm_mday, "invalid day" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_mon, actual_value.tm_mon, "invalid month" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_year, actual_value.tm_year, "invalid year" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_wday, actual_value.tm_wday, "invalid weekday" - ); - TEST_ASSERT_EQUAL_UINT32_MESSAGE( - expected->tm_yday, actual_value.tm_yday, "invalid year day" - ); - } +utest::v1::status_t teardown_handler_t(const Case * const source, const size_t passed, const size_t failed, + const failure_t reason) +{ + return greentea_case_teardown_handler(source, passed, failed, reason); } -utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) { - greentea_case_failure_abort_handler(source, reason); - return STATUS_CONTINUE; +utest::v1::status_t full_leap_year_case_setup_handler_t(const Case * const source, const size_t index_of_case) +{ + rtc_leap_year_support = RTC_FULL_LEAP_YEAR_SUPPORT; + + return greentea_case_setup_handler(source, index_of_case); +} + +utest::v1::status_t partial_leap_year_case_setup_handler_t(const Case * const source, const size_t index_of_case) +{ + rtc_leap_year_support = RTC_4_YEAR_LEAP_YEAR_SUPPORT; + + return greentea_case_setup_handler(source, index_of_case); } Case cases[] = { - Case("test is leap year", test_is_leap_year, greentea_failure_handler), - Case("test mk time out of range values", test_mk_time_out_of_range, greentea_failure_handler), - Case("mk time", test_mk_time, greentea_failure_handler), - Case("test local time", test_local_time, greentea_failure_handler), - Case("test local time limits", test_local_time_limit, greentea_failure_handler), + Case("test is leap year - RTC leap years full support", full_leap_year_case_setup_handler_t, test_is_leap_year, teardown_handler_t), + Case("test is leap year - RTC leap years partial support", partial_leap_year_case_setup_handler_t, test_is_leap_year, teardown_handler_t), + Case("test make time boundary values - RTC leap years full support", full_leap_year_case_setup_handler_t, test_mk_time_boundary, teardown_handler_t), + Case("test make time boundary values - RTC leap years partial support", partial_leap_year_case_setup_handler_t, test_mk_time_boundary, teardown_handler_t), + Case("test make time - invalid param", test_mk_time_invalid_param, teardown_handler_t), + Case("test local time - invalid param", test_local_time_invalid_param, teardown_handler_t), }; -utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(1200, "default_auto"); +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(20, "default_auto"); return greentea_test_setup_handler(number_of_cases); } Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); -int main() { +int main() +{ return Harness::run(specification); } diff --git a/TESTS/mbed_hal/rtc_time_conv/main.cpp b/TESTS/mbed_hal/rtc_time_conv/main.cpp new file mode 100644 index 00000000000..a33b363492d --- /dev/null +++ b/TESTS/mbed_hal/rtc_time_conv/main.cpp @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This is the mbed device part of the test to verify if: + * - _rtc_maketime() function converts a calendar time into time since UNIX epoch as a time_t, + * - _rtc_localtime() function converts a given time in seconds since epoch into calendar time. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "utest/utest.h" +#include "unity/unity.h" +#include "mbed_mktime.h" + +#define LAST_VALID_YEAR 206 + +using namespace utest::v1; + +static rtc_leap_year_support_t rtc_leap_year_support; + +/* + * regular is_leap_year, see platform/mbed_mktime.c for the optimised version + */ +bool is_leap_year(int year) +{ + year = 1900 + year; + if (year % 4) { + return false; + } else if (year % 100) { + return true; + } else if (year % 400) { + return false; + } + return true; +} + +struct tm make_time_info(int year, int month, int day, int hours, int minutes, int seconds) +{ + struct tm timeinfo = + { seconds, // tm_sec + minutes, // tm_min + hours, // tm_hour + day, // tm_mday + month, // tm_mon + year, // tm_year + 0, // tm_wday + 0, // tm_yday + 0, // tm_isdst + }; + return timeinfo; +} + +/* Test _rtc_maketime() and _rtc_localtime() across wide range + * + * Note: This test functions handles both types of RTC devices: + * - devices which supports full leap years support in range 1970 - 2106. + * - devices which supports parial leap years support and incorrectly treats 2100 year as a leap year. + * + * Given is valid calendar time. + * When _rtc_maketime() is used to generate timestamp from calendar time and _rtc_localtime() is used to convert + * timestamp to calendar time. + * Then both operations gives valid results. + */ +void test_case_mktime_localtime() +{ + char _key[11] = + { }; + char _value[128] = + { }; + + size_t years[] = {70, 71, 100, 196, 200, 205}; + + /* Inform host part of the test about tested RTC type. */ + greentea_send_kv("leap_year_setup", rtc_leap_year_support); + + /* Check the first and last last day of each month. */ + for (size_t year_id = 0; year_id < (sizeof(years) /sizeof(size_t)) ; ++year_id) { + for (size_t month = 0; month < 12; ++month) { + for (size_t dayid = 0; dayid < 2; ++dayid) { + + size_t year = years[year_id]; + + size_t day = 0; + /* Test the first and the last day of each month: + * day 0 - first, + * day 1 - last + * */ + switch (dayid) + { + case 0: + day = 1; + break; + + case 1: + day = 31; + + if (month == 3 || month == 5 || month == 8 || month == 10) { + day = 30; + } + + if (month == 1) { + day = 28; + } + + if (month == 1 && is_leap_year(year)) { + day = 29; + } + + /* Additional conditions for RTCs with partial leap year support. */ + if(month == 1 && year == 200 && rtc_leap_year_support == RTC_4_YEAR_LEAP_YEAR_SUPPORT) { + day = 29; + } + + break; + + default: + break; + } + + tm time_info = make_time_info(year, month, day, 23, dayid ? 59 : 0, dayid ? 59 : 0); + + time_t actual_timestamp; + + TEST_ASSERT_TRUE(_rtc_maketime(&time_info, &actual_timestamp, rtc_leap_year_support)); + + greentea_send_kv("timestamp", (int) actual_timestamp); + + greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + + TEST_ASSERT_EQUAL_STRING("passed", _key); + + /* Response which indicates success contains encoded week day + * and year day needed to verify _rtc_localtime(). + * Use validated timestamp to generate and validate calendar time. + */ + + unsigned int buf = (unsigned int) strtol(_value, NULL, 10); + + time_info.tm_wday = ((buf >> 16) & 0x0000FFFF); + time_info.tm_yday = (buf & 0x0000FFFF); + + tm actual_time_info; + + bool result = _rtc_localtime((time_t) actual_timestamp, &actual_time_info, rtc_leap_year_support); + + TEST_ASSERT_TRUE(result); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_sec, actual_time_info.tm_sec, "invalid seconds"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_min, actual_time_info.tm_min, "invalid minutes"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_hour, actual_time_info.tm_hour, "invalid hours"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_mday, actual_time_info.tm_mday, "invalid day"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_mon, actual_time_info.tm_mon, "invalid month"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_year, actual_time_info.tm_year, "invalid year"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_wday, actual_time_info.tm_wday, "invalid weekday"); + TEST_ASSERT_EQUAL_UINT32_MESSAGE(time_info.tm_yday, actual_time_info.tm_yday, "invalid year day"); + } + } + } +} + +utest::v1::status_t full_leap_year_case_setup_handler_t(const Case * const source, const size_t index_of_case) +{ + rtc_leap_year_support = RTC_FULL_LEAP_YEAR_SUPPORT; + + return greentea_case_setup_handler(source, index_of_case); +} + +utest::v1::status_t partial_leap_year_case_setup_handler_t(const Case * const source, const size_t index_of_case) +{ + rtc_leap_year_support = RTC_4_YEAR_LEAP_YEAR_SUPPORT; + + return greentea_case_setup_handler(source, index_of_case); +} + +utest::v1::status_t teardown_handler_t(const Case * const source, const size_t passed, const size_t failed, + const failure_t reason) +{ + return greentea_case_teardown_handler(source, passed, failed, reason); +} + +// Test cases +Case cases[] ={ + Case("test make time and local time - RTC leap years full support", full_leap_year_case_setup_handler_t, test_case_mktime_localtime, teardown_handler_t), + Case("test make time and local time - RTC leap years partial support", partial_leap_year_case_setup_handler_t, test_case_mktime_localtime, teardown_handler_t), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(300, "rtc_calc_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() +{ + Harness::run(specification); +} diff --git a/TESTS/mbed_platform/SingletonPtr/main.cpp b/TESTS/mbed_platform/SingletonPtr/main.cpp new file mode 100644 index 00000000000..80813ebc9a4 --- /dev/null +++ b/TESTS/mbed_platform/SingletonPtr/main.cpp @@ -0,0 +1,101 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "utest/utest.h" +#include "unity/unity.h" + +using utest::v1::Case; + + +class InstanceTest { +public: + InstanceTest() + { + _instance_counter++; + } + + static int get_instance_counter() + { + return _instance_counter; + } + +private: + static int _instance_counter; +}; + +int InstanceTest::_instance_counter = 0; + + +SingletonPtr singleton; + + +/** Test SingletonPtr lazy initialization + * + * Given a global singleton of type SingletonPtr + * When before first singleton use + * Then underneath object is yet not created + */ +void test_lazy_initialization() +{ + TEST_ASSERT_MESSAGE(InstanceTest::get_instance_counter() == 0, "Initialized before first use!!!"); +} + +/** Test SingletonPtr single instance + * + * Given a singleton of type SingletonPtr + * + * When after first singleton use + * Then underneath object was created exactly once + * + * When after second singleton use + * Then underneath object was created exactly once + * and both (ref1 and ref2) are references to same instance + * + */ +void test_single_instance() +{ + InstanceTest *ref1 = singleton.get(); + TEST_ASSERT_NOT_NULL(ref1); + + TEST_ASSERT_EQUAL_INT(1, InstanceTest::get_instance_counter()); + + InstanceTest *ref2 = singleton.get(); + TEST_ASSERT_NOT_NULL(ref2); + + TEST_ASSERT_EQUAL_INT(1, InstanceTest::get_instance_counter()); + + // same instance + TEST_ASSERT_EQUAL_PTR(ref1, ref2); +} + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(10, "default_auto"); + return utest::v1::verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Test lazy initialization", test_lazy_initialization), + Case("Test single instance", test_single_instance), +}; + +utest::v1::Specification specification(test_setup, cases); + +int main() +{ + return !utest::v1::Harness::run(specification); +} diff --git a/TESTS/mbedmicro-rtos-mbed/CircularBuffer/main.cpp b/TESTS/mbedmicro-rtos-mbed/CircularBuffer/main.cpp new file mode 100644 index 00000000000..2191ee91b75 --- /dev/null +++ b/TESTS/mbedmicro-rtos-mbed/CircularBuffer/main.cpp @@ -0,0 +1,469 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "utest/utest.h" +#include "unity/unity.h" +#include "greentea-client/test_env.h" + +#include "mbed.h" + +using namespace utest::v1; + +/* Structure for complex type. */ +typedef struct +{ + int a; + char b; + int c; +} COMPLEX_TYPE; + +/* Function to check if complex type object holds specified values.*/ +bool comp_is_equal(COMPLEX_TYPE *object, int a, char b, int c) +{ + if (object->a == a && object->b == b && object->c == c) { + return true; + } + + return false; +} + +/* Function to set complex type object fields.*/ +void comp_set(COMPLEX_TYPE *object, int a, char b, int c) +{ + object->a = a; + object->b = b; + object->c = c; +} + +/* Test circular buffer - input does not exceed capacity. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When circular buffer is filled with N elements. + * Then all elements are read from the circular buffer in the FIFO order. + * + */ +template +void test_input_does_not_exceed_capacity_push_max_pop_max() +{ + CircularBuffer cb; + T data = 0; + + for (uint32_t i = 0; i < BufferSize; i++) { + data = (0xAA + i); + cb.push(data); + TEST_ASSERT_EQUAL(i + 1, cb.size()); + } + + for (uint32_t i = 0; i < BufferSize; i++) { + TEST_ASSERT_TRUE(cb.pop(data)); + TEST_ASSERT_EQUAL(0xAA + i, data); + TEST_ASSERT_EQUAL(BufferSize - i - 1, cb.size()); + } +} + +/* Test circular buffer - input does not exceed capacity. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When circular buffer is filled as follows: (2 * N - 2) times 2 elements are pushed and 1 element is popped. + * Then all elements are read from the circular buffer in the FIFO order. + * + */ +template +void test_input_does_not_exceed_capacity_push_2_pop_1() +{ + CircularBuffer cb; + static const int num_of_elem_push = (2 * BufferSize - 2); + T push_buffer = 0; + T pop_buffer = 0; + + /* Push 2 elements and pop one element in each cycle. */ + for (uint32_t i = 0; i < num_of_elem_push; i += 2) { + push_buffer = (0xAA + i); + cb.push(push_buffer); + push_buffer++; + cb.push(push_buffer); + TEST_ASSERT_EQUAL(i / 2 + 2, cb.size()); + + TEST_ASSERT_TRUE(cb.pop(pop_buffer)); + TEST_ASSERT_EQUAL(0xAA + i / 2, pop_buffer); + TEST_ASSERT_EQUAL(i / 2 + 1, cb.size()); + } + + /* Pop the rest. */ + for (uint32_t i = 0; i < (num_of_elem_push / 2); i++) { + TEST_ASSERT_TRUE(cb.pop(pop_buffer)); + TEST_ASSERT_EQUAL(0xAA + num_of_elem_push / 2 + i, pop_buffer); + TEST_ASSERT_EQUAL(num_of_elem_push / 2 - 1 - i, cb.size()); + + } +} + +/* Test circular buffer - input exceeds capacity. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When circular buffer is filled with N + 1 elements. + * Then first pushed element is lost (overwritten by the last element) and + * elements are read from the circular buffer in the FIFO order. + * + */ +template +void test_input_exceeds_capacity_push_max_plus_1_pop_max() +{ + CircularBuffer cb; + static const int num_of_elem_push = (BufferSize + 1); + T data = 0; + + for (uint32_t i = 0; i < num_of_elem_push; i++) { + data = (0xAA + i); + cb.push(data); + if (i < BufferSize) { + TEST_ASSERT_EQUAL(i + 1, cb.size()); + } else { + TEST_ASSERT_EQUAL(BufferSize, cb.size()); + } + + } + + for (uint32_t i = 0; i < (BufferSize - 1); i++) { + TEST_ASSERT_TRUE(cb.pop(data)); + TEST_ASSERT_EQUAL(0xAA + i + 1, data); + TEST_ASSERT_EQUAL(BufferSize - 1 - i, cb.size()); + } + + /* First element should be overwritten. */ + TEST_ASSERT_TRUE(cb.pop(data)); + TEST_ASSERT_EQUAL((0xAA + num_of_elem_push - 1), data); + TEST_ASSERT_EQUAL(0, cb.size()); +} + +/* Test circular buffer - input exceeds capacity. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When circular buffer is filled as follows: (2 * N) times 2 elements are pushed and 1 element is popped. + * Then first pushed element is lost (overwritten by the last element) and + * elements are read from the circular buffer in the FIFO order. + * + */ +template +void test_input_exceeds_capacity_push_2_pop_1() +{ + CircularBuffer cb; + static const int num_of_elem_push = (2 * BufferSize); + T push_buffer = 0; + T pop_buffer = 0; + + /* Push 2 elements and pop one element in each cycle. */ + for (uint32_t i = 0; i < num_of_elem_push; i += 2) { + push_buffer = (0xAA + i); + cb.push(push_buffer); + push_buffer++; + cb.push(push_buffer); + if ((i / 2 + 1) < BufferSize) { + TEST_ASSERT_EQUAL(i / 2 + 2, cb.size()); + } else { + TEST_ASSERT_EQUAL(BufferSize, cb.size()); + } + + TEST_ASSERT_TRUE(cb.pop(pop_buffer)); + if ((i / 2 + 1) < BufferSize) { + TEST_ASSERT_EQUAL(i / 2 + 1, cb.size()); + } else { + TEST_ASSERT_EQUAL(BufferSize - 1, cb.size()); + } + + /* First element has been overwritten. */ + if (i == (num_of_elem_push - 2)) { + TEST_ASSERT_EQUAL(0xAA + i / 2 + 1, pop_buffer); + } else { + TEST_ASSERT_EQUAL(0xAA + i / 2, pop_buffer); + } + } + + /* Pop the rest - one element has been overwritten. */ + for (uint32_t i = 0; i < (num_of_elem_push / 2 - 1); i++) { + TEST_ASSERT_TRUE(cb.pop(pop_buffer)); + TEST_ASSERT_EQUAL(0xAA + num_of_elem_push / 2 + i + 1, pop_buffer); + } +} + +/* Test circular buffer - input exceeds capacity (complex type). + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When circular buffer is filled as follows: (2 * N) times 2 elements are pushed and 1 element is popped. + * Then first pushed element is lost (overwritten by the last element) and + * elements are read from the circular buffer in the FIFO order. + * + */ +template +void test_input_exceeds_capacity_push_2_pop_1_complex_type() +{ + CircularBuffer cb; + static const int num_of_elem_push = (2 * BufferSize); + COMPLEX_TYPE push_buffer = {0}; + COMPLEX_TYPE pop_buffer = {0}; + + /* Push 2 elements and pop one element in each cycle. */ + for (uint32_t i = 0; i < num_of_elem_push; i += 2) { + comp_set(&push_buffer, 0xAA + i, 0xBB + i, 0xCC + i); + cb.push(push_buffer); + comp_set(&push_buffer, 0xAA + i + 1, 0xBB + i + 1, 0xCC + i + 1); + cb.push(push_buffer); + if ((i / 2 + 1) < BufferSize) { + TEST_ASSERT_EQUAL(i / 2 + 2, cb.size()); + } else { + TEST_ASSERT_EQUAL(BufferSize, cb.size()); + } + + TEST_ASSERT_TRUE(cb.pop(pop_buffer)); + if ((i / 2 + 1) < BufferSize) { + TEST_ASSERT_EQUAL(i / 2 + 1, cb.size()); + } else { + TEST_ASSERT_EQUAL(BufferSize - 1, cb.size()); + } + + /* First element has been overwritten. */ + if (i == (num_of_elem_push - 2)) { + const bool result = comp_is_equal(&pop_buffer, 0xAA + 1 + i / 2, 0xBB + 1 + i / 2, 0xCC + 1 + i / 2); + TEST_ASSERT_TRUE(result); + } else { + const bool result = comp_is_equal(&pop_buffer, 0xAA + i / 2, 0xBB + i / 2, 0xCC + i / 2); + TEST_ASSERT_TRUE(result); + } + } + + /* Pop the rest - one element has been overwritten. */ + for (uint32_t i = 0; i < (num_of_elem_push / 2 - 1); i++) { + TEST_ASSERT_TRUE(cb.pop(pop_buffer)); + const bool result = comp_is_equal(&pop_buffer, 0xAA + num_of_elem_push / 2 + i + 1, + 0xBB + num_of_elem_push / 2 + i + 1, 0xCC + num_of_elem_push / 2 + i + 1); + TEST_ASSERT_TRUE(result); + } +} + +/* Test circular buffer - test pop(), empty(), full(), size() after CircularBuffer creation. + * + * Given is a circular buffer. + * When circular buffer is created. + * Then circular buffer is empty: + * - empty() returns true, + * - pop() function returns false, + * - full() function returns false, + * - size() function returns 0, + * + */ +void test_pop_empty_full_size_after_creation() +{ + CircularBuffer cb; + int data = 0; + + TEST_ASSERT_TRUE(cb.empty()); + TEST_ASSERT_FALSE(cb.pop(data)); + TEST_ASSERT_FALSE(cb.full()); + TEST_ASSERT_EQUAL(0, cb.size()); +} + +/* Test circular buffer - test empty() function. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When operations on circular buffer are performed (push, pop). + * Then empty() function returns true if buffer is empty, false otherwise. + * + */ +template +void test_empty() +{ + CircularBuffer cb; + T data = 0; + + /* Push max elements. */ + for (uint32_t i = 0; i < BufferSize; i++) { + cb.push(data); + TEST_ASSERT_FALSE(cb.empty()); + } + + /* Push next 2*BufferSize elements (overwrite entries). */ + for (uint32_t i = 0; i < (2 * BufferSize); i++) { + cb.push(data); + TEST_ASSERT_FALSE(cb.empty()); + } + + /* Pop (BufferSize - 1) elements (leave one). */ + for (uint32_t i = 0; i < (BufferSize - 1); i++) { + TEST_ASSERT_TRUE(cb.pop(data)); + TEST_ASSERT_FALSE(cb.empty()); + } + + /* Take one which is left. */ + TEST_ASSERT_TRUE(cb.pop(data)); + TEST_ASSERT_TRUE(cb.empty()); + + /* Add one element to the empty buffer. */ + cb.push(data); + TEST_ASSERT_FALSE(cb.empty()); +} + +/* Test circular buffer - test full() function. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When operations on circular buffer are performed (push, pop). + * Then full() function returns true if buffer is full, false otherwise. + * + */ +template +void test_full() +{ + CircularBuffer cb; + T data = 0; + + /* Push max elements - 1. */ + for (uint32_t i = 0; i < (BufferSize - 1); i++) { + cb.push(data); + TEST_ASSERT_FALSE(cb.full()); + } + + /* Push one element - buffer should be full now. */ + cb.push(data); + TEST_ASSERT_TRUE(cb.full()); + + /* Push next 2*BufferSize elements (overwrite entries). */ + for (uint32_t i = 0; i < (2 * BufferSize); i++) { + cb.push(data); + TEST_ASSERT_TRUE(cb.full()); + } + + /* Pop all elements. */ + for (uint32_t i = 0; i < BufferSize; i++) { + TEST_ASSERT_TRUE(cb.pop(data)); + TEST_ASSERT_FALSE(cb.full()); + } +} + +/* Test circular buffer - test reset() function. + * + * Given is a circular buffer with the capacity equal to N (BufferSize). + * When reset operation is performed on circular buffer. + * Then circular buffer is cleared. + * + */ +template +void test_reset() +{ + CircularBuffer cb; + T data = 0xAA; + + /* Push max elements. */ + for (uint32_t i = 0; i < BufferSize; i++) { + cb.push(data); + } + + TEST_ASSERT_TRUE(cb.full()); + TEST_ASSERT_FALSE(cb.empty()); + TEST_ASSERT_EQUAL(BufferSize, cb.size()); + + cb.reset(); + + TEST_ASSERT_FALSE(cb.full()); + TEST_ASSERT_TRUE(cb.empty()); + TEST_ASSERT_FALSE(cb.pop(data)); + TEST_ASSERT_EQUAL(0, cb.size()); + + /* Check if after reset push and pop operations work. */ + for (uint32_t i = 0; i < BufferSize; i++) { + cb.push(data); + data++; + } + + for (uint32_t i = 0; i < BufferSize; i++) { + cb.pop(data); + TEST_ASSERT_EQUAL(0xAA + i, data); + } +} + +/* Test circular buffer - creation of circular buffer with max buffer size consistent with counter type. + * + * Given is a circular buffer. + * When circular buffer is created with buffer size equal to 255 and counter type equal to unsigned char. + * Then circular buffer is successfully created. + * + */ +void test_counter_type_buffer_size() +{ + CircularBuffer cb; + int data = 100; + + /* Perform some operations. */ + cb.push(data); + data = 0; + cb.pop(data); + TEST_ASSERT_EQUAL(100, data); +} + +utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) +{ + greentea_case_failure_abort_handler(source, reason); + return STATUS_CONTINUE; +} + +Case cases[] = { + Case("Input does not exceed capacity(1) push max, pop max.", + test_input_does_not_exceed_capacity_push_max_pop_max, greentea_failure_handler), + Case("Input does not exceed capacity(3) push max, pop max.", + test_input_does_not_exceed_capacity_push_max_pop_max, greentea_failure_handler), + + Case("Input does not exceed capacity(5) push 2, pop 1.", + test_input_does_not_exceed_capacity_push_2_pop_1, greentea_failure_handler), + Case("Input does not exceed capacity(10) push 2, pop 1.", + test_input_does_not_exceed_capacity_push_2_pop_1, greentea_failure_handler), + + Case("Input exceeds capacity(1) push max+1, pop max.", + test_input_exceeds_capacity_push_max_plus_1_pop_max, greentea_failure_handler), + Case("Input exceeds capacity(3) push max+1, pop max.", + test_input_exceeds_capacity_push_max_plus_1_pop_max, greentea_failure_handler), + + Case("Input exceeds capacity(5) push 2, pop 1.", + test_input_exceeds_capacity_push_2_pop_1, greentea_failure_handler), + Case("Input exceeds capacity(10) push 2, pop 1.", + test_input_exceeds_capacity_push_2_pop_1, greentea_failure_handler), + + Case("empty() returns true when buffer(3 elements) is empty.", test_empty, greentea_failure_handler), + Case("empty() returns true when buffer(5 elements) is empty.", test_empty, greentea_failure_handler), + + Case("full() returns true when buffer(3 elements) is full.", test_full, greentea_failure_handler), + Case("full() returns true when buffer(5 elements) is full.", test_full, greentea_failure_handler), + + Case("reset() clears the buffer.", test_reset, greentea_failure_handler), + + Case("Test pop(), empty(), full(), size() after CircularBuffer creation.", + test_pop_empty_full_size_after_creation, greentea_failure_handler), + + Case("Test CounterType/BufferSize boarder case.", test_counter_type_buffer_size, greentea_failure_handler), + + Case("Input exceeds capacity(5) push 2, pop 1 - complex type.", + test_input_exceeds_capacity_push_2_pop_1_complex_type<5, unsigned short>, greentea_failure_handler), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(15, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() +{ + return Harness::run(specification); +} diff --git a/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp index b2e253a13f8..b5b6b4cbf90 100644 --- a/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp @@ -16,7 +16,7 @@ */ #if defined(TARGET_CORTEX_A) -　 #error [NOT_SUPPORTED] This function not supported for this target + #error [NOT_SUPPORTED] This function not supported for this target #endif #include diff --git a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp index 2b685783117..6655bc33b73 100644 --- a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp @@ -32,7 +32,7 @@ volatile bool thread_should_continue = true; #define THREAD_MALLOC_SIZE 100 #if defined(__CORTEX_A9) -#define THREAD_STACK_SIZE DEFAULT_STACK_SIZE +#define THREAD_STACK_SIZE 512 #else #define THREAD_STACK_SIZE 256 #endif diff --git a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp index 8940024eb54..7ebf09e795e 100644 --- a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp @@ -26,7 +26,11 @@ #endif #define THREAD_STACK_SIZE 512 +#if defined(__CORTEX_A9) +#define PARALLEL_THREAD_STACK_SIZE 512 +#else #define PARALLEL_THREAD_STACK_SIZE 384 +#endif #define CHILD_THREAD_STACK_SIZE 384 using namespace utest::v1; diff --git a/TESTS/netsocket/gethostbyname/main.cpp b/TESTS/netsocket/gethostbyname/main.cpp index 23eabc9be33..58a4e47470c 100644 --- a/TESTS/netsocket/gethostbyname/main.cpp +++ b/TESTS/netsocket/gethostbyname/main.cpp @@ -29,8 +29,8 @@ using namespace utest::v1; // Hostname for testing against // Must have A and AAAA records -#ifndef MBED_DNS_TEST_HOST -#define MBED_DNS_TEST_HOST "connector.mbed.com" +#ifndef MBED_CONF_APP_DNS_TEST_HOST +#define MBED_CONF_APP_DNS_TEST_HOST "connector.mbed.com" #endif @@ -59,9 +59,9 @@ void net_bringup() { // DNS tests void test_dns_query() { SocketAddress addr; - int err = net->gethostbyname(MBED_DNS_TEST_HOST, &addr); + int err = net->gethostbyname(MBED_CONF_APP_DNS_TEST_HOST, &addr); printf("DNS: query \"%s\" => \"%s\"\n", - MBED_DNS_TEST_HOST, addr.get_ip_address()); + MBED_CONF_APP_DNS_TEST_HOST, addr.get_ip_address()); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT((bool)addr); @@ -70,9 +70,9 @@ void test_dns_query() { void test_dns_query_pref() { SocketAddress addr; - int err = net->gethostbyname(MBED_DNS_TEST_HOST, &addr, ip_pref); + int err = net->gethostbyname(MBED_CONF_APP_DNS_TEST_HOST, &addr, ip_pref); printf("DNS: query %s \"%s\" => \"%s\"\n", - ip_pref_repr, MBED_DNS_TEST_HOST, addr.get_ip_address()); + ip_pref_repr, MBED_CONF_APP_DNS_TEST_HOST, addr.get_ip_address()); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT((bool)addr); diff --git a/TESTS/netsocket/socket_sigio/main.cpp b/TESTS/netsocket/socket_sigio/main.cpp index 6c357abd4a6..e0949f7e37b 100644 --- a/TESTS/netsocket/socket_sigio/main.cpp +++ b/TESTS/netsocket/socket_sigio/main.cpp @@ -29,11 +29,13 @@ using namespace utest::v1; +#ifndef MBED_CONF_APP_HTTP_SERVER_NAME +#define MBED_CONF_APP_HTTP_SERVER_NAME "os.mbed.com" +#define MBED_CONF_APP_HTTP_SERVER_FILE_PATH "/media/uploads/mbed_official/hello.txt" +#endif namespace { // Test connection information - const char *HTTP_SERVER_NAME = "os.mbed.com"; - const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt"; const int HTTP_SERVER_PORT = 80; #if defined(TARGET_VK_RZ_A1H) const int RECV_BUFFER_SIZE = 300; @@ -97,12 +99,14 @@ void prep_buffer() { // We are constructing GET command like this: // GET http://developer.mbed.org/media/uploads/mbed_official/hello.txt HTTP/1.0\n\n strcpy(buffer, "GET http://"); - strcat(buffer, HTTP_SERVER_NAME); - strcat(buffer, HTTP_SERVER_FILE_PATH); + strcat(buffer, MBED_CONF_APP_HTTP_SERVER_NAME); + strcat(buffer, MBED_CONF_APP_HTTP_SERVER_FILE_PATH); strcat(buffer, " HTTP/1.0\n\n"); } void test_socket_attach() { + bool result = false; + // Dispatch event queue Thread eventThread; EventQueue queue(4*EVENTS_EVENT_SIZE); @@ -111,8 +115,8 @@ void test_socket_attach() { printf("TCP client IP Address is %s\r\n", net->get_ip_address()); TCPSocket sock(net); - printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT); - if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { + printf("HTTP: Connection to %s:%d\r\n", MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT); + if (sock.connect(MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { printf("HTTP: OK\r\n"); prep_buffer(); @@ -122,10 +126,13 @@ void test_socket_attach() { sock.send(buffer, strlen(buffer)); // wait for recv data recvd.wait(); + + result = true; } else { printf("HTTP: ERROR\r\n"); } sock.close(); + TEST_ASSERT_EQUAL(true, result); } void cb_fail() { @@ -145,8 +152,8 @@ void test_socket_detach() { printf("TCP client IP Address is %s\r\n", net->get_ip_address()); TCPSocket sock(net); - printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT); - if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { + printf("HTTP: Connection to %s:%d\r\n", MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT); + if (sock.connect(MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { printf("HTTP: OK\r\n"); prep_buffer(); @@ -172,8 +179,8 @@ void test_socket_reattach() { printf("TCP client IP Address is %s\r\n", net->get_ip_address()); TCPSocket sock(net); - printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT); - if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { + printf("HTTP: Connection to %s:%d\r\n", MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT); + if (sock.connect(MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { printf("HTTP: OK\r\n"); prep_buffer(); diff --git a/TESTS/netsocket/tcp_echo/main.cpp b/TESTS/netsocket/tcp_echo/main.cpp index 90124a28711..13776ebc10c 100644 --- a/TESTS/netsocket/tcp_echo/main.cpp +++ b/TESTS/netsocket/tcp_echo/main.cpp @@ -15,9 +15,9 @@ * limitations under the License. */ - #ifndef MBED_CONF_APP_CONNECT_STATEMENT - #error [NOT_SUPPORTED] No network configuration found for this target. - #endif +#ifndef MBED_CONF_APP_CONNECT_STATEMENT + #error [NOT_SUPPORTED] No network configuration found for this target. +#endif #include "mbed.h" #include MBED_CONF_APP_HEADER_FILE @@ -28,14 +28,13 @@ using namespace utest::v1; -#ifndef MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE -#define MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE 256 +#ifndef MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE +#define MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE 256 #endif namespace { - char tx_buffer[MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; - char rx_buffer[MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; - const char ASCII_MAX = '~' - ' '; + char tx_buffer[MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; + char rx_buffer[MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; } void prep_buffer(char *tx_buffer, size_t tx_size) { @@ -45,7 +44,7 @@ void prep_buffer(char *tx_buffer, size_t tx_size) { } void test_tcp_echo() { - + int n = 0; NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION; int err = MBED_CONF_APP_CONNECT_STATEMENT; @@ -60,15 +59,40 @@ void test_tcp_echo() { TCPSocket sock(net); +#if defined(MBED_CONF_APP_ECHO_SERVER_ADDR) && defined(MBED_CONF_APP_ECHO_SERVER_PORT) + printf("TCP: Connect to %s:%d\r\n", MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT); SocketAddress tcp_addr(MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT); +#else /* MBED_CONF_APP_ECHO_SERVER_ADDR && MBED_CONF_APP_ECHO_SERVER_PORT */ + char recv_key[] = "host_port"; + char ipbuf[60] = {0}; + char portbuf[16] = {0}; + unsigned int port = 0; + + greentea_send_kv("target_ip", net->get_ip_address()); + greentea_send_kv("host_ip", " "); + greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf)); + + greentea_send_kv("host_port", " "); + greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf)); + sscanf(portbuf, "%u", &port); + + printf("TCP: Connect to %s:%d\r\n", ipbuf, port); + SocketAddress tcp_addr(ipbuf, port); +#endif /* MBED_CONF_APP_ECHO_SERVER_ADDR && MBED_CONF_APP_ECHO_SERVER_PORT */ if (sock.connect(tcp_addr) == 0) { - printf("HTTP: Connected to %s:%d\r\n", MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT); printf("tx_buffer buffer size: %u\r\n", sizeof(tx_buffer)); printf("rx_buffer buffer size: %u\r\n", sizeof(rx_buffer)); prep_buffer(tx_buffer, sizeof(tx_buffer)); - sock.recv(rx_buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX)); +#if defined(MBED_CONF_APP_TCP_ECHO_PREFIX) + n = sock.recv(rx_buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX)); + if (n >= 0) { + printf("recv-ed prefix: %d bytes - %.*s \n", n, n, rx_buffer); + } else { + printf("Network error in receiving prefix: %d\n", n); + } +#endif /* MBED_CONF_APP_TCP_ECHO_PREFIX */ const int ret = sock.send(tx_buffer, sizeof(tx_buffer)); if (ret >= 0) { printf("sent %d bytes - %.*s \n", ret, ret, tx_buffer); @@ -76,7 +100,7 @@ void test_tcp_echo() { printf("Network error %d\n", ret); } - int n = sock.recv(rx_buffer, sizeof(rx_buffer)); + n = sock.recv(rx_buffer, sizeof(rx_buffer)); if (n >= 0) { printf("recv %d bytes - %.*s \n", n, n, rx_buffer); } else { @@ -96,16 +120,7 @@ void test_tcp_echo() { // Test setup utest::v1::status_t test_setup(const size_t number_of_cases) { - char uuid[48] = {0}; GREENTEA_SETUP(240, "tcp_echo"); - - // create mac address based on uuid - uint64_t mac = 0; - for (int i = 0; i < sizeof(uuid); i++) { - mac += uuid[i]; - } - //mbed_set_mac_address((const char*)mac, /*coerce control bits*/ 1); - return verbose_test_setup_handler(number_of_cases); } diff --git a/TESTS/netsocket/tcp_hello_world/main.cpp b/TESTS/netsocket/tcp_hello_world/main.cpp index 9e42e21c046..b6e36dd5385 100644 --- a/TESTS/netsocket/tcp_hello_world/main.cpp +++ b/TESTS/netsocket/tcp_hello_world/main.cpp @@ -29,11 +29,13 @@ using namespace utest::v1; +#ifndef MBED_CONF_APP_HTTP_SERVER_NAME +#define MBED_CONF_APP_HTTP_SERVER_NAME "os.mbed.com" +#define MBED_CONF_APP_HTTP_SERVER_FILE_PATH "/media/uploads/mbed_official/hello.txt" +#endif namespace { // Test connection information - const char *HTTP_SERVER_NAME = "os.mbed.com"; - const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt"; const int HTTP_SERVER_PORT = 80; #if defined(TARGET_VK_RZ_A1H) const int RECV_BUFFER_SIZE = 300; @@ -60,23 +62,29 @@ void test_tcp_hello_world() { printf("TCP client IP Address is %s\r\n", net->get_ip_address()); TCPSocket sock(net); - printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT); - if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { + printf("HTTP: Connection to %s:%d\r\n", MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT); + if (sock.connect(MBED_CONF_APP_HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) { printf("HTTP: OK\r\n"); // We are constructing GET command like this: // GET http://developer.mbed.org/media/uploads/mbed_official/hello.txt HTTP/1.0\n\n strcpy(buffer, "GET http://"); - strcat(buffer, HTTP_SERVER_NAME); - strcat(buffer, HTTP_SERVER_FILE_PATH); + strcat(buffer, MBED_CONF_APP_HTTP_SERVER_NAME); + strcat(buffer, MBED_CONF_APP_HTTP_SERVER_FILE_PATH); strcat(buffer, " HTTP/1.0\n\n"); // Send GET command sock.send(buffer, strlen(buffer)); // Server will respond with HTTP GET's success code - const int ret = sock.recv(buffer, sizeof(buffer) - 1); - buffer[ret] = '\0'; + int ret = 0; + int bytes_recvd = 0; + do { + ret += bytes_recvd; + bytes_recvd = sock.recv(buffer+ret, sizeof(buffer) - 1 - ret); + }while(bytes_recvd > 0); + buffer[ret] = '\0'; + // Find 200 OK HTTP status in reply bool found_200_ok = find_substring(buffer, buffer + ret, HTTP_OK_STR, HTTP_OK_STR + strlen(HTTP_OK_STR)); // Find "Hello World!" string in reply diff --git a/TESTS/netsocket/udp_echo/main.cpp b/TESTS/netsocket/udp_echo/main.cpp index a5ab9bef4df..3989bb74d6f 100644 --- a/TESTS/netsocket/udp_echo/main.cpp +++ b/TESTS/netsocket/udp_echo/main.cpp @@ -40,19 +40,12 @@ using namespace utest::v1; namespace { char tx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE] = {0}; char rx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE] = {0}; - const char ASCII_MAX = '~' - ' '; const int ECHO_LOOPS = 16; - char uuid[48] = {0}; } -void prep_buffer(char *uuid, char *tx_buffer, size_t tx_size) { +void prep_buffer(char *tx_buffer, size_t tx_size) { size_t i = 0; - memcpy(tx_buffer, uuid, strlen(uuid)); - i += strlen(uuid); - - tx_buffer[i++] = ' '; - for (; iget_ip_address()); + greentea_send_kv("host_ip", " "); + greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf)); + + greentea_send_kv("host_port", " "); + greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf)); + sscanf(portbuf, "%u", &port); + + printf("MBED: UDP Server IP address received: %s:%d \n", ipbuf, port); + SocketAddress udp_addr(ipbuf, port); +#endif /* MBED_CONF_APP_ECHO_SERVER_ADDR && MBED_CONF_APP_ECHO_SERVER_PORT */ int success = 0; for (int i = 0; success < ECHO_LOOPS; i++) { - prep_buffer(uuid, tx_buffer, sizeof(tx_buffer)); + prep_buffer(tx_buffer, sizeof(tx_buffer)); const int ret = sock.sendto(udp_addr, tx_buffer, sizeof(tx_buffer)); if (ret >= 0) { printf("[%02d] sent %d bytes - %.*s \n", i, ret, ret, tx_buffer); @@ -127,14 +138,6 @@ void test_udp_echo() { // Test setup utest::v1::status_t test_setup(const size_t number_of_cases) { GREENTEA_SETUP(240, "udp_echo"); - - // create mac address based on uuid - uint64_t mac = 0; - for (int i = 0; i < sizeof(uuid); i++) { - mac += uuid[i]; - } - //mbed_set_mac_address((const char*)mac, /*coerce control bits*/ 1); - return verbose_test_setup_handler(number_of_cases); } diff --git a/TESTS/network/emac/README.md b/TESTS/network/emac/README.md new file mode 100644 index 00000000000..610f7a7c42f --- /dev/null +++ b/TESTS/network/emac/README.md @@ -0,0 +1,28 @@ +# Description + +This document describes how to run EMAC tests. The EMAC test cases are made using Ethernet Configuration Testing Protocol (CTP). To run the tests, one device in the Ethernet segment needs to be configured to be a CTP echo server. The devices running the test cases, use the echo server to forward the CTP Ethernet frames back. + +# Configuring CTP echo server + +A device can be configured to be a CTP echo server by enabling `echo-server` setting in the test environment's application `json` file. When device is configured to be a CTP echo server, it starts to forward CTP messages automatically after power up and will continue forwarding until power down. + +# Test cases + +## EMAC interface initialise + +Initializes EMAC interface driver. + +For WLAN installs test case so that it can intercept incoming Ethernet messages from the WLAN driver. Incoming CTP frames are handed by the test case and other frames are forwarded to the LWIP stack. + +## EMAC interface broadcast + +Sends three 100 byte CTP broadcast messages, waits for three seconds and sends three 50 byte CTP broadcast messages. Listens for the CTP echo server responses and stores the addresses of the echo servers if replies are received. The test case will pass if there are no responses from echo server, but further test cases will be skipped. + +## EMAC interface unicast + +Sends three CTP unicast messages to the CTP echo server. Verifies that all are replied. + +## EMAC interface unicast frame length + +Sends CTP unicast messages with Ethernet message length from 100 bytes to maximum. Verifies that all are replied. + diff --git a/TESTS/network/emac/emac_ctp.cpp b/TESTS/network/emac/emac_ctp.cpp new file mode 100644 index 00000000000..308f29f988d --- /dev/null +++ b/TESTS/network/emac/emac_ctp.cpp @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "mbed.h" + +#include "lwip/opt.h" /* ETH_PAD_SIZE */ + +#include "emac_stack_mem.h" +#include "emac_api.h" + +#include "emac_tests.h" +#include "emac_ctp.h" + +#include "emac_initialize.h" +#include "emac_util.h" +#include "emac_membuf.h" + +using namespace utest::v1; + +// Unique identifier for message +static int receipt_number = 0; + +static int emac_if_ctp_header_build(unsigned char *eth_frame, const unsigned char *dest_addr, const unsigned char *origin_addr, const unsigned char *forward_addr) +{ + memcpy(ð_frame[0], dest_addr, 6); + memcpy(ð_frame[6], origin_addr, 6); + + eth_frame[12] = 0x90; /* loop back */ + eth_frame[13] = 0x00; + + eth_frame[14] = 0x00; /* skip count */ + eth_frame[15] = 0x00; + + eth_frame[16] = 0x02; /* function, forward */ + eth_frame[17] = 0x00; + + memcpy(ð_frame[18], forward_addr, 6); + + eth_frame[24] = 0x01; /* function, reply */ + eth_frame[25] = 0x00; + + receipt_number++; + + eth_frame[26] = receipt_number; /* receipt number */ + eth_frame[27] = receipt_number >> 8; + + return receipt_number; +} + +ctp_function emac_if_ctp_header_handle(unsigned char *eth_input_frame, unsigned char *eth_output_frame, unsigned char *origin_addr, int *receipt_number) +{ + if (eth_input_frame[12] != 0x90 || eth_input_frame[13] != 0x00) { + return CTP_NONE; + } + + int skip_count = eth_input_frame[15] << 8 | eth_input_frame[14]; + unsigned char *ethernet_ptr = ð_input_frame[16] + skip_count; + + int function = ethernet_ptr[1] << 8 | ethernet_ptr[0]; + ethernet_ptr += 2; + + // Forward + if (function == 0x0002) { + memcpy(eth_output_frame, eth_input_frame, ETH_FRAME_HEADER_LEN); + // Update skip count + skip_count += 8; + eth_output_frame[14] = skip_count; + eth_output_frame[15] = skip_count >> 8; + // Set forward address to destination address + memcpy(ð_output_frame[0], ethernet_ptr, 6); + // Copy own address to origin + memcpy(ð_output_frame[6], origin_addr, 6); + return CTP_FORWARD; + // reply + } else if (function == 0x0001) { + *receipt_number = ethernet_ptr[1] << 8 | ethernet_ptr[0]; + return CTP_REPLY; + } + + return CTP_NONE; +} + +void emac_if_ctp_msg_build(int eth_frame_len, const unsigned char *dest_addr, const unsigned char *origin_addr, const unsigned char *forward_addr) +{ + if (eth_frame_len < ETH_FRAME_HEADER_LEN) { + eth_frame_len = ETH_FRAME_HEADER_LEN; + } + + printf("message sent %x:%x:%x:%x:%x:%x\r\n\r\n", dest_addr[0], dest_addr[1], dest_addr[2], dest_addr[3], dest_addr[4], dest_addr[5]); + + int outgoing_msg_index = emac_if_add_outgoing_msg(eth_frame_len); + + if (outgoing_msg_index < 0) { + SET_ERROR_FLAGS(OUT_OF_MSG_DATA); + return; + } + + emac_stack_mem_chain_t *mem_chain_p = emac_stack_mem_alloc(0, eth_frame_len + ETH_PAD_SIZE, 0); + + if (!mem_chain_p) { + SET_ERROR_FLAGS(NO_FREE_MEM_BUF); + emac_if_free_outgoing_msg(outgoing_msg_index); + return; + } + + if (memcmp(dest_addr, eth_mac_broadcast_addr, 6) == 0) { + emac_if_set_outgoing_msg_flags(outgoing_msg_index, BROADCAST); + } + + unsigned char eth_output_frame_data[ETH_FRAME_HEADER_LEN]; + int receipt_number = emac_if_ctp_header_build(eth_output_frame_data, dest_addr, origin_addr, forward_addr); + emac_if_set_outgoing_msg_receipt_num(outgoing_msg_index, receipt_number); + + emac_if_memory_buffer_write(mem_chain_p, eth_output_frame_data, true); + + //emac_if->ops.link_out(hw_driver, mem_chain_p); + emac_if_get()->ops.link_out(emac_if_get(), mem_chain_p); + + emac_stack_mem_free(0, mem_chain_p); +} + +#endif + diff --git a/TESTS/network/emac/emac_ctp.h b/TESTS/network/emac/emac_ctp.h new file mode 100644 index 00000000000..97c18e6a911 --- /dev/null +++ b/TESTS/network/emac/emac_ctp.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_CTP_H +#define EMAC_CTP_H + +enum ctp_function { + CTP_NONE, + CTP_FORWARD, + CTP_REPLY +}; + +ctp_function emac_if_ctp_header_handle(unsigned char *eth_input_frame, unsigned char *eth_output_frame, unsigned char *origin_addr, int *receipt_number); +void emac_if_ctp_msg_build(int eth_frame_len, const unsigned char *dest_addr, const unsigned char *origin_addr, const unsigned char *forward_addr); +void emac_if_ctp_reply_handle(int lenght, int invalid_data_index); + +#endif /* EMAC_CTP_H */ diff --git a/TESTS/network/emac/emac_initialize.h b/TESTS/network/emac/emac_initialize.h new file mode 100644 index 00000000000..307b7c47f69 --- /dev/null +++ b/TESTS/network/emac/emac_initialize.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_INITIALIZE_H +#define EMAC_INITIALIZE_H + +uint8_t *emac_if_get_hw_addr(void); +emac_interface_t *emac_if_get(void); + +#endif /* EMAC_INITIALIZE_H */ diff --git a/TESTS/network/emac/emac_membuf.cpp b/TESTS/network/emac/emac_membuf.cpp new file mode 100644 index 00000000000..1b5f31d6857 --- /dev/null +++ b/TESTS/network/emac/emac_membuf.cpp @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "lwip/opt.h" /* ETH_PAD_SIZE */ + +#include "emac_api.h" +#include "emac_stack_mem.h" + +#include "emac_membuf.h" +#include "emac_util.h" + +int emac_if_memory_buffer_read(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame) +{ + int eth_frame_index = 0; + int invalid_data_index = 0; + int index = ETH_PAD_SIZE; + + for (emac_stack_mem_t *mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p); mem_p != NULL; mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p)) { + unsigned char *buf_payload = (unsigned char *) emac_stack_mem_ptr(0, mem_p); + int buf_payload_len = emac_stack_mem_len(0, mem_p); + + for (; index < buf_payload_len; index++) { + if (eth_frame_index < ETH_FRAME_HEADER_LEN) { + eth_frame[eth_frame_index] = buf_payload[index]; + } else { + if (buf_payload[index] != (uint8_t) eth_frame_index) { + invalid_data_index = eth_frame_index; + break; + } + } + eth_frame_index++; + } + index = 0; + } + + return invalid_data_index; +} + +void emac_if_memory_buffer_write(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame, bool write_data) +{ + int eth_frame_index = 0; + int index = ETH_PAD_SIZE; + + for (emac_stack_mem_t *mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p); mem_p != NULL; mem_p = emac_stack_mem_chain_dequeue(0, &mem_chain_p)) { + unsigned char *buf_payload = (unsigned char *) emac_stack_mem_ptr(0, mem_p); + int buf_payload_len = emac_stack_mem_len(0, mem_p); + + for (; index < buf_payload_len; index++) { + if (eth_frame_index < ETH_FRAME_HEADER_LEN) { + buf_payload[index] = eth_frame[eth_frame_index]; + } else if (write_data) { + buf_payload[index] = (char) eth_frame_index; + } else { + break; + } + eth_frame_index++; + } + index = 0; + } +} + +#endif diff --git a/TESTS/network/emac/emac_membuf.h b/TESTS/network/emac/emac_membuf.h new file mode 100644 index 00000000000..b02f0692c33 --- /dev/null +++ b/TESTS/network/emac/emac_membuf.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_MEMBUF_H +#define EMAC_MEMBUF_H + +int emac_if_memory_buffer_read(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame); +void emac_if_memory_buffer_write(emac_stack_mem_chain_t *mem_chain_p, unsigned char *eth_frame, bool write_data); + +#endif /* EMAC_MEMBUF_H */ diff --git a/TESTS/network/emac/emac_test_broadcast.cpp b/TESTS/network/emac/emac_test_broadcast.cpp new file mode 100644 index 00000000000..1b5588cf5d9 --- /dev/null +++ b/TESTS/network/emac/emac_test_broadcast.cpp @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "emac_tests.h" +#include "emac_util.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +void test_emac_broadcast_cb(void) +{ + emac_if_validate_outgoing_msg(); + + static int counter = 0; + + // Send three broadcast + if (counter < 3) { + emac_if_ctp_msg_build(100, eth_mac_broadcast_addr, emac_if_get_own_addr(), emac_if_get_own_addr()); + counter++; + } else if (counter < 6) { + counter++; + } else if (counter < 9) { + emac_if_ctp_msg_build(50, eth_mac_broadcast_addr, emac_if_get_own_addr(), emac_if_get_own_addr()); + counter++; + } else if (counter < 12) { + counter++; + } else if (counter == 12) { + emac_if_reset_outgoing_msg(); + // ignore errors since just probing + RESET_ERROR_FLAGS; +#if MBED_CONF_APP_ECHO_SERVER + printf("echo server started successfully\r\n\r\n"); + counter = 255; +#else + worker_loop_end(); +#endif + } +} + +void test_emac_broadcast(void) +{ + RESET_ERROR_FLAGS; + SET_TRACE_LEVEL(TRACE_ETH_FRAMES | TRACE_SUCCESS | TRACE_FAILURE); + + worker_loop_start(test_emac_broadcast_cb, 10 * SECOND_TO_MS); + + PRINT_ERROR_FLAGS; + TEST_ASSERT_FALSE(ERROR_FLAGS); + RESET_OUTGOING_MSG_DATA; +} + +#endif diff --git a/TESTS/network/emac/emac_test_initialize.cpp b/TESTS/network/emac/emac_test_initialize.cpp new file mode 100644 index 00000000000..64cd5f907e2 --- /dev/null +++ b/TESTS/network/emac/emac_test_initialize.cpp @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "inttypes.h" + +#if MBED_CONF_APP_TEST_WIFI +#ifdef TARGET_UBLOX_EVK_ODIN_W2 +#include "wifi_emac_api.h" +#include "OdinWiFiInterface.h" +#endif +#ifdef TARGET_REALTEK_RTL8195AM +#include "rtw_emac.h" +#include "RTWInterface.h" +#endif +#endif + +#include "emac_api.h" +#include "emac_tests.h" +#include "emac_util.h" + +using namespace utest::v1; + +static unsigned char eth_mac_addr[ETH_MAC_ADDR_LEN]; + +static char emac_if_link_state_change_cb_data[] = "link_state_change_cb_data"; +static char emac_if_link_input_cb_data[] = "link_input_cb_data"; + +static bool emac_if_init(void); + +void test_emac_initialize() +{ +#if MBED_CONF_APP_TEST_WIFI + static WiFiInterface *wifi; + +#ifdef TARGET_UBLOX_EVK_ODIN_W2 + wifi = new OdinWiFiInterface; +#endif +#ifdef TARGET_REALTEK_RTL8195AM + wifi = new RTWInterface; +#endif + +#if MBED_CONF_APP_WIFI_SCAN + WiFiAccessPoint ap[30]; + + int size = wifi->scan(ap, 30); + + for (int i=0; iset_credentials(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, MBED_CONF_APP_WIFI_SECURITY); + wifi->connect(); + + const char *ip_addr = wifi->get_ip_address(); + printf("connected IP %s\r\n\r\n", ip_addr); +#endif + + TEST_ASSERT(emac_if_init()); +} + +unsigned char *emac_if_get_hw_addr(void) +{ + return ð_mac_addr[0]; +} + +emac_interface_t *emac_if_get(void) +{ +#if MBED_CONF_APP_TEST_WIFI +#ifdef TARGET_UBLOX_EVK_ODIN_W2 + return wifi_emac_get_interface(); +#endif +#ifdef TARGET_REALTEK_RTL8195AM + return wlan_emac_init_interface(); +#endif +#else + return 0; +#endif +} + +static bool emac_if_init(void) +{ + emac_interface_t *emac_if = emac_if_get(); + + emac_if->ops.set_link_input_cb(emac_if, emac_if_link_input_cb, emac_if_link_input_cb_data); + emac_if->ops.set_link_state_cb(emac_if, emac_if_link_state_change_cb, emac_if_link_state_change_cb_data); + + int hwaddr_len = emac_if->ops.get_hwaddr_size(emac_if); + printf("emac hwaddr length %i\r\n\r\n", hwaddr_len); + + if (hwaddr_len == 6) { + emac_if->ops.get_hwaddr(emac_if, eth_mac_addr); + printf("emac hwaddr %x:%x:%x:%x:%x:%x\r\n\r\n", eth_mac_addr[0],eth_mac_addr[1],eth_mac_addr[2],eth_mac_addr[3],eth_mac_addr[4],eth_mac_addr[5]); + } + + int mtu = emac_if->ops.get_mtu_size(emac_if); + printf("emac mtu %i\r\n\r\n", mtu); + + char hw_name[11]; + emac_if->ops.get_ifname(emac_if, hw_name, 10); + printf("emac if name %s\r\n\r\n", hw_name); + + if (!emac_if->ops.power_up(emac_if)) { + return false; + } + + return true; +} + +#endif diff --git a/TESTS/network/emac/emac_test_unicast.cpp b/TESTS/network/emac/emac_test_unicast.cpp new file mode 100644 index 00000000000..ee4088c647e --- /dev/null +++ b/TESTS/network/emac/emac_test_unicast.cpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "emac_tests.h" +#include "emac_util.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +void test_emac_unicast_cb(void) +{ + emac_if_validate_outgoing_msg(); + + static uint8_t counter = 0; + + // Send three unicast + if (counter < 3) { + emac_if_ctp_msg_build(100, emac_if_get_echo_server_addr(0), emac_if_get_own_addr(), emac_if_get_own_addr()); + } + + // End test + if (counter > 10) { + worker_loop_end(); + + if (emac_if_count_outgoing_msg() != 0) { + SET_ERROR_FLAGS(TEST_FAILED); + } + } + counter++; +} + +void test_emac_unicast() +{ + RESET_ERROR_FLAGS; + SET_TRACE_LEVEL(TRACE_ETH_FRAMES | TRACE_SUCCESS | TRACE_FAILURE); + + if (emac_if_count_echo_server_addr()) { + worker_loop_start(test_emac_unicast_cb, 1 * SECOND_TO_MS); + } + + PRINT_ERROR_FLAGS; + TEST_ASSERT_FALSE(ERROR_FLAGS); + RESET_OUTGOING_MSG_DATA; +} + +#endif diff --git a/TESTS/network/emac/emac_test_unicast_frame_len.cpp b/TESTS/network/emac/emac_test_unicast_frame_len.cpp new file mode 100644 index 00000000000..96aed45d130 --- /dev/null +++ b/TESTS/network/emac/emac_test_unicast_frame_len.cpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +#include "emac_tests.h" +#include "emac_util.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +void test_emac_unicast_frame_len_cb(void) +{ + emac_if_validate_outgoing_msg(); + + static uint32_t counter = 0; + + // Send unicast to echo server + if (counter < 16) { + static uint32_t msg_len = 0; + + emac_if_ctp_msg_build(msg_len, emac_if_get_echo_server_addr(0), emac_if_get_own_addr(), emac_if_get_own_addr()); + + msg_len += 100; + + if (msg_len > 1514) { + msg_len = 1514; + } + } + + if (counter > 18) { + if (emac_if_count_outgoing_msg() == 0) { + worker_loop_end(); + } + } + counter++; +} + +void test_emac_unicast_frame_len() +{ + RESET_ERROR_FLAGS; + SET_TRACE_LEVEL(TRACE_SUCCESS | TRACE_FAILURE); + + if (emac_if_count_echo_server_addr()) { + worker_loop_start(test_emac_unicast_frame_len_cb, 1 * SECOND_TO_MS); + } + + PRINT_ERROR_FLAGS; + TEST_ASSERT_FALSE(ERROR_FLAGS); + RESET_OUTGOING_MSG_DATA; +} + +#endif diff --git a/TESTS/network/emac/emac_tests.h b/TESTS/network/emac/emac_tests.h new file mode 100644 index 00000000000..edd0679cced --- /dev/null +++ b/TESTS/network/emac/emac_tests.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_TESTS_H +#define EMAC_TESTS_H + +void test_emac_initialize(); +void test_emac_broadcast(); +void test_emac_unicast(); +void test_emac_unicast_frame_len(); + +#endif /* EMAC_TESTS_H */ diff --git a/TESTS/network/emac/emac_util.cpp b/TESTS/network/emac/emac_util.cpp new file mode 100644 index 00000000000..920bd6407a6 --- /dev/null +++ b/TESTS/network/emac/emac_util.cpp @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +#if MBED_CONF_APP_TEST_WIFI || MBED_CONF_APP_TEST_ETHERNET + +extern "C" { // netif input +#include "tcpip.h" +} + +#include "emac_api.h" +#include "emac_stack_mem.h" + +#include "emac_tests.h" +#include "emac_initialize.h" +#include "emac_util.h" +#include "emac_membuf.h" +#include "emac_ctp.h" + +using namespace utest::v1; + +typedef struct { + int length; + int receipt_number; + unsigned short flags; + unsigned short lifetime; +} outgoing_msg_t; + +#define ECHO_SERVER_COUNT 5 + +#define OUTGOING_MSG_COUNT 100 + +// Event flags +#define LINK_UP 0x01 +#define LINK_DOWN 0x02 + +// Hook to lwip input function +extern struct netif *netif_list; + +// Broadcast address +const unsigned char eth_mac_broadcast_addr[ETH_MAC_ADDR_LEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + +// Event queue +static EventQueue worker_loop_event_queue; +static void worker_loop_event_cb(int event); +static Event worker_loop_event(&worker_loop_event_queue, worker_loop_event_cb); +static void link_input_event_cb(emac_stack_mem_chain_t *mem_chain_p); +static Event link_input_event(&worker_loop_event_queue, link_input_event_cb); + +// Found echo server addresses +static unsigned char eth_mac_echo_server_addr[ECHO_SERVER_COUNT][ETH_MAC_ADDR_LEN]; +static int etc_mac_echo_server_free_index = 0; + +// Outgoing messages +static outgoing_msg_t outgoing_msgs[OUTGOING_MSG_COUNT]; + +static unsigned int trace_level = 0; +static unsigned int error_flags = 0; +static unsigned int no_response_cnt = 0; + +int emac_if_find_outgoing_msg(int receipt_number) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length && outgoing_msgs[i].receipt_number == receipt_number) { + return i; + } + } + return -1; +} + +void emac_if_free_outgoing_msg(int index) +{ + outgoing_msgs[index].length = 0; +} + +int emac_if_count_outgoing_msg(void) +{ + int count = 0; + + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + count++; + } + } + + return count; +} + +void emac_if_reset_outgoing_msg(void) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + outgoing_msgs[i].length = 0; + } + } +} + +int emac_if_add_outgoing_msg(int length) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (!outgoing_msgs[i].length) { + outgoing_msgs[i].receipt_number = 0; + outgoing_msgs[i].length = length; + outgoing_msgs[i].flags = 0; + outgoing_msgs[i].lifetime = 10; + return i; + } + } + return -1; +} + +void emac_if_set_outgoing_msg_receipt_num(int index, int receipt_number) +{ + outgoing_msgs[index].receipt_number = receipt_number; +} + +void emac_if_set_outgoing_msg_flags(int index, int flags) +{ + outgoing_msgs[index].flags |= flags; +} + +void emac_if_timeout_outgoing_msg(void) +{ + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + if (outgoing_msgs[i].lifetime) { + outgoing_msgs[i].lifetime--; + if (outgoing_msgs[i].lifetime == 0) { + SET_ERROR_FLAGS(NO_RESPONSE); + } + } + } + } +} + +void emac_if_validate_outgoing_msg(void) +{ + static char broadcast_resp_count = 0; + + for (int i = 0; i < OUTGOING_MSG_COUNT; i++) { + if (outgoing_msgs[i].length) { + + if (outgoing_msgs[i].flags & RESPONSE_RECEIVED) { + + int failure = outgoing_msgs[i].flags & (INVALID_LENGHT | INVALID_DATA); + + if (failure) { + SET_ERROR_FLAGS(MSG_VALID_ERROR); + } + + if (!(outgoing_msgs[i].flags & PRINTED)) { + if ((trace_level & TRACE_SUCCESS) || ((trace_level & TRACE_FAILURE) && failure)) { + printf("response: receipt number %i %s %s %s\r\n\r\n", outgoing_msgs[i].receipt_number, + outgoing_msgs[i].flags & INVALID_LENGHT ? "LENGTH INVALID" : "LENGTH OK", + outgoing_msgs[i].flags & INVALID_DATA ? "DATA INVALID" : "DATA OK", + outgoing_msgs[i].flags & BROADCAST ? "BROADCAST" : "UNICAST"); + outgoing_msgs[i].flags |= PRINTED; + } + } + + if (outgoing_msgs[i].flags & BROADCAST) { + outgoing_msgs[i].lifetime = 2; + broadcast_resp_count++; + if (broadcast_resp_count > 5) { + emac_if_free_outgoing_msg(i); + } + } else { + emac_if_free_outgoing_msg(i); + } + } + + if (!outgoing_msgs[i].lifetime) { + if (!(outgoing_msgs[i].flags & RESPONSE_RECEIVED) && (trace_level & TRACE_FAILURE)) { + printf("NO RESPONSE: receipt number %i\r\n\r\n", outgoing_msgs[i].receipt_number); + } + emac_if_free_outgoing_msg(i); + } + } + } +} + +void emac_if_update_reply_to_outgoing_msg(int receipt_number, int lenght, int invalid_data_index) +{ + int32_t outgoing_msg_index = emac_if_find_outgoing_msg(receipt_number); + + if (outgoing_msg_index >= 0) { + outgoing_msgs[outgoing_msg_index].flags |= RESPONSE_RECEIVED; + +#if MBED_CONF_APP_TEST_ETHERNET + if (outgoing_msgs[outgoing_msg_index].length < ETH_FRAME_MIN_LEN) { + if (lenght != ETH_FRAME_MIN_LEN) { + outgoing_msgs[outgoing_msg_index].flags |= INVALID_LENGHT; + } + } else { +#endif + if (outgoing_msgs[outgoing_msg_index].length != lenght) { + outgoing_msgs[outgoing_msg_index].flags |= INVALID_LENGHT; + } +#if MBED_CONF_APP_TEST_ETHERNET + } +#endif + if (invalid_data_index && invalid_data_index < outgoing_msgs[outgoing_msg_index].length) { + outgoing_msgs[outgoing_msg_index].flags |= INVALID_DATA; + } + } +} + +void emac_if_add_echo_server_addr(unsigned char *addr) +{ + if (etc_mac_echo_server_free_index == ECHO_SERVER_COUNT) { + return; + } + + for (int i = 0; i < etc_mac_echo_server_free_index; i++) { + if (memcmp(ð_mac_echo_server_addr[i][0], addr, ETH_MAC_ADDR_LEN) == 0) { + return; + } + } + + memcpy(ð_mac_echo_server_addr[etc_mac_echo_server_free_index][0], addr, ETH_MAC_ADDR_LEN); + etc_mac_echo_server_free_index++; +} + +int emac_if_count_echo_server_addr(void) +{ + return etc_mac_echo_server_free_index; +} + +unsigned char *emac_if_get_echo_server_addr(int index) +{ + if (index < etc_mac_echo_server_free_index) { + return ð_mac_echo_server_addr[index][0]; + } + + return 0; +} + +void emac_if_set_error_flags(unsigned int error_flags_value) +{ + error_flags |= error_flags_value; + + if (error_flags_value & NO_RESPONSE) { + no_response_cnt++; + } +} + +unsigned int emac_if_get_error_flags(void) +{ + int error_flags_value = error_flags; + + // Indicate no response error only if more than three messages are lost + if (error_flags_value & NO_RESPONSE) { + if (no_response_cnt < 3) { + error_flags_value &= ~NO_RESPONSE; + } + } + + return error_flags_value; +} + +void emac_if_reset_error_flags(void) +{ + error_flags = 0; + no_response_cnt = 0; +} + +void emac_if_print_error_flags(void) +{ + int error_flags_value = emac_if_get_error_flags(); + + char no_resp_message[50]; + if (error_flags_value & NO_RESPONSE) { + snprintf(no_resp_message, 50, "no response from echo server, counter: %i", no_response_cnt); + } else if (no_response_cnt > 0) { + printf("no response from echo server, counter: %i\r\n\r\n", no_response_cnt); + } + + printf("test result: %s%s%s%s%s%s\r\n\r\n", + error_flags_value ? "Test FAILED, reason: ": "PASS", + error_flags_value & TEST_FAILED ? "test failed ": "", + error_flags_value & MSG_VALID_ERROR ? "message content validation error ": "", + error_flags_value & OUT_OF_MSG_DATA ? "out of message validation data storage ": "", + error_flags_value & NO_FREE_MEM_BUF ? "no free memory buffers ": "", + error_flags_value & NO_RESPONSE ? no_resp_message: ""); +} + +void emac_if_set_trace_level(char trace_level_value) +{ + trace_level = trace_level_value; +} + +void emac_if_trace_to_ascii_hex_dump(const char *prefix, int len, unsigned char *data) +{ + int line_len = 0; + + for (int i = 0; i < len; i++) { + if ((line_len % 14) == 0) { + if (line_len != 0) { + printf("\r\n"); + } + printf("%s %06x", prefix, line_len); + } + line_len++; + printf(" %02x", data[i]); + } + printf("\r\n\r\n"); +} + +void emac_if_link_state_change_cb(void *data, bool up) +{ + if (up) { + worker_loop_event.post(LINK_UP); + } else { + worker_loop_event.post(LINK_DOWN); + } +} + +void emac_if_link_input_cb(void *data, emac_stack_mem_chain_t *mem_chain_p) +{ + link_input_event.post(mem_chain_p); +} + +static void link_input_event_cb(emac_stack_mem_chain_t *mem_chain_p) +{ + int lenght = emac_stack_mem_len(0, mem_chain_p); + + if (lenght >= ETH_FRAME_HEADER_LEN) { + // Ethernet input frame + unsigned char eth_input_frame_data[ETH_FRAME_HEADER_LEN]; + memset(eth_input_frame_data, 0, ETH_FRAME_HEADER_LEN); + + int invalid_data_index = emac_if_memory_buffer_read(mem_chain_p, eth_input_frame_data); + + if (eth_input_frame_data[12] == 0x90 && eth_input_frame_data[13] == 0x00) { + unsigned char eth_output_frame_data[ETH_FRAME_HEADER_LEN]; + int receipt_number; + + ctp_function function = emac_if_ctp_header_handle(eth_input_frame_data, eth_output_frame_data, emac_if_get_hw_addr(), &receipt_number); + + if (function == CTP_REPLY) { + emac_if_update_reply_to_outgoing_msg(receipt_number, lenght, invalid_data_index); +#if MBED_CONF_APP_ECHO_SERVER + // Echoes only if configured as echo server + } else if (function == CTP_FORWARD) { + emac_if_memory_buffer_write(mem_chain_p, eth_output_frame_data, false); + emac_if_get()->ops.link_out(emac_if_get(), mem_chain_p); +#endif + } + + emac_if_add_echo_server_addr(ð_input_frame_data[6]); + + emac_stack_mem_free(0, mem_chain_p); + + if (trace_level & TRACE_ETH_FRAMES) { + printf("LEN %i\r\n\r\n", lenght); + const char trace_type[] = "INP>"; + emac_if_trace_to_ascii_hex_dump(trace_type, ETH_FRAME_HEADER_LEN, eth_input_frame_data); + } + return; + } + } + + // Forward other than CTP frames to lwip + struct netif *netif; + + /* loop through netif's */ + netif = netif_list; + if (netif != NULL) { + struct pbuf *p = (struct pbuf *)mem_chain_p; + + /* pass all packets to ethernet_input, which decides what packets it supports */ + if (netif->input(p, netif) != ERR_OK) { + emac_stack_mem_free(0, mem_chain_p); + } + } else { + emac_stack_mem_free(0, mem_chain_p); + } +} + +void worker_loop_start(void (*test_step_cb_fnc)(void), int timeout) +{ + int test_step_cb_timer = worker_loop_event_queue.call_every(timeout, test_step_cb_fnc); + int timeout_outgoing_msg_timer = worker_loop_event_queue.call_every(1000, emac_if_timeout_outgoing_msg); + +#if MBED_CONF_APP_ECHO_SERVER + worker_loop_event_queue.dispatch_forever(); +#else + worker_loop_event_queue.dispatch(600 * SECOND_TO_MS); +#endif + + worker_loop_event_queue.cancel(test_step_cb_timer); + worker_loop_event_queue.cancel(timeout_outgoing_msg_timer); + + worker_loop_event_queue.dispatch(5); +} + +static void worker_loop_event_cb(int event) +{ + if (event == LINK_UP) { + printf("cable connected\r\n\r\n"); + } + + if (event == LINK_DOWN) { + printf("cable disconnected\r\n\r\n"); + } +} + +void worker_loop_end(void) +{ + worker_loop_event_queue.break_dispatch(); +} + +unsigned char *emac_if_get_own_addr(void) +{ + return (emac_if_get_hw_addr()); +} + +#endif diff --git a/TESTS/network/emac/emac_util.h b/TESTS/network/emac/emac_util.h new file mode 100644 index 00000000000..59fc8506b0c --- /dev/null +++ b/TESTS/network/emac/emac_util.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMAC_UTIL_H +#define EMAC_UTIL_H + +#define SECOND_TO_US 1000000 +#define SECOND_TO_MS 1000 +#define MS_TO_US 1000 + +extern const unsigned char eth_mac_broadcast_addr[]; + +// Trace flags +#define TRACE_ETH_FRAMES 0x01 +#define TRACE_SUCCESS 0x02 +#define TRACE_FAILURE 0x04 +#define SET_TRACE_LEVEL(level) emac_if_set_trace_level(level) + +// Message validation flags +#define BROADCAST 0x01 +#define RESPONSE_RECEIVED 0x02 +#define INVALID_LENGHT 0x04 +#define INVALID_DATA 0x08 +#define PRINTED 0x10 + +#define RESET_OUTGOING_MSG_DATA emac_if_reset_outgoing_msg() + +// General error flags +#define TEST_FAILED 0x01 +#define MSG_VALID_ERROR 0x02 +#define OUT_OF_MSG_DATA 0x04 +#define NO_FREE_MEM_BUF 0x08 +#define NO_RESPONSE 0x10 + +#define ERROR_FLAGS emac_if_get_error_flags() +#define RESET_ERROR_FLAGS emac_if_reset_error_flags() +#define PRINT_ERROR_FLAGS emac_if_print_error_flags() +#define SET_ERROR_FLAGS(flags) emac_if_set_error_flags(flags) + +#define ETH_FRAME_HEADER_LEN 28 +#define ETH_FRAME_MIN_LEN 60 +#define ETH_MAC_ADDR_LEN 6 + +int emac_if_find_outgoing_msg(int receipt_number); +void emac_if_free_outgoing_msg(int index); +int emac_if_count_outgoing_msg(void); +void emac_if_reset_outgoing_msg(void); +int emac_if_add_outgoing_msg(int length); +void emac_if_timeout_outgoing_msg(void); +void emac_if_validate_outgoing_msg(void); +void emac_if_set_outgoing_msg_receipt_num(int index, int receipt_number); +void emac_if_set_outgoing_msg_flags(int index, int flags); + +void emac_if_add_echo_server_addr(unsigned char *addr); +int emac_if_count_echo_server_addr(void); +unsigned char *emac_if_get_echo_server_addr(int index); + +void emac_if_set_error_flags(unsigned int error_flags_value); +unsigned int emac_if_get_error_flags(void); +void emac_if_reset_error_flags(void); +void emac_if_print_error_flags(void); + +void emac_if_set_trace_level(char trace_level_value); + +void emac_if_trace_to_ascii_hex_dump(const char *prefix, int len, char *data); + +void emac_if_link_state_change_cb(void *data, bool up); + +unsigned char *emac_if_get_own_addr(void); + +extern void emac_if_link_input_cb(void *data, void *mem_chain_p); +extern void emac_if_link_state_change_cb(void *data, bool up); + +void worker_loop_start(void (*test_step_cb_fnc)(void), int timeout); +void worker_loop_end(void); + +void emac_if_init_main_thread(void); + +#endif /* EMAC_UTIL_H */ diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp new file mode 100644 index 00000000000..454bb693530 --- /dev/null +++ b/TESTS/network/emac/main.cpp @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(MBED_CONF_APP_TEST_WIFI) || \ + !defined(MBED_CONF_APP_TEST_ETHERNET) || \ + !defined(MBED_CONF_APP_ECHO_SERVER) || \ + !defined(MBED_CONF_APP_WIFI_SCAN) || \ + !defined(MBED_CONF_APP_WIFI_SSID ) || \ + !defined(MBED_CONF_APP_WIFI_SECURITY) || \ + !defined(MBED_CONF_APP_WIFI_PASSWORD) +#error [NOT_SUPPORTED] Requires parameters from mbed_app.json +#endif + +#if !MBED_CONF_APP_TEST_WIFI && !MBED_CONF_APP_TEST_ETHERNET +#error [NOT_SUPPORTED] Either wifi or ethernet testing need to be enabled +#endif +#if MBED_CONF_APP_TEST_WIFI +#if !defined(TARGET_UBLOX_EVK_ODIN_W2) && !defined(TARGET_REALTEK_RTL8195AM) +#error [NOT_SUPPORTED] Tests are valid only for UBLOX_EVK_ODIN_W2 and REALTEK_RTL8195AM +#endif +#endif +#if MBED_CONF_APP_TEST_ETHERNET +#error [NOT_SUPPORTED] Ethernet testing not supported +#endif + +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest.h" + +#include "emac_tests.h" +#include "emac_util.h" + +using namespace utest::v1; + +// Test setup +utest::v1::status_t test_setup(const size_t number_of_cases) { +#if !MBED_CONF_APP_ECHO_SERVER + GREENTEA_SETUP(600, "default_auto"); +#endif + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("EMAC interface initialize", test_emac_initialize), + Case("EMAC interface broadcast", test_emac_broadcast), + Case("EMAC interface unicast", test_emac_unicast), + Case("EMAC interface unicast frame length", test_emac_unicast_frame_len), + Case("EMAC interface broadcast (run again)", test_emac_broadcast) +}; + +Specification specification(test_setup, cases); + +int main() +{ + return !Harness::run(specification); +} + diff --git a/TESTS/network/emac/template_mbed_app.txt b/TESTS/network/emac/template_mbed_app.txt new file mode 100644 index 00000000000..ce8b8076e0e --- /dev/null +++ b/TESTS/network/emac/template_mbed_app.txt @@ -0,0 +1,32 @@ +{ + "config": { + "test-ethernet": { + "help": "Enable ethernet testing", + "value": 0 + }, + "test-wifi": { + "help": "Enable wifi testing", + "value": 1 + }, + "echo-server": { + "help": "Build test to be echo server", + "value": 0 + }, + "wifi-scan": { + "help": "Scan and list access points", + "value": 0 + }, + "wifi-ssid": { + "help": "WiFi SSID for network", + "value": "\"SSID\"" + }, + "wifi-security": { + "help": "WiFi Security", + "value": "NSAPI_SECURITY_WPA_WPA2" + }, + "wifi-password": { + "help": "WiFi Password", + "value": "\"PASSWORD\"" + } + } +} diff --git a/TESTS/network/wifi/get_interface.cpp b/TESTS/network/wifi/get_interface.cpp index 9bafab9b588..bc464e2de14 100644 --- a/TESTS/network/wifi/get_interface.cpp +++ b/TESTS/network/wifi/get_interface.cpp @@ -20,7 +20,7 @@ // Pick the correct driver based on mbed_app.json #define INTERNAL 1 #define WIFI_ESP8266 2 -#define X_NUCLEO_IDW01M1 3 +#define X_NUCLEO_IDW0XX1 3 #if MBED_CONF_APP_WIFI_DRIVER == INTERNAL @@ -39,7 +39,7 @@ #include "ESP8266Interface.h" #define DRIVER ESP8266Interface -#elif MBED_CONF_APP_WIFI_DRIVER == X_NUCLEO_IDW01M1 +#elif MBED_CONF_APP_WIFI_DRIVER == X_NUCLEO_IDW0XX1 #include "SpwfSAInterface.h" #define DRIVER SpwfSAInterface #else @@ -50,8 +50,10 @@ WiFiInterface *get_interface() { static WiFiInterface *interface = NULL; - if (interface) - delete interface; + if (interface) { + interface->disconnect(); + return interface; + } #if MBED_CONF_APP_WIFI_DRIVER == INTERNAL interface = new DRIVER(); diff --git a/TESTS/network/wifi/get_security.cpp b/TESTS/network/wifi/get_security.cpp new file mode 100644 index 00000000000..ae94b656b06 --- /dev/null +++ b/TESTS/network/wifi/get_security.cpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "mbed.h" +#include "nsapi_types.h" + +nsapi_security get_security() +{ +#if defined MBED_CONF_APP_WIFI_SECURE_PROTOCOL + static const char *SEC_WEP = "WEP"; + static const char *SEC_WPA = "WPA"; + static const char *SEC_WPA2 = "WPA2"; + static const char *SEC_WPA_WPA2 = "WPA/WPA2"; + + if (strcmp(MBED_CONF_APP_WIFI_SECURE_PROTOCOL, SEC_WEP) == 0) { + return NSAPI_SECURITY_WEP; + } + if (strcmp(MBED_CONF_APP_WIFI_SECURE_PROTOCOL, SEC_WPA) == 0) { + return NSAPI_SECURITY_WPA; + } + if (strcmp(MBED_CONF_APP_WIFI_SECURE_PROTOCOL, SEC_WPA2) == 0) { + return NSAPI_SECURITY_WPA2; + } + if (strcmp(MBED_CONF_APP_WIFI_SECURE_PROTOCOL, SEC_WPA_WPA2) == 0) { + return NSAPI_SECURITY_WPA_WPA2; + } +#endif + return NSAPI_SECURITY_NONE; +} diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp index 1245b11e2dd..38d311d6b9e 100644 --- a/TESTS/network/wifi/main.cpp +++ b/TESTS/network/wifi/main.cpp @@ -22,19 +22,32 @@ #include "wifi_tests.h" // Test for parameters +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) #if !defined(MBED_CONF_APP_AP_MAC_SECURE) || \ - !defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ !defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ !defined(MBED_CONF_APP_WIFI_CH_SECURE) || \ - !defined(MBED_CONF_APP_WIFI_CH_UNSECURE) || \ !defined(MBED_CONF_APP_WIFI_DRIVER) || \ !defined(MBED_CONF_APP_WIFI_PASSWORD) || \ !defined(MBED_CONF_APP_WIFI_RX) || \ !defined(MBED_CONF_APP_WIFI_SECURE_SSID) || \ !defined(MBED_CONF_APP_WIFI_TX) || \ + !defined MBED_CONF_APP_WIFI_SECURE_PROTOCOL +#error [NOT_SUPPORTED] Requires parameters from mbed_app.json (for secure connections) +#endif +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) + +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) +#if !defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ + !defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ + !defined(MBED_CONF_APP_WIFI_CH_UNSECURE) || \ + !defined(MBED_CONF_APP_WIFI_DRIVER) || \ + !defined(MBED_CONF_APP_WIFI_PASSWORD) || \ + !defined(MBED_CONF_APP_WIFI_RX) || \ + !defined(MBED_CONF_APP_WIFI_TX) || \ !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) -#error [NOT_SUPPORTED] Requires parameters from mbed_app.json +#error [NOT_SUPPORTED] Requires parameters from mbed_app.json (for unsecure connections) #endif +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) using namespace utest::v1; @@ -46,21 +59,35 @@ utest::v1::status_t test_setup(const size_t number_of_cases) { // Test cases Case cases[] = { Case("WIFI-CONSTRUCTOR", wifi_constructor), + Case("WIFI-CONNECT-NOCREDENTIALS", wifi_connect_nocredentials), Case("WIFI-SET-CREDENTIAL", wifi_set_credential), Case("WIFI-SET-CHANNEL", wifi_set_channel), +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-GET-RSSI", wifi_get_rssi), +#endif Case("WIFI-CONNECT-PARAMS-NULL", wifi_connect_params_null), +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-CONNECT-PARAMS-VALID-UNSECURE", wifi_connect_params_valid_unsecure), +#endif +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) Case("WIFI-CONNECT-PARAMS-VALID-SECURE", wifi_connect_params_valid_secure), Case("WIFI-CONNECT-PARAMS-CHANNEL", wifi_connect_params_channel), Case("WIFI-CONNECT-PARAMS-CHANNEL-FAIL", wifi_connect_params_channel_fail), - Case("WIFI-CONNECT-NOCREDENTIALS", wifi_connect_nocredentials), +#endif +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-CONNECT", wifi_connect), +#endif +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) Case("WIFI-CONNECT-SECURE", wifi_connect_secure), Case("WIFI-CONNECT-SECURE-FAIL", wifi_connect_secure_fail), +#endif +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-CONNECT-DISCONNECT-REPEAT", wifi_connect_disconnect_repeat), +#endif Case("WIFI-SCAN-NULL", wifi_scan_null), +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) && defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-SCAN", wifi_scan), +#endif }; Specification specification(test_setup, cases); diff --git a/TESTS/network/wifi/template_mbed_app.txt b/TESTS/network/wifi/template_mbed_app.txt index ddab934545a..6c680422e52 100644 --- a/TESTS/network/wifi/template_mbed_app.txt +++ b/TESTS/network/wifi/template_mbed_app.txt @@ -12,6 +12,10 @@ "help": "WiFi Password", "value": "\"PASSWORD\"" }, + "wifi-secure-protocol": { + "help": "WiFi security protocol, valid values are WEP, WPA, WPA2, WPA/WPA2", + "value": "\"WPA/WPA2\"" + }, "wifi-ch-secure": { "help": "Channel number of secure SSID", "value": 1 @@ -21,7 +25,7 @@ "value": 2 }, "wifi-driver": { - "help": "Wifi driver to use, valid values are INTERNAL, WIFI_ESP8266 and X_NUCLEO_IDW01M1", + "help": "Wifi driver to use, valid values are INTERNAL, WIFI_ESP8266 and X_NUCLEO_IDW0XX1", "value": "INTERNAL" }, "wifi-tx": { diff --git a/TESTS/network/wifi/wifi_connect.cpp b/TESTS/network/wifi/wifi_connect.cpp index c244e0247fc..6d279888385 100644 --- a/TESTS/network/wifi/wifi_connect.cpp +++ b/TESTS/network/wifi/wifi_connect.cpp @@ -23,6 +23,8 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + void wifi_connect(void) { WiFiInterface *wifi = get_interface(); @@ -31,3 +33,5 @@ void wifi_connect(void) TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect()); } + +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp index 9ee73fc5587..90f4c5994bd 100644 --- a/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp +++ b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp @@ -23,6 +23,8 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + void wifi_connect_disconnect_repeat(void) { WiFiInterface *wifi = get_interface(); @@ -38,3 +40,5 @@ void wifi_connect_disconnect_repeat(void) TEST_ASSERT(error == NSAPI_ERROR_OK); } } + +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_nocredentials.cpp b/TESTS/network/wifi/wifi_connect_nocredentials.cpp index c930d7d0a95..5e3026623c5 100644 --- a/TESTS/network/wifi/wifi_connect_nocredentials.cpp +++ b/TESTS/network/wifi/wifi_connect_nocredentials.cpp @@ -28,6 +28,5 @@ void wifi_connect_nocredentials(void) WiFiInterface *wifi = get_interface(); nsapi_error_t error; error = wifi->connect(); - wifi->disconnect(); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT(error == NSAPI_ERROR_NO_SSID || error == NSAPI_ERROR_PARAMETER); } diff --git a/TESTS/network/wifi/wifi_connect_params_channel.cpp b/TESTS/network/wifi/wifi_connect_params_channel.cpp index 08c34a9c541..ed129327354 100644 --- a/TESTS/network/wifi/wifi_connect_params_channel.cpp +++ b/TESTS/network/wifi/wifi_connect_params_channel.cpp @@ -23,6 +23,8 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) + void wifi_connect_params_channel(void) { WiFiInterface *wifi = get_interface(); @@ -32,7 +34,8 @@ void wifi_connect_params_channel(void) return; } - nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2, MBED_CONF_APP_WIFI_CH_SECURE); + nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security(), MBED_CONF_APP_WIFI_CH_SECURE); TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); } +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp b/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp index f1d56d22496..ad0d6a0f552 100644 --- a/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp +++ b/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp @@ -23,6 +23,8 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) + void wifi_connect_params_channel_fail(void) { WiFiInterface *wifi = get_interface(); @@ -32,7 +34,8 @@ void wifi_connect_params_channel_fail(void) return; } - nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2, MBED_CONF_APP_WIFI_CH_UNSECURE); + nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security(), MBED_CONF_APP_WIFI_CH_SECURE); TEST_ASSERT(error==NSAPI_ERROR_CONNECTION_TIMEOUT || error==NSAPI_ERROR_NO_CONNECTION); } +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp b/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp index 0da25c67927..112a4af389c 100644 --- a/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp +++ b/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp @@ -23,8 +23,17 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) + void wifi_connect_params_valid_secure(void) { WiFiInterface *wifi = get_interface(); - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2)); + + if(wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security()) == NSAPI_ERROR_OK) { + return; + } + + TEST_FAIL(); } + +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp b/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp index e1540b24a8d..91d8f144ea9 100644 --- a/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp +++ b/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp @@ -23,9 +23,12 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + void wifi_connect_params_valid_unsecure(void) { WiFiInterface *wifi = get_interface(); TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL)); } +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_secure.cpp b/TESTS/network/wifi/wifi_connect_secure.cpp index dce86f969fd..5f0cfba64d7 100644 --- a/TESTS/network/wifi/wifi_connect_secure.cpp +++ b/TESTS/network/wifi/wifi_connect_secure.cpp @@ -23,12 +23,15 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) + void wifi_connect_secure(void) { WiFiInterface *wifi = get_interface(); - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2)); + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security())); TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect()); } +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) diff --git a/TESTS/network/wifi/wifi_connect_secure_fail.cpp b/TESTS/network/wifi/wifi_connect_secure_fail.cpp index 7e55a290a87..2c4a90ba1d1 100644 --- a/TESTS/network/wifi/wifi_connect_secure_fail.cpp +++ b/TESTS/network/wifi/wifi_connect_secure_fail.cpp @@ -23,12 +23,15 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) + void wifi_connect_secure_fail(void) { WiFiInterface *wifi = get_interface(); - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, "aaaaaaaa", NSAPI_SECURITY_WPA2)); + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, "aaaaaaaa", get_security())); TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_AUTH_FAILURE, wifi->connect()); } +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) diff --git a/TESTS/network/wifi/wifi_get_rssi.cpp b/TESTS/network/wifi/wifi_get_rssi.cpp index ac4338ff934..d95e6386ffe 100644 --- a/TESTS/network/wifi/wifi_get_rssi.cpp +++ b/TESTS/network/wifi/wifi_get_rssi.cpp @@ -23,6 +23,8 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + void wifi_get_rssi(void) { WiFiInterface *wifi = get_interface(); @@ -33,6 +35,7 @@ void wifi_get_rssi(void) TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect()); - TEST_ASSERT_INT8_WITHIN(-35, -65, wifi->get_rssi()); // -30 ... -100 + TEST_ASSERT_INT8_WITHIN(-10, -100, wifi->get_rssi()); } +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) diff --git a/TESTS/network/wifi/wifi_scan.cpp b/TESTS/network/wifi/wifi_scan.cpp index d4722dd0d08..6986d64d1ef 100644 --- a/TESTS/network/wifi/wifi_scan.cpp +++ b/TESTS/network/wifi/wifi_scan.cpp @@ -24,6 +24,8 @@ using namespace utest::v1; +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) && defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + void wifi_scan(void) { WiFiInterface *wifi = get_interface(); @@ -44,24 +46,27 @@ void wifi_scan(void) for (int i=0; iset_credentials("OK", NULL, NSAPI_SECURITY_WPA_WPA2); TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); - error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA); + error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_NONE); TEST_ASSERT(error == NSAPI_ERROR_OK); + error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WEP); + TEST_ASSERT((error == NSAPI_ERROR_OK) || (error == NSAPI_ERROR_UNSUPPORTED)); + + error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA); + TEST_ASSERT((error == NSAPI_ERROR_OK) || (error == NSAPI_ERROR_UNSUPPORTED)); + error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA2); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT((error == NSAPI_ERROR_OK) || (error == NSAPI_ERROR_UNSUPPORTED)); error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA_WPA2); TEST_ASSERT(error == NSAPI_ERROR_OK); - error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni82", NSAPI_SECURITY_WPA2); + error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni", get_security()); + TEST_ASSERT(error == NSAPI_ERROR_OK); + + error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni8", get_security()); TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); } diff --git a/TESTS/network/wifi/wifi_tests.h b/TESTS/network/wifi/wifi_tests.h index 1ef40ccc2de..b7d598b8b65 100644 --- a/TESTS/network/wifi/wifi_tests.h +++ b/TESTS/network/wifi/wifi_tests.h @@ -7,6 +7,11 @@ * app_json. */ WiFiInterface *get_interface(void); +/** + * Get security protocol to be used + */ +nsapi_security get_security(void); + /* * Test cases */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_armcc.h b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h index 1b4ab2c321c..cef7694a754 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h @@ -37,26 +37,29 @@ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm -#endif -#ifndef __INLINE +#endif +#ifndef __INLINE #define __INLINE __inline -#endif -#ifndef __FORCEINLINE +#endif +#ifndef __FORCEINLINE #define __FORCEINLINE __forceinline -#endif -#ifndef __STATIC_INLINE +#endif +#ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE +#endif +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN +#endif +#ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED #define __USED __attribute__((used)) -#endif -#ifndef __WEAK +#endif +#ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED @@ -79,8 +82,8 @@ #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED +#endif +#ifndef __PACKED #define __PACKED __attribute__((packed)) #endif @@ -134,6 +137,7 @@ /** \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ @@ -141,6 +145,7 @@ /** \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ @@ -153,12 +158,13 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u #endif /** - \brief Reverse byte order in signed short value + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr @@ -351,14 +357,16 @@ __STATIC_INLINE void __set_CPSR(uint32_t cpsr) /** \brief Get Mode \return Processor Mode */ -__STATIC_INLINE uint32_t __get_mode(void) { +__STATIC_INLINE uint32_t __get_mode(void) +{ return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ -__STATIC_INLINE __ASM void __set_mode(uint32_t mode) { +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ MOV r1, lr MSR CPSR_C, r0 BX r1 @@ -373,7 +381,7 @@ __STATIC_INLINE __ASM uint32_t __get_SP(void) BX lr } -/** \brief Set Stack Pointer +/** \brief Set Stack Pointer \param [in] stack Stack Pointer value to set */ __STATIC_INLINE __ASM void __set_SP(uint32_t stack) @@ -442,75 +450,32 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) /* * Include common core functions to access Coprocessor 15 registers */ - -#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); Rt = tmp; } while(0) -#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = Rt; } while(0) -#include "cmsis_cp15.h" +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) -/** \brief Clean and Invalidate the entire data or unified cache - * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean - */ -__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) { - ARM +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) - PUSH {R4-R11} - - MRC p15, 1, R6, c0, c0, 1 // Read CLIDR - ANDS R3, R6, #0x07000000 // Extract coherency level - MOV R3, R3, LSR #23 // Total cache levels << 1 - BEQ Finished // If 0, no need to clean - - MOV R10, #0 // R10 holds current cache level << 1 -Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position - MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level - AND R1, R1, #7 // Isolate those lower 3 bits - CMP R1, #2 - BLT Skip // No cache or only instruction cache at this level - - MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register - ISB // ISB to sync the change to the CacheSizeID reg - MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register - AND R2, R1, #7 // Extract the line length field - ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) - LDR R4, =0x3FF - ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) - CLZ R5, R4 // R5 is the bit position of the way size increment - LDR R7, =0x7FFF - ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) - -Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) - -Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 - ORR R11, R11, R7, LSL R2 // Factor in the Set number - CMP R0, #0 - BNE Dccsw - MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way - B cont -Dccsw CMP R0, #1 - BNE Dccisw - MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way - B cont -Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way -cont SUBS R9, R9, #1 // Decrement the Way number - BGE Loop3 - SUBS R7, R7, #1 // Decrement the Set number - BGE Loop2 -Skip ADD R10, R10, #2 // Increment the cache number - CMP R3, R10 - BGT Loop1 - -Finished - DSB - POP {R4-R11} - BX lr -} +#include "cmsis_cp15.h" /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled */ -__STATIC_INLINE __ASM void __FPU_Enable(void) { +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ ARM //Permit access to VFP/NEON, registers by modifying CPACR @@ -528,7 +493,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) { //Initialise VFP/NEON registers to 0 MOV R2,#0 - IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 + //Initialise D16 registers to 0 VMOV D0, R2,R2 VMOV D1, R2,R2 @@ -546,7 +511,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) { VMOV D13,R2,R2 VMOV D14,R2,R2 VMOV D15,R2,R2 - ENDIF + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 //Initialise D32 registers to 0 VMOV D16,R2,R2 diff --git a/cmsis/TARGET_CORTEX_A/cmsis_armclang.h b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h index 9c93f2fd1d5..8853836e0b7 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h @@ -25,6 +25,8 @@ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H +#pragma clang system_header /* treat file as system include file */ + #ifndef __ARM_COMPAT_H #include /* Compatibility header for ARM Compiler 5 intrinsics */ #endif @@ -32,26 +34,29 @@ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm -#endif -#ifndef __INLINE +#endif +#ifndef __INLINE #define __INLINE __inline -#endif -#ifndef __FORCEINLINE +#endif +#ifndef __FORCEINLINE #define __FORCEINLINE __attribute__((always_inline)) -#endif -#ifndef __STATIC_INLINE +#endif +#ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE +#endif +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED #define __USED __attribute__((used)) -#endif -#ifndef __WEAK +#endif +#ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED @@ -93,8 +98,8 @@ #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED +#endif +#ifndef __PACKED #define __PACKED __attribute__((packed)) #endif @@ -148,38 +153,29 @@ /** \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ -#define __REV __builtin_bswap32 +#define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); - return result; -} -#endif +#define __REV16(value) __ROR(__REV(value), 16) + /** - \brief Reverse byte order in signed short value + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value)); - return result; -} -#endif +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + /** \brief Rotate Right in unsigned value (32 bit) @@ -188,31 +184,37 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t \param [in] op2 Number of Bits to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } return (op1 >> op2) | (op1 << (32U - op2)); } + /** \brief Breakpoint \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) +#define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \param [in] value Value to reverse \return Reversed value */ -#define __RBIT __builtin_arm_rbit +#define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __builtin_clz +#define __CLZ (uint8_t)__builtin_clz /** \brief LDR Exclusive (8 bit) @@ -313,7 +315,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint /** \brief Get CPSR Register \return CPSR Register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPSR(void) +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) { uint32_t result; __ASM volatile("MRS %0, cpsr" : "=r" (result) ); @@ -323,7 +325,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPSR(void) /** \brief Set CPSR Register \param [in] cpsr CPSR value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) { __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); } @@ -331,7 +333,7 @@ __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); /** \brief Get Mode \return Processor Mode */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_mode(void) +__STATIC_FORCEINLINE uint32_t __get_mode(void) { return (__get_CPSR() & 0x1FU); } @@ -339,7 +341,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_mode(void) /** \brief Set Mode \param [in] mode Mode value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_mode(uint32_t mode) +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) { __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } @@ -347,7 +349,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_mode(uint32_t mode) /** \brief Get Stack Pointer \return Stack Pointer value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP() +__STATIC_FORCEINLINE uint32_t __get_SP() { uint32_t result; __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); @@ -357,7 +359,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP() /** \brief Set Stack Pointer \param [in] stack Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_SP(uint32_t stack) +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) { __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); } @@ -365,7 +367,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_SP(uint32_t stack) /** \brief Get USR/SYS Stack Pointer \return USR/SYS Stack Pointer value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr() +__STATIC_FORCEINLINE uint32_t __get_SP_usr() { uint32_t cpsr; uint32_t result; @@ -382,7 +384,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr() /** \brief Set USR/SYS Stack Pointer \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack) +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) { uint32_t cpsr; __ASM volatile( @@ -397,7 +399,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfP /** \brief Get FPEXC \return Floating Point Exception Control register value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void) +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) { #if (__FPU_PRESENT == 1) uint32_t result; @@ -411,7 +413,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void) /** \brief Set FPEXC \param [in] fpexc Floating Point Exception Control value to set */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) { #if (__FPU_PRESENT == 1) __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); @@ -424,69 +426,11 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" - -/** \brief Clean and Invalidate the entire data or unified cache - - Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency - */ -__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) -{ - __ASM volatile( - " PUSH {R4-R11} \n" - - " MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR - " ANDS R3, R6, #0x07000000 \n" // Extract coherency level - " MOV R3, R3, LSR #23 \n" // Total cache levels << 1 - " BEQ Finished \n" // If 0, no need to clean - - " MOV R10, #0 \n" // R10 holds current cache level << 1 - "Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position - " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level - " AND R1, R1, #7 \n" // Isolate those lower 3 bits - " CMP R1, #2 \n" - " BLT Skip \n" // No cache or only instruction cache at this level - - " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register - " ISB \n" // ISB to sync the change to the CacheSizeID reg - " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register - " AND R2, R1, #7 \n" // Extract the line length field - " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes) - " LDR R4, =0x3FF \n" - " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned) - " CLZ R5, R4 \n" // R5 is the bit position of the way size increment - " LDR R7, =0x7FFF \n" - " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned) - - "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned) - - "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11 - " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number - " CMP R0, #0 \n" - " BNE Dccsw \n" - " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way - " B cont \n" - "Dccsw: CMP R0, #1 \n" - " BNE Dccisw \n" - " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way - " B cont \n" - "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way - "cont: SUBS R9, R9, #1 \n" // Decrement the Way number - " BGE Loop3 \n" - " SUBS R7, R7, #1 \n" // Decrement the Set number - " BGE Loop2 \n" - "Skip: ADD R10, R10, #2 \n" // Increment the cache number - " CMP R3, R10 \n" - " BGT Loop1 \n" - - "Finished: \n" - " DSB \n" - " POP {R4-R11} " - ); -} - /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled @@ -494,24 +438,23 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) __STATIC_INLINE void __FPU_Enable(void) { __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR + //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" - //Enable VFP/NEON + //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" - //Initialise VFP/NEON registers to 0 + //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" -#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16 - //Initialise D16 registers to 0 + //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" @@ -528,10 +471,9 @@ __STATIC_INLINE void __FPU_Enable(void) " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" -#endif -#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 - //Initialise D32 registers to 0 +#if __ARM_NEON == 1 + //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" @@ -548,9 +490,9 @@ __STATIC_INLINE void __FPU_Enable(void) " VMOV D29,R2,R2 \n" " VMOV D30,R2,R2 \n" " VMOV D31,R2,R2 \n" - ".endif \n" #endif - //Initialise FPSCR to a known state + + //Initialise FPSCR to a known state " VMRS R2,FPSCR \n" " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R2,R2,R3 \n" diff --git a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h index ec27cfeac8e..d1ef182353e 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.00 - * @date 22. Feb 2017 + * @version V1.0.1 + * @date 01. December 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -54,7 +54,7 @@ #elif defined ( __ICCARM__ ) #include "cmsis_iccarm.h" - + /* * TI ARM Compiler */ @@ -70,9 +70,18 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif #ifndef __USED #define __USED __attribute__((used)) #endif @@ -110,9 +119,15 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif #ifndef __USED #define __USED __attribute__((used)) #endif @@ -146,6 +161,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN @@ -154,6 +172,10 @@ #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif #ifndef __WEAK #define __WEAK __weak #endif diff --git a/cmsis/TARGET_CORTEX_A/cmsis_cp15.h b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h index 68b39f30921..69c991eea80 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_cp15.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h @@ -22,6 +22,12 @@ * limitations under the License. */ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef __CMSIS_CP15_H #define __CMSIS_CP15_H @@ -31,7 +37,6 @@ __STATIC_FORCEINLINE uint32_t __get_ACTLR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r" (result) : : "memory" ); __get_CP(15, 0, result, 1, 0, 1); return(result); } @@ -41,7 +46,6 @@ __STATIC_FORCEINLINE uint32_t __get_ACTLR(void) */ __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) { - // __ASM volatile ("MCR p15, 0, %0, c1, c0, 1" : : "r" (actlr) : "memory"); __set_CP(15, 0, actlr, 1, 0, 1); } @@ -51,7 +55,6 @@ __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) __STATIC_FORCEINLINE uint32_t __get_CPACR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 1, 0, 2); return result; } @@ -61,7 +64,6 @@ __STATIC_FORCEINLINE uint32_t __get_CPACR(void) */ __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) { -// __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory"); __set_CP(15, 0, cpacr, 1, 0, 2); } @@ -71,7 +73,6 @@ __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) __STATIC_FORCEINLINE uint32_t __get_DFSR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c5, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 5, 0, 0); return result; } @@ -81,7 +82,6 @@ __STATIC_FORCEINLINE uint32_t __get_DFSR(void) */ __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) { -// __ASM volatile("MCR p15, 0, %0, c5, c0, 0" : : "r"(dfsr) : "memory"); __set_CP(15, 0, dfsr, 5, 0, 0); } @@ -91,7 +91,6 @@ __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) __STATIC_FORCEINLINE uint32_t __get_IFSR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c5, c0, 1" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 5, 0, 1); return result; } @@ -101,7 +100,6 @@ __STATIC_FORCEINLINE uint32_t __get_IFSR(void) */ __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) { -// __ASM volatile("MCR p15, 0, %0, c5, c0, 1" : : "r"(ifsr) : "memory"); __set_CP(15, 0, ifsr, 5, 0, 1); } @@ -111,7 +109,6 @@ __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) __STATIC_FORCEINLINE uint32_t __get_ISR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c12, c1, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 12, 1, 0); return result; } @@ -122,7 +119,6 @@ __STATIC_FORCEINLINE uint32_t __get_ISR(void) __STATIC_FORCEINLINE uint32_t __get_CBAR(void) { uint32_t result; -// __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 4, result, 15, 0, 0); return result; } @@ -136,7 +132,6 @@ __STATIC_FORCEINLINE uint32_t __get_CBAR(void) __STATIC_FORCEINLINE uint32_t __get_TTBR0(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 2, 0, 0); return result; } @@ -149,7 +144,6 @@ __STATIC_FORCEINLINE uint32_t __get_TTBR0(void) */ __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) { -// __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory"); __set_CP(15, 0, ttbr0, 2, 0, 0); } @@ -162,7 +156,6 @@ __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) __STATIC_FORCEINLINE uint32_t __get_DACR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 3, 0, 0); return result; } @@ -175,7 +168,6 @@ __STATIC_FORCEINLINE uint32_t __get_DACR(void) */ __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) { -// __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory"); __set_CP(15, 0, dacr, 3, 0, 0); } @@ -187,7 +179,6 @@ __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) */ __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) { -// __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory"); __set_CP(15, 0, sctlr, 1, 0, 0); } @@ -197,7 +188,6 @@ __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) __STATIC_FORCEINLINE uint32_t __get_SCTLR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 1, 0, 0); return result; } @@ -207,7 +197,6 @@ __STATIC_FORCEINLINE uint32_t __get_SCTLR(void) */ __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) { -// __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory"); __set_CP(15, 0, actrl, 1, 0, 1); } @@ -217,7 +206,6 @@ __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) __STATIC_FORCEINLINE uint32_t __get_ACTRL(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 1, 0, 1); return result; } @@ -231,7 +219,6 @@ __STATIC_FORCEINLINE uint32_t __get_ACTRL(void) __STATIC_FORCEINLINE uint32_t __get_MPIDR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 0, 0, 5); return result; } @@ -245,7 +232,6 @@ __STATIC_FORCEINLINE uint32_t __get_MPIDR(void) __STATIC_FORCEINLINE uint32_t __get_VBAR(void) { uint32_t result; -// __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 12, 0, 0); return result; } @@ -258,7 +244,6 @@ __STATIC_FORCEINLINE uint32_t __get_VBAR(void) */ __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) { -// __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory"); __set_CP(15, 0, vbar, 12, 0, 1); } @@ -274,7 +259,6 @@ __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) */ __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) { - // __ASM volatile("MCR p15, 0, %0, c14, c0, 0" : : "r"(value) : "memory"); __set_CP(15, 0, value, 14, 0, 0); } @@ -287,7 +271,6 @@ __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) { uint32_t result; - // __ASM volatile("MRC p15, 0, %0, c14, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 14, 0 , 0); return result; } @@ -300,7 +283,6 @@ __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) */ __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) { - // __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory"); __set_CP(15, 0, value, 14, 2, 0); } @@ -313,11 +295,47 @@ __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) { uint32_t result; - // __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 14, 2, 0); return result; } +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + /** \brief Set CNTP_CTL This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). @@ -326,7 +344,6 @@ __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) */ __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) { - // __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory"); __set_CP(15, 0, value, 14, 2, 1); } @@ -336,7 +353,6 @@ __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) { uint32_t result; - // __ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result) : : "memory"); __get_CP(15, 0, result, 14, 2, 1); return result; } @@ -349,7 +365,6 @@ __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) */ __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) { -// __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory"); __set_CP(15, 0, value, 8, 7, 0); } @@ -359,7 +374,6 @@ __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) */ __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) { -// __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory"); __set_CP(15, 0, value, 7, 5, 6); } @@ -369,7 +383,6 @@ __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) */ __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) { -// __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory"); __set_CP(15, 0, value, 7, 5, 0); } @@ -379,7 +392,6 @@ __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) */ __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) { -// __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory"); __set_CP(15, 0, value, 7, 10, 1); } @@ -389,7 +401,6 @@ __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) */ __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) { -// __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory"); __set_CP(15, 0, value, 7, 6, 1); } @@ -399,7 +410,6 @@ __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) */ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) { -// __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory"); __set_CP(15, 0, value, 7, 14, 1); } @@ -434,4 +444,28 @@ __STATIC_FORCEINLINE uint32_t __get_CLIDR(void) return result; } +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + #endif diff --git a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h index 45b6129456f..7f42293beeb 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h @@ -43,17 +43,20 @@ #ifndef __INLINE #define __INLINE inline #endif -#ifndef __FORCEINLINE +#ifndef __FORCEINLINE #define __FORCEINLINE __attribute__((always_inline)) -#endif +#endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __USED #define __USED __attribute__((used)) @@ -157,7 +160,7 @@ __STATIC_FORCEINLINE void __DMB(void) /** \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ @@ -169,12 +172,13 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; #endif } /** \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ @@ -188,20 +192,20 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_ #endif /** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ -__STATIC_FORCEINLINE int32_t __REVSH(int32_t value) +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); + return (int16_t)__builtin_bswap16(value); #else - int32_t result; + int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; #endif } @@ -214,9 +218,14 @@ __STATIC_FORCEINLINE int32_t __REVSH(int32_t value) */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { + op2 %= 32U; + if (op2 == 0U) { + return op1; + } return (op1 >> op2) | (op1 << (32U - op2)); } + /** \brief Breakpoint \param [in] value is ignored by the processor. @@ -239,7 +248,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) @@ -250,7 +259,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) } result <<= s; /* shift when v's highest bits are zero */ #endif - return(result); + return result; } /** @@ -258,7 +267,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __builtin_clz +#define __CLZ (uint8_t)__builtin_clz /** \brief LDR Exclusive (8 bit) @@ -496,14 +505,16 @@ __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); /** \brief Get Mode \return Processor Mode */ -__STATIC_FORCEINLINE uint32_t __get_mode(void) { +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ -__STATIC_FORCEINLINE void __set_mode(uint32_t mode) { +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } @@ -585,108 +596,35 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" -__STATIC_FORCEINLINE int32_t log2_up(uint32_t n) -{ - int32_t log = -1; - uint32_t t = n; - while(t) - { - log++; t >>=1; - } - /* if n not power of 2 -> round up*/ - if ( n & (n - 1) ) log++; - return log; -} - -__STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) -{ - register volatile uint32_t Dummy; - register volatile uint32_t ccsidr; - uint32_t num_sets; - uint32_t num_ways; - uint32_t shift_way; - uint32_t log2_linesize; - uint32_t log2_num_ways; - - Dummy = level << 1; - /* set csselr, select ccsidr register */ - __set_CCSIDR(Dummy); - /* get current ccsidr register */ - ccsidr = __get_CCSIDR(); - num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1; - num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1; - log2_linesize = (ccsidr & 0x00000007) + 2 + 2; - log2_num_ways = log2_up(num_ways); - shift_way = 32 - log2_num_ways; - for(int way = num_ways-1; way >= 0; way--) { - for(int set = num_sets-1; set >= 0; set--) { - Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way); - switch (maint) - { - case 0: - __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(Dummy) : "memory"); // DCISW. Invalidate by Set/Way - break; - - case 1: - __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(Dummy) : "memory"); // DCCSW. Clean by Set/Way - break; - - default: - __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(Dummy) : "memory"); // DCCISW. Clean and Invalidate by Set/Way - break; - - } - } - } - __DMB(); -} - -/** \brief Clean and Invalidate the entire data or unified cache - - Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency - */ -__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) { - register volatile uint32_t clidr; - uint32_t cache_type; - clidr = __get_CLIDR(); - for(uint32_t i = 0; i<7; i++) - { - cache_type = (clidr >> i*3) & 0x7UL; - if ((cache_type >= 2) && (cache_type <= 4)) - { - __L1C_MaintainDCacheSetWay(i, op); - } - } - -} - /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled */ -__STATIC_INLINE void __FPU_Enable(void) { +__STATIC_INLINE void __FPU_Enable(void) +{ __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR + //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" - //Enable VFP/NEON + //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" - //Initialise VFP/NEON registers to 0 + //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" -#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16 - //Initialise D16 registers to 0 + //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" @@ -703,10 +641,9 @@ __STATIC_INLINE void __FPU_Enable(void) { " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" -#endif -#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 - //Initialise D32 registers to 0 +#if __ARM_NEON == 1 + //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" @@ -724,7 +661,8 @@ __STATIC_INLINE void __FPU_Enable(void) { " VMOV D30,R2,R2 \n" " VMOV D31,R2,R2 \n" #endif - //Initialise FPSCR to a known state + + //Initialise FPSCR to a known state " VMRS R2,FPSCR \n" " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R2,R2,R3 \n" diff --git a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h index 18e6e6acfb0..beddfe8162d 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR compiler) header file - * @version V5.0.3 - * @date 29. August 2017 + * @version V5.0.4 + * @date 01. December 2017 ******************************************************************************/ //------------------------------------------------------------------------------ @@ -74,7 +74,11 @@ #endif #ifndef __NO_RETURN - #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif #endif #ifndef __PACKED @@ -105,25 +109,30 @@ #endif #ifndef __RESTRICT - #define __RESTRICT restrict + #define __RESTRICT restrict #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE _Pragma("inline=forced") static inline + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended - __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { return *(__packed uint16_t*)(ptr); } #pragma language=restore @@ -134,7 +143,8 @@ #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended - __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore @@ -144,7 +154,8 @@ #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended - __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { return *(__packed uint32_t*)(ptr); } #pragma language=restore @@ -154,7 +165,8 @@ #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended - __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore @@ -212,12 +224,12 @@ #include "iccarm_builtin.h" - #define __enable_irq __iar_builtin_enable_interrupt - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr #if __FPU_PRESENT #define __get_FPSCR() (__arm_rsr("FPSCR")) @@ -234,28 +246,31 @@ #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) - #define __get_FPEXC() (__arm_rsr("FPEXC")) - #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ - (RT = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ - (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, RT)) + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) - #include "cmsis_cp15.h" + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) - #define __NOP __iar_builtin_no_operation + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - __IAR_FT uint8_t __CLZ(uint32_t val) { - return __iar_builtin_CLZ(val); - } + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation - #define __CLREX __iar_builtin_CLREX + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH @@ -265,8 +280,9 @@ #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 - __IAR_FT int32_t __REVSH(int32_t val) { - return __iar_builtin_REVSH((int16_t)val); + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR @@ -354,6 +370,10 @@ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #endif + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + #include #if !__FPU_PRESENT @@ -363,36 +383,40 @@ #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - #define __NOP __no_operation + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation - #define __get_xPSR __get_PSR + #define __get_xPSR __get_PSR __IAR_FT void __set_mode(uint32_t mode) { __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { return __LDREX((unsigned long *)ptr); } - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { return __STREX(value, (unsigned long *)ptr); } - __IAR_FT uint32_t __RRX(uint32_t value) { + __IAR_FT uint32_t __RRX(uint32_t value) + { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } @@ -418,7 +442,11 @@ #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ - __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" @@ -455,86 +483,27 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack) #define __get_mode() (__get_CPSR() & 0x1FU) - -__STATIC_INLINE -void __L1C_CleanInvalidateCache(uint32_t op) -{ - __ASM volatile( - " PUSH {R4-R11} \n" - - " MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR - " ANDS R3, R6, #0x07000000 \n" // Extract coherency level - " MOV R3, R3, LSR #23 \n" // Total cache levels << 1 - " BEQ Finished \n" // If 0, no need to clean - - " MOV R10, #0 \n" // R10 holds current cache level << 1 - "Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position - " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level - " AND R1, R1, #7 \n" // Isolate those lower 3 bits - " CMP R1, #2 \n" - " BLT Skip \n" // No cache or only instruction cache at this level - - " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register - " ISB \n" // ISB to sync the change to the CacheSizeID reg - " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register - " AND R2, R1, #7 \n" // Extract the line length field - " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes) - " MOVW R4, #0x3FF \n" - " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned) - " CLZ R5, R4 \n" // R5 is the bit position of the way size increment - " MOVW R7, #0x7FFF \n" - " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned) - - "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned) - - "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11 - " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number - " CMP R0, #0 \n" - " BNE Dccsw \n" - " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way - " B cont \n" - "Dccsw: CMP R0, #1 \n" - " BNE Dccisw \n" - " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way - " B cont \n" - "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way - "cont: SUBS R9, R9, #1 \n" // Decrement the Way number - " BGE Loop3 \n" - " SUBS R7, R7, #1 \n" // Decrement the Set number - " BGE Loop2 \n" - "Skip: ADD R10, R10, #2 \n" // Increment the cache number - " CMP R3, R10 \n" - " BGT Loop1 \n" - - "Finished: \n" - " DSB \n" - " POP {R4-R11} " - ); -} - - __STATIC_INLINE void __FPU_Enable(void) { __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR + //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" - //Enable VFP/NEON + //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" - //Initialise VFP/NEON registers to 0 + //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" -#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16 - //Initialise D16 registers to 0 + //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" @@ -551,10 +520,9 @@ void __FPU_Enable(void) " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" -#endif -#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 - //Initialise D32 registers to 0 +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" @@ -571,12 +539,12 @@ void __FPU_Enable(void) " VMOV D29,R2,R2 \n" " VMOV D30,R2,R2 \n" " VMOV D31,R2,R2 \n" - ".endif \n" #endif - //Initialise FPSCR to a known state + + //Initialise FPSCR to a known state " VMRS R2,FPSCR \n" " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R2,R2,R3 \n" + " AND R2,R2,R3 \n" " VMSR FPSCR,R2 \n"); } diff --git a/cmsis/TARGET_CORTEX_A/core_ca.h b/cmsis/TARGET_CORTEX_A/core_ca.h index 1792dc35db7..4757a04f93e 100644 --- a/cmsis/TARGET_CORTEX_A/core_ca.h +++ b/cmsis/TARGET_CORTEX_A/core_ca.h @@ -22,8 +22,10 @@ * limitations under the License. */ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ #endif #ifdef __cplusplus @@ -40,7 +42,7 @@ /* CMSIS CA definitions */ #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ -#define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ @@ -505,9 +507,9 @@ typedef union uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ - uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ - uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ - uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ RESERVED(0:1, uint32_t) uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ @@ -539,7 +541,7 @@ typedef union uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ RESERVED(0:1, uint32_t) - uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ @@ -550,7 +552,7 @@ typedef union { uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ RESERVED(0:3, uint32_t) - uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ RESERVED(1:1, uint32_t) uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ @@ -846,35 +848,35 @@ typedef struct /** \brief Enable Caches by setting I and C bits in SCTLR register. */ -__STATIC_INLINE void L1C_EnableCaches(void) { - __set_SCTLR( __get_SCTLR() | (1U << SCTLR_I_Pos) | (1U << SCTLR_C_Pos)); +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); __ISB(); } /** \brief Disable Caches by clearing I and C bits in SCTLR register. */ -__STATIC_INLINE void L1C_DisableCaches(void) { - __set_SCTLR( __get_SCTLR() & ~(1U << SCTLR_I_Pos) & ~(1U << SCTLR_C_Pos)); +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); __ISB(); } /** \brief Enable Branch Prediction by setting Z bit in SCTLR register. */ -__STATIC_INLINE void L1C_EnableBTAC(void) { - __set_SCTLR( __get_SCTLR() | (1U << SCTLR_Z_Pos)); +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); __ISB(); } /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. */ -__STATIC_INLINE void L1C_DisableBTAC(void) { - __set_SCTLR( __get_SCTLR() & ~(1U << SCTLR_Z_Pos)); +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); __ISB(); } /** \brief Invalidate entire branch predictor array */ -__STATIC_INLINE void L1C_InvalidateBTAC(void) { +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { __set_BPIALL(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new state @@ -882,7 +884,7 @@ __STATIC_INLINE void L1C_InvalidateBTAC(void) { /** \brief Invalidate the whole instruction cache */ -__STATIC_INLINE void L1C_InvalidateICacheAll(void) { +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { __set_ICIALLU(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new I cache state @@ -891,7 +893,7 @@ __STATIC_INLINE void L1C_InvalidateICacheAll(void) { /** \brief Clean data cache line by address. * \param [in] va Pointer to data to clear the cache for. */ -__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) { +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { __set_DCCMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } @@ -899,7 +901,7 @@ __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) { /** \brief Invalidate data cache line by address. * \param [in] va Pointer to data to invalidate the cache for. */ -__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) { +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { __set_DCIMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } @@ -907,38 +909,130 @@ __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) { /** \brief Clean and Invalidate data cache by address. * \param [in] va Pointer to data to invalidate the cache for. */ -__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) { +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { __set_DCCIMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + register volatile uint32_t Dummy; + register volatile uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CCSIDR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + /** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean -* \see __L1C_CleanInvalidateCache */ -__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) { - __L1C_CleanInvalidateCache(op); +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + register volatile uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); } /** \brief Invalidate the whole data cache. */ -__STATIC_INLINE void L1C_InvalidateDCacheAll(void) { +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { L1C_CleanInvalidateCache(0); } /** \brief Clean the whole data cache. */ -__STATIC_INLINE void L1C_CleanDCacheAll(void) { +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { L1C_CleanInvalidateCache(1); } /** \brief Clean and invalidate the whole data cache. */ -__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) { +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { L1C_CleanInvalidateCache(2); } - /* ########################## L2 Cache functions ################################# */ #if (__L2C_PRESENT == 1U) || defined(DOXYGEN) /** \brief Cache Sync operation by writing CACHE_SYNC register. @@ -1354,8 +1448,8 @@ __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) */ __STATIC_INLINE void GIC_DistInit(void) { - IRQn_Type i; - uint32_t num_irq = 0; + uint32_t i; + uint32_t num_irq = 0U; uint32_t priority_field; //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, @@ -1364,26 +1458,24 @@ __STATIC_INLINE void GIC_DistInit(void) //Disable interrupt forwarding GIC_DisableDistributor(); //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); /* Priority level is implementation defined. To determine the number of priority bits implemented write 0xFF to an IPRIORITYR priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); - for (i = (IRQn_Type)32; i < num_irq; i++) + for (i = 32U; i < num_irq; i++) { //Disable the SPI interrupt - GIC_DisableIRQ(i); - if (i > 15) { - //Set level-sensitive (and N-N model) - GIC_SetConfiguration(i, 0); - } + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); //Set priority - GIC_SetPriority(i, priority_field/2); + GIC_SetPriority((IRQn_Type)i, priority_field/2U); //Set target list to CPU0 - GIC_SetTarget(i, 1); + GIC_SetTarget((IRQn_Type)i, 1U); } //Enable distributor GIC_EnableDistributor(); @@ -1393,7 +1485,7 @@ __STATIC_INLINE void GIC_DistInit(void) */ __STATIC_INLINE void GIC_CPUInterfaceInit(void) { - IRQn_Type i; + uint32_t i; uint32_t priority_field; //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, @@ -1405,27 +1497,27 @@ __STATIC_INLINE void GIC_CPUInterfaceInit(void) /* Priority level is implementation defined. To determine the number of priority bits implemented write 0xFF to an IPRIORITYR priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); //SGI and PPI - for (i = (IRQn_Type)0; i < 32; i++) + for (i = 0U; i < 32U; i++) { - if(i > 15) { + if(i > 15U) { //Set level-sensitive (and N-N model) for PPI - GIC_SetConfiguration(i, 0U); + GIC_SetConfiguration((IRQn_Type)i, 0U); } //Disable SGI and PPI interrupts - GIC_DisableIRQ(i); + GIC_DisableIRQ((IRQn_Type)i); //Set priority - GIC_SetPriority(i, priority_field/2); + GIC_SetPriority((IRQn_Type)i, priority_field/2U); } //Enable interface GIC_EnableInterface(); //Set binary point to 0 - GIC_SetBinaryPoint(0); + GIC_SetBinaryPoint(0U); //Set priority mask - GIC_SetInterfacePriorityMask(0xff); + GIC_SetInterfacePriorityMask(0xFFU); } /** \brief Initialize and enable the GIC @@ -1477,11 +1569,36 @@ __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) /** \brief Get the current counter value. * \return Current counter value. */ -__STATIC_INLINE uint32_t PL1_GetCurrentValue() +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) { return(__get_CNTP_TVAL()); } +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + /** \brief Configure the timer by setting the control value. * \param [in] value New timer control value. */ @@ -1494,7 +1611,7 @@ __STATIC_INLINE void PL1_SetControl(uint32_t value) /** \brief Get the control value. * \return Control value. */ -__STATIC_INLINE uint32_t PL1_GetControl() +__STATIC_INLINE uint32_t PL1_GetControl(void) { return(__get_CNTP_CTL()); } @@ -1763,6 +1880,21 @@ typedef struct RegionStruct { region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ diff --git a/doxyfile_options b/doxyfile_options index 3018654640f..c97e13de78d 100644 --- a/doxyfile_options +++ b/doxyfile_options @@ -841,10 +841,15 @@ EXCLUDE_PATTERNS = */tools/* \ */BUILD/* \ */rtos/TARGET_CORTEX/rtx* \ */cmsis/* \ - */FEATURE_* \ */features/mbedtls/* \ */features/storage/* \ */features/unsupported/* \ + */features/FEATURE_COMMON_PAL/* \ + */features/FEATURE_LWIP/* \ + */features/FEATURE_UVISOR/* \ + */features/nanostack/* \ + */ble/generic/* \ + */ble/pal/* # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the @@ -2081,7 +2086,8 @@ PREDEFINED = DOXYGEN_ONLY \ DEVICE_SPISLAVE \ DEVICE_STORAGE \ "MBED_DEPRECATED_SINCE(d, m)=" \ - "MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=" + "MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=" \ + "MBED_DEPRECATED(s)=" # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this # tag can be used to specify a list of macro names that should be expanded. The diff --git a/doxygen_options.json b/doxygen_options.json index ed187aca800..eed31ad6cb2 100644 --- a/doxygen_options.json +++ b/doxygen_options.json @@ -6,8 +6,8 @@ "SEARCH_INCLUDES": "YES", "INCLUDE_PATH": "", "INCLUDE_FILE_PATTERNS": "", - "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"", + "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\" \"MBED_DEPRECATED(s)=\"", "EXPAND_AS_DEFINED": "", "SKIP_FUNCTION_MACROS": "NO", - "EXCLUDE_PATTERNS": "*/tools/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURES_*" + "EXCLUDE_PATTERNS": "*/tools/* */targets/* */features/mbedtls/* */features/storage/* */features/unsupported/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURE_COMMON_PAL/* */features/FEATURE_LWIP/* */features/FEATURE_UVISOR/* */features/nanostack/* */ble/generic/* */ble/pal/*" } diff --git a/drivers/I2C.cpp b/drivers/I2C.cpp index 31d8532b40e..c912e3f9e52 100644 --- a/drivers/I2C.cpp +++ b/drivers/I2C.cpp @@ -28,9 +28,10 @@ SingletonPtr I2C::_mutex; I2C::I2C(PinName sda, PinName scl) : #if DEVICE_I2C_ASYNCH - _irq(this), _usage(DMA_USAGE_NEVER), + _irq(this), _usage(DMA_USAGE_NEVER), _deep_sleep_locked(false), #endif - _i2c(), _hz(100000) { + _i2c(), _hz(100000) +{ // No lock needed in the constructor // The init function also set the frequency to 100000 @@ -133,7 +134,7 @@ int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_bu unlock(); return -1; // transaction ongoing } - sleep_manager_lock_deep_sleep(); + lock_deep_sleep(); aquire(); _callback = callback; @@ -148,7 +149,7 @@ void I2C::abort_transfer(void) { lock(); i2c_abort_asynch(&_i2c); - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); unlock(); } @@ -159,11 +160,26 @@ void I2C::irq_handler_asynch(void) _callback.call(event); } if (event) { - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); } } +void I2C::lock_deep_sleep() +{ + if (_deep_sleep_locked == false) { + sleep_manager_lock_deep_sleep(); + _deep_sleep_locked = true; + } +} + +void I2C::unlock_deep_sleep() +{ + if (_deep_sleep_locked == true) { + sleep_manager_unlock_deep_sleep(); + _deep_sleep_locked = false; + } +} #endif diff --git a/drivers/I2C.h b/drivers/I2C.h index b4fbc2f0937..920a506eb75 100644 --- a/drivers/I2C.h +++ b/drivers/I2C.h @@ -176,11 +176,19 @@ class I2C : private NonCopyable { /** Abort the on-going I2C transfer */ void abort_transfer(); -protected: + + protected: + /** Lock deep sleep only if it is not yet locked */ + void lock_deep_sleep(); + + /** Unlock deep sleep only if it has been locked */ + void unlock_deep_sleep(); + void irq_handler_asynch(void); event_callback_t _callback; CThunk _irq; DMAUsage _usage; + bool _deep_sleep_locked; #endif protected: diff --git a/drivers/SPI.cpp b/drivers/SPI.cpp index 9b2209b0fec..e21922b2581 100644 --- a/drivers/SPI.cpp +++ b/drivers/SPI.cpp @@ -33,6 +33,7 @@ SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) : #if DEVICE_SPI_ASYNCH _irq(this), _usage(DMA_USAGE_NEVER), + _deep_sleep_locked(false), #endif _bits(8), _mode(0), @@ -140,7 +141,7 @@ int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_ void SPI::abort_transfer() { spi_abort_asynch(&_spi); - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); #if TRANSACTION_QUEUE_SIZE_SPI dequeue_transaction(); #endif @@ -200,13 +201,29 @@ int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, i void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event) { - sleep_manager_lock_deep_sleep(); + lock_deep_sleep(); _acquire(); _callback = callback; _irq.callback(&SPI::irq_handler_asynch); spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage); } +void SPI::lock_deep_sleep() +{ + if (_deep_sleep_locked == false) { + sleep_manager_lock_deep_sleep(); + _deep_sleep_locked = true; + } +} + +void SPI::unlock_deep_sleep() +{ + if (_deep_sleep_locked == true) { + sleep_manager_unlock_deep_sleep(); + _deep_sleep_locked = false; + } +} + #if TRANSACTION_QUEUE_SIZE_SPI void SPI::start_transaction(transaction_t *data) @@ -230,7 +247,7 @@ void SPI::irq_handler_asynch(void) { int event = spi_irq_handler_asynch(&_spi); if (_callback && (event & SPI_EVENT_ALL)) { - sleep_manager_unlock_deep_sleep(); + unlock_deep_sleep(); _callback.call(event & SPI_EVENT_ALL); } #if TRANSACTION_QUEUE_SIZE_SPI diff --git a/drivers/SPI.h b/drivers/SPI.h index e312dcc7b3d..af102dc07c6 100644 --- a/drivers/SPI.h +++ b/drivers/SPI.h @@ -246,6 +246,14 @@ class SPI : private NonCopyable { */ void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event); +private: + /** Lock deep sleep only if it is not yet locked */ + void lock_deep_sleep(); + + /** Unlock deep sleep in case it is locked */ + void unlock_deep_sleep(); + + #if TRANSACTION_QUEUE_SIZE_SPI /** Start a new transaction @@ -274,6 +282,7 @@ class SPI : private NonCopyable { CThunk _irq; event_callback_t _callback; DMAUsage _usage; + bool _deep_sleep_locked; #endif void aquire(void); diff --git a/features/FEATURE_BLE/ble/BLE.h b/features/FEATURE_BLE/ble/BLE.h index 0aea37dc32c..20eedb4e080 100644 --- a/features/FEATURE_BLE/ble/BLE.h +++ b/features/FEATURE_BLE/ble/BLE.h @@ -280,7 +280,7 @@ class BLE * function-pointer, init() can also take an pair as its * callback target. * - * @important This should be called before using anything else in the BLE + * @attention This should be called before using anything else in the BLE * API. */ ble_error_t init(InitializationCompleteCallback_t completion_cb = NULL) { @@ -321,7 +321,7 @@ class BLE * @return BLE_ERROR_NONE if the instance was shut down without error or the * appropriate error code. * - * @important init() must be called afterward to reinstate services and + * @attention init() must be called afterward to reinstate services and * GAP state. This API offers a way to repopulate the GATT database with new * services and characteristics. */ @@ -400,6 +400,15 @@ class BLE */ const SecurityManager& securityManager() const; + /** + * Translate error code into a printable string. + * + * @param[in] error Error code returned by BLE functions. + * + * @return A pointer to a const string describing the error. + */ + static const char* errorToString(ble_error_t error); + /* * Deprecation alert! * All of the following are deprecated and may be dropped in a future diff --git a/features/FEATURE_BLE/ble/BLEInstanceBase.h b/features/FEATURE_BLE/ble/BLEInstanceBase.h index 18eb0264845..d7ff34cb71a 100644 --- a/features/FEATURE_BLE/ble/BLEInstanceBase.h +++ b/features/FEATURE_BLE/ble/BLEInstanceBase.h @@ -46,7 +46,7 @@ class GattClient; * createBLEInstance(). The BLE API uses this singleton function to gain * access to a concrete implementation of this class defined in the vendor port. * - * @important This class is part of the porting API and is not meant to be used + * @attention This class is part of the porting API and is not meant to be used * by end users of BLE API. * * @see BLE @@ -237,7 +237,7 @@ class BLEInstanceBase * Process pending events present in the vendor subsystem; then, put the MCU * to sleep until an external source wakes it up. * - * @important This function is deprecated in the BLE class. It will be + * @attention This function is deprecated in the BLE class. It will be * removed from this interface once it is removed from BLE. * * @see BLE::waitForEvent() BLE::processEvents() @@ -254,10 +254,10 @@ class BLEInstanceBase /** * Return the instance of the vendor implementation of BLEInstanceBase. * - * @important Contrary to its name, this function does not return a new instance + * @attention Contrary to its name, this function does not return a new instance * at each call. It rather acts like an accessor to a singleton. * - * @important The vendor library must provide an implementation for this function + * @attention The vendor library must provide an implementation for this function * library. Otherwise, there will be a linker error. */ extern BLEInstanceBase *createBLEInstance(void); diff --git a/features/FEATURE_BLE/ble/DiscoveredService.h b/features/FEATURE_BLE/ble/DiscoveredService.h index cfa97e9039f..867c286eb06 100644 --- a/features/FEATURE_BLE/ble/DiscoveredService.h +++ b/features/FEATURE_BLE/ble/DiscoveredService.h @@ -84,7 +84,7 @@ class DiscoveredService { /** * Construct a DiscoveredService instance. * - * @important This API is not meant to be used publicly. It is meant to be + * @attention This API is not meant to be used publicly. It is meant to be * used by internal APIs of Mbed BLE. */ DiscoveredService() : @@ -96,7 +96,7 @@ class DiscoveredService { /** * Set information about the discovered service. * - * @important This API is not meant to be used publicly. It is meant to be + * @attention This API is not meant to be used publicly. It is meant to be * used by internal APIs of Mbed BLE. * * @param[in] uuidIn The UUID of the discovered service. @@ -118,7 +118,7 @@ class DiscoveredService { /** * Set the start and end handle of the discovered service. * - * @important This API is not meant to be used publicly. It is meant to be + * @attention This API is not meant to be used publicly. It is meant to be * used by internal APIs of Mbed BLE. * * @param[in] startHandleIn The start handle of the discovered service in @@ -137,7 +137,7 @@ class DiscoveredService { /** * Set the long UUID of the discovered service. * - * @important This API is not meant to be used publicly. It is meant to be + * @attention This API is not meant to be used publicly. It is meant to be * used by internal APIs of Mbed BLE. * * @param[in] longUUID The bytes composing the long UUID of this discovered diff --git a/features/FEATURE_BLE/ble/FunctionPointerWithContext.h b/features/FEATURE_BLE/ble/FunctionPointerWithContext.h index 1a38a987e86..83507b7715e 100644 --- a/features/FEATURE_BLE/ble/FunctionPointerWithContext.h +++ b/features/FEATURE_BLE/ble/FunctionPointerWithContext.h @@ -46,7 +46,7 @@ * This class also offers a mechanism to chain other instances to it. When an * instance is called, all the instances being part of the chain are called. * - * @important freestanding or member function adapted must accept a single + * @attention freestanding or member function adapted must accept a single * argument, and this argument is a pointer to ContextType. Adapted * primitives do not return anything. * @@ -77,7 +77,7 @@ class FunctionPointerWithContext : public SafeBool FunctionPointerWithContext(T *object, void (T::*member)(ContextType context)) : @@ -136,7 +136,7 @@ class FunctionPointerWithContext : public SafeBool void attach(T *object, void (T::*member)(ContextType context)) diff --git a/features/FEATURE_BLE/ble/Gap.h b/features/FEATURE_BLE/ble/Gap.h index fb13050d91d..f9b5bdbe34d 100644 --- a/features/FEATURE_BLE/ble/Gap.h +++ b/features/FEATURE_BLE/ble/Gap.h @@ -347,7 +347,7 @@ class Gap { /** * Enumeration of disconnection reasons. * - * @important There might be a mismatch between the disconnection reason + * @attention There might be a mismatch between the disconnection reason * passed to disconnect() and the disconnection event generated locally * because the disconnection reason passed to disconnect() is the * disconnection reason to be transmitted to the peer. @@ -356,7 +356,7 @@ class Gap { /** * The connection timed out. * - * @important shall not be used as a reason in disconnect(). + * @attention shall not be used as a reason in disconnect(). */ CONNECTION_TIMEOUT = 0x08, @@ -379,7 +379,7 @@ class Gap { * Indicate that the local user or the internal * Bluetooth subsystem terminated the connection. * - * @important shall not be used as a reason in disconnect(). + * @attention shall not be used as a reason in disconnect(). */ LOCAL_HOST_TERMINATED_CONNECTION = 0x16, @@ -548,7 +548,7 @@ class Gap { * * @note The BLE API does not express the broadcaster and scanner roles. * - * @important A device can fulfill different roles concurrently. + * @attention A device can fulfill different roles concurrently. */ enum Role_t { /** @@ -1147,7 +1147,7 @@ class Gap { * invoked with the @p deviceName parameter set to NULL. * * @param[out] deviceName Pointer to an empty buffer where the UTF-8 - * non NULL-terminated string is placed. + * non NULL-terminated string is placed. * * @param[in,out] lengthP Length of the @p deviceName buffer. If the device * name is successfully copied, then the length of the device name @@ -1192,7 +1192,7 @@ class Gap { /** * Get the value of the appearance characteristic in the GAP service. * - * @param[out] appearance The current device-appearance value. + * @param[out] appearanceP The current device-appearance value. * * @return BLE_ERROR_NONE if the device-appearance was fetched correctly * from the underlying BLE stack. @@ -1265,8 +1265,6 @@ class Gap { * * @return BLE_ERROR_NONE if the implementation's whitelist was successfully * copied into the supplied reference. - * - * @experimental */ virtual ble_error_t getWhitelist(Whitelist_t &whitelist) const { @@ -1284,7 +1282,7 @@ class Gap { * populated with the addresses in the given whitelist. * * @note The whitelist must not contain addresses of type @ref - * BLEProtocol::AddressType_t::RANDOM_PRIVATE_NON_RESOLVABLE. This + * BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE. This * results in a @ref BLE_ERROR_INVALID_PARAM because the remote peer might * change its private address at any time, and it is not possible to resolve * it. @@ -1971,14 +1969,14 @@ class Gap { /** * Start the advertising procedure. * - * @param[in] Advertising parameters to use. + * @param[in] params Advertising parameters to use. * * @return BLE_ERROR_NONE if the advertising procedure successfully * started. * * @note Must be implemented in vendor port. */ - virtual ble_error_t startAdvertising(const GapAdvertisingParams &) = 0; + virtual ble_error_t startAdvertising(const GapAdvertisingParams ¶ms) = 0; public: /** @@ -2271,7 +2269,7 @@ class Gap { /** * Notify all registered connection event handlers of a connection event. * - * @important This function is meant to be called from the BLE stack specific + * @attention This function is meant to be called from the BLE stack specific * implementation when a connection event occurs. * * @param[in] handle Handle of the new connection. @@ -2312,7 +2310,7 @@ class Gap { /** * Notify all registered disconnection event handlers of a disconnection event. * - * @important This function is meant to be called from the BLE stack specific + * @attention This function is meant to be called from the BLE stack specific * implementation when a disconnection event occurs. * * @param[in] handle Handle of the terminated connection. @@ -2334,12 +2332,12 @@ class Gap { * Forward a received advertising packet to all registered event handlers * listening for scanned packet events. * - * @important This function is meant to be called from the BLE stack specific + * @attention This function is meant to be called from the BLE stack specific * implementation when a disconnection event occurs. * * @param[in] peerAddr Address of the peer that has emitted the packet. * @param[in] rssi Value of the RSSI measured for the received packet. - * @param[in] isScanReponse If true, then the packet is a response to a scan + * @param[in] isScanResponse If true, then the packet is a response to a scan * request. * @param[in] type Advertising type of the packet. * @param[in] advertisingDataLen Length of the advertisement data received. @@ -2367,7 +2365,7 @@ class Gap { * Notify the occurrence of a timeout event to all registered timeout events * handler. * - * @important This function is meant to be called from the BLE stack specific + * @attention This function is meant to be called from the BLE stack specific * implementation when a disconnection event occurs. * * @param[in] source Source of the timout event. diff --git a/features/FEATURE_BLE/ble/GapEvents.h b/features/FEATURE_BLE/ble/GapEvents.h index 15db125dfbf..7e190dfae5b 100644 --- a/features/FEATURE_BLE/ble/GapEvents.h +++ b/features/FEATURE_BLE/ble/GapEvents.h @@ -19,7 +19,7 @@ #include "blecommon.h" -/// @cond 0 +/// @cond INVALID_SECTIONS /*! \brief diff --git a/features/FEATURE_BLE/ble/GattAttribute.h b/features/FEATURE_BLE/ble/GattAttribute.h index 2423301464d..59bb7285bc1 100644 --- a/features/FEATURE_BLE/ble/GattAttribute.h +++ b/features/FEATURE_BLE/ble/GattAttribute.h @@ -166,7 +166,7 @@ class GattAttribute { /** * Get a pointer to the current length of the attribute value. * - * @important note Do not use this function. + * @attention note Do not use this function. * * @return A pointer to the current length of the attribute value. */ @@ -178,7 +178,7 @@ class GattAttribute { /** * Set the attribute handle. * - * @important The GattServer uses this function internally. + * @attention The GattServer uses this function internally. * Application code must not use it. * * @param[in] id The new attribute handle. diff --git a/features/FEATURE_BLE/ble/GattCallbackParamTypes.h b/features/FEATURE_BLE/ble/GattCallbackParamTypes.h index 50c16ba938c..aa161bb4747 100644 --- a/features/FEATURE_BLE/ble/GattCallbackParamTypes.h +++ b/features/FEATURE_BLE/ble/GattCallbackParamTypes.h @@ -31,11 +31,11 @@ * whether the GattServer has received a write request or a GattClient has * received a write response. * - * @important The GattServer only populates the fields offset, len and data + * @attention The GattServer only populates the fields offset, len and data * when it has received a write request. Callbacks attached to the GattClient * do not use those fields. * - * @important The GattClient only populates the fields status and error_code + * @attention The GattClient only populates the fields status and error_code * when it has received a write response. Callbacks attached to the GattServer * do not use those fields. */ @@ -99,14 +99,14 @@ struct GattWriteCallbackParams { /** * Offset within the attribute value to be written. * - * @important Reserved for GattServer registered callbacks. + * @attention Reserved for GattServer registered callbacks. */ uint16_t offset; /** * Status of the GattClient Write operation. * - * @important Reserved for GattClient registered callbacks. + * @attention Reserved for GattClient registered callbacks. */ ble_error_t status; }; @@ -115,14 +115,14 @@ struct GattWriteCallbackParams { /** * Length (in bytes) of the data to write. * - * @important Reserved for GattServer registered callbacks. + * @attention Reserved for GattServer registered callbacks. */ uint16_t len; /** * Error code of the GattClient Write operation. * - * @important Reserved for GattClient registered callbacks. + * @attention Reserved for GattClient registered callbacks. */ uint8_t error_code; }; @@ -130,9 +130,9 @@ struct GattWriteCallbackParams { /** * Pointer to the data to write. * - * @important Data may not persist beyond the callback scope. + * @attention Data may not persist beyond the callback scope. * - * @important Reserved for GattServer registered callbacks. + * @attention Reserved for GattServer registered callbacks. */ const uint8_t *data; }; @@ -144,7 +144,7 @@ struct GattWriteCallbackParams { * whether the GattServer has received a read request or a GattClient has * received a read response. * - * @important The GattClient only populates the fields status and error_code + * @attention The GattClient only populates the fields status and error_code * when it has received a read response. Callbacks attached to the GattServer * do not use those fields. */ @@ -173,9 +173,9 @@ struct GattReadCallbackParams { /** * Error code of the GattClient read operation. * - * @important Reserved for GattClient registered callbacks. + * @attention Reserved for GattClient registered callbacks. * - * @important set if status is not equal to BLE_ERROR_NONE; otherwise, + * @attention set if status is not equal to BLE_ERROR_NONE; otherwise, * this field is interpreted as len. */ uint8_t error_code; @@ -184,14 +184,14 @@ struct GattReadCallbackParams { /** * Pointer to the data read. * - * @important Data may not persist beyond the callback scope. + * @attention Data may not persist beyond the callback scope. */ const uint8_t *data; /** * Status of the GattClient Read operation. * - * @important Reserved for GattClient registered callbacks. + * @attention Reserved for GattClient registered callbacks. */ ble_error_t status; }; diff --git a/features/FEATURE_BLE/ble/GattCharacteristic.h b/features/FEATURE_BLE/ble/GattCharacteristic.h index 9f0a246b2ec..671665f4e50 100644 --- a/features/FEATURE_BLE/ble/GattCharacteristic.h +++ b/features/FEATURE_BLE/ble/GattCharacteristic.h @@ -1357,7 +1357,7 @@ class GattCharacteristic { * be allocated if either the notify or indicate flag in the @p props bit * field; the underlying BLE stack handles it. * - * @important GattCharacteristic registered in a GattServer must remain + * @attention GattCharacteristic registered in a GattServer must remain * valid for the lifetime of the GattServer. */ GattCharacteristic( @@ -1476,7 +1476,7 @@ class GattCharacteristic { * This function is a helper that calls the registered write handler to * determine the authorization reply for a write request. * - * @important This function is not meant to be called by user code. + * @attention This function is not meant to be called by user code. * * @param[in] params Context of the write-auth request; it contains an * out-parameter used as a reply. @@ -1502,7 +1502,7 @@ class GattCharacteristic { * This function is a helper that calls the registered read handler to * determine the authorization reply for a read request. * - * @important This function is not meant to be called by user code. + * @attention This function is not meant to be called by user code. * * @param[in] params Context of the read-auth request; it contains an * out-parameter used as a reply and the handler can fill it with outgoing diff --git a/features/FEATURE_BLE/ble/GattClient.h b/features/FEATURE_BLE/ble/GattClient.h index 9dcbd2a4f5b..137304bc236 100644 --- a/features/FEATURE_BLE/ble/GattClient.h +++ b/features/FEATURE_BLE/ble/GattClient.h @@ -743,7 +743,7 @@ class GattClient { /** * Forward an attribute read event to all registered handlers. * - * @important This function is meant to be called from the vendor + * @attention This function is meant to be called from the vendor * implementation when an attribute read event occurs. * * @param[in] params Attribute read event to pass to the registered handlers. @@ -756,7 +756,7 @@ class GattClient { /** * Forward an attribute written event to all registered handlers. * - * @important This function is meant to be called from the vendor + * @attention This function is meant to be called from the vendor * implementation when an attribute written event occurs. * * @param[in] params Attribute written event to pass to the registered @@ -771,7 +771,7 @@ class GattClient { * Forward a handle value notification or indication event to all registered * handlers. * - * @important This function is meant to be called from the vendor + * @attention This function is meant to be called from the vendor * implementation when a notification or indication event is available. * * @param[in] params Notification or Indication event to pass to the diff --git a/features/FEATURE_BLE/ble/GattServer.h b/features/FEATURE_BLE/ble/GattServer.h index 63e91539bb0..6704e6db58d 100644 --- a/features/FEATURE_BLE/ble/GattServer.h +++ b/features/FEATURE_BLE/ble/GattServer.h @@ -195,7 +195,7 @@ class GattServer { * Application code can remove all the registered services by calling * reset(). * - * @important Service, characteristics and descriptors objects registered + * @attention Service, characteristics and descriptors objects registered * within the GattServer must remain reachable until reset() is called. * * @param[in] service The service to be added; attribute handle of services, @@ -227,7 +227,7 @@ class GattServer { * * @return BLE_ERROR_NONE if a value was read successfully into the buffer. * - * @important read(Gap::Handle_t, GattAttribute::Handle_t, uint8_t *, uint16_t *) + * @attention read(Gap::Handle_t, GattAttribute::Handle_t, uint8_t *, uint16_t *) * must be used to read Client Characteristic Configuration Descriptor (CCCD) * because the value of this type of attribute depends on the connection. */ @@ -409,7 +409,7 @@ class GattServer { * Indicate if the underlying stack emit events when an attribute is read by * a client. * - * @important This function should be overridden to return true if + * @attention This function should be overridden to return true if * applicable. * * @return true if onDataRead is supported; false otherwise. @@ -465,12 +465,12 @@ class GattServer { } /** - * Set an event handler that is called after + * Set an event handler that is called after * a connected peer has written an attribute. * * @param[in] callback The event handler being registered. * - * @important It is possible to set multiple event handlers. Registered + * @attention It is possible to set multiple event handlers. Registered * handlers may be removed with onDataWritten().detach(callback). */ void onDataWritten(const DataWrittenCallback_t &callback) @@ -526,7 +526,7 @@ class GattServer { * @see GattCharacteristic::setReadAuthorizationCallback() * @see isOnDataReadAvailable(). * - * @important It is possible to set multiple event handlers. Registered + * @attention It is possible to set multiple event handlers. Registered * handlers may be removed with onDataRead().detach(callback). */ ble_error_t onDataRead(const DataReadCallback_t &callback) @@ -668,7 +668,7 @@ class GattServer { * Helper function that notifies all registered handlers of an occurrence * of a data written event. * - * @important Vendor implementation must invoke this function after one of + * @attention Vendor implementation must invoke this function after one of * the GattServer attributes has been written. * * @param[in] params The data written parameters passed to the registered @@ -683,7 +683,7 @@ class GattServer { * Helper function that notifies all registered handlers of an occurrence * of a data read event. * - * @important Vendor implementation must invoke this function after one of + * @attention Vendor implementation must invoke this function after one of * the GattServer attributes has been read. * * @param[in] params The data read parameters passed to the registered @@ -698,7 +698,7 @@ class GattServer { * Helper function that notifies the registered handler of an occurrence * of updates enabled, updates disabled or confirmation received events. * - * @important Vendor implementation must invoke this function when a client + * @attention Vendor implementation must invoke this function when a client * subscribes to characteristic updates, unsubscribes from characteristic * updates or a notification confirmation has been received. * @@ -735,7 +735,7 @@ class GattServer { * Helper function that notifies all registered handlers of an occurrence * of a data sent event. * - * @important Vendor implementation must invoke this function after the + * @attention Vendor implementation must invoke this function after the * emission of a notification or an indication. * * @param[in] count Number of packets sent. diff --git a/features/FEATURE_BLE/ble/GattServerEvents.h b/features/FEATURE_BLE/ble/GattServerEvents.h index 00fb68d3419..8aea1e05fb0 100644 --- a/features/FEATURE_BLE/ble/GattServerEvents.h +++ b/features/FEATURE_BLE/ble/GattServerEvents.h @@ -29,7 +29,7 @@ /** * Abstract events generated by a GattServer vendor port. * - * @important This class is not part of the public API. + * @attention This class is not part of the public API. */ class GattServerEvents { diff --git a/features/FEATURE_BLE/ble/GattService.h b/features/FEATURE_BLE/ble/GattService.h index 5918cffb4bb..2148be1dcba 100644 --- a/features/FEATURE_BLE/ble/GattService.h +++ b/features/FEATURE_BLE/ble/GattService.h @@ -143,7 +143,7 @@ class GattService { * belongs to the service. * @param[in] numCharacteristics The number of characteristics. * - * @important The characteristics of the service must remain valid while the + * @attention The characteristics of the service must remain valid while the * GattServer uses the service. */ GattService( @@ -190,7 +190,7 @@ class GattService { /** * Set the handle of the service declaration attribute in the ATT table. * - * @important Application code must not use this API. + * @attention Application code must not use this API. * * @param[in] handle The service's handle. */ diff --git a/features/FEATURE_BLE/ble/SafeBool.h b/features/FEATURE_BLE/ble/SafeBool.h index 9a4836b5633..8b135b5e5fb 100644 --- a/features/FEATURE_BLE/ble/SafeBool.h +++ b/features/FEATURE_BLE/ble/SafeBool.h @@ -124,7 +124,7 @@ class SafeBool : public SafeBool_::base { /** * Avoid conversion to bool between different classes. * - * @important Will generate a compile time error if instantiated. + * @attention Will generate a compile time error if instantiated. */ template void operator==(const SafeBool& lhs,const SafeBool& rhs) @@ -136,7 +136,7 @@ void operator==(const SafeBool& lhs,const SafeBool& rhs) /** * Avoid conversion to bool between different classes. * - * @important Will generate a compile time error if instantiated. + * @attention Will generate a compile time error if instantiated. */ template void operator!=(const SafeBool& lhs,const SafeBool& rhs) diff --git a/features/FEATURE_BLE/ble/SecurityManager.h b/features/FEATURE_BLE/ble/SecurityManager.h index 955d88c8e0a..f2077561d17 100644 --- a/features/FEATURE_BLE/ble/SecurityManager.h +++ b/features/FEATURE_BLE/ble/SecurityManager.h @@ -175,8 +175,6 @@ class SecurityManager { * @retval BLE_ERROR_NONE On success, else an error code indicating reason for failure. * @retval BLE_ERROR_INVALID_STATE If the API is called without module initialization or * application registration. - * - * @experimental */ virtual ble_error_t getAddressesFromBondTable(Gap::Whitelist_t &addresses) const { /* Avoid compiler warnings about unused variables */ diff --git a/features/FEATURE_BLE/ble/ServiceDiscovery.h b/features/FEATURE_BLE/ble/ServiceDiscovery.h index 7712d5e90e2..c2e7512d1f1 100644 --- a/features/FEATURE_BLE/ble/ServiceDiscovery.h +++ b/features/FEATURE_BLE/ble/ServiceDiscovery.h @@ -39,7 +39,7 @@ class DiscoveredCharacteristic; * This class is also an interface that may be used in vendor port to model * the service discovery process. This interface is not used in user code. * - * @important Implementing this interface is not a requirement for the + * @attention Implementing this interface is not a requirement for the * implementation of the service discover process. */ class ServiceDiscovery { @@ -49,7 +49,7 @@ class ServiceDiscovery { * * The callback accepts a pointer to a DiscoveredService as parameter. * - * @important The argument passed to the callback may not persist after the + * @attention The argument passed to the callback may not persist after the * callback invocation; therefore, the callbacks must make a shallow copy * of the DiscoveredService passed as parameter to access its value beyond * the callback scope. @@ -63,7 +63,7 @@ class ServiceDiscovery { * The callback accepts a pointer to a DiscoveredCharacteristic as * parameter. * - * @important The argument passed to the callback may not persist after the + * @attention The argument passed to the callback may not persist after the * callback invocation; therefore, the callbacks must make a shallow copy * of the DiscoveredCharacteristic passed as parameter to access its value * beyond the callback scope. diff --git a/features/FEATURE_BLE/ble/UUID.h b/features/FEATURE_BLE/ble/UUID.h index 6e89f91a9cb..19acda27f57 100644 --- a/features/FEATURE_BLE/ble/UUID.h +++ b/features/FEATURE_BLE/ble/UUID.h @@ -17,6 +17,7 @@ #ifndef MBED_UUID_H__ #define MBED_UUID_H__ +#include #include #include #include @@ -205,7 +206,7 @@ class UUID { * shortened version of the UUID 0000xxxx-0000-1000-8000-00805F9B34FB, where * xxxx is the value of the 16-bit UUID. * - * @important 16-bit UUIDs are not used in user defined data type or + * @attention 16-bit UUIDs are not used in user defined data type or * user defined element ID. * * @param[in] _shortUUID 16-bit part of the standard UUID. @@ -296,7 +297,7 @@ class UUID { /** * Get the uint16_t value of the UUID. * - * @important This function is not used on long UUIDs. + * @attention This function is not used on long UUIDs. * * @return The value of the shortened UUID. */ diff --git a/features/FEATURE_BLE/ble/generic/GenericGap.h b/features/FEATURE_BLE/ble/generic/GenericGap.h new file mode 100644 index 00000000000..b2d392c76c7 --- /dev/null +++ b/features/FEATURE_BLE/ble/generic/GenericGap.h @@ -0,0 +1,296 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_BLE_GENERIC_GAP +#define MBED_BLE_GENERIC_GAP + +#include + +#include "ble/BLE.h" +#include "ble/BLEProtocol.h" +#include "ble/Gap.h" +#include "ble/pal/PalGap.h" +#include "ble/pal/GapEvents.h" +#include "ble/pal/GapTypes.h" +#include "ble/pal/GenericAccessService.h" +#include "ble/pal/EventQueue.h" + +#include "drivers/Timeout.h" + +namespace ble { +namespace generic { + +/** + * Generic implementation of the Gap class. + * It requires a pal::Gap and a pal::GenericAccessService injected at + * construction site. + * + * @attention: Not part of the public interface of BLE API. + */ +class GenericGap : public ::Gap { + +public: + /** + * Construct a GenericGap instance for a given BLE instance ID. + * + * @param ble_instance_id Id of the BLE instance using this instance. + * + * @param pal_gap GAP Platform abstraction instance containing the base GAP + * primitives. + * + * @param generic_access_service Platform abstraction instance managing + * the GATT generic access service. + */ + GenericGap( + pal::EventQueue &event_queue, + pal::Gap &pal_gap, + pal::GenericAccessService &generic_access_service + ); + + /** + * @see Gap::~Gap + */ + virtual ~GenericGap(); + + /** + * @see Gap::setAddress + */ + virtual ble_error_t setAddress( + BLEProtocol::AddressType_t type, + const BLEProtocol::AddressBytes_t address + ); + + /** + * @see Gap::getAddress + */ + virtual ble_error_t getAddress( + BLEProtocol::AddressType_t *type, + BLEProtocol::AddressBytes_t address + ); + + /** + * @see Gap::getMinAdvertisingInterval + */ + virtual uint16_t getMinAdvertisingInterval() const; + + /** + * @see Gap::getMinNonConnectableAdvertisingInterval + */ + virtual uint16_t getMinNonConnectableAdvertisingInterval() const; + + /** + * @see Gap::getMaxAdvertisingInterval + */ + virtual uint16_t getMaxAdvertisingInterval() const; + + /** + * @see Gap::stopAdvertising + */ + virtual ble_error_t stopAdvertising(); + + /** + * @see Gap::stopScan + */ + virtual ble_error_t stopScan(); + + /** + * @see Gap::connect + */ + virtual ble_error_t connect( + const BLEProtocol::AddressBytes_t peerAddr, + BLEProtocol::AddressType_t peerAddrType, + const ConnectionParams_t *connectionParams, + const GapScanningParams *scanParams + ); + + /** + * @see Gap::disconnect + */ + virtual ble_error_t disconnect( + Handle_t connectionHandle, + DisconnectionReason_t reason + ); + + /** + * @see Gap::updateConnectionParams + */ + virtual ble_error_t updateConnectionParams( + Handle_t handle, + const ConnectionParams_t *params + ); + + /** + * @see Gap::getPreferredConnectionParams + */ + virtual ble_error_t getPreferredConnectionParams( + ConnectionParams_t *params + ); + + /** + * @see Gap::setPreferredConnectionParams + */ + virtual ble_error_t setPreferredConnectionParams( + const ConnectionParams_t *params + ); + + /** + * @see Gap::setDeviceName + */ + virtual ble_error_t setDeviceName(const uint8_t *deviceName); + + /** + * @see Gap::getDeviceName + */ + virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP); + + /** + * @see Gap::setAppearance + */ + virtual ble_error_t setAppearance(GapAdvertisingData::Appearance appearance); + + /** + * @see Gap::getAppearance + */ + virtual ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP); + + /** + * @see Gap::setTxPower + */ + virtual ble_error_t setTxPower(int8_t txPower); + + /** + * @see Gap::getPermittedTxPowerValues + */ + virtual void getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP); + + /** + * @see Gap::getMaxWhitelistSize + */ + virtual uint8_t getMaxWhitelistSize(void) const; + + /** + * @see Gap::getWhitelist + */ + virtual ble_error_t getWhitelist(Whitelist_t &whitelist) const; + + /** + * @see Gap::setWhitelist + */ + virtual ble_error_t setWhitelist(const Whitelist_t &whitelist); + + /** + * @see Gap::setAdvertisingPolicyMode + */ + virtual ble_error_t setAdvertisingPolicyMode(AdvertisingPolicyMode_t mode); + + /** + * @see Gap::setScanningPolicyMode + */ + virtual ble_error_t setScanningPolicyMode(ScanningPolicyMode_t mode); + + /** + * @see Gap::setInitiatorPolicyMode + */ + virtual ble_error_t setInitiatorPolicyMode(InitiatorPolicyMode_t mode); + + /** + * @see Gap::getAdvertisingPolicyMode + */ + virtual AdvertisingPolicyMode_t getAdvertisingPolicyMode(void) const; + + /** + * @see Gap::getScanningPolicyMode + */ + virtual ScanningPolicyMode_t getScanningPolicyMode(void) const; + + /** + * @see Gap::getInitiatorPolicyMode + */ + virtual InitiatorPolicyMode_t getInitiatorPolicyMode(void) const; + + /** + * @see Gap::startRadioScan + */ + virtual ble_error_t startRadioScan(const GapScanningParams &scanningParams); + + /** + * @see Gap::initRadioNotification + */ + virtual ble_error_t initRadioNotification(void); + + /** + * @see Gap::setAdvertisingData + */ + virtual ble_error_t setAdvertisingData( + const GapAdvertisingData &advData, + const GapAdvertisingData &scanResponse + ); + + /** + * @see Gap::startAdvertising + */ + virtual ble_error_t startAdvertising(const GapAdvertisingParams ¶ms); + + /** + * @see Gap::reset + */ + virtual ble_error_t reset(void); + +private: + void on_scan_timeout(); + + void process_scan_timeout(); + + void on_advertising_timeout(); + + void process_advertising_timeout(); + + void on_gap_event_received(const pal::GapEvent &e); + + void on_advertising_report(const pal::GapAdvertisingReportEvent &e); + + void on_connection_complete(const pal::GapConnectionCompleteEvent &e); + + void on_disconnection_complete(const pal::GapDisconnectionCompleteEvent &e); + + void on_connection_parameter_request( + const pal::GapRemoteConnectionParameterRequestEvent &e + ); + + void on_connection_update(const pal::GapConnectionUpdateEvent &e); + + void on_unexpected_error(const pal::GapUnexpectedErrorEvent &e); + + pal::own_address_type_t get_own_address_type(); + + bool initialize_whitelist() const; + + pal::EventQueue& _event_queue; + pal::Gap &_pal_gap; + pal::GenericAccessService &_gap_service; + BLEProtocol::AddressType_t _address_type; + pal::initiator_policy_t _initiator_policy_mode; + pal::scanning_filter_policy_t _scanning_filter_policy; + pal::advertising_filter_policy_t _advertising_filter_policy; + mutable Whitelist_t _whitelist; + mbed::Timeout _advertising_timeout; + mbed::Timeout _scan_timeout; +}; + +} +} + +#endif /* MBED_BLE_GENERIC_GAP */ diff --git a/features/FEATURE_BLE/ble/generic/GenericGattClient.h b/features/FEATURE_BLE/ble/generic/GenericGattClient.h index 8b525e8d06e..f0a8462ff97 100644 --- a/features/FEATURE_BLE/ble/generic/GenericGattClient.h +++ b/features/FEATURE_BLE/ble/generic/GenericGattClient.h @@ -26,27 +26,12 @@ namespace ble { namespace generic { -// forward declarations -struct procedure_control_block_t; -struct discovery_control_block_t; -struct read_control_block_t; -struct write_control_block_t; -struct descriptor_discovery_control_block_t; - /** * Generic implementation of the GattClient. * It requires a pal::GattClient injected at construction site. - * @important: Not part of the public interface of BLE API. + * @attention: Not part of the public interface of BLE API. */ class GenericGattClient : public GattClient { - - // give access to control block classes - friend struct procedure_control_block_t; - friend struct discovery_control_block_t; - friend struct read_control_block_t; - friend struct write_control_block_t; - friend struct descriptor_discovery_control_block_t; - public: /** * Create a GenericGattClient from a pal::GattClient @@ -130,10 +115,16 @@ class GenericGattClient : public GattClient { virtual ble_error_t reset(void); private: - procedure_control_block_t* get_control_block(Gap::Handle_t connection); - const procedure_control_block_t* get_control_block(Gap::Handle_t connection) const; - void insert_control_block(procedure_control_block_t* cb) const; - void remove_control_block(procedure_control_block_t* cb) const; + struct ProcedureControlBlock; + struct DiscoveryControlBlock; + struct ReadControlBlock; + struct WriteControlBlock; + struct DescriptorDiscoveryControlBlock; + + ProcedureControlBlock* get_control_block(Gap::Handle_t connection); + const ProcedureControlBlock* get_control_block(Gap::Handle_t connection) const; + void insert_control_block(ProcedureControlBlock* cb) const; + void remove_control_block(ProcedureControlBlock* cb) const; void on_termination(Gap::Handle_t connection_handle); void on_server_message_received(connection_handle_t, const pal::AttServerMessage&); @@ -145,7 +136,8 @@ class GenericGattClient : public GattClient { pal::GattClient* const _pal_client; ServiceDiscovery::TerminationCallback_t _termination_callback; - mutable procedure_control_block_t* control_blocks; + mutable ProcedureControlBlock* control_blocks; + bool _is_reseting; }; } diff --git a/features/FEATURE_BLE/ble/pal/EventQueue.h b/features/FEATURE_BLE/ble/pal/EventQueue.h index 062f9109e81..ead56dd36ab 100644 --- a/features/FEATURE_BLE/ble/pal/EventQueue.h +++ b/features/FEATURE_BLE/ble/pal/EventQueue.h @@ -55,7 +55,7 @@ struct EventQueue { * * @return true in case of success and false otherwise * - * @important Event availability shall be signaled to the upper layer and + * @attention Event availability shall be signaled to the upper layer and * the event queue shall be processed at the next invocation of * BLEInstanceBase::process */ diff --git a/features/FEATURE_BLE/ble/pal/GapEvents.h b/features/FEATURE_BLE/ble/pal/GapEvents.h index 34b7c7487a8..a406d6cdccb 100644 --- a/features/FEATURE_BLE/ble/pal/GapEvents.h +++ b/features/FEATURE_BLE/ble/pal/GapEvents.h @@ -175,13 +175,13 @@ struct GapConnectionCompleteEvent : public GapEvent { /** * Handle of the connection created, valid if status is equal to 0. - * @important Valid if status is equal to 0. + * @attention Valid if status is equal to 0. */ const connection_handle_t connection_handle; /** * Role of the device in the connection - * @important Valid if status is equal to 0. + * @attention Valid if status is equal to 0. */ const connection_role_t role; @@ -217,7 +217,7 @@ struct GapConnectionCompleteEvent : public GapEvent { /** * Report advertising from one or more LE device. * - * @important This class has to be implemented by the BLE port. + * @attention This class has to be implemented by the BLE port. * * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.2 LE Advertising Report Event */ @@ -432,7 +432,7 @@ struct GapDisconnectionCompleteEvent : public GapEvent { /** * Reason for disconnection. * - * @important ignored in case of faillure. + * @attention ignored in case of faillure. */ const uint8_t reason; }; diff --git a/features/FEATURE_BLE/ble/pal/PalGap.h b/features/FEATURE_BLE/ble/pal/PalGap.h index 288b0f9d082..b365e5c23b0 100644 --- a/features/FEATURE_BLE/ble/pal/PalGap.h +++ b/features/FEATURE_BLE/ble/pal/PalGap.h @@ -293,7 +293,7 @@ struct Gap { * @parameter filter_duplicates Enable duplicate filtering if true, * otherwise disable it. * - * @important advertising data or scan response data is not considered + * @attention advertising data or scan response data is not considered * significant when determining duplicate advertising reports. * * @return BLE_ERROR_NONE if the request has been successfully sent or the @@ -420,7 +420,7 @@ struct Gap { /** * Clear the whitelist stored in the LE subsystem. * - * @important This command shall not be issued if the whitelist is being + * @attention This command shall not be issued if the whitelist is being * used by the advertising, scanning or connection creation procedure. * * @return BLE_ERROR_NONE if the request has been successfully sent or the @@ -441,7 +441,7 @@ struct Gap { * @return BLE_ERROR_NONE if the request has been successfully sent or the * appropriate error otherwise. * - * @important This command shall not be issued if the whitelist is being + * @attention This command shall not be issued if the whitelist is being * used by the advertising, scanning or connection creation procedure. * * @note: See Bluetooth 5 Vol 2 PartE: 7.8.16 LE add device to white list @@ -463,7 +463,7 @@ struct Gap { * @return BLE_ERROR_NONE if the request has been successfully sent or the * appropriate error otherwise. * - * @important This command shall not be issued if the whitelist is being + * @attention This command shall not be issued if the whitelist is being * used by the advertising, scanning or connection creation procedure. * * @note: See Bluetooth 5 Vol 2 PartE: 7.8.17 LE remove device from white @@ -589,7 +589,7 @@ struct Gap { * @note Usually parameters of this function match the connection parameters * received in the connection parameter request event. * - * @important: Once the new connection parameters are in used a Connection + * @attention: Once the new connection parameters are in used a Connection * Update Complete event shall be emmited. * * @return BLE_ERROR_NONE if the request has been successfully sent or the diff --git a/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h b/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h index 6cd766421ec..84ccacfd485 100644 --- a/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h +++ b/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h @@ -20,7 +20,7 @@ #include #include "EventQueue.h" #include "ble/BLEInstanceBase.h" -#include "BLE/ble.h" +#include "ble/BLE.h" namespace ble { namespace pal { @@ -35,7 +35,7 @@ struct SimpleEventQueue : EventQueue { /** * Construct an empty event queue. * - * @important a call to initialize is mandatory before any other call. + * @attention a call to initialize is mandatory before any other call. * * @param ble_instance_id The id of the ble instance associated with that * event queue. diff --git a/features/FEATURE_BLE/ble/services/BatteryService.h b/features/FEATURE_BLE/ble/services/BatteryService.h index e6025af5152..2fcb7d516e0 100644 --- a/features/FEATURE_BLE/ble/services/BatteryService.h +++ b/features/FEATURE_BLE/ble/services/BatteryService.h @@ -49,7 +49,7 @@ * @note You can find specification of the battery service here: * https://www.bluetooth.com/specifications/gatt * - * @important Multiple instances of this battery service are not supported. + * @attention Multiple instances of this battery service are not supported. */ class BatteryService { public: @@ -95,7 +95,7 @@ class BatteryService { * @param newLevel Charge level of the battery. It is a percentage of the * remaining charge between 0% and 100%. * - * @important This function must be called in the execution context of the + * @attention This function must be called in the execution context of the * BLE stack. */ void updateBatteryLevel(uint8_t newLevel) diff --git a/features/FEATURE_BLE/ble/services/EddystoneConfigService.h b/features/FEATURE_BLE/ble/services/EddystoneConfigService.h index 8bebe509f4e..f21bd13a500 100644 --- a/features/FEATURE_BLE/ble/services/EddystoneConfigService.h +++ b/features/FEATURE_BLE/ble/services/EddystoneConfigService.h @@ -112,13 +112,16 @@ class EddystoneConfigService }; /** - * @param[ref] ble + * @param[in] bleIn * BLEDevice object for the underlying controller. - * @param[in/out] paramsIn + * @param[in,out] paramsIn * Reference to application-visible beacon state, loaded * from persistent storage at startup. * @param[in] defaultAdvPowerLevelsIn * Default power-levels array; applies only if resetToDefaultsFlag is true. + * + * @param[in] radioPowerLevelsIn + * Transmission power-levels to use in TX. */ EddystoneConfigService(BLEDevice &bleIn, Params_t ¶msIn, @@ -176,7 +179,7 @@ class EddystoneConfigService * @brief Start EddystoneConfig advertising. This function should be called * after the EddystoneConfig constructor and after all the frames have been added. * - * @paramsP[in] resetToDefaultsFlag + * @param[in] resetToDefaultsFlag * Applies to the state of the 'paramsIn' parameter. * If true, it indicates that paramsIn is potentially * un-initialized, and default values should be used diff --git a/features/FEATURE_BLE/ble/services/EddystoneService.h b/features/FEATURE_BLE/ble/services/EddystoneService.h index 6d92cf8a0f4..c88a8a4791d 100644 --- a/features/FEATURE_BLE/ble/services/EddystoneService.h +++ b/features/FEATURE_BLE/ble/services/EddystoneService.h @@ -98,6 +98,7 @@ class EddystoneService * @param[in] power TX Power in dB measured at 0 meters from the device. Range of -100 to +20 dB. * @param[in] namespaceID 10B namespace ID * @param[in] instanceID 6B instance ID + * @param[in] uidAdvPeriodIn Advertising period of UID frames. * @param[in] RFU 2B of RFU, initialized to 0x0000 and not broadcast, included for future reference. */ void setUIDFrameData(int8_t power, @@ -168,7 +169,7 @@ class EddystoneService /** * Set Eddystone URL Frame information. * @param[in] power TX Power in dB measured at 0 meters from the device. - * @param[in] url URL to encode + * @param[in] urlIn URL to encode * @param[in] urlAdvPeriodIn How long to advertise the URL frame (measured in # of adv periods) * @return false on success, true on failure. */ diff --git a/features/FEATURE_BLE/ble/services/EnvironmentalService.h b/features/FEATURE_BLE/ble/services/EnvironmentalService.h index 774cc4a30fa..c081245bebf 100644 --- a/features/FEATURE_BLE/ble/services/EnvironmentalService.h +++ b/features/FEATURE_BLE/ble/services/EnvironmentalService.h @@ -35,10 +35,7 @@ class EnvironmentalService { /** * @brief EnvironmentalService constructor. - * @param ble Reference to BLE device. - * @param temperature_en Enable this characteristic. - * @param humidity_en Enable this characteristic. - * @param pressure_en Enable this characteristic. + * @param _ble Reference to BLE device. */ EnvironmentalService(BLE& _ble) : ble(_ble), diff --git a/features/FEATURE_BLE/ble/services/HealthThermometerService.h b/features/FEATURE_BLE/ble/services/HealthThermometerService.h index 6b35eba79b3..af06b59f5d9 100644 --- a/features/FEATURE_BLE/ble/services/HealthThermometerService.h +++ b/features/FEATURE_BLE/ble/services/HealthThermometerService.h @@ -29,7 +29,6 @@ class HealthThermometerService { public: /** - * @enum Sensor Location. * @brief Location of sensor on the body. */ enum SensorLocation_t { @@ -47,7 +46,7 @@ class HealthThermometerService { public: /** * @brief Add the Health Thermometer Service to an existing BLE object, initialize with temperature and location. - * @param[ref] _ble Reference to the BLE device. + * @param[in] _ble Reference to the BLE device. * @param[in] initialTemp Initial value in celsius. * @param[in] _location */ diff --git a/features/FEATURE_BLE/ble/services/HeartRateService.h b/features/FEATURE_BLE/ble/services/HeartRateService.h index 7f5f240ff41..e8e239361cd 100644 --- a/features/FEATURE_BLE/ble/services/HeartRateService.h +++ b/features/FEATURE_BLE/ble/services/HeartRateService.h @@ -22,7 +22,7 @@ /** * BLE Heart Rate Service. * - * @purpose + * @par purpose * * Fitness applications use the heart rate service to expose the heart * beat per minute measured by a heart rate sensor. @@ -49,10 +49,10 @@ * @note You can find specification of the heart rate service here: * https://www.bluetooth.com/specifications/gatt * - * @important The service does not expose information related to the sensor + * @attention The service does not expose information related to the sensor * contact, the accumulated energy expanded or the interbeat intervals. * - * @important The heart rate profile limits the number of instantiations of the + * @attention The heart rate profile limits the number of instantiations of the * heart rate services to one. */ class HeartRateService { @@ -139,7 +139,7 @@ class HeartRateService { * * @param[in] hrmCounter Heart rate measured in BPM. * - * @important This function must be called in the execution context of the + * @attention This function must be called in the execution context of the * BLE stack. */ void updateHeartRate(uint16_t hrmCounter) { diff --git a/features/FEATURE_BLE/ble/services/LinkLossService.h b/features/FEATURE_BLE/ble/services/LinkLossService.h index beb44c20525..9bfed115e5c 100644 --- a/features/FEATURE_BLE/ble/services/LinkLossService.h +++ b/features/FEATURE_BLE/ble/services/LinkLossService.h @@ -36,8 +36,10 @@ class LinkLossService { typedef void (* callback_t)(AlertLevel_t level); /** - * @param[ref] ble + * @param bleIn * BLE object for the underlying controller. + * @param callbackIn Callback invoked upon disconnection. + * @param levelIn Alert level. */ LinkLossService(BLE &bleIn, callback_t callbackIn, AlertLevel_t levelIn = NO_ALERT) : ble(bleIn), diff --git a/features/FEATURE_BLE/ble/services/UARTService.h b/features/FEATURE_BLE/ble/services/UARTService.h index e8701ab155f..43da23c6f99 100644 --- a/features/FEATURE_BLE/ble/services/UARTService.h +++ b/features/FEATURE_BLE/ble/services/UARTService.h @@ -51,7 +51,7 @@ class UARTService { public: /** - * @param[ref] ble + * @param _ble * BLE object for the underlying controller. */ UARTService(BLE &_ble) : @@ -98,7 +98,7 @@ class UARTService { * a long read request; this is because notifications include only the first * 20 bytes of the updated data. * - * @param buffer The received update. + * @param _buffer The received update. * @param length Number of characters to be appended. * @return Number of characters appended to the rxCharacteristic. */ diff --git a/features/FEATURE_BLE/ble/services/URIBeaconConfigService.h b/features/FEATURE_BLE/ble/services/URIBeaconConfigService.h index db63707f3c1..9eb95bd40c2 100644 --- a/features/FEATURE_BLE/ble/services/URIBeaconConfigService.h +++ b/features/FEATURE_BLE/ble/services/URIBeaconConfigService.h @@ -75,17 +75,17 @@ class URIBeaconConfigService { }; /** - * @param[ref] ble + * @param[in] bleIn * BLE object for the underlying controller. - * @param[in/out] paramsIn + * @param[in,out] paramsIn * Reference to application-visible beacon state, loaded * from persistent storage at startup. - * @paramsP[in] resetToDefaultsFlag + * @param[in] resetToDefaultsFlag * Applies to the state of the 'paramsIn' parameter. * If true, it indicates that paramsIn is potentially * un-initialized, and default values should be used * instead. Otherwise, paramsIn overrides the defaults. - * @param[in] defaultUriDataIn + * @param[in] defaultURIDataIn * Default un-encoded URI. Applies only if the resetToDefaultsFlag is true. * @param[in] defaultAdvPowerLevelsIn * Default power-levels array. Applies only if the resetToDefaultsFlag is true. diff --git a/features/FEATURE_BLE/ble/services/iBeacon.h b/features/FEATURE_BLE/ble/services/iBeacon.h index bc520d3a0ae..f75e460381e 100644 --- a/features/FEATURE_BLE/ble/services/iBeacon.h +++ b/features/FEATURE_BLE/ble/services/iBeacon.h @@ -76,7 +76,7 @@ * * Beacon configuration and advertising commencement is left to the user. * - * @important If you are interested in manufacturing iBeacons, you must obtain a + * @attention If you are interested in manufacturing iBeacons, you must obtain a * license from Apple. More information at https://developer.apple.com/ibeacon/. * The licence also grant access to the iBeacons technical specification. * diff --git a/features/FEATURE_BLE/source/BLE.cpp b/features/FEATURE_BLE/source/BLE.cpp index 2d90b083bf6..9eba68f96e2 100644 --- a/features/FEATURE_BLE/source/BLE.cpp +++ b/features/FEATURE_BLE/source/BLE.cpp @@ -31,6 +31,30 @@ #include #endif +static const char* error_strings[] = { + "BLE_ERROR_NONE: No error", + "BLE_ERROR_BUFFER_OVERFLOW: The requested action would cause a buffer overflow and has been aborted", + "BLE_ERROR_NOT_IMPLEMENTED: Requested a feature that isn't yet implement or isn't supported by the target HW", + "BLE_ERROR_PARAM_OUT_OF_RANGE: One of the supplied parameters is outside the valid range", + "BLE_ERROR_INVALID_PARAM: One of the supplied parameters is invalid", + "BLE_STACK_BUSY: The stack is busy", + "BLE_ERROR_INVALID_STATE: Invalid state", + "BLE_ERROR_NO_MEM: Out of Memory", + "BLE_ERROR_OPERATION_NOT_PERMITTED: The operation requested is not permitted", + "BLE_ERROR_INITIALIZATION_INCOMPLETE: The BLE subsystem has not completed its initialisation", + "BLE_ERROR_ALREADY_INITIALIZED: The BLE system has already been initialised", + "BLE_ERROR_UNSPECIFIED: Unknown error", + "BLE_ERROR_INTERNAL_STACK_FAILURE: The platform-specific stack failed" +}; + +const char* BLE::errorToString(ble_error_t error) +{ + if (error > BLE_ERROR_INTERNAL_STACK_FAILURE) { + return "Illegal error code"; + } + return error_strings[error]; +} + ble_error_t BLE::initImplementation(FunctionPointerWithContext callback) { diff --git a/features/FEATURE_BLE/source/generic/GenericGap.cpp b/features/FEATURE_BLE/source/generic/GenericGap.cpp new file mode 100644 index 00000000000..8d87ce2dc0a --- /dev/null +++ b/features/FEATURE_BLE/source/generic/GenericGap.cpp @@ -0,0 +1,1102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "ble/BLEProtocol.h" +#include "ble/Gap.h" +#include "ble/pal/PalGap.h" +#include "ble/pal/GapEvents.h" +#include "ble/pal/GapTypes.h" +#include "ble/pal/GenericAccessService.h" +#include "ble/generic/GenericGap.h" + +#include "drivers/Timeout.h" + +namespace ble { +namespace generic { + +namespace { + +// Constants +static const uint16_t scan_interval_min = 0x0004; +static const uint16_t scan_interval_max = 0x4000; +static const uint16_t connection_interval_min = 0x0006; +static const uint16_t connection_interval_max = 0x0C80; +static const uint16_t slave_latency_min = 0x0000; +static const uint16_t slave_latency_max = 0x01F3; +static const uint16_t advertising_interval_min = 0x0020; +static const uint16_t advertising_interval_max = 0x4000; +static const uint16_t supervision_timeout_min = 0x000A; +static const uint16_t supervision_timeout_max = 0x0C80; + + +/* + * Return true if value is included in the range [lower_bound : higher_bound] + */ +template +static bool is_in_range(T value, T lower_bound, T higher_bound) { + if (value < lower_bound || value > higher_bound) { + return false; + } + return true; +} + +/* + * Return true if the scan parameters are valid or false otherwise. + */ +static bool is_scan_params_valid(const GapScanningParams* params) +{ + if (params == NULL) { + return false; + } + + if (is_in_range(params->getInterval(), scan_interval_min, scan_interval_max) == false) { + return false; + } + + if (is_in_range(params->getWindow(), scan_interval_min, params->getInterval()) == false) { + return false; + } + + return true; +} + +/* + * Return true if the connection parameters are valid or false otherwise. + */ +static bool is_connection_params_valid(const Gap::ConnectionParams_t* params) +{ + if (params == NULL) { + return false; + } + + if (is_in_range(params->slaveLatency, slave_latency_min, slave_latency_max) == false) { + return false; + } + + if (is_in_range(params->maxConnectionInterval, connection_interval_min, connection_interval_max) == false) { + return false; + } + + if (is_in_range(params->minConnectionInterval, connection_interval_min, params->maxConnectionInterval) == false) { + return false; + } + + if (is_in_range(params->connectionSupervisionTimeout, supervision_timeout_min, supervision_timeout_max) == false) { + return false; + } + + uint16_t max_connection_interval_ms = + ((uint32_t)params->maxConnectionInterval * 125) / 100; + uint16_t min_connection_supervision_timeout = + ((1 + params->slaveLatency) * max_connection_interval_ms * 2) / 10; + + if (params->connectionSupervisionTimeout < min_connection_supervision_timeout) { + return false; + } + + return true; +} + +/* + * Return true of the connection parameters are acceptable as preferred connection + * parameters. + * + * Prefered connection parameters unlike actual connection parameters allow the + * max connection interval, min connection interval and connection supervision + * timeout to be equal to 0xFFFF. When it is the case that value can be + * interpreted as "non specific". + */ +static bool is_preferred_connection_params_valid(const Gap::ConnectionParams_t* params) +{ + if (params == NULL) { + return false; + } + + if (is_in_range(params->slaveLatency, slave_latency_min, slave_latency_max) == false) { + return false; + } + + if ((is_in_range(params->maxConnectionInterval, connection_interval_min, connection_interval_max) == false) && + (params->maxConnectionInterval != 0xFFFF)) { + return false; + } + + if ((is_in_range(params->minConnectionInterval, connection_interval_min, params->maxConnectionInterval) == false) && + (params->minConnectionInterval != 0xFFFF)) { + return false; + } + + if (params->connectionSupervisionTimeout == 0xFFFF) { + return true; + } + + if ((is_in_range(params->connectionSupervisionTimeout, supervision_timeout_min, supervision_timeout_max) == false)) { + return false; + } + + if (params->maxConnectionInterval == 0xFFFF) { + return true; + } + + uint16_t max_connection_interval_ms = + ((uint32_t)params->maxConnectionInterval * 125) / 100; + uint16_t min_connection_supervision_timeout = + ((1 + params->slaveLatency) * max_connection_interval_ms * 2) / 10; + + if (params->connectionSupervisionTimeout < min_connection_supervision_timeout) { + return false; + } + + return true; +} + +/** + * Check if random bytes of an address are valid. + */ +static bool is_prand_valid(const uint8_t* bytes, size_t len) +{ + // at least one bit of the random part of the static address shall be + // equal to 0 and at least one bit of the random part of the static + // address shall be equal to 1 + for (size_t i = 0; i < (len - 1); ++i) { + if ((bytes[i] != 0x00) && (bytes[i] != 0xFF)) { + return true; + } + + if ((i > 0) && (bytes[i] != bytes[i - 1])) { + return true; + } + } + + if (((bytes[len - 1] & 0x3F) == 0x3F) && (bytes[len - 2] == 0xFF)) { + return false; + } + + if (((bytes[len - 1] & 0x3F) == 0x00) && (bytes[len - 2] == 0x00)) { + return false; + } + + return true; +} + +/* + * Check if the random part of a random address with 48 random bytes are valid + * or not. + * Return true if it is the case and false otherwise. + */ +static bool is_prand_48_bits_valid(const BLEProtocol::AddressBytes_t address) +{ + return is_prand_valid(address, 6); +} + +/* + * Check if the random part of a random address with 24 random bytes are valid + * or not. + * Return true if it is the case and false otherwise. + */ +static bool is_prand_24_bits_valid(const BLEProtocol::AddressBytes_t address) +{ + return is_prand_valid(address + 3, 3); +} + +/* + * Return true if address is a random static address. + */ +static bool is_random_static_address(const BLEProtocol::AddressBytes_t address) +{ + // top two msb bits shall be equal to 1. + if ((address[5] >> 6) != 0x03) { + return false; + } + + return is_prand_48_bits_valid(address); +} + +/* + * Return true if address is a random private non resolvable address. + */ +static bool is_random_private_non_resolvable_address( + const BLEProtocol::AddressBytes_t address +) { + // top two msb bits shall be equal to 0. + if ((address[5] >> 6) != 0x00) { + return false; + } + + return is_prand_48_bits_valid(address); +} + +/* + * Return true if address is a random private resolvable address. + */ +static bool is_random_private_resolvable_address( + const BLEProtocol::AddressBytes_t address +) { + // top two msb bits shall be equal to 01. + if ((address[5] >> 6) != 0x01) { + return false; + } + + return is_prand_24_bits_valid(address); +} + +/* + * Return true if the address is a random address. + */ +static bool is_random_address(const BLEProtocol::AddressBytes_t address) +{ + return is_random_private_resolvable_address(address) || + is_random_private_non_resolvable_address(address) || + is_random_static_address(address); +} + +/* + * Check disconnection reason validity. + */ +static bool is_disconnection_reason_valid(Gap::DisconnectionReason_t reason) +{ + switch (reason) { + /** + * Note: accepted reasons are: + typedef pal::disconnection_reason_t reason_t; + case reason_t::AUTHENTICATION_FAILLURE: + case reason_t::REMOTE_USER_TERMINATED_CONNECTION: + case reason_t::REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES: + case reason_t::REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_POWER_OFF: + case reason_t::UNSUPPORTED_REMOTE_FEATURE: + case reason_t::PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED: + case reason_t::UNACCEPTABLE_CONNECTION_PARAMETERS: + */ + + // TODO Fix Disconnectionreason_t which expose invalid value + case Gap::REMOTE_USER_TERMINATED_CONNECTION: + case Gap::REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES: + case Gap::REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF: + case Gap::CONN_INTERVAL_UNACCEPTABLE: + return true; + default: + return false; + } +} + +/* + * Return true if the whitelist in input is valid or false otherwise. + */ +static bool is_whitelist_valid(const Gap::Whitelist_t& whitelist) +{ + if (whitelist.size > whitelist.capacity) { + return false; + } + + for (size_t i = 0; i < whitelist.size; ++i) { + const BLEProtocol::Address_t& address = whitelist.addresses[i]; + if (address.type > BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE) { + return false; + } + + if (address.type != BLEProtocol::AddressType::PUBLIC) { + if (is_random_address(address.address) == false) { + return false; + } + } + } + return true; +} + +/* + * Return true if device is present in the whitelist. + */ +static bool is_in_whitelist( + const BLEProtocol::Address_t& device, const Gap::Whitelist_t& whitelist +) { + for (size_t i = 0; i < whitelist.size; ++i) { + const BLEProtocol::Address_t& potential_device = whitelist.addresses[i]; + + if (potential_device.type != device.type) { + continue; + } + + if (memcmp(potential_device.address, device.address, sizeof(device.address)) == 0) { + return true; + } + } + return false; +} + +/* + * Convert a BLEProtocol::AddressType_t into a pal::whitelist_address_type_t. + */ +static pal::whitelist_address_type_t to_device_address_type( + BLEProtocol::AddressType_t address_type +) { + return (address_type == BLEProtocol::AddressType::PUBLIC) ? + pal::whitelist_address_type_t::PUBLIC_DEVICE_ADDRESS : + pal::whitelist_address_type_t::RANDOM_DEVICE_ADDRESS; +} + +/* + * Return true if the advertising parameters are valid. + */ +static bool is_advertising_params_valid(const GapAdvertisingParams& params) +{ + if (is_in_range(params.getIntervalInADVUnits(), advertising_interval_min, advertising_interval_max) == false) { + return false; + } + + if (params.getAdvertisingType() > GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED) { + return false; + } + + return true; +} + +} // end of anonymous namespace + +GenericGap::GenericGap( + pal::EventQueue& event_queue, + pal::Gap& pal_gap, + pal::GenericAccessService& generic_access_service +) : _event_queue(event_queue), + _pal_gap(pal_gap), + _gap_service(generic_access_service), + _address_type(BLEProtocol::AddressType::PUBLIC), + _initiator_policy_mode(pal::initiator_policy_t::NO_FILTER), + _scanning_filter_policy(pal::scanning_filter_policy_t::NO_FILTER), + _advertising_filter_policy(pal::advertising_filter_policy_t::NO_FILTER), + _whitelist(), + _advertising_timeout(), + _scan_timeout() +{ + _pal_gap.when_gap_event_received( + mbed::callback(this, &GenericGap::on_gap_event_received) + ); +} + +GenericGap::~GenericGap() +{ +} + +ble_error_t GenericGap::setAddress( + BLEProtocol::AddressType_t type, + const BLEProtocol::AddressBytes_t address +) { + switch (type) { + case BLEProtocol::AddressType::PUBLIC: + // The public address cannot be set, just set the type to public + _address_type = type; + return BLE_ERROR_NONE; + + case BLEProtocol::AddressType::RANDOM_STATIC: { + if (is_random_static_address(address) == false) { + return BLE_ERROR_INVALID_PARAM; + } + + ble_error_t err = _pal_gap.set_random_address( + pal::address_t(address, true) + ); + if (err) { + return err; + } + + _address_type = type; + return BLE_ERROR_NONE; + } + + case BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE: + // TODO: Fix with the privacy/security rework + return BLE_ERROR_NOT_IMPLEMENTED; + + case BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE: + // TODO: add process to set the random private non resolvable + // address (privacy/security work) + return BLE_ERROR_NOT_IMPLEMENTED; + + default: + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } +} + +ble_error_t GenericGap::getAddress( + BLEProtocol::AddressType_t *type, + BLEProtocol::AddressBytes_t address +) { + *type = _address_type; + pal::address_t address_value; + if (_address_type == BLEProtocol::AddressType::PUBLIC) { + address_value = _pal_gap.get_device_address(); + } else { + address_value = _pal_gap.get_random_address(); + } + + memcpy(address, address_value.data(), address_value.size()); + return BLE_ERROR_NONE; +} + +uint16_t GenericGap::getMinAdvertisingInterval() const +{ + return GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN; +} + +uint16_t GenericGap::getMinNonConnectableAdvertisingInterval() const +{ + return GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN_NONCON; +} + +uint16_t GenericGap::getMaxAdvertisingInterval() const +{ + return GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX; +} + +ble_error_t GenericGap::stopAdvertising() +{ + ble_error_t err = _pal_gap.advertising_enable(false); + if (err) { + return err; + } + _advertising_timeout.detach(); + state.advertising = false; + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::stopScan() +{ + ble_error_t err = _pal_gap.scan_enable(false, false); + if (err) { + return err; + } + + _scan_timeout.detach(); + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::connect( + const BLEProtocol::AddressBytes_t peerAddr, + BLEProtocol::AddressType_t peerAddrType, + const ConnectionParams_t* connectionParams, + const GapScanningParams* scanParams +) { + if (is_scan_params_valid(scanParams) == false) { + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } + + if (is_connection_params_valid(connectionParams) == false) { + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } + + // TODO fix upper layer API, address type factorization is incorrect. + + return _pal_gap.create_connection( + scanParams->getInterval(), + scanParams->getWindow(), + _initiator_policy_mode, + (pal::connection_peer_address_type_t::type) peerAddrType, + pal::address_t(peerAddr, true), + (pal::own_address_type_t::type) _address_type, + connectionParams->minConnectionInterval, + connectionParams->maxConnectionInterval, + connectionParams->slaveLatency, + connectionParams->connectionSupervisionTimeout, + /* minimum_connection_event_length */ 0, + /* maximum_connection_event_length */ 0 + ); +} + +ble_error_t GenericGap::disconnect(Handle_t connectionHandle, DisconnectionReason_t reason) +{ + if (is_disconnection_reason_valid(reason) == false) { + return BLE_ERROR_INVALID_PARAM; + } + return _pal_gap.disconnect( + connectionHandle, + (pal::disconnection_reason_t::type) reason + ); +} + +ble_error_t GenericGap::updateConnectionParams(Handle_t handle, const ConnectionParams_t *params) +{ + if (is_connection_params_valid(params) == false) { + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } + + return _pal_gap.connection_parameters_update( + handle, + params->minConnectionInterval, + params->maxConnectionInterval, + params->slaveLatency, + params->connectionSupervisionTimeout, + /* minimum_connection_event_length */ 0, + /* maximum_connection_event_length */ 0 + ); +} + +ble_error_t GenericGap::getPreferredConnectionParams(ConnectionParams_t *params) +{ + if (params == NULL) { + return BLE_ERROR_INVALID_PARAM; + } + + return _gap_service.get_peripheral_prefered_connection_parameters( + *params + ); +} + +ble_error_t GenericGap::setPreferredConnectionParams(const ConnectionParams_t *params) +{ + if(is_preferred_connection_params_valid(params) == false) { + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } + + return _gap_service.set_peripheral_prefered_connection_parameters( + *params + ); +} + +ble_error_t GenericGap::setDeviceName(const uint8_t *deviceName) +{ + return _gap_service.set_device_name(deviceName); +} + +ble_error_t GenericGap::getDeviceName(uint8_t *deviceName, unsigned *lengthP) +{ + if (lengthP == NULL) { + return BLE_ERROR_INVALID_PARAM; + } + + uint8_t length = 0; + ble_error_t err = _gap_service.get_device_name_length(length); + if (err) { + return err; + } + + if (deviceName != NULL) { + if (*lengthP < length) { + return BLE_ERROR_INVALID_PARAM; + } + + ArrayView name(deviceName, *lengthP); + err = _gap_service.get_device_name(name); + if (err) { + return err; + } + } + *lengthP = length; + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::setAppearance(GapAdvertisingData::Appearance appearance) +{ + return _gap_service.set_appearance(appearance); +} + +ble_error_t GenericGap::getAppearance(GapAdvertisingData::Appearance *appearanceP) +{ + if (appearanceP == NULL) { + return BLE_ERROR_INVALID_PARAM; + } + return _gap_service.get_appearance(*appearanceP); +} + +ble_error_t GenericGap::setTxPower(int8_t txPower) +{ + // TODO: This is not standard, expose it as an extension API and document it + // as such + return BLE_ERROR_NOT_IMPLEMENTED; +} + +void GenericGap::getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP) +{ + *countP = 0; +} + +uint8_t GenericGap::getMaxWhitelistSize(void) const +{ + return _pal_gap.read_white_list_capacity(); +} + +ble_error_t GenericGap::getWhitelist(Whitelist_t &whitelist) const +{ + if(initialize_whitelist() == false) { + return BLE_ERROR_INVALID_STATE; + } + + if (whitelist.capacity < _whitelist.capacity) { + return BLE_ERROR_INVALID_PARAM; + } + + for (size_t i = 0; i < _whitelist.size; ++i) { + whitelist.addresses[i] = _whitelist.addresses[i]; + } + + whitelist.capacity = _whitelist.capacity; + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::setWhitelist(const Whitelist_t &whitelist) +{ + if (is_whitelist_valid(whitelist) == false) { + return BLE_ERROR_INVALID_PARAM; + } + + if(initialize_whitelist() == false) { + return BLE_ERROR_INVALID_STATE; + } + + if (whitelist.capacity > _whitelist.capacity) { + return BLE_ERROR_INVALID_PARAM; + } + + // first evict devices not in the existing whitelist + for (size_t i = 0; i < _whitelist.size; ++i) { + const BLEProtocol::Address_t& device = _whitelist.addresses[i]; + + if (is_in_whitelist(device, whitelist) == false) { + ble_error_t err = _pal_gap.remove_device_from_whitelist( + to_device_address_type(device.type), + device.address + ); + + // try to restore the whitelist to its initial state + if (err) { + for (size_t j = 0; j < i; ++j) { + const BLEProtocol::Address_t& device = _whitelist.addresses[j]; + + if (is_in_whitelist(device, whitelist) == false) { + _pal_gap.add_device_to_whitelist( + to_device_address_type(device.type), + device.address + ); + } + } + return err; + } + } + } + + // second add devices which were not in the initial whitelist + for (size_t i = 0; i < whitelist.size; ++i) { + const BLEProtocol::Address_t& device = whitelist.addresses[i]; + + if (is_in_whitelist(device, _whitelist) == false) { + ble_error_t err = _pal_gap.add_device_to_whitelist( + to_device_address_type(device.type), + device.address + ); + + // try to restore the whitelist to its initial state + if (err) { + // first remove the devices added + for (size_t j = 0; j < i; ++j) { + const BLEProtocol::Address_t& device = whitelist.addresses[j]; + + if (is_in_whitelist(device, _whitelist) == false) { + _pal_gap.remove_device_from_whitelist( + to_device_address_type(device.type), + device.address + ); + } + } + + // second add the devices of the initial list evicted + for (size_t i = 0; i < _whitelist.size; ++i) { + const BLEProtocol::Address_t& device = _whitelist.addresses[i]; + + if (is_in_whitelist(device, whitelist) == false) { + _pal_gap.add_device_to_whitelist( + to_device_address_type(device.type), + device.address + ); + } + } + + return err; + } + } + } + + // commit the devices into the whitelist + for (size_t i = 0; i < whitelist.size; ++i) { + _whitelist.addresses[i] = whitelist.addresses[i]; + } + + _whitelist.size = whitelist.size; + + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::setAdvertisingPolicyMode(AdvertisingPolicyMode_t mode) +{ + if (mode > Gap::ADV_POLICY_FILTER_ALL_REQS) { + return BLE_ERROR_INVALID_PARAM; + } + + _advertising_filter_policy = (pal::advertising_filter_policy_t::type) mode; + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::setScanningPolicyMode(ScanningPolicyMode_t mode) +{ + if (mode > Gap::SCAN_POLICY_FILTER_ALL_ADV) { + return BLE_ERROR_INVALID_PARAM; + } + + _scanning_filter_policy = (pal::scanning_filter_policy_t::type) mode; + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::setInitiatorPolicyMode(InitiatorPolicyMode_t mode) +{ + if (mode > Gap::INIT_POLICY_FILTER_ALL_ADV) { + return BLE_ERROR_INVALID_PARAM; + } + + _initiator_policy_mode = (pal::initiator_policy_t::type) mode; + return BLE_ERROR_NONE; +} + +Gap::AdvertisingPolicyMode_t GenericGap::getAdvertisingPolicyMode(void) const +{ + return (AdvertisingPolicyMode_t) _advertising_filter_policy.value(); +} + +Gap::ScanningPolicyMode_t GenericGap::getScanningPolicyMode(void) const +{ + return (ScanningPolicyMode_t) _scanning_filter_policy.value(); +} + +Gap::InitiatorPolicyMode_t GenericGap::getInitiatorPolicyMode(void) const +{ + return (InitiatorPolicyMode_t) _initiator_policy_mode.value(); +} + +ble_error_t GenericGap::startRadioScan(const GapScanningParams &scanningParams) +{ + if (is_scan_params_valid(&scanningParams) == false) { + return BLE_ERROR_INVALID_PARAM; + } + + if (_scanning_filter_policy == pal::scanning_filter_policy_t::FILTER_ADVERTISING && + _whitelist.size == 0) { + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = _pal_gap.set_scan_parameters( + scanningParams.getActiveScanning(), + scanningParams.getInterval(), + scanningParams.getWindow(), + get_own_address_type(), + _scanning_filter_policy + ); + + if (err) { + return err; + } + + err = _pal_gap.scan_enable(true, false); + + if (err) { + return err; + } + + _scan_timeout.detach(); + uint16_t timeout = scanningParams.getTimeout(); + if (timeout) { + _scan_timeout.attach_us( + mbed::callback(this, &GenericGap::on_scan_timeout), + scanningParams.getTimeout() * 1000000U + ); + } + + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::initRadioNotification(void) +{ + return BLE_ERROR_NOT_IMPLEMENTED; +} + +ble_error_t GenericGap::setAdvertisingData(const GapAdvertisingData &advData, const GapAdvertisingData &scanResponse) +{ + ble_error_t err = _pal_gap.set_advertising_data( + advData.getPayloadLen(), + pal::advertising_data_t(advData.getPayload(), advData.getPayloadLen()) + ); + if (err) { + return err; + } + + return _pal_gap.set_scan_response_data( + scanResponse.getPayloadLen(), + pal::advertising_data_t(scanResponse.getPayload(), scanResponse.getPayloadLen()) + ); +} + +ble_error_t GenericGap::startAdvertising(const GapAdvertisingParams& params) +{ + if (is_advertising_params_valid(params) == false) { + return BLE_ERROR_INVALID_PARAM; + } + + // TODO: fix the high level API to have a min/max range + // Going against recommendations (The Advertising_Interval_Min and + // Advertising_Interval_Max should not be the same value to enable the + // Controller to determine the best advertising interval given other activities.) + // for now but not against specification: "The Advertising_Interval_Min + // shall be less than or equal to the Advertising_Interval_Max" + ble_error_t err = _pal_gap.set_advertising_parameters( + /* advertising_interval_min */ params.getIntervalInADVUnits(), + /* advertising_interval_max */ params.getIntervalInADVUnits(), + (pal::advertising_type_t::type) params.getAdvertisingType(), + get_own_address_type(), + pal::advertising_peer_address_type_t::PUBLIC_ADDRESS, + pal::address_t(), + pal::advertising_channel_map_t::ALL_ADVERTISING_CHANNELS, + _advertising_filter_policy + ); + + if (err) { + return err; + } + + err = _pal_gap.advertising_enable(true); + if (err) { + return err; + } + + state.advertising = true; + + _advertising_timeout.detach(); + uint16_t timeout = params.getTimeout(); + if (timeout) { + _advertising_timeout.attach_us( + mbed::callback(this, &GenericGap::on_advertising_timeout), + params.getTimeout() * 1000000U + ); + } + + return BLE_ERROR_NONE; +} + +ble_error_t GenericGap::reset(void) +{ + Gap::reset(); + _advertising_timeout.detach(); + _scan_timeout.detach(); + + return BLE_ERROR_NONE; +} + +void GenericGap::on_scan_timeout() +{ + _event_queue.post(mbed::callback(this, &GenericGap::process_scan_timeout)); +} + +void GenericGap::process_scan_timeout() +{ + ble_error_t err = _pal_gap.scan_enable(false, false); + if (err) { + // TODO: define the mechanism signaling the error + } + processTimeoutEvent(Gap::TIMEOUT_SRC_SCAN); +} + +void GenericGap::on_advertising_timeout() +{ + _event_queue.post(mbed::callback(this, &GenericGap::process_advertising_timeout)); +} + +void GenericGap::process_advertising_timeout() +{ + ble_error_t err = _pal_gap.advertising_enable(false); + if (err) { + // TODO: define the mechanism signaling the error + } + processTimeoutEvent(Gap::TIMEOUT_SRC_ADVERTISING); +} + +void GenericGap::on_gap_event_received(const pal::GapEvent& e) +{ + switch (e.type.value()) { + case pal::GapEventType::ADVERTISING_REPORT: + on_advertising_report(static_cast(e)); + break; + + case pal::GapEventType::CONNECTION_COMPLETE: + on_connection_complete(static_cast(e)); + break; + + case pal::GapEventType::CONNECTION_UPDATE: + on_connection_update(static_cast(e)); + break; + + case pal::GapEventType::DISCONNECTION_COMPLETE: + on_disconnection_complete(static_cast(e)); + break; + + case pal::GapEventType::REMOTE_CONNECTION_PARAMETER_REQUEST: + on_connection_parameter_request(static_cast(e)); + break; + + case pal::GapEventType::UNEXPECTED_ERROR: + on_unexpected_error(static_cast(e)); + break; + + default: + break; + } +} + +void GenericGap::on_advertising_report(const pal::GapAdvertisingReportEvent& e) +{ + for (size_t i = 0; i < e.size(); ++i) { + pal::GapAdvertisingReportEvent::advertising_t advertising = e[i]; + + processAdvertisementReport( + advertising.address.data(), + advertising.rssi, + advertising.type == pal::received_advertising_type_t::SCAN_RESPONSE, + (GapAdvertisingParams::AdvertisingType_t) advertising.type.value(), + advertising.data.size(), + advertising.data.data() + ); + } +} + +void GenericGap::on_connection_complete(const pal::GapConnectionCompleteEvent& e) +{ + // TODO: deprecate ownAddrType and ownAddr, those are not specified + // from the Bluetooth perspective + if (e.status == pal::hci_error_code_t::SUCCESS) { + if (e.role.value() == e.role.SLAVE) { + _advertising_timeout.detach(); + _pal_gap.advertising_enable(false); + } + + // using these parameters if stupid, there is no range for the + // connection interval when the connection is established + ConnectionParams_t connection_params = { + /* minConnectionInterval */ e.connection_interval, + /* maxConnectionInterval */ e.connection_interval, + e.connection_latency, + e.supervision_timeout + }; + pal::address_t address; + if (_address_type == BLEProtocol::AddressType::PUBLIC) { + address = _pal_gap.get_device_address(); + } else { + address = _pal_gap.get_random_address(); + } + + processConnectionEvent( + e.connection_handle, + e.role.value() == e.role.MASTER ? ::Gap::CENTRAL : ::Gap::PERIPHERAL, + (BLEProtocol::AddressType_t) e.peer_address_type.value(), + e.peer_address.data(), + _address_type, + address.data(), + &connection_params + ); + } else { + // for now notify user that the connection failled by issuing a timeout + // event + + // TODO: Define events in case of connection faillure + processTimeoutEvent(Gap::TIMEOUT_SRC_CONN); + } +} + +void GenericGap::on_disconnection_complete(const pal::GapDisconnectionCompleteEvent& e) +{ + if (e.status == pal::hci_error_code_t::SUCCESS) { + processDisconnectionEvent( + e.connection_handle, + (Gap::DisconnectionReason_t) e.reason + ); + } else { + // TODO: define what to do in case of faillure + } +} + +void GenericGap::on_connection_parameter_request(const pal::GapRemoteConnectionParameterRequestEvent& e) +{ + // intern behavior, accept all new parameter requests + // TODO: expose an API so user code can accept or reject such request + _pal_gap.accept_connection_parameter_request( + e.connection_handle, + e.min_connection_interval, + e.max_connection_interval, + e.connection_latency, + e.supervision_timeout, + /* minimum_connection_event_length */ 0, + /* maximum_connection_event_length */ 0 + ); +} + +void GenericGap::on_connection_update(const pal::GapConnectionUpdateEvent& e) +{ + // TODO: add feature in interface to notify the user that the connection + // has been updated. +} + +void GenericGap::on_unexpected_error(const pal::GapUnexpectedErrorEvent& e) +{ + // TODO: add feature in interface to notify the user that the connection + // has been updated. +} + +pal::own_address_type_t GenericGap::get_own_address_type() +{ + switch (_address_type) { + case BLEProtocol::AddressType::PUBLIC: + return pal::own_address_type_t::PUBLIC_ADDRESS; + case BLEProtocol::AddressType::RANDOM_STATIC: + case BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE: + return pal::own_address_type_t::RANDOM_ADDRESS; + case BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE: + return pal::own_address_type_t::RESOLVABLE_PRIVATE_ADDRESS_PUBLIC_FALLBACK; + default: + // not reachable + return pal::own_address_type_t::PUBLIC_ADDRESS; + } +} + +bool GenericGap::initialize_whitelist() const +{ + if (_whitelist.addresses != NULL) { + return true; + } + + uint8_t whitelist_capacity = _pal_gap.read_white_list_capacity(); + + if (whitelist_capacity == 0) { + return false; + } + + _whitelist.addresses = new (std::nothrow) BLEProtocol::Address_t[whitelist_capacity] ; + if (_whitelist.addresses == NULL) { + return false; + } + + _whitelist.size = 0; + _whitelist.capacity = whitelist_capacity; + + return true; +} + +} // namespace generic +} // namespace ble diff --git a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp index 595babcccc0..97c6d57fc0f 100644 --- a/features/FEATURE_BLE/source/generic/GenericGattClient.cpp +++ b/features/FEATURE_BLE/source/generic/GenericGattClient.cpp @@ -55,14 +55,14 @@ enum procedure_type_t { /* * Base class for a procedure control block */ -struct procedure_control_block_t { +struct GenericGattClient::ProcedureControlBlock { /* * Base constructor for procedure control block. */ - procedure_control_block_t(procedure_type_t type, Gap::Handle_t handle) : + ProcedureControlBlock(procedure_type_t type, Gap::Handle_t handle) : type(type), connection_handle(handle), next(NULL) { } - virtual ~procedure_control_block_t() { } + virtual ~ProcedureControlBlock() { } /* * Entry point of the control block stack machine. @@ -74,23 +74,28 @@ struct procedure_control_block_t { */ virtual void handle_timeout_error(GenericGattClient* client) = 0; + /** + * Function called when the procedure is aborted + */ + virtual void abort(GenericGattClient *client) = 0; + procedure_type_t type; Gap::Handle_t connection_handle; - procedure_control_block_t* next; + ProcedureControlBlock* next; }; /* * Procedure control block for the discovery process. */ -struct discovery_control_block_t : public procedure_control_block_t { - discovery_control_block_t( +struct GenericGattClient::DiscoveryControlBlock : public ProcedureControlBlock { + DiscoveryControlBlock( Gap::Handle_t handle, ServiceDiscovery::ServiceCallback_t service_callback, ServiceDiscovery::CharacteristicCallback_t characteristic_callback, UUID matching_service_uuid, UUID matching_characteristic_uuid - ) : procedure_control_block_t(COMPLETE_DISCOVERY_PROCEDURE, handle), + ) : ProcedureControlBlock(COMPLETE_DISCOVERY_PROCEDURE, handle), service_callback(service_callback), characteristic_callback(characteristic_callback), matching_service_uuid(matching_service_uuid), @@ -99,7 +104,7 @@ struct discovery_control_block_t : public procedure_control_block_t { done(false) { } - virtual ~discovery_control_block_t() { + virtual ~DiscoveryControlBlock() { while(services_discovered) { service_t* tmp = services_discovered->next; delete services_discovered; @@ -111,6 +116,10 @@ struct discovery_control_block_t : public procedure_control_block_t { terminate(client); } + virtual void abort(GenericGattClient *client) { + terminate(client); + } + virtual void handle(GenericGattClient* client, const AttServerMessage& message) { // if end of discovery has been requested, ends it immediately if (done) { @@ -409,15 +418,15 @@ struct discovery_control_block_t : public procedure_control_block_t { }; -struct read_control_block_t : public procedure_control_block_t { - read_control_block_t( +struct GenericGattClient::ReadControlBlock : public ProcedureControlBlock { + ReadControlBlock( Gap::Handle_t connection_handle, uint16_t attribute_handle, uint16_t offset - ) : procedure_control_block_t(READ_PROCEDURE, connection_handle), + ) : ProcedureControlBlock(READ_PROCEDURE, connection_handle), attribute_handle(attribute_handle), offset(offset), current_offset(offset), data(NULL) { } - virtual ~read_control_block_t() { + virtual ~ReadControlBlock() { if (data != NULL) { free(data); } @@ -436,6 +445,19 @@ struct read_control_block_t : public procedure_control_block_t { terminate(client, response); } + virtual void abort(GenericGattClient *client) { + GattReadCallbackParams response = { + connection_handle, + attribute_handle, + offset, + 0, // size of 0 + NULL, // no data + BLE_ERROR_INVALID_STATE, + + }; + terminate(client, response); + } + void terminate(GenericGattClient* client, const GattReadCallbackParams& response) { client->remove_control_block(this); client->processReadResponse(&response); @@ -593,16 +615,16 @@ struct read_control_block_t : public procedure_control_block_t { /* * Control block for the write process */ -struct write_control_block_t : public procedure_control_block_t { - write_control_block_t( +struct GenericGattClient::WriteControlBlock : public ProcedureControlBlock { + WriteControlBlock( Gap::Handle_t connection_handle, uint16_t attribute_handle, uint8_t* data, uint16_t len - ) : procedure_control_block_t(WRITE_PROCEDURE, connection_handle), + ) : ProcedureControlBlock(WRITE_PROCEDURE, connection_handle), attribute_handle(attribute_handle), len(len), offset(0), data(data), prepare_success(false), status(BLE_ERROR_UNSPECIFIED), error_code(0xFF) { } - virtual ~write_control_block_t() { + virtual ~WriteControlBlock() { free(data); } @@ -617,6 +639,17 @@ struct write_control_block_t : public procedure_control_block_t { terminate(client, response); } + virtual void abort(GenericGattClient *client) { + GattWriteCallbackParams response = { + connection_handle, + attribute_handle, + GattWriteCallbackParams::OP_WRITE_REQ, + BLE_ERROR_INVALID_STATE, + 0x00 + }; + terminate(client, response); + } + void terminate(GenericGattClient* client, const GattWriteCallbackParams& response) { client->remove_control_block(this); client->processWriteResponse(&response); @@ -785,12 +818,12 @@ struct write_control_block_t : public procedure_control_block_t { /* * Control block for the descriptor discovery process */ -struct descriptor_discovery_control_block_t : public procedure_control_block_t { - descriptor_discovery_control_block_t( +struct GenericGattClient::DescriptorDiscoveryControlBlock : public ProcedureControlBlock { + DescriptorDiscoveryControlBlock( const DiscoveredCharacteristic& characteristic, const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback - ) : procedure_control_block_t(DESCRIPTOR_DISCOVERY_PROCEDURE, characteristic.getConnectionHandle()), + ) : ProcedureControlBlock(DESCRIPTOR_DISCOVERY_PROCEDURE, characteristic.getConnectionHandle()), characteristic(characteristic), discovery_cb(discoveryCallback), termination_cb(terminationCallback), @@ -798,7 +831,7 @@ struct descriptor_discovery_control_block_t : public procedure_control_block_t { done(false) { } - virtual ~descriptor_discovery_control_block_t() { } + virtual ~DescriptorDiscoveryControlBlock() { } ble_error_t start(GenericGattClient* client) { return client->_pal_client->discover_characteristics_descriptors( @@ -814,6 +847,10 @@ struct descriptor_discovery_control_block_t : public procedure_control_block_t { terminate(client, BLE_ERROR_UNSPECIFIED); } + virtual void abort(GenericGattClient *client) { + terminate(client, BLE_ERROR_INVALID_STATE); + } + virtual void handle(GenericGattClient* client, const AttServerMessage& message) { if (done) { terminate(client, BLE_ERROR_NONE); @@ -892,7 +929,8 @@ struct descriptor_discovery_control_block_t : public procedure_control_block_t { GenericGattClient::GenericGattClient(pal::GattClient* pal_client) : _pal_client(pal_client), _termination_callback(), - control_blocks(NULL) { + control_blocks(NULL), + _is_reseting(false) { _pal_client->when_server_message_received( mbed::callback(this, &GenericGattClient::on_server_message_received) ); @@ -909,7 +947,7 @@ ble_error_t GenericGattClient::launchServiceDiscovery( const UUID& matching_characteristic_uuid ) { // verify that there is no other procedures going on this connection - if (get_control_block(connection_handle)) { + if (_is_reseting || get_control_block(connection_handle)) { return BLE_ERROR_INVALID_STATE; } @@ -919,7 +957,7 @@ ble_error_t GenericGattClient::launchServiceDiscovery( return BLE_ERROR_NONE; } - discovery_control_block_t* discovery_pcb = new(std::nothrow) discovery_control_block_t( + DiscoveryControlBlock* discovery_pcb = new(std::nothrow) DiscoveryControlBlock( connection_handle, service_callback, characteristic_callback, @@ -959,7 +997,7 @@ ble_error_t GenericGattClient::launchServiceDiscovery( } bool GenericGattClient::isServiceDiscoveryActive() const { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == COMPLETE_DISCOVERY_PROCEDURE) { @@ -973,10 +1011,10 @@ bool GenericGattClient::isServiceDiscoveryActive() const { void GenericGattClient::terminateServiceDiscovery() { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == COMPLETE_DISCOVERY_PROCEDURE) { - static_cast(pcb)->done = true; + static_cast(pcb)->done = true; } pcb = pcb->next; } @@ -988,11 +1026,11 @@ ble_error_t GenericGattClient::read( uint16_t offset) const { // verify that there is no other procedures going on this connection - if (get_control_block(connection_handle)) { + if (_is_reseting || get_control_block(connection_handle)) { return BLE_ERROR_INVALID_STATE; } - read_control_block_t* read_pcb = new(std::nothrow) read_control_block_t( + ReadControlBlock* read_pcb = new(std::nothrow) ReadControlBlock( connection_handle, attribute_handle, offset @@ -1032,7 +1070,7 @@ ble_error_t GenericGattClient::write( const uint8_t* value ) const { // verify that there is no other procedures going on this connection - if (get_control_block(connection_handle)) { + if (_is_reseting || get_control_block(connection_handle)) { return BLE_ERROR_INVALID_STATE; } @@ -1058,7 +1096,7 @@ ble_error_t GenericGattClient::write( memcpy(data, value, length); } - write_control_block_t* write_pcb = new(std::nothrow) write_control_block_t( + WriteControlBlock* write_pcb = new(std::nothrow) WriteControlBlock( connection_handle, attribute_handle, data, @@ -1111,7 +1149,7 @@ ble_error_t GenericGattClient::discoverCharacteristicDescriptors( const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback ) { // verify that there is no other procedures going on this connection - if (get_control_block(characteristic.getConnectionHandle())) { + if (_is_reseting || get_control_block(characteristic.getConnectionHandle())) { return BLE_ERROR_INVALID_STATE; } @@ -1126,8 +1164,8 @@ ble_error_t GenericGattClient::discoverCharacteristicDescriptors( return BLE_ERROR_NONE; } - descriptor_discovery_control_block_t* discovery_pcb = - new(std::nothrow) descriptor_discovery_control_block_t( + DescriptorDiscoveryControlBlock* discovery_pcb = + new(std::nothrow) DescriptorDiscoveryControlBlock( characteristic, discoveryCallback, terminationCallback @@ -1152,11 +1190,11 @@ ble_error_t GenericGattClient::discoverCharacteristicDescriptors( bool GenericGattClient::isCharacteristicDescriptorDiscoveryActive( const DiscoveredCharacteristic& characteristic ) const { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == DESCRIPTOR_DISCOVERY_PROCEDURE && - static_cast(pcb)->characteristic == characteristic) { + static_cast(pcb)->characteristic == characteristic) { return true; } pcb = pcb->next; @@ -1168,12 +1206,12 @@ bool GenericGattClient::isCharacteristicDescriptorDiscoveryActive( void GenericGattClient::terminateCharacteristicDescriptorDiscovery( const DiscoveredCharacteristic& characteristic ) { - procedure_control_block_t* pcb = control_blocks; + ProcedureControlBlock* pcb = control_blocks; while (pcb) { if (pcb->type == DESCRIPTOR_DISCOVERY_PROCEDURE) { - descriptor_discovery_control_block_t* dpcb = - static_cast(pcb); + DescriptorDiscoveryControlBlock* dpcb = + static_cast(pcb); if (dpcb->characteristic == characteristic) { dpcb->done = true; return; @@ -1186,7 +1224,17 @@ void GenericGattClient::terminateCharacteristicDescriptorDiscovery( } ble_error_t GenericGattClient::reset(void) { - return BLE_ERROR_NOT_IMPLEMENTED; + + // _is_reseting prevent executions of new procedure while the instance resets. + // otherwise new procedures can be launched from callbacks generated by the + // reset. + _is_reseting = true; + while (control_blocks) { + control_blocks->abort(this); + } + _is_reseting = false; + + return BLE_ERROR_NONE; } void GenericGattClient::on_termination(Gap::Handle_t connection_handle) { @@ -1230,7 +1278,7 @@ void GenericGattClient::on_server_response( connection_handle_t connection, const AttServerMessage& message ) { - procedure_control_block_t* pcb = get_control_block(connection); + ProcedureControlBlock* pcb = get_control_block(connection); if (pcb == NULL) { return; } @@ -1270,7 +1318,7 @@ void GenericGattClient::on_server_event(connection_handle_t connection, const At } void GenericGattClient::on_transaction_timeout(connection_handle_t connection) { - procedure_control_block_t* pcb = get_control_block(connection); + ProcedureControlBlock* pcb = get_control_block(connection); if (pcb == NULL) { return; } @@ -1278,36 +1326,36 @@ void GenericGattClient::on_transaction_timeout(connection_handle_t connection) { pcb->handle_timeout_error(this); } -procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) { - procedure_control_block_t* it = control_blocks; +GenericGattClient::ProcedureControlBlock* GenericGattClient::get_control_block(Gap::Handle_t connection) { + ProcedureControlBlock* it = control_blocks; while (it && it->connection_handle != connection) { it = it->next; } return it; } -const procedure_control_block_t* GenericGattClient::get_control_block(Gap::Handle_t connection) const { - procedure_control_block_t* it = control_blocks; +const GenericGattClient::ProcedureControlBlock* GenericGattClient::get_control_block(Gap::Handle_t connection) const { + ProcedureControlBlock* it = control_blocks; while (it && it->connection_handle != connection) { it = it->next; } return it; } -void GenericGattClient::insert_control_block(procedure_control_block_t* cb) const { +void GenericGattClient::insert_control_block(ProcedureControlBlock* cb) const { if (control_blocks == NULL) { control_blocks = cb; return; } - procedure_control_block_t* current = control_blocks; + ProcedureControlBlock* current = control_blocks; while (current->next) { current = current->next; } current->next = cb; } -void GenericGattClient::remove_control_block(procedure_control_block_t* cb) const { +void GenericGattClient::remove_control_block(ProcedureControlBlock* cb) const { if (control_blocks == NULL) { return; } @@ -1317,7 +1365,7 @@ void GenericGattClient::remove_control_block(procedure_control_block_t* cb) cons return; } - procedure_control_block_t* current = control_blocks; + ProcedureControlBlock* current = control_blocks; while (current->next && current->next != cb) { current = current->next; } diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioBLE.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioBLE.h index da4b345a628..d31196a2758 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioBLE.h +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioBLE.h @@ -22,12 +22,15 @@ #include "ble/BLEInstanceBase.h" #include "CordioHCIDriver.h" -#include "CordioGap.h" #include "CordioGattServer.h" #include "CordioSecurityManager.h" #include "CordioPalAttClient.h" #include "ble/pal/AttClientToGattClientAdapter.h" #include "ble/generic/GenericGattClient.h" +#include "CordioPalGap.h" +#include "CordioPalGenericAccessService.h" +#include "ble/generic/GenericGap.h" +#include "ble/pal/SimpleEventQueue.h" namespace ble { namespace vendor { @@ -81,12 +84,12 @@ class BLE : public ::BLEInstanceBase { /** * @see BLEInstanceBase::getGap */ - virtual Gap& getGap(); + virtual ::Gap& getGap(); /** * @see BLEInstanceBase::getGap */ - virtual const Gap& getGap() const; + virtual const ::Gap& getGap() const; /** * @see BLEInstanceBase::getGattServer @@ -143,6 +146,7 @@ class BLE : public ::BLEInstanceBase { } initialization_status; ::BLE::InstanceID_t instanceID; + mutable pal::SimpleEventQueue _event_queue; }; } // namespace cordio diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioGap.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioGap.h deleted file mode 100644 index ab139d5b908..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioGap.h +++ /dev/null @@ -1,262 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef CORDIO_GAP_H_ -#define CORDIO_GAP_H_ - -#include -#include "ble/blecommon.h" -#include "ble/GapAdvertisingParams.h" -#include "ble/GapAdvertisingData.h" -#include "ble/Gap.h" -#include "ble/GapScanningParams.h" -#include "dm_api.h" -#include "att_api.h" - -namespace ble { -namespace vendor { -namespace cordio { - -/** - * @see ::Gap - */ -class Gap : public ::Gap -{ -public: - /** - * Return the Gap singleton implementing ::Gap for the Cordio stac. - */ - static Gap &getInstance(); - - /** - * This function shall be called once the stack has been initialized - */ - void initialize(); - - /** - * @see ::Gap::setAddress - */ - virtual ble_error_t setAddress(AddressType_t type, const Address_t address); - - /** - * @see ::Gap::getAddress - */ - virtual ble_error_t getAddress(AddressType_t *typeP, Address_t address); - - /** - * @see ::Gap::setAdvertisingData - */ - virtual ble_error_t setAdvertisingData( - const GapAdvertisingData&, const GapAdvertisingData& - ); - - /** - * @see ::Gap::connect - */ - virtual ble_error_t connect( - const BLEProtocol::AddressBytes_t peerAddr, - BLEProtocol::AddressType_t peerAddrType, - const ConnectionParams_t* connectionParams, - const GapScanningParams* scanParams - ); - - /** - * @see ::Gap::getMinAdvertisingInterval - */ - virtual uint16_t getMinAdvertisingInterval() const; - - /** - * @see ::Gap::getMinNonConnectableAdvertisingInterval - */ - virtual uint16_t getMinNonConnectableAdvertisingInterval() const; - - /** - * @see ::Gap::getMaxAdvertisingInterval - */ - virtual uint16_t getMaxAdvertisingInterval() const; - - /** - * @see ::Gap::startAdvertising - */ - virtual ble_error_t startAdvertising(const GapAdvertisingParams &); - - /** - * @see ::Gap::stopAdvertising - */ - virtual ble_error_t stopAdvertising(); - - /** - * @see ::Gap::disconnect - */ - virtual ble_error_t disconnect( - Handle_t connectionHandle, - DisconnectionReason_t reason - ); - - /** - * @see ::Gap::disconnect - */ - virtual ble_error_t disconnect(DisconnectionReason_t reason); - - /** - * @see ::Gap::setDeviceName - */ - virtual ble_error_t setDeviceName(const uint8_t *deviceName); - - /** - * @see ::Gap::getDeviceName - */ - virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP); - - /** - * @see ::Gap::setAppearance - */ - virtual ble_error_t setAppearance(GapAdvertisingData::Appearance appearance); - - /** - * @see ::Gap::getAppearance - */ - virtual ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP); - - /** - * @see ::Gap::setTxPower - */ - virtual ble_error_t setTxPower(int8_t txPower); - - /** - * @see ::Gap::getPermittedTxPowerValues - */ - virtual void getPermittedTxPowerValues( - const int8_t **valueArrayPP, size_t *countP - ); - - /** - * Set the internal connection handle - */ - void setConnectionHandle(uint16_t m_connectionHandle); - - /** - * Get the current connection handle - */ - uint16_t getConnectionHandle(); - - /** - * @see ::Gap::getPreferredConnectionParams - */ - virtual ble_error_t getPreferredConnectionParams(ConnectionParams_t *params); - - /** - * @see ::Gap::setPreferredConnectionParams - */ - virtual ble_error_t setPreferredConnectionParams( - const ConnectionParams_t *params - ); - - /** - * @see ::Gap::updateConnectionParams - */ - virtual ble_error_t updateConnectionParams( - Handle_t handle, const ConnectionParams_t *params - ); - - /** - * @see ::Gap::startRadioScan - */ - virtual ble_error_t startRadioScan(const GapScanningParams &scanningParams); - - /** - * @see ::Gap::stopScan - */ - virtual ble_error_t stopScan(); - - /** - * Called when advertising is stopped. - */ - void advertisingStopped(); - - // Whitelist management - - /** - * @see ::Gap::getMaxWhitelistSize - */ - virtual uint8_t getMaxWhitelistSize(void) const; - - /** - * @see ::Gap::getWhitelist - */ - virtual ble_error_t getWhitelist(Whitelist_t &whitelist) const; - - /** - * @see ::Gap::setWhitelist - */ - virtual ble_error_t setWhitelist(const Whitelist_t &whitelist); - - /** - * @see ::Gap::setAdvertisingPolicyMode - */ - virtual ble_error_t setAdvertisingPolicyMode(AdvertisingPolicyMode_t mode); - - /** - * @see ::Gap::getAdvertisingPolicyMode - */ - virtual AdvertisingPolicyMode_t getAdvertisingPolicyMode(void) const; - - /** - * @see ::Gap::setScanningPolicyMode - */ - virtual ble_error_t setScanningPolicyMode(ScanningPolicyMode_t mode); - - /** - * @see ::Gap::getScanningPolicyMode - */ - virtual ScanningPolicyMode_t getScanningPolicyMode(void) const; - - /** - * @see ::Gap::setInitiatorPolicyMode - */ - virtual ble_error_t setInitiatorPolicyMode(InitiatorPolicyMode_t mode); - - /** - * @see ::Gap::getInitiatorPolicyMode - */ - virtual InitiatorPolicyMode_t getInitiatorPolicyMode(void) const; - - /** - * @see ::Gap::reset - */ - virtual ble_error_t reset(void); - -private: - Gap(); - - Gap(Gap const &); - void operator=(Gap const &); - - uint16_t m_connectionHandle; - addr_type_t m_type; - Address_t m_addr; - - AdvertisingPolicyMode_t advertising_policy_mode; - ScanningPolicyMode_t scanning_policy_mode; - InitiatorPolicyMode_t initiator_policy_mode; - Whitelist_t whitelist; -}; - -} // namespace cordio -} // namespace vendor -} // namespace ble - -#endif /* CORDIO_GAP_H_ */ diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioPalGap.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioPalGap.h new file mode 100644 index 00000000000..e0379ed352b --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioPalGap.h @@ -0,0 +1,477 @@ +#ifndef CORDIO_PAL_GAP_ +#define CORDIO_PAL_GAP_ + +#include "ble/pal/PalGap.h" +#include "dm_api.h" + +namespace ble { +namespace pal { +namespace vendor { +namespace cordio { + +/** + * Implementation of ble::pal::Gap for the Cordio stack. + */ +class Gap : public ::ble::pal::Gap { + +public: + virtual ble_error_t initialize() { + return BLE_ERROR_NONE; + } + + virtual ble_error_t terminate() { + return BLE_ERROR_NONE; + } + + virtual address_t get_device_address() { + return address_t(HciGetBdAddr(), true); + } + + virtual address_t get_random_address() { + return device_random_address; + } + + virtual ble_error_t set_random_address(const address_t& address) { + device_random_address = address; + DmDevSetRandAddr(const_cast(address.data())); + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_advertising_parameters( + uint16_t advertising_interval_min, + uint16_t advertising_interval_max, + advertising_type_t advertising_type, + own_address_type_t own_address_type, + advertising_peer_address_type_t peer_address_type, + const address_t& peer_address, + advertising_channel_map_t advertising_channel_map, + advertising_filter_policy_t advertising_filter_policy + ) { + DmAdvSetInterval( + DM_ADV_HANDLE_DEFAULT, + advertising_interval_min, + advertising_interval_max + ); + + DmAdvSetAddrType(own_address_type.value()); + + DmAdvSetChannelMap( + DM_ADV_HANDLE_DEFAULT, + advertising_channel_map.value() + ); + + DmDevSetFilterPolicy( + DM_FILT_POLICY_MODE_ADV, + advertising_filter_policy.value() + ); + + DmAdvConfig( + DM_ADV_HANDLE_DEFAULT, + advertising_type.value(), + peer_address_type.value(), + const_cast(peer_address.data()) + ); + + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_advertising_data( + uint8_t advertising_data_length, + const advertising_data_t& advertising_data + ) { + DmAdvSetData( + DM_ADV_HANDLE_DEFAULT, + HCI_ADV_DATA_OP_COMP_FRAG, + DM_DATA_LOC_ADV, + advertising_data_length, + const_cast(advertising_data.data()) + ); + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_scan_response_data( + uint8_t scan_response_data_length, + const advertising_data_t& scan_response_data + ) { + DmAdvSetData( + DM_ADV_HANDLE_DEFAULT, + HCI_ADV_DATA_OP_COMP_FRAG, + DM_DATA_LOC_SCAN, + scan_response_data_length, + const_cast(scan_response_data.data()) + ); + return BLE_ERROR_NONE; + } + + virtual ble_error_t advertising_enable(bool enable) { + if (enable) { + uint8_t adv_handles[] = { DM_ADV_HANDLE_DEFAULT }; + uint16_t adv_durations[] = { /* infinite */ 0 }; + uint8_t max_ea_events[] = { 0 }; + DmAdvStart(1, adv_handles, adv_durations, max_ea_events); + } else { + uint8_t adv_handles[] = { DM_ADV_HANDLE_DEFAULT }; + DmAdvStop(1, adv_handles); + } + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_scan_parameters( + bool active_scanning, + uint16_t scan_interval, + uint16_t scan_window, + own_address_type_t own_address_type, + scanning_filter_policy_t filter_policy + ) { + use_active_scanning = active_scanning; + DmScanSetInterval(HCI_INIT_PHY_LE_1M_BIT, &scan_interval, &scan_window); + DmScanSetAddrType(own_address_type.value()); + DmDevSetFilterPolicy( + DM_FILT_POLICY_MODE_SCAN, + filter_policy.value() + ); + return BLE_ERROR_NONE; + } + + virtual ble_error_t scan_enable( + bool enable, + bool filter_duplicates + ) { + if (enable) { + uint8_t scanType = use_active_scanning ? DM_SCAN_TYPE_ACTIVE : DM_SCAN_TYPE_PASSIVE; + DmScanStart( + HCI_SCAN_PHY_LE_1M_BIT, + DM_DISC_MODE_NONE, + &scanType, + filter_duplicates, + 0, + 0 + ); + } else { + DmScanStop(); + } + return BLE_ERROR_NONE; + } + + virtual ble_error_t create_connection( + uint16_t scan_interval, + uint16_t scan_window, + initiator_policy_t initiator_policy, + connection_peer_address_type_t peer_address_type, + const address_t& peer_address, + own_address_type_t own_address_type, + uint16_t connection_interval_min, + uint16_t connection_interval_max, + uint16_t connection_latency, + uint16_t supervision_timeout, + uint16_t minimum_connection_event_length, + uint16_t maximum_connection_event_length + ) { + DmConnSetScanInterval(scan_interval, scan_window); + DmDevSetFilterPolicy(DM_FILT_POLICY_MODE_INIT, initiator_policy.value()); + DmConnSetAddrType(own_address_type.value()); + + hciConnSpec_t conn_spec = { + connection_interval_min, + connection_interval_max, + connection_latency, + supervision_timeout, + minimum_connection_event_length, + maximum_connection_event_length + }; + DmConnSetConnSpec(&conn_spec); + + dmConnId_t connection_id = DmConnOpen( + DM_CLIENT_ID_APP, + HCI_INIT_PHY_LE_1M_BIT, + peer_address_type.value(), + const_cast(peer_address.data()) + ); + + if (connection_id == DM_CONN_ID_NONE) { + return BLE_ERROR_INTERNAL_STACK_FAILURE; + } + + return BLE_ERROR_NONE; + } + + virtual ble_error_t cancel_connection_creation() { + DmConnClose( + DM_CLIENT_ID_APP, + /* connection handle - invalid */ DM_CONN_ID_NONE, + /* reason - invalid (use success) */ 0x00 + ); + return BLE_ERROR_NONE; + } + + virtual uint8_t read_white_list_capacity() { + return HciGetWhiteListSize(); + } + + virtual ble_error_t clear_whitelist() { + DmDevWhiteListClear(); + return BLE_ERROR_NONE; + } + + virtual ble_error_t add_device_to_whitelist( + whitelist_address_type_t address_type, + address_t address + ) { + DmDevWhiteListAdd( + address_type.value(), + const_cast(address.data()) + ); + return BLE_ERROR_NONE; + } + + virtual ble_error_t remove_device_from_whitelist( + whitelist_address_type_t address_type, + address_t address + ) { + DmDevWhiteListRemove( + address_type.value(), + const_cast(address.data()) + ); + return BLE_ERROR_NONE; + } + + virtual ble_error_t connection_parameters_update( + connection_handle_t connection, + uint16_t connection_interval_min, + uint16_t connection_interval_max, + uint16_t connection_latency, + uint16_t supervision_timeout, + uint16_t minimum_connection_event_length, + uint16_t maximum_connection_event_length + ) { + if (DmConnCheckIdle(connection) != 0) { + return BLE_ERROR_INVALID_STATE; + } + + hciConnSpec_t connection_spec = { + connection_interval_min, + connection_interval_max, + connection_latency, + supervision_timeout, + minimum_connection_event_length, + maximum_connection_event_length + }; + DmConnUpdate( + connection, + &connection_spec + ); + + return BLE_ERROR_NONE; + } + + virtual ble_error_t accept_connection_parameter_request( + connection_handle_t connection_handle, + uint16_t interval_min, + uint16_t interval_max, + uint16_t latency, + uint16_t supervision_timeout, + uint16_t minimum_connection_event_length, + uint16_t maximum_connection_event_length + ) { + hciConnSpec_t connection_spec = { + interval_min, + interval_max, + latency, + supervision_timeout, + minimum_connection_event_length, + maximum_connection_event_length + }; + DmRemoteConnParamReqReply(connection_handle, &connection_spec); + return BLE_ERROR_NONE; + } + + virtual ble_error_t reject_connection_parameter_request( + connection_handle_t connection_handle, + hci_error_code_t rejection_reason + ) { + DmRemoteConnParamReqNegReply( + connection_handle, + rejection_reason.value() + ); + return BLE_ERROR_NONE; + } + + virtual ble_error_t disconnect( + connection_handle_t connection, + disconnection_reason_t disconnection_reason + ) { + DmConnClose( + DM_CLIENT_ID_APP, + connection, + disconnection_reason.value() + ); + return BLE_ERROR_NONE; + } + + // singleton of the ARM Cordio client + static Gap& get_gap() { + static Gap _gap; + return _gap; + } + +private: + typedef bool (*event_handler_t)(const wsfMsgHdr_t* msg); + +public: + /** + * Callback which handle wsfMsgHdr_t and forward them to emit_gap_event. + */ + static void gap_handler(const wsfMsgHdr_t* msg) { + if (msg == NULL) { + return; + } + + // all handlers are stored in a static array + static const event_handler_t handlers[] = { + &event_handler, + &event_handler, + &event_handler, + &event_handler, + &event_handler + }; + + // event->hdr.param: connection handle + + // traverse all handlers and execute them with the event in input. + // exit if an handler has handled the event. + for(size_t i = 0; i < (sizeof(handlers)/sizeof(handlers[0])); ++i) { + if (handlers[i](msg)) { + return; + } + } + } + +private: + /** + * T shall define a can_convert and convert function and a type + */ + template + static bool event_handler(const wsfMsgHdr_t* msg) { + if (T::can_convert(msg)) { + get_gap().emit_gap_event(T::convert((const typename T::type*)msg)); + return true; + } + return false; + } + + /** + * Traits defining can_convert for events. + */ + template + struct MessageConverter { + static bool can_convert(const wsfMsgHdr_t* msg) { + if (msg->event == EventID) { + return true; + } + return false; + } + }; + + struct ConnectionCompleteMessageConverter : public MessageConverter { + typedef hciLeConnCmplEvt_t type; + + static GapConnectionCompleteEvent convert(const hciLeConnCmplEvt_t* conn_evt) { + return GapConnectionCompleteEvent( + conn_evt->status, + // note the usage of the stack handle, not the HCI handle + conn_evt->hdr.param, + (connection_role_t::type) conn_evt->role, + (advertising_peer_address_type_t::type) conn_evt->addrType, + conn_evt->peerAddr, + conn_evt->connInterval, + conn_evt->connLatency, + conn_evt->supTimeout + ); + } + }; + + struct GapAdvertisingReportMessageConverter : public MessageConverter { + typedef hciLeAdvReportEvt_t type; + + struct CordioGapAdvertisingReportEvent : public GapAdvertisingReportEvent { + CordioGapAdvertisingReportEvent(const advertising_t& advertising) : + GapAdvertisingReportEvent(), advertising(advertising) { + } + + virtual ~CordioGapAdvertisingReportEvent() { } + + virtual uint8_t size() const { + return 1; + } + + virtual advertising_t operator[](uint8_t i) const { + return advertising; + } + + advertising_t advertising; + }; + + static CordioGapAdvertisingReportEvent convert(const hciLeAdvReportEvt_t *scan_report) { + GapAdvertisingReportEvent::advertising_t advertising = { + (received_advertising_type_t::type) scan_report->eventType, + (connection_peer_address_type_t::type) scan_report->addrType, + scan_report->addr, + make_const_ArrayView(scan_report->pData, scan_report->len), + scan_report->rssi + }; + return CordioGapAdvertisingReportEvent(advertising); + } + }; + + struct DisconnectionMessageConverter : public MessageConverter { + typedef hciDisconnectCmplEvt_t type; + + static GapDisconnectionCompleteEvent convert(const hciDisconnectCmplEvt_t* disc_evt) { + return GapDisconnectionCompleteEvent( + disc_evt->status, + // note the usage of the stack handle, not the HCI handle + disc_evt->hdr.param, + disc_evt->reason + ); + } + }; + + struct ConnectionUpdateMessageConverter : public MessageConverter { + typedef hciLeConnUpdateCmplEvt_t type; + + static GapConnectionUpdateEvent convert(const hciLeConnUpdateCmplEvt_t* evt) { + return GapConnectionUpdateEvent( + evt->status, + evt->hdr.param, + evt->connInterval, + evt->connLatency, + evt->supTimeout + ); + } + }; + + struct RemoteConnectionParameterRequestMessageConverter : public MessageConverter { + typedef hciLeRemConnParamReqEvt_t type; + + static GapRemoteConnectionParameterRequestEvent convert(const hciLeRemConnParamReqEvt_t* evt) { + return GapRemoteConnectionParameterRequestEvent( + evt->hdr.param, + evt->intervalMin, + evt->intervalMax, + evt->latency, + evt->timeout + ); + } + }; + +private: + address_t device_random_address; + bool use_active_scanning; +}; + +} // cordio +} // vendor +} // pal +} // ble + +#endif /* CORDIO_PAL_GAP_ */ diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioPalGenericAccessService.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioPalGenericAccessService.h new file mode 100644 index 00000000000..1eb4dcd5dff --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/CordioPalGenericAccessService.h @@ -0,0 +1,88 @@ +#ifndef CORDIO_PAL_GENERIC_ACCESS_SERVICE_ +#define CORDIO_PAL_GENERIC_ACCESS_SERVICE_ + +#include "ble/pal/GenericAccessService.h" +#include "CordioGattServer.h" + + +namespace ble { +namespace pal { +namespace vendor { +namespace cordio { + +/** + * Implementation of ble::pal::GenericAccessService for the Cordio stack. + */ +class GenericAccessService : public ::ble::pal::GenericAccessService { +public: + GenericAccessService() { } + + virtual ~GenericAccessService() { } + + virtual ble_error_t get_device_name_length(uint8_t& length) { + const uint8_t* name = NULL; + uint16_t actual_length = 0; + + gatt_server().getDeviceName(name, actual_length); + length = actual_length; + return BLE_ERROR_NONE; + } + + virtual ble_error_t get_device_name(ArrayView& array) { + const uint8_t* name = NULL; + uint16_t length = 0; + + gatt_server().getDeviceName(name, length); + + if (length > array.size()) { + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } + + memcpy(array.data(), name, length); + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_device_name(const uint8_t* device_name) { + return gatt_server().setDeviceName(device_name); + } + + virtual ble_error_t get_appearance( + GapAdvertisingData::Appearance& appearance + ) { + appearance = gatt_server().getAppearance(); + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_appearance( + GapAdvertisingData::Appearance appearance + ) { + gatt_server().setAppearance(appearance); + return BLE_ERROR_NONE; + } + + virtual ble_error_t get_peripheral_prefered_connection_parameters( + ::Gap::ConnectionParams_t& parameters + ) { + parameters = gatt_server().getPreferredConnectionParams(); + return BLE_ERROR_NONE; + } + + virtual ble_error_t set_peripheral_prefered_connection_parameters( + const ::Gap::ConnectionParams_t& parameters + ) { + gatt_server().setPreferredConnectionParams(parameters); + return BLE_ERROR_NONE; + } + +private: + ble::vendor::cordio::GattServer& gatt_server() { + return ble::vendor::cordio::GattServer::getInstance(); + } +}; + +} // cordio +} // vendor +} // pal +} // ble + +#endif /* CORDIO_PAL_GENERIC_ACCESS_SERVICE_ */ diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioBLE.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioBLE.cpp index ba2d5e15bd0..9a4c8325a86 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioBLE.cpp +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioBLE.cpp @@ -39,9 +39,6 @@ /*! WSF handler ID */ wsfHandlerId_t stack_handler_id; -/* Store the Event signaling state */ -bool isEventsSignaled = false; - /** * Weak definition of ble_cordio_get_hci_driver. * A runtime error is generated if the user does not define any @@ -78,10 +75,7 @@ extern "C" void hci_mbed_os_handle_reset_sequence(uint8_t* msg) */ extern "C" void wsf_mbed_ble_signal_event(void) { - if(isEventsSignaled == false) { - isEventsSignaled = true; - ble::vendor::cordio::BLE::deviceInstance().signalEventsToProcess(::BLE::DEFAULT_INSTANCE); - } + ble::vendor::cordio::BLE::deviceInstance().signalEventsToProcess(::BLE::DEFAULT_INSTANCE); } /** @@ -99,7 +93,8 @@ namespace cordio { BLE::BLE(CordioHCIDriver& hci_driver) : initialization_status(NOT_INITIALIZED), - instanceID(::BLE::DEFAULT_INSTANCE) + instanceID(::BLE::DEFAULT_INSTANCE), + _event_queue() { _hci_driver = &hci_driver; stack_setup(); @@ -122,9 +117,9 @@ ble_error_t BLE::init( ::BLE::InstanceID_t instanceID, FunctionPointerWithContext< ::BLE::InitializationCompleteCallbackContext *> initCallback) { - switch (initialization_status) { case NOT_INITIALIZED: + _event_queue.initialize(this, instanceID); _init_callback = initCallback; start_stack_reset(); return BLE_ERROR_NONE; @@ -157,6 +152,7 @@ ble_error_t BLE::shutdown() getGattServer().reset(); getGattClient().reset(); getGap().reset(); + _event_queue.clear(); return BLE_ERROR_NONE; } @@ -167,15 +163,25 @@ const char* BLE::getVersion() return version; } -Gap& BLE::getGap() +::Gap& BLE::getGap() { - return cordio::Gap::getInstance(); + typedef ::Gap& return_type; + const BLE* self = this; + return const_cast(self->getGap()); } -const Gap& BLE::getGap() const +const ::Gap& BLE::getGap() const { - return cordio::Gap::getInstance(); -} + static pal::vendor::cordio::Gap& cordio_pal_gap = + pal::vendor::cordio::Gap::get_gap(); + static pal::vendor::cordio::GenericAccessService cordio_gap_service; + static ble::generic::GenericGap gap( + _event_queue, + cordio_pal_gap, + cordio_gap_service + ); + return gap; +}; GattServer& BLE::getGattServer() { @@ -226,11 +232,8 @@ void BLE::waitForEvent() void BLE::processEvents() { - if (isEventsSignaled) { - isEventsSignaled = false; - callDispatcher(); - } - } + callDispatcher(); +} void BLE::stack_handler(wsfEventMask_t event, wsfMsgHdr_t* msg) { @@ -245,66 +248,12 @@ void BLE::processEvents() BLE_ERROR_NONE }; deviceInstance().getGattServer().initialize(); - deviceInstance().getGap().initialize(); deviceInstance().initialization_status = INITIALIZED; _init_callback.call(&context); } break; - case DM_ADV_START_IND: - break; - - case DM_ADV_STOP_IND: - Gap::getInstance().advertisingStopped(); - break; - - case DM_SCAN_REPORT_IND: { - hciLeAdvReportEvt_t *scan_report = (hciLeAdvReportEvt_t*) msg; - Gap::getInstance().processAdvertisementReport( - scan_report->addr, - scan_report->rssi, - (scan_report->eventType == DM_RPT_SCAN_RESPONSE) ? true : false, - (GapAdvertisingParams::AdvertisingType_t) scan_report->eventType, - scan_report->len, - scan_report->pData - ); - } break; - - case DM_CONN_OPEN_IND: { - hciLeConnCmplEvt_t* conn_evt = (hciLeConnCmplEvt_t*) msg; - dmConnId_t connection_id = conn_evt->hdr.param; - Gap::getInstance().setConnectionHandle(connection_id); - Gap::AddressType_t own_addr_type; - Gap::Address_t own_addr; - Gap::getInstance().getAddress(&own_addr_type, own_addr); - - Gap::ConnectionParams_t params = { - conn_evt->connInterval, - conn_evt->connInterval, - conn_evt->connLatency, - conn_evt->supTimeout - }; - - Gap::getInstance().processConnectionEvent( - connection_id, - (conn_evt->role == DM_ROLE_MASTER) ? Gap::CENTRAL : Gap::PERIPHERAL, - (Gap::AddressType_t) conn_evt->addrType, - conn_evt->peerAddr, - own_addr_type, - own_addr, - ¶ms - ); - } break; - - case DM_CONN_CLOSE_IND: { - dmEvt_t *disconnect_evt = (dmEvt_t*) msg; - Gap::getInstance().setConnectionHandle(DM_CONN_ID_NONE); - Gap::getInstance().processDisconnectionEvent( - disconnect_evt->hdr.param, - (Gap::DisconnectionReason_t) disconnect_evt->connClose.reason - ); - } break; - default: + ble::pal::vendor::cordio::Gap::gap_handler(msg); break; } } @@ -419,6 +368,10 @@ void BLE::start_stack_reset() void BLE::callDispatcher() { + // process the external event queue + _event_queue.process(); + + // follow by stack events static uint32_t lastTimeUs = us_ticker_read(); uint32_t currTimeUs, deltaTimeMs; diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGap.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGap.cpp deleted file mode 100644 index 450a2def4bc..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGap.cpp +++ /dev/null @@ -1,543 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#include "CordioGap.h" -#include "mbed.h" -#include "dm_api.h" -#include "CordioGattServer.h" -#include "hci_core.h" - -/**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ -#define BLE_GAP_ADV_INTERVAL_MIN 0x0020 - -/**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */ -#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 - -/**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ -#define BLE_GAP_ADV_INTERVAL_MAX 0x4000 - -namespace ble { -namespace vendor { -namespace cordio { - -Gap &Gap::getInstance() -{ - static Gap m_instance; - return m_instance; -} - -void Gap::initialize() -{ - uint8_t whitelist_size = HciGetWhiteListSize(); - - if (whitelist_size == 0) { - return; - } - - whitelist.addresses = new(std::nothrow) BLEProtocol::Address_t[whitelist_size]; - if (whitelist.addresses == NULL) { - return; - } - - whitelist.size = 0; - whitelist.capacity = hciCoreCb.whiteListSize; -} - -ble_error_t Gap::setAddress(AddressType_t type, const Address_t address) -{ - switch (type) { - case BLEProtocol::AddressType::PUBLIC: - // TODO: use vendor specific commands from the driver - return BLE_ERROR_OPERATION_NOT_PERMITTED; - - // See bluetooth 5, Vol 6 part, part B, 1.3.2 - case BLEProtocol::AddressType::RANDOM_STATIC: - if ((address[5] >> 6) != 3) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - m_type = type; - BdaCpy(m_addr, address); - DmDevSetRandAddr(m_addr); - break; - - // should not be here, generation is supposed to be handled by the controller. - case BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE: - case BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE: - m_type = type; - return BLE_ERROR_NONE; - - default: - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - DmAdvSetAddrType(m_type); - DmConnSetAddrType(m_type); - DmScanSetAddrType(m_type); - return BLE_ERROR_NONE; -} - -ble_error_t Gap::getAddress(AddressType_t *typeP, Address_t address) -{ - *typeP = m_type; - - if(m_type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE || - m_type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE) { - return BLE_ERROR_NONE; - } - - BdaCpy(address, m_addr); - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setAdvertisingData(const GapAdvertisingData &advData, const GapAdvertisingData &scanResponse) -{ - /* Make sure we don't exceed the advertising payload length */ - if (advData.getPayloadLen() > GAP_ADVERTISING_DATA_MAX_PAYLOAD) { - return BLE_ERROR_BUFFER_OVERFLOW; - } - - /* Make sure we have a payload! */ - if (advData.getPayloadLen() == 0) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - /* set advertising and scan response data for discoverable mode */ - DmAdvSetData(DM_ADV_HANDLE_DEFAULT, HCI_ADV_DATA_OP_COMP_FRAG, DM_DATA_LOC_ADV, advData.getPayloadLen(), (uint8_t*)advData.getPayload()); - DmAdvSetData(DM_ADV_HANDLE_DEFAULT, HCI_ADV_DATA_OP_COMP_FRAG, DM_DATA_LOC_SCAN, scanResponse.getPayloadLen(), (uint8_t*)scanResponse.getPayload()); - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::connect( - const BLEProtocol::AddressBytes_t peerAddr, - BLEProtocol::AddressType_t peerAddrType, - const ConnectionParams_t* connectionParams, - const GapScanningParams* scanParams -) { - // prepare the scan interval - if (scanParams != NULL) { - DmConnSetScanInterval(scanParams->getInterval(), scanParams->getWindow()); - } - - if (connectionParams != NULL) { - hciConnSpec_t conn_spec = { - /* connIntervalMin */ connectionParams->minConnectionInterval, - /* connIntervalMax */ connectionParams->maxConnectionInterval, - /* connLatency */ connectionParams->slaveLatency, - /* supTimeout */ connectionParams->connectionSupervisionTimeout, - /* minCeLen */ DM_GAP_CONN_EST_MIN_CE_LEN, - /* maxCeLen */ DM_GAP_CONN_EST_MAX_CE_LEN - }; - DmConnSetConnSpec(&conn_spec); - } - - DmScanStop(); - dmConnId_t connection_id = DmConnOpen( - DM_CLIENT_ID_APP, - HCI_INIT_PHY_LE_1M_BIT, - peerAddrType, - (uint8_t*) peerAddr - ); - - if (connection_id == DM_CONN_ID_NONE) { - return BLE_ERROR_INTERNAL_STACK_FAILURE; - } - - return BLE_ERROR_NONE; -} - -uint16_t Gap::getMinAdvertisingInterval() const -{ - return BLE_GAP_ADV_INTERVAL_MIN; -} - -uint16_t Gap::getMinNonConnectableAdvertisingInterval() const -{ - return BLE_GAP_ADV_NONCON_INTERVAL_MIN; -} - -uint16_t Gap::getMaxAdvertisingInterval() const -{ - return BLE_GAP_ADV_INTERVAL_MAX; -} - -ble_error_t Gap::startAdvertising(const GapAdvertisingParams ¶ms) -{ - /* Make sure we support the advertising type */ - if (params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) { - /* ToDo: This requires a proper security implementation, etc. */ - return BLE_ERROR_NOT_IMPLEMENTED; - } - - /* Check interval range */ - if (params.getAdvertisingType() == GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED) { - /* Min delay is slightly longer for unconnectable devices */ - if ((params.getIntervalInADVUnits() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN_NONCON) || - (params.getIntervalInADVUnits() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - } else { - if ((params.getIntervalInADVUnits() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN) || - (params.getIntervalInADVUnits() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - } - - /* Check timeout is zero for Connectable Directed */ - if ((params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) && (params.getTimeout() != 0)) { - /* Timeout must be 0 with this type, although we'll never get here */ - /* since this isn't implemented yet anyway */ - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - /* Check timeout for other advertising types */ - if ((params.getAdvertisingType() != GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) && - (params.getTimeout() > GapAdvertisingParams::GAP_ADV_PARAMS_TIMEOUT_MAX)) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - uint16_t adv_interval_min = params.getIntervalInADVUnits(); - if (adv_interval_min == GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX) { - --adv_interval_min; - } - uint16_t adv_interval_max = adv_interval_min + 1; - - DmAdvSetInterval(DM_ADV_HANDLE_DEFAULT, adv_interval_min, adv_interval_max); - - /* Peer Addr Type 0 = Public */ - uint8_t peerAddrType = 0; - uint8_t peerAddr[6] = { 0 }; - DmAdvConfig(DM_ADV_HANDLE_DEFAULT, params.getAdvertisingType(), peerAddrType, peerAddr); - - uint8_t adv_handles[] = { DM_ADV_HANDLE_DEFAULT }; - uint16_t adv_durations[] = { (uint16_t) (params.getTimeout() * 1000) }; - uint8_t max_ea_events[] = { 0 }; - DmAdvStart(1, adv_handles, adv_durations, max_ea_events); - - state.advertising = 1; - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::stopAdvertising(void) -{ - uint8_t adv_handles[] = { DM_ADV_HANDLE_DEFAULT }; - DmAdvStop(1, adv_handles); - - state.advertising = 0; - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::disconnect(Handle_t connectionHandle, DisconnectionReason_t reason) -{ - DmConnClose(DM_CLIENT_ID_APP, connectionHandle, reason); - - state.advertising = 0; - state.connected = 0; - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::disconnect(DisconnectionReason_t reason) -{ - DmConnClose(DM_CLIENT_ID_APP, m_connectionHandle, reason); - - state.advertising = 0; - state.connected = 0; - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setDeviceName(const uint8_t *deviceName) -{ - return GattServer::getInstance().setDeviceName(deviceName); -} - -ble_error_t Gap::getDeviceName(uint8_t *deviceName, unsigned *lengthP) -{ - const uint8_t* name = NULL; - uint16_t length = 0; - - GattServer::getInstance().getDeviceName(name, length); - - if (deviceName != NULL) { - memcpy(deviceName, name, std::min((uint16_t) *lengthP, length)); - } - - *lengthP = length; - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setAppearance(GapAdvertisingData::Appearance appearance) -{ - GattServer::getInstance().setAppearance(appearance); - return BLE_ERROR_NONE; -} - -ble_error_t Gap::getAppearance(GapAdvertisingData::Appearance *appearanceP) -{ - *appearanceP = GattServer::getInstance().getAppearance(); - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setTxPower(int8_t txPower) -{ -#if 0 - HciVsSetTxPower(txPower); - return BLE_ERROR_NONE; -#else - return BLE_ERROR_NOT_IMPLEMENTED; -#endif -} - -void Gap::getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP) -{ - *valueArrayPP = NULL; - *countP = 0; -} - -void Gap::setConnectionHandle(uint16_t connectionHandle) -{ - m_connectionHandle = connectionHandle; -} - -uint16_t Gap::getConnectionHandle(void) -{ - return m_connectionHandle; -} - -ble_error_t Gap::getPreferredConnectionParams(ConnectionParams_t *params) -{ - *params = GattServer::getInstance().getPreferredConnectionParams(); - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setPreferredConnectionParams(const ConnectionParams_t *params) -{ - // ensure that parameters are correct - // see BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part C] - // section 12.3 PERIPHERAL PREFERRED CONNECTION PARAMETERS CHARACTERISTIC - if (((0x0006 > params->minConnectionInterval) || (params->minConnectionInterval > 0x0C80)) && - params->minConnectionInterval != 0xFFFF) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - if (((params->minConnectionInterval > params->maxConnectionInterval) || (params->maxConnectionInterval > 0x0C80)) && - params->maxConnectionInterval != 0xFFFF) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - if (params->slaveLatency > 0x01F3) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - if (((0x000A > params->connectionSupervisionTimeout) || (params->connectionSupervisionTimeout > 0x0C80)) && - params->connectionSupervisionTimeout != 0xFFFF) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - GattServer::getInstance().setPreferredConnectionParams(*params); - return BLE_ERROR_NONE; -} - -ble_error_t Gap::updateConnectionParams(Handle_t handle, const ConnectionParams_t *newParams) -{ - if (DmConnCheckIdle(handle) != 0) { - return BLE_STACK_BUSY; - } - - hciConnSpec_t connSpec; - connSpec.connIntervalMin = newParams->minConnectionInterval; - connSpec.connIntervalMax = newParams->maxConnectionInterval; - connSpec.connLatency = newParams->slaveLatency; - connSpec.supTimeout = newParams->connectionSupervisionTimeout; - DmConnUpdate(handle, &connSpec); - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::startRadioScan(const GapScanningParams &scanningParams) -{ - // not needed to start scanning if the whitelist is empty and the scanning - // policy filter all the advertising packets - if ((whitelist.size == 0) && (scanning_policy_mode == Gap::SCAN_POLICY_FILTER_ALL_ADV)) { - return BLE_ERROR_INVALID_STATE; - } - - uint16_t scan_intervals[] = { scanningParams.getInterval() }; - uint16_t scan_windows[] = { scanningParams.getWindow() }; - - DmScanSetInterval(HCI_SCAN_PHY_LE_1M_BIT, scan_intervals, scan_windows); - - uint8_t scanType = scanningParams.getActiveScanning() ? DM_SCAN_TYPE_ACTIVE : DM_SCAN_TYPE_PASSIVE; - uint32_t duration = (uint32_t)scanningParams.getTimeout() * 1000; - if (duration > 0xFFFF) { - // saturate to 16-bits - duration = 0xFFFF; - } - - DmScanStart(HCI_SCAN_PHY_LE_1M_BIT, DM_DISC_MODE_NONE, &scanType, TRUE, duration, 0); - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::stopScan(void) -{ - DmScanStop(); - return BLE_ERROR_NONE; -} - -void Gap::advertisingStopped(void) -{ - /* If advertising stopped due to a call to stopAdvertising(), state.advertising will - * be '0.' Otherwise, advertising must have stopped due to a timeout - */ - if (state.advertising) { - processTimeoutEvent(Gap::TIMEOUT_SRC_ADVERTISING); - } -} - -uint8_t Gap::getMaxWhitelistSize(void) const -{ - return whitelist.capacity; -} - -ble_error_t Gap::getWhitelist(Whitelist_t &other) const -{ - // i is a shorthand for other.size - uint8_t& i = other.size; - - for (i = 0; (i < whitelist.capacity) && (i < other.capacity); ++i) { - other.addresses[i] = whitelist.addresses[i]; - } - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setWhitelist(const Whitelist_t& other) -{ - if (other.capacity > whitelist.capacity) { - return BLE_ERROR_PARAM_OUT_OF_RANGE; - } - - // note : can be improved by sending the diff instead of the full list - - DmDevWhiteListClear(); - - // alias i to whitelist.size - uint8_t& i = whitelist.size; - - for (i = 0; (i < other.capacity) && (i < whitelist.capacity); ++i) { - whitelist.addresses[i] = other.addresses[i]; - DmDevWhiteListAdd( - (whitelist.addresses[i].type > 1) ? 0xFF : whitelist.addresses[i].type, - whitelist.addresses[i].address - ); - } - - return BLE_ERROR_NONE; -} - -ble_error_t Gap::setAdvertisingPolicyMode(AdvertisingPolicyMode_t mode) -{ - bool_t result = DmDevSetFilterPolicy( - DM_FILT_POLICY_MODE_ADV, - mode - ); - - if (result == false) { - return BLE_ERROR_INVALID_STATE; - } - - advertising_policy_mode = mode; - return BLE_ERROR_NONE; -} - -Gap::AdvertisingPolicyMode_t Gap::getAdvertisingPolicyMode(void) const -{ - return advertising_policy_mode; -} - -ble_error_t Gap::setScanningPolicyMode(ScanningPolicyMode_t mode) -{ - bool_t result = DmDevSetFilterPolicy( - DM_FILT_POLICY_MODE_SCAN, - mode - ); - - if (result == false) { - return BLE_ERROR_INVALID_STATE; - } - - scanning_policy_mode = mode; - return BLE_ERROR_NONE; - -} - -Gap::ScanningPolicyMode_t Gap::getScanningPolicyMode(void) const -{ - return scanning_policy_mode; -} - -ble_error_t Gap::setInitiatorPolicyMode(InitiatorPolicyMode_t mode) -{ - bool_t result = DmDevSetFilterPolicy( - DM_FILT_POLICY_MODE_INIT, - mode - ); - - if (result == false) { - return BLE_ERROR_INVALID_STATE; - } - - initiator_policy_mode = mode; - return BLE_ERROR_NONE; -} - -Gap::InitiatorPolicyMode_t Gap::getInitiatorPolicyMode(void) const -{ - return initiator_policy_mode; -} - -ble_error_t Gap::reset(void) -{ - this->::Gap::reset(); - delete[] whitelist.addresses; - whitelist.addresses = NULL; - whitelist.size = 0; - whitelist.capacity = 0; - return BLE_ERROR_NONE; -} - -Gap::Gap() : - ::Gap(), - m_connectionHandle(DM_CONN_ID_NONE), - m_type(BLEProtocol::AddressType::RANDOM_STATIC), - m_addr(), - advertising_policy_mode(ADV_POLICY_IGNORE_WHITELIST), - scanning_policy_mode(SCAN_POLICY_IGNORE_WHITELIST), - initiator_policy_mode(INIT_POLICY_IGNORE_WHITELIST), - whitelist() -{ -} - -} // namespace cordio -} // namespace vendor -} // namespace ble diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp index 6f1a68da17f..79173e39c90 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp @@ -16,7 +16,6 @@ #include #include "CordioGattServer.h" -#include "CordioGap.h" #include "mbed.h" #include "wsf_types.h" #include "att_api.h" @@ -286,33 +285,63 @@ ble_error_t GattServer::read(Gap::Handle_t connectionHandle, GattAttribute::Hand ble_error_t GattServer::write(GattAttribute::Handle_t attributeHandle, const uint8_t buffer[], uint16_t len, bool localOnly) { - uint16_t connectionHandle = Gap::getInstance().getConnectionHandle(); + // Check to see if this is a CCCD, if it is the case update the value for all + // connections + uint8_t idx; + for (idx = 0; idx < cccCnt; idx++) { + if (attributeHandle == cccSet[idx].handle) { + for (uint16_t conn_id = 0, conn_found = 0; (conn_found < DM_CONN_MAX) && (conn_id < 0x100); ++conn_id) { + if (DmConnInUse(conn_id) == true) { + ++conn_found; + } else { + continue; + } + AttsCccSet(conn_id, idx, *((uint16_t*)buffer)); + } + return BLE_ERROR_NONE; + } + } + + // write the value to the attribute handle if (AttsSetAttr(attributeHandle, len, (uint8_t*)buffer) != ATT_SUCCESS) { return BLE_ERROR_PARAM_OUT_OF_RANGE; } - if (!localOnly) { - if (connectionHandle != DM_CONN_ID_NONE) { + // return if the update does not have to be propagated to peers + if (localOnly) { + return BLE_ERROR_NONE; + } - // Check to see if this characteristic has a CCCD attribute - uint8_t idx; - for (idx = 0; idx < cccCnt; idx++) { - if (attributeHandle == cccHandles[idx]) { - break; - } + // Check to see if this characteristic has a CCCD attribute + for (idx = 0; idx < cccCnt; idx++) { + if (attributeHandle == cccHandles[idx]) { + break; + } + } + + // exit if the characteristic has no CCCD attribute + if (idx >= cccCnt) { + return BLE_ERROR_NONE; + } + + // This characteristic has a CCCD attribute. Handle notifications and indications. + // for all connections + + for (uint16_t conn_id = 0, conn_found = 0; (conn_found < DM_CONN_MAX) && (conn_id < 0x100); ++conn_id) { + if (DmConnInUse(conn_id) == true) { + ++conn_found; + } else { + uint16_t cccEnabled = AttsCccEnabled(conn_id, idx); + if (cccEnabled & ATT_CLIENT_CFG_NOTIFY) { + AttsHandleValueNtf(conn_id, attributeHandle, len, (uint8_t*)buffer); } - if (idx < cccCnt) { - // This characteristic has a CCCD attribute. Handle notifications and indications. - uint16_t cccEnabled = AttsCccEnabled(connectionHandle, idx); - if (cccEnabled & ATT_CLIENT_CFG_NOTIFY) { - AttsHandleValueNtf(connectionHandle, attributeHandle, len, (uint8_t*)buffer); - } - if (cccEnabled & ATT_CLIENT_CFG_INDICATE) { - AttsHandleValueInd(connectionHandle, attributeHandle, len, (uint8_t*)buffer); - } + if (cccEnabled & ATT_CLIENT_CFG_INDICATE) { + AttsHandleValueInd(conn_id, attributeHandle, len, (uint8_t*)buffer); } } + + AttsCccSet(conn_id, idx, *((uint16_t*)buffer)); } return BLE_ERROR_NONE; @@ -332,26 +361,59 @@ ble_error_t GattServer::write(Gap::Handle_t connectionHandle, GattAttribute::Han } } - // This is not a CCCD. Use the non-connection specific update method. - return write(attributeHandle, buffer, len, localOnly); + // write the value to the attribute handle + if (AttsSetAttr(attributeHandle, len, (uint8_t*)buffer) != ATT_SUCCESS) { + return BLE_ERROR_PARAM_OUT_OF_RANGE; + } + + // return if the update does not have to be propagated to peers + if (localOnly) { + return BLE_ERROR_NONE; + } + + // Check to see if this characteristic has a CCCD attribute + for (idx = 0; idx < cccCnt; idx++) { + if (attributeHandle == cccHandles[idx]) { + break; + } + } + + // exit if the characteristic has no CCCD attribute + if (idx >= cccCnt) { + return BLE_ERROR_NONE; + } + + // This characteristic has a CCCD attribute. Handle notifications and indications. + uint16_t cccEnabled = AttsCccEnabled(connectionHandle, idx); + if (cccEnabled & ATT_CLIENT_CFG_NOTIFY) { + AttsHandleValueNtf(connectionHandle, attributeHandle, len, (uint8_t*)buffer); + } + if (cccEnabled & ATT_CLIENT_CFG_INDICATE) { + AttsHandleValueInd(connectionHandle, attributeHandle, len, (uint8_t*)buffer); + } + + return BLE_ERROR_NONE; } ble_error_t GattServer::areUpdatesEnabled(const GattCharacteristic &characteristic, bool *enabledP) { - uint16_t connectionHandle = Gap::getInstance().getConnectionHandle(); + for (size_t idx = 0; idx < cccCnt; idx++) { + if (characteristic.getValueHandle() == cccHandles[idx]) { + for (uint16_t conn_id = 0, conn_found = 0; (conn_found < DM_CONN_MAX) && (conn_id < 0x100); ++conn_id) { + if (DmConnInUse(conn_id) == true) { + ++conn_found; + } else { + continue; + } - if (connectionHandle != DM_CONN_ID_NONE) { - uint8_t idx; - for (idx = 0; idx < cccCnt; idx++) { - if (characteristic.getValueHandle() == cccHandles[idx]) { - uint16_t cccValue = AttsCccGet(connectionHandle, idx); - if (cccValue & ATT_CLIENT_CFG_NOTIFY) { + uint16_t cccValue = AttsCccGet(conn_id, idx); + if ((cccValue & ATT_CLIENT_CFG_NOTIFY) || (cccValue & ATT_CLIENT_CFG_INDICATE)) { *enabledP = true; - } else { - *enabledP = false; + return BLE_ERROR_NONE; } - return BLE_ERROR_NONE; } + *enabledP = false; + return BLE_ERROR_NONE; } } @@ -365,7 +427,7 @@ ble_error_t GattServer::areUpdatesEnabled(Gap::Handle_t connectionHandle, const for (idx = 0; idx < cccCnt; idx++) { if (characteristic.getValueHandle() == cccHandles[idx]) { uint16_t cccValue = AttsCccGet(connectionHandle, idx); - if (cccValue & ATT_CLIENT_CFG_NOTIFY) { + if (cccValue & ATT_CLIENT_CFG_NOTIFY || (cccValue & ATT_CLIENT_CFG_INDICATE)) { *enabledP = true; } else { *enabledP = false; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/critical_section_api.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/critical_section_api.c new file mode 100644 index 00000000000..32245e1a2bc --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/critical_section_api.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015-2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" +#include "nrf_error.h" +#include "nrf_sdm.h" +#include "nrf_soc.h" + +#include +#include + +static union { + uint32_t _PRIMASK_state; + uint8_t _sd_state; +} _state = {0}; + +static bool _use_softdevice_routine = false; +static bool _state_saved = false; + +void hal_critical_section_enter(void) +{ + // Fetch the current state of interrupts + uint32_t primask = __get_PRIMASK(); + uint8_t temp_state = 0; + + // If interrupts are enabled, try to use the soft device + uint8_t sd_enabled; + if ((primask == 0) && + (sd_softdevice_is_enabled(&sd_enabled) == NRF_SUCCESS) && + (sd_enabled == 1)) { + // If the softdevice can be used, use it. + sd_nvic_critical_region_enter(&temp_state); + _use_softdevice_routine = true; + + if (_state_saved == false) { + _state._sd_state = temp_state; + } + } else { + // If interrupts are enabled, disable them. + if (primask == 0) { + __disable_irq(); + } + + // Store PRIMASK state, it will be restored when exiting critical + // section. + _use_softdevice_routine = false; + + if (_state_saved == false) { + _state._PRIMASK_state = primask; + } + } + + _state_saved = true; +} + +void hal_critical_section_exit(void) +{ + _state_saved = false; + + // Restore the state as it was prior to entering the critical section. + if (_use_softdevice_routine) { + sd_nvic_critical_region_exit(_state._sd_state) + } else { + __set_PRIMASK(_state._PRIMASK_state); + } +} + +bool hal_in_critical_section(void) +{ + return (_state_saved == true); +} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/nordic_critical.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/nordic_critical.c deleted file mode 100644 index c8ebae99a7e..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/nordic_critical.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include // uint32_t, UINT32_MAX -#include // uint32_t, UINT32_MAX -#include "cmsis.h" -#include "nrf_soc.h" -#include "nrf_sdm.h" - -static union { - uint32_t _PRIMASK_state; - uint8_t _sd_state; -} _state = { 0 } ; -static volatile uint32_t _entry_count = 0; -static bool _use_softdevice_routine = false; - -void core_util_critical_section_enter() -{ - // if a critical section has already been entered, just update the counter - if (_entry_count) { - ++_entry_count; - return; - } - - // in this path, a critical section has never been entered - uint32_t primask = __get_PRIMASK(); - - // if interrupts are enabled, try to use the soft device - uint8_t sd_enabled; - if ((primask == 0) && (sd_softdevice_is_enabled(&sd_enabled) == NRF_SUCCESS) && sd_enabled == 1) { - // if the soft device can be use, use it - sd_nvic_critical_region_enter(&_state._sd_state); - _use_softdevice_routine = true; - } else { - // if interrupts where enabled, disable them - if(primask == 0) { - __disable_irq(); - } - - // store the PRIMASK state, it will be restored at the end of the critical section - _state._PRIMASK_state = primask; - _use_softdevice_routine = false; - } - - assert(_entry_count == 0); // entry count should always be equal to 0 at this point - ++_entry_count; -} - -void core_util_critical_section_exit() -{ - assert(_entry_count > 0); - --_entry_count; - - // If their is other segments which have entered the critical section, just leave - if (_entry_count) { - return; - } - - // This is the last segment of the critical section, state should be restored as before entering - // the critical section - if (_use_softdevice_routine) { - sd_nvic_critical_region_exit(_state._sd_state); - } else { - __set_PRIMASK(_state._PRIMASK_state); - } -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp index 811e7152544..029016f9e47 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp @@ -51,11 +51,9 @@ extern "C" { } #include "nrf_ble_hci.h" -#include "btle_discovery.h" -#include "nRF5xGattClient.h" -#include "nRF5xServiceDiscovery.h" -#include "nRF5xCharacteristicDescriptorDiscoverer.h" +#include "nRF5XPalGattClient.h" + bool isEventsSignaled = false; @@ -67,23 +65,6 @@ extern "C" void SD_EVT_IRQHandler(void); // export the softdevice event handler static void btle_handler(ble_evt_t *p_ble_evt); -#if 0 -#define CENTRAL_LINK_COUNT (YOTTA_CFG_NORDIC_BLE_CENTRAL_LINKS) /**evt.gap_evt.params.connected.peer_addr; #if (NRF_SD_BLE_API_VERSION <= 2) const ble_gap_addr_t *own = &p_ble_evt->evt.gap_evt.params.connected.own_addr; - + gap.processConnectionEvent(handle, role, static_cast(peer->addr_type), peer->addr, @@ -275,9 +258,7 @@ static void btle_handler(ble_evt_t *p_ble_evt) #if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) // Close all pending discoveries for this connection - nRF5xGattClient& gattClient = ble.getGattClient(); - gattClient.characteristicDescriptorDiscoverer().terminate(handle, BLE_ERROR_INVALID_STATE); - gattClient.discovery().terminate(handle); + nRF5XGattClient::handle_connection_termination(handle); #endif gap.processDisconnectionEvent(handle, reason); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h index 021dd50513b..dfeccef05be 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h @@ -26,6 +26,13 @@ extern "C" { #include "ble_srv_common.h" #include "headers/nrf_ble.h" +#define CENTRAL_LINK_COUNT 3 /**header.evt_id) { - case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: - switch (p_ble_evt->evt.gattc_evt.gatt_status) { - case BLE_GATT_STATUS_SUCCESS: - sdSingleton.setupDiscoveredServices(&p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp); - break; - - case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND: - default: - sdSingleton.terminate(); - break; - } - break; - - case BLE_GATTC_EVT_CHAR_DISC_RSP: - switch (p_ble_evt->evt.gattc_evt.gatt_status) { - case BLE_GATT_STATUS_SUCCESS: - sdSingleton.setupDiscoveredCharacteristics(&p_ble_evt->evt.gattc_evt.params.char_disc_rsp); - break; - - case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND: - default: - sdSingleton.terminateCharacteristicDiscovery(BLE_ERROR_NONE); - break; - } - break; - - case BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP: - if (sdSingleton.isActive()) { - sdSingleton.processDiscoverUUIDResponse(&p_ble_evt->evt.gattc_evt); - } - break; - - case BLE_GATTC_EVT_READ_RSP: { - GattReadCallbackParams response = { - /* .connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, - /* .handle = */ p_ble_evt->evt.gattc_evt.params.read_rsp.handle, - /* .offset = */ p_ble_evt->evt.gattc_evt.params.read_rsp.offset, - /* .len = */ p_ble_evt->evt.gattc_evt.params.read_rsp.len, - /* .data = */ p_ble_evt->evt.gattc_evt.params.read_rsp.data, - }; - gattClient.processReadResponse(&response); - } - break; - - case BLE_GATTC_EVT_WRITE_RSP: { - GattWriteCallbackParams response = { - /* .connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, - /* .handle = */ p_ble_evt->evt.gattc_evt.params.write_rsp.handle, - /* .writeOp = */ (GattWriteCallbackParams::WriteOp_t)(p_ble_evt->evt.gattc_evt.params.write_rsp.write_op), - /* .offset = */ p_ble_evt->evt.gattc_evt.params.write_rsp.offset, - /* .len = */ p_ble_evt->evt.gattc_evt.params.write_rsp.len, - /* .data = */ p_ble_evt->evt.gattc_evt.params.write_rsp.data, - }; - gattClient.processWriteResponse(&response); - } - break; - - case BLE_GATTC_EVT_HVX: { - GattHVXCallbackParams params = { - /* connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, - /* handle = */ p_ble_evt->evt.gattc_evt.params.hvx.handle, - /* type = */ static_cast(p_ble_evt->evt.gattc_evt.params.hvx.type), - /* len = */ p_ble_evt->evt.gattc_evt.params.hvx.len, - /* data = */ p_ble_evt->evt.gattc_evt.params.hvx.data - }; - - gattClient.processHVXEvent(¶ms); - } - break; - - case BLE_GATTC_EVT_DESC_DISC_RSP: { - uint16_t conn_handle = p_ble_evt->evt.gattc_evt.conn_handle; - uint16_t status = p_ble_evt->evt.gattc_evt.gatt_status; - const ble_gattc_evt_desc_disc_rsp_t& discovered_descriptors = p_ble_evt->evt.gattc_evt.params.desc_disc_rsp; - - switch(status) { - case BLE_GATT_STATUS_SUCCESS: - characteristicDescriptorDiscoverer.process( - conn_handle, - discovered_descriptors - ); - break; - case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND: - // end of discovery - characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_NONE); - break; - default: - characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_UNSPECIFIED); - break; - } - } break; - - case BLE_GATTC_EVT_ATTR_INFO_DISC_RSP : { - uint16_t conn_handle = p_ble_evt->evt.gattc_evt.conn_handle; - uint16_t status = p_ble_evt->evt.gattc_evt.gatt_status; - const ble_gattc_evt_attr_info_disc_rsp_t& infos = p_ble_evt->evt.gattc_evt.params.attr_info_disc_rsp; - - switch(status) { - case BLE_GATT_STATUS_SUCCESS: - characteristicDescriptorDiscoverer.processAttributeInformation( - conn_handle, - infos - ); - break; - default: - characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_UNSPECIFIED); - break; - } - - } break; - } - - sdSingleton.progressCharacteristicDiscovery(); - sdSingleton.progressServiceDiscovery(); -} -#endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp index 2a8e600c0ad..bc46d3d58de 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp @@ -210,6 +210,8 @@ error_t custom_add_in_characteristic(uint16_t service_handle, bool has_variable_len, const uint8_t *userDescriptionDescriptorValuePtr, uint16_t userDescriptionDescriptorValueLen, + const uint8_t *presentationFormatDescriptorValuePtr, + uint16_t presentationFormatDescriptorValueLen, bool readAuthorization, bool writeAuthorization, ble_gatts_char_handles_t *p_char_handle) @@ -238,6 +240,11 @@ error_t custom_add_in_characteristic(uint16_t service_handle, char_md.char_user_desc_max_size = userDescriptionDescriptorValueLen; char_md.char_user_desc_size = userDescriptionDescriptorValueLen; } + if ((presentationFormatDescriptorValueLen > 0) && (presentationFormatDescriptorValuePtr != NULL)) { + ASSERT_TRUE( sizeof(ble_gatts_char_pf_t) == sizeof(GattCharacteristic::PresentationFormat_t), ERROR_INVALID_PARAM ); + ASSERT_TRUE( presentationFormatDescriptorValueLen == sizeof(GattCharacteristic::PresentationFormat_t), ERROR_INVALID_PARAM ); + char_md.p_char_pf = const_cast(reinterpret_cast(presentationFormatDescriptorValuePtr)); + } /* Attribute declaration */ ble_gatts_attr_md_t attr_md = {0}; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h index af47fb98527..93480b873ba 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h @@ -52,6 +52,8 @@ error_t custom_add_in_characteristic(uint16_t service_handle, bool has_variable_len, const uint8_t *userDescriptionDescriptorValuePtr, uint16_t userDescriptionDescriptorValueLen, + const uint8_t *presentationFormatDescriptorValuePtr, + uint16_t presentationFormatDescriptorValueLen, bool readAuthorization, bool writeAuthorization, ble_gatts_char_handles_t *p_char_handle); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp new file mode 100644 index 00000000000..e1baf9569e8 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.cpp @@ -0,0 +1,1679 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "nRF5XPalGattClient.h" + +#include "ble/pal/PalGattClient.h" +#include "ble/pal/SimpleAttServerMessage.h" + +#include "nrf_ble_gatt.h" +#include "nrf_ble.h" +#include "nrf_ble_types.h" +#include "nrf_ble_err.h" + +namespace ble { +namespace pal { +namespace vendor { +namespace nordic { + +namespace { + +/** + * Extract an uint16_t value from a memory location. + */ +static uint16_t bytes_to_u16(const void* b) +{ + uint16_t res; + memcpy(&res, b, sizeof(uint16_t)); + return res; +} + +/** + * Push an uint16_t value into a byte stream. + * + * @note it is incremented. + */ +static void u16_to_stream(uint8_t *&it, uint16_t v) +{ + memcpy(it, &v, sizeof(uint16_t)); + it += 2; +} + +/** + * Convert a pal::attribute_handle_range_t into a ble_gattc_handle_range_t. + */ +static ble_gattc_handle_range_t to_nordic_handle_range(const attribute_handle_range_t &range) +{ + ble_gattc_handle_range_t result = { + range.begin, + range.end + }; + return result; +} + +/** + * Convert a ble_gattc_handle_range_t into a pal::attribute_handle_range_t. + */ +static attribute_handle_range_t to_ble_handle_range(const ble_gattc_handle_range_t &range) +{ + attribute_handle_range_t result = { + range.start_handle, + range.end_handle + }; + return result; +} + +/** + * Convert an error from the softdevice into a ble_error_t + */ +static ble_error_t convert_sd_error(uint32_t err) +{ + switch (err) { + case NRF_SUCCESS: + return BLE_ERROR_NONE; + case NRF_ERROR_INVALID_PARAM: + case BLE_ERROR_INVALID_CONN_HANDLE: + case NRF_ERROR_INVALID_ADDR: + return BLE_ERROR_INVALID_PARAM; + case NRF_ERROR_INVALID_STATE: + return BLE_ERROR_INVALID_STATE; + case NRF_ERROR_DATA_SIZE: + return BLE_ERROR_PARAM_OUT_OF_RANGE; + case BLE_ERROR_NO_TX_PACKETS: + return BLE_ERROR_NO_MEM; + case NRF_ERROR_BUSY: + return BLE_STACK_BUSY; + case NRF_ERROR_NO_MEM: + return BLE_ERROR_NO_MEM; + default: + return BLE_ERROR_UNSPECIFIED; + } +} + +/** + * Convert a UUID into a ble_uuid_t . + * If the UUID is a 128 bit one then it is registered into the softdevice. + */ +static ble_error_t to_nordic_uuid(const UUID &uuid, ble_uuid_t &nordic_uuid) +{ + if (uuid.getLen() == UUID::LENGTH_OF_LONG_UUID) { + // first try to get the long UUID in the table of UUIDs + uint32_t err = sd_ble_uuid_decode( + uuid.getLen(), + uuid.getBaseUUID(), + &nordic_uuid + ); + + // UUID found and filed, return. + if (err == NRF_SUCCESS) { + return BLE_ERROR_NONE; + } + + ble_uuid128_t uuid128; + memcpy(uuid128.uuid128, uuid.getBaseUUID(), sizeof(uuid128.uuid128)); + + // UUID not found, try to register it + err = sd_ble_uuid_vs_add(&uuid128, &nordic_uuid.type); + if (err == NRF_SUCCESS) { + nordic_uuid.uuid = bytes_to_u16(uuid.getBaseUUID() + 12); + } + + return convert_sd_error(err); + } else { + nordic_uuid.type = BLE_UUID_TYPE_BLE; + nordic_uuid.uuid = uuid.getShortUUID(); + return BLE_ERROR_NONE; + } +} + +/** + * Convert an attribute error code from the softdevice into a valid ATT error. + */ +static uint8_t convert_sd_att_error_code(uint16_t err) +{ + if (err < 0x101 || err > 0x1FF) { + return AttErrorResponse::UNLIKELY_ERROR; + } else { + return err & 0xFF; + } +} + +static const size_t long_uuid_length = 16; +static const size_t read_by_group_type_long_uuid_index = 4; +static const size_t characteristic_declaration_length = 1 + 2 + 16; + +} // end of anonymous namespace + +nRF5XGattClient::nRF5XGattClient() : + ble::pal::GattClient(), + _procedures() +{ +} + +nRF5XGattClient::~nRF5XGattClient() +{ + terminate(); +} + +ble_error_t nRF5XGattClient::initialize() +{ + return BLE_ERROR_NONE; +} + +ble_error_t nRF5XGattClient::exchange_mtu(connection_handle_t connection) +{ + // FIXME: implement when SD 140 5.x.x is present + // (see sd_ble_gatts_exchange_mtu_reply) + return BLE_ERROR_NOT_IMPLEMENTED; +} + +ble_error_t nRF5XGattClient::get_mtu_size( + connection_handle_t connection_handle, uint16_t& mtu_size +) { +#if (NRF_SD_BLE_API_VERSION >= 3) + // FIXME: implement when MTU size can be configured; the mtu size must be + // stored locally when BLE_GATTC_EVT_EXCHANGE_MTU_RSP has been received + mtu_size = BLE_GATT_MTU_SIZE_DEFAULT; +#else + mtu_size = GATT_RX_MTU; +#endif + return BLE_ERROR_NONE; +} + +ble_error_t nRF5XGattClient::discover_primary_service( + connection_handle_t connection, + attribute_handle_t discovery_range_begining +) { + return launch_procedure( + connection, discovery_range_begining + ); +} + +ble_error_t nRF5XGattClient::discover_primary_service_by_service_uuid( + connection_handle_t connection_handle, + attribute_handle_t discovery_range_beginning, + const UUID& uuid +) { + return launch_procedure( + connection_handle, discovery_range_beginning, uuid + ); +} + +ble_error_t nRF5XGattClient::find_included_service( + connection_handle_t connection_handle, + attribute_handle_range_t service_range +) { + return launch_procedure( + connection_handle, service_range + ); +} + +ble_error_t nRF5XGattClient::discover_characteristics_of_a_service( + connection_handle_t connection_handle, + attribute_handle_range_t discovery_range +) { + return launch_procedure( + connection_handle, discovery_range + ); +} + +ble_error_t nRF5XGattClient::discover_characteristics_descriptors( + connection_handle_t connection_handle, + attribute_handle_range_t descriptors_discovery_range +) { + return launch_procedure( + connection_handle, descriptors_discovery_range + ); +} + +ble_error_t nRF5XGattClient::read_attribute_value( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle +) { + return launch_procedure( + connection_handle, attribute_handle + ); +} + +ble_error_t nRF5XGattClient::read_using_characteristic_uuid( + connection_handle_t connection_handle, + attribute_handle_range_t read_range, + const UUID& uuid +) { + return launch_procedure( + connection_handle, read_range, uuid + ); +} + +ble_error_t nRF5XGattClient::read_attribute_blob( + connection_handle_t connection, + attribute_handle_t attribute_handle, + uint16_t offset +) { + return launch_procedure( + connection, attribute_handle, offset + ); +} + +ble_error_t nRF5XGattClient::read_multiple_characteristic_values( + connection_handle_t connection, + const ArrayView& characteristic_handles +) { + return launch_procedure( + connection, characteristic_handles + ); +} + +ble_error_t nRF5XGattClient::write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value +) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_WRITE_CMD, + /* exec flags */ 0, + characteristic_value_handle, + /* offset */ 0, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); +} + +ble_error_t nRF5XGattClient::signed_write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value +) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_SIGN_WRITE_CMD, + /* exec flags */ 0, + characteristic_value_handle, + /* offset */ 0, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); +} + +ble_error_t nRF5XGattClient::write_attribute( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle, + const ArrayView& value +) { + return launch_procedure( + connection_handle, attribute_handle, value + ); +} + +ble_error_t nRF5XGattClient::queue_prepare_write( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value, + uint16_t offset +) { + return launch_procedure( + connection_handle, characteristic_value_handle, value, offset + ); +} + +ble_error_t nRF5XGattClient::execute_write_queue( + connection_handle_t connection_handle, + bool execute +) { + return launch_procedure( + connection_handle, execute + ); +} + + +/** + * Base definition of a GATT procedure. + * + * Nordic implementation of discovery procedures requires more than a single + * request to the BLE peer when it involves 128bit UUID. As a consequence it is + * necessary to reserve the connection slot, maintain state between requests and + * interpret responses depending on the context. + * + * The concept of procedures for Gatt operations formalize the process. A + * procedure lifecycle is defined by three function: + * - start: Launch of the procedure. It initiate the first request to send to + * the peer. It must be implemented by Procedure derived classes. + * - handle: Event handler that process ble events comming from the softdevice. + * This function drive the procedure flow and must be implemented by + * Procedure derived classes. + * - terminate: end the procedure and forward the result to the GattClient + * event handle. + * + * @note Commands such as write without response or signed write without response + * are not procedures. + */ +struct nRF5XGattClient::GattProcedure { + /** + * Initialize the procedure. + * + * @param connection Handle representing the connection used by the procedure. + * @param op Opcode of the procedure. + */ + GattProcedure(connection_handle_t connection, AttributeOpcode op) : + connection_handle(connection), procedure_opcode(op) { } + + /** + * To overide in child if necessary. + */ + virtual ~GattProcedure() { } + + /** + * Handle events targeting the connection. + */ + virtual void handle(const ble_evt_t &evt) = 0; + + /** + * Terminate the execution of the procedure and forward msg to the handler + * registered in the client. + * + * @note delete this. + */ + void terminate(const AttServerMessage &msg) + { + get_client().remove_procedure(this); + get_client().on_server_event(connection_handle, msg); + delete this; + } + + /** + * Terminate the procedure with an unlikely error. + */ + void abort() + { + terminate(AttErrorResponse( + procedure_opcode, AttErrorResponse::UNLIKELY_ERROR + )); + } + + const connection_handle_t connection_handle; + const AttributeOpcode procedure_opcode; +}; + + +/** + * A regular procedure is a procedure that follows Gatt specification. + * + * It initiate a single request to the peer and excepts a single response. This + * kind of procedure doesn't requires extra processing step. + * + * Given that such procedure expects a single event type from the soft device, + * error handling can be generalized. + */ +struct nRF5XGattClient::RegularGattProcedure : GattProcedure { + + /** + * Construct a RegularGattProcedure. + * + * @param connection Handle of the connection used by the procedure. + * @param op Attribute operation code + * @param event_type Type of event expected by the stack. + */ + RegularGattProcedure( + connection_handle_t connection, AttributeOpcode op, BLE_GATTC_EVTS event_type + ) : GattProcedure(connection, op), _event_type(event_type) { } + + /** + * Handle events from the BLE stack; do not overide in child. + * + * @note This function offload error handling from user error handler. If + * the event in input match the expected event type and does not carry error + * then it is forwarded to the do_handle function. Otherwise the procedure + * is terminated and an error is forwarded to the client event handler. + */ + virtual void handle(const ble_evt_t &evt) + { + if (evt.header.evt_id == _event_type) { + const ble_gattc_evt_t &gattc_evt = evt.evt.gattc_evt; + if (gattc_evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + procedure_opcode, + gattc_evt.error_handle, + convert_sd_att_error_code(gattc_evt.gatt_status) + )); + return; + } else { + do_handle(gattc_evt); + } + } else { + abort(); + } + } + + /** + * Handle gatt event received from the stack. + * + * @note The event passed in parameter is valid. + */ + virtual void do_handle(const ble_gattc_evt_t &evt) = 0; + +protected: + BLE_GATTC_EVTS _event_type; +}; + + +/** + * Procedure that handle discovery of primary services. + * + * The softdevice doesn't forward to user UUID of services that are 128 bit long. + * In such case a read request is issued for each service attribute handle + * to extract that information. + */ +struct nRF5XGattClient::DiscoverPrimaryServiceProcedure : GattProcedure { + + typedef ArrayView services_array_t; + + DiscoverPrimaryServiceProcedure(connection_handle_t connection) : + GattProcedure(connection, AttributeOpcode::READ_BY_GROUP_TYPE_REQUEST), + response(NULL), count(0), idx(0) { } + + virtual ~DiscoverPrimaryServiceProcedure() + { + if (response) { + delete[] response; + } + } + + ble_error_t start(attribute_handle_t begining) + { + uint32_t err = sd_ble_gattc_primary_services_discover( + connection_handle, begining, /* p_srvc_uuid */ NULL + ); + return convert_sd_error(err); + } + + /** + * Dispatch responses either to service discovery handler or attribute read + * handler. + */ + virtual void handle(const ble_evt_t &evt) + { + switch (evt.header.evt_id) { + case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: + handle_service_discovered(evt.evt.gattc_evt); + return; + case BLE_GATTC_EVT_READ_RSP: + handle_uuid_read(evt.evt.gattc_evt); + return; + default: + abort(); + return; + } + } + + /** + * Dispatch service discovery response either to the short UUID handler or + * the long UUID handler. + */ + void handle_service_discovered(const ble_gattc_evt_t &evt) + { + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_BY_GROUP_TYPE_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + services_array_t services( + evt.params.prim_srvc_disc_rsp.services, + evt.params.prim_srvc_disc_rsp.count + ); + + // note 128 bit and 16 bits UUID cannot be mixed up + if (services[0].uuid.type == BLE_UUID_TYPE_BLE) { + handle_16bit_services_discovered(services); + } else { + handle_128bit_services_discovered(services); + } + } + + /** + * Handle discovery of services with a 16 bit UUID. + * + * The procedure ends here. + */ + void handle_16bit_services_discovered(const services_array_t &services) + { + /** + * Custom implementation of AttReadByGroupTypeResponse that can be used + * with data returned by the nordic stack. + */ + struct CustomAttReadByGroupTypeResponse : AttReadByGroupTypeResponse { + CustomAttReadByGroupTypeResponse(const services_array_t &s) : + AttReadByGroupTypeResponse(), services(s) { + } + + virtual size_t size() const + { + return services.size(); + } + + virtual attribute_data_t operator[](size_t i) const + { + attribute_data_t result = { + to_ble_handle_range(services[i].handle_range), + make_const_ArrayView( + reinterpret_cast(&services[i].uuid.uuid), + sizeof(uint16_t) + ) + }; + return result; + } + + const services_array_t &services; + }; + + terminate(CustomAttReadByGroupTypeResponse(services)); + } + + /** + * Handle discovery of services with a 128 UUID. + * + * Handle of the services discovered will be stored locally then the + * procedure sequentially initiate a read request of each of these attribute + * handle to acquire the value of the UUID of the service. + * + * The procedure ends once all the informations initially sent by the peer + * has been reconstructed and forwarded to the registered client handler. + */ + void handle_128bit_services_discovered(const services_array_t &services) + { + response = new(std::nothrow) packed_discovery_response_t[services.size()]; + if (!response) { + abort(); + return; + } + + count = services.size(); + idx = 0; + for (size_t i = 0; i < count; ++i) { + uint8_t *it = &response[i][0]; + u16_to_stream(it, services[i].handle_range.start_handle); + u16_to_stream(it, services[i].handle_range.end_handle); + } + + read_service_uuid(); + } + + /** + * Initiate the read request of the next service attribute handle. + */ + void read_service_uuid(void) + { + // note: use read multiple once different mtu size are supported ? + uint16_t attribute_handle = bytes_to_u16(&response[idx][0]); + + uint32_t err = sd_ble_gattc_read(connection_handle, attribute_handle, 0); + if (err) { + abort(); + } + } + + /** + * Handle reception of a service (long) UUID. + */ + void handle_uuid_read(const ble_gattc_evt_t &evt) + { + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + const ble_gattc_evt_read_rsp_t &rsp = evt.params.read_rsp; + + uint16_t expected_handle = bytes_to_u16(&response[idx][0]); + + if (rsp.handle != expected_handle || rsp.offset != 0 || + rsp.len != long_uuid_length) { + abort(); + return; + } + + memcpy(&response[idx][read_by_group_type_long_uuid_index], rsp.data, rsp.len); + + ++idx; + + if (idx == count) { + terminate(SimpleAttReadByGroupTypeResponse( + sizeof(packed_discovery_response_t), + make_const_ArrayView( + reinterpret_cast(response), + count * sizeof(packed_discovery_response_t) + )) + ); + } else { + read_service_uuid(); + } + } + + // Hold read by group type response of services with 128 bit UUID. + // The response is composed of the service attribute handle (2 bytes), the + // end group handle (2 bytes) and the service UUID (16 bytes). + typedef uint8_t packed_discovery_response_t[20]; + + packed_discovery_response_t* response; + uint16_t count; + uint16_t idx; +}; + + +/** + * Procedure that manage Discover Primary Service by Service UUID transactions. + * + * @note Even if the softdevice doesn't forward the complete content of the peer + * response it is possible to reconstruct it by keeping a copy of the UUID to + * find. + */ +struct nRF5XGattClient::DiscoverPrimaryServiceByUUIDProcedure : RegularGattProcedure { + + typedef ArrayView services_array_t; + + DiscoverPrimaryServiceByUUIDProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::FIND_BY_TYPE_VALUE_REQUEST, + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP + ), + _service_uuid() { } + + ble_error_t start(attribute_handle_t begining, const UUID &uuid) + { + ble_uuid_t nordic_uuid; + ble_error_t ble_err = to_nordic_uuid(uuid, nordic_uuid); + if (ble_err) { + return ble_err; + } + + uint32_t err = sd_ble_gattc_primary_services_discover( + connection_handle, begining, &nordic_uuid + ); + if (!err) { + _service_uuid = uuid; + } + + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + services_array_t services( + evt.params.prim_srvc_disc_rsp.services, + evt.params.prim_srvc_disc_rsp.count + ); + + /** + * Implementation of AttReadByGroupTypeResponse that addapt Nordic data + * structure. + */ + struct CustomAttReadByGroupTypeResponse : AttReadByGroupTypeResponse { + CustomAttReadByGroupTypeResponse(const services_array_t &s, const UUID &u) : + AttReadByGroupTypeResponse(), services(s), uuid(u) { + } + + virtual size_t size() const + { + return services.size(); + } + + virtual attribute_data_t operator[](size_t i) const + { + attribute_data_t result = { + to_ble_handle_range(services[i].handle_range), + make_ArrayView(uuid.getBaseUUID(), uuid.getLen()) + }; + return result; + } + + const services_array_t &services; + const UUID &uuid; + }; + + terminate(CustomAttReadByGroupTypeResponse(services, _service_uuid)); + } + + UUID _service_uuid; +}; + + +/** + * Procedure that manage Find Included Services transactions. + */ +struct nRF5XGattClient::FindIncludedServicesProcedure : RegularGattProcedure { + + typedef ArrayView services_array_t; + + FindIncludedServicesProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::READ_BY_TYPE_REQUEST, + BLE_GATTC_EVT_REL_DISC_RSP + ) { } + + ble_error_t start(attribute_handle_range_t service_range) + { + ble_gattc_handle_range_t range = to_nordic_handle_range(service_range); + uint32_t err = sd_ble_gattc_relationships_discover( + connection_handle, &range + ); + + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + // recompose the message into a raw att read by type response. + const ble_gattc_evt_rel_disc_rsp_t &resp = evt.params.rel_disc_rsp; + + bool contain_short_uuid = + (resp.includes[0].included_srvc.uuid.type == BLE_UUID_TYPE_BLE); + + uint8_t element_size = 6; + if (contain_short_uuid) { + element_size += 2; + } + + // It would be more efficient to use an API like alloca but it is + // unavailable and unsafe. Another alternative would be to have a fixed + // size stack buffer since the size of the MTU is fixed however once new + // softdevices lands could would have to be rewritten because they support + // variable MTU size. + size_t buffer_size = element_size * resp.count; + uint8_t* buffer = new(std::nothrow) uint8_t[buffer_size]; + if (!buffer) { + abort(); + return; + } + + uint8_t *it = buffer; + for(size_t i = 0; i < resp.count; ++i) { + u16_to_stream(it, resp.includes[i].handle); + u16_to_stream(it, resp.includes[i].included_srvc.handle_range.start_handle); + u16_to_stream(it, resp.includes[i].included_srvc.handle_range.end_handle); + if (contain_short_uuid) { + u16_to_stream(it, resp.includes[i].included_srvc.uuid.uuid); + } + } + + terminate(SimpleAttReadByTypeResponse( + element_size, + make_const_ArrayView(buffer, buffer_size) + )); + + delete[] buffer; + } + + UUID _service_uuid; +}; + + +/** + * Procedure that handle Discover All Characteristics of a Service transactions. + * + * The softdevice doesn't forward to user UUID of services that are 128 bit long. + * In such case a read request is issued for each attribute handle of + * characteristics that exposes a long UUID. + */ +struct nRF5XGattClient::DiscoverCharacteristicsProcedure : GattProcedure { + /** + * Data structure returned by the function flatten_response. + */ + struct read_by_type_response_t { + uint16_t count; + uint16_t element_size; + uint8_t* buffer; + }; + + DiscoverCharacteristicsProcedure(connection_handle_t connection) : + GattProcedure(connection, AttributeOpcode::READ_BY_TYPE_REQUEST), + _response(), _idx(0) { } + + virtual ~DiscoverCharacteristicsProcedure() + { + if (_response.buffer) { + delete[] _response.buffer; + } + } + + ble_error_t start(attribute_handle_range_t discovery_range) + { + ble_gattc_handle_range_t range = to_nordic_handle_range(discovery_range); + uint32_t err = sd_ble_gattc_characteristics_discover( + connection_handle, + &range + ); + + return convert_sd_error(err); + } + + /** + * Dispatch ble events to the appropriate handler: + * - handle_characteristic_discovered: For a discovery response. + * - handle_uuid_read: For a read response. + */ + virtual void handle(const ble_evt_t &evt) + { + switch (evt.header.evt_id) { + case BLE_GATTC_EVT_CHAR_DISC_RSP: + handle_characteristic_discovered(evt.evt.gattc_evt); + return; + case BLE_GATTC_EVT_READ_RSP: + handle_uuid_read(evt.evt.gattc_evt); + return; + default: + abort(); + return; + } + } + + void handle_characteristic_discovered(const ble_gattc_evt_t &evt) + { + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_BY_TYPE_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + // layout the data structure into a flat byte array. + _response = flatten_response(evt.params.char_disc_rsp); + if (!_response.buffer) { + abort(); + return; + } + + // If element size is equal to 7 then the characteristic discovered + // have 16 bit UUID. It is not necessary to read their characteristic + // declaration attribute. + if (_response.element_size == 7) { + forward_response_and_terminate(); + } else { + // 128 bit UUID. + // read sequentially each characteristic declaration attribute + // discovered. + _idx = 0; + read_characteristic_uuid(); + } + } + + /** + * Initiate read of the next characteristic declaration attribute. + */ + void read_characteristic_uuid(void) + { + // note: use read multiple once different mtu size are supported ? + uint16_t attribute_handle = + bytes_to_u16(&_response.buffer[_idx * _response.element_size]); + + uint32_t err = sd_ble_gattc_read(connection_handle, attribute_handle, 0); + if (err) { + abort(); + } + } + + /** + * Handle read response of a characteristic declaration attribute. + * It add the data in the response then initiate the read of the next + * attribute or terminate the procedure if all characteristic declaration + * attributes have been read. + */ + void handle_uuid_read(const ble_gattc_evt_t &evt) + { + // should never happen + if (!_response.buffer) { + abort(); + return; + } + + if (evt.gatt_status != BLE_GATT_STATUS_SUCCESS) { + terminate(AttErrorResponse( + AttributeOpcode::READ_REQUEST, + convert_sd_att_error_code(evt.gatt_status) + )); + return; + } + + const ble_gattc_evt_read_rsp_t &rsp = evt.params.read_rsp; + uint8_t* current_element = &_response.buffer[_idx * _response.element_size]; + uint16_t expected_handle = bytes_to_u16(current_element); + + if (rsp.handle != expected_handle || rsp.offset != 0 || + rsp.len != characteristic_declaration_length) { + abort(); + return; + } + + // note: elements are the pair characteristic declaration handle followed + // by the attribute value. + memcpy(current_element + 2, rsp.data, rsp.len); + + ++_idx; + + if (_idx == _response.count) { + forward_response_and_terminate(); + } else { + read_characteristic_uuid(); + } + } + + /** + * Terminate the procedure by forwarding the AttReadByTypeResponse built. + */ + void forward_response_and_terminate() { + terminate(SimpleAttReadByTypeResponse( + _response.element_size, + make_const_ArrayView( + _response.buffer, + _response.element_size * _response.count + ) + )); + } + + /** + * Convert a ble_gattc_evt_char_disc_rsp_t into a raw response. + * + * If UUIDs present are 16 bits long then the output contain the whole + * response. Otherwise only the handle declaration of each characteristic + * discovered is present and properties, handle value and UUID are populated + * by reading the attribute handle. + */ + static read_by_type_response_t flatten_response(const ble_gattc_evt_char_disc_rsp_t& resp) + { + read_by_type_response_t result = { resp.count, 0 }; + + bool short_uuid = (resp.chars[0].uuid.type == BLE_UUID_TYPE_BLE); + + // att handle + prop + value handle + uuid size + result.element_size = 5 + (short_uuid ? 2 : 16) ; + + size_t buffer_size = resp.count * result.element_size; + result.buffer = new(std::nothrow) uint8_t[buffer_size]; + if(!result.buffer) { + return result; + } + + uint8_t *it = result.buffer; + for(size_t i = 0; i < resp.count; ++i) { + u16_to_stream(it, resp.chars[i].handle_decl); + if (short_uuid) { + *it++ = get_properties(resp.chars[i]); + u16_to_stream(it, resp.chars[i].handle_value); + u16_to_stream(it, resp.chars[i].uuid.uuid); + } else { + // leave the characteristic value declaration empty; it will be + // fullfiled by a read of the attribute. + it += (1 + 2 + 16); + } + } + + return result; + } + + /** + * Compute characteristic properties from ble_gattc_char_t. + */ + static uint8_t get_properties(const ble_gattc_char_t& char_desc) + { + return + (char_desc.char_props.broadcast << 0) | + (char_desc.char_props.read << 1) | + (char_desc.char_props.write_wo_resp << 2) | + (char_desc.char_props.write << 3) | + (char_desc.char_props.notify << 4) | + (char_desc.char_props.indicate << 5) | + (char_desc.char_props.auth_signed_wr << 6) | + (char_desc.char_ext_props << 7); + } + + read_by_type_response_t _response; + uint16_t _idx; +}; + +/** + * Procedure that handle discovery of characteristic descriptors. + */ +struct nRF5XGattClient::DiscoverDescriptorsProcedure : RegularGattProcedure { + DiscoverDescriptorsProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::FIND_INFORMATION_REQUEST, + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP + ) { + } + + ble_error_t start(attribute_handle_range_t discovery_range) + { + ble_gattc_handle_range_t range = to_nordic_handle_range(discovery_range); + uint32_t err = sd_ble_gattc_attr_info_discover( + connection_handle, + &range + ); + + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + /** + * Adapt ble_gattc_evt_attr_info_disc_rsp_t into + * pal::AttFindInformationResponse + */ + struct CustomFindInformationResponse : AttFindInformationResponse { + CustomFindInformationResponse(const ble_gattc_evt_attr_info_disc_rsp_t &resp) : + AttFindInformationResponse(), response(resp) {} + + virtual size_t size() const + { + return response.count; + } + +#if (NRF_SD_BLE_API_VERSION < 3) + virtual information_data_t operator[](size_t i) const + { + information_data_t result = { + response.attr_info[i].handle + }; + + if (response.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { + result.uuid = UUID(response.attr_info[i].info.uuid16.uuid); + } else { + result.uuid = UUID( + response.attr_info[i].info.uuid128.uuid128, + UUID::LSB + ); + } + + return result; + } +#else + virtual information_data_t operator[](size_t i) const + { + if (response.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { + information_data_t result = { + response.info.attr_info16[i].handle, + UUID(response.info.attr_info16[i].uuid.uuid) + }; + + return result; + } else { + information_data_t result = { + response.info.attr_info128[i].handle, + UUID( + response.info.attr_info128[i].uuid.uuid128, + UUID::LSB + ) + }; + + return result; + } + } + + +#endif + + + const ble_gattc_evt_attr_info_disc_rsp_t &response; + }; + + terminate(CustomFindInformationResponse(evt.params.attr_info_disc_rsp)); + } +}; + + +/** + * Procedure that handle read of attribute handles. + */ +struct nRF5XGattClient::ReadAttributeProcedure : RegularGattProcedure { + ReadAttributeProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, AttributeOpcode::READ_REQUEST, BLE_GATTC_EVT_READ_RSP + ) { } + + ble_error_t start(attribute_handle_t attribute_handle) + { + uint32_t err = sd_ble_gattc_read(connection_handle, attribute_handle, 0); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_read_rsp_t& rsp = evt.params.read_rsp; + if (rsp.offset != 0 ) { + abort(); + return; + } + + terminate(AttReadResponse(make_const_ArrayView(rsp.data, rsp.len))); + } +}; + +/** + * Procedure that handle read of characteristic using characteristic UUID. + */ +struct nRF5XGattClient::ReadUsingCharacteristicUUIDProcedure : RegularGattProcedure { + ReadUsingCharacteristicUUIDProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::READ_BY_TYPE_REQUEST, + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP + ) { } + + ble_error_t start(attribute_handle_range_t read_range, const UUID& uuid) + { + ble_uuid_t nordic_uuid = { 0 }; + ble_error_t ble_err = to_nordic_uuid(uuid, nordic_uuid); + if (ble_err) { + return ble_err; + } + + ble_gattc_handle_range_t range = { + read_range.begin, + read_range.end + }; + + uint32_t err = sd_ble_gattc_char_value_by_uuid_read( + connection_handle, + &nordic_uuid, + &range + ); + return convert_sd_error(err); + } + +#if (NRF_SD_BLE_API_VERSION >= 3) + /** + * Adapt ble_gattc_evt_char_val_by_uuid_read_rsp_t into AttReadByTypeResponse. + */ + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_char_val_by_uuid_read_rsp_t &rsp = + evt.params.char_val_by_uuid_read_rsp; + + uint8_t element_size = sizeof(uint16_t) + rsp.value_len; + + terminate(SimpleAttReadByTypeResponse( + element_size, + make_const_ArrayView( + rsp.handle_value, + rsp.count * element_size + ) + )); + } + +#else + /** + * Adapt ble_gattc_evt_char_val_by_uuid_read_rsp_t into AttReadByTypeResponse. + */ + virtual void do_handle(const ble_gattc_evt_t &evt) + { + struct CustomReadByTypeResponse : AttReadByTypeResponse { + CustomReadByTypeResponse(const ble_gattc_evt_char_val_by_uuid_read_rsp_t& rsp) : + AttReadByTypeResponse(), response(rsp) { } + + virtual size_t size() const + { + return response.count; + } + + virtual attribute_data_t operator[](size_t i) const + { + attribute_data_t result = { + response.handle_value[i].handle, + make_const_ArrayView( + response.handle_value[i].p_value, + response.value_len + ) + }; + return result; + } + + const ble_gattc_evt_char_val_by_uuid_read_rsp_t& response; + } + + terminate(CustomReadByTypeResponse(evt.params.char_val_by_uuid_read_rsp)); + } +#endif +}; + +/** + * Procedure that handles read blob transactions. + */ +struct nRF5XGattClient::ReadAttributeBlobProcedure : RegularGattProcedure { + ReadAttributeBlobProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, AttributeOpcode::READ_BLOB_REQUEST, BLE_GATTC_EVT_READ_RSP + ) { } + + ble_error_t start(attribute_handle_t attribute_handle, uint16_t offset) + { + uint32_t err = sd_ble_gattc_read( + connection_handle, attribute_handle, offset + ); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + terminate(AttReadBlobResponse(make_const_ArrayView( + evt.params.read_rsp.data, + evt.params.read_rsp.len + ))); + } +}; + +/** + * Procedure that handles Read Multiple Characteristic Values transactions. + */ +struct nRF5XGattClient::ReadMultipleCharacteristicsProcedure : RegularGattProcedure { + ReadMultipleCharacteristicsProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::READ_MULTIPLE_REQUEST, + BLE_GATTC_EVT_CHAR_VALS_READ_RSP + ) { } + + ble_error_t start(const ArrayView& characteristic_handles) + { + uint32_t err = sd_ble_gattc_char_values_read( + connection_handle, + characteristic_handles.data(), + characteristic_handles.size() + ); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + terminate(AttReadMultipleResponse(make_const_ArrayView( + evt.params.char_vals_read_rsp.values, + evt.params.char_vals_read_rsp.len + ))); + } +}; + +/** + * Procedure that handles Write transactions. + */ +struct nRF5XGattClient::WriteAttributeProcedure : RegularGattProcedure { + WriteAttributeProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, AttributeOpcode::WRITE_REQUEST, BLE_GATTC_EVT_WRITE_RSP + ) { } + + ble_error_t start( + attribute_handle_t attribute_handle, const ArrayView& value + ) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_WRITE_REQ, + /* exec flags */ 0, + attribute_handle, + /* offset */ 0, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + terminate(AttWriteResponse()); + } +}; + +/** + * Procedure that handles Prepare Write transactions. + */ +struct nRF5XGattClient::QueuePrepareWriteProcedure : RegularGattProcedure { + QueuePrepareWriteProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::PREPARE_WRITE_REQUEST, + BLE_GATTC_EVT_WRITE_RSP + ) { } + + ble_error_t start( + attribute_handle_t characteristic_value_handle, + const ArrayView& value, + uint16_t offset + ) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_PREP_WRITE_REQ, + /* exec flags */ 0, + characteristic_value_handle, + offset, + static_cast(value.size()), + const_cast(value.data()) + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_write_rsp_t &response = evt.params.write_rsp; + + if (response.write_op != BLE_GATT_OP_PREP_WRITE_REQ) { + abort(); + return; + } + + terminate(AttPrepareWriteResponse( + response.handle, + response.offset, + make_const_ArrayView(response.data, response.len) + )); + } +}; + +/** + * Procedure that handles Execute Write transactions. + */ +struct nRF5XGattClient::ExecuteWriteQueueProcedure : RegularGattProcedure { + ExecuteWriteQueueProcedure(connection_handle_t connection) : + RegularGattProcedure( + connection, + AttributeOpcode::EXECUTE_WRITE_REQUEST, + BLE_GATTC_EVT_WRITE_RSP + ) { } + + ble_error_t start(bool execute) { + ble_gattc_write_params_t write_params = { + BLE_GATT_OP_EXEC_WRITE_REQ, + static_cast( + execute ? + BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL : + BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE + ), + /* attribute handle */ 0, + /* value offset */ 0, + /* buffer size*/ 0, + /* buffer data */ NULL + }; + + uint32_t err = sd_ble_gattc_write(connection_handle, &write_params); + return convert_sd_error(err); + } + + virtual void do_handle(const ble_gattc_evt_t &evt) + { + const ble_gattc_evt_write_rsp_t &response = evt.params.write_rsp; + if (response.write_op != BLE_GATT_OP_EXEC_WRITE_REQ) { + abort(); + return; + } + + terminate(AttExecuteWriteResponse()); + } +}; + +// NOTE: position after declaration of GattProcedure on purpose. +ble_error_t nRF5XGattClient::terminate() +{ + for (size_t i = 0; i < max_procedures_count; ++i) { + if (_procedures[i]) { + _procedures[i]->abort(); + _procedures[i] = NULL; + } + } + + return BLE_ERROR_NONE; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, const A0& a0 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, const A0& a0, const A1& a1 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0, a1); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0, a1, a2); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +template +ble_error_t nRF5XGattClient::launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2, const A3& a3 +) { + ProcType* p = new(std::nothrow) ProcType(connection); + if (!p) { + return BLE_ERROR_NO_MEM; + } + + if (!register_procedure(p)) { + delete p; + return BLE_ERROR_INVALID_STATE; + } + + ble_error_t err = p->start(a0, a1, a2, a3); + if (err) { + remove_procedure(p); + delete p; + } + + return err; +} + +nRF5XGattClient::GattProcedure* nRF5XGattClient::get_procedure( + connection_handle_t connection +) const { + for (size_t i = 0; i < max_procedures_count; ++i) { + if (_procedures[i] && _procedures[i]->connection_handle == connection) { + return _procedures[i]; + } + } + return NULL; +} + +bool nRF5XGattClient::register_procedure(GattProcedure *p) +{ + if (get_procedure(p->connection_handle)) { + return false; + } + + for (size_t i = 0; i < max_procedures_count; ++i) { + if (!_procedures[i]) { + _procedures[i] = p; + return true; + } + } + + return false; +} + +bool nRF5XGattClient::remove_procedure(nRF5XGattClient::GattProcedure* p) +{ + for (size_t i = 0; i < max_procedures_count; ++i) { + if (_procedures[i] == p) { + _procedures[i] = NULL; + return true; + } + } + + return false; +} + +// singleton of the ARM Cordio client +nRF5XGattClient& nRF5XGattClient::get_client() +{ + static nRF5XGattClient _client; + return _client; +} + +void nRF5XGattClient::handle_events(const ble_evt_t *evt) { + switch (evt->header.evt_id) { + case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: + case BLE_GATTC_EVT_REL_DISC_RSP: + case BLE_GATTC_EVT_CHAR_DISC_RSP: + case BLE_GATTC_EVT_DESC_DISC_RSP: + case BLE_GATTC_EVT_ATTR_INFO_DISC_RSP: + case BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP: + case BLE_GATTC_EVT_READ_RSP: + case BLE_GATTC_EVT_CHAR_VALS_READ_RSP: + case BLE_GATTC_EVT_WRITE_RSP: + get_client().handle_procedure_event(*evt); + break; + case BLE_GATTC_EVT_HVX: + get_client().handle_hvx_event(*evt); + break; + case BLE_GATTC_EVT_TIMEOUT: + get_client().handle_timeout_event(*evt); + break; + } +} + +void nRF5XGattClient::handle_procedure_event(const ble_evt_t &evt) +{ + GattProcedure* p = get_procedure(evt.evt.gattc_evt.conn_handle); + if (p) { + p->handle(evt); + } +} + +void nRF5XGattClient::handle_hvx_event(const ble_evt_t &evt) +{ + connection_handle_t connection = evt.evt.gattc_evt.conn_handle; + const ble_gattc_evt_hvx_t &hvx_evt = evt.evt.gattc_evt.params.hvx; + + switch (hvx_evt.type) { + case BLE_GATT_HVX_NOTIFICATION: + on_server_event( + connection, + AttHandleValueNotification( + hvx_evt.handle, + make_const_ArrayView(hvx_evt.data, hvx_evt.len) + ) + ); + return; + case BLE_GATT_HVX_INDICATION: + // send confirmation first then process the event + sd_ble_gattc_hv_confirm(connection, hvx_evt.handle); + on_server_event( + connection, + AttHandleValueIndication( + hvx_evt.handle, + make_const_ArrayView(hvx_evt.data, hvx_evt.len) + ) + ); + return; + default: + return; + } +} + +void nRF5XGattClient::handle_timeout_event(const ble_evt_t &evt) +{ + connection_handle_t connection = evt.evt.gattc_evt.conn_handle; + GattProcedure* p = get_procedure(connection); + if (p) { + p->abort(); + } + + on_transaction_timeout(connection); +} + +void nRF5XGattClient::handle_connection_termination(connection_handle_t connection) +{ + GattProcedure* p = get_client().get_procedure(connection); + if (p) { + p->abort(); + } +} + +} // nordic +} // vendor +} // pal +} // ble + + + + diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h new file mode 100644 index 00000000000..ede03ce3f4e --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5XPalGattClient.h @@ -0,0 +1,257 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_NORDIC_PAL_GATT_CLIENT_H_ +#define BLE_NORDIC_PAL_GATT_CLIENT_H_ + +#include "ble/pal/PalGattClient.h" +#include "ble/blecommon.h" +#include "ble/UUID.h" + +#include "nrf_ble_gatt.h" +#include "nrf_ble.h" +#include "nrf_ble_types.h" +#include "btle.h" + +namespace ble { +namespace pal { +namespace vendor { +namespace nordic { + +/** + * Implementation of pal::GattClient for the Nordic stack. + */ +class nRF5XGattClient : public ble::pal::GattClient { + +public: + nRF5XGattClient(); + + virtual ~nRF5XGattClient(); + + /** + * see pal::GattClient::initialize . + */ + virtual ble_error_t initialize(); + + /** + * see pal::GattClient::terminate . + */ + virtual ble_error_t terminate(); + + /** + * see pal::GattClient::exchange_mtu . + */ + virtual ble_error_t exchange_mtu(connection_handle_t connection); + + /** + * see pal::GattClient::get_mtu_size . + */ + virtual ble_error_t get_mtu_size( + connection_handle_t connection_handle, uint16_t& mtu_size + ); + + /** + * see pal::GattClient::discover_primary_service . + */ + virtual ble_error_t discover_primary_service( + connection_handle_t connection, + attribute_handle_t discovery_range_begining + ); + + /** + * see pal::GattClient::discover_primary_service_by_service_uuid . + */ + virtual ble_error_t discover_primary_service_by_service_uuid( + connection_handle_t connection_handle, + attribute_handle_t discovery_range_beginning, + const UUID& uuid + ); + + /** + * see pal::GattClient::find_included_service . + */ + virtual ble_error_t find_included_service( + connection_handle_t connection_handle, + attribute_handle_range_t service_range + ); + + /** + * see pal::GattClient::discover_characteristics_of_a_service . + */ + virtual ble_error_t discover_characteristics_of_a_service( + connection_handle_t connection_handle, + attribute_handle_range_t discovery_range + ); + + /** + * see pal::GattClient::discover_characteristics_descriptors . + */ + virtual ble_error_t discover_characteristics_descriptors( + connection_handle_t connection_handle, + attribute_handle_range_t descriptors_discovery_range + ); + + /** + * see pal::GattClient::read_attribute_value . + */ + virtual ble_error_t read_attribute_value( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle + ); + + /** + * see pal::GattClient::read_using_characteristic_uuid . + */ + virtual ble_error_t read_using_characteristic_uuid( + connection_handle_t connection_handle, + attribute_handle_range_t read_range, + const UUID& uuid + ); + + /** + * see pal::GattClient::read_attribute_blob . + */ + virtual ble_error_t read_attribute_blob( + connection_handle_t connection, + attribute_handle_t attribute_handle, + uint16_t offset + ); + + /** + * see pal::GattClient::read_multiple_characteristic_values . + */ + virtual ble_error_t read_multiple_characteristic_values( + connection_handle_t connection, + const ArrayView& characteristic_handles + ); + + /** + * see pal::GattClient::write_without_response . + */ + virtual ble_error_t write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value + ); + + /** + * see pal::GattClient::signed_write_without_response . + */ + virtual ble_error_t signed_write_without_response( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value + ); + + /** + * see pal::GattClient::write_attribute . + */ + virtual ble_error_t write_attribute( + connection_handle_t connection_handle, + attribute_handle_t attribute_handle, + const ArrayView& value + ); + + /** + * see pal::GattClient::queue_prepare_write . + */ + virtual ble_error_t queue_prepare_write( + connection_handle_t connection_handle, + attribute_handle_t characteristic_value_handle, + const ArrayView& value, + uint16_t offset + ); + + /** + * see pal::GattClient::execute_write_queue . + */ + virtual ble_error_t execute_write_queue( + connection_handle_t connection_handle, + bool execute + ); + + // singleton of the ARM Cordio client + static nRF5XGattClient& get_client(); + + /** + * Function call from btle.cpp + * + * Do not call directly. + */ + static void handle_events(const ble_evt_t *p_ble_evt); + + /** + * Called by btle.cpp when a disconnection happens. + */ + static void handle_connection_termination(connection_handle_t connection); + +private: + struct GattProcedure; + struct RegularGattProcedure; + struct DiscoverPrimaryServiceProcedure; + struct DiscoverPrimaryServiceByUUIDProcedure; + struct FindIncludedServicesProcedure; + struct DiscoverCharacteristicsProcedure; + struct DiscoverDescriptorsProcedure; + struct ReadAttributeProcedure; + struct ReadUsingCharacteristicUUIDProcedure; + struct ReadAttributeBlobProcedure; + struct ReadMultipleCharacteristicsProcedure; + struct WriteAttributeProcedure; + struct QueuePrepareWriteProcedure; + struct ExecuteWriteQueueProcedure; + + template + ble_error_t launch_procedure(connection_handle_t connection, const A0& a0); + + template + ble_error_t launch_procedure( + connection_handle_t connection, const A0& a0, const A1& a1 + ); + + template + ble_error_t launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2 + ); + + template + ble_error_t launch_procedure( + connection_handle_t connection, + const A0& a0, const A1& a1, const A2& a2, const A3& a3 + ); + + GattProcedure* get_procedure(connection_handle_t) const; + bool register_procedure(GattProcedure*); + bool remove_procedure(GattProcedure*); + + void handle_procedure_event(const ble_evt_t &evt); + void handle_hvx_event(const ble_evt_t &evt); + void handle_timeout_event(const ble_evt_t &evt); + + static const size_t max_procedures_count = + CENTRAL_LINK_COUNT + PERIPHERAL_LINK_COUNT; + + // Note: Ideally we would have used an array of variant here + GattProcedure* _procedures[max_procedures_count]; +}; + +} // nordic +} // vendor +} // pal +} // ble + +#endif /* BLE_NORDIC_PAL_GATT_CLIENT_H_ */ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp deleted file mode 100644 index 0dee44efbfc..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp +++ /dev/null @@ -1,325 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "nRF5xCharacteristicDescriptorDiscoverer.h" -#include "headers/nrf_ble_err.h" -#include "ble/DiscoveredCharacteristicDescriptor.h" - -nRF5xCharacteristicDescriptorDiscoverer::nRF5xCharacteristicDescriptorDiscoverer() : - discoveryRunning() { - // nothing to do -} - -nRF5xCharacteristicDescriptorDiscoverer::~nRF5xCharacteristicDescriptorDiscoverer() { - // nothing to do -} - -ble_error_t nRF5xCharacteristicDescriptorDiscoverer::launch( - const DiscoveredCharacteristic& characteristic, - const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback -) { - Gap::Handle_t connHandle = characteristic.getConnectionHandle(); - // it is ok to deduce that the start handle for descriptors is after - // the characteristic declaration and the characteristic value declaration - // see BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] (3.3) - Gap::Handle_t descriptorStartHandle = characteristic.getDeclHandle() + 2; - Gap::Handle_t descriptorEndHandle = characteristic.getLastHandle(); - - // check if there is any descriptor to discover - if (descriptorEndHandle < descriptorStartHandle) { - CharacteristicDescriptorDiscovery::TerminationCallbackParams_t termParams = { - characteristic, - BLE_ERROR_NONE - }; - terminationCallback.call(&termParams); - return BLE_ERROR_NONE; - } - - // check if we can run this discovery - if (isConnectionInUse(connHandle)) { - return BLE_STACK_BUSY; - } - - // get a new discovery slot, if none are available, just return - Discovery* discovery = getAvailableDiscoverySlot(); - if(discovery == NULL) { - return BLE_STACK_BUSY; - } - - // try to launch the discovery - ble_error_t err = gattc_descriptors_discover(connHandle, descriptorStartHandle, descriptorEndHandle); - if(!err) { - // commit the new discovery to its slot - *discovery = Discovery(characteristic, discoveryCallback, terminationCallback); - } - - return err; -} - -bool nRF5xCharacteristicDescriptorDiscoverer::isActive(const DiscoveredCharacteristic& characteristic) const { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if(discoveryRunning[i].getCharacteristic() == characteristic) { - return true; - } - } - return false; -} - -void nRF5xCharacteristicDescriptorDiscoverer::requestTerminate(const DiscoveredCharacteristic& characteristic) { - Discovery* discovery = findRunningDiscovery(characteristic); - if(discovery) { - // call terminate anyway - terminate(discovery, BLE_ERROR_NONE); - } -} - -void nRF5xCharacteristicDescriptorDiscoverer::process(uint16_t connectionHandle, const ble_gattc_evt_desc_disc_rsp_t& descriptors) { - Discovery* discovery = findRunningDiscovery(connectionHandle); - // the discovery has been removed - if(!discovery) { - return; - } - - for (uint16_t i = 0; i < descriptors.count; ++i) { - const ble_gattc_desc_t& desc = descriptors.descs[i]; - const ble_uuid_t& uuid = desc.uuid; - - if (uuid.type == BLE_UUID_TYPE_BLE) { - discovery->process( - desc.handle, UUID(uuid.uuid) - ); - } else { - // discover attribute infos of the descriptor - ble_error_t err = gattc_attr_info_discover(connectionHandle, desc.handle, desc.handle); - if (err) { - terminate(discovery, err); - } - - return; - } - } - - // prepare the next discovery request (if needed) - uint16_t startHandle = descriptors.descs[descriptors.count - 1].handle + 1; - uint16_t endHandle = discovery->getCharacteristic().getLastHandle(); - - if(startHandle > endHandle) { - terminate(discovery, BLE_ERROR_NONE); - return; - } - - ble_error_t err = gattc_descriptors_discover(connectionHandle, startHandle, endHandle); - if(err) { - terminate(discovery, err); - return; - } -} - -void nRF5xCharacteristicDescriptorDiscoverer::processAttributeInformation( - uint16_t connectionHandle, const ble_gattc_evt_attr_info_disc_rsp_t& infos) { - Discovery* discovery = findRunningDiscovery(connectionHandle); - // the discovery has been removed - if(!discovery) { - return; - } - -#if (NRF_SD_BLE_API_VERSION <= 2) - // for all UUIDS found, process the discovery - for (uint16_t i = 0; i < infos.count; ++i) { - bool use_16bits_uuids = infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT; - const ble_gattc_attr_info_t& attr_info = infos.attr_info[i]; - UUID uuid = use_16bits_uuids ? UUID(attr_info.info.uuid16.uuid) : UUID(attr_info.info.uuid128.uuid128, UUID::LSB); - discovery->process(attr_info.handle, uuid); - } - - // prepare the next round of descriptors discovery - uint16_t startHandle = infos.attr_info[infos.count - 1].handle + 1; -#else - uint16_t startHandle; - // for all UUIDS found, process the discovery - if (infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { - for (uint16_t i = 0; i < infos.count; ++i) { - UUID uuid = UUID(infos.info.attr_info16[i].uuid.uuid); - discovery->process(infos.info.attr_info16[i].handle, uuid); - } - - // prepare the next round of descriptors discovery - startHandle = infos.info.attr_info16[infos.count - 1].handle + 1; - } else { - for (uint16_t i = 0; i < infos.count; ++i) { - UUID uuid = UUID(infos.info.attr_info128[i].uuid.uuid128, UUID::LSB); - discovery->process(infos.info.attr_info128[i].handle, uuid); - } - - // prepare the next round of descriptors discovery - startHandle = infos.info.attr_info128[infos.count - 1].handle + 1; - } -#endif - uint16_t endHandle = discovery->getCharacteristic().getLastHandle(); - - if(startHandle > endHandle) { - terminate(discovery, BLE_ERROR_NONE); - return; - } - - ble_error_t err = gattc_descriptors_discover(connectionHandle, startHandle, endHandle); - if(err) { - terminate(discovery, err); - return; - } -} - -void nRF5xCharacteristicDescriptorDiscoverer::terminate(uint16_t handle, ble_error_t err) { - Discovery* discovery = findRunningDiscovery(handle); - // the discovery has already been terminated - if(!discovery) { - return; - } - - terminate(discovery, err); -} - -void nRF5xCharacteristicDescriptorDiscoverer::terminate(Discovery* discovery, ble_error_t err) { - // temporary copy, user code can try to launch a new discovery in the onTerminate - // callback. So, this discovery should not appear in such case. - Discovery tmp = *discovery; - *discovery = Discovery(); - tmp.terminate(err); -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery* -nRF5xCharacteristicDescriptorDiscoverer::findRunningDiscovery(const DiscoveredCharacteristic& characteristic) { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if((discoveryRunning[i].getCharacteristic() == characteristic) && - (discoveryRunning[i].isEmpty() == false)) { - return &discoveryRunning[i]; - } - } - return NULL; -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery* -nRF5xCharacteristicDescriptorDiscoverer::findRunningDiscovery(uint16_t handle) { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if((discoveryRunning[i].getCharacteristic().getConnectionHandle() == handle) && - (discoveryRunning[i].isEmpty() == false)) { - return &discoveryRunning[i]; - } - } - return NULL; -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery* -nRF5xCharacteristicDescriptorDiscoverer::getAvailableDiscoverySlot() { - for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) { - if(discoveryRunning[i].isEmpty()) { - return &discoveryRunning[i]; - } - } - return NULL; -} - -bool nRF5xCharacteristicDescriptorDiscoverer::isConnectionInUse(uint16_t connHandle) { - return findRunningDiscovery(connHandle) != NULL; -} - -ble_error_t nRF5xCharacteristicDescriptorDiscoverer::gattc_descriptors_discover( - uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle) { - - ble_gattc_handle_range_t discoveryRange = { - start_handle, - end_handle - }; - uint32_t err = sd_ble_gattc_descriptors_discover(connection_handle, &discoveryRange); - - switch(err) { - case NRF_SUCCESS: - return BLE_ERROR_NONE; - case BLE_ERROR_INVALID_CONN_HANDLE: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_INVALID_ADDR: - return BLE_ERROR_PARAM_OUT_OF_RANGE; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - default: - return BLE_ERROR_UNSPECIFIED; - } -} - -ble_error_t nRF5xCharacteristicDescriptorDiscoverer::gattc_attr_info_discover( - uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle) { - ble_gattc_handle_range_t handle_range = { start_handle, end_handle }; - uint32_t err = sd_ble_gattc_attr_info_discover(connection_handle, &handle_range); - - switch(err) { - case NRF_SUCCESS: - return BLE_ERROR_NONE; - case BLE_ERROR_INVALID_CONN_HANDLE: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_INVALID_ADDR: - return BLE_ERROR_PARAM_OUT_OF_RANGE; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - case NRF_ERROR_INVALID_STATE: - return BLE_ERROR_INVALID_STATE; - default: - return BLE_ERROR_UNSPECIFIED; - } -} - - - -// implementation of nRF5xCharacteristicDescriptorDiscoverer::Discovery - -nRF5xCharacteristicDescriptorDiscoverer::Discovery::Discovery() : - characteristic(), onDiscovery(), onTerminate() { -} - -nRF5xCharacteristicDescriptorDiscoverer::Discovery::Discovery( - const DiscoveredCharacteristic& c, const DiscoveryCallback_t& dCb, const TerminationCallback_t& tCb) : - characteristic(c), onDiscovery(dCb), onTerminate(tCb) { -} - -void nRF5xCharacteristicDescriptorDiscoverer::Discovery::process( - GattAttribute::Handle_t handle, const UUID& uuid) { - CharacteristicDescriptorDiscovery::DiscoveryCallbackParams_t params = { - characteristic, - DiscoveredCharacteristicDescriptor( - characteristic.getGattClient(), - characteristic.getConnectionHandle(), - handle, - uuid - ) - }; - onDiscovery.call(¶ms); -} - -void nRF5xCharacteristicDescriptorDiscoverer::Discovery::terminate(ble_error_t err) { - CharacteristicDescriptorDiscovery::TerminationCallbackParams_t params = { - characteristic, - err - }; - - onTerminate.call(¶ms); -} - -bool nRF5xCharacteristicDescriptorDiscoverer::Discovery::isEmpty() const { - return *this == Discovery(); -} - -const DiscoveredCharacteristic& nRF5xCharacteristicDescriptorDiscoverer::Discovery::getCharacteristic() const { - return characteristic; -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h deleted file mode 100644 index 753e368f0fe..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h +++ /dev/null @@ -1,227 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__ -#define __NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__ - -#include "ble/Gap.h" -#include "ble/DiscoveredCharacteristic.h" -#include "ble/CharacteristicDescriptorDiscovery.h" -#include "ble/GattClient.h" -#include "headers/nrf_ble_gattc.h" - -/** - * @brief Manage the discovery of Characteristic descriptors - * @details is a bridge between BLE API and Nordic stack regarding Characteristic - * Descriptor discovery. The BLE API can launch, monitor and ask for termination - * of a discovery. The Nordic stack will provide new descriptors and indicate when - * the discovery is done. - */ -class nRF5xCharacteristicDescriptorDiscoverer -{ - typedef CharacteristicDescriptorDiscovery::DiscoveryCallback_t DiscoveryCallback_t; - typedef CharacteristicDescriptorDiscovery::TerminationCallback_t TerminationCallback_t; - -public: - /** - * @brief Construct a new characteristic descriptor discoverer. - */ - nRF5xCharacteristicDescriptorDiscoverer(); - - /** - * @brief Destroy a characteristic descriptor discoverer. - */ - ~nRF5xCharacteristicDescriptorDiscoverer(); - - /** - * Launch a new characteristic descriptor discovery for a given DiscoveredCharacteristic. - * @param characteristic The characteristic owning the descriptors to discover. - * @param discoveryCallback The callback called when a descriptor is discovered. - * @param terminationCallback The callback called when the discovery process end. - * @return BLE_ERROR_NONE if characteristic descriptor discovery is launched successfully; - * else an appropriate error. - * @note: this will be called by BLE API side. - */ - ble_error_t launch( - const DiscoveredCharacteristic& characteristic, - const DiscoveryCallback_t& discoveryCallback, - const TerminationCallback_t& terminationCallback - ); - - /** - * @brief indicate if a characteristic descriptor discovery is active for a - * given DiscoveredCharacteristic. - * @param characteristic The characteristic for whom the descriptor might be - * currently discovered. - * @return true if descriptors of characteristic are discovered, false otherwise. - * @note: this will be called by BLE API side. - */ - bool isActive(const DiscoveredCharacteristic& characteristic) const; - - /** - * @brief request the termination of characteristic descriptor discovery - * for a give DiscoveredCharacteristic - * @param characteristic The characteristic for whom the descriptor discovery - * should be stopped. - * @note: this will be called by BLE API side. - */ - void requestTerminate(const DiscoveredCharacteristic& characteristic); - - /** - * @brief process descriptors discovered from the Nordic stack. - * @param connectionHandle The connection handle upon which descriptors has been - * discovered. - * @param descriptors Discovered descriptors. - * @note This will be called by the Nordic stack. - */ - void process(uint16_t connectionHandle, const ble_gattc_evt_desc_disc_rsp_t& descriptors); - - /** - * @brief Called by the Nordic stack when the discovery is over. - * @param The connection handle upon which the discovery process is done. - * @param err An error if the termination is due to an error. - */ - void terminate(uint16_t connectionHandle, ble_error_t err); - - /** - * @brief process attribute informations from the Nordic stack. - * @param connectionHandle The connection handle upon which - * attribute informations has been fetch. - * @param infos Informations around attribute, in that case the - * 128bit UUID of a descriptor. - * @note This will be called by the Nordic stack. - */ - void processAttributeInformation(uint16_t handle, const ble_gattc_evt_attr_info_disc_rsp_t& infos); - -private: - // protection against copy construction and assignment - nRF5xCharacteristicDescriptorDiscoverer(const nRF5xCharacteristicDescriptorDiscoverer&); - nRF5xCharacteristicDescriptorDiscoverer& operator=(const nRF5xCharacteristicDescriptorDiscoverer&); - - /** - * @brief Discovery process, it store the DiscoveredCharacteristic, the - * discovery callback and the termination callback. - */ - class Discovery { - public: - /** - * @brief Construct an empty discovery, such can be considerate as a not running discovery. - * @note #isEmpty function will return true - */ - Discovery(); - - /** - * @brief Construct a valid discovery process. - * - * @param c the characteristic from whom descriptors will be discovered. - * @param dCb The discovery callback called each time a descriptor is discovered. - * @param tCb The termination callback called when the discovery terminate. - * - * @note #isEmpty function will return false - */ - Discovery(const DiscoveredCharacteristic& c, const DiscoveryCallback_t& dCb, const TerminationCallback_t& tCb); - - /** - * @brief Process the discovery of a descriptor. - * - * @param handle The attribute handle of the descriptor found - * @param uuid The UUID of the descriptor found. - */ - void process(GattAttribute::Handle_t handle, const UUID& uuid); - - /** - * @brief Terminate the discovery process. - * - * @param err Error associate with the termination - * @note after this call #isEmpty function will return true. - */ - void terminate(ble_error_t err); - - /** - * @brief check if the discovery process is empty or not. Empty discovery are - * not running. - * - * @detail Discovery are empty after: - * - a default construction - * - a copy construction form a default constructed - * - an assignment from a default constructed Discovery - * @return true if the Discovery is empty and false otherwise. - */ - bool isEmpty() const; - - /** - * @brief return the characteristic from whom descriptors are discovered. - * @return the characteristic from whom descriptors are discovered. - */ - const DiscoveredCharacteristic& getCharacteristic() const; - - /** - * @brief equal to operator, test if two discovery process are equal - * - * @param lhs left hand side of the expression - * @param rhs right hand side of the expression - * @return true if lhs == rhs - */ - friend bool operator==(const Discovery& lhs, const Discovery& rhs) { - return lhs.characteristic == rhs.characteristic && - lhs.onDiscovery == rhs.onDiscovery && - lhs.onTerminate == rhs.onTerminate; - } - - /** - * @brief not equal to operator, test if two discovery process are not equal - * - * @param lhs left hand side of the expression - * @param rhs right hand side of the expression - * @return true if lhs != rhs - */ - friend bool operator!=(const Discovery& lhs, const Discovery& rhs) { - return !(lhs == rhs); - } - - private: - DiscoveredCharacteristic characteristic; - DiscoveryCallback_t onDiscovery; - TerminationCallback_t onTerminate; - }; - - // find a running discovery process - Discovery* findRunningDiscovery(const DiscoveredCharacteristic& characteristic); - Discovery* findRunningDiscovery(uint16_t handle); - - // Called to terminate a discovery is over. - void terminate(Discovery* discovery, ble_error_t err); - - // get one slot for a discovery process - Discovery* getAvailableDiscoverySlot(); - - // indicate if a connection is already running a discovery - bool isConnectionInUse(uint16_t connHandle); - - // low level start of a discovery - static ble_error_t gattc_descriptors_discover(uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle); - - // discovery of 128bits UUIDS - static ble_error_t gattc_attr_info_discover(uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle); - - // count of concurrent connections which can run a descriptor discovery process - static const size_t MAXIMUM_CONCURRENT_CONNECTIONS_COUNT = 3; - - // array of running discoveries - Discovery discoveryRunning[MAXIMUM_CONCURRENT_CONNECTIONS_COUNT]; -}; - -#endif /*__NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__*/ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp deleted file mode 100644 index f7d6996f4d8..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xDiscoveredCharacteristic.h" -#include "nRF5xGattClient.h" -#include "headers/nrf_ble_gatt.h" - -void -nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn) -{ - gattc = gattcIn; - connHandle = connectionHandleIn; - declHandle = declHandleIn; - valueHandle = valueHandleIn; - - props._broadcast = propsIn.broadcast; - props._read = propsIn.read; - props._writeWoResp = propsIn.write_wo_resp; - props._write = propsIn.write; - props._notify = propsIn.notify; - props._indicate = propsIn.indicate; - props._authSignedWrite = propsIn.auth_signed_wr; -} - -void -nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - UUID::ShortUUIDBytes_t uuidIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn) -{ - gattc = gattcIn; - connHandle = connectionHandleIn; - uuid = uuidIn; - declHandle = declHandleIn; - valueHandle = valueHandleIn; - - props._broadcast = propsIn.broadcast; - props._read = propsIn.read; - props._writeWoResp = propsIn.write_wo_resp; - props._write = propsIn.write; - props._notify = propsIn.notify; - props._indicate = propsIn.indicate; - props._authSignedWrite = propsIn.auth_signed_wr; -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h deleted file mode 100644 index 87ebbbf7679..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF_DISCOVERED_CHARACTERISTIC_H__ -#define __NRF_DISCOVERED_CHARACTERISTIC_H__ - -#include "ble/DiscoveredCharacteristic.h" -#include "headers/nrf_ble_gatt.h" - -class nRF5xGattClient; /* forward declaration */ - -class nRF5xDiscoveredCharacteristic : public DiscoveredCharacteristic { -public: - void setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn); - - void setup(nRF5xGattClient *gattcIn, - Gap::Handle_t connectionHandleIn, - UUID::ShortUUIDBytes_t uuidIn, - ble_gatt_char_props_t propsIn, - GattAttribute::Handle_t declHandleIn, - GattAttribute::Handle_t valueHandleIn); - - void setLastHandle(GattAttribute::Handle_t last) { - lastHandle = last; - } -}; - -#endif /* __NRF_DISCOVERED_CHARACTERISTIC_H__ */ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp deleted file mode 100644 index e79e47afa24..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp +++ /dev/null @@ -1,50 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xGattClient.h" - -#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) -ble_error_t -nRF5xGattClient::launchServiceDiscovery(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc, - ServiceDiscovery::CharacteristicCallback_t cc, - const UUID &matchingServiceUUIDIn, - const UUID &matchingCharacteristicUUIDIn) -{ - return _discovery.launch(connectionHandle, sc, cc, matchingServiceUUIDIn, matchingCharacteristicUUIDIn); -} - -ble_error_t nRF5xGattClient::discoverCharacteristicDescriptors( - const DiscoveredCharacteristic& characteristic, - const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback) -{ - return _characteristicDescriptorDiscoverer.launch( - characteristic, - discoveryCallback, - terminationCallback - ); -} - -bool nRF5xGattClient::isCharacteristicDescriptorsDiscoveryActive(const DiscoveredCharacteristic& characteristic) const { - return _characteristicDescriptorDiscoverer.isActive(characteristic); -} - -void nRF5xGattClient::terminateCharacteristicDescriptorsDiscovery(const DiscoveredCharacteristic& characteristic) { - return _characteristicDescriptorDiscoverer.requestTerminate(characteristic); -} - -#endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h deleted file mode 100644 index 5670d15b9d1..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h +++ /dev/null @@ -1,218 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF51822_GATT_CLIENT_H__ -#define __NRF51822_GATT_CLIENT_H__ - -#include "ble/GattClient.h" -#include "nRF5xServiceDiscovery.h" -#include "nRF5xCharacteristicDescriptorDiscoverer.h" - -class nRF5xGattClient : public GattClient -{ -public: - /** - * When using S110, all Gatt client features will return - * BLE_ERROR_NOT_IMPLEMENTED - */ -#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) - - /** - * Launch service discovery. Once launched, service discovery will remain - * active with callbacks being issued back into the application for matching - * services/characteristics. isActive() can be used to determine status; and - * a termination callback (if setup) will be invoked at the end. Service - * discovery can be terminated prematurely if needed using terminate(). - * - * @param connectionHandle - * Handle for the connection with the peer. - * @param sc - * This is the application callback for matching service. Taken as - * NULL by default. Note: service discovery may still be active - * when this callback is issued; calling asynchronous BLE-stack - * APIs from within this application callback might cause the - * stack to abort service discovery. If this becomes an issue, it - * may be better to make local copy of the discoveredService and - * wait for service discovery to terminate before operating on the - * service. - * @param cc - * This is the application callback for matching characteristic. - * Taken as NULL by default. Note: service discovery may still be - * active when this callback is issued; calling asynchronous - * BLE-stack APIs from within this application callback might cause - * the stack to abort service discovery. If this becomes an issue, - * it may be better to make local copy of the discoveredCharacteristic - * and wait for service discovery to terminate before operating on the - * characteristic. - * @param matchingServiceUUID - * UUID based filter for specifying a service in which the application is - * interested. By default it is set as the wildcard UUID_UNKNOWN, - * in which case it matches all services. If characteristic-UUID - * filter (below) is set to the wildcard value, then a service - * callback will be invoked for the matching service (or for every - * service if the service filter is a wildcard). - * @param matchingCharacteristicUUIDIn - * UUID based filter for specifying characteristic in which the application - * is interested. By default it is set as the wildcard UUID_UKNOWN - * to match against any characteristic. If both service-UUID - * filter and characteristic-UUID filter are used with non- wildcard - * values, then only a single characteristic callback is - * invoked for the matching characteristic. - * - * @Note Using wildcard values for both service-UUID and characteristic- - * UUID will result in complete service discovery--callbacks being - * called for every service and characteristic. - * - * @return - * BLE_ERROR_NONE if service discovery is launched successfully; else an appropriate error. - */ - virtual ble_error_t launchServiceDiscovery(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc = NULL, - ServiceDiscovery::CharacteristicCallback_t cc = NULL, - const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN), - const UUID &matchingCharacteristicUUIDIn = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)); - - virtual void onServiceDiscoveryTermination(ServiceDiscovery::TerminationCallback_t callback) { - _discovery.onTermination(callback); - } - - /** - * Is service-discovery currently active? - */ - virtual bool isServiceDiscoveryActive(void) const { - return _discovery.isActive(); - } - - /** - * Terminate an ongoing service-discovery. This should result in an - * invocation of the TerminationCallback if service-discovery is active. - */ - virtual void terminateServiceDiscovery(void) { - _discovery.terminate(); - } - - /** - * @brief Implementation of GattClient::discoverCharacteristicDescriptors - * @see GattClient::discoverCharacteristicDescriptors - */ - virtual ble_error_t discoverCharacteristicDescriptors( - const DiscoveredCharacteristic& characteristic, - const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback - ); - - /** - * @brief Implementation of GattClient::isCharacteristicDiscoveryActive - * @see GattClient::isCharacteristicDiscoveryActive - */ - virtual bool isCharacteristicDescriptorsDiscoveryActive(const DiscoveredCharacteristic& characteristic) const; - - /** - * @brief Implementation of GattClient::terminateCharacteristicDiscovery - * @see GattClient::terminateCharacteristicDiscovery - */ - virtual void terminateCharacteristicDescriptorsDiscovery(const DiscoveredCharacteristic& characteristic); - - virtual ble_error_t read(Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, uint16_t offset) const { - uint32_t rc = sd_ble_gattc_read(connHandle, attributeHandle, offset); - if (rc == NRF_SUCCESS) { - return BLE_ERROR_NONE; - } - switch (rc) { - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_STATE: - case NRF_ERROR_INVALID_ADDR: - default: - return BLE_ERROR_INVALID_STATE; - } - } - - virtual ble_error_t write(GattClient::WriteOp_t cmd, Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, size_t length, const uint8_t *value) const { - ble_gattc_write_params_t writeParams; - writeParams.write_op = cmd; - writeParams.flags = 0; /* this is inconsequential */ - writeParams.handle = attributeHandle; - writeParams.offset = 0; - writeParams.len = length; - writeParams.p_value = const_cast(value); - - uint32_t rc = sd_ble_gattc_write(connHandle, &writeParams); - if (rc == NRF_SUCCESS) { - return BLE_ERROR_NONE; - } - switch (rc) { - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - case BLE_ERROR_NO_TX_PACKETS: - return BLE_ERROR_NO_MEM; - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_STATE: - case NRF_ERROR_INVALID_ADDR: - default: - return BLE_ERROR_INVALID_STATE; - } - } - - /** - * @brief Clear nRF5xGattClient's state. - * - * @return - * BLE_ERROR_NONE if successful. - */ - virtual ble_error_t reset(void) { - /* Clear all state that is from the parent, including private members */ - if (GattClient::reset() != BLE_ERROR_NONE) { - return BLE_ERROR_INVALID_STATE; - } - - /* Clear derived class members */ - _discovery.reset(); - - return BLE_ERROR_NONE; - } - -public: - /* - * Allow instantiation from nRF5xn when required. - */ - friend class nRF5xn; - - nRF5xGattClient() : _discovery(this) { - /* empty */ - } - - nRF5xServiceDiscovery& discovery() { - return _discovery; - } - - nRF5xCharacteristicDescriptorDiscoverer& characteristicDescriptorDiscoverer() { - return _characteristicDescriptorDiscoverer; - } - -private: - nRF5xGattClient(const nRF5xGattClient &); - const nRF5xGattClient& operator=(const nRF5xGattClient &); - -private: - nRF5xServiceDiscovery _discovery; - nRF5xCharacteristicDescriptorDiscoverer _characteristicDescriptorDiscoverer; - -#endif // if !S110 -}; - -#endif // ifndef __NRF51822_GATT_CLIENT_H__ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp index 5ab02d702b7..8bcdd7d07a8 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp @@ -131,6 +131,7 @@ ble_error_t nRF5xGattServer::addService(GattService &service) } GattCharacteristic *p_char = service.getCharacteristic(i); GattAttribute *p_description_descriptor = NULL; + GattAttribute *p_presentation_format_descriptor = NULL; /* Skip any incompletely defined, read-only characteristics. */ if ((p_char->getValueAttribute().getValuePtr() == NULL) && @@ -141,11 +142,13 @@ ble_error_t nRF5xGattServer::addService(GattService &service) nordicUUID = custom_convert_to_nordic_uuid(p_char->getValueAttribute().getUUID()); - /* The user-description descriptor is a special case which needs to be - * handled at the time of adding the characteristic. The following block - * is meant to discover its presence. */ + /* The user-description and presentation-format descriptors are special cases + * that need to be handled at the time of adding each characteristic. The + * following block is meant to discover their presence. */ const uint8_t *userDescriptionDescriptorValuePtr = NULL; uint16_t userDescriptionDescriptorValueLen = 0; + const uint8_t *presentationFormatDescriptorValuePtr = NULL; + uint16_t presentationFormatDescriptorValueLen = 0; for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) { GattAttribute *p_desc = p_char->getDescriptor(j); if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) { @@ -153,6 +156,11 @@ ble_error_t nRF5xGattServer::addService(GattService &service) userDescriptionDescriptorValuePtr = p_desc->getValuePtr(); userDescriptionDescriptorValueLen = p_desc->getLength(); } + if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT) { + p_presentation_format_descriptor = p_desc; + presentationFormatDescriptorValuePtr = p_desc->getValuePtr(); + presentationFormatDescriptorValueLen = p_desc->getLength(); + } } ASSERT_TRUE ( ERROR_NONE == @@ -166,6 +174,8 @@ ble_error_t nRF5xGattServer::addService(GattService &service) p_char->getValueAttribute().hasVariableLength(), userDescriptionDescriptorValuePtr, userDescriptionDescriptorValueLen, + presentationFormatDescriptorValuePtr, + presentationFormatDescriptorValueLen, p_char->isReadAuthorizationEnabled(), p_char->isWriteAuthorizationEnabled(), &nrfCharacteristicHandles[characteristicCount]), @@ -179,6 +189,10 @@ ble_error_t nRF5xGattServer::addService(GattService &service) nrfCharacteristicHandles[characteristicCount].user_desc_handle ); } + if (p_presentation_format_descriptor) { + // The handle is not available from the SoftDevice + p_presentation_format_descriptor->setHandle(GattAttribute::INVALID_HANDLE); + } characteristicCount++; /* Add optional descriptors if any */ @@ -188,8 +202,10 @@ ble_error_t nRF5xGattServer::addService(GattService &service) } GattAttribute *p_desc = p_char->getDescriptor(j); - /* skip the user-description-descriptor here; this has already been handled when adding the characteristic (above). */ - if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) { + /* skip the user-description or presentation-format descriptor here; + * they have already been handled when adding the characteristic (above). */ + if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC + || p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT) { continue; } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp deleted file mode 100644 index 79f691bfcf6..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp +++ /dev/null @@ -1,329 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "nRF5xServiceDiscovery.h" - -ble_error_t -nRF5xServiceDiscovery::launchCharacteristicDiscovery(Gap::Handle_t connectionHandle, - Gap::Handle_t startHandle, - Gap::Handle_t endHandle) -{ - characteristicDiscoveryStarted(connectionHandle); - - ble_gattc_handle_range_t handleRange = { - (uint16_t) startHandle, - (uint16_t) endHandle - }; - uint32_t rc = sd_ble_gattc_characteristics_discover(connectionHandle, &handleRange); - ble_error_t err = BLE_ERROR_NONE; - - switch (rc) { - case NRF_SUCCESS: - err = BLE_ERROR_NONE; - break; - case BLE_ERROR_INVALID_CONN_HANDLE: - case NRF_ERROR_INVALID_ADDR: - err = BLE_ERROR_INVALID_PARAM; - break; - case NRF_ERROR_BUSY: - err = BLE_STACK_BUSY; - break; - case NRF_ERROR_INVALID_STATE: - err = BLE_ERROR_INVALID_STATE; - break; - default: - err = BLE_ERROR_UNSPECIFIED; - break; - } - - if (err) { - terminateCharacteristicDiscovery(err); - } - return err; -} - -void -nRF5xServiceDiscovery::setupDiscoveredServices(const ble_gattc_evt_prim_srvc_disc_rsp_t *response) -{ - serviceIndex = 0; - numServices = response->count; - - /* Account for the limitation on the number of discovered services we can handle at a time. */ - if (numServices > BLE_DB_DISCOVERY_MAX_SRV) { - numServices = BLE_DB_DISCOVERY_MAX_SRV; - } - - serviceUUIDDiscoveryQueue.reset(); - for (unsigned i = 0; i < numServices; ++i) { - if (response->services[i].uuid.type == BLE_UUID_TYPE_UNKNOWN) { - serviceUUIDDiscoveryQueue.enqueue(i); - services[i].setup(response->services[i].handle_range.start_handle, - response->services[i].handle_range.end_handle); - } else { - services[i].setup(response->services[i].uuid.uuid, - response->services[i].handle_range.start_handle, - response->services[i].handle_range.end_handle); - } - } - - /* Trigger discovery of service UUID if necessary. */ - if (serviceUUIDDiscoveryQueue.getCount()) { - serviceUUIDDiscoveryQueue.triggerFirst(); - } -} - -void -nRF5xServiceDiscovery::setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response) -{ - numCharacteristics = response->count; - - /* Account for the limitation on the number of discovered characteristics we can handle at a time. */ - if (numCharacteristics > BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV) { - numCharacteristics = BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV; - } - - charUUIDDiscoveryQueue.reset(); - for (unsigned charIndex = 0; charIndex < numCharacteristics; charIndex++) { - if (response->chars[charIndex].uuid.type == BLE_UUID_TYPE_UNKNOWN) { - charUUIDDiscoveryQueue.enqueue(charIndex); - characteristics[charIndex].setup(gattc, - connHandle, - response->chars[charIndex].char_props, - response->chars[charIndex].handle_decl, - response->chars[charIndex].handle_value); - } else { - characteristics[charIndex].setup(gattc, - connHandle, - response->chars[charIndex].uuid.uuid, - response->chars[charIndex].char_props, - response->chars[charIndex].handle_decl, - response->chars[charIndex].handle_value); - } - } - - /* Trigger discovery of char UUID if necessary. */ - if (charUUIDDiscoveryQueue.getCount()) { - charUUIDDiscoveryQueue.triggerFirst(); - } -} - -void -nRF5xServiceDiscovery::progressCharacteristicDiscovery(void) -{ - if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) { - return; - } - - if ((discoveredCharacteristic != nRF5xDiscoveredCharacteristic()) && (numCharacteristics > 0)) { - discoveredCharacteristic.setLastHandle(characteristics[0].getDeclHandle() - 1); - - if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - ((matchingCharacteristicUUID == discoveredCharacteristic.getUUID()) && - (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) { - if (characteristicCallback) { - characteristicCallback(&discoveredCharacteristic); - } - } - } - - for (uint8_t i = 0; i < numCharacteristics; ++i) { - if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) { - return; - } - - if (i == (numCharacteristics - 1)) { - discoveredCharacteristic = characteristics[i]; - break; - } else { - characteristics[i].setLastHandle(characteristics[i + 1].getDeclHandle() - 1); - } - - if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - ((matchingCharacteristicUUID == characteristics[i].getUUID()) && - (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) { - if (characteristicCallback) { - characteristicCallback(&characteristics[i]); - } - } - } - - if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) { - return; - } - - Gap::Handle_t startHandle = (numCharacteristics > 0) ? characteristics[numCharacteristics - 1].getValueHandle() + 1 : SRV_DISC_END_HANDLE; - Gap::Handle_t endHandle = services[serviceIndex].getEndHandle(); - resetDiscoveredCharacteristics(); /* Note: resetDiscoveredCharacteristics() must come after fetching start and end Handles. */ - - if (startHandle < endHandle) { - ble_gattc_handle_range_t handleRange = { - (uint16_t) startHandle, - (uint16_t) endHandle - }; - if (sd_ble_gattc_characteristics_discover(connHandle, &handleRange) != NRF_SUCCESS) { - terminateCharacteristicDiscovery(BLE_ERROR_UNSPECIFIED); - } - } else { - terminateCharacteristicDiscovery(BLE_ERROR_NONE); - } -} - -void -nRF5xServiceDiscovery::progressServiceDiscovery(void) -{ - /* Iterate through the previously discovered services cached in services[]. */ - while ((state == SERVICE_DISCOVERY_ACTIVE) && (serviceIndex < numServices)) { - if ((matchingServiceUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - (matchingServiceUUID == services[serviceIndex].getUUID())) { - - if (serviceCallback && (matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN))) { - serviceCallback(&services[serviceIndex]); - } - - if ((state == SERVICE_DISCOVERY_ACTIVE) && characteristicCallback) { - launchCharacteristicDiscovery(connHandle, services[serviceIndex].getStartHandle(), services[serviceIndex].getEndHandle()); - } else { - serviceIndex++; - } - } else { - serviceIndex++; - } - } - - /* Relaunch discovery of new services beyond the last entry cached in services[]. */ - if ((state == SERVICE_DISCOVERY_ACTIVE) && (numServices > 0) && (serviceIndex > 0)) { - /* Determine the ending handle of the last cached service. */ - Gap::Handle_t endHandle = services[serviceIndex - 1].getEndHandle(); - resetDiscoveredServices(); /* Note: resetDiscoveredServices() must come after fetching endHandle. */ - - if (endHandle == SRV_DISC_END_HANDLE) { - terminateServiceDiscovery(); - } else { - // the next service is located after the last handle discovered - // Launch a new discovery from [endHandle + 1 : 0xFFFF] - if (sd_ble_gattc_primary_services_discover(connHandle, endHandle + 1, NULL) != NRF_SUCCESS) { - terminateServiceDiscovery(); - } - } - } -} - -void -nRF5xServiceDiscovery::ServiceUUIDDiscoveryQueue::triggerFirst(void) -{ - while (numIndices) { /* loop until a call to char_value_by_uuid_read() succeeds or we run out of pending indices. */ - parentDiscoveryObject->state = DISCOVER_SERVICE_UUIDS; - - unsigned serviceIndex = getFirst(); - ble_uuid_t uuid = { - .uuid = BLE_UUID_SERVICE_PRIMARY, - .type = BLE_UUID_TYPE_BLE, - }; - ble_gattc_handle_range_t handleRange = { - .start_handle = parentDiscoveryObject->services[serviceIndex].getStartHandle(), - .end_handle = parentDiscoveryObject->services[serviceIndex].getEndHandle(), - }; - if (sd_ble_gattc_char_value_by_uuid_read(parentDiscoveryObject->connHandle, &uuid, &handleRange) == NRF_SUCCESS) { - return; - } - - /* Skip this service if we fail to launch a read for its service-declaration - * attribute. Its UUID will remain INVALID, and it may not match any filters. */ - dequeue(); - } - - /* Switch back to service discovery upon exhausting the service-indices pending UUID discovery. */ - if (parentDiscoveryObject->state == DISCOVER_SERVICE_UUIDS) { - parentDiscoveryObject->state = SERVICE_DISCOVERY_ACTIVE; - } -} - -void -nRF5xServiceDiscovery::CharUUIDDiscoveryQueue::triggerFirst(void) -{ - while (numIndices) { /* loop until a call to char_value_by_uuid_read() succeeds or we run out of pending indices. */ - parentDiscoveryObject->state = DISCOVER_CHARACTERISTIC_UUIDS; - - unsigned charIndex = getFirst(); - ble_uuid_t uuid = { - .uuid = BLE_UUID_CHARACTERISTIC, - .type = BLE_UUID_TYPE_BLE, - }; - ble_gattc_handle_range_t handleRange = { }; - handleRange.start_handle = parentDiscoveryObject->characteristics[charIndex].getDeclHandle(); - handleRange.end_handle = parentDiscoveryObject->characteristics[charIndex].getDeclHandle() + 1; - if (sd_ble_gattc_char_value_by_uuid_read(parentDiscoveryObject->connHandle, &uuid, &handleRange) == NRF_SUCCESS) { - return; - } - - /* Skip this service if we fail to launch a read for its service-declaration - * attribute. Its UUID will remain INVALID, and it may not match any filters. */ - dequeue(); - } - - /* Switch back to service discovery upon exhausting the service-indices pending UUID discovery. */ - if (parentDiscoveryObject->state == DISCOVER_CHARACTERISTIC_UUIDS) { - parentDiscoveryObject->state = CHARACTERISTIC_DISCOVERY_ACTIVE; - } -} - -void -nRF5xServiceDiscovery::processDiscoverUUIDResponse(const ble_gattc_evt_t *p_gattc_evt) -{ - const ble_gattc_evt_char_val_by_uuid_read_rsp_t * response = &p_gattc_evt->params.char_val_by_uuid_read_rsp; - - if (state == DISCOVER_SERVICE_UUIDS) { - if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID)) { - UUID::LongUUIDBytes_t uuid; - -#if (NRF_SD_BLE_API_VERSION >= 3) - ble_gattc_handle_value_t iter; - memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); - (void) sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(const_cast(p_gattc_evt), &iter); - memcpy(uuid, iter.p_value, UUID::LENGTH_OF_LONG_UUID); -#else - memcpy(uuid, &(response->handle_value[0].p_value[0]), UUID::LENGTH_OF_LONG_UUID); -#endif - - unsigned serviceIndex = serviceUUIDDiscoveryQueue.dequeue(); - services[serviceIndex].setupLongUUID(uuid, UUID::LSB); - - serviceUUIDDiscoveryQueue.triggerFirst(); - } else { - serviceUUIDDiscoveryQueue.dequeue(); - } - } else if (state == DISCOVER_CHARACTERISTIC_UUIDS) { - if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID + 1 /* props */ + 2 /* value handle */)) { - UUID::LongUUIDBytes_t uuid; - -#if (NRF_SD_BLE_API_VERSION >= 3) - ble_gattc_handle_value_t iter; - memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); - (void) sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(const_cast(p_gattc_evt), &iter); - memcpy(uuid, &(iter.p_value[3]), UUID::LENGTH_OF_LONG_UUID); -#else - memcpy(uuid, &(response->handle_value[0].p_value[3]), UUID::LENGTH_OF_LONG_UUID); -#endif - - unsigned charIndex = charUUIDDiscoveryQueue.dequeue(); - characteristics[charIndex].setupLongUUID(uuid, UUID::LSB); - - charUUIDDiscoveryQueue.triggerFirst(); - } else { - charUUIDDiscoveryQueue.dequeue(); - } - } -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h deleted file mode 100644 index 9fb28f1d798..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h +++ /dev/null @@ -1,366 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __NRF_SERVICE_DISCOVERY_H__ -#define __NRF_SERVICE_DISCOVERY_H__ - -#include "ble/ServiceDiscovery.h" -#include "ble/DiscoveredService.h" -#include "nRF5xDiscoveredCharacteristic.h" - -#include "headers/nrf_ble.h" -#include "headers/nrf_ble_gattc.h" - -class nRF5xGattClient; /* forward declaration */ - -class nRF5xServiceDiscovery : public ServiceDiscovery -{ -public: - static const uint16_t SRV_DISC_START_HANDLE = 0x0001; /**< The start handle value used during service discovery. */ - static const uint16_t SRV_DISC_END_HANDLE = 0xFFFF; /**< The end handle value used during service discovery. */ - -public: - static const unsigned BLE_DB_DISCOVERY_MAX_SRV = 4; /**< Maximum number of services we can retain information for after a single discovery. */ - static const unsigned BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV = 4; /**< Maximum number of characteristics per service we can retain information for. */ - -public: - nRF5xServiceDiscovery(nRF5xGattClient *gattcIn) : - gattc(gattcIn), - serviceIndex(0), - numServices(0), - numCharacteristics(0), - state(INACTIVE), - services(), - characteristics(), - serviceUUIDDiscoveryQueue(this), - charUUIDDiscoveryQueue(this), - onTerminationCallback(NULL) { - /* empty */ - } - - virtual ble_error_t launch(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc, - ServiceDiscovery::CharacteristicCallback_t cc, - const UUID &matchingServiceUUIDIn, - const UUID &matchingCharacteristicUUIDIn) - { - if (isActive()) { - return BLE_ERROR_INVALID_STATE; - } - - serviceCallback = sc; - characteristicCallback = cc; - matchingServiceUUID = matchingServiceUUIDIn; - matchingCharacteristicUUID = matchingCharacteristicUUIDIn; - - serviceDiscoveryStarted(connectionHandle); - - uint32_t rc; - if ((rc = sd_ble_gattc_primary_services_discover(connectionHandle, SRV_DISC_START_HANDLE, NULL)) != NRF_SUCCESS) { - terminate(); - switch (rc) { - case NRF_ERROR_INVALID_PARAM: - case BLE_ERROR_INVALID_CONN_HANDLE: - return BLE_ERROR_INVALID_PARAM; - case NRF_ERROR_BUSY: - return BLE_STACK_BUSY; - default: - case NRF_ERROR_INVALID_STATE: - return BLE_ERROR_INVALID_STATE; - } - } - - return BLE_ERROR_NONE; - } - - virtual bool isActive(void) const { - return state != INACTIVE; - } - - virtual void terminate(void) { - terminateServiceDiscovery(); - } - - void terminate(Gap::Handle_t connectionHandle) { - if(connHandle == connectionHandle) { - terminate(); - } - } - - virtual void onTermination(ServiceDiscovery::TerminationCallback_t callback) { - onTerminationCallback = callback; - } - - /** - * @brief Clear nRF5xServiceDiscovery's state. - * - * @return - * BLE_ERROR_NONE if successful. - */ - virtual ble_error_t reset(void) { - /* Clear all state that is from the parent, including private members */ - if (ServiceDiscovery::reset() != BLE_ERROR_NONE) { - return BLE_ERROR_INVALID_STATE; - } - - /* Clear derived class members */ - serviceIndex = 0; - numServices = 0; - numCharacteristics = 0; - - state = INACTIVE; - - serviceUUIDDiscoveryQueue.reset(); - charUUIDDiscoveryQueue.reset(); - - onTerminationCallback = NULL; - - return BLE_ERROR_NONE; - } - -private: - ble_error_t launchCharacteristicDiscovery(Gap::Handle_t connectionHandle, Gap::Handle_t startHandle, Gap::Handle_t endHandle); - -private: - void setupDiscoveredServices(const ble_gattc_evt_prim_srvc_disc_rsp_t *response); - void setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response); - - void triggerServiceUUIDDiscovery(void); - void processDiscoverUUIDResponse(const ble_gattc_evt_t *p_gattc_evt); - void removeFirstServiceNeedingUUIDDiscovery(void); - - void terminateServiceDiscovery(void) { - discoveredCharacteristic = nRF5xDiscoveredCharacteristic(); - - bool wasActive = isActive(); - state = INACTIVE; - - if (wasActive && onTerminationCallback) { - onTerminationCallback(connHandle); - } - } - - void terminateCharacteristicDiscovery(ble_error_t err) { - if (state == CHARACTERISTIC_DISCOVERY_ACTIVE) { - if(discoveredCharacteristic != nRF5xDiscoveredCharacteristic()) { - if(err == BLE_ERROR_NONE) { - // fullfill the last characteristic - discoveredCharacteristic.setLastHandle(services[serviceIndex].getEndHandle()); - - if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) || - ((matchingCharacteristicUUID == discoveredCharacteristic.getUUID()) && - (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) { - if (characteristicCallback) { - characteristicCallback(&discoveredCharacteristic); - } - } - } - discoveredCharacteristic = nRF5xDiscoveredCharacteristic(); - } - - state = SERVICE_DISCOVERY_ACTIVE; - } - serviceIndex++; /* Progress service index to keep discovery alive. */ - } - -private: - void resetDiscoveredServices(void) { - numServices = 0; - serviceIndex = 0; - } - - void resetDiscoveredCharacteristics(void) { - numCharacteristics = 0; - } - -private: - void serviceDiscoveryStarted(Gap::Handle_t connectionHandle) { - connHandle = connectionHandle; - resetDiscoveredServices(); - state = SERVICE_DISCOVERY_ACTIVE; - } - -private: - void characteristicDiscoveryStarted(Gap::Handle_t connectionHandle) { - connHandle = connectionHandle; - resetDiscoveredCharacteristics(); - state = CHARACTERISTIC_DISCOVERY_ACTIVE; - } - -private: - /** - * A datatype to contain service-indices for which long UUIDs need to be - * discovered using read_val_by_uuid(). - */ - class ServiceUUIDDiscoveryQueue { - public: - ServiceUUIDDiscoveryQueue(nRF5xServiceDiscovery *parent) : - numIndices(0), - serviceIndices(), - parentDiscoveryObject(parent) { - /* empty */ - } - - public: - void reset(void) { - numIndices = 0; - for (unsigned i = 0; i < BLE_DB_DISCOVERY_MAX_SRV; i++) { - serviceIndices[i] = INVALID_INDEX; - } - } - void enqueue(int serviceIndex) { - serviceIndices[numIndices++] = serviceIndex; - } - int dequeue(void) { - if (numIndices == 0) { - return INVALID_INDEX; - } - - unsigned valueToReturn = serviceIndices[0]; - numIndices--; - for (unsigned i = 0; i < numIndices; i++) { - serviceIndices[i] = serviceIndices[i + 1]; - } - - return valueToReturn; - } - unsigned getFirst(void) const { - return serviceIndices[0]; - } - size_t getCount(void) const { - return numIndices; - } - - /** - * Trigger UUID discovery for the first of the enqueued ServiceIndices. - */ - void triggerFirst(void); - - private: - static const int INVALID_INDEX = -1; - - private: - size_t numIndices; - int serviceIndices[BLE_DB_DISCOVERY_MAX_SRV]; - - nRF5xServiceDiscovery *parentDiscoveryObject; - }; - friend class ServiceUUIDDiscoveryQueue; - - /** - * A datatype to contain characteristic-indices for which long UUIDs need to - * be discovered using read_val_by_uuid(). - */ - class CharUUIDDiscoveryQueue { - public: - CharUUIDDiscoveryQueue(nRF5xServiceDiscovery *parent) : - numIndices(0), - charIndices(), - parentDiscoveryObject(parent) { - /* empty */ - } - - public: - void reset(void) { - numIndices = 0; - for (unsigned i = 0; i < BLE_DB_DISCOVERY_MAX_SRV; i++) { - charIndices[i] = INVALID_INDEX; - } - } - void enqueue(int serviceIndex) { - charIndices[numIndices++] = serviceIndex; - } - int dequeue(void) { - if (numIndices == 0) { - return INVALID_INDEX; - } - - unsigned valueToReturn = charIndices[0]; - numIndices--; - for (unsigned i = 0; i < numIndices; i++) { - charIndices[i] = charIndices[i + 1]; - } - - return valueToReturn; - } - unsigned getFirst(void) const { - return charIndices[0]; - } - size_t getCount(void) const { - return numIndices; - } - - /** - * Trigger UUID discovery for the first of the enqueued charIndices. - */ - void triggerFirst(void); - - private: - static const int INVALID_INDEX = -1; - - private: - size_t numIndices; - int charIndices[BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV]; - - nRF5xServiceDiscovery *parentDiscoveryObject; - }; - friend class CharUUIDDiscoveryQueue; - -private: - friend void bleGattcEventHandler(const ble_evt_t *p_ble_evt); - void progressCharacteristicDiscovery(void); - void progressServiceDiscovery(void); - -private: - nRF5xGattClient *gattc; - -private: - uint8_t serviceIndex; /**< Index of the current service being discovered. This is intended for internal use during service discovery.*/ - uint8_t numServices; /**< Number of services at the peers GATT database.*/ - uint8_t numCharacteristics; /**< Number of characteristics within the service.*/ - - enum State_t { - INACTIVE, - SERVICE_DISCOVERY_ACTIVE, - CHARACTERISTIC_DISCOVERY_ACTIVE, - DISCOVER_SERVICE_UUIDS, - DISCOVER_CHARACTERISTIC_UUIDS, - } state; - - DiscoveredService services[BLE_DB_DISCOVERY_MAX_SRV]; /**< Information related to the current service being discovered. - * This is intended for internal use during service discovery. */ - nRF5xDiscoveredCharacteristic characteristics[BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV]; - - ServiceUUIDDiscoveryQueue serviceUUIDDiscoveryQueue; - CharUUIDDiscoveryQueue charUUIDDiscoveryQueue; - - TerminationCallback_t onTerminationCallback; - - /* - * The currently discovered characteristic. Discovery of a characteristic - * is a two phase process. - * First, declaration handle is fetched, it provide the UUID, the value handle and - * the properties of a characteristic. - * Second, the next declaration handle is fetched, with its declaration handle, it is - * possible to compute the last handle of the discovered characteristic and fill the - * missing part of the object. - * If there is no remaining characteristic to discover, the last handle of the - * discovered characteristic will be set to the last handle of its enclosing service. - */ - nRF5xDiscoveredCharacteristic discoveredCharacteristic; -}; - -#endif /*__NRF_SERVICE_DISCOVERY_H__*/ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp index 61d9a38d90a..111bfc1bb07 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp @@ -31,6 +31,8 @@ extern "C" { #include "softdevice_handler.h" } +#include "nRF5XPalGattClient.h" + /** * The singleton which represents the nRF51822 transport for the BLE. */ @@ -60,7 +62,7 @@ nRF5xn::nRF5xn(void) : instanceID(BLE::DEFAULT_INSTANCE), gapInstance(), gattServerInstance(NULL), - gattClientInstance(NULL), + gattClient(&(ble::pal::vendor::nordic::nRF5XGattClient::get_client())), securityManagerInstance(NULL) { } @@ -189,11 +191,9 @@ ble_error_t nRF5xn::shutdown(void) /* S110 does not support BLE client features, nothing to reset. */ #if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) - if (gattClientInstance != NULL) { - error = gattClientInstance->reset(); - if (error != BLE_ERROR_NONE) { - return error; - } + error = getGattClient().reset(); + if (error != BLE_ERROR_NONE) { + return error; } #endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h index 33c7926e0d8..154b9e49dc0 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h @@ -20,10 +20,10 @@ #include "ble/BLE.h" #include "ble/blecommon.h" #include "ble/BLEInstanceBase.h" +#include "ble/generic/GenericGattClient.h" #include "nRF5xGap.h" #include "nRF5xGattServer.h" -#include "nRF5xGattClient.h" #include "nRF5xSecurityManager.h" #include "btle.h" @@ -77,11 +77,8 @@ class nRF5xn : public BLEInstanceBase * * @return A reference to GattClient. */ - virtual nRF5xGattClient &getGattClient() { - if (gattClientInstance == NULL) { - gattClientInstance = new nRF5xGattClient(); - } - return *gattClientInstance; + virtual GattClient &getGattClient() { + return gattClient; } /** @@ -171,10 +168,8 @@ class nRF5xn : public BLEInstanceBase * If NULL, then GattServer has not been initialized. * The pointer has been declared as 'mutable' so that * it can be assigned inside a 'const' function. */ - mutable nRF5xGattClient *gattClientInstance; /**< Pointer to the GattClient object instance. - * If NULL, then GattClient has not been initialized. - * The pointer has been declared as 'mutable' so that - * it can be assigned inside a 'const' function. */ + ble::generic::GenericGattClient gattClient; + mutable nRF5xSecurityManager *securityManagerInstance; /**< Pointer to the SecurityManager object instance. * If NULL, then SecurityManager has not been initialized. * The pointer has been declared as 'mutable' so that diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/k64f_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/k64f_emac.c index 4b3c003eb9d..e07e700b153 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/k64f_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/k64f_emac.c @@ -140,7 +140,9 @@ static void k64f_tx_reclaim(struct k64f_enetdata *k64f_enet) */ void enet_mac_rx_isr() { - osThreadFlagsSet(k64f_enetdata.thread, FLAG_RX); + if (k64f_enetdata.thread) { + osThreadFlagsSet(k64f_enetdata.thread, FLAG_RX); + } } void enet_mac_tx_isr() @@ -246,6 +248,16 @@ static err_t low_level_init(struct netif *netif) config.txAccelerConfig = kENET_TxAccelIsShift16Enabled; config.rxAccelerConfig = kENET_RxAccelisShift16Enabled | kENET_RxAccelMacCheckEnabled; ENET_Init(ENET, &g_handle, &config, &buffCfg, netif->hwaddr, sysClock); + +#if defined(TOOLCHAIN_ARM) +#if defined(__OPTIMISE_TIME) && (__ARMCC_VERSION < 5060750) + /* Add multicast groups + work around for https://github.com/ARMmbed/mbed-os/issues/4372 */ + ENET->GAUR = 0xFFFFFFFFu; + ENET->GALR = 0xFFFFFFFFu; +#endif +#endif + ENET_SetCallback(&g_handle, ethernet_callback, netif); ENET_ActiveRead(ENET); @@ -746,6 +758,9 @@ err_t eth_arch_enetif_init(struct netif *netif) /* Worker thread */ k64f_enetdata.thread = sys_thread_new("k64f_emac_thread", emac_thread, netif->state, THREAD_STACKSIZE, THREAD_PRIORITY)->id; + /* Trigger thread to deal with any RX packets that arrived before thread was started */ + enet_mac_rx_isr(); + return ERR_OK; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c new file mode 100644 index 00000000000..096689e5e51 --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_FF_LPC546XX/hardware_init_LPC546XX.c @@ -0,0 +1,227 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_iocon.h" + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INPFILT_OFF 0x0200u /*!<@brief Input filter disabled */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_FAST 0x0400u /*!<@brief Fast mode, slew rate control is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/******************************************************************************* + * Code + ******************************************************************************/ +void lpc546xx_init_eth_hardware(void) +{ + CLOCK_EnableClock(kCLOCK_InputMux); + + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin10_config = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN10 (coords: P2) is configured as SWO */ + IOCON_PinMuxSet(IOCON, 0U, 10U, port0_pin10_config); + + const uint32_t port1_pin10_config = (/* Pin is configured as ENET_TXD1 */ + IOCON_PIO_FUNC1 /* IOCON_PIO_FUNC1 */ | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN10 (coords: E14) is configured as ENET_TXD1 */ + IOCON_PinMuxSet(IOCON, 1U, 10U, port1_pin10_config); + + + const uint32_t port1_pin18_config = (/* Pin is configured as ENET_PHY_RST */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: H11) is configured as ENET_PHY_RST */ + IOCON_PinMuxSet(IOCON, 1U, 18U, port1_pin18_config); + + const uint32_t port1_pin14_config = (/* Pin is configured as ENET_RX_DV */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN14 (coords: B9) is configured as ENET_RX_DV */ + IOCON_PinMuxSet(IOCON, 1U, 14U, port1_pin14_config); + + const uint32_t port1_pin12_config = (/* Pin is configured as ENET_RXD0 */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN12 (coords: A9) is configured as ENET_RXD0 */ + IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config); + + const uint32_t port1_pin13_config = (/* Pin is configured as ENET_RXD1 */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN12 (coords: A6) is configured as ENET_RXD1 */ + IOCON_PinMuxSet(IOCON, 1U, 13U, port1_pin13_config); + + const uint32_t port1_pin11_config = (/* Pin is configured as ENET_TX_EN */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN13 (coords: B6) is configured as ENET_TX_EN */ + IOCON_PinMuxSet(IOCON, 1U, 11U, port1_pin11_config); + + const uint32_t port1_pin15_config = (/* Pin is configured as ENET_RX_CLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN14 (coords: B5) is configured as ENET_RX_CLK */ + IOCON_PinMuxSet(IOCON, 1U, 15U, port1_pin15_config); + + const uint32_t port1_pin16_config = (/* Pin is configured as ENET_MDC */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN15 (coords: A4) is configured as ENET_MDC */ + IOCON_PinMuxSet(IOCON, 1U, 16U, port1_pin16_config); + + const uint32_t port1_pin17_config = (/* Pin is configured as ENET_MDIO */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN16 (coords: C4) is configured as ENET_MDIO */ + IOCON_PinMuxSet(IOCON, 1U, 17U, port1_pin17_config); + + const uint32_t port1_pin9_config = (/* Pin is configured as ENET_TXD0 */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT4 PIN8 (coords: B14) is configured as ENET_TXD0 */ + IOCON_PinMuxSet(IOCON, 1U, 9U, port1_pin9_config); +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/harware_init_LPC546XX.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_LPCXpresso/hardware_init_LPC546XX.c similarity index 100% rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/harware_init_LPC546XX.c rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPC546XX/TARGET_LPCXpresso/hardware_init_LPC546XX.c diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/lwipopts_conf.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/lwipopts_conf.h deleted file mode 100644 index 1ad186c7a14..00000000000 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/lwipopts_conf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright (C) 2012 mbed.org, MIT License - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING - * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef LWIPOPTS_CONF_H -#define LWIPOPTS_CONF_H - -#define LWIP_TRANSPORT_ETHERNET 1 - -#define MEM_SIZE (1600 * 16) - -#endif diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c deleted file mode 100644 index 65515507a05..00000000000 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c +++ /dev/null @@ -1,210 +0,0 @@ -#include "lwip/opt.h" -#include "lwip/tcpip.h" -#include "netif/etharp.h" -#include "lwip/ethip6.h" -#include "mbed_interface.h" -#include "ethernet_api.h" -#include "ethernetext_api.h" - -#define RECV_TASK_PRI (osPriorityNormal) -#define PHY_TASK_PRI (osPriorityNormal) -#define PHY_TASK_WAIT (200) - -/* memory */ -static sys_sem_t recv_ready_sem; /* receive ready semaphore */ - -/* function */ -static void rza1_recv_task(void *arg); -static void rza1_phy_task(void *arg); -#if LWIP_IPV4 -static err_t rza1_etharp_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); -#endif -#if LWIP_IPV6 -static err_t rza1_etharp_output_ipv6(struct netif *netif, struct pbuf *q, const ip6_addr_t *ipaddr); -#endif -static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p); -static void rza1_recv_callback(void); - -static void rza1_recv_task(void *arg) { - struct netif *netif = (struct netif*)arg; - u16_t recv_size; - struct pbuf *p; - int cnt; - - while (1) { - sys_arch_sem_wait(&recv_ready_sem, 0); - for (cnt = 0; cnt < 16; cnt++) { - recv_size = ethernet_receive(); - if (recv_size != 0) { - p = pbuf_alloc(PBUF_RAW, recv_size, PBUF_RAM); - if (p != NULL) { - (void)ethernet_read((char *)p->payload, p->len); - /* full packet send to tcpip_thread to process */ - if (netif->input(p, netif) != ERR_OK) { - /* Free buffer */ - pbuf_free(p); - } - } - } else { - break; - } - } - } -} - -static void rza1_phy_task(void *arg) { - struct netif *netif = (struct netif*)arg; - s32_t connect_sts = 0; /* 0: disconnect, 1:connect */ - s32_t link_sts; - s32_t link_mode_new = NEGO_FAIL; - s32_t link_mode_old = NEGO_FAIL; - - while (1) { - link_sts = ethernet_link(); - if (link_sts == 1) { - link_mode_new = ethernetext_chk_link_mode(); - if (link_mode_new != link_mode_old) { - if (connect_sts == 1) { - tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1); - } - if (link_mode_new != NEGO_FAIL) { - ethernetext_set_link_mode(link_mode_new); - tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1); - connect_sts = 1; - } - } - } else { - if (connect_sts != 0) { - tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1); - link_mode_new = NEGO_FAIL; - connect_sts = 0; - } - } - link_mode_old = link_mode_new; - osDelay(PHY_TASK_WAIT); - } -} - -#if LWIP_IPV4 -static err_t rza1_etharp_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) { - /* Only send packet is link is up */ - if (netif->flags & NETIF_FLAG_LINK_UP) { - return etharp_output(netif, q, ipaddr); - } - - return ERR_CONN; -} -#endif - -#if LWIP_IPV6 -static err_t rza1_etharp_output_ipv6(struct netif *netif, struct pbuf *q, const ip6_addr_t *ipaddr) { - /* Only send packet is link is up */ - if (netif->flags & NETIF_FLAG_LINK_UP) { - return ethip6_output(netif, q, ipaddr); - } - - return ERR_CONN; -} -#endif - -static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p) { - struct pbuf *q; - s32_t cnt; - err_t err = ERR_MEM; - s32_t write_size = 0; - - if ((p->payload != NULL) && (p->len != 0)) { - /* If the first data can't be written, transmit descriptor is full. */ - for (cnt = 0; cnt < 100; cnt++) { - write_size = ethernet_write((char *)p->payload, p->len); - if (write_size != 0) { - break; - } - osDelay(1); - } - if (write_size != 0) { - for (q = p->next; q != NULL; q = q->next) { - (void)ethernet_write((char *)q->payload, q->len); - } - if (ethernet_send() == 1) { - err = ERR_OK; - } - } - } - - return err; -} - -static void rza1_recv_callback(void) { - sys_sem_signal(&recv_ready_sem); -} - -err_t eth_arch_enetif_init(struct netif *netif) -{ - ethernet_cfg_t ethcfg; - - /* set MAC hardware address */ -#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE) - netif->hwaddr[0] = MBED_MAC_ADDR_0; - netif->hwaddr[1] = MBED_MAC_ADDR_1; - netif->hwaddr[2] = MBED_MAC_ADDR_2; - netif->hwaddr[3] = MBED_MAC_ADDR_3; - netif->hwaddr[4] = MBED_MAC_ADDR_4; - netif->hwaddr[5] = MBED_MAC_ADDR_5; -#else - mbed_mac_address((char *)netif->hwaddr); -#endif - netif->hwaddr_len = ETH_HWADDR_LEN; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* device capabilities */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET; -#ifdef LWIP_IGMP - netif->flags |= NETIF_FLAG_IGMP; -#endif -#if LWIP_IPV6_MLD - netif->flags |= NETIF_FLAG_MLD6; -#endif - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwiprza1"; -#endif /* LWIP_NETIF_HOSTNAME */ - - netif->name[0] = 'e'; - netif->name[1] = 'n'; - -#if LWIP_IPV4 - netif->output = rza1_etharp_output_ipv4; -#endif -#if LWIP_IPV6 - netif->output_ip6 = rza1_etharp_output_ipv6; -#endif - - netif->linkoutput = rza1_low_level_output; - - /* Initialize the hardware */ - ethcfg.int_priority = 6; - ethcfg.recv_cb = &rza1_recv_callback; - ethcfg.ether_mac = (char *)netif->hwaddr; - ethernetext_init(ðcfg); - - /* semaphore */ - sys_sem_new(&recv_ready_sem, 0); - - /* task */ - sys_thread_new("rza1_emac_rx_thread", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI); - sys_thread_new("rza1_emac_phy_thread", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI); - - return ERR_OK; -} - -void eth_arch_enable_interrupts(void) { - ethernetext_start_stop(1); -} - -void eth_arch_disable_interrupts(void) { - ethernetext_start_stop(0); -} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h similarity index 82% rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h index 1ad186c7a14..0e272a25fc4 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h @@ -23,4 +23,11 @@ #define MEM_SIZE (1600 * 16) +#define MEMP_NUM_TCP_SEG 32 +#define TCP_MSS 1460 +#define PBUF_POOL_SIZE 16 +#define TCP_SND_BUF (8 * TCP_MSS) +#define TCP_WND (TCP_MSS * 8) +#define PBUF_POOL_BUFSIZE 1600 + #endif diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c similarity index 86% rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c index 65515507a05..1d033e12da9 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c @@ -5,11 +5,73 @@ #include "mbed_interface.h" #include "ethernet_api.h" #include "ethernetext_api.h" +#include "platform/mbed_toolchain.h" #define RECV_TASK_PRI (osPriorityNormal) #define PHY_TASK_PRI (osPriorityNormal) #define PHY_TASK_WAIT (200) +WEAK int ethernetext_init(ethernet_cfg_t *p_ethcfg) +{ + return -1; +} + +WEAK void ethernetext_start_stop(int32_t mode) +{ +} + +WEAK int ethernetext_chk_link_mode(void) +{ + return NEGO_FAIL; +} + +WEAK void ethernetext_set_link_mode(int32_t link) +{ +} + +WEAK int ethernet_init(void) +{ + return -1; +} + +WEAK void ethernet_free(void) +{ +} + +WEAK int ethernet_write(const char *data, int size) +{ + return 0; +} + +WEAK int ethernet_send(void) +{ + return 0; +} + +WEAK int ethernet_receive(void) +{ + return 0; +} + +WEAK int ethernet_read(char *data, int size) +{ + return 0; +} + +WEAK void ethernet_address(char *mac) +{ +} + +WEAK int ethernet_link(void) +{ + return 0; +} + +WEAK void ethernet_set_link(int speed, int duplex) +{ +} + + /* memory */ static sys_sem_t recv_ready_sem; /* receive ready semaphore */ @@ -195,8 +257,8 @@ err_t eth_arch_enetif_init(struct netif *netif) sys_sem_new(&recv_ready_sem, 0); /* task */ - sys_thread_new("rza1_emac_rx_thread", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI); - sys_thread_new("rza1_emac_phy_thread", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI); + sys_thread_new("rza1_recv_task", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI); + sys_thread_new("rza1_phy_task", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI); return ERR_OK; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c new file mode 100644 index 00000000000..56f754a4f4c --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_conf.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32f4xx_hal.h" + +void _eth_config_mac(ETH_HandleTypeDef *heth) +{ + ETH_MACInitTypeDef macconf = + { + .Watchdog = ETH_WATCHDOG_ENABLE, + .Jabber = ETH_JABBER_ENABLE, + .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, + .CarrierSense = ETH_CARRIERSENCE_ENABLE, + .ReceiveOwn = ETH_RECEIVEOWN_ENABLE, + .LoopbackMode = ETH_LOOPBACKMODE_DISABLE, + .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE, + .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE, + .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE, + .BackOffLimit = ETH_BACKOFFLIMIT_10, + .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE, + .ReceiveAll = ETH_RECEIVEAll_DISABLE, + .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE, + .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL, + .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE, + .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL, + .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE, + .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter + .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT, + .HashTableHigh = 0x0U, + .HashTableLow = 0x0U, + .PauseTime = 0x0U, + .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE, + .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4, + .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, + .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, + .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, + .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, + .VLANTagIdentifier = 0x0U + }; + + if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } else { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + + (void) HAL_ETH_ConfigMAC(heth, &macconf); +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c new file mode 100644 index 00000000000..9baf012f2ac --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MTB_UBLOX_ODIN_W2/stm32f4_eth_init.c @@ -0,0 +1,159 @@ +/* Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include +#include "stm32f4xx_hal.h" +#include "mbed_toolchain.h" + +#define C029_OTP_START_ADDRESS (0x1FFF7800U) +#define C029_OTP_END_ADDRESS (C029_OTP_START_ADDRESS + (16*32)) +#define C029_MAC_ETHERNET_ID (3) + +typedef MBED_PACKED(struct) C029_OTP_Header { + uint8_t id; + uint8_t len; + uint8_t data[]; +} C029_OTP_Header; + +static int _macRetrieved = 0; +static char _macAddr[6] = { 0x02, 0x02, 0xF7, 0xF0, 0x00, 0x00 }; + +static C029_OTP_Header *increment(C029_OTP_Header *pTemp) +{ + uint8_t len = 0; + uint8_t id = 0; + uint8_t *p = (uint8_t*)pTemp; + + memcpy((void*)&id, (void*)pTemp, 1); + + if (id == 0xFF){ + p++; + } else { + p++; + memcpy((void*)&len, (void*)p++, 1); + p += len; + } + return (C029_OTP_Header*)p; +} + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStructure; + if (heth->Instance == ETH) { + + /* Enable GPIOs clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_PULLUP; + GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7; + GPIO_InitStructure.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pin = GPIO_PIN_1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PB13 */ + GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure PC1, PC4 and PC5 */ + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Enable the Ethernet global Interrupt */ + HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + + /* Enable ETHERNET clock */ + __HAL_RCC_ETH_CLK_ENABLE(); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if (heth->Instance == ETH) { + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); + + /* Disable the Ethernet global Interrupt */ + NVIC_DisableIRQ(ETH_IRQn); + } +} + +uint8_t mbed_otp_mac_address(char *mac) +{ + C029_OTP_Header *pFound = NULL; + C029_OTP_Header *pTemp = (C029_OTP_Header*)C029_OTP_START_ADDRESS; + C029_OTP_Header temp; + + if (_macRetrieved == 0) { + while ((pTemp >= (C029_OTP_Header*)C029_OTP_START_ADDRESS) && (pTemp < (C029_OTP_Header*)C029_OTP_END_ADDRESS)){ + memcpy((void*)&temp, (void*)pTemp, sizeof(temp)); + if (temp.id == C029_MAC_ETHERNET_ID){ + pFound = pTemp; + break; + } + pTemp = increment(pTemp); + } + if (pFound != NULL) { + memcpy(_macAddr, pFound->data, 6); + _macRetrieved = 1; + } + } + memcpy(mac, _macAddr, 6); + + return 1; +} \ No newline at end of file diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c index 7325703f5ec..23ffbc5317c 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c @@ -275,6 +275,37 @@ static const ip_addr_t *mbed_lwip_get_ipv6_addr(const struct netif *netif) } #endif +static bool mbed_lwip_is_local_addr(const ip_addr_t *ip_addr) +{ + struct netif *netif; + + for (netif = netif_list; netif != NULL; netif = netif->next) { + if (!netif_is_up(netif)) { + continue; + } +#if LWIP_IPV6 + if (IP_IS_V6(ip_addr)) { + for (int i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_cmp(netif_ip6_addr(netif, i), ip_2_ip6(ip_addr))) { + return true; + } + } + } +#endif + +#if LWIP_IPV4 + if (IP_IS_V4(ip_addr)) { + if (!ip4_addr_isany(netif_ip4_addr(netif)) && + ip4_addr_cmp(netif_ip4_addr(netif), ip_2_ip4(ip_addr))) { + return true; + } + } +#endif + } + return false; +} + const ip_addr_t *mbed_lwip_get_ip_addr(bool any_addr, const struct netif *netif) { const ip_addr_t *pref_ip_addr = 0; @@ -992,6 +1023,10 @@ static nsapi_error_t mbed_lwip_socket_bind(nsapi_stack_t *stack, nsapi_socket_t return NSAPI_ERROR_PARAMETER; } + if (!ip_addr_isany(&ip_addr) && !mbed_lwip_is_local_addr(&ip_addr)) { + return NSAPI_ERROR_PARAMETER; + } + err_t err = netconn_bind(s->conn, &ip_addr, port); return mbed_lwip_err_remap(err); } @@ -1000,6 +1035,10 @@ static nsapi_error_t mbed_lwip_socket_listen(nsapi_stack_t *stack, nsapi_socket_ { struct lwip_socket *s = (struct lwip_socket *)handle; + if (s->conn->pcb.tcp->local_port == 0) { + return NSAPI_ERROR_PARAMETER; + } + err_t err = netconn_listen_with_backlog(s->conn, backlog); return mbed_lwip_err_remap(err); } @@ -1028,6 +1067,10 @@ static nsapi_error_t mbed_lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_ return NSAPI_ERROR_NO_SOCKET; } + if (s->conn->pcb.tcp->state != LISTEN) { + return NSAPI_ERROR_PARAMETER; + } + err_t err = netconn_accept(s->conn, &ns->conn); if (err != ERR_OK) { mbed_lwip_arena_dealloc(ns); diff --git a/features/filesystem/FileSystem.cpp b/features/filesystem/FileSystem.cpp index b356b0a0378..99f98d2fe99 100644 --- a/features/filesystem/FileSystem.cpp +++ b/features/filesystem/FileSystem.cpp @@ -51,6 +51,11 @@ int FileSystem::mkdir(const char *path, mode_t mode) return -ENOSYS; } +int FileSystem::statvfs(const char *path, struct statvfs *buf) +{ + return -ENOSYS; +} + int FileSystem::file_sync(fs_file_t file) { return 0; diff --git a/features/filesystem/FileSystem.h b/features/filesystem/FileSystem.h index 06659f38308..9b95e35dd88 100644 --- a/features/filesystem/FileSystem.h +++ b/features/filesystem/FileSystem.h @@ -109,6 +109,14 @@ class FileSystem : public FileSystemLike { */ virtual int mkdir(const char *path, mode_t mode); + /** Store information about the mounted filesystem in a statvfs structure + * + * @param path The name of the file to find information about + * @param buf The stat buffer to write to + * @return 0 on success, negative error code on failure + */ + virtual int statvfs(const char *path, struct statvfs *buf); + protected: friend class File; friend class Dir; @@ -143,7 +151,7 @@ class FileSystem : public FileSystemLike { * * @param file File handle * @param buffer The buffer to write from - * @param size The number of bytes to write + * @param size The number of bytes to write * @return The number of bytes written, negative error on failure */ virtual ssize_t file_write(fs_file_t file, const void *buffer, size_t size) = 0; @@ -240,7 +248,7 @@ class FileSystem : public FileSystemLike { */ virtual void dir_rewind(fs_dir_t dir); - /** Get the sizeof the directory + /** Get the sizeof the directory * * @param dir Dir handle * @return Number of files in the directory diff --git a/features/filesystem/fat/FATFileSystem.cpp b/features/filesystem/fat/FATFileSystem.cpp index 152cc96b335..69fbc29c7d4 100644 --- a/features/filesystem/fat/FATFileSystem.cpp +++ b/features/filesystem/fat/FATFileSystem.cpp @@ -196,7 +196,9 @@ DRESULT disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count) { debug_if(FFS_DBG, "disk_read(sector %d, count %d) on pdrv [%d]\n", sector, count, pdrv); DWORD ssize = disk_get_sector_size(pdrv); - int err = _ffs[pdrv]->read(buff, sector*ssize, count*ssize); + bd_addr_t addr = (bd_addr_t)sector*ssize; + bd_size_t size = (bd_size_t)count*ssize; + int err = _ffs[pdrv]->read(buff, addr, size); return err ? RES_PARERR : RES_OK; } @@ -204,12 +206,14 @@ DRESULT disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count) { debug_if(FFS_DBG, "disk_write(sector %d, count %d) on pdrv [%d]\n", sector, count, pdrv); DWORD ssize = disk_get_sector_size(pdrv); - int err = _ffs[pdrv]->erase(sector*ssize, count*ssize); + bd_addr_t addr = (bd_addr_t)sector*ssize; + bd_size_t size = (bd_size_t)count*ssize; + int err = _ffs[pdrv]->erase(addr, size); if (err) { return RES_PARERR; } - err = _ffs[pdrv]->program(buff, sector*ssize, count*ssize); + err = _ffs[pdrv]->program(buff, addr, size); if (err) { return RES_PARERR; } @@ -250,7 +254,9 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) } else { DWORD *sectors = (DWORD*)buff; DWORD ssize = disk_get_sector_size(pdrv); - int err = _ffs[pdrv]->trim(sectors[0]*ssize, (sectors[1]-sectors[0]+1)*ssize); + bd_addr_t addr = (bd_addr_t)sectors[0]*ssize; + bd_size_t size = (bd_size_t)(sectors[1]-sectors[0]+1)*ssize; + int err = _ffs[pdrv]->trim(addr, size); return err ? RES_PARERR : RES_OK; } } @@ -275,12 +281,14 @@ FATFileSystem::~FATFileSystem() unmount(); } -int FATFileSystem::mount(BlockDevice *bd) { +int FATFileSystem::mount(BlockDevice *bd) +{ // requires duplicate definition to allow virtual overload to work return mount(bd, true); } -int FATFileSystem::mount(BlockDevice *bd, bool mount) { +int FATFileSystem::mount(BlockDevice *bd, bool mount) +{ lock(); if (_id != -1) { unlock(); @@ -322,7 +330,8 @@ int FATFileSystem::unmount() /* See http://elm-chan.org/fsw/ff/en/mkfs.html for details of f_mkfs() and * associated arguments. */ -int FATFileSystem::format(BlockDevice *bd, bd_size_t cluster_size) { +int FATFileSystem::format(BlockDevice *bd, bd_size_t cluster_size) +{ FATFileSystem fs; int err = fs.mount(bd, false); if (err) { @@ -345,7 +354,8 @@ int FATFileSystem::format(BlockDevice *bd, bd_size_t cluster_size) { return 0; } -int FATFileSystem::reformat(BlockDevice *bd, int allocation_unit) { +int FATFileSystem::reformat(BlockDevice *bd, int allocation_unit) +{ lock(); if (_id != -1) { if (!bd) { @@ -375,7 +385,8 @@ int FATFileSystem::reformat(BlockDevice *bd, int allocation_unit) { return err; } -int FATFileSystem::remove(const char *path) { +int FATFileSystem::remove(const char *path) +{ Deferred fpath = fat_path_prefix(_id, path); lock(); @@ -388,7 +399,8 @@ int FATFileSystem::remove(const char *path) { return fat_error_remap(res); } -int FATFileSystem::rename(const char *oldpath, const char *newpath) { +int FATFileSystem::rename(const char *oldpath, const char *newpath) +{ Deferred oldfpath = fat_path_prefix(_id, oldpath); Deferred newfpath = fat_path_prefix(_id, newpath); @@ -402,7 +414,8 @@ int FATFileSystem::rename(const char *oldpath, const char *newpath) { return fat_error_remap(res); } -int FATFileSystem::mkdir(const char *path, mode_t mode) { +int FATFileSystem::mkdir(const char *path, mode_t mode) +{ Deferred fpath = fat_path_prefix(_id, path); lock(); @@ -415,7 +428,8 @@ int FATFileSystem::mkdir(const char *path, mode_t mode) { return fat_error_remap(res); } -int FATFileSystem::stat(const char *path, struct stat *st) { +int FATFileSystem::stat(const char *path, struct stat *st) +{ Deferred fpath = fat_path_prefix(_id, path); lock(); @@ -442,17 +456,49 @@ int FATFileSystem::stat(const char *path, struct stat *st) { return 0; } -void FATFileSystem::lock() { +int FATFileSystem::statvfs(const char *path, struct statvfs *buf) +{ + + memset(buf, 0, sizeof(struct statvfs)); + FATFS *fs; + DWORD fre_clust; + + lock(); + FRESULT res = f_getfree(_fsid, &fre_clust, &fs); + if (res != FR_OK) { + unlock(); + return fat_error_remap(res); + } + + buf->f_bsize = fs->ssize; + buf->f_frsize = fs->ssize; + buf->f_blocks = (fs->n_fatent - 2) * fs->csize; + buf->f_bfree = fre_clust * fs->csize; + buf->f_bavail = buf->f_bfree; +#if FF_USE_LFN + buf->f_namemax = FF_LFN_BUF; +#else + buf->f_namemax = FF_SFN_BUF; +#endif + + unlock(); + return 0; +} + +void FATFileSystem::lock() +{ _ffs_mutex->lock(); } -void FATFileSystem::unlock() { +void FATFileSystem::unlock() +{ _ffs_mutex->unlock(); } ////// File operations ////// -int FATFileSystem::file_open(fs_file_t *file, const char *path, int flags) { +int FATFileSystem::file_open(fs_file_t *file, const char *path, int flags) +{ debug_if(FFS_DBG, "open(%s) on filesystem [%s], drv [%s]\n", path, getName(), _id); FIL *fh = new FIL; @@ -496,7 +542,8 @@ int FATFileSystem::file_open(fs_file_t *file, const char *path, int flags) { return 0; } -int FATFileSystem::file_close(fs_file_t file) { +int FATFileSystem::file_close(fs_file_t file) +{ FIL *fh = static_cast(file); lock(); @@ -507,7 +554,8 @@ int FATFileSystem::file_close(fs_file_t file) { return fat_error_remap(res); } -ssize_t FATFileSystem::file_read(fs_file_t file, void *buffer, size_t len) { +ssize_t FATFileSystem::file_read(fs_file_t file, void *buffer, size_t len) +{ FIL *fh = static_cast(file); lock(); @@ -523,7 +571,8 @@ ssize_t FATFileSystem::file_read(fs_file_t file, void *buffer, size_t len) { } } -ssize_t FATFileSystem::file_write(fs_file_t file, const void *buffer, size_t len) { +ssize_t FATFileSystem::file_write(fs_file_t file, const void *buffer, size_t len) +{ FIL *fh = static_cast(file); lock(); @@ -539,7 +588,8 @@ ssize_t FATFileSystem::file_write(fs_file_t file, const void *buffer, size_t len } } -int FATFileSystem::file_sync(fs_file_t file) { +int FATFileSystem::file_sync(fs_file_t file) +{ FIL *fh = static_cast(file); lock(); @@ -552,7 +602,8 @@ int FATFileSystem::file_sync(fs_file_t file) { return fat_error_remap(res); } -off_t FATFileSystem::file_seek(fs_file_t file, off_t offset, int whence) { +off_t FATFileSystem::file_seek(fs_file_t file, off_t offset, int whence) +{ FIL *fh = static_cast(file); lock(); @@ -574,7 +625,8 @@ off_t FATFileSystem::file_seek(fs_file_t file, off_t offset, int whence) { } } -off_t FATFileSystem::file_tell(fs_file_t file) { +off_t FATFileSystem::file_tell(fs_file_t file) +{ FIL *fh = static_cast(file); lock(); @@ -584,7 +636,8 @@ off_t FATFileSystem::file_tell(fs_file_t file) { return res; } -off_t FATFileSystem::file_size(fs_file_t file) { +off_t FATFileSystem::file_size(fs_file_t file) +{ FIL *fh = static_cast(file); lock(); @@ -596,7 +649,8 @@ off_t FATFileSystem::file_size(fs_file_t file) { ////// Dir operations ////// -int FATFileSystem::dir_open(fs_dir_t *dir, const char *path) { +int FATFileSystem::dir_open(fs_dir_t *dir, const char *path) +{ FATFS_DIR *dh = new FATFS_DIR; Deferred fpath = fat_path_prefix(_id, path); @@ -614,7 +668,8 @@ int FATFileSystem::dir_open(fs_dir_t *dir, const char *path) { return 0; } -int FATFileSystem::dir_close(fs_dir_t dir) { +int FATFileSystem::dir_close(fs_dir_t dir) +{ FATFS_DIR *dh = static_cast(dir); lock(); @@ -625,7 +680,8 @@ int FATFileSystem::dir_close(fs_dir_t dir) { return fat_error_remap(res); } -ssize_t FATFileSystem::dir_read(fs_dir_t dir, struct dirent *ent) { +ssize_t FATFileSystem::dir_read(fs_dir_t dir, struct dirent *ent) +{ FATFS_DIR *dh = static_cast(dir); FILINFO finfo; @@ -653,7 +709,8 @@ ssize_t FATFileSystem::dir_read(fs_dir_t dir, struct dirent *ent) { return 1; } -void FATFileSystem::dir_seek(fs_dir_t dir, off_t offset) { +void FATFileSystem::dir_seek(fs_dir_t dir, off_t offset) +{ FATFS_DIR *dh = static_cast(dir); lock(); @@ -675,7 +732,8 @@ void FATFileSystem::dir_seek(fs_dir_t dir, off_t offset) { unlock(); } -off_t FATFileSystem::dir_tell(fs_dir_t dir) { +off_t FATFileSystem::dir_tell(fs_dir_t dir) +{ FATFS_DIR *dh = static_cast(dir); lock(); @@ -685,7 +743,8 @@ off_t FATFileSystem::dir_tell(fs_dir_t dir) { return offset; } -void FATFileSystem::dir_rewind(fs_dir_t dir) { +void FATFileSystem::dir_rewind(fs_dir_t dir) +{ FATFS_DIR *dh = static_cast(dir); lock(); diff --git a/features/filesystem/fat/FATFileSystem.h b/features/filesystem/fat/FATFileSystem.h index a1242321007..29afb9109a4 100644 --- a/features/filesystem/fat/FATFileSystem.h +++ b/features/filesystem/fat/FATFileSystem.h @@ -43,7 +43,7 @@ class FATFileSystem : public FileSystem { */ FATFileSystem(const char *name = NULL, BlockDevice *bd = NULL); virtual ~FATFileSystem(); - + /** Formats a logical drive, FDISK partitioning rule. * * The block device to format should be mounted when this function is called. @@ -57,7 +57,7 @@ class FATFileSystem : public FileSystem { * cluster_size must be a multiple of the underlying device's allocation unit * and is currently limited to a max of 32,768 bytes. If zero, a cluster size * will be determined from the device's allocation unit. Defaults to zero. - * + * * @return 0 on success, negative error code on failure */ static int format(BlockDevice *bd, bd_size_t cluster_size = 0); @@ -139,6 +139,14 @@ class FATFileSystem : public FileSystem { */ virtual int mkdir(const char *path, mode_t mode); + /** Store information about the mounted filesystem in a statvfs structure + * + * @param path The name of the file to find information about + * @param buf The stat buffer to write to + * @return 0 on success, negative error code on failure + */ + virtual int statvfs(const char *path, struct statvfs *buf); + protected: /** Open a file on the filesystem * @@ -170,7 +178,7 @@ class FATFileSystem : public FileSystem { * * @param file File handle * @param buffer The buffer to write from - * @param len The number of bytes to write + * @param len The number of bytes to write * @return The number of bytes written, negative error on failure */ virtual ssize_t file_write(fs_file_t file, const void *buffer, size_t len); @@ -251,7 +259,7 @@ class FATFileSystem : public FileSystem { * @param dir Dir handle */ virtual void dir_rewind(fs_dir_t dir); - + private: FATFS _fs; // Work area (file system object) for logical drive char _fsid[sizeof("0:")]; diff --git a/features/filesystem/littlefs/LittleFileSystem.cpp b/features/filesystem/littlefs/LittleFileSystem.cpp index 56d799b35be..9278ca4f09c 100644 --- a/features/filesystem/littlefs/LittleFileSystem.cpp +++ b/features/filesystem/littlefs/LittleFileSystem.cpp @@ -85,19 +85,19 @@ static int lfs_totype(int type) static int lfs_bd_read(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, void *buffer, lfs_size_t size) { BlockDevice *bd = (BlockDevice *)c->context; - return bd->read(buffer, block*c->block_size + off, size); + return bd->read(buffer, (bd_addr_t)block*c->block_size + off, size); } static int lfs_bd_prog(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, const void *buffer, lfs_size_t size) { BlockDevice *bd = (BlockDevice *)c->context; - return bd->program(buffer, block*c->block_size + off, size); + return bd->program(buffer, (bd_addr_t)block*c->block_size + off, size); } static int lfs_bd_erase(const struct lfs_config *c, lfs_block_t block) { BlockDevice *bd = (BlockDevice *)c->context; - return bd->erase(block*c->block_size, c->block_size); + return bd->erase((bd_addr_t)block*c->block_size, c->block_size); } static int lfs_bd_sync(const struct lfs_config *c) @@ -336,6 +336,34 @@ int LittleFileSystem::stat(const char *name, struct stat *st) return lfs_toerror(err); } +static int lfs_statvfs_count(void *p, lfs_block_t b) +{ + *(lfs_size_t *)p += 1; + return 0; +} + +int LittleFileSystem::statvfs(const char *name, struct statvfs *st) +{ + memset(st, 0, sizeof(struct statvfs)); + + lfs_size_t in_use = 0; + _mutex.lock(); + LFS_INFO("statvfs(\"%s\", %p)", name, st); + int err = lfs_traverse(&_lfs, lfs_statvfs_count, &in_use); + LFS_INFO("statvfs -> %d", lfs_toerror(err)); + _mutex.unlock(); + if (err) { + return err; + } + + st->f_bsize = _config.block_size; + st->f_frsize = _config.block_size; + st->f_blocks = _config.block_count; + st->f_bfree = _config.block_count - in_use; + st->f_bavail = _config.block_count - in_use; + st->f_namemax = LFS_NAME_MAX; + return 0; +} ////// File operations ////// int LittleFileSystem::file_open(fs_file_t *file, const char *path, int flags) diff --git a/features/filesystem/littlefs/LittleFileSystem.h b/features/filesystem/littlefs/LittleFileSystem.h index 0829eb2faa4..6f15a423ba0 100644 --- a/features/filesystem/littlefs/LittleFileSystem.h +++ b/features/filesystem/littlefs/LittleFileSystem.h @@ -143,6 +143,14 @@ class LittleFileSystem : public mbed::FileSystem { */ virtual int mkdir(const char *path, mode_t mode); + /** Store information about the mounted filesystem in a statvfs structure + * + * @param path The name of the file to find information about + * @param buf The stat buffer to write to + * @return 0 on success, negative error code on failure + */ + virtual int statvfs(const char *path, struct statvfs *buf); + protected: /** Open a file on the filesystem * diff --git a/features/filesystem/littlefs/TESTS_COMMON/atomic_usage.cpp b/features/filesystem/littlefs/TESTS/COMMON/atomic_usage.cpp similarity index 100% rename from features/filesystem/littlefs/TESTS_COMMON/atomic_usage.cpp rename to features/filesystem/littlefs/TESTS/COMMON/atomic_usage.cpp diff --git a/features/filesystem/littlefs/TESTS_COMMON/atomic_usage.h b/features/filesystem/littlefs/TESTS/COMMON/atomic_usage.h similarity index 100% rename from features/filesystem/littlefs/TESTS_COMMON/atomic_usage.h rename to features/filesystem/littlefs/TESTS/COMMON/atomic_usage.h diff --git a/features/filesystem/littlefs/littlefs/.travis.yml b/features/filesystem/littlefs/littlefs/.travis.yml index d673c159ab8..c17af8b17bb 100644 --- a/features/filesystem/littlefs/littlefs/.travis.yml +++ b/features/filesystem/littlefs/littlefs/.travis.yml @@ -12,10 +12,9 @@ script: - make test QUIET=1 # run tests with a few different configurations - - CFLAGS="-DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make test QUIET=1 - - CFLAGS="-DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make test QUIET=1 - - CFLAGS="-DLFS_BLOCK_COUNT=1023" make test QUIET=1 - - CFLAGS="-DLFS_LOOKAHEAD=2048" make test QUIET=1 + - CFLAGS="-DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make test QUIET=1 + - CFLAGS="-DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make test QUIET=1 + - CFLAGS="-DLFS_BLOCK_COUNT=1023 -DLFS_LOOKAHEAD=2048" make test QUIET=1 # self-host with littlefs-fuse for fuzz test - make -C littlefs-fuse diff --git a/features/filesystem/littlefs/littlefs/lfs.c b/features/filesystem/littlefs/littlefs/lfs.c index 04870925cde..9678181fd34 100644 --- a/features/filesystem/littlefs/littlefs/lfs.c +++ b/features/filesystem/littlefs/littlefs/lfs.c @@ -1261,6 +1261,9 @@ int lfs_file_open(lfs_t *lfs, lfs_file_t *file, file->pos = 0; if (flags & LFS_O_TRUNC) { + if (file->size != 0) { + file->flags |= LFS_F_DIRTY; + } file->head = 0xffffffff; file->size = 0; } @@ -1635,13 +1638,13 @@ lfs_soff_t lfs_file_seek(lfs_t *lfs, lfs_file_t *file, if (whence == LFS_SEEK_SET) { file->pos = off; } else if (whence == LFS_SEEK_CUR) { - if ((lfs_off_t)-off > file->pos) { + if (off < 0 && (lfs_off_t)-off > file->pos) { return LFS_ERR_INVAL; } file->pos = file->pos + off; } else if (whence == LFS_SEEK_END) { - if ((lfs_off_t)-off > file->size) { + if (off < 0 && (lfs_off_t)-off > file->size) { return LFS_ERR_INVAL; } @@ -2039,9 +2042,9 @@ int lfs_mount(lfs_t *lfs, const struct lfs_config *cfg) { return err; } - // setup free lookahead - lfs->free.begin = -lfs->cfg->lookahead; - lfs->free.off = lfs->cfg->lookahead; + // setup free lookahead, rewind so first allocation triggers a scan + lfs->free.begin = -lfs_min(lfs->cfg->lookahead, lfs->cfg->block_count); + lfs->free.off = -lfs->free.begin; lfs->free.end = lfs->free.begin + lfs->free.off + lfs->cfg->block_count; // load superblock diff --git a/features/filesystem/littlefs/littlefs/tests/test_files.sh b/features/filesystem/littlefs/littlefs/tests/test_files.sh index 6086107c89b..444346371b5 100755 --- a/features/filesystem/littlefs/littlefs/tests/test_files.sh +++ b/features/filesystem/littlefs/littlefs/tests/test_files.sh @@ -34,7 +34,8 @@ tests/test.py << TEST lfs_size_t chunk = 31; srand(0); lfs_mount(&lfs, &cfg) => 0; - lfs_file_open(&lfs, &file[0], "$2", LFS_O_WRONLY | LFS_O_CREAT) => 0; + lfs_file_open(&lfs, &file[0], "$2", + ${3:-LFS_O_WRONLY | LFS_O_CREAT | LFS_O_TRUNC}) => 0; for (lfs_size_t i = 0; i < size; i += chunk) { chunk = (chunk < size - i) ? chunk : size - i; for (lfs_size_t b = 0; b < chunk; b++) { @@ -53,7 +54,10 @@ tests/test.py << TEST lfs_size_t chunk = 29; srand(0); lfs_mount(&lfs, &cfg) => 0; - lfs_file_open(&lfs, &file[0], "$2", LFS_O_RDONLY) => 0; + lfs_stat(&lfs, "$2", &info) => 0; + info.type => LFS_TYPE_REG; + info.size => size; + lfs_file_open(&lfs, &file[0], "$2", ${3:-LFS_O_RDONLY}) => 0; for (lfs_size_t i = 0; i < size; i += chunk) { chunk = (chunk < size - i) ? chunk : size - i; lfs_file_read(&lfs, &file[0], buffer, chunk) => chunk; @@ -78,10 +82,27 @@ echo "--- Large file test ---" w_test $LARGESIZE largeavacado r_test $LARGESIZE largeavacado +echo "--- Zero file test ---" +w_test 0 noavacado +r_test 0 noavacado + +echo "--- Truncate small test ---" +w_test $SMALLSIZE mediumavacado +r_test $SMALLSIZE mediumavacado +w_test $MEDIUMSIZE mediumavacado +r_test $MEDIUMSIZE mediumavacado + +echo "--- Truncate zero test ---" +w_test $SMALLSIZE noavacado +r_test $SMALLSIZE noavacado +w_test 0 noavacado +r_test 0 noavacado + echo "--- Non-overlap check ---" r_test $SMALLSIZE smallavacado r_test $MEDIUMSIZE mediumavacado r_test $LARGESIZE largeavacado +r_test 0 noavacado echo "--- Dir check ---" tests/test.py << TEST @@ -105,6 +126,10 @@ tests/test.py << TEST strcmp(info.name, "largeavacado") => 0; info.type => LFS_TYPE_REG; info.size => $LARGESIZE; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, "noavacado") => 0; + info.type => LFS_TYPE_REG; + info.size => 0; lfs_dir_read(&lfs, &dir[0], &info) => 0; lfs_dir_close(&lfs, &dir[0]) => 0; lfs_unmount(&lfs) => 0; diff --git a/features/filesystem/littlefs/littlefs/tests/test_seek.sh b/features/filesystem/littlefs/littlefs/tests/test_seek.sh index 6600cb2f5c5..3b46892b6ea 100755 --- a/features/filesystem/littlefs/littlefs/tests/test_seek.sh +++ b/features/filesystem/littlefs/littlefs/tests/test_seek.sh @@ -133,6 +133,14 @@ tests/test.py << TEST lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], 0, LFS_SEEK_CUR) => size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + + lfs_file_seek(&lfs, &file[0], size, LFS_SEEK_CUR) => 3*size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], pos, LFS_SEEK_SET) => pos; lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; @@ -174,6 +182,14 @@ tests/test.py << TEST lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], 0, LFS_SEEK_CUR) => size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + + lfs_file_seek(&lfs, &file[0], size, LFS_SEEK_CUR) => 3*size; + lfs_file_read(&lfs, &file[0], buffer, size) => size; + memcmp(buffer, "kittycatcat", size) => 0; + lfs_file_seek(&lfs, &file[0], pos, LFS_SEEK_SET) => pos; lfs_file_read(&lfs, &file[0], buffer, size) => size; memcmp(buffer, "kittycatcat", size) => 0; diff --git a/features/frameworks/unity/unity/unity.h b/features/frameworks/unity/unity/unity.h index 31f4af53aa9..45d6a065f92 100644 --- a/features/frameworks/unity/unity/unity.h +++ b/features/frameworks/unity/unity/unity.h @@ -20,6 +20,8 @@ extern "C" #define UNITY_SUPPORT_64 // support double precision floating point #define UNITY_INCLUDE_DOUBLE +// support float values in error print +#define UNITY_FLOAT_VERBOSE #include "unity_internals.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h index 22396dfea2e..1043cab9fd2 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/mbedtls_device.h @@ -23,9 +23,5 @@ #define MBEDTLS_SHA512_ALT #define MBEDTLS_AES_ALT -#define MBEDTLS_AES_SETKEY_ENC_ALT -#define MBEDTLS_AES_SETKEY_DEC_ALT -#define MBEDTLS_AES_ENCRYPT_ALT -#define MBEDTLS_AES_DECRYPT_ALT #endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 0aeeb0286be..69a6f790af3 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -21,298 +21,229 @@ * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) #include - -#include "mbedtls/aes.h" +#include #include "M480.h" #include "mbed_toolchain.h" #include "mbed_assert.h" - - - -#define mbedtls_trace(...) //printf(__VA_ARGS__) +#include "mbed_error.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } - -static uint32_t au32MyAESIV[4] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - -extern volatile int g_AES_done; - -// Must be a multiple of 16 bytes block size +/* AES DMA compatible backup buffer if user buffer doesn't meet requirements + * + * AES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * AES DMA buffer size MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + * + */ #define MAX_DMA_CHAIN_SIZE (16*6) MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; -static void dumpHex(const unsigned char au8Data[], int len) -{ - int j; - for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]); - mbedtls_trace("\r\n"); -} - -static void swapInitVector(unsigned char iv[16]) -{ - unsigned int* piv; - int i; - // iv SWAP - piv = (unsigned int*)iv; - for( i=0; i< 4; i++) - { - *piv = (((*piv) & 0x000000FF) << 24) | - (((*piv) & 0x0000FF00) << 8) | - (((*piv) & 0x00FF0000) >> 8) | - (((*piv) & 0xFF000000) >> 24); - piv++; - } -} - -/* IRQHandler: To share CRYPTO_IRQHandler() with TRNG & other crypto IPs - For ex: - volatile void CRYPTO_IRQHandler() - { - ... - if (AES_GET_INT_FLAG()) { - g_AES_done = 1; - AES_CLR_INT_FLAG(); - } - ... - } -*/ - - -/* AES available channel 0~3 */ -static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00}; // 0: idle, 1: busy -static int channel_alloc() -{ - int i; - for(i=0; i< (int)sizeof(channel_flag); i++) - { - if( channel_flag[i] == 0x00 ) - { - channel_flag[i] = 0x01; - return i; - } - } - return(-1); -} - -static void channel_free(int i) -{ - if( i >=0 && i < (int)sizeof(channel_flag) ) - channel_flag[i] = 0x00; -} - - void mbedtls_aes_init( mbedtls_aes_context *ctx ) { - int i =-1; - - - mbedtls_trace("=== %s \r\n", __FUNCTION__); memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - - ctx->swapType = AES_IN_OUT_SWAP; - while( (i = channel_alloc()) < 0 ) - { - mbed_assert_internal("No available AES channel", __FILE__, __LINE__); - } - ctx->channel = i; - ctx->iv = au32MyAESIV; - - /* Unlock protected registers */ - SYS_UnlockReg(); - CLK_EnableModuleClock(CRPT_MODULE); - /* Lock protected registers */ - SYS_LockReg(); - - NVIC_EnableIRQ(CRPT_IRQn); - AES_ENABLE_INT(); - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel); - if( ctx == NULL ) return; - - channel_free(ctx->channel); + mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } /* * AES key schedule (encryption) */ -#if defined(MBEDTLS_AES_SETKEY_ENC_ALT) int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { unsigned int i; - - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex(key,keybits/8); - - switch( keybits ) - { - case 128: - ctx->keySize = AES_KEY_SIZE_128; - break; - case 192: - ctx->keySize = AES_KEY_SIZE_192; - break; - case 256: - ctx->keySize = AES_KEY_SIZE_256; - break; - default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); - } - + switch( keybits ) { + case 128: + ctx->keySize = AES_KEY_SIZE_128; + break; + case 192: + ctx->keySize = AES_KEY_SIZE_192; + break; + case 256: + ctx->keySize = AES_KEY_SIZE_256; + break; + default : + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } - // key swap - for( i = 0; i < ( keybits >> 5 ); i++ ) - { - ctx->buf[i] = (*(key+i*4) << 24) | - (*(key+1+i*4) << 16) | - (*(key+2+i*4) << 8) | - (*(key+3+i*4) ); - } - AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); - + /* Fetch key byte data in big-endian */ + for( i = 0; i < ( keybits >> 5 ); i++ ) { + ctx->keys[i] = nu_get32_be(key + i * 4); + } return( 0 ); } -#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */ /* * AES key schedule (decryption) */ -#if defined(MBEDTLS_AES_SETKEY_DEC_ALT) int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { int ret; - - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex((uint8_t *)key,keybits/8); - + /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) - goto exit; + goto exit; exit: - return( ret ); } -#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */ - +/* Do AES encrypt/decrypt with H/W accelerator + * + * NOTE: As input/output buffer doesn't follow constraint of DMA buffer, static allocated + * DMA compatible buffer is used for DMA instead and this needs extra copy. + * + * NOTE: dataSize requires to be: + * 1) Multiple of block size 16 + * 2) <= MAX_DMA_CHAIN_SIZE + */ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16], int dataSize) + const unsigned char *input, + unsigned char *output, size_t dataSize) { - unsigned char* pIn; - unsigned char* pOut; - -// mbedtls_trace("=== %s \r\n", __FUNCTION__); - dumpHex(input,16); - - AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); - AES_SetInitVect(ctx->channel, ctx->iv); - if( ((uint32_t)input) & 0x03 ) - { - memcpy(au8InputData, input, dataSize); - pIn = au8InputData; - }else{ - pIn = (unsigned char*)input; + const unsigned char* pIn; + unsigned char* pOut; + + MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); + + /* AES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 16-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region + */ + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE, 16)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE, 16))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - if( (((uint32_t)output) & 0x03) || (dataSize%4)) // HW CFB output byte count must be multiple of word - { - pOut = au8OutputData; - } else { - pOut = output; - } - - AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); - - g_AES_done = 0; - AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT); - while (!g_AES_done); - if( pOut != output ) memcpy(output, au8OutputData, dataSize); - dumpHex(output,16); + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of AES H/W */ + while (! crypto_aes_acquire()); + + /* Init crypto module */ + crypto_init(); + /* Enable AES interrupt */ + AES_ENABLE_INT(); + + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + + /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ + AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); + AES_SetInitVect(0, ctx->iv); + AES_SetKey(0, ctx->keys, ctx->keySize); + + /* AES DMA buffer requirements same as above */ + if (! crypto_dma_buff_compat(input, dataSize, 16)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } else { + pIn = input; + } + /* AES DMA buffer requirements same as above */ + if (! crypto_dma_buff_compat(output, dataSize, 16)) { + pOut = au8OutputData; + } else { + pOut = output; + } + /* Even though AES H/W has limited support for overlapped DMA input/output buffers, + * we still seek to one backup buffer to make them non-overlapped for simplicity. */ + if (crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } + MBED_ASSERT(! crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)); + + AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); + + crypto_aes_prestart(); + AES_Start(0, CRYPTO_DMA_ONE_SHOT); + crypto_aes_wait(); + + if( pOut != output ) { + memcpy(output, au8OutputData, dataSize); + } + + /* Save IV for next block */ + ctx->iv[0] = CRPT->AES_FDBCK[0]; + ctx->iv[1] = CRPT->AES_FDBCK[1]; + ctx->iv[2] = CRPT->AES_FDBCK[2]; + ctx->iv[3] = CRPT->AES_FDBCK[3]; + + /* Disable AES interrupt */ + AES_DISABLE_INT(); + /* Uninit crypto module */ + crypto_uninit(); + + /* Release ownership of AES H/W */ + crypto_aes_release(); } /* * AES-ECB block encryption */ -#if defined(MBEDTLS_AES_ENCRYPT_ALT) void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, 16); - + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_ENCRYPT_ALT */ /* * AES-ECB block decryption */ -#if defined(MBEDTLS_AES_DECRYPT_ALT) void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, 16); - - + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_DECRYPT_ALT */ /* * AES-ECB block encryption/decryption */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) + int mode, + const unsigned char input[16], + unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - ctx->opMode = AES_MODE_ECB; + ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) mbedtls_aes_encrypt( ctx, input, output ); else mbedtls_aes_decrypt( ctx, input, output ); - + return( 0 ); } @@ -322,108 +253,135 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * AES-CBC buffer encryption/decryption */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t len, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t len, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - unsigned char temp[16]; int length = len; - int blockChainLen; - mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length); + int blockChainLen; + if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else { - blockChainLen = length; - } - - while( length > 0 ) - { - ctx->opMode = AES_MODE_CBC; - swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; - - if( mode == MBEDTLS_AES_ENCRYPT ) - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, output+blockChainLen-16, 16 ); - }else{ - memcpy( temp, input+blockChainLen-16, 16 ); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, temp, 16 ); - } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - + + ctx->opMode = AES_MODE_CBC; + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + } + else { + ctx->encDec = 0; } + + while( length > 0 ) { + blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; + __nvt_aes_crypt(ctx, input, output, blockChainLen); + + length -= blockChainLen; + input += blockChainLen; + output += blockChainLen; + } + + /* Save IV for next block cipher */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + return( 0 ); } #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) -/* - * AES-CFB128 buffer encryption/decryption - */ -/* Support partial block encryption/decryption */ -static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { int c; size_t n = *iv_off; - unsigned char iv_tmp[16]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); - if( mode == MBEDTLS_AES_DECRYPT ) - { - while( length-- ) - { - if( n == 0) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); - iv[n] = (unsigned char) c; + + /* First incomplete block */ + if (n % 16) { + while (n && length) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } n = ( n + 1 ) & 0x0F; + length --; } } - else - { - while( length-- ) - { - if( n == 0 ) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + /* Middle complete block(s) */ + size_t block_chain_len = length - (length % 16); + + if (block_chain_len) { + ctx->opMode = AES_MODE_CFB; + if (mode == MBEDTLS_AES_DECRYPT) { + ctx->encDec = 0; + } + else { + ctx->encDec = 1; + } + + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + while (block_chain_len) { + size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; + + __nvt_aes_crypt(ctx, input, output, block_chain_len2); + + input += block_chain_len2; + output += block_chain_len2; + length -= block_chain_len2; + + block_chain_len -= block_chain_len2; + } + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + /* Fetch IV byte data in big-endian */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + } + + /* Last incomplete block */ + if (length) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + while (length --) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } + n = ( n + 1 ) & 0x0F; } } @@ -433,96 +391,21 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, return( 0 ); } -int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t len, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) -{ - size_t n = *iv_off; - unsigned char temp[16]; - int length=len; - int blockChainLen; - int remLen=0; - int ivLen; - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - // proceed: start with partial block by ECB mode first - if( n !=0 ) { - __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output); - input += (16 - n); - output += (16 - n); - length -= (16 - n); - } - - // For address or byte count non-word alignment, go through reserved DMA buffer. - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) // Must reserved DMA buffer for each block - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else if(length%4) { // Need reserved DMA buffer once for last chain - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); - } else { // Not need reserved DMA buffer - blockChainLen = length; - } - - // proceed: start with block alignment - while( length > 0 ) - { - - ctx->opMode = AES_MODE_CFB; - - swapInitVector(iv); // iv SWAP - - ctx->iv = (uint32_t *)iv; - remLen = blockChainLen%16; - ivLen = (( remLen > 0) ? remLen: 16 ); - - if( mode == MBEDTLS_AES_DECRYPT ) - { - memcpy(temp, input+blockChainLen - ivLen, ivLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy(iv,temp, ivLen); - } - else - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16); - memcpy(iv,output+blockChainLen-ivLen,ivLen); - } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } - - *iv_off = remLen; - - return( 0 ); -} - /* * AES-CFB8 buffer encryption/decryption */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { unsigned char c; unsigned char ov[17]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); - while( length-- ) - { + while( length-- ) { memcpy( ov, iv, 16 ); mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); @@ -546,19 +429,17 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * AES-CTR buffer encryption/decryption */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ) + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) { int c, i; size_t n = *nc_off; - mbedtls_trace("=== %s \r\n", __FUNCTION__); - while( length-- ) - { + while( length-- ) { if( n == 0 ) { mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h index f0fec3122a9..23625b5b67e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.h @@ -23,13 +23,8 @@ #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" -#if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation // @@ -39,29 +34,13 @@ extern "C" { /** * \brief AES context structure - * - * \note buf is able to hold 32 extra bytes, which can be used: - * - for alignment purposes if VIA padlock is used, and/or - * - to simplify key expansion in the 256-bit case by - * generating an extra round key */ -typedef struct -{ - uint32_t keySize; - uint32_t encDec; - uint32_t opMode; - uint32_t channel; - uint32_t swapType; - uint32_t *iv; - unsigned char prv_iv[16]; -#if 1 - uint32_t buf[8]; -/* For comparsion with software AES for correctness */ -#else - uint32_t buf[68]; /*!< unaligned data */ - int nr; /*!< number of rounds */ - uint32_t *rk; /*!< AES round keys */ -#endif +typedef struct { + uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ + uint32_t iv[4]; /* IV for next block cipher */ + uint32_t keys[8]; /* Cipher key */ } mbedtls_aes_context; @@ -89,7 +68,7 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ); * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -101,7 +80,7 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -114,9 +93,9 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ); + int mode, + const unsigned char input[16], + unsigned char output[16] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -142,11 +121,11 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) @@ -176,12 +155,12 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** * \brief AES-CFB8 buffer encryption/decryption. @@ -208,11 +187,11 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /*MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) @@ -239,12 +218,12 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ); + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CTR */ /** @@ -279,6 +258,5 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, #endif /* MBEDTLS_AES_ALT */ -#endif /* MBEDTLS_AES_C */ #endif /* aes_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c deleted file mode 100644 index 7f6646f40b1..00000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.c +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "cmsis.h" -#include "mbed_assert.h" -#include "nu_modutil.h" -#include "nu_bitutil.h" -#include "crypto-misc.h" - -static int crypto_inited = 0; -static int crypto_sha_avail = 1; - -void crypto_init(void) -{ - if (crypto_inited) { - return; - } - crypto_inited = 1; - - CLK_EnableModuleClock(CRPT_MODULE); -} - -/* Implementation that should never be optimized out by the compiler */ -void crypto_zeroize(void *v, size_t n) -{ - volatile unsigned char *p = (unsigned char*) v; - while (n--) { - *p++ = 0; - } -} - -int crypto_sha_acquire(void) -{ - if (crypto_sha_avail) { - crypto_sha_avail = 0; - return 1; - } - else { - return 0; - } - -} - -void crypto_sha_release(void) -{ - if (! crypto_sha_avail) { - crypto_sha_avail = 1; - } -} diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index e4e9fd4023d..2ef63f4b3cb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -14,33 +14,37 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include -#include "mbedtls/des.h" -#include "des_alt.h" +#include #include "crypto-misc.h" #include "nu_bitutil.h" #include "mbed_toolchain.h" - -// Must be a multiple of 64-bit block size +#include "mbed_error.h" + +/* DES DMA compatible buffer requirements + * + * DES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * DES DMA buffer size MAXSIZE_DMABUF must be a multiple of 64-bit block size. + * Its value is estimated to trade memory footprint off against performance. + * + */ #define MAXSIZE_DMABUF (8 * 5) -static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4); -static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4); +MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; +MBED_ALIGN(4) static uint8_t dmabuf_out[MAXSIZE_DMABUF]; -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output); +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output); void mbedtls_des_init(mbedtls_des_context *ctx) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des_context)); } @@ -55,7 +59,6 @@ void mbedtls_des_free( mbedtls_des_context *ctx ) void mbedtls_des3_init( mbedtls_des3_context *ctx ) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des3_context)); } @@ -69,15 +72,16 @@ void mbedtls_des3_free( mbedtls_des3_context *ctx ) } static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; + 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, + 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, + 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, + 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, + 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, + 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, + 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, + 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, + 254 + }; void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE]) { @@ -125,8 +129,7 @@ int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SI #define WEAK_KEY_COUNT 16 -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ +static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, @@ -168,7 +171,7 @@ int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MB memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE); - + return 0; } @@ -191,7 +194,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * Triple-DES key schedule (112-bit, encryption) */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 1; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -207,7 +210,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (112-bit, decryption) */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 0; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -223,7 +226,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, encryption) */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 1; // Keying option 1: All three keys are independent. @@ -239,7 +242,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, decryption) */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 0; // Keying option 1: All three keys are independent. @@ -255,8 +258,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * DES-ECB block encryption/decryption */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output); @@ -267,11 +270,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * DES-CBC buffer encryption/decryption */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output); } @@ -281,8 +284,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * 3DES-ECB block encryption/decryption */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output); @@ -293,11 +296,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * 3DES-CBC buffer encryption/decryption */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output); } @@ -305,103 +308,157 @@ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output) +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output) { + if ((keyopt < 1) || (keyopt > 3)) { + error("Key option in DES alter. requires to be 1/2/3."); + } + + if (key == NULL) { + error("Meet null key pointer in DES alter."); + } + + if ((enc != 0) && (enc != 1)) { + error("Enc/dec flag in DES alter. requires to be 0/1."); + } + + if (tdes_opmode & ~(CRPT_TDES_CTL_TMODE_Msk | CRPT_TDES_CTL_OPMODE_Msk)) { + error("Invalid TMODE/OPMODE in DES alter."); + } + if (length % 8) { return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } - - // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. - CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | - tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); - // Keying option 1: All three keys are independent. - // Keying option 2: K1 and K2 are independent, and K3 = K1. - // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. - if (keyopt == 1) { - CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk; + if (iv == NULL) { + error("Meet null IV pointer in DES alter."); + } + + if (input == NULL || output == NULL) { + error("Meet null input/output pointer in DES alter."); } - else { - CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; + + /* DES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 8-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region + */ + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF, 8)) || + (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF, 8))) { + error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - - // Set DES/TDES keys - // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap. - uint32_t val; - volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0)); - val = nu_get32_be(key[0] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[0] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 4); - *tdes_key ++ = val; + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of DES H/W */ + while (! crypto_des_acquire()); + + /* Init crypto module */ + crypto_init(); + /* Enable DES interrupt */ + TDES_ENABLE_INT(); + + /* Configure TDES_CTL register + * + * BSP TDES driver supports multiple channels. Just use channel #0. + * + * Relationship of keying option and TDES H/W mode configuration + * 1: All three keys are independent ==> TDES 3-key mode (TMODE=1, 3KEYS=1) + * 2: K1 and K2 are independent, and K3 = K1 ==> TDES 2-key mode (TMODE=1, 3KEYS=0) + * 3: All three keys are identical, i.e. K1 = K2 = K3 ==> DES mode (TMODE=0) + * + * tdes_opmode is combination of TMODE/OPMODE, but TDES_Open I/F requires TMODE/OPMODE to be separate. + * We need to divide tdes_opmode to TMODE and OPMODE. + * + * TDES_IN_OUT_WHL_SWAP lets TDES H/W know input/output data are arranged in below for DMA transfer: + * 1. BE for byte sequence in word + * 2. BE for word sequence in double-word + */ + TDES_Open(0, // Channel number (0~4) + enc, // 0: decode, 1: encode + (tdes_opmode & CRPT_TDES_CTL_TMODE_Msk) ? 1 : 0, // 0: DES, 1: TDES + (keyopt == 1) ? 1 : 0, // 0: TDES 2-key mode, 1: TDES 3-key mode + tdes_opmode & CRPT_TDES_CTL_OPMODE_Msk, // ECB/CBC/CFB/OFB/CTR + TDES_IN_OUT_WHL_SWAP); // TDES_NO_SWAP~TDES_IN_OUT_WHL_SWAP + + /* Set DES/TDES keys + * + * TDES_SetKey requires 3x2 word array. Change 3x8 byte array to 3x2 word array. + */ + unsigned i; + uint32_t keys3x2[3][2]; + for (i = 0; i < 3; i ++ ) { + keys3x2[i][0] = nu_get32_be(key[i] + 0); + keys3x2[i][1] = nu_get32_be(key[i] + 4); + } + TDES_SetKey(0, keys3x2); + uint32_t rmn = length; const unsigned char *in_pos = input; unsigned char *out_pos = output; - - while (rmn) { + + while (rmn > 0) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; - + uint32_t ivh, ivl; ivh = nu_get32_be(iv); ivl = nu_get32_be(iv + 4); TDES_SetInitVect(0, ivh, ivl); - + memcpy(dmabuf_in, in_pos, data_len); - + + /* We always use DMA backup buffers, which are guaranteed to be non-overlapped. */ TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - - // Start enc/dec. - // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting. - CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); - while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); - + + crypto_des_prestart(); + TDES_Start(0, CRYPTO_DMA_ONE_SHOT); + crypto_des_wait(); + memcpy(out_pos, dmabuf_out, data_len); in_pos += data_len; out_pos += data_len; rmn -= data_len; - + // Update IV for next block enc/dec in next function call switch (tdes_opmode) { - case DES_MODE_OFB: - case TDES_MODE_OFB: { - // OFB: IV (enc/dec) = output block XOR input block - uint32_t lbh, lbl; - // Last block of input data - lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); - lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); - // Last block of output data - ivh = nu_get32_be(dmabuf_out + 4); - ivl = nu_get32_be(dmabuf_out + 0); - ivh = ivh ^ lbh; - ivl = ivl ^ lbl; - nu_set32_be(iv + 4, ivh); - nu_set32_be(iv, ivl); - break; - } - case DES_MODE_CBC: - case DES_MODE_CFB: - case TDES_MODE_CBC: - case TDES_MODE_CFB: { - // CBC/CFB: IV (enc) = output block - // IV (dec) = input block - if (enc) { - memcpy(iv, dmabuf_out + data_len - 8, 8); - } - else { - memcpy(iv, dmabuf_in + data_len - 8, 8); - } + case DES_MODE_OFB: + case TDES_MODE_OFB: { + // OFB: IV (enc/dec) = output block XOR input block + uint32_t lbh, lbl; + // Last block of input data + lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); + lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); + // Last block of output data + ivh = nu_get32_be(dmabuf_out + 4); + ivl = nu_get32_be(dmabuf_out + 0); + ivh = ivh ^ lbh; + ivl = ivl ^ lbl; + nu_set32_be(iv + 4, ivh); + nu_set32_be(iv, ivl); + break; + } + case DES_MODE_CBC: + case DES_MODE_CFB: + case TDES_MODE_CBC: + case TDES_MODE_CFB: { + // CBC/CFB: IV (enc) = output block + // IV (dec) = input block + if (enc) { + memcpy(iv, dmabuf_out + data_len - 8, 8); + } else { + memcpy(iv, dmabuf_in + data_len - 8, 8); } } + } } + + /* Disable DES interrupt */ + TDES_DISABLE_INT(); + /* Uninit crypto module */ + crypto_uninit(); + + /* Release ownership of DES H/W */ + crypto_des_release(); return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h index b783889d538..09b693c524a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.h @@ -13,23 +13,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" -#if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include #include -#include "des.h" -#include "des_alt_sw.h" #ifdef __cplusplus extern "C" { @@ -38,19 +31,19 @@ extern "C" { /** * \brief DES context structure */ -typedef struct -{ - int enc; /*!< 0: dec, 1: enc */ - uint16_t keyopt; - uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ +typedef struct { + int enc; /* 0: dec, 1: enc */ + uint16_t keyopt; /* 1: All three keys are independent. + * 2: K1 and K2 are independent, and K3 = K1. + * 3: All three keys are identical, i.e. K1 = K2 = K3. */ + uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /* 3DES keys */ } mbedtls_des_context; /** * \brief Triple-DES context structure */ -typedef struct -{ +typedef struct { int enc; /*!< 0: dec, 1: enc */ uint16_t keyopt; uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ @@ -145,7 +138,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * \return 0 */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (112-bit, decryption) @@ -156,7 +149,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (168-bit, encryption) @@ -167,7 +160,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief Triple-DES key schedule (168-bit, decryption) @@ -178,7 +171,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief DES-ECB block encryption/decryption @@ -190,8 +183,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * \return 0 if successful */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -213,11 +206,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * \param output buffer holding the output data */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -230,8 +223,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * \return 0 if successful */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -255,11 +248,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -277,6 +270,5 @@ void mbedtls_des_setkey( uint32_t SK[32], #endif #endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ #endif /* des_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c deleted file mode 100644 index 1e51151c862..00000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * FIPS-46-3 compliant Triple-DES implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -/* - * DES, on which TDES is based, was originally designed by Horst Feistel - * at IBM in 1974, and was adopted as a standard by NIST (formerly NBS). - * - * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf - */ - -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include "mbedtls/des.h" - -#include - -/* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - -/* - * 32-bit integer manipulation macros (big endian) - */ -#ifndef GET_UINT32_BE -#define GET_UINT32_BE(n,b,i) \ -{ \ - (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ - | ( (uint32_t) (b)[(i) + 1] << 16 ) \ - | ( (uint32_t) (b)[(i) + 2] << 8 ) \ - | ( (uint32_t) (b)[(i) + 3] ); \ -} -#endif - -#ifndef PUT_UINT32_BE -#define PUT_UINT32_BE(n,b,i) \ -{ \ - (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ - (b)[(i) + 3] = (unsigned char) ( (n) ); \ -} -#endif - -/* - * Expanded DES S-boxes - */ -static const uint32_t SB1[64] = -{ - 0x01010400, 0x00000000, 0x00010000, 0x01010404, - 0x01010004, 0x00010404, 0x00000004, 0x00010000, - 0x00000400, 0x01010400, 0x01010404, 0x00000400, - 0x01000404, 0x01010004, 0x01000000, 0x00000004, - 0x00000404, 0x01000400, 0x01000400, 0x00010400, - 0x00010400, 0x01010000, 0x01010000, 0x01000404, - 0x00010004, 0x01000004, 0x01000004, 0x00010004, - 0x00000000, 0x00000404, 0x00010404, 0x01000000, - 0x00010000, 0x01010404, 0x00000004, 0x01010000, - 0x01010400, 0x01000000, 0x01000000, 0x00000400, - 0x01010004, 0x00010000, 0x00010400, 0x01000004, - 0x00000400, 0x00000004, 0x01000404, 0x00010404, - 0x01010404, 0x00010004, 0x01010000, 0x01000404, - 0x01000004, 0x00000404, 0x00010404, 0x01010400, - 0x00000404, 0x01000400, 0x01000400, 0x00000000, - 0x00010004, 0x00010400, 0x00000000, 0x01010004 -}; - -static const uint32_t SB2[64] = -{ - 0x80108020, 0x80008000, 0x00008000, 0x00108020, - 0x00100000, 0x00000020, 0x80100020, 0x80008020, - 0x80000020, 0x80108020, 0x80108000, 0x80000000, - 0x80008000, 0x00100000, 0x00000020, 0x80100020, - 0x00108000, 0x00100020, 0x80008020, 0x00000000, - 0x80000000, 0x00008000, 0x00108020, 0x80100000, - 0x00100020, 0x80000020, 0x00000000, 0x00108000, - 0x00008020, 0x80108000, 0x80100000, 0x00008020, - 0x00000000, 0x00108020, 0x80100020, 0x00100000, - 0x80008020, 0x80100000, 0x80108000, 0x00008000, - 0x80100000, 0x80008000, 0x00000020, 0x80108020, - 0x00108020, 0x00000020, 0x00008000, 0x80000000, - 0x00008020, 0x80108000, 0x00100000, 0x80000020, - 0x00100020, 0x80008020, 0x80000020, 0x00100020, - 0x00108000, 0x00000000, 0x80008000, 0x00008020, - 0x80000000, 0x80100020, 0x80108020, 0x00108000 -}; - -static const uint32_t SB3[64] = -{ - 0x00000208, 0x08020200, 0x00000000, 0x08020008, - 0x08000200, 0x00000000, 0x00020208, 0x08000200, - 0x00020008, 0x08000008, 0x08000008, 0x00020000, - 0x08020208, 0x00020008, 0x08020000, 0x00000208, - 0x08000000, 0x00000008, 0x08020200, 0x00000200, - 0x00020200, 0x08020000, 0x08020008, 0x00020208, - 0x08000208, 0x00020200, 0x00020000, 0x08000208, - 0x00000008, 0x08020208, 0x00000200, 0x08000000, - 0x08020200, 0x08000000, 0x00020008, 0x00000208, - 0x00020000, 0x08020200, 0x08000200, 0x00000000, - 0x00000200, 0x00020008, 0x08020208, 0x08000200, - 0x08000008, 0x00000200, 0x00000000, 0x08020008, - 0x08000208, 0x00020000, 0x08000000, 0x08020208, - 0x00000008, 0x00020208, 0x00020200, 0x08000008, - 0x08020000, 0x08000208, 0x00000208, 0x08020000, - 0x00020208, 0x00000008, 0x08020008, 0x00020200 -}; - -static const uint32_t SB4[64] = -{ - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802080, 0x00800081, 0x00800001, 0x00002001, - 0x00000000, 0x00802000, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00800080, 0x00800001, - 0x00000001, 0x00002000, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002001, 0x00002080, - 0x00800081, 0x00000001, 0x00002080, 0x00800080, - 0x00002000, 0x00802080, 0x00802081, 0x00000081, - 0x00800080, 0x00800001, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00000000, 0x00802000, - 0x00002080, 0x00800080, 0x00800081, 0x00000001, - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802081, 0x00000081, 0x00000001, 0x00002000, - 0x00800001, 0x00002001, 0x00802080, 0x00800081, - 0x00002001, 0x00002080, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002000, 0x00802080 -}; - -static const uint32_t SB5[64] = -{ - 0x00000100, 0x02080100, 0x02080000, 0x42000100, - 0x00080000, 0x00000100, 0x40000000, 0x02080000, - 0x40080100, 0x00080000, 0x02000100, 0x40080100, - 0x42000100, 0x42080000, 0x00080100, 0x40000000, - 0x02000000, 0x40080000, 0x40080000, 0x00000000, - 0x40000100, 0x42080100, 0x42080100, 0x02000100, - 0x42080000, 0x40000100, 0x00000000, 0x42000000, - 0x02080100, 0x02000000, 0x42000000, 0x00080100, - 0x00080000, 0x42000100, 0x00000100, 0x02000000, - 0x40000000, 0x02080000, 0x42000100, 0x40080100, - 0x02000100, 0x40000000, 0x42080000, 0x02080100, - 0x40080100, 0x00000100, 0x02000000, 0x42080000, - 0x42080100, 0x00080100, 0x42000000, 0x42080100, - 0x02080000, 0x00000000, 0x40080000, 0x42000000, - 0x00080100, 0x02000100, 0x40000100, 0x00080000, - 0x00000000, 0x40080000, 0x02080100, 0x40000100 -}; - -static const uint32_t SB6[64] = -{ - 0x20000010, 0x20400000, 0x00004000, 0x20404010, - 0x20400000, 0x00000010, 0x20404010, 0x00400000, - 0x20004000, 0x00404010, 0x00400000, 0x20000010, - 0x00400010, 0x20004000, 0x20000000, 0x00004010, - 0x00000000, 0x00400010, 0x20004010, 0x00004000, - 0x00404000, 0x20004010, 0x00000010, 0x20400010, - 0x20400010, 0x00000000, 0x00404010, 0x20404000, - 0x00004010, 0x00404000, 0x20404000, 0x20000000, - 0x20004000, 0x00000010, 0x20400010, 0x00404000, - 0x20404010, 0x00400000, 0x00004010, 0x20000010, - 0x00400000, 0x20004000, 0x20000000, 0x00004010, - 0x20000010, 0x20404010, 0x00404000, 0x20400000, - 0x00404010, 0x20404000, 0x00000000, 0x20400010, - 0x00000010, 0x00004000, 0x20400000, 0x00404010, - 0x00004000, 0x00400010, 0x20004010, 0x00000000, - 0x20404000, 0x20000000, 0x00400010, 0x20004010 -}; - -static const uint32_t SB7[64] = -{ - 0x00200000, 0x04200002, 0x04000802, 0x00000000, - 0x00000800, 0x04000802, 0x00200802, 0x04200800, - 0x04200802, 0x00200000, 0x00000000, 0x04000002, - 0x00000002, 0x04000000, 0x04200002, 0x00000802, - 0x04000800, 0x00200802, 0x00200002, 0x04000800, - 0x04000002, 0x04200000, 0x04200800, 0x00200002, - 0x04200000, 0x00000800, 0x00000802, 0x04200802, - 0x00200800, 0x00000002, 0x04000000, 0x00200800, - 0x04000000, 0x00200800, 0x00200000, 0x04000802, - 0x04000802, 0x04200002, 0x04200002, 0x00000002, - 0x00200002, 0x04000000, 0x04000800, 0x00200000, - 0x04200800, 0x00000802, 0x00200802, 0x04200800, - 0x00000802, 0x04000002, 0x04200802, 0x04200000, - 0x00200800, 0x00000000, 0x00000002, 0x04200802, - 0x00000000, 0x00200802, 0x04200000, 0x00000800, - 0x04000002, 0x04000800, 0x00000800, 0x00200002 -}; - -static const uint32_t SB8[64] = -{ - 0x10001040, 0x00001000, 0x00040000, 0x10041040, - 0x10000000, 0x10001040, 0x00000040, 0x10000000, - 0x00040040, 0x10040000, 0x10041040, 0x00041000, - 0x10041000, 0x00041040, 0x00001000, 0x00000040, - 0x10040000, 0x10000040, 0x10001000, 0x00001040, - 0x00041000, 0x00040040, 0x10040040, 0x10041000, - 0x00001040, 0x00000000, 0x00000000, 0x10040040, - 0x10000040, 0x10001000, 0x00041040, 0x00040000, - 0x00041040, 0x00040000, 0x10041000, 0x00001000, - 0x00000040, 0x10040040, 0x00001000, 0x00041040, - 0x10001000, 0x00000040, 0x10000040, 0x10040000, - 0x10040040, 0x10000000, 0x00040000, 0x10001040, - 0x00000000, 0x10041040, 0x00040040, 0x10000040, - 0x10040000, 0x10001000, 0x10001040, 0x00000000, - 0x10041040, 0x00041000, 0x00041000, 0x00001040, - 0x00001040, 0x00040040, 0x10000000, 0x10041000 -}; - -/* - * PC1: left and right halves bit-swap - */ -static const uint32_t LHs[16] = -{ - 0x00000000, 0x00000001, 0x00000100, 0x00000101, - 0x00010000, 0x00010001, 0x00010100, 0x00010101, - 0x01000000, 0x01000001, 0x01000100, 0x01000101, - 0x01010000, 0x01010001, 0x01010100, 0x01010101 -}; - -static const uint32_t RHs[16] = -{ - 0x00000000, 0x01000000, 0x00010000, 0x01010000, - 0x00000100, 0x01000100, 0x00010100, 0x01010100, - 0x00000001, 0x01000001, 0x00010001, 0x01010001, - 0x00000101, 0x01000101, 0x00010101, 0x01010101, -}; - -/* - * Initial Permutation macro - */ -#define DES_IP(X,Y) \ -{ \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T; \ - X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF; \ -} - -/* - * Final Permutation macro - */ -#define DES_FP(X,Y) \ -{ \ - X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T; \ - Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF; \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ -} - -/* - * DES round macro - */ -#define DES_ROUND(X,Y) \ -{ \ - T = *SK++ ^ X; \ - Y ^= SB8[ (T ) & 0x3F ] ^ \ - SB6[ (T >> 8) & 0x3F ] ^ \ - SB4[ (T >> 16) & 0x3F ] ^ \ - SB2[ (T >> 24) & 0x3F ]; \ - \ - T = *SK++ ^ ((X << 28) | (X >> 4)); \ - Y ^= SB7[ (T ) & 0x3F ] ^ \ - SB5[ (T >> 8) & 0x3F ] ^ \ - SB3[ (T >> 16) & 0x3F ] ^ \ - SB1[ (T >> 24) & 0x3F ]; \ -} - -#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; } - -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) ); -} - -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) ); -} - -static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; - -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - key[i] = odd_parity_table[key[i] / 2]; -} - -/* - * Check the given key's parity, returns 1 on failure, 0 on SUCCESS - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - if( key[i] != odd_parity_table[key[i] / 2] ) - return( 1 ); - - return( 0 ); -} - -/* - * Table of weak and semi-weak keys - * - * Source: http://en.wikipedia.org/wiki/Weak_key - * - * Weak: - * Alternating ones + zeros (0x0101010101010101) - * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE) - * '0xE0E0E0E0F1F1F1F1' - * '0x1F1F1F1F0E0E0E0E' - * - * Semi-weak: - * 0x011F011F010E010E and 0x1F011F010E010E01 - * 0x01E001E001F101F1 and 0xE001E001F101F101 - * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01 - * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E - * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E - * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1 - * - */ - -#define WEAK_KEY_COUNT 16 - -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ - { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, - { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, - { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, - { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 }, - - { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E }, - { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 }, - { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 }, - { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 }, - { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE }, - { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 }, - { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 }, - { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E }, - { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE }, - { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E }, - { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE }, - { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 } -}; - -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < WEAK_KEY_COUNT; i++ ) - if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 ) - return( 1 ); - - return( 0 ); -} - -void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - uint32_t X, Y, T; - - GET_UINT32_BE( X, key, 0 ); - GET_UINT32_BE( Y, key, 4 ); - - /* - * Permuted Choice 1 - */ - T = ((Y >> 4) ^ X) & 0x0F0F0F0F; X ^= T; Y ^= (T << 4); - T = ((Y ) ^ X) & 0x10101010; X ^= T; Y ^= (T ); - - X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2) - | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) - | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) - | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); - - Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2) - | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) - | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) - | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); - - X &= 0x0FFFFFFF; - Y &= 0x0FFFFFFF; - - /* - * calculate subkeys - */ - for( i = 0; i < 16; i++ ) - { - if( i < 2 || i == 8 || i == 15 ) - { - X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF; - Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF; - } - else - { - X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF; - Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF; - } - - *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000) - | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) - | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) - | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) - | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) - | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) - | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) - | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) - | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) - | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) - | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); - - *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000) - | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) - | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) - | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) - | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) - | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) - | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) - | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) - | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) - | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) - | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); - } -} - -/* - * DES key schedule (56-bit, encryption) - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - mbedtls_des_setkey( ctx->sk, key ); - - return( 0 ); -} - -/* - * DES key schedule (56-bit, decryption) - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - mbedtls_des_setkey( ctx->sk, key ); - - for( i = 0; i < 16; i += 2 ) - { - SWAP( ctx->sk[i ], ctx->sk[30 - i] ); - SWAP( ctx->sk[i + 1], ctx->sk[31 - i] ); - } - - return( 0 ); -} - -static void des3_set2key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - - for( i = 0; i < 32; i += 2 ) - { - dsk[i ] = esk[30 - i]; - dsk[i + 1] = esk[31 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - esk[i + 64] = esk[i ]; - esk[i + 65] = esk[i + 1]; - - dsk[i + 64] = dsk[i ]; - dsk[i + 65] = dsk[i + 1]; - } -} - -/* - * Triple-DES key schedule (112-bit, encryption) - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (112-bit, decryption) - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -static void des3_set3key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[24] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - mbedtls_des_setkey( esk + 64, key + 16 ); - - for( i = 0; i < 32; i += 2 ) - { - dsk[i ] = esk[94 - i]; - dsk[i + 1] = esk[95 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - dsk[i + 64] = esk[30 - i]; - dsk[i + 65] = esk[31 - i]; - } -} - -/* - * Triple-DES key schedule (168-bit, encryption) - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (168-bit, decryption) - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * DES-ECB block encryption/decryption - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * DES-CBC buffer encryption/decryption - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { - memcpy( temp, input, 8 ); - mbedtls_des_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/* - * 3DES-ECB block encryption/decryption - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( X, Y ); - DES_ROUND( Y, X ); - } - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * 3DES-CBC buffer encryption/decryption - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des3_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { - memcpy( temp, input, 8 ); - mbedtls_des3_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h deleted file mode 100644 index d42aa2ba050..00000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt_sw.h +++ /dev/null @@ -1,283 +0,0 @@ -/** - * \file des.h - * - * \brief DES block cipher - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -#ifndef MBEDTLS_DES_ALT_SW_H -#define MBEDTLS_DES_ALT_SW_H - -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief DES context structure - */ -typedef struct -{ - uint32_t sk[32]; /*!< DES subkeys */ -} -mbedtls_des_sw_context; - -/** - * \brief Triple-DES context structure - */ -typedef struct -{ - uint32_t sk[96]; /*!< 3DES subkeys */ -} -mbedtls_des3_sw_context; - -/** - * \brief Initialize DES context - * - * \param ctx DES context to be initialized - */ -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ); - -/** - * \brief Clear DES context - * - * \param ctx DES context to be cleared - */ -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ); - -/** - * \brief Initialize Triple-DES context - * - * \param ctx DES3 context to be initialized - */ -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Clear Triple-DES context - * - * \param ctx DES3 context to be cleared - */ -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Set key parity on the given key to odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - */ -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key parity on the given key is odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - * - * \return 0 is parity was ok, 1 if parity was not correct. - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key is not a weak or semi-weak DES key - * - * \param key 8-byte secret key - * - * \return 0 if no weak key was found, 1 if a weak key was identified. - */ -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, encryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, decryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Triple-DES key schedule (112-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (112-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (168-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief Triple-DES key schedule (168-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief DES-ECB block encryption/decryption - * - * \param ctx DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief 3DES-ECB block encryption/decryption - * - * \param ctx 3DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief 3DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx 3DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief Internal function for key expansion. - * (Only exposed to allow overriding it, - * see MBEDTLS_DES_SETKEY_ALT) - * - * \param SK Round keys - * \param key Base key - */ -void mbedtls_des_sw_setkey( uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ - -#endif /* des.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index de6ff01415c..35d71226100 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -14,53 +14,69 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { - ctx->ishw = 1; + if (try_hw && crypto_sha_acquire()) { + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha1_hw_init(&ctx->hw_ctx); - } - else { - ctx->ishw = 0; + } else { + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha1_sw_init(&ctx->sw_ctx); } } +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +{ + mbedtls_sha1_init_internal(ctx, 1); +} + void mbedtls_sha1_free(mbedtls_sha1_context *ctx) { if (ctx == NULL) { return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { - if (src->ishw) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + // If dst is H/W context, we need to change it to S/W context first before cloning to. + if (dst->active_ctx == &dst->hw_ctx) { + mbedtls_sha1_free(dst); + // Force S/W context + mbedtls_sha1_init_internal(dst, 0); + } + + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -78,8 +94,7 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -90,10 +105,9 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, */ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_starts(&ctx->hw_ctx); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_starts(&ctx->sw_ctx); } } @@ -103,10 +117,9 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) */ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -116,20 +129,18 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, */ void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_finish(&ctx->hw_ctx, output); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_process(&ctx->hw_ctx, data); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h index 6cf738a1bb6..59f519fac96 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.h @@ -16,13 +16,8 @@ #ifndef MBEDTLS_SHA1_ALT_H #define MBEDTLS_SHA1_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include "sha_alt_hw.h" @@ -37,9 +32,8 @@ struct mbedtls_sha1_context_s; /** * \brief SHA-1 context structure */ -typedef struct mbedtls_sha1_context_s -{ - int ishw; +typedef struct mbedtls_sha1_context_s { + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha1_sw_context sw_ctx; } @@ -100,6 +94,5 @@ void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[6 #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c index cc7ff7f0741..759823b2cc5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.c @@ -24,17 +24,10 @@ * http://www.itl.nist.gov/fipspubs/fip180-1.htm */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) - -#include "mbedtls/sha1.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) @@ -46,8 +39,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } /* @@ -87,7 +82,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ) } void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ) + const mbedtls_sha1_sw_context *src ) { *dst = *src; } @@ -283,8 +278,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha1_sw_process( ctx, ctx->buffer ); input += fill; @@ -292,8 +286,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha1_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -303,9 +296,8 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha1_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha1_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -321,7 +313,7 @@ void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[ unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h index 9d138abb8ac..5ba3aa853dd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt_sw.h @@ -23,13 +23,6 @@ #ifndef MBEDTLS_SHA1_ALT_SW_H #define MBEDTLS_SHA1_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include @@ -42,8 +35,7 @@ extern "C" { /** * \brief SHA-1 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[5]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -71,7 +63,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ); + const mbedtls_sha1_sw_context *src ); /** * \brief SHA-1 context setup @@ -105,6 +97,5 @@ void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index de337ac5259..c4e27dfa5f6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -14,53 +14,69 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { - ctx->ishw = 1; + if (try_hw && crypto_sha_acquire()) { + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha256_hw_init(&ctx->hw_ctx); - } - else { - ctx->ishw = 0; + } else { + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha256_sw_init(&ctx->sw_ctx); } } +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + mbedtls_sha256_init_internal(ctx, 1); +} + void mbedtls_sha256_free(mbedtls_sha256_context *ctx) { if (ctx == NULL) { return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha256_clone(mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src) + const mbedtls_sha256_context *src) { - if (src->ishw) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + // If dst is H/W context, we need to change it to S/W context first before cloning to. + if (dst->active_ctx == &dst->hw_ctx) { + mbedtls_sha256_free(dst); + // Force S/W context + mbedtls_sha256_init_internal(dst, 0); + } + + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -79,8 +95,7 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -90,11 +105,10 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, * SHA-256 context setup */ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) -{ - if (ctx->ishw) { +{ + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224); } } @@ -104,10 +118,9 @@ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) */ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -117,20 +130,18 @@ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inp */ void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_finish(&ctx->hw_ctx, output); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_process(&ctx->hw_ctx, data); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h index 23a156ddd7d..04ff65fd188 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.h @@ -16,13 +16,8 @@ #ifndef MBEDTLS_SHA256_ALT_H #define MBEDTLS_SHA256_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include "sha_alt_hw.h" @@ -37,9 +32,8 @@ struct mbedtls_sha256_context_s; /** * \brief SHA-256 context structure */ -typedef struct mbedtls_sha256_context_s -{ - int ishw; +typedef struct mbedtls_sha256_context_s { + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha256_sw_context sw_ctx; } @@ -84,7 +78,7 @@ void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest @@ -102,6 +96,5 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c index 20626433351..771c998eefd 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.c @@ -24,17 +24,11 @@ * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "mbedtls/sha256.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) @@ -49,8 +43,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; + while( n-- ) *p++ = 0; } /* @@ -90,7 +86,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ) } void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ) + const mbedtls_sha256_sw_context *src ) { *dst = *src; } @@ -103,8 +99,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->total[0] = 0; ctx->total[1] = 0; - if( is224 == 0 ) - { + if( is224 == 0 ) { /* SHA-256 */ ctx->state[0] = 0x6A09E667; ctx->state[1] = 0xBB67AE85; @@ -114,9 +109,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->state[5] = 0x9B05688C; ctx->state[6] = 0x1F83D9AB; ctx->state[7] = 0x5BE0CD19; - } - else - { + } else { /* SHA-224 */ ctx->state[0] = 0xC1059ED8; ctx->state[1] = 0x367CD507; @@ -131,8 +124,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->is224 = is224; } -static const uint32_t K[] = -{ +static const uint32_t K[] = { 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5, 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5, 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3, @@ -186,8 +178,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c A[i] = ctx->state[i]; #if defined(MBEDTLS_SHA256_SMALLER) - for( i = 0; i < 64; i++ ) - { + for( i = 0; i < 64; i++ ) { if( i < 16 ) GET_UINT32_BE( W[i], data, 4 * i ); else @@ -195,15 +186,21 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); - temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3]; - A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1; + temp1 = A[7]; + A[7] = A[6]; + A[6] = A[5]; + A[5] = A[4]; + A[4] = A[3]; + A[3] = A[2]; + A[2] = A[1]; + A[1] = A[0]; + A[0] = temp1; } #else /* MBEDTLS_SHA256_SMALLER */ for( i = 0; i < 16; i++ ) GET_UINT32_BE( W[i], data, 4 * i ); - for( i = 0; i < 16; i += 8 ) - { + for( i = 0; i < 16; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] ); @@ -214,8 +211,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] ); } - for( i = 16; i < 64; i += 8 ) - { + for( i = 16; i < 64; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] ); @@ -235,7 +231,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c * SHA-256 process buffer */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ) + size_t ilen ) { size_t fill; uint32_t left; @@ -252,8 +248,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha256_sw_process( ctx, ctx->buffer ); input += fill; @@ -261,8 +256,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha256_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -272,9 +266,8 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha256_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha256_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -290,7 +283,7 @@ void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char out unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h index c1b72ea8f70..6c292b7516f 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt_sw.h @@ -23,13 +23,6 @@ #ifndef MBEDTLS_SHA256_ALT_SW_H #define MBEDTLS_SHA256_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include @@ -42,8 +35,7 @@ extern "C" { /** * \brief SHA-256 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[8]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -72,7 +64,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ); + const mbedtls_sha256_sw_context *src ); /** * \brief SHA-256 context setup @@ -90,7 +82,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest @@ -108,6 +100,5 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index 365d172b54d..48baf9132f2 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -14,53 +14,69 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) -#include "sha512_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha512_init(mbedtls_sha512_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha512_init_internal(mbedtls_sha512_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { - ctx->ishw = 1; + if (try_hw && crypto_sha_acquire()) { + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha512_hw_init(&ctx->hw_ctx); - } - else { - ctx->ishw = 0; + } else { + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha512_sw_init(&ctx->sw_ctx); } } +void mbedtls_sha512_init(mbedtls_sha512_context *ctx) +{ + mbedtls_sha512_init_internal(ctx, 1); +} + void mbedtls_sha512_free(mbedtls_sha512_context *ctx) { if (ctx == NULL) { return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha512_clone(mbedtls_sha512_context *dst, - const mbedtls_sha512_context *src) + const mbedtls_sha512_context *src) { - if (src->ishw) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + // If dst is H/W context, we need to change it to S/W context first before cloning to. + if (dst->active_ctx == &dst->hw_ctx) { + mbedtls_sha512_free(dst); + // Force S/W context + mbedtls_sha512_init_internal(dst, 0); + } + + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -80,8 +96,7 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha512_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -91,11 +106,10 @@ void mbedtls_sha512_clone(mbedtls_sha512_context *dst, * SHA-512 context setup */ void mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) -{ - if (ctx->ishw) { +{ + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_starts(&ctx->hw_ctx, is384); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_starts(&ctx->sw_ctx, is384); } } @@ -105,10 +119,9 @@ void mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) */ void mbedtls_sha512_update(mbedtls_sha512_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -118,20 +131,18 @@ void mbedtls_sha512_update(mbedtls_sha512_context *ctx, const unsigned char *inp */ void mbedtls_sha512_finish(mbedtls_sha512_context *ctx, unsigned char output[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_finish(&ctx->hw_ctx, output); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha512_process(mbedtls_sha512_context *ctx, const unsigned char data[128]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha512_hw_process(&ctx->hw_ctx, data); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha512_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h index 67ecb0f5896..afd0294ca39 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.h @@ -16,13 +16,8 @@ #ifndef MBEDTLS_SHA512_ALT_H #define MBEDTLS_SHA512_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha512.h" -#if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) #include "sha_alt_hw.h" @@ -37,9 +32,8 @@ struct mbedtls_sha512_context_s; /** * \brief SHA-512 context structure */ -typedef struct mbedtls_sha512_context_s -{ - int ishw; +typedef struct mbedtls_sha512_context_s { + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha512_sw_context sw_ctx; } @@ -84,7 +78,7 @@ void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, int is384 ); * \param ilen length of the input data */ void mbedtls_sha512_update( mbedtls_sha512_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-512 final digest @@ -102,6 +96,5 @@ void mbedtls_sha512_process( mbedtls_sha512_context *ctx, const unsigned char da #endif #endif /* MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C */ #endif /* sha512_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c index 1f8387445c1..7dfce4ff855 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.c @@ -24,21 +24,15 @@ * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) -#include "mbedtls/sha512.h" - #if defined(_MSC_VER) || defined(__WATCOMC__) - #define UL64(x) x##ui64 +#define UL64(x) x##ui64 #else - #define UL64(x) x##ULL +#define UL64(x) x##ULL #endif #include @@ -56,8 +50,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; + while( n-- ) *p++ = 0; } /* @@ -105,7 +101,7 @@ void mbedtls_sha512_sw_free( mbedtls_sha512_sw_context *ctx ) } void mbedtls_sha512_sw_clone( mbedtls_sha512_sw_context *dst, - const mbedtls_sha512_sw_context *src ) + const mbedtls_sha512_sw_context *src ) { *dst = *src; } @@ -118,8 +114,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ) ctx->total[0] = 0; ctx->total[1] = 0; - if( is384 == 0 ) - { + if( is384 == 0 ) { /* SHA-512 */ ctx->state[0] = UL64(0x6A09E667F3BCC908); ctx->state[1] = UL64(0xBB67AE8584CAA73B); @@ -129,9 +124,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ) ctx->state[5] = UL64(0x9B05688C2B3E6C1F); ctx->state[6] = UL64(0x1F83D9ABFB41BD6B); ctx->state[7] = UL64(0x5BE0CD19137E2179); - } - else - { + } else { /* SHA-384 */ ctx->state[0] = UL64(0xCBBB9D5DC1059ED8); ctx->state[1] = UL64(0x629A292A367CD507); @@ -151,8 +144,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ) /* * Round constants */ -static const uint64_t K[80] = -{ +static const uint64_t K[80] = { UL64(0x428A2F98D728AE22), UL64(0x7137449123EF65CD), UL64(0xB5C0FBCFEC4D3B2F), UL64(0xE9B5DBA58189DBBC), UL64(0x3956C25BF348B538), UL64(0x59F111F1B605D019), @@ -220,13 +212,11 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c d += temp1; h = temp1 + temp2; \ } - for( i = 0; i < 16; i++ ) - { + for( i = 0; i < 16; i++ ) { GET_UINT64_BE( W[i], data, i << 3 ); } - for( ; i < 80; i++ ) - { + for( ; i < 80; i++ ) { W[i] = S1(W[i - 2]) + W[i - 7] + S0(W[i - 15]) + W[i - 16]; } @@ -241,18 +231,24 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c H = ctx->state[7]; i = 0; - do - { - P( A, B, C, D, E, F, G, H, W[i], K[i] ); i++; - P( H, A, B, C, D, E, F, G, W[i], K[i] ); i++; - P( G, H, A, B, C, D, E, F, W[i], K[i] ); i++; - P( F, G, H, A, B, C, D, E, W[i], K[i] ); i++; - P( E, F, G, H, A, B, C, D, W[i], K[i] ); i++; - P( D, E, F, G, H, A, B, C, W[i], K[i] ); i++; - P( C, D, E, F, G, H, A, B, W[i], K[i] ); i++; - P( B, C, D, E, F, G, H, A, W[i], K[i] ); i++; - } - while( i < 80 ); + do { + P( A, B, C, D, E, F, G, H, W[i], K[i] ); + i++; + P( H, A, B, C, D, E, F, G, W[i], K[i] ); + i++; + P( G, H, A, B, C, D, E, F, W[i], K[i] ); + i++; + P( F, G, H, A, B, C, D, E, W[i], K[i] ); + i++; + P( E, F, G, H, A, B, C, D, W[i], K[i] ); + i++; + P( D, E, F, G, H, A, B, C, W[i], K[i] ); + i++; + P( C, D, E, F, G, H, A, B, W[i], K[i] ); + i++; + P( B, C, D, E, F, G, H, A, W[i], K[i] ); + i++; + } while( i < 80 ); ctx->state[0] += A; ctx->state[1] += B; @@ -269,7 +265,7 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c * SHA-512 process buffer */ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned char *input, - size_t ilen ) + size_t ilen ) { size_t fill; unsigned int left; @@ -285,8 +281,7 @@ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned ch if( ctx->total[0] < (uint64_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha512_sw_process( ctx, ctx->buffer ); input += fill; @@ -294,8 +289,7 @@ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned ch left = 0; } - while( ilen >= 128 ) - { + while( ilen >= 128 ) { mbedtls_sha512_sw_process( ctx, input ); input += 128; ilen -= 128; @@ -305,9 +299,8 @@ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned ch memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha512_padding[128] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha512_padding[128] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -327,7 +320,7 @@ void mbedtls_sha512_sw_finish( mbedtls_sha512_sw_context *ctx, unsigned char out unsigned char msglen[16]; high = ( ctx->total[0] >> 61 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT64_BE( high, msglen, 0 ); @@ -346,8 +339,7 @@ void mbedtls_sha512_sw_finish( mbedtls_sha512_sw_context *ctx, unsigned char out PUT_UINT64_BE( ctx->state[4], output, 32 ); PUT_UINT64_BE( ctx->state[5], output, 40 ); - if( ctx->is384 == 0 ) - { + if( ctx->is384 == 0 ) { PUT_UINT64_BE( ctx->state[6], output, 48 ); PUT_UINT64_BE( ctx->state[7], output, 56 ); } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h index cbdd9b49628..6c0aed40560 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt_sw.h @@ -23,13 +23,6 @@ #ifndef MBEDTLS_SHA512_ALT_SW_H #define MBEDTLS_SHA512_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) #include @@ -42,8 +35,7 @@ extern "C" { /** * \brief SHA-512 context structure */ -typedef struct -{ +typedef struct { uint64_t total[2]; /*!< number of bytes processed */ uint64_t state[8]; /*!< intermediate digest state */ unsigned char buffer[128]; /*!< data block being processed */ @@ -72,7 +64,7 @@ void mbedtls_sha512_sw_free( mbedtls_sha512_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha512_sw_clone( mbedtls_sha512_sw_context *dst, - const mbedtls_sha512_sw_context *src ); + const mbedtls_sha512_sw_context *src ); /** * \brief SHA-512 context setup @@ -90,7 +82,7 @@ void mbedtls_sha512_sw_starts( mbedtls_sha512_sw_context *ctx, int is384 ); * \param ilen length of the input data */ void mbedtls_sha512_sw_update( mbedtls_sha512_sw_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-512 final digest @@ -108,6 +100,5 @@ void mbedtls_sha512_sw_process( mbedtls_sha512_sw_context *ctx, const unsigned c #endif #endif /* MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C */ #endif /* sha512_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c index 3b5c65793a7..1067fb4057a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c @@ -14,30 +14,18 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) -#if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" -#endif /* MBEDTLS_SHA1_ALT */ - -#if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" -#endif /* MBEDTLS_SHA256_ALT */ - -#if defined(MBEDTLS_SHA512_ALT) -#include "sha512_alt.h" -#endif /* MBEDTLS_SHA512_ALT */ - #include "nu_bitutil.h" +#include "nu_timer.h" #include "mbed_assert.h" +#include "mbed_error.h" #include "crypto-misc.h" #include @@ -53,8 +41,9 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha1_hw_free(crypto_sha_context *ctx) @@ -63,30 +52,28 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) return; } - crypto_zeroize(ctx, sizeof(crypto_sha_context)); -} + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; -void mbedtls_sha1_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; + /* Uninit crypto module */ + crypto_uninit(); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; ctx->blocksize_mask = 0x3F; SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP, 0); - + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; - + return; } @@ -102,17 +89,16 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, 20); - - CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha1_sw_context ctx_sw; - + mbedtls_sha1_sw_init(&ctx_sw); mbedtls_sha1_sw_starts(&ctx_sw); mbedtls_sha1_sw_finish(&ctx_sw, output); mbedtls_sha1_sw_free(&ctx_sw); } + + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -128,8 +114,9 @@ void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[6 void mbedtls_sha256_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha256_hw_free(crypto_sha_context *ctx) @@ -138,20 +125,18 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) return; } - crypto_zeroize(ctx, sizeof(crypto_sha_context)); -} + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; -void mbedtls_sha256_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; + /* Uninit crypto module */ + crypto_uninit(); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; @@ -159,10 +144,10 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) ctx->is224_384 = is224; SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP, 0); - - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; - + return; } @@ -178,17 +163,16 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224_384 ? 28 : 32); - - CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha256_sw_context ctx_sw; - + mbedtls_sha256_sw_init(&ctx_sw); mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224_384); mbedtls_sha256_sw_finish(&ctx_sw, output); mbedtls_sha256_sw_free(&ctx_sw); } + + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -205,8 +189,9 @@ void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data void mbedtls_sha512_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha512_hw_free(crypto_sha_context *ctx) @@ -215,20 +200,18 @@ void mbedtls_sha512_hw_free(crypto_sha_context *ctx) return; } - crypto_zeroize(ctx, sizeof(crypto_sha_context)); -} - -void mbedtls_sha512_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; + + /* Uninit crypto module */ + crypto_uninit(); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 128; @@ -236,10 +219,10 @@ void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384) ctx->is224_384 = is384; SHA_Open(is384 ? SHA_MODE_SHA384 : SHA_MODE_SHA512, SHA_NO_SWAP, 0); - - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk; - + return; } @@ -255,17 +238,16 @@ void mbedtls_sha512_hw_finish(crypto_sha_context *ctx, unsigned char output[64]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224_384 ? 48 : 64); - - CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha512_sw_context ctx_sw; - + mbedtls_sha512_sw_init(&ctx_sw); mbedtls_sha512_sw_starts(&ctx_sw, ctx->is224_384); mbedtls_sha512_sw_finish(&ctx_sw, output); mbedtls_sha512_sw_free(&ctx_sw); } + + CRPT->HMAC_CTL |= CRPT_HMAC_CTL_STOP_Msk; } void mbedtls_sha512_hw_process(crypto_sha_context *ctx, const unsigned char data[128]) @@ -284,7 +266,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size if (ilen == 0) { return; } - + size_t fill = ctx->blocksize - ctx->buffer_left; ctx->total += (uint32_t) ilen; @@ -299,7 +281,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size ctx->buffer_left = 0; } } - + while (ilen > ctx->blocksize) { crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0); input += ctx->blocksize; @@ -318,17 +300,14 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input // 1. Last block which may be incomplete // 2. Non-last block which is complete MBED_ASSERT(islast || ilen == ctx->blocksize); - + const unsigned char *in_pos = input; int rmn = ilen; uint32_t sha_ctl_start = (CRPT->HMAC_CTL & ~(CRPT_HMAC_CTL_DMALAST_Msk | CRPT_HMAC_CTL_DMAEN_Msk | CRPT_HMAC_CTL_HMACEN_Msk)) | CRPT_HMAC_CTL_START_Msk; uint32_t sha_opmode = (CRPT->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; - uint32_t DGST0_old = 0, DGST1_old = 0, DGST2_old = 0, DGST3_old = 0, DGST4_old = 0, DGST5_old = 0, DGST6_old = 0, DGST7_old = 0, - DGST8_old = 0, DGST9_old = 0, DGST10_old = 0, DGST11_old = 0, DGST12_old = 0, DGST13_old = 0, DGST14_old = 0, DGST15_old = 0; + uint32_t DGSTs[16] = { 0 }; while (rmn > 0) { - CRPT->HMAC_CTL = sha_ctl_start; - uint32_t data = nu_get32_be(in_pos); if (rmn <= 4) { // Last word of a (in)complete block if (islast) { @@ -338,93 +317,112 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input } CRPT->HMAC_DMACNT = lastblock_size; CRPT->HMAC_CTL = sha_ctl_start | CRPT_HMAC_CTL_DMALAST_Msk; - } - else { + } else { switch (sha_opmode) { - case SHA_MODE_SHA512: - DGST15_old = CRPT->HMAC_DGST[15]; - DGST14_old = CRPT->HMAC_DGST[14]; - DGST13_old = CRPT->HMAC_DGST[13]; - DGST12_old = CRPT->HMAC_DGST[12]; - case SHA_MODE_SHA384: - DGST11_old = CRPT->HMAC_DGST[11]; - DGST10_old = CRPT->HMAC_DGST[10]; - DGST9_old = CRPT->HMAC_DGST[9]; - DGST8_old = CRPT->HMAC_DGST[8]; - case SHA_MODE_SHA256: - DGST7_old = CRPT->HMAC_DGST[7]; - case SHA_MODE_SHA224: - DGST5_old = CRPT->HMAC_DGST[5]; - DGST6_old = CRPT->HMAC_DGST[6]; - case SHA_MODE_SHA1: - DGST0_old = CRPT->HMAC_DGST[0]; - DGST1_old = CRPT->HMAC_DGST[1]; - DGST2_old = CRPT->HMAC_DGST[2]; - DGST3_old = CRPT->HMAC_DGST[3]; - DGST4_old = CRPT->HMAC_DGST[4]; + case SHA_MODE_SHA512: + DGSTs[12] = CRPT->HMAC_DGST[12]; + DGSTs[13] = CRPT->HMAC_DGST[13]; + DGSTs[14] = CRPT->HMAC_DGST[14]; + DGSTs[15] = CRPT->HMAC_DGST[15]; + case SHA_MODE_SHA384: + DGSTs[8] = CRPT->HMAC_DGST[8]; + DGSTs[9] = CRPT->HMAC_DGST[9]; + DGSTs[10] = CRPT->HMAC_DGST[10]; + DGSTs[11] = CRPT->HMAC_DGST[11]; + case SHA_MODE_SHA256: + DGSTs[7] = CRPT->HMAC_DGST[7]; + case SHA_MODE_SHA224: + DGSTs[5] = CRPT->HMAC_DGST[5]; + DGSTs[6] = CRPT->HMAC_DGST[6]; + case SHA_MODE_SHA1: + DGSTs[0] = CRPT->HMAC_DGST[0]; + DGSTs[1] = CRPT->HMAC_DGST[1]; + DGSTs[2] = CRPT->HMAC_DGST[2]; + DGSTs[3] = CRPT->HMAC_DGST[3]; + DGSTs[4] = CRPT->HMAC_DGST[4]; } CRPT->HMAC_CTL = sha_ctl_start; } - } - else { // Non-last word of a complete block + } else { // Non-last word of a complete block CRPT->HMAC_CTL = sha_ctl_start; } while (! (CRPT->HMAC_STS & CRPT_HMAC_STS_DATINREQ_Msk)); CRPT->HMAC_DATIN = data; - + in_pos += 4; rmn -= 4; } - + if (islast) { // Finish of last block while (CRPT->HMAC_STS & CRPT_HMAC_STS_BUSY_Msk); - } - else { // Finish of non-last block - // No H/W flag to indicate finish of non-last block process. - // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement. + } else { // Finish of non-last block + /* SHA accelerator doesn't export a flag to indicate non-last block process has finished. + * Per designer, if the digest (SHA_DGSTx) code changes after the last word of the block is input, + * this indicates the non-last block process has finished. + * + * There is a rare case that two digest codes are the same for + * two non-last block processes in a row. + * To address it, we use a count-down timer to detect it. + * As the count-down timer expires, we see it as finished. + */ int isfinish = 0; + struct nu_countdown_ctx_s ctx; + + // Set up 2s timeout + nu_countdown_init(&ctx, 2000*1000); while (! isfinish) { switch (sha_opmode) { - case SHA_MODE_SHA512: - if (DGST12_old != CRPT->HMAC_DGST[12] || DGST13_old != CRPT->HMAC_DGST[13] || DGST14_old != CRPT->HMAC_DGST[14] || - DGST15_old != CRPT->HMAC_DGST[15]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA384: - if (DGST8_old != CRPT->HMAC_DGST[8] || DGST9_old != CRPT->HMAC_DGST[9] || DGST10_old != CRPT->HMAC_DGST[10] || - DGST11_old != CRPT->HMAC_DGST[11]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA256: - if (DGST7_old != CRPT->HMAC_DGST[7]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA224: - if (DGST5_old != CRPT->HMAC_DGST[5] || DGST6_old != CRPT->HMAC_DGST[6]) { - isfinish = 1; - break; - } - case SHA_MODE_SHA1: - if (DGST0_old != CRPT->HMAC_DGST[0] || DGST1_old != CRPT->HMAC_DGST[1] || DGST2_old != CRPT->HMAC_DGST[2] || - DGST3_old != CRPT->HMAC_DGST[3] || DGST4_old != CRPT->HMAC_DGST[4]) { - isfinish = 1; - break; - } + case SHA_MODE_SHA512: + if (DGSTs[12] != CRPT->HMAC_DGST[12] || DGSTs[13] != CRPT->HMAC_DGST[13] || DGSTs[14] != CRPT->HMAC_DGST[14] || + DGSTs[15] != CRPT->HMAC_DGST[15]) { + isfinish = 1; + break; + } + case SHA_MODE_SHA384: + if (DGSTs[8] != CRPT->HMAC_DGST[8] || DGSTs[9] != CRPT->HMAC_DGST[9] || DGSTs[10] != CRPT->HMAC_DGST[10] || + DGSTs[11] != CRPT->HMAC_DGST[11]) { + isfinish = 1; + break; + } + case SHA_MODE_SHA256: + if (DGSTs[7] != CRPT->HMAC_DGST[7]) { + isfinish = 1; + break; + } + case SHA_MODE_SHA224: + if (DGSTs[5] != CRPT->HMAC_DGST[5] || DGSTs[6] != CRPT->HMAC_DGST[6]) { + isfinish = 1; + break; + } + case SHA_MODE_SHA1: + if (DGSTs[0] != CRPT->HMAC_DGST[0] || DGSTs[1] != CRPT->HMAC_DGST[1] || DGSTs[2] != CRPT->HMAC_DGST[2] || + DGSTs[3] != CRPT->HMAC_DGST[3] || DGSTs[4] != CRPT->HMAC_DGST[4]) { + isfinish = 1; + break; + } + } + + if (nu_countdown_expired(&ctx)) { + // We may meet a rare case that the current digest code and the previous one are the same. + isfinish = 1; } } + // Must pair nu_countdown_init with nu_countdown_free in the end + nu_countdown_free(&ctx); } } void crypto_sha_getinternstate(unsigned char output[], size_t olen) { + if (olen & 0x3) { + error("Internal error in SHA alter. SHA internal state size requires to be a multiple of 4 bytes."); + } + uint32_t *in_pos = (uint32_t *) &CRPT->HMAC_DGST[0]; unsigned char *out_pos = output; uint32_t rmn = olen; - + while (rmn) { uint32_t val = *in_pos ++; nu_set32_be(out_pos, val); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h index 527a38e657c..120a8abdf72 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.h @@ -16,13 +16,6 @@ #ifndef MBEDTLS_SHA_ALT_HW_H #define MBEDTLS_SHA_ALT_HW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) #include @@ -35,14 +28,13 @@ extern "C" { /** * \brief SHA context structure */ -typedef struct -{ +typedef struct { uint32_t total; /*!< number of bytes processed */ - unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ + uint8_t buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ uint16_t buffer_left; uint16_t blocksize; /*!< block size */ uint32_t blocksize_mask; /*!< block size mask */ - + int is224_384; /*!< 0 => SHA-256/SHA-512, else SHA-224/384 */ } crypto_sha_context; @@ -51,58 +43,45 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast); void crypto_sha_getinternstate(unsigned char output[], size_t olen); -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha1_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha256_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] ); void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ -#if defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA512_ALT) void mbedtls_sha512_hw_init( crypto_sha_context *ctx ); void mbedtls_sha512_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha512_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384 ); void mbedtls_sha512_hw_update( crypto_sha_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); void mbedtls_sha512_hw_finish( crypto_sha_context *ctx, unsigned char output[64] ); void mbedtls_sha512_hw_process( crypto_sha_context *ctx, const unsigned char data[128] ); #endif /* MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA512_C */ #ifdef __cplusplus } #endif #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C*/ #endif /* sha_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h index 7f0f6c81424..3a4009a23b5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbedtls_device.h @@ -22,9 +22,5 @@ #define MBEDTLS_SHA256_ALT #define MBEDTLS_AES_ALT -#define MBEDTLS_AES_SETKEY_ENC_ALT -#define MBEDTLS_AES_SETKEY_DEC_ALT -#define MBEDTLS_AES_ENCRYPT_ALT -#define MBEDTLS_AES_DECRYPT_ALT #endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index a86c0cb9e39..af52848035a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -21,304 +21,229 @@ * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" #if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) #include - -#include "mbedtls/aes.h" +#include #include "NUC472_442.h" #include "mbed_toolchain.h" #include "mbed_assert.h" - -//static int aes_init_done = 0; - - -#define mbedtls_trace(...) //printf(__VA_ARGS__) +#include "mbed_error.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - - -static uint32_t au32MyAESIV[4] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - -extern volatile int g_AES_done; - -// Must be a multiple of 16 bytes block size -#define MAX_DMA_CHAIN_SIZE (16*6) -static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); -static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4); - -static void dumpHex(const unsigned char au8Data[], int len) -{ - int j; - for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]); - mbedtls_trace("\r\n"); -} - -static void swapInitVector(unsigned char iv[16]) +static void mbedtls_zeroize( void *v, size_t n ) { - unsigned int* piv; - int i; - // iv SWAP - piv = (unsigned int*)iv; - for( i=0; i< 4; i++) - { - *piv = (((*piv) & 0x000000FF) << 24) | - (((*piv) & 0x0000FF00) << 8) | - (((*piv) & 0x00FF0000) >> 8) | - (((*piv) & 0xFF000000) >> 24); - piv++; - } -} - -//volatile void CRYPTO_IRQHandler() -//{ -// if (AES_GET_INT_FLAG()) { -// g_AES_done = 1; -// AES_CLR_INT_FLAG(); -// } -//} - -// AES available channel 0~3 -static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00}; // 0: idle, 1: busy -static int channel_alloc() -{ - int i; - for(i=0; i< (int)sizeof(channel_flag); i++) - { - if( channel_flag[i] == 0x00 ) - { - channel_flag[i] = 0x01; - return i; - } - } - return(-1); -} - -static void channel_free(int i) -{ - if( i >=0 && i < (int)sizeof(channel_flag) ) - channel_flag[i] = 0x00; + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } +/* AES DMA compatible backup buffer if user buffer doesn't meet requirements + * + * AES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * AES DMA buffer size MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + * + */ +#define MAX_DMA_CHAIN_SIZE (16*6) +MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; +MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; void mbedtls_aes_init( mbedtls_aes_context *ctx ) { - int i =-1; - -// sw_mbedtls_aes_init(ctx); -// return; - - mbedtls_trace("=== %s \r\n", __FUNCTION__); memset( ctx, 0, sizeof( mbedtls_aes_context ) ); - - ctx->swapType = AES_IN_OUT_SWAP; - while( (i = channel_alloc()) < 0 ) - { - mbed_assert_internal("No available AES channel", __FILE__, __LINE__); - //osDelay(300); - } - ctx->channel = i; - ctx->iv = au32MyAESIV; - - /* Unlock protected registers */ - SYS_UnlockReg(); - CLK_EnableModuleClock(CRPT_MODULE); - /* Lock protected registers */ - SYS_LockReg(); - - NVIC_EnableIRQ(CRPT_IRQn); - AES_ENABLE_INT(); - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel); } void mbedtls_aes_free( mbedtls_aes_context *ctx ) { - - mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel); - if( ctx == NULL ) return; - /* Unlock protected registers */ -// SYS_UnlockReg(); -// CLK_DisableModuleClock(CRPT_MODULE); - /* Lock protected registers */ -// SYS_LockReg(); - -// NVIC_DisableIRQ(CRPT_IRQn); -// AES_DISABLE_INT(); - channel_free(ctx->channel); mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); } /* * AES key schedule (encryption) */ -#if defined(MBEDTLS_AES_SETKEY_ENC_ALT) int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { unsigned int i; - - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex(key,keybits/8); - - switch( keybits ) - { - case 128: - ctx->keySize = AES_KEY_SIZE_128; - break; - case 192: - ctx->keySize = AES_KEY_SIZE_192; - break; - case 256: - ctx->keySize = AES_KEY_SIZE_256; - break; - default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); - } - + switch( keybits ) { + case 128: + ctx->keySize = AES_KEY_SIZE_128; + break; + case 192: + ctx->keySize = AES_KEY_SIZE_192; + break; + case 256: + ctx->keySize = AES_KEY_SIZE_256; + break; + default : + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } - // key swap - for( i = 0; i < ( keybits >> 5 ); i++ ) - { - ctx->buf[i] = (*(key+i*4) << 24) | - (*(key+1+i*4) << 16) | - (*(key+2+i*4) << 8) | - (*(key+3+i*4) ); - } - AES_SetKey(ctx->channel, ctx->buf, ctx->keySize); - + /* Fetch key byte data in big-endian */ + for( i = 0; i < ( keybits >> 5 ); i++ ) { + ctx->keys[i] = nu_get32_be(key + i * 4); + } return( 0 ); } -#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */ /* * AES key schedule (decryption) */ -#if defined(MBEDTLS_AES_SETKEY_DEC_ALT) int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { int ret; - - mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits); - dumpHex((uint8_t *)key,keybits/8); - + /* Also checks keybits */ if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) - goto exit; + goto exit; exit: - return( ret ); } -#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */ - +/* Do AES encrypt/decrypt with H/W accelerator + * + * NOTE: As input/output buffer doesn't follow constraint of DMA buffer, static allocated + * DMA compatible buffer is used for DMA instead and this needs extra copy. + * + * NOTE: dataSize requires to be: + * 1) Multiple of block size 16 + * 2) <= MAX_DMA_CHAIN_SIZE + */ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16], int dataSize) + const unsigned char *input, + unsigned char *output, size_t dataSize) { - unsigned char* pIn; - unsigned char* pOut; - -// mbedtls_trace("=== %s \r\n", __FUNCTION__); - dumpHex(input,16); - - AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType); - AES_SetInitVect(ctx->channel, ctx->iv); - if( ((uint32_t)input) & 0x03 ) - { - memcpy(au8InputData, input, dataSize); - pIn = au8InputData; - }else{ - pIn = (unsigned char*)input; + const unsigned char* pIn; + unsigned char* pOut; + + MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); + + /* AES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 16-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region + */ + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE, 16)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE, 16))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - if( (((uint32_t)output) & 0x03) || (dataSize%4)) // HW CFB output byte count must be multiple of word - { - pOut = au8OutputData; - } else { - pOut = output; - } - - AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize); - - g_AES_done = 0; - AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT); - while (!g_AES_done); - if( pOut != output ) memcpy(output, au8OutputData, dataSize); - dumpHex(output,16); + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of AES H/W */ + while (! crypto_aes_acquire()); + + /* Init crypto module */ + crypto_init(); + /* Enable AES interrupt */ + AES_ENABLE_INT(); + + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + + /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ + AES_Open(0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); + AES_SetInitVect(0, ctx->iv); + AES_SetKey(0, ctx->keys, ctx->keySize); + + /* AES DMA buffer requirements same as above */ + if (! crypto_dma_buff_compat(input, dataSize, 16)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } else { + pIn = input; + } + /* AES DMA buffer requirements same as above */ + if (! crypto_dma_buff_compat(output, dataSize, 16)) { + pOut = au8OutputData; + } else { + pOut = output; + } + /* Even though AES H/W has limited support for overlapped DMA input/output buffers, + * we still seek to one backup buffer to make them non-overlapped for simplicity. */ + if (crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } + MBED_ASSERT(! crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)); + + AES_SetDMATransfer(0, (uint32_t)pIn, (uint32_t)pOut, dataSize); + + crypto_aes_prestart(); + AES_Start(0, CRYPTO_DMA_ONE_SHOT); + crypto_aes_wait(); + + if( pOut != output ) { + memcpy(output, au8OutputData, dataSize); + } + + /* Save IV for next block */ + ctx->iv[0] = CRPT->AES_FDBCK0; + ctx->iv[1] = CRPT->AES_FDBCK1; + ctx->iv[2] = CRPT->AES_FDBCK2; + ctx->iv[3] = CRPT->AES_FDBCK3; + + /* Disable AES interrupt */ + AES_DISABLE_INT(); + /* Uninit crypto module */ + crypto_uninit(); + + /* Release ownership of AES H/W */ + crypto_aes_release(); } /* * AES-ECB block encryption */ -#if defined(MBEDTLS_AES_ENCRYPT_ALT) void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, 16); - + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_ENCRYPT_ALT */ /* * AES-ECB block decryption */ -#if defined(MBEDTLS_AES_DECRYPT_ALT) void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, 16); - - + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, 16); } -#endif /* MBEDTLS_AES_DECRYPT_ALT */ /* * AES-ECB block encryption/decryption */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) + int mode, + const unsigned char input[16], + unsigned char output[16] ) { - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - ctx->opMode = AES_MODE_ECB; + ctx->opMode = AES_MODE_ECB; if( mode == MBEDTLS_AES_ENCRYPT ) mbedtls_aes_encrypt( ctx, input, output ); else mbedtls_aes_decrypt( ctx, input, output ); - + return( 0 ); } @@ -328,108 +253,135 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * AES-CBC buffer encryption/decryption */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t len, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t len, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - unsigned char temp[16]; int length = len; - int blockChainLen; - mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length); + int blockChainLen; + if( length % 16 ) return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else { - blockChainLen = length; - } - - while( length > 0 ) - { - ctx->opMode = AES_MODE_CBC; - swapInitVector(iv); // iv SWAP - ctx->iv = (uint32_t *)iv; - - if( mode == MBEDTLS_AES_ENCRYPT ) - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, output+blockChainLen-16, 16 ); - }else{ - memcpy( temp, input+blockChainLen-16, 16 ); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); -// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test() - memcpy( iv, temp, 16 ); - } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - + + ctx->opMode = AES_MODE_CBC; + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + } + else { + ctx->encDec = 0; } + + while( length > 0 ) { + blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; + __nvt_aes_crypt(ctx, input, output, blockChainLen); + + length -= blockChainLen; + input += blockChainLen; + output += blockChainLen; + } + + /* Save IV for next block cipher */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + return( 0 ); } #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) -/* - * AES-CFB128 buffer encryption/decryption - */ -/* Support partial block encryption/decryption */ -static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { int c; size_t n = *iv_off; - unsigned char iv_tmp[16]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); - if( mode == MBEDTLS_AES_DECRYPT ) - { - while( length-- ) - { - if( n == 0) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); - iv[n] = (unsigned char) c; + + /* First incomplete block */ + if (n % 16) { + while (n && length) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } n = ( n + 1 ) & 0x0F; + length --; } } - else - { - while( length-- ) - { - if( n == 0 ) - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); - else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode - { - memcpy(iv_tmp, iv, n); - mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv ); - memcpy(iv, iv_tmp, n); - } - - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + /* Middle complete block(s) */ + size_t block_chain_len = length - (length % 16); + + if (block_chain_len) { + ctx->opMode = AES_MODE_CFB; + if (mode == MBEDTLS_AES_DECRYPT) { + ctx->encDec = 0; + } + else { + ctx->encDec = 1; + } + + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + while (block_chain_len) { + size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; + + __nvt_aes_crypt(ctx, input, output, block_chain_len2); + + input += block_chain_len2; + output += block_chain_len2; + length -= block_chain_len2; + + block_chain_len -= block_chain_len2; + } + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + /* Fetch IV byte data in big-endian */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + } + + /* Last incomplete block */ + if (length) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + while (length --) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } + n = ( n + 1 ) & 0x0F; } } @@ -439,96 +391,21 @@ static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx, return( 0 ); } -int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t len, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) -{ - size_t n = *iv_off; - unsigned char temp[16]; - int length=len; - int blockChainLen; - int remLen=0; - int ivLen; - - mbedtls_trace("=== %s \r\n", __FUNCTION__); - - // proceed: start with partial block by ECB mode first - if( n !=0 ) { - __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output); - input += (16 - n); - output += (16 - n); - length -= (16 - n); - } - - // For address or byte count non-word alignment, go through reserved DMA buffer. - if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) // Must reserved DMA buffer for each block - { - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length ); - } else if(length%4) { // Need reserved DMA buffer once for last chain - blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length ); - } else { // Not need reserved DMA buffer - blockChainLen = length; - } - - // proceed: start with block alignment - while( length > 0 ) - { - - ctx->opMode = AES_MODE_CFB; - - swapInitVector(iv); // iv SWAP - - ctx->iv = (uint32_t *)iv; - remLen = blockChainLen%16; - ivLen = (( remLen > 0) ? remLen: 16 ); - - if( mode == MBEDTLS_AES_DECRYPT ) - { - memcpy(temp, input+blockChainLen - ivLen, ivLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16); - ctx->encDec = 0; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - memcpy(iv,temp, ivLen); - } - else - { - ctx->encDec = 1; - __nvt_aes_crypt(ctx, input, output, blockChainLen); - if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16); - memcpy(iv,output+blockChainLen-ivLen,ivLen); - } - length -= blockChainLen; - input += blockChainLen; - output += blockChainLen; - if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain - } - - *iv_off = remLen; - - return( 0 ); -} - /* * AES-CFB8 buffer encryption/decryption */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { unsigned char c; unsigned char ov[17]; - mbedtls_trace("=== %s \r\n", __FUNCTION__); - while( length-- ) - { + while( length-- ) { memcpy( ov, iv, 16 ); mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); @@ -552,19 +429,17 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * AES-CTR buffer encryption/decryption */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ) + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) { int c, i; size_t n = *nc_off; - mbedtls_trace("=== %s \r\n", __FUNCTION__); - while( length-- ) - { + while( length-- ) { if( n == 0 ) { mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h index d46ef6d16e3..23625b5b67e 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.h @@ -20,17 +20,11 @@ * * This file is part of mbed TLS (https://tls.mbed.org) */ - #ifndef MBEDTLS_AES_ALT_H #define MBEDTLS_AES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/aes.h" -#if defined(MBEDTLS_AES_C) #if defined(MBEDTLS_AES_ALT) // Regular implementation // @@ -40,29 +34,13 @@ extern "C" { /** * \brief AES context structure - * - * \note buf is able to hold 32 extra bytes, which can be used: - * - for alignment purposes if VIA padlock is used, and/or - * - to simplify key expansion in the 256-bit case by - * generating an extra round key */ -typedef struct -{ - uint32_t keySize; - uint32_t encDec; - uint32_t opMode; - uint32_t channel; - uint32_t swapType; - uint32_t *iv; - unsigned char prv_iv[16]; -#if 1 - uint32_t buf[8]; -/* For comparsion with software AES for correctness */ -#else - uint32_t buf[68]; /*!< unaligned data */ - int nr; /*!< number of rounds */ - uint32_t *rk; /*!< AES round keys */ -#endif +typedef struct { + uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ + uint32_t iv[4]; /* IV for next block cipher */ + uint32_t keys[8]; /* Cipher key */ } mbedtls_aes_context; @@ -90,7 +68,7 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ); * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -102,7 +80,7 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); + unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -115,9 +93,9 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, * \return 0 if successful */ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ); + int mode, + const unsigned char input[16], + unsigned char output[16] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -143,11 +121,11 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH */ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) @@ -177,12 +155,12 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** * \brief AES-CFB8 buffer encryption/decryption. @@ -209,11 +187,11 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); #endif /*MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) @@ -240,12 +218,12 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * \return 0 if successful */ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ); + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CTR */ /** @@ -280,6 +258,5 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, #endif /* MBEDTLS_AES_ALT */ -#endif /* MBEDTLS_AES_C */ #endif /* aes_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c deleted file mode 100644 index 7f6646f40b1..00000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.c +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "cmsis.h" -#include "mbed_assert.h" -#include "nu_modutil.h" -#include "nu_bitutil.h" -#include "crypto-misc.h" - -static int crypto_inited = 0; -static int crypto_sha_avail = 1; - -void crypto_init(void) -{ - if (crypto_inited) { - return; - } - crypto_inited = 1; - - CLK_EnableModuleClock(CRPT_MODULE); -} - -/* Implementation that should never be optimized out by the compiler */ -void crypto_zeroize(void *v, size_t n) -{ - volatile unsigned char *p = (unsigned char*) v; - while (n--) { - *p++ = 0; - } -} - -int crypto_sha_acquire(void) -{ - if (crypto_sha_avail) { - crypto_sha_avail = 0; - return 1; - } - else { - return 0; - } - -} - -void crypto_sha_release(void) -{ - if (! crypto_sha_avail) { - crypto_sha_avail = 1; - } -} diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index e4e9fd4023d..2ef63f4b3cb 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -14,33 +14,37 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" #if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include -#include "mbedtls/des.h" -#include "des_alt.h" +#include #include "crypto-misc.h" #include "nu_bitutil.h" #include "mbed_toolchain.h" - -// Must be a multiple of 64-bit block size +#include "mbed_error.h" + +/* DES DMA compatible buffer requirements + * + * DES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * DES DMA buffer size MAXSIZE_DMABUF must be a multiple of 64-bit block size. + * Its value is estimated to trade memory footprint off against performance. + * + */ #define MAXSIZE_DMABUF (8 * 5) -static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4); -static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4); +MBED_ALIGN(4) static uint8_t dmabuf_in[MAXSIZE_DMABUF]; +MBED_ALIGN(4) static uint8_t dmabuf_out[MAXSIZE_DMABUF]; -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output); +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output); void mbedtls_des_init(mbedtls_des_context *ctx) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des_context)); } @@ -55,7 +59,6 @@ void mbedtls_des_free( mbedtls_des_context *ctx ) void mbedtls_des3_init( mbedtls_des3_context *ctx ) { - crypto_init(); memset(ctx, 0, sizeof(mbedtls_des3_context)); } @@ -69,15 +72,16 @@ void mbedtls_des3_free( mbedtls_des3_context *ctx ) } static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; + 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, + 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, + 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, + 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, + 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, + 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, + 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, + 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, + 254 + }; void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE]) { @@ -125,8 +129,7 @@ int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SI #define WEAK_KEY_COUNT 16 -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ +static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = { { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, @@ -168,7 +171,7 @@ int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MB memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE); memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE); - + return 0; } @@ -191,7 +194,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * Triple-DES key schedule (112-bit, encryption) */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 1; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -207,7 +210,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (112-bit, decryption) */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) { ctx->enc = 0; // Keying option 2: K1 and K2 are independent, and K3 = K1. @@ -223,7 +226,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, encryption) */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 1; // Keying option 1: All three keys are independent. @@ -239,7 +242,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * Triple-DES key schedule (168-bit, decryption) */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) { ctx->enc = 0; // Keying option 1: All three keys are independent. @@ -255,8 +258,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * DES-ECB block encryption/decryption */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output); @@ -267,11 +270,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * DES-CBC buffer encryption/decryption */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output); } @@ -281,8 +284,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * 3DES-ECB block encryption/decryption */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) + const unsigned char input[8], + unsigned char output[8] ) { unsigned char iv[8] = {0x00}; return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output); @@ -293,11 +296,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * 3DES-CBC buffer encryption/decryption */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ) { return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output); } @@ -305,103 +308,157 @@ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, -static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, - unsigned char iv[8], const unsigned char *input, unsigned char *output) +static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, + unsigned char iv[8], const unsigned char *input, unsigned char *output) { + if ((keyopt < 1) || (keyopt > 3)) { + error("Key option in DES alter. requires to be 1/2/3."); + } + + if (key == NULL) { + error("Meet null key pointer in DES alter."); + } + + if ((enc != 0) && (enc != 1)) { + error("Enc/dec flag in DES alter. requires to be 0/1."); + } + + if (tdes_opmode & ~(CRPT_TDES_CTL_TMODE_Msk | CRPT_TDES_CTL_OPMODE_Msk)) { + error("Invalid TMODE/OPMODE in DES alter."); + } + if (length % 8) { return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH; } - - // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting. - CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) | - tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos); - // Keying option 1: All three keys are independent. - // Keying option 2: K1 and K2 are independent, and K3 = K1. - // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. - if (keyopt == 1) { - CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk; + if (iv == NULL) { + error("Meet null IV pointer in DES alter."); + } + + if (input == NULL || output == NULL) { + error("Meet null input/output pointer in DES alter."); } - else { - CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk; + + /* DES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 8-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region + */ + if ((! crypto_dma_buff_compat(dmabuf_in, MAXSIZE_DMABUF, 8)) || + (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF, 8))) { + error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - - // Set DES/TDES keys - // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap. - uint32_t val; - volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0)); - val = nu_get32_be(key[0] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[0] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[1] + 4); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 0); - *tdes_key ++ = val; - val = nu_get32_be(key[2] + 4); - *tdes_key ++ = val; + /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of DES H/W */ + while (! crypto_des_acquire()); + + /* Init crypto module */ + crypto_init(); + /* Enable DES interrupt */ + TDES_ENABLE_INT(); + + /* Configure TDES_CTL register + * + * BSP TDES driver supports multiple channels. Just use channel #0. + * + * Relationship of keying option and TDES H/W mode configuration + * 1: All three keys are independent ==> TDES 3-key mode (TMODE=1, 3KEYS=1) + * 2: K1 and K2 are independent, and K3 = K1 ==> TDES 2-key mode (TMODE=1, 3KEYS=0) + * 3: All three keys are identical, i.e. K1 = K2 = K3 ==> DES mode (TMODE=0) + * + * tdes_opmode is combination of TMODE/OPMODE, but TDES_Open I/F requires TMODE/OPMODE to be separate. + * We need to divide tdes_opmode to TMODE and OPMODE. + * + * TDES_IN_OUT_WHL_SWAP lets TDES H/W know input/output data are arranged in below for DMA transfer: + * 1. BE for byte sequence in word + * 2. BE for word sequence in double-word + */ + TDES_Open(0, // Channel number (0~4) + enc, // 0: decode, 1: encode + (tdes_opmode & CRPT_TDES_CTL_TMODE_Msk) ? 1 : 0, // 0: DES, 1: TDES + (keyopt == 1) ? 1 : 0, // 0: TDES 2-key mode, 1: TDES 3-key mode + tdes_opmode & CRPT_TDES_CTL_OPMODE_Msk, // ECB/CBC/CFB/OFB/CTR + TDES_IN_OUT_WHL_SWAP); // TDES_NO_SWAP~TDES_IN_OUT_WHL_SWAP + + /* Set DES/TDES keys + * + * TDES_SetKey requires 3x2 word array. Change 3x8 byte array to 3x2 word array. + */ + unsigned i; + uint32_t keys3x2[3][2]; + for (i = 0; i < 3; i ++ ) { + keys3x2[i][0] = nu_get32_be(key[i] + 0); + keys3x2[i][1] = nu_get32_be(key[i] + 4); + } + TDES_SetKey(0, keys3x2); + uint32_t rmn = length; const unsigned char *in_pos = input; unsigned char *out_pos = output; - - while (rmn) { + + while (rmn > 0) { uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF; - + uint32_t ivh, ivl; ivh = nu_get32_be(iv); ivl = nu_get32_be(iv + 4); TDES_SetInitVect(0, ivh, ivl); - + memcpy(dmabuf_in, in_pos, data_len); - + + /* We always use DMA backup buffers, which are guaranteed to be non-overlapped. */ TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len); - - // Start enc/dec. - // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting. - CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos); - while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk); - + + crypto_des_prestart(); + TDES_Start(0, CRYPTO_DMA_ONE_SHOT); + crypto_des_wait(); + memcpy(out_pos, dmabuf_out, data_len); in_pos += data_len; out_pos += data_len; rmn -= data_len; - + // Update IV for next block enc/dec in next function call switch (tdes_opmode) { - case DES_MODE_OFB: - case TDES_MODE_OFB: { - // OFB: IV (enc/dec) = output block XOR input block - uint32_t lbh, lbl; - // Last block of input data - lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); - lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); - // Last block of output data - ivh = nu_get32_be(dmabuf_out + 4); - ivl = nu_get32_be(dmabuf_out + 0); - ivh = ivh ^ lbh; - ivl = ivl ^ lbl; - nu_set32_be(iv + 4, ivh); - nu_set32_be(iv, ivl); - break; - } - case DES_MODE_CBC: - case DES_MODE_CFB: - case TDES_MODE_CBC: - case TDES_MODE_CFB: { - // CBC/CFB: IV (enc) = output block - // IV (dec) = input block - if (enc) { - memcpy(iv, dmabuf_out + data_len - 8, 8); - } - else { - memcpy(iv, dmabuf_in + data_len - 8, 8); - } + case DES_MODE_OFB: + case TDES_MODE_OFB: { + // OFB: IV (enc/dec) = output block XOR input block + uint32_t lbh, lbl; + // Last block of input data + lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4); + lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0); + // Last block of output data + ivh = nu_get32_be(dmabuf_out + 4); + ivl = nu_get32_be(dmabuf_out + 0); + ivh = ivh ^ lbh; + ivl = ivl ^ lbl; + nu_set32_be(iv + 4, ivh); + nu_set32_be(iv, ivl); + break; + } + case DES_MODE_CBC: + case DES_MODE_CFB: + case TDES_MODE_CBC: + case TDES_MODE_CFB: { + // CBC/CFB: IV (enc) = output block + // IV (dec) = input block + if (enc) { + memcpy(iv, dmabuf_out + data_len - 8, 8); + } else { + memcpy(iv, dmabuf_in + data_len - 8, 8); } } + } } + + /* Disable DES interrupt */ + TDES_DISABLE_INT(); + /* Uninit crypto module */ + crypto_uninit(); + + /* Release ownership of DES H/W */ + crypto_des_release(); return 0; } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h index b783889d538..09b693c524a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.h @@ -13,23 +13,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef MBEDTLS_DES_ALT_H #define MBEDTLS_DES_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/des.h" -#if defined(MBEDTLS_DES_C) #if defined(MBEDTLS_DES_ALT) #include #include -#include "des.h" -#include "des_alt_sw.h" #ifdef __cplusplus extern "C" { @@ -38,19 +31,19 @@ extern "C" { /** * \brief DES context structure */ -typedef struct -{ - int enc; /*!< 0: dec, 1: enc */ - uint16_t keyopt; - uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ +typedef struct { + int enc; /* 0: dec, 1: enc */ + uint16_t keyopt; /* 1: All three keys are independent. + * 2: K1 and K2 are independent, and K3 = K1. + * 3: All three keys are identical, i.e. K1 = K2 = K3. */ + uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /* 3DES keys */ } mbedtls_des_context; /** * \brief Triple-DES context structure */ -typedef struct -{ +typedef struct { int enc; /*!< 0: dec, 1: enc */ uint16_t keyopt; uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */ @@ -145,7 +138,7 @@ int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MB * \return 0 */ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (112-bit, decryption) @@ -156,7 +149,7 @@ int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); /** * \brief Triple-DES key schedule (168-bit, encryption) @@ -167,7 +160,7 @@ int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief Triple-DES key schedule (168-bit, decryption) @@ -178,7 +171,7 @@ int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx, * \return 0 */ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); /** * \brief DES-ECB block encryption/decryption @@ -190,8 +183,8 @@ int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx, * \return 0 if successful */ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -213,11 +206,11 @@ int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx, * \param output buffer holding the output data */ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -230,8 +223,8 @@ int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx, * \return 0 if successful */ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); + const unsigned char input[8], + unsigned char output[8] ); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -255,11 +248,11 @@ int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx, * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH */ int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output ); #endif /* MBEDTLS_CIPHER_MODE_CBC */ /** @@ -277,6 +270,5 @@ void mbedtls_des_setkey( uint32_t SK[32], #endif #endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ #endif /* des_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c deleted file mode 100644 index 1e51151c862..00000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * FIPS-46-3 compliant Triple-DES implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -/* - * DES, on which TDES is based, was originally designed by Horst Feistel - * at IBM in 1974, and was adopted as a standard by NIST (formerly NBS). - * - * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf - */ - -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include "mbedtls/des.h" - -#include - -/* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - -/* - * 32-bit integer manipulation macros (big endian) - */ -#ifndef GET_UINT32_BE -#define GET_UINT32_BE(n,b,i) \ -{ \ - (n) = ( (uint32_t) (b)[(i) ] << 24 ) \ - | ( (uint32_t) (b)[(i) + 1] << 16 ) \ - | ( (uint32_t) (b)[(i) + 2] << 8 ) \ - | ( (uint32_t) (b)[(i) + 3] ); \ -} -#endif - -#ifndef PUT_UINT32_BE -#define PUT_UINT32_BE(n,b,i) \ -{ \ - (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ - (b)[(i) + 3] = (unsigned char) ( (n) ); \ -} -#endif - -/* - * Expanded DES S-boxes - */ -static const uint32_t SB1[64] = -{ - 0x01010400, 0x00000000, 0x00010000, 0x01010404, - 0x01010004, 0x00010404, 0x00000004, 0x00010000, - 0x00000400, 0x01010400, 0x01010404, 0x00000400, - 0x01000404, 0x01010004, 0x01000000, 0x00000004, - 0x00000404, 0x01000400, 0x01000400, 0x00010400, - 0x00010400, 0x01010000, 0x01010000, 0x01000404, - 0x00010004, 0x01000004, 0x01000004, 0x00010004, - 0x00000000, 0x00000404, 0x00010404, 0x01000000, - 0x00010000, 0x01010404, 0x00000004, 0x01010000, - 0x01010400, 0x01000000, 0x01000000, 0x00000400, - 0x01010004, 0x00010000, 0x00010400, 0x01000004, - 0x00000400, 0x00000004, 0x01000404, 0x00010404, - 0x01010404, 0x00010004, 0x01010000, 0x01000404, - 0x01000004, 0x00000404, 0x00010404, 0x01010400, - 0x00000404, 0x01000400, 0x01000400, 0x00000000, - 0x00010004, 0x00010400, 0x00000000, 0x01010004 -}; - -static const uint32_t SB2[64] = -{ - 0x80108020, 0x80008000, 0x00008000, 0x00108020, - 0x00100000, 0x00000020, 0x80100020, 0x80008020, - 0x80000020, 0x80108020, 0x80108000, 0x80000000, - 0x80008000, 0x00100000, 0x00000020, 0x80100020, - 0x00108000, 0x00100020, 0x80008020, 0x00000000, - 0x80000000, 0x00008000, 0x00108020, 0x80100000, - 0x00100020, 0x80000020, 0x00000000, 0x00108000, - 0x00008020, 0x80108000, 0x80100000, 0x00008020, - 0x00000000, 0x00108020, 0x80100020, 0x00100000, - 0x80008020, 0x80100000, 0x80108000, 0x00008000, - 0x80100000, 0x80008000, 0x00000020, 0x80108020, - 0x00108020, 0x00000020, 0x00008000, 0x80000000, - 0x00008020, 0x80108000, 0x00100000, 0x80000020, - 0x00100020, 0x80008020, 0x80000020, 0x00100020, - 0x00108000, 0x00000000, 0x80008000, 0x00008020, - 0x80000000, 0x80100020, 0x80108020, 0x00108000 -}; - -static const uint32_t SB3[64] = -{ - 0x00000208, 0x08020200, 0x00000000, 0x08020008, - 0x08000200, 0x00000000, 0x00020208, 0x08000200, - 0x00020008, 0x08000008, 0x08000008, 0x00020000, - 0x08020208, 0x00020008, 0x08020000, 0x00000208, - 0x08000000, 0x00000008, 0x08020200, 0x00000200, - 0x00020200, 0x08020000, 0x08020008, 0x00020208, - 0x08000208, 0x00020200, 0x00020000, 0x08000208, - 0x00000008, 0x08020208, 0x00000200, 0x08000000, - 0x08020200, 0x08000000, 0x00020008, 0x00000208, - 0x00020000, 0x08020200, 0x08000200, 0x00000000, - 0x00000200, 0x00020008, 0x08020208, 0x08000200, - 0x08000008, 0x00000200, 0x00000000, 0x08020008, - 0x08000208, 0x00020000, 0x08000000, 0x08020208, - 0x00000008, 0x00020208, 0x00020200, 0x08000008, - 0x08020000, 0x08000208, 0x00000208, 0x08020000, - 0x00020208, 0x00000008, 0x08020008, 0x00020200 -}; - -static const uint32_t SB4[64] = -{ - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802080, 0x00800081, 0x00800001, 0x00002001, - 0x00000000, 0x00802000, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00800080, 0x00800001, - 0x00000001, 0x00002000, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002001, 0x00002080, - 0x00800081, 0x00000001, 0x00002080, 0x00800080, - 0x00002000, 0x00802080, 0x00802081, 0x00000081, - 0x00800080, 0x00800001, 0x00802000, 0x00802081, - 0x00000081, 0x00000000, 0x00000000, 0x00802000, - 0x00002080, 0x00800080, 0x00800081, 0x00000001, - 0x00802001, 0x00002081, 0x00002081, 0x00000080, - 0x00802081, 0x00000081, 0x00000001, 0x00002000, - 0x00800001, 0x00002001, 0x00802080, 0x00800081, - 0x00002001, 0x00002080, 0x00800000, 0x00802001, - 0x00000080, 0x00800000, 0x00002000, 0x00802080 -}; - -static const uint32_t SB5[64] = -{ - 0x00000100, 0x02080100, 0x02080000, 0x42000100, - 0x00080000, 0x00000100, 0x40000000, 0x02080000, - 0x40080100, 0x00080000, 0x02000100, 0x40080100, - 0x42000100, 0x42080000, 0x00080100, 0x40000000, - 0x02000000, 0x40080000, 0x40080000, 0x00000000, - 0x40000100, 0x42080100, 0x42080100, 0x02000100, - 0x42080000, 0x40000100, 0x00000000, 0x42000000, - 0x02080100, 0x02000000, 0x42000000, 0x00080100, - 0x00080000, 0x42000100, 0x00000100, 0x02000000, - 0x40000000, 0x02080000, 0x42000100, 0x40080100, - 0x02000100, 0x40000000, 0x42080000, 0x02080100, - 0x40080100, 0x00000100, 0x02000000, 0x42080000, - 0x42080100, 0x00080100, 0x42000000, 0x42080100, - 0x02080000, 0x00000000, 0x40080000, 0x42000000, - 0x00080100, 0x02000100, 0x40000100, 0x00080000, - 0x00000000, 0x40080000, 0x02080100, 0x40000100 -}; - -static const uint32_t SB6[64] = -{ - 0x20000010, 0x20400000, 0x00004000, 0x20404010, - 0x20400000, 0x00000010, 0x20404010, 0x00400000, - 0x20004000, 0x00404010, 0x00400000, 0x20000010, - 0x00400010, 0x20004000, 0x20000000, 0x00004010, - 0x00000000, 0x00400010, 0x20004010, 0x00004000, - 0x00404000, 0x20004010, 0x00000010, 0x20400010, - 0x20400010, 0x00000000, 0x00404010, 0x20404000, - 0x00004010, 0x00404000, 0x20404000, 0x20000000, - 0x20004000, 0x00000010, 0x20400010, 0x00404000, - 0x20404010, 0x00400000, 0x00004010, 0x20000010, - 0x00400000, 0x20004000, 0x20000000, 0x00004010, - 0x20000010, 0x20404010, 0x00404000, 0x20400000, - 0x00404010, 0x20404000, 0x00000000, 0x20400010, - 0x00000010, 0x00004000, 0x20400000, 0x00404010, - 0x00004000, 0x00400010, 0x20004010, 0x00000000, - 0x20404000, 0x20000000, 0x00400010, 0x20004010 -}; - -static const uint32_t SB7[64] = -{ - 0x00200000, 0x04200002, 0x04000802, 0x00000000, - 0x00000800, 0x04000802, 0x00200802, 0x04200800, - 0x04200802, 0x00200000, 0x00000000, 0x04000002, - 0x00000002, 0x04000000, 0x04200002, 0x00000802, - 0x04000800, 0x00200802, 0x00200002, 0x04000800, - 0x04000002, 0x04200000, 0x04200800, 0x00200002, - 0x04200000, 0x00000800, 0x00000802, 0x04200802, - 0x00200800, 0x00000002, 0x04000000, 0x00200800, - 0x04000000, 0x00200800, 0x00200000, 0x04000802, - 0x04000802, 0x04200002, 0x04200002, 0x00000002, - 0x00200002, 0x04000000, 0x04000800, 0x00200000, - 0x04200800, 0x00000802, 0x00200802, 0x04200800, - 0x00000802, 0x04000002, 0x04200802, 0x04200000, - 0x00200800, 0x00000000, 0x00000002, 0x04200802, - 0x00000000, 0x00200802, 0x04200000, 0x00000800, - 0x04000002, 0x04000800, 0x00000800, 0x00200002 -}; - -static const uint32_t SB8[64] = -{ - 0x10001040, 0x00001000, 0x00040000, 0x10041040, - 0x10000000, 0x10001040, 0x00000040, 0x10000000, - 0x00040040, 0x10040000, 0x10041040, 0x00041000, - 0x10041000, 0x00041040, 0x00001000, 0x00000040, - 0x10040000, 0x10000040, 0x10001000, 0x00001040, - 0x00041000, 0x00040040, 0x10040040, 0x10041000, - 0x00001040, 0x00000000, 0x00000000, 0x10040040, - 0x10000040, 0x10001000, 0x00041040, 0x00040000, - 0x00041040, 0x00040000, 0x10041000, 0x00001000, - 0x00000040, 0x10040040, 0x00001000, 0x00041040, - 0x10001000, 0x00000040, 0x10000040, 0x10040000, - 0x10040040, 0x10000000, 0x00040000, 0x10001040, - 0x00000000, 0x10041040, 0x00040040, 0x10000040, - 0x10040000, 0x10001000, 0x10001040, 0x00000000, - 0x10041040, 0x00041000, 0x00041000, 0x00001040, - 0x00001040, 0x00040040, 0x10000000, 0x10041000 -}; - -/* - * PC1: left and right halves bit-swap - */ -static const uint32_t LHs[16] = -{ - 0x00000000, 0x00000001, 0x00000100, 0x00000101, - 0x00010000, 0x00010001, 0x00010100, 0x00010101, - 0x01000000, 0x01000001, 0x01000100, 0x01000101, - 0x01010000, 0x01010001, 0x01010100, 0x01010101 -}; - -static const uint32_t RHs[16] = -{ - 0x00000000, 0x01000000, 0x00010000, 0x01010000, - 0x00000100, 0x01000100, 0x00010100, 0x01010100, - 0x00000001, 0x01000001, 0x00010001, 0x01010001, - 0x00000101, 0x01000101, 0x00010101, 0x01010101, -}; - -/* - * Initial Permutation macro - */ -#define DES_IP(X,Y) \ -{ \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T; \ - X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF; \ -} - -/* - * Final Permutation macro - */ -#define DES_FP(X,Y) \ -{ \ - X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF; \ - T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T; \ - Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF; \ - T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \ - T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \ - T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \ - T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \ -} - -/* - * DES round macro - */ -#define DES_ROUND(X,Y) \ -{ \ - T = *SK++ ^ X; \ - Y ^= SB8[ (T ) & 0x3F ] ^ \ - SB6[ (T >> 8) & 0x3F ] ^ \ - SB4[ (T >> 16) & 0x3F ] ^ \ - SB2[ (T >> 24) & 0x3F ]; \ - \ - T = *SK++ ^ ((X << 28) | (X >> 4)); \ - Y ^= SB7[ (T ) & 0x3F ] ^ \ - SB5[ (T >> 8) & 0x3F ] ^ \ - SB3[ (T >> 16) & 0x3F ] ^ \ - SB1[ (T >> 24) & 0x3F ]; \ -} - -#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; } - -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) ); -} - -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ) -{ - memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) ); -} - -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ) -{ - if( ctx == NULL ) - return; - - mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) ); -} - -static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8, - 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44, - 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81, - 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112, - 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140, - 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168, - 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196, - 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224, - 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253, - 254 }; - -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - key[i] = odd_parity_table[key[i] / 2]; -} - -/* - * Check the given key's parity, returns 1 on failure, 0 on SUCCESS - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ ) - if( key[i] != odd_parity_table[key[i] / 2] ) - return( 1 ); - - return( 0 ); -} - -/* - * Table of weak and semi-weak keys - * - * Source: http://en.wikipedia.org/wiki/Weak_key - * - * Weak: - * Alternating ones + zeros (0x0101010101010101) - * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE) - * '0xE0E0E0E0F1F1F1F1' - * '0x1F1F1F1F0E0E0E0E' - * - * Semi-weak: - * 0x011F011F010E010E and 0x1F011F010E010E01 - * 0x01E001E001F101F1 and 0xE001E001F101F101 - * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01 - * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E - * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E - * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1 - * - */ - -#define WEAK_KEY_COUNT 16 - -static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] = -{ - { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, - { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, - { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, - { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 }, - - { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E }, - { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 }, - { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 }, - { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 }, - { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE }, - { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 }, - { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 }, - { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E }, - { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE }, - { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E }, - { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE }, - { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 } -}; - -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - for( i = 0; i < WEAK_KEY_COUNT; i++ ) - if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 ) - return( 1 ); - - return( 0 ); -} - -void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - uint32_t X, Y, T; - - GET_UINT32_BE( X, key, 0 ); - GET_UINT32_BE( Y, key, 4 ); - - /* - * Permuted Choice 1 - */ - T = ((Y >> 4) ^ X) & 0x0F0F0F0F; X ^= T; Y ^= (T << 4); - T = ((Y ) ^ X) & 0x10101010; X ^= T; Y ^= (T ); - - X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2) - | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] ) - | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6) - | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4); - - Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2) - | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] ) - | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6) - | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4); - - X &= 0x0FFFFFFF; - Y &= 0x0FFFFFFF; - - /* - * calculate subkeys - */ - for( i = 0; i < 16; i++ ) - { - if( i < 2 || i == 8 || i == 15 ) - { - X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF; - Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF; - } - else - { - X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF; - Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF; - } - - *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000) - | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000) - | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000) - | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000) - | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000) - | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000) - | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400) - | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100) - | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010) - | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004) - | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001); - - *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000) - | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000) - | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000) - | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000) - | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000) - | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000) - | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000) - | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400) - | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100) - | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011) - | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002); - } -} - -/* - * DES key schedule (56-bit, encryption) - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - mbedtls_des_setkey( ctx->sk, key ); - - return( 0 ); -} - -/* - * DES key schedule (56-bit, decryption) - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ) -{ - int i; - - mbedtls_des_setkey( ctx->sk, key ); - - for( i = 0; i < 16; i += 2 ) - { - SWAP( ctx->sk[i ], ctx->sk[30 - i] ); - SWAP( ctx->sk[i + 1], ctx->sk[31 - i] ); - } - - return( 0 ); -} - -static void des3_set2key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - - for( i = 0; i < 32; i += 2 ) - { - dsk[i ] = esk[30 - i]; - dsk[i + 1] = esk[31 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - esk[i + 64] = esk[i ]; - esk[i + 65] = esk[i + 1]; - - dsk[i + 64] = dsk[i ]; - dsk[i + 65] = dsk[i + 1]; - } -} - -/* - * Triple-DES key schedule (112-bit, encryption) - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (112-bit, decryption) - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ) -{ - uint32_t sk[96]; - - des3_set2key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -static void des3_set3key( uint32_t esk[96], - uint32_t dsk[96], - const unsigned char key[24] ) -{ - int i; - - mbedtls_des_setkey( esk, key ); - mbedtls_des_setkey( dsk + 32, key + 8 ); - mbedtls_des_setkey( esk + 64, key + 16 ); - - for( i = 0; i < 32; i += 2 ) - { - dsk[i ] = esk[94 - i]; - dsk[i + 1] = esk[95 - i]; - - esk[i + 32] = dsk[62 - i]; - esk[i + 33] = dsk[63 - i]; - - dsk[i + 64] = esk[30 - i]; - dsk[i + 65] = esk[31 - i]; - } -} - -/* - * Triple-DES key schedule (168-bit, encryption) - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( ctx->sk, sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * Triple-DES key schedule (168-bit, decryption) - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ) -{ - uint32_t sk[96]; - - des3_set3key( sk, ctx->sk, key ); - mbedtls_zeroize( sk, sizeof( sk ) ); - - return( 0 ); -} - -/* - * DES-ECB block encryption/decryption - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * DES-CBC buffer encryption/decryption - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { - memcpy( temp, input, 8 ); - mbedtls_des_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/* - * 3DES-ECB block encryption/decryption - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ) -{ - int i; - uint32_t X, Y, T, *SK; - - SK = ctx->sk; - - GET_UINT32_BE( X, input, 0 ); - GET_UINT32_BE( Y, input, 4 ); - - DES_IP( X, Y ); - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( X, Y ); - DES_ROUND( Y, X ); - } - - for( i = 0; i < 8; i++ ) - { - DES_ROUND( Y, X ); - DES_ROUND( X, Y ); - } - - DES_FP( Y, X ); - - PUT_UINT32_BE( Y, output, 0 ); - PUT_UINT32_BE( X, output, 4 ); - - return( 0 ); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/* - * 3DES-CBC buffer encryption/decryption - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ) -{ - int i; - unsigned char temp[8]; - - if( length % 8 ) - return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH ); - - if( mode == MBEDTLS_DES_ENCRYPT ) - { - while( length > 0 ) - { - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( input[i] ^ iv[i] ); - - mbedtls_des3_sw_crypt_ecb( ctx, output, output ); - memcpy( iv, output, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - else /* MBEDTLS_DES_DECRYPT */ - { - while( length > 0 ) - { - memcpy( temp, input, 8 ); - mbedtls_des3_sw_crypt_ecb( ctx, input, output ); - - for( i = 0; i < 8; i++ ) - output[i] = (unsigned char)( output[i] ^ iv[i] ); - - memcpy( iv, temp, 8 ); - - input += 8; - output += 8; - length -= 8; - } - } - - return( 0 ); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h deleted file mode 100644 index d42aa2ba050..00000000000 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt_sw.h +++ /dev/null @@ -1,283 +0,0 @@ -/** - * \file des.h - * - * \brief DES block cipher - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of mbed TLS (https://tls.mbed.org) - */ -#ifndef MBEDTLS_DES_ALT_SW_H -#define MBEDTLS_DES_ALT_SW_H - -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_DES_C) -#if defined(MBEDTLS_DES_ALT) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief DES context structure - */ -typedef struct -{ - uint32_t sk[32]; /*!< DES subkeys */ -} -mbedtls_des_sw_context; - -/** - * \brief Triple-DES context structure - */ -typedef struct -{ - uint32_t sk[96]; /*!< 3DES subkeys */ -} -mbedtls_des3_sw_context; - -/** - * \brief Initialize DES context - * - * \param ctx DES context to be initialized - */ -void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx ); - -/** - * \brief Clear DES context - * - * \param ctx DES context to be cleared - */ -void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx ); - -/** - * \brief Initialize Triple-DES context - * - * \param ctx DES3 context to be initialized - */ -void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Clear Triple-DES context - * - * \param ctx DES3 context to be cleared - */ -void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx ); - -/** - * \brief Set key parity on the given key to odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - */ -void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key parity on the given key is odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - * - * \return 0 is parity was ok, 1 if parity was not correct. - */ -int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Check that key is not a weak or semi-weak DES key - * - * \param key 8-byte secret key - * - * \return 0 if no weak key was found, 1 if a weak key was identified. - */ -int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, encryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief DES key schedule (56-bit, decryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - */ -int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -/** - * \brief Triple-DES key schedule (112-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (112-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] ); - -/** - * \brief Triple-DES key schedule (168-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief Triple-DES key schedule (168-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - */ -int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] ); - -/** - * \brief DES-ECB block encryption/decryption - * - * \param ctx DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - */ -int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief 3DES-ECB block encryption/decryption - * - * \param ctx 3DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - */ -int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx, - const unsigned char input[8], - unsigned char output[8] ); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief 3DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx 3DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH - */ -int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output ); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief Internal function for key expansion. - * (Only exposed to allow overriding it, - * see MBEDTLS_DES_SETKEY_ALT) - * - * \param SK Round keys - * \param key Base key - */ -void mbedtls_des_sw_setkey( uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE] ); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_DES_ALT */ -#endif /* MBEDTLS_DES_C */ - -#endif /* des.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index de6ff01415c..35d71226100 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -14,53 +14,69 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { - ctx->ishw = 1; + if (try_hw && crypto_sha_acquire()) { + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha1_hw_init(&ctx->hw_ctx); - } - else { - ctx->ishw = 0; + } else { + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha1_sw_init(&ctx->sw_ctx); } } +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +{ + mbedtls_sha1_init_internal(ctx, 1); +} + void mbedtls_sha1_free(mbedtls_sha1_context *ctx) { if (ctx == NULL) { return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha1_clone(mbedtls_sha1_context *dst, const mbedtls_sha1_context *src) { - if (src->ishw) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + // If dst is H/W context, we need to change it to S/W context first before cloning to. + if (dst->active_ctx == &dst->hw_ctx) { + mbedtls_sha1_free(dst); + // Force S/W context + mbedtls_sha1_init_internal(dst, 0); + } + + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -78,8 +94,7 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -90,10 +105,9 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst, */ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_starts(&ctx->hw_ctx); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_starts(&ctx->sw_ctx); } } @@ -103,10 +117,9 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx) */ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -116,20 +129,18 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, */ void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_finish(&ctx->hw_ctx, output); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha1_hw_process(&ctx->hw_ctx, data); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha1_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h index 6cf738a1bb6..59f519fac96 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.h @@ -16,13 +16,8 @@ #ifndef MBEDTLS_SHA1_ALT_H #define MBEDTLS_SHA1_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include "sha_alt_hw.h" @@ -37,9 +32,8 @@ struct mbedtls_sha1_context_s; /** * \brief SHA-1 context structure */ -typedef struct mbedtls_sha1_context_s -{ - int ishw; +typedef struct mbedtls_sha1_context_s { + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha1_sw_context sw_ctx; } @@ -100,6 +94,5 @@ void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[6 #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c index 230c872465d..097b0e518f1 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.c @@ -24,17 +24,11 @@ * http://www.itl.nist.gov/fipspubs/fip180-1.htm */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) -#include "mbedtls/sha1.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) @@ -46,8 +40,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; } /* @@ -87,7 +83,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ) } void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ) + const mbedtls_sha1_sw_context *src ) { *dst = *src; } @@ -283,8 +279,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha1_sw_process( ctx, ctx->buffer ); input += fill; @@ -292,8 +287,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha1_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -303,9 +297,8 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char * memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha1_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha1_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -321,7 +314,7 @@ void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[ unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h index 9d138abb8ac..7c847564812 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt_sw.h @@ -23,13 +23,8 @@ #ifndef MBEDTLS_SHA1_ALT_SW_H #define MBEDTLS_SHA1_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) #include @@ -42,8 +37,7 @@ extern "C" { /** * \brief SHA-1 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[5]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -71,7 +65,7 @@ void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst, - const mbedtls_sha1_sw_context *src ); + const mbedtls_sha1_sw_context *src ); /** * \brief SHA-1 context setup @@ -105,6 +99,5 @@ void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char #endif #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ #endif /* sha1_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index e5fd727e2a7..b576d7a767d 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -14,53 +14,69 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" #include "crypto-misc.h" #include "nu_bitutil.h" #include "string.h" -void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +/* Choose SHA S/W or H/W context and initialize it + * + * try_hw: + * 0: Initialize S/W context + * 1: Try acquiring SHA H/W resource first and initialize its H/W context if successful. If failed, initialize S/W context. + */ +static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { - if (crypto_sha_acquire()) { - ctx->ishw = 1; + if (try_hw && crypto_sha_acquire()) { + ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha256_hw_init(&ctx->hw_ctx); - } - else { - ctx->ishw = 0; + } else { + ctx->active_ctx = &ctx->sw_ctx; mbedtls_sha256_sw_init(&ctx->sw_ctx); } } +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + mbedtls_sha256_init_internal(ctx, 1); +} + void mbedtls_sha256_free(mbedtls_sha256_context *ctx) { if (ctx == NULL) { return; } - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_free(&ctx->hw_ctx); crypto_sha_release(); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_free(&ctx->sw_ctx); } + ctx->active_ctx = NULL; } void mbedtls_sha256_clone(mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src) + const mbedtls_sha256_context *src) { - if (src->ishw) { + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + // If dst is H/W context, we need to change it to S/W context first before cloning to. + if (dst->active_ctx == &dst->hw_ctx) { + mbedtls_sha256_free(dst); + // Force S/W context + mbedtls_sha256_init_internal(dst, 0); + } + + if (src->active_ctx == &src->hw_ctx) { // Clone S/W ctx from H/W ctx - dst->ishw = 0; dst->sw_ctx.total[0] = src->hw_ctx.total; dst->sw_ctx.total[1] = 0; { @@ -79,8 +95,7 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) { mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer); } - } - else { + } else if (src->active_ctx == &src->sw_ctx) { // Clone S/W ctx from S/W ctx dst->sw_ctx = src->sw_ctx; } @@ -90,11 +105,10 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst, * SHA-256 context setup */ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) -{ - if (ctx->ishw) { +{ + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224); } } @@ -104,10 +118,9 @@ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) */ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen); } } @@ -117,20 +130,18 @@ void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *inp */ void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_finish(&ctx->hw_ctx, output); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_finish(&ctx->sw_ctx, output); } } void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) { - if (ctx->ishw) { + if (ctx->active_ctx == &ctx->hw_ctx) { mbedtls_sha256_hw_process(&ctx->hw_ctx, data); - } - else { + } else if (ctx->active_ctx == &ctx->sw_ctx) { mbedtls_sha256_sw_process(&ctx->sw_ctx, data); } } diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h index 23a156ddd7d..04ff65fd188 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.h @@ -16,13 +16,8 @@ #ifndef MBEDTLS_SHA256_ALT_H #define MBEDTLS_SHA256_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include "sha_alt_hw.h" @@ -37,9 +32,8 @@ struct mbedtls_sha256_context_s; /** * \brief SHA-256 context structure */ -typedef struct mbedtls_sha256_context_s -{ - int ishw; +typedef struct mbedtls_sha256_context_s { + void *active_ctx; crypto_sha_context hw_ctx; mbedtls_sha256_sw_context sw_ctx; } @@ -84,7 +78,7 @@ void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest @@ -102,6 +96,5 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c index 3ac2b613173..616a8400f6c 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.c @@ -24,17 +24,11 @@ * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) -#include "mbedtls/sha256.h" - #include #if defined(MBEDTLS_SELF_TEST) #if defined(MBEDTLS_PLATFORM_C) @@ -49,8 +43,10 @@ #endif /* MBEDTLS_SELF_TEST */ /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = v; + while( n-- ) *p++ = 0; } /* @@ -90,7 +86,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ) } void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ) + const mbedtls_sha256_sw_context *src ) { *dst = *src; } @@ -103,8 +99,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->total[0] = 0; ctx->total[1] = 0; - if( is224 == 0 ) - { + if( is224 == 0 ) { /* SHA-256 */ ctx->state[0] = 0x6A09E667; ctx->state[1] = 0xBB67AE85; @@ -114,9 +109,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->state[5] = 0x9B05688C; ctx->state[6] = 0x1F83D9AB; ctx->state[7] = 0x5BE0CD19; - } - else - { + } else { /* SHA-224 */ ctx->state[0] = 0xC1059ED8; ctx->state[1] = 0x367CD507; @@ -131,8 +124,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ) ctx->is224 = is224; } -static const uint32_t K[] = -{ +static const uint32_t K[] = { 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5, 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5, 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3, @@ -186,8 +178,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c A[i] = ctx->state[i]; #if defined(MBEDTLS_SHA256_SMALLER) - for( i = 0; i < 64; i++ ) - { + for( i = 0; i < 64; i++ ) { if( i < 16 ) GET_UINT32_BE( W[i], data, 4 * i ); else @@ -195,15 +186,21 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); - temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3]; - A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1; + temp1 = A[7]; + A[7] = A[6]; + A[6] = A[5]; + A[5] = A[4]; + A[4] = A[3]; + A[3] = A[2]; + A[2] = A[1]; + A[1] = A[0]; + A[0] = temp1; } #else /* MBEDTLS_SHA256_SMALLER */ for( i = 0; i < 16; i++ ) GET_UINT32_BE( W[i], data, 4 * i ); - for( i = 0; i < 16; i += 8 ) - { + for( i = 0; i < 16; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] ); @@ -214,8 +211,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] ); } - for( i = 16; i < 64; i += 8 ) - { + for( i = 16; i < 64; i += 8 ) { P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] ); P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] ); P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] ); @@ -235,7 +231,7 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c * SHA-256 process buffer */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ) + size_t ilen ) { size_t fill; uint32_t left; @@ -252,8 +248,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch if( ctx->total[0] < (uint32_t) ilen ) ctx->total[1]++; - if( left && ilen >= fill ) - { + if( left && ilen >= fill ) { memcpy( (void *) (ctx->buffer + left), input, fill ); mbedtls_sha256_sw_process( ctx, ctx->buffer ); input += fill; @@ -261,8 +256,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch left = 0; } - while( ilen >= 64 ) - { + while( ilen >= 64 ) { mbedtls_sha256_sw_process( ctx, input ); input += 64; ilen -= 64; @@ -272,9 +266,8 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned ch memcpy( (void *) (ctx->buffer + left), input, ilen ); } -static const unsigned char sha256_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const unsigned char sha256_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 @@ -290,7 +283,7 @@ void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char out unsigned char msglen[8]; high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); + | ( ctx->total[1] << 3 ); low = ( ctx->total[0] << 3 ); PUT_UINT32_BE( high, msglen, 0 ); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h index c1b72ea8f70..bd96f5cdda6 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt_sw.h @@ -23,13 +23,8 @@ #ifndef MBEDTLS_SHA256_ALT_SW_H #define MBEDTLS_SHA256_ALT_SW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha256.h" -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) #include @@ -42,8 +37,7 @@ extern "C" { /** * \brief SHA-256 context structure */ -typedef struct -{ +typedef struct { uint32_t total[2]; /*!< number of bytes processed */ uint32_t state[8]; /*!< intermediate digest state */ unsigned char buffer[64]; /*!< data block being processed */ @@ -72,7 +66,7 @@ void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx ); * \param src The context to be cloned */ void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst, - const mbedtls_sha256_sw_context *src ); + const mbedtls_sha256_sw_context *src ); /** * \brief SHA-256 context setup @@ -90,7 +84,7 @@ void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 ); * \param ilen length of the input data */ void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); /** * \brief SHA-256 final digest @@ -108,6 +102,5 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned c #endif #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #endif /* sha256_alt_sw.h */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c index b34bcd7f876..246a75858b5 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.c @@ -14,30 +14,18 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" #if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) -#if defined(MBEDTLS_SHA1_ALT) -#include "sha1_alt.h" -#endif /* MBEDTLS_SHA1_ALT */ - -#if defined(MBEDTLS_SHA256_ALT) -#include "sha256_alt.h" -#endif /* MBEDTLS_SHA256_ALT */ - -#if defined(MBEDTLS_SHA512_ALT) -#include "sha512_alt.h" -#endif /* MBEDTLS_SHA512_ALT */ - #include "nu_bitutil.h" +#include "nu_timer.h" #include "mbed_assert.h" +#include "mbed_error.h" #include "crypto-misc.h" #include @@ -53,8 +41,9 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen); void mbedtls_sha1_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha1_hw_free(crypto_sha_context *ctx) @@ -63,30 +52,28 @@ void mbedtls_sha1_hw_free(crypto_sha_context *ctx) return; } - crypto_zeroize(ctx, sizeof(crypto_sha_context)); -} + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; -void mbedtls_sha1_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; + /* Uninit crypto module */ + crypto_uninit(); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha1_hw_starts(crypto_sha_context *ctx) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; ctx->blocksize_mask = 0x3F; SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP); - - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk; - + return; } @@ -102,17 +89,16 @@ void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, 20); - - CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha1_sw_context ctx_sw; - + mbedtls_sha1_sw_init(&ctx_sw); mbedtls_sha1_sw_starts(&ctx_sw); mbedtls_sha1_sw_finish(&ctx_sw, output); mbedtls_sha1_sw_free(&ctx_sw); } + + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; } void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -128,8 +114,9 @@ void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[6 void mbedtls_sha256_hw_init(crypto_sha_context *ctx) { + /* Init crypto module */ crypto_init(); - memset(ctx, 0, sizeof(crypto_sha_context)); + memset(ctx, 0, sizeof(*ctx)); } void mbedtls_sha256_hw_free(crypto_sha_context *ctx) @@ -138,20 +125,18 @@ void mbedtls_sha256_hw_free(crypto_sha_context *ctx) return; } - crypto_zeroize(ctx, sizeof(crypto_sha_context)); -} + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; -void mbedtls_sha256_hw_clone(crypto_sha_context *dst, - const crypto_sha_context *src) -{ - *dst = *src; + /* Uninit crypto module */ + crypto_uninit(); + crypto_zeroize(ctx, sizeof(*ctx)); } void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) { // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - + ctx->total = 0; ctx->buffer_left = 0; ctx->blocksize = 64; @@ -159,10 +144,10 @@ void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224) ctx->is224 = is224; SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP); - - // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started. + + // Ensure we have correct initial internal states in SHA_DGST registers even though SHA H/W is not actually started. CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk; - + return; } @@ -178,17 +163,16 @@ void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32]) crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1); ctx->buffer_left = 0; crypto_sha_getinternstate(output, ctx->is224 ? 28 : 32); - - CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; - } - else { + } else { mbedtls_sha256_sw_context ctx_sw; - + mbedtls_sha256_sw_init(&ctx_sw); mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224); mbedtls_sha256_sw_finish(&ctx_sw, output); mbedtls_sha256_sw_free(&ctx_sw); } + + CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk; } void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64]) @@ -207,7 +191,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size if (ilen == 0) { return; } - + size_t fill = ctx->blocksize - ctx->buffer_left; ctx->total += (uint32_t) ilen; @@ -222,7 +206,7 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size ctx->buffer_left = 0; } } - + while (ilen > ctx->blocksize) { crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0); input += ctx->blocksize; @@ -241,16 +225,14 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input // 1. Last block which may be incomplete // 2. Non-last block which is complete MBED_ASSERT(islast || ilen == ctx->blocksize); - + const unsigned char *in_pos = input; int rmn = ilen; uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk; uint32_t sha_opmode = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos; - uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old; - + uint32_t DGSTs[8] = { 0 }; + while (rmn > 0) { - CRPT->SHA_CTL = sha_ctl_start; - uint32_t data = nu_get32_be(in_pos); if (rmn <= 4) { // Last word of a (in)complete block if (islast) { @@ -260,71 +242,90 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input } CRPT->SHA_DMACNT = lastblock_size; CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk; - } - else { + } else { switch (sha_opmode) { - case SHA_MODE_SHA256: - DGST7_old = CRPT->SHA_DGST7; - case SHA_MODE_SHA224: - DGST5_old = CRPT->SHA_DGST5; - DGST6_old = CRPT->SHA_DGST6; - case SHA_MODE_SHA1: - DGST0_old = CRPT->SHA_DGST0; - DGST1_old = CRPT->SHA_DGST1; - DGST2_old = CRPT->SHA_DGST2; - DGST3_old = CRPT->SHA_DGST3; - DGST4_old = CRPT->SHA_DGST4; + case SHA_MODE_SHA256: + DGSTs[7] = CRPT->SHA_DGST7; + case SHA_MODE_SHA224: + DGSTs[5] = CRPT->SHA_DGST5; + DGSTs[6] = CRPT->SHA_DGST6; + case SHA_MODE_SHA1: + DGSTs[0] = CRPT->SHA_DGST0; + DGSTs[1] = CRPT->SHA_DGST1; + DGSTs[2] = CRPT->SHA_DGST2; + DGSTs[3] = CRPT->SHA_DGST3; + DGSTs[4] = CRPT->SHA_DGST4; } CRPT->SHA_CTL = sha_ctl_start; } - } - else { // Non-last word of a complete block + } else { // Non-last word of a complete block CRPT->SHA_CTL = sha_ctl_start; } while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk)); CRPT->SHA_DATIN = data; - + in_pos += 4; rmn -= 4; } - + if (islast) { // Finish of last block while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk); - } - else { // Finish of non-last block - // No H/W flag to indicate finish of non-last block process. - // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement. + } else { // Finish of non-last block + /* SHA accelerator doesn't export a flag to indicate non-last block process has finished. + * Per designer, if the digest (SHA_DGSTx) code changes after the last word of the block is input, + * this indicates the non-last block process has finished. + * + * There is a rare case that two digest codes are the same for + * two non-last block processes in a row. + * To address it, we use a count-down timer to detect it. + * As the count-down timer expires, we see it as finished. + */ int isfinish = 0; + struct nu_countdown_ctx_s ctx; + + // Set up 2s timeout + nu_countdown_init(&ctx, 2000*1000); while (! isfinish) { switch (sha_opmode) { - case SHA_MODE_SHA256: - if (DGST7_old != CRPT->SHA_DGST7) { - isfinish = 1; - break; - } - case SHA_MODE_SHA224: - if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) { - isfinish = 1; - break; - } - case SHA_MODE_SHA1: - if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 || - DGST3_old != CRPT->SHA_DGST3 || DGST4_old != CRPT->SHA_DGST4) { - isfinish = 1; - break; - } + case SHA_MODE_SHA256: + if (DGSTs[7] != CRPT->SHA_DGST7) { + isfinish = 1; + break; + } + case SHA_MODE_SHA224: + if (DGSTs[5] != CRPT->SHA_DGST5 || DGSTs[6] != CRPT->SHA_DGST6) { + isfinish = 1; + break; + } + case SHA_MODE_SHA1: + if (DGSTs[0] != CRPT->SHA_DGST0 || DGSTs[1] != CRPT->SHA_DGST1 || DGSTs[2] != CRPT->SHA_DGST2 || + DGSTs[3] != CRPT->SHA_DGST3 || DGSTs[4] != CRPT->SHA_DGST4) { + isfinish = 1; + break; + } + } + + if (nu_countdown_expired(&ctx)) { + // We may meet a rare case that the current digest code and the previous one are the same. + isfinish = 1; } } + // Must pair nu_countdown_init with nu_countdown_free in the end + nu_countdown_free(&ctx); } } void crypto_sha_getinternstate(unsigned char output[], size_t olen) { + if (olen & 0x3) { + error("Internal error in SHA alter. SHA internal state size requires to be a multiple of 4 bytes."); + } + uint32_t *in_pos = (uint32_t *) &CRPT->SHA_DGST0; unsigned char *out_pos = output; uint32_t rmn = olen; - + while (rmn) { uint32_t val = *in_pos ++; nu_set32_be(out_pos, val); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h index 6ee7da14df8..9b91f7c27af 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha_alt_hw.h @@ -16,13 +16,6 @@ #ifndef MBEDTLS_SHA_ALT_HW_H #define MBEDTLS_SHA_ALT_HW_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) #if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) #include @@ -35,14 +28,13 @@ extern "C" { /** * \brief SHA context structure */ -typedef struct -{ +typedef struct { uint32_t total; /*!< number of bytes processed */ - unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ + uint8_t buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ uint16_t buffer_left; uint16_t blocksize; /*!< block size */ uint32_t blocksize_mask; /*!< block size mask */ - + int is224; /*!< 0 => SHA-256, else SHA-224 */ } crypto_sha_context; @@ -51,42 +43,33 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast); void crypto_sha_getinternstate(unsigned char output[], size_t olen); -#if defined(MBEDTLS_SHA1_C) #if defined(MBEDTLS_SHA1_ALT) void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha1_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA1_ALT */ -#endif /* MBEDTLS_SHA1_C */ -#if defined(MBEDTLS_SHA256_C) #if defined(MBEDTLS_SHA256_ALT) void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); -void mbedtls_sha256_hw_clone( crypto_sha_context *dst, - const crypto_sha_context *src ); void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, - size_t ilen ); + size_t ilen ); void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] ); void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); #endif /* MBEDTLS_SHA256_ALT */ -#endif /* MBEDTLS_SHA256_C */ #ifdef __cplusplus } #endif #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ -#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */ -#endif /* sha_alt.h */ +#endif /* sha_alt_hw.h */ diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile b/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile index c808df61709..f104a781109 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile @@ -48,10 +48,7 @@ override CFLAGS += -I$(EVENTLOOP_DIR)/nanostack-event-loop/ COAPSERVICE_DIR := ../coap-service override CFLAGS += -I$(COAPSERVICE_DIR)/coap-service/ override CFLAGS += -I$(COAPSERVICE_DIR)/source/include/ - -ifeq (Linux,$(shell uname)) override CFLAGS += -DHAVE_DEBUG -endif LIB = libcoap-service.a diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c index 63ef7011947..1a280374556 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c @@ -46,13 +46,16 @@ static void own_free(void *ptr) static NS_LIST_DEFINE(request_list, coap_transaction_t, link); -static coap_transaction_t *transaction_find_client_by_token(uint8_t token[4]) +static coap_transaction_t *transaction_find_client_by_token(uint8_t *token, uint8_t token_len, const uint8_t address[static 16], uint16_t port) { + (void) address; + (void) port; coap_transaction_t *this = NULL; + ns_list_foreach(coap_transaction_t, cur_ptr, &request_list) { - if (memcmp(cur_ptr->token,token,4) == 0 && cur_ptr->client_request) { + if ((cur_ptr->token_len == token_len) && (memcmp(cur_ptr->token, token, token_len) == 0) && cur_ptr->client_request) { this = cur_ptr; - break; + break; } } return this; @@ -147,12 +150,13 @@ static int8_t coap_rx_function(sn_coap_hdr_s *resp_ptr, sn_nsdl_addr_s *address_ coap_transaction_t *this = NULL; (void)address_ptr; (void)param; + tr_warn("transaction was not handled %d", resp_ptr->msg_id); if (!resp_ptr) { return -1; } - if( resp_ptr->token_ptr ){ - this = transaction_find_client_by_token(resp_ptr->token_ptr); + if(resp_ptr->token_ptr){ + this = transaction_find_client_by_token(resp_ptr->token_ptr, resp_ptr->token_len, address_ptr->addr_ptr, address_ptr->port); } if (!this) { return 0; @@ -278,6 +282,7 @@ int16_t coap_message_handler_coap_msg_process(coap_msg_handler_t *handle, int8_t memcpy(transaction_ptr->remote_address, source_addr_ptr, 16); if (coap_message->token_len) { memcpy(transaction_ptr->token, coap_message->token_ptr, coap_message->token_len); + transaction_ptr->token_len = coap_message->token_len; } transaction_ptr->remote_port = port; if (cb(socket_id, coap_message, transaction_ptr) < 0) { @@ -292,7 +297,7 @@ int16_t coap_message_handler_coap_msg_process(coap_msg_handler_t *handle, int8_t } else { coap_transaction_t *this = NULL; if (coap_message->token_ptr) { - this = transaction_find_client_by_token(coap_message->token_ptr); + this = transaction_find_client_by_token(coap_message->token_ptr, coap_message->token_len, source_addr_ptr, port); } if (!this) { tr_error("client transaction not found"); @@ -337,6 +342,7 @@ uint16_t coap_message_handler_request_send(coap_msg_handler_t *handle, int8_t se transaction_ptr->options = options; memcpy(transaction_ptr->remote_address, destination_addr, 16); transaction_ptr->remote_port = destination_port; + transaction_ptr->req_msg_type = msg_type; memset(&request, 0, sizeof(request)); dst_addr.addr_ptr = (uint8_t *) destination_addr; // Cast away const and trust that nsdl doesn't modify... dst_addr.addr_len = 16; @@ -351,8 +357,9 @@ uint16_t coap_message_handler_request_send(coap_msg_handler_t *handle, int8_t se do{ randLIB_get_n_bytes_random(token,4); - }while(transaction_find_client_by_token(token)); + }while(transaction_find_client_by_token(token, 4, destination_addr, destination_port)); memcpy(transaction_ptr->token,token,4); + transaction_ptr->token_len = 4; request.token_ptr = transaction_ptr->token; request.token_len = 4; @@ -463,7 +470,7 @@ int8_t coap_message_handler_response_send_by_msg_id(coap_msg_handler_t *handle, response.payload_len = payload_len; response.payload_ptr = (uint8_t *) payload_ptr; // Cast away const and trust that nsdl doesn't modify... response.content_format = content_type; - response.token_len = 4; + response.token_len = transaction_ptr->token_len; response.token_ptr = transaction_ptr->token; response.msg_code = message_code; if (transaction_ptr->req_msg_type == COAP_MSG_TYPE_CONFIRMABLE) { diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_service_api.c b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_service_api.c index 91f2e3ef588..9adcee212a4 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_service_api.c +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_service_api.c @@ -188,7 +188,7 @@ static uint8_t coap_tx_function(uint8_t *data_ptr, uint16_t data_len, sn_nsdl_ad memcpy(transaction_ptr->data_ptr, data_ptr, data_len); transaction_ptr->data_len = data_len; } - } else if ((ret_val == -1) || (transaction_ptr->resp_cb == NULL)) { + } else if ((ret_val == -1) || (!transaction_ptr->resp_cb && transaction_ptr->req_msg_type == COAP_MSG_TYPE_NON_CONFIRMABLE)) { transaction_delete(transaction_ptr); } @@ -300,7 +300,7 @@ static void sec_done_cb(int8_t socket_id, uint8_t address[static 16], uint16_t p ns_dyn_mem_free(transaction_ptr->data_ptr); transaction_ptr->data_ptr = NULL; transaction_ptr->data_len = 0; - if (transaction_ptr->resp_cb == NULL) { + if (!transaction_ptr->resp_cb && transaction_ptr->req_msg_type == COAP_MSG_TYPE_NON_CONFIRMABLE) { transaction_delete(transaction_ptr); } } diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h index a484216900c..35c6af129bc 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h @@ -50,18 +50,19 @@ typedef struct coap_msg_handler_s { typedef struct coap_transaction { uint8_t remote_address[16]; uint8_t local_address[16]; - uint8_t token[4]; + uint8_t token[8]; uint32_t create_time; + uint8_t *data_ptr; + coap_message_handler_response_recv *resp_cb; uint16_t remote_port; uint16_t msg_id; uint16_t data_len; int8_t service_id; uint8_t options; - uint8_t *data_ptr; + uint8_t token_len; sn_coap_msg_type_e req_msg_type; bool client_request: 1; - coap_message_handler_response_recv *resp_cb; ns_list_link_t link; } coap_transaction_t; diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h index 2c20f8a49a5..0a4d948a789 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h @@ -20,11 +20,18 @@ #include "ns_types.h" #ifdef NS_USE_EXTERNAL_MBED_TLS +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SSL_TLS_C) #include "mbedtls/ssl.h" -#ifdef MBEDTLS_SSL_TLS_C #define COAP_SECURITY_AVAILABLE #endif -#endif + +#endif /* NS_USE_EXTERNAL_MBED_TLS */ #define COOKIE_SIMPLE_LEN 8 typedef struct simple_cookie { diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md deleted file mode 100644 index eb50e73fb91..00000000000 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md +++ /dev/null @@ -1,141 +0,0 @@ -# mbed mesh API - -ARM mbed mesh API allows the client to use the IPv6 mesh network. - -The client can use the `LoWPANNDInterface` or `ThreadInterface` object for connecting to the mesh network and when successfully connected, the client can create a socket by using the [mbed C++ socket API](https://developer.mbed.org/teams/NetworkSocketAPI/code/NetworkSocketAPI/docs/tip/) to start communication with a remote peer. - -For ethernet `NanostackEthernetInterface` is provided. - -## Supported mesh networking modes - -Currently, 6LoWPAN-ND (neighbour discovery) and Thread bootstrap modes are supported. - -## Module Configuration - -This module supports static configuration via **mbed configuration system** by using the `mbed_app.json` file. The application needs to create the configuration file if it wants to use other than default settings. - -An example of the configuration file: - -``` -{ - "target_overrides": { - "*": { - "target.features_add": ["IPV6"], - "mbed-mesh-api.6lowpan-nd-channel": 12, - "mbed-mesh-api.6lowpan-nd-channel-mask": "(1<<12)", - "mbed-mesh-api.heap-size": 10000 - } - } -} -``` - -### Configurable parameters in section mbed-mesh-api - -| Parameter name | Value | Description | -| --------------- | ------------- | ----------- | -| heap-size | number [0-0xfffe] | Nanostack's internal heap size | -| use-malloc-for-heap | `false` or `true` | Use `malloc()` for reserving the internal heap. Default: `false` | - -### Thread related configuration parameters - -| Parameter name | Value | Description | -| --------------- | ------------- | ----------- | -| thread-pskd | string [6-255 chars] | Human-scaled commissioning credentials. | -| thread-use-static-link-config | boolean | True: Use the below link config, False: Use commissioning, ignore the below link config. | -| thread-device-type | enum from mesh_device_type_t | Supported device operating modes: MESH_DEVICE_TYPE_THREAD_ROUTER, MESH_DEVICE_TYPE_THREAD_SLEEPY_END_DEVICE, MESH_DEVICE_TYPE_THREAD_MINIMAL_END_DEVICE | -| thread-config-channel-mask | number [0-0x07fff800] | Channel mask, 0x07fff800 scans all channels. | -| thread-config-channel-page | number [0, 2]| Channel page, 0 for 2,4 GHz and 2 for sub-GHz radios. | -| thread-config-channel | number [0-27] | RF channel to use. | -| thread-config-panid | number [0-0xFFFF] | Network identifier. | -| thread-config-network-name | string [1-16] | -| thread-config-commissioning-dataset-timestamp | [0-0xFFFFFFFFFFFFFFFF] | [48 bit timestamp seconds]-[15 bit timestamp ticks]-[U bit] | -|thread-config-extended-panid | byte array [8] | Extended PAN ID | -| thread-master-key | byte array [16]| Network master key. | -| thread-config-ml-prefix | byte array [8] | Mesh local prefix. | -| thread-config-pskc | byte array [16] | Pre-Shared Key for the Commissioner. | -| thread-security-policy | number [0-0xFF] | Commissioning security policy bits | - -### 6LoWPAN related configuration parameters - -| Parameter name | Type | Description | -| --------------- | ---------| ----------- | -| 6lowpan-nd-channel-mask | number [0-0x07fff800] | Channel mask, bit-mask of channels to use | -| 6lowpan-nd-channel-page | number [0, 2] | 0 for 2,4 GHz and 2 for sub-GHz radios | -| 6lowpan-nd-channel | number [0-27] | RF channel to use when `channel_mask` is not defined | -| 6lowpan-nd-panid-filter | number [0-0xffff] | Beacon PAN ID filter, 0xffff means no filtering | -| 6lowpan-nd-security-mode | "NONE" or "PSK" | To use either no security, or Pre shared network key | -| 6lowpan-nd-psk-key-id | number | PSK key id when PSK is enabled | -| 6lowpan-nd-psk-key | byte array [16] | Pre shared network key | -| 6lowpan-nd-sec-level | number [1-7] | Network security level. Use default `5` | -| 6lowpan-nd-device-type | "NET_6LOWPAN_ROUTER" or "NET_6LOWPAN_HOST" | Device mode. Router is routing packets from other device, creating a mesh network. | - -## Usage notes - -This module should not be used directly by the applications. The applications should use the `LoWPANNDInterface`, `ThreadInterface` or `NanostackEthernetInterface` directly. - -When using Ethernet interface, there is no configuration options available. It is using dynamic mode to learn the IPv6 prefix from the network. No static configuration is supported. - -### Network connection states - -After the initialization, the network state is `MESH_DISCONNECTED`. After a successful connection, the state changes to `MESH_CONNECTED` and when disconnected from the network the state is changed back to `MESH_DISCONNECTED`. - -In case of connection errors, the state is changed to some of the connection error states. In an error state, there is no need to make a `disconnect` request and the client is allowed to attempt connecting again. - -## Getting started - -See the example application [mbed-os-example-mesh-minimal](https://github.com/ARMmbed/mbed-os-example-mesh-minimal) for usage. - -## Usage example for 6LoWPAN ND mode - -Create a network interface and driver objects. - -``` -LoWPANNDInterface mesh; -NanostackRfPhyNcs36510 rf_phy; -``` - -Initialize interface with given PHY driver. - -``` -mesh.initialize(&rf_phy); -``` - -Then connect to network: - -``` - if (mesh.connect()) { - printf("Connection failed!\r\n"); - return -1; - } - - printf("connected. IP = %s\r\n", mesh.get_ip_address()); -``` - -## Usage example for 6LoWPAN Thread mode - -Basically the same as for ND, but the network interface uses different class: - -``` -ThreadInterface mesh; -mesh.connect(); -``` - -## Usage example with Ethernet - -API is still the same, you just need to provide a driver that implements `NanostackEthernetPhy` API. - -``` -NanostackEthernetInterface eth; -NanostackEthernetPhyK64F phy; - -int main() { - eth.initialize(&phy); - - if (eth.connect()) { - printf("Connection failed!\r\n"); - return -1; - } - - printf("connected. IP = %s\r\n", eth.get_ip_address()); -} -``` diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json index c9401e662c3..f3a1cd359c3 100644 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json +++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json @@ -3,16 +3,16 @@ "config": { "heap-size": 32500, "use-malloc-for-heap": false, - "6lowpan-nd-channel-mask": "(1<<12)", + "6lowpan-nd-channel-mask": "0x7fff800", "6lowpan-nd-channel-page": 0, - "6lowpan-nd-channel": 12, + "6lowpan-nd-channel": 0, "6lowpan-nd-panid-filter": "0xffff", "6lowpan-nd-security-mode": "NONE", "6lowpan-nd-psk-key-id": 1, "6lowpan-nd-psk-key": "{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf}", "6lowpan-nd-sec-level": 5, "6lowpan-nd-device-type": "NET_6LOWPAN_ROUTER", - "thread-pskd": "\"abcdefghijklmno\"", + "thread-pskd": "\"ABCDEFGH\"", "thread-use-static-link-config": true, "thread-config-channel-mask": "0x7fff800", "thread-config-channel-page": 0, diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c index e3eab47677e..efd42993485 100644 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c +++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c @@ -106,7 +106,7 @@ static void initialize_channel_list(void) tr_debug("Channel: %ld", channel); tr_debug("Channel page: %d", tasklet_data_ptr->channel_list.channel_page); - tr_debug("Channel mask: %ld", tasklet_data_ptr->channel_list.channel_mask[word_index]); + tr_debug("Channel mask: 0x%.8lx", tasklet_data_ptr->channel_list.channel_mask[word_index]); } /* diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/thread_tasklet.c b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/thread_tasklet.c index 676b0c786b1..5a307159da8 100644 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/thread_tasklet.c +++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/thread_tasklet.c @@ -274,8 +274,8 @@ void thread_tasklet_configure_and_connect_to_network(void) thread_tasklet_data_ptr->channel_list.channel_mask[0] = MBED_CONF_MBED_MESH_API_THREAD_CONFIG_CHANNEL_MASK; TRACE_DETAIL("channel page: %d", thread_tasklet_data_ptr->channel_list.channel_page); - TRACE_DETAIL("channel mask: %d", (int)thread_tasklet_data_ptr->channel_list.channel_mask[0]); - + TRACE_DETAIL("channel mask: 0x%.8lx", thread_tasklet_data_ptr->channel_list.channel_mask[0]); + // PSKd const char PSKd[] = MBED_CONF_MBED_MESH_API_THREAD_PSKD; MBED_ASSERT(sizeof(PSKd) > 5 && sizeof(PSKd) < 33); diff --git a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp index 739871c5409..c85cfca2a95 100644 --- a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp @@ -128,6 +128,20 @@ static void convert_ns_addr_to_mbed(SocketAddress *s_addr, const ns_address_t *n s_addr->set_ip_bytes(ns_addr->address, NSAPI_IPv6); } +static int8_t find_interface_by_address(const uint8_t target_addr[16]) +{ + for (int if_id = 1; if_id <= 127; if_id++) { + int i = 0; + uint8_t if_addr[16]; + while (arm_net_address_list_get_next(if_id, &i, if_addr) == 0) { + if (memcmp(target_addr, if_addr, 16) == 0) { + return if_id; + } + } + } + return -1; +} + void* NanostackSocket::operator new(std::size_t sz) { return MALLOC(sz); } @@ -693,17 +707,50 @@ nsapi_error_t NanostackInterface::setsockopt(void *handle, int level, int optnam return NSAPI_ERROR_NO_SOCKET; } - nsapi_error_t ret; - NanostackLockGuard lock; + ns_ipv6_mreq_t ns_mreq; + + if (level == NSAPI_SOCKET) { + switch (optname) { + case NSAPI_ADD_MEMBERSHIP: + case NSAPI_DROP_MEMBERSHIP: { + if (optlen != sizeof(nsapi_ip_mreq_t)) { + return NSAPI_ERROR_PARAMETER; + } + const nsapi_ip_mreq_t *imr = static_cast(optval); + + /* Check address types are IPv6, or unspecified for interface */ + if (imr->imr_multiaddr.version != NSAPI_IPv6 || + (imr->imr_interface.version != NSAPI_UNSPEC && imr->imr_interface.version != NSAPI_IPv6)) { + return NSAPI_ERROR_PARAMETER; + } + + /* Convert all parameters to Nanostack native, and proceed with setsockopt */ + memcpy(ns_mreq.ipv6mr_multiaddr, imr->imr_multiaddr.bytes, 16); + if (imr->imr_interface.version == NSAPI_UNSPEC || memcmp(imr->imr_interface.bytes, ns_in6addr_any, 16) == 0) { + ns_mreq.ipv6mr_interface = 0; + } else { + // If this fails, Nanostack will itself fault the invalid -1 interface ID + ns_mreq.ipv6mr_interface = find_interface_by_address(imr->imr_interface.bytes); + } + + level = SOCKET_IPPROTO_IPV6; + optname = optname == NSAPI_ADD_MEMBERSHIP ? SOCKET_IPV6_JOIN_GROUP : SOCKET_IPV6_LEAVE_GROUP; + optval = &ns_mreq; + optlen = sizeof ns_mreq; + break; + } + default: + return NSAPI_ERROR_PARAMETER; + } + } + if (::socket_setsockopt(socket->socket_id, level, optname, optval, optlen) == 0) { - ret = NSAPI_ERROR_OK; + return NSAPI_ERROR_OK; } else { - ret = NSAPI_ERROR_PARAMETER; + return NSAPI_ERROR_PARAMETER; } - - return ret; } nsapi_error_t NanostackInterface::getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen) diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index d045f241664..75c3af2d9b0 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -62,7 +62,7 @@ enum RFThreadSignal { SL_QUEUE_FULL = (1 << 11), // ACK pend flag can be signalled in addition to RX_DONE - SL_ACK_PEND = (1 << 31), + SL_ACK_PEND = (1 << 30), }; /* Adaptor thread definitions */ diff --git a/features/netsocket/TCPSocket.h b/features/netsocket/TCPSocket.h index 7b12ba3a9ea..39c547d7afa 100644 --- a/features/netsocket/TCPSocket.h +++ b/features/netsocket/TCPSocket.h @@ -111,7 +111,9 @@ class TCPSocket : public Socket { * @param data Destination buffer for data received from the host * @param size Size of the buffer in bytes * @return Number of received bytes on success, negative error - * code on failure + * code on failure. If no data is available to be received + * and the peer has performed an orderly shutdown, + * recv() returns 0. */ nsapi_size_or_error_t recv(void *data, nsapi_size_t size); diff --git a/features/netsocket/UDPSocket.h b/features/netsocket/UDPSocket.h index 02f39e9ed6a..a4570fa80e5 100644 --- a/features/netsocket/UDPSocket.h +++ b/features/netsocket/UDPSocket.h @@ -94,17 +94,18 @@ class UDPSocket : public Socket { nsapi_size_or_error_t sendto(const SocketAddress &address, const void *data, nsapi_size_t size); - /** Receive a packet over a UDP socket + /** Receive a datagram over a UDP socket * - * Receives data and stores the source address in address if address - * is not NULL. Returns the number of bytes received into the buffer. + * Receives a datagram and stores the source address in address if address + * is not NULL. Returns the number of bytes written into the buffer. If the + * datagram is larger than the buffer, the excess data is silently discarded. * - * By default, recvfrom blocks until data is sent. If socket is set to - * non-blocking or times out, NSAPI_ERROR_WOULD_BLOCK is returned - * immediately. + * By default, recvfrom blocks until a datagram is received. If socket is set to + * non-blocking or times out with no datagram, NSAPI_ERROR_WOULD_BLOCK + * is returned. * * @param address Destination for the source address or NULL - * @param data Destination buffer for data received from the host + * @param data Destination buffer for datagram received from the host * @param size Size of the buffer in bytes * @return Number of received bytes on success, negative error * code on failure diff --git a/features/nvstore/README.md b/features/nvstore/README.md new file mode 100644 index 00000000000..dfac2e0e5fc --- /dev/null +++ b/features/nvstore/README.md @@ -0,0 +1,55 @@ +# NVStore + +A lightweight module providing the functionality of storing data by keys in the internal flash, for security purpose. + +## Description + +NVStore provides the ability to store a minimal set of system critical items in the internal flash. +For each item key, NVStore module provides the ability to set the item data or get it. +Newly set values are added to the flash (as in journal), with the effect of overriding the previous value for this key. +NVStore module ensures that existing data isn't harmed by power failures, during any operation. +The full interface can be found under nvstore.h. + +### Flash structure +NVStore uses two Flash areas, active and non-active. Data is written to the active area, until it gets full. +When it does, garbage collection is invoked, compacting items from the active area to the non-active one, +and switching activity between areas. +Each item is kept in an entry, containing header and data, where the header holds the item key, size and CRC. +Each area must consist of one or more erasable units (sectors). + +### APIs +- init: Initialize NVStore (also lazily called by get, set, set_once and remove APIs). +- deinit: Deinitialize NVStore. +- get: Get the value of an item, given key. +- set: Set the value of an item, given key and value. +- set_once: Like set, but allows only a one time setting of this item (and disables deleting of this item). +- remove: Remove an item, given key. +- get_item_size: Get the item value size (in bytes). +- set_max_keys: Set maximal value of unique keys. Overriding the default of NVSTORE_MAX_KEYS. This affects RAM consumption, + as NVStore consumes 4 bytes per unique key. Reinitializes the module. + + +## Usage + +### Configuring NVStore for your board +NVStore requires the addresses and sizes of both areas in flash. For this purpose, the following values should be defined in +mbed_lib.json, for each supported board: +- area_1_address +- area_1_size +- area_2_address +- area_2_size + +In addition, the num_keys value should be modified, in order to change the default number of different keys. + +### Using NVStore +NVStore is a singleton class, meaning that the system can have only a single instance of it. +To instanciate NVStore, one needs to call its get_instance member function as following: +``` c++ + NVStore &nvstore = NVStore::get_instance(); +``` +After the NVStore instantiation, one can call the init API, but it is not necessary, as all +NVStore APIs (get, set et al.) perform a "lazy initialization". + +### Testing NVStore +Run the NVStore functionality test with the mbed command as following: +mbed test -n features-nvstore-tests-nvstore-functionality \ No newline at end of file diff --git a/features/nvstore/TESTS/nvstore/functionality/main.cpp b/features/nvstore/TESTS/nvstore/functionality/main.cpp new file mode 100644 index 00000000000..2ad994b5087 --- /dev/null +++ b/features/nvstore/TESTS/nvstore/functionality/main.cpp @@ -0,0 +1,752 @@ +/* +* Copyright (c) 2018 ARM Limited. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +#include "nvstore.h" +#include "nvstore_int_flash_wrapper.h" +#include "nvstore_shared_lock.h" +#include "Thread.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest/utest.h" +#include +#include +#include + +#ifndef NVSTORE_ENABLED +#error [NOT_SUPPORTED] NVSTORE needs to be enabled for this test +#endif + +using namespace utest::v1; + +#undef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) + +#define MAX_KEYS 20 + +#define NVSTORE_MAX_NAME_LENGTH (1024) +#define NVSTORE_SIZE (64 *1024) +#define MASTER_RECORD_SIZE (8 + 4) + +#define MAX_DATA_SIZE 128 + +#define NUM_OF_ITERATIONS_CHUNK_TEST (16) +static uint32_t nvstore_testing_buf_set[NVSTORE_MAX_NAME_LENGTH] = {0}; +static uint32_t nvstore_testing_buf_get[NVSTORE_MAX_NAME_LENGTH] = {0}; + +#define THR_TEST_NUM_BUFFS 10 +#define THR_TEST_NUM_SECS 10 +#define TEST_THREAD_STACK_SIZE (2048) + +#define MAX_NUMBER_OF_THREADS 4 + +static uint32_t *thr_test_buffs[MAX_KEYS][THR_TEST_NUM_BUFFS]; +static uint16_t thr_test_sizes[MAX_KEYS][THR_TEST_NUM_BUFFS]; +static int thr_test_inds[MAX_KEYS]; +static int thr_test_num_threads; +static uint8_t thr_test_last_key; +static int thr_test_last_ind; + +void zero_get_array(uint32_t array_size) +{ + memset(nvstore_testing_buf_get, 0, array_size); +} + + +void gen_random(uint8_t *s, int len) { + for (int i = 0; i < len; ++i) { + s[i] = rand() % 256; + } +} + + +typedef struct +{ + uint32_t address; + size_t size; +} nvstore_area_data_t; + +const nvstore_area_data_t flash_area_params[] = +{ + {NVSTORE_AREA_1_ADDRESS, NVSTORE_AREA_1_SIZE}, + {NVSTORE_AREA_2_ADDRESS, NVSTORE_AREA_2_SIZE} +}; + + +void nvstore_basic_flash_test() +{ + + uint32_t pattern1[8], pattern2[6], pattern3[4], read_pat[12]; + int res; + uint32_t address; + uint8_t area; + + nvstore_int_flash_init(); + + for (area = 0; area < 2; area++) { + printf("\nArea %d data, address 0x%lx, size %d\n", area, flash_area_params[area].address, flash_area_params[area].size); + address = flash_area_params[area].address; + + res = nvstore_int_flash_erase(flash_area_params[area].address, flash_area_params[area].size); + TEST_ASSERT_EQUAL(0, res); + + memset(pattern1, 0xFF, sizeof(pattern1)); + memset(pattern1, 'A', 15); + res = nvstore_int_flash_write(15, address, pattern1); + TEST_ASSERT_EQUAL(0, res); + address += sizeof(pattern1); + + memset(pattern2, 0xFF, sizeof(pattern2)); + memset(pattern2, 'B', 16); + res = nvstore_int_flash_write(16, address, pattern2); + TEST_ASSERT_EQUAL(0, res); + address += sizeof(pattern2); + + memset(pattern3, 0xFF, sizeof(pattern3)); + memset(pattern3, 'C', 7); + res = nvstore_int_flash_write(7, address, pattern3); + TEST_ASSERT_EQUAL(0, res); + address += sizeof(pattern3); + + address = flash_area_params[area].address; + + res = nvstore_int_flash_read(sizeof(pattern1), address, read_pat); + TEST_ASSERT_EQUAL(0, res); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t *)read_pat, (uint8_t *)pattern1, sizeof(pattern1)); + address += sizeof(pattern1); + + res = nvstore_int_flash_read(sizeof(pattern2), address, read_pat); + TEST_ASSERT_EQUAL(0, res); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t *)read_pat, (uint8_t *)pattern2, sizeof(pattern2)); + address += sizeof(pattern2); + + res = nvstore_int_flash_read(sizeof(pattern3), address, read_pat); + TEST_ASSERT_EQUAL(0, res); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t *)read_pat, (uint8_t *)pattern3, sizeof(pattern3)); + address += sizeof(pattern3); + } + + nvstore_int_flash_deinit(); +} + +void nvstore_basic_functionality_test() +{ + + nvstore_int_flash_init(); + + uint16_t actual_len_bytes = 0; + NVStore &nvstore = NVStore::get_instance(); + + int result; + + gen_random((uint8_t *) nvstore_testing_buf_set, NVSTORE_MAX_NAME_LENGTH); + + result = nvstore.probe(MAX_KEYS, 0, NULL, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_NOT_FOUND, result); + + nvstore.set_max_keys(MAX_KEYS); + TEST_ASSERT_EQUAL(MAX_KEYS, nvstore.get_max_keys()); + + result = nvstore.reset(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + + result = nvstore.set(5, 18, nvstore_testing_buf_set); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + + result = nvstore.get(5, 22, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(18, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)nvstore_testing_buf_set, (uint8_t*)nvstore_testing_buf_get, 15); + result = nvstore.remove(5); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.get(5, 20, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_NOT_FOUND, result); + + result = nvstore.set(11, 0, NULL); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(9, 20, NULL); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(7, 0, nvstore_testing_buf_set); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(10, 2048, nvstore_testing_buf_set); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(13, 3, &(nvstore_testing_buf_set[1])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(15, 15, &(nvstore_testing_buf_set[2])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(64, 15, &(nvstore_testing_buf_set[2])); + TEST_ASSERT_EQUAL(NVSTORE_BAD_VALUE, result); + result = nvstore.set(9, 20, &(nvstore_testing_buf_set[3])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set_once(19, 12, &(nvstore_testing_buf_set[2])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(19, 10, &(nvstore_testing_buf_set[3])); + TEST_ASSERT_EQUAL(NVSTORE_ALREADY_EXISTS, result); + + // Make sure set items are also gotten OK after reset + result = nvstore.deinit(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.init(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + + result = nvstore.get(14, 20, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_NOT_FOUND, result); + result = nvstore.get(7, 0, NULL, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + result = nvstore.get(7, 15, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + result = nvstore.get(7, 0, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + result = nvstore.get(9, 0, NULL, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BUFF_TOO_SMALL, result); + result = nvstore.get(9, 150, NULL, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BUFF_TOO_SMALL, result); + result = nvstore.get(9, 0, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BUFF_TOO_SMALL, result); + result = nvstore.get(10, 2048, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(2048, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)nvstore_testing_buf_set, (uint8_t*)nvstore_testing_buf_get, 2048); + zero_get_array(2048); + result = nvstore.get(10, 2049, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(2048, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)nvstore_testing_buf_set, (uint8_t*)nvstore_testing_buf_get, 2048); + zero_get_array(2048); + result = nvstore.get(10, 2047, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BUFF_TOO_SMALL, result); + actual_len_bytes = 0; + result = nvstore.get(64, 20, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BAD_VALUE, result); + result = nvstore.get(9, 20, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(20, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[3]), (uint8_t*)nvstore_testing_buf_get, 20); + zero_get_array(20); + result = nvstore.get(9, 21, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(20, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[3]), (uint8_t*)nvstore_testing_buf_get, 20); + zero_get_array(20); + result = nvstore.get(9, 19, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BUFF_TOO_SMALL, result); + result = nvstore.get(13, 3, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(3, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[1]), (uint8_t*)nvstore_testing_buf_get, 3); + result = nvstore.get_item_size(13, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(3, actual_len_bytes); + zero_get_array(3); + result = nvstore.get(13, 4, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(3, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[1]), (uint8_t*)nvstore_testing_buf_get, 3); + zero_get_array(3); + result = nvstore.get(13, 2, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_BUFF_TOO_SMALL, result); + result = nvstore.init(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + // check all the expected keys + actual_len_bytes = 0; + result = nvstore.get(10, 2048, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(2048, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)nvstore_testing_buf_set, (uint8_t*)nvstore_testing_buf_get, 2048); + zero_get_array(2048); + + actual_len_bytes = 0; + result = nvstore.get(11, 2048, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + + actual_len_bytes = 0; + result = nvstore.get(13, 3, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(3, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[1]), (uint8_t*)nvstore_testing_buf_get, 3); + zero_get_array(3); + + actual_len_bytes = 0; + result = nvstore.get(9, 20, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(20, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[3]), (uint8_t*)nvstore_testing_buf_get, 20); + zero_get_array(20); + + actual_len_bytes = 0; + result = nvstore.get(7, 0, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + + actual_len_bytes = 0; + result = nvstore.get(15, 15, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(15, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[2]), (uint8_t*)nvstore_testing_buf_get, 15); + zero_get_array(15); + + actual_len_bytes = 0; + result = nvstore.get(19, 12, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(12, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[2]), (uint8_t*)nvstore_testing_buf_get, 12); + zero_get_array(12); + + // change the data for all keys + result = nvstore.set(10, 15, &(nvstore_testing_buf_set[4])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(11, 27, &(nvstore_testing_buf_set[5])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(13, 7, &(nvstore_testing_buf_set[6])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(9, 0, &(nvstore_testing_buf_set[7])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(7, 48, &(nvstore_testing_buf_set[8])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(14, 109, &(nvstore_testing_buf_set[9])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + result = nvstore.set(15, 53, &(nvstore_testing_buf_set[10])); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + +#ifdef NVSTORE_TESTING + result = nvstore.force_garbage_collection(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); +#endif + + actual_len_bytes = 0; + result = nvstore.get(10, 15, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(15, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[4]), (uint8_t*)nvstore_testing_buf_get, 15); + zero_get_array(15); + + actual_len_bytes = 0; + result = nvstore.get(11, 27, nvstore_testing_buf_get, actual_len_bytes); // no care about the buf and len values + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(27, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[5]), (uint8_t*)nvstore_testing_buf_get, 27); + zero_get_array(27); + + actual_len_bytes = 0; + result = nvstore.get(13, 7, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(7, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[6]), (uint8_t*)nvstore_testing_buf_get, 7); + zero_get_array(7); + + actual_len_bytes = 0; + result = nvstore.get(9, 0, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + + actual_len_bytes = 0; + result = nvstore.get(7, 48, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(48, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[8]), (uint8_t*)nvstore_testing_buf_get, 48); + zero_get_array(48); + + actual_len_bytes = 0; + result = nvstore.get(14, 109, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(109, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[9]), (uint8_t*)nvstore_testing_buf_get, 109); + zero_get_array(109); + + actual_len_bytes = 0; + result = nvstore.get(15, 53, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(53, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[10]), (uint8_t*)nvstore_testing_buf_get, 53); + zero_get_array(53); + + result = nvstore.deinit(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + + actual_len_bytes = 0; + result = nvstore.probe(10, 15, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(15, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[4]), (uint8_t*)nvstore_testing_buf_get, 15); + + result = nvstore.init(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + + actual_len_bytes = 0; + result = nvstore.get(10, 15, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(15, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[4]), (uint8_t*)nvstore_testing_buf_get, 15); + zero_get_array(15); + + actual_len_bytes = 0; + result = nvstore.get(11, 27, nvstore_testing_buf_get, actual_len_bytes); // no care about the buf and len values + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(27, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[5]), (uint8_t*)nvstore_testing_buf_get, 27); + zero_get_array(27); + + actual_len_bytes = 0; + result = nvstore.get(13, 7, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(7, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[6]), (uint8_t*)nvstore_testing_buf_get, 7); + zero_get_array(7); + + actual_len_bytes = 0; + result = nvstore.get(9, 0, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(0, actual_len_bytes); + + actual_len_bytes = 0; + result = nvstore.get(7, 48, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(48, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[8]), (uint8_t*)nvstore_testing_buf_get, 48); + zero_get_array(48); + + actual_len_bytes = 0; + result = nvstore.get(14, 109, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(109, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[9]), (uint8_t*)nvstore_testing_buf_get, 109); + zero_get_array(109); + + actual_len_bytes = 0; + result = nvstore.get(15, 53, nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(53, actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)&(nvstore_testing_buf_set[10]), (uint8_t*)nvstore_testing_buf_get, 53); + zero_get_array(53); + + nvstore_int_flash_deinit(); +} + + +void nvstore_chunk_iterations_test() +{ + nvstore_int_flash_init(); + + uint32_t *data_array[MAX_KEYS]; + uint32_t data_size_array[MAX_KEYS] = {0}; + uint16_t actual_len_bytes = 0; + int result = NVSTORE_SUCCESS; + NVStore &nvstore = NVStore::get_instance(); + + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + data_array[i] = (uint32_t *) malloc(MAX_DATA_SIZE); + } + + result = nvstore.reset(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + for (uint32_t iter_num_index = 0; iter_num_index < NUM_OF_ITERATIONS_CHUNK_TEST; iter_num_index++) + { + memset(data_size_array, 0, sizeof(data_size_array)); + for (uint32_t i = 0; i < 50; i++) + { + uint32_t data_size = 1 + (rand() % MAX_DATA_SIZE); + uint16_t key = rand() % MAX_KEYS; + gen_random((uint8_t *)data_array[key] , data_size); + result = nvstore.set(key, data_size, data_array[key]); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + data_size_array[key] = data_size; + } + + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + if (data_size_array[i] != 0) + { + result = nvstore.get(i, data_size_array[i], nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(data_size_array[i], actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)(data_array[i]), (uint8_t*)nvstore_testing_buf_get, data_size_array[i]); + } + } + + } + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + free(data_array[i]); + } + nvstore_int_flash_deinit(); +} + + + +void nvstore_garbage_collection_test() +{ + nvstore_int_flash_init(); + + uint32_t nvstore_curr_size = MASTER_RECORD_SIZE; + int result; + NVStore &nvstore = NVStore::get_instance(); + + result = nvstore.reset(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); +#ifdef NVSTORE_TESTING + result = nvstore.force_garbage_collection(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); +#endif + uint32_t *data_array[MAX_KEYS]; + uint32_t data_size_array[MAX_KEYS] = {0}; + uint16_t actual_len_bytes = 0; + + for (uint32_t i = 0; i < MAX_KEYS; i++) + { + data_array[i] = (uint32_t *) malloc(MAX_DATA_SIZE); + } + + while (nvstore_curr_size < (1.5 * NVSTORE_SIZE)) + { + uint32_t data_size = 1 + (rand() % MAX_DATA_SIZE); + uint16_t key = rand() % MAX_KEYS; + gen_random((uint8_t *)data_array[key], data_size); + result = nvstore.set(key, data_size, data_array[key]); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + data_size_array[key] = data_size; + result = nvstore.get(key, data_size_array[key], nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(data_size_array[key], actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)(data_array[key]), (uint8_t*)nvstore_testing_buf_get, data_size_array[key]); + nvstore_curr_size += (8 + data_size_array[key]); + } + + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + if (data_size_array[i] != 0) + { + result = nvstore.get(i, data_size_array[i], nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(data_size_array[i], actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)(data_array[i]), (uint8_t*)nvstore_testing_buf_get, data_size_array[i]); + } + } + +#ifdef NVSTORE_TESTING + result = nvstore.force_garbage_collection(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); +#endif + + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + if (data_size_array[i] != 0) + { + result = nvstore.get(i, data_size_array[i], nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(data_size_array[i], actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)(data_array[i]), (uint8_t*)nvstore_testing_buf_get, data_size_array[i]); + } + } + + result = nvstore.init(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + if (data_size_array[i] != 0) + { + result = nvstore.get(i, data_size_array[i], nvstore_testing_buf_get, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(data_size_array[i], actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY((uint8_t*)(data_array[i]), (uint8_t*)nvstore_testing_buf_get, data_size_array[i]); + } + } + + for (uint16_t i = 0; i < MAX_KEYS; i++) + { + free(data_array[i]); + } + + nvstore_int_flash_deinit(); +} + +static void thread_test_check_key(uint16_t key, int check_probe) +{ + uint32_t get_buff[MAX_DATA_SIZE/sizeof(uint32_t)]; + int ret; + uint16_t actual_len_bytes; + int i, first, last; + NVStore &nvstore = NVStore::get_instance(); + + if (check_probe) { + ret = nvstore.probe(key, MAX_DATA_SIZE, get_buff, actual_len_bytes); + } + else { + ret = nvstore.get(key, MAX_DATA_SIZE, get_buff, actual_len_bytes); + } + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret); + TEST_ASSERT_NOT_EQUAL(0, actual_len_bytes); + + if (thr_test_num_threads == 1) { + first = thr_test_inds[key]; + last = thr_test_inds[key]; + } + else { + first = 0; + last = THR_TEST_NUM_BUFFS - 1; + } + + for (i = first; i <= last; i++) { + if (thr_test_sizes[key][i] != actual_len_bytes) + continue; + + if (!memcmp(thr_test_buffs[key][i], get_buff, actual_len_bytes)) + return; + } + + if (key == thr_test_last_key) { + if ((thr_test_sizes[key][thr_test_last_ind] == actual_len_bytes) && + (!memcmp(thr_test_buffs[key][thr_test_last_ind], get_buff, actual_len_bytes))) + return; + } + + // Got here - always assert + TEST_ASSERT(0); +} + +void thread_test_worker() +{ + int ret; + int buf_num, is_set; + uint16_t key; + NVStore &nvstore = NVStore::get_instance(); + + for (;;) { + key = rand() % MAX_KEYS; + is_set = rand() % 4; + + if (is_set) { + buf_num = rand() % THR_TEST_NUM_BUFFS; + thr_test_last_key = key; + thr_test_last_ind = buf_num; + ret = nvstore.set(key, thr_test_sizes[key][buf_num], thr_test_buffs[key][buf_num]); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret); + thr_test_inds[key] = buf_num; + } + else + thread_test_check_key(key, 0); + + osDelay(1); + } +} + +static void run_thread_test(int num_threads) +{ + int i; + uint16_t size, max_size; + uint16_t key; + int ret; + rtos::Thread **threads = new rtos::Thread*[num_threads]; + + NVStore &nvstore = NVStore::get_instance(); + + nvstore_int_flash_init(); + ret = nvstore.reset(); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret); + + max_size = MIN(flash_area_params[0].size, flash_area_params[1].size); + max_size = MIN(max_size / MAX_KEYS - 16, max_size); + max_size = MIN(max_size, MAX_DATA_SIZE); + + for (key = 0; key < MAX_KEYS; key++) { + for (i = 0; i < THR_TEST_NUM_BUFFS; i++) { + size = 1 + rand() % max_size; + thr_test_sizes[key][i] = size; + thr_test_buffs[key][i] = (uint32_t*) malloc(size); + thr_test_inds[key] = 0; + gen_random((uint8_t *)thr_test_buffs[key][i], size); + } + ret = nvstore.set(key, thr_test_sizes[key][0], thr_test_buffs[key][0]); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret); + } + + for (i = 0; i < num_threads; i++) { + threads[i] = new rtos::Thread(osPriorityBelowNormal, TEST_THREAD_STACK_SIZE); + threads[i]->start(callback(thread_test_worker)); + } + + rtos::Thread::wait(THR_TEST_NUM_SECS * 1000); + + for (i = 0; i < num_threads; i++) { + threads[i]->terminate(); + delete threads[i]; + } + + delete[] threads; + + rtos::Thread::wait(1000); + + nvstore_int_flash_deinit(); + nvstore.deinit(); + nvstore_int_flash_init(); + + thread_test_check_key(MAX_KEYS-1, 1); + + nvstore.init(); + + for (key = 0; key < MAX_KEYS; key++) { + thread_test_check_key(key, 0); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, ret); + } + + for (key = 0; key < MAX_KEYS; key++) { + for (i = 0; i < THR_TEST_NUM_BUFFS; i++) { + free(thr_test_buffs[key][i]); + } + } + nvstore_int_flash_deinit(); +} + + +void nvstore_single_thread_test() +{ + run_thread_test(1); +} + +void nvstore_multi_thread_test() +{ + run_thread_test(MAX_NUMBER_OF_THREADS); +} + + +utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) { + greentea_case_failure_abort_handler(source, reason); + return STATUS_CONTINUE; +} + +Case cases[] = { + Case("NVStore: Basic flash", nvstore_basic_flash_test, greentea_failure_handler), + Case("NVStore: Basic functionality", nvstore_basic_functionality_test, greentea_failure_handler), + Case("NVStore: Chunk iterations", nvstore_chunk_iterations_test, greentea_failure_handler), + Case("NVStore: Garbage collection" , nvstore_garbage_collection_test, greentea_failure_handler), + Case("NVStore: Single thread test", nvstore_single_thread_test, greentea_failure_handler), + Case("NVStore: Multiple thread test", nvstore_multi_thread_test, greentea_failure_handler), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { + GREENTEA_SETUP(120, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() { + return !Harness::run(specification); +} diff --git a/features/nvstore/mbed_lib.json b/features/nvstore/mbed_lib.json new file mode 100644 index 00000000000..7cff5eac21c --- /dev/null +++ b/features/nvstore/mbed_lib.json @@ -0,0 +1,40 @@ +{ + "name": "nvstore", + "config": { + "num_keys": { + "macro_name": "NVSTORE_MAX_KEYS", + "value": 16, + "help": "Maximal number of allowed NVStore keys" + }, + "area_1_address": { + "macro_name": "NVSTORE_AREA_1_ADDRESS", + "help": "Area 1 address" + }, + "area_1_size": { + "macro_name": "NVSTORE_AREA_1_SIZE", + "help": "Area 1 size" + }, + "area_2_address": { + "macro_name": "NVSTORE_AREA_2_ADDRESS", + "help": "Area 2 address" + }, + "area_2_size": { + "macro_name": "NVSTORE_AREA_2_SIZE", + "help": "Area 2 size" + } + }, + "target_overrides": { + "K64F": { + "area_1_address": "0xFE000", + "area_1_size" : "0x1000", + "area_2_address": "0xFF000", + "area_2_size" : "0x1000" + }, + "K82F": { + "area_1_address": "0x3E000", + "area_1_size" : "0x1000", + "area_2_address": "0x3F000", + "area_2_size" : "0x1000" + } + } +} diff --git a/features/nvstore/source/nvstore.cpp b/features/nvstore/source/nvstore.cpp new file mode 100644 index 00000000000..a472d48ab98 --- /dev/null +++ b/features/nvstore/source/nvstore.cpp @@ -0,0 +1,993 @@ +/* + * Copyright (c) 2018 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// ----------------------------------------------------------- Includes ----------------------------------------------------------- + +#include "nvstore.h" +#include "nvstore_int_flash_wrapper.h" +#include "nvstore_shared_lock.h" +#include "mbed_critical.h" +#include "mbed_assert.h" +#include "Thread.h" +#include +#include + +#if NVSTORE_ENABLED + +// --------------------------------------------------------- Definitions ---------------------------------------------------------- + +#define PR_ERR printf +#define PR_INFO printf +#define PR_DEBUG printf + +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#define MAX(a,b) ((a) > (b) ? (a) : (b)) + +#define DELETE_ITEM_FLAG 0x8000 +#define SET_ONCE_FLAG 0x4000 +#define HEADER_FLAG_MASK 0xF000 + +#define MASTER_RECORD_KEY 0xFFE +#define NO_KEY 0xFFF + +typedef struct { + uint16_t key_and_flags; + uint16_t length; + uint32_t mac; +} record_header_t __attribute__((aligned(4))); + + +#define OFFS_BY_KEY_AREA_MASK 0x80000000 +#define OFFS_BY_KEY_SET_ONCE_MASK 0x40000000 +#define OFFS_BY_KEY_FLAG_MASK 0xC0000000 +#define OFFS_BY_KEY_AREA_BIT_POS 31 +#define OFFS_BY_KEY_SET_ONCE_BIT_POS 30 + +#define FLASH_MINIMAL_PROG_UNIT 8 + +#define MASTER_RECORD_BLANK_FIELD_SIZE FLASH_MINIMAL_PROG_UNIT + +typedef struct { + uint16_t version; + uint16_t reserved1; + uint32_t reserved2; +} master_record_data_t __attribute__((aligned(4))); + +#define MASTER_RECORD_SIZE sizeof(master_record_data_t) + +#define MEDITATE_TIME_MS 1 + +typedef struct +{ + uint32_t address; + size_t size; +} nvstore_area_data_t; + +const nvstore_area_data_t flash_area_params[] = +{ + {NVSTORE_AREA_1_ADDRESS, NVSTORE_AREA_1_SIZE}, + {NVSTORE_AREA_2_ADDRESS, NVSTORE_AREA_2_SIZE} +}; + +typedef enum { + AREA_STATE_NONE = 0, + AREA_STATE_EMPTY, + AREA_STATE_VALID, +} area_state_e; + +#define INITIAL_CRC 0xFFFFFFFF + +// -------------------------------------------------- Local Functions Declaration ---------------------------------------------------- + +// -------------------------------------------------- Functions Implementation ---------------------------------------------------- + +// Safely increment an integer (depending on if we're thread safe or not) +// Parameters : +// value - [IN] Pointer to variable. +// size - [IN] Increment. +// Return : Value after increment. +int32_t safe_increment(uint32_t &value, uint32_t increment) +{ + return core_util_atomic_incr_u32(&value, increment); +} + +// Check whether a buffer is aligned. +// Parameters : +// buf - [IN] Data buffer. +// size - [IN] Alignment size. +// Return : Boolean result. +static inline int is_buf_aligned(const void *buf, uint32_t size) +{ + return (((size_t) buf / size * size) == (size_t) buf); +} + +// Align a value to a specified size. +// Parameters : +// val - [IN] Value. +// size - [IN] Size. +// Return : Aligned value. +static inline uint32_t align_up(uint32_t val, uint32_t size) +{ + return (((val-1) / size) + 1) * size; +} + +// CRC32 calculation. Supports "rolling" calculation (using the initial value). +// Parameters : +// init_crc - [IN] Initial CRC. +// data_len - [IN] Buffer's data length. +// data_buf - [IN] Data buffer. +// Return : CRC. +static uint32_t crc32(uint32_t init_crc, uint32_t data_len, uint8_t *data_buf) +{ + uint32_t i, j; + uint32_t crc, mask; + + crc = init_crc; + for (i = 0; i < data_len; i++) { + crc = crc ^ (uint32_t) (data_buf[i]); + for (j = 0; j < 8; j++) { + mask = -(crc & 1); + crc = (crc >> 1) ^ (0xEDB88320 & mask); + } + } + return crc; +} + +NVStore::NVStore() : _init_done(0), _init_attempts(0), _active_area(0), _max_keys(NVSTORE_MAX_KEYS), + _active_area_version(0), _free_space_offset(0), _size(0), _offset_by_key(0) +{ +} + +NVStore::~NVStore() +{ + if (_init_done) { + deinit(); + } +} + +uint16_t NVStore::get_max_keys() const +{ + return _max_keys; +} + +void NVStore::set_max_keys(uint16_t num_keys) +{ + MBED_ASSERT(num_keys < MASTER_RECORD_KEY); + _max_keys = num_keys; + // User is allowed to change number of types. As this affects init, need to deinitialize now. + // Don't call init right away - it is lazily called by get/set functions if needed. + deinit(); +} + +// Flash access helper functions, using area and offset notations + +// Read from flash, given area and offset. +// Parameters : +// area - [IN] Flash area. +// offset - [IN] Offset in area. +// len_bytes - [IN] Length in bytes. +// buf - [IN] Data buffer. +// Return : 0 on success. Error code otherwise. +int NVStore::flash_read_area(uint8_t area, uint32_t offset, uint32_t len_bytes, uint32_t *buf) +{ + return nvstore_int_flash_read(len_bytes, flash_area_params[area].address + offset, buf); +} + +// Write to flash, given area and offset. +// Parameters : +// area - [IN] Flash area. +// offset - [IN] Offset in area. +// len_bytes - [IN] Length in bytes. +// buf - [IN] Data buffer. +// Return : 0 on success. Error code otherwise. +int NVStore::flash_write_area(uint8_t area, uint32_t offset, uint32_t len_bytes, const uint32_t *buf) +{ + return nvstore_int_flash_write(len_bytes, flash_area_params[area].address + offset, buf); +} + +// Erase a flash area, given area. +// Parameters : +// area - [IN] Flash area. +// Return : 0 on success. Error code otherwise. +int NVStore::flash_erase_area(uint8_t area) +{ + return nvstore_int_flash_erase(flash_area_params[area].address, flash_area_params[area].size); +} + + +// Scan start of latest continuous empty area in flash area. +// Parameters : +// area - [IN] Flash area. +// offset - [OUT] Blank chunk offset. +// Return : 0 on success. Error code otherwise. +int NVStore::calc_empty_space(uint8_t area, uint32_t &offset) +{ + uint32_t buf[32]; + uint8_t *chbuf; + uint32_t i, j; + int ret; + + offset = _size; + for (i = 0; i < _size / sizeof(buf); i++) { + offset -= sizeof(buf); + ret = flash_read_area(area, offset, sizeof(buf), buf); + if (ret) + return ret; + chbuf = (uint8_t *) buf; + for (j = sizeof(buf); j > 0; j--) { + if (chbuf[j-1] != NVSTORE_BLANK_FLASH_VAL) { + offset += j; + return 0; + } + } + } + return 0; +} + +// Read a record from a given area and offset. +// Parameters : +// area - [IN] Flash area. +// offset - [IN] Record offset. +// buf_len_bytes - [IN] Length of user buffer in byte. +// buf - [IN] User buffer. +// actual_len_bytes +// - [Out] Actual length of returned data. +// validate_only - [IN] Just validate (don't return user data). +// valid - [Out] Is record valid. +// key - [Out] Record key. +// flags - [Out] Record flags. +// next_offset - [Out] If valid, offset of next record. +// Return : NVSTORE_SUCCESS on success. Error code otherwise. +int NVStore::read_record(uint8_t area, uint32_t offset, uint16_t buf_len_bytes, uint32_t *buf, + uint16_t &actual_len_bytes, int validate_only, int &valid, + uint16_t &key, uint16_t &flags, uint32_t &next_offset) +{ + uint32_t int_buf[32]; + uint32_t *buf_ptr; + uint32_t data_len, chunk_len; + int os_ret; + record_header_t header; + uint32_t crc = INITIAL_CRC; + + valid = 1; + + os_ret = flash_read_area(area, offset, sizeof(header), (uint32_t *) &header); + if (os_ret) { + return NVSTORE_READ_ERROR; + } + + crc = crc32(crc, sizeof(header) - sizeof(header.mac), (uint8_t *) &header); + + actual_len_bytes = 0; + key = header.key_and_flags & ~HEADER_FLAG_MASK; + flags = header.key_and_flags & HEADER_FLAG_MASK; + + if ((key >= _max_keys) && (key != MASTER_RECORD_KEY)) { + valid = 0; + return NVSTORE_SUCCESS; + } + + data_len = header.length; + offset += sizeof(header); + + // In case of validate only enabled, we use our internal buffer for data reading, + // instead of the user one. This allows us to use a smaller buffer, on which CRC + // is continuously calculated. + if (validate_only) { + buf_ptr = int_buf; + buf_len_bytes = sizeof(int_buf); + } + else { + if (data_len > buf_len_bytes) { + offset += data_len; + actual_len_bytes = data_len; + next_offset = align_up(offset, FLASH_MINIMAL_PROG_UNIT); + return NVSTORE_BUFF_TOO_SMALL; + } + buf_ptr = buf; + } + + while (data_len) { + chunk_len = MIN(data_len, buf_len_bytes); + os_ret = flash_read_area(area, offset, chunk_len, buf_ptr); + if (os_ret) { + return NVSTORE_READ_ERROR; + } + crc = crc32(crc, chunk_len, (uint8_t *) buf_ptr); + data_len -= chunk_len; + offset += chunk_len; + } + + if (header.mac != crc) { + valid = 0; + return NVSTORE_SUCCESS; + } + + actual_len_bytes = header.length; + next_offset = align_up(offset, FLASH_MINIMAL_PROG_UNIT); + + return NVSTORE_SUCCESS; +} + +// Write a record in a given area and offset. +// Parameters : +// area - [IN] Flash area. +// offset - [IN] Record offset. +// key - [IN] Record key. +// flags - [IN] Record flags +// data_len - [IN] Record's data length. +// data_buf - [IN] Record's data buffer. +// next_offset - [Out] offset of next record. +// Return : NVSTORE_SUCCESS on success. Error code otherwise. +int NVStore::write_record(uint8_t area, uint32_t offset, uint16_t key, uint16_t flags, + uint32_t data_len, const uint32_t *data_buf, uint32_t &next_offset) +{ + record_header_t header; + uint32_t crc = INITIAL_CRC; + int os_ret; + uint32_t write_len; + + header.key_and_flags = key | flags; + header.length = data_len; + header.mac = 0; // Satisfy compiler + crc = crc32(crc, sizeof(header) - sizeof(header.mac), (uint8_t *) &header); + if (data_len) + crc = crc32(crc, data_len, (uint8_t *) data_buf); + header.mac = crc; + + os_ret = flash_write_area(area, offset, sizeof(header), (uint32_t *)&header); + if (os_ret) { + return NVSTORE_WRITE_ERROR; + } + + if (data_len) { + offset += sizeof(header); + write_len = data_len; + os_ret = flash_write_area(area, offset, write_len, data_buf); + if (os_ret) { + return NVSTORE_WRITE_ERROR; + } + offset += data_len; + } + + next_offset = align_up(offset, FLASH_MINIMAL_PROG_UNIT); + return NVSTORE_SUCCESS; +} + +// Write a master record in a given area. +// Parameters : +// area - [IN] Flash area. +// version - [IN] Version. +// next_offset - [Out] offset of next record. +// Return : NVSTORE_SUCCESS on success. Error code otherwise. +int NVStore::write_master_record(uint8_t area, uint16_t version, uint32_t &next_offset) +{ + master_record_data_t master_rec; + + master_rec.version = version; + master_rec.reserved1 = 0; + master_rec.reserved2 = 0; + return write_record(area, 0, MASTER_RECORD_KEY, 0, sizeof(master_rec), + (uint32_t*) &master_rec, next_offset); +} + +// Copy a record from a given area and offset to another offset in the other area. +// Parameters : +// from_area - [IN] Flash area to copy from. +// from_offset - [IN] Record offset in current area. +// to_offset - [IN] Record offset in new area. +// next_offset - [Out] Offset of next record in the new area. +// Return : NVSTORE_SUCCESS on success. Error code otherwise. +int NVStore::copy_record(uint8_t from_area, uint32_t from_offset, uint32_t to_offset, + uint32_t &next_offset) +{ + uint32_t int_buf[32]; + uint32_t data_len, chunk_len; + int os_ret; + record_header_t header; + + // This function assumes that the source record is valid, so no need to recalculate CRC. + + os_ret = flash_read_area(from_area, from_offset, sizeof(header), (uint32_t *) &header); + if (os_ret) { + return NVSTORE_READ_ERROR; + } + + data_len = header.length; + + // No need to copy records whose flags indicate deletion + if (header.key_and_flags & DELETE_ITEM_FLAG) { + next_offset = align_up(to_offset, FLASH_MINIMAL_PROG_UNIT); + return NVSTORE_SUCCESS; + } + + // no need to align record size here, as it won't change the outcome of this condition + if (to_offset + sizeof(header) + data_len >= _size) { + return NVSTORE_FLASH_AREA_TOO_SMALL; + } + + os_ret = flash_write_area(1-from_area, to_offset, sizeof(header), (uint32_t *)&header); + if (os_ret) { + return NVSTORE_WRITE_ERROR; + } + + from_offset += sizeof(header); + to_offset += sizeof(header); + + while (data_len) { + chunk_len = MIN(data_len, sizeof(int_buf)); + os_ret = flash_read_area(from_area, from_offset, chunk_len, int_buf); + if (os_ret) { + return NVSTORE_READ_ERROR; + } + os_ret = flash_write_area(1-from_area, to_offset, chunk_len, int_buf); + if (os_ret) { + return NVSTORE_WRITE_ERROR; + } + + data_len -= chunk_len; + from_offset += chunk_len; + to_offset += chunk_len; + } + + next_offset = align_up(to_offset, FLASH_MINIMAL_PROG_UNIT); + return NVSTORE_SUCCESS; +} + +// Perform the garbage collection process. +// Parameters : +// key - [IN] Item's key. +// buf_len_bytes - [IN] Item length in bytes. +// buf - [IN] Pointer to user buffer. +// Return : NVSTORE_SUCCESS on success. Error code otherwise. +int NVStore::garbage_collection(uint16_t key, uint16_t flags, uint16_t buf_len_bytes, const uint32_t *buf) +{ + uint32_t curr_offset, new_area_offset, next_offset; + uint8_t curr_area; + int ret; + + new_area_offset = sizeof(record_header_t) + sizeof(master_record_data_t); + + // If GC is triggered by a set item request, we need to first write that item in the new location, + // otherwise we may either write it twice (if already included), or lose it in case we decide + // to skip it at garbage collection phase (and the system crashes). + if ((key != NO_KEY) && !(flags & DELETE_ITEM_FLAG)) { + ret = write_record(1 - _active_area, new_area_offset, key, 0, buf_len_bytes, buf, next_offset); + if (ret != NVSTORE_SUCCESS) { + PR_ERR("nvstore_garbage_collection: write_record failed with ret %d\n", ret); + return ret; + } + _offset_by_key[key] = new_area_offset | (1-_active_area) << OFFS_BY_KEY_AREA_BIT_POS | + (((flags & SET_ONCE_FLAG) != 0) << OFFS_BY_KEY_SET_ONCE_BIT_POS); + new_area_offset = next_offset; + } + + // Now iterate on all types, and copy the ones who have valid offsets (meaning that they exist) + // to the other area. + for (key = 0; key < _max_keys; key++) { + curr_offset = _offset_by_key[key]; + uint16_t save_flags = curr_offset & OFFS_BY_KEY_AREA_MASK; + curr_area = (uint8_t) (curr_offset >> OFFS_BY_KEY_AREA_BIT_POS) & 1; + curr_offset &= ~OFFS_BY_KEY_FLAG_MASK; + if ((!curr_offset) || (curr_area != _active_area)) + continue; + ret = copy_record(curr_area, curr_offset, new_area_offset, next_offset); + if (ret != NVSTORE_SUCCESS) { + PR_ERR("nvstore_garbage_collection: copy_record failed with ret %d\n", ret); + return ret; + } + _offset_by_key[key] = new_area_offset | (1-curr_area) << OFFS_BY_KEY_AREA_BIT_POS | save_flags; + new_area_offset = next_offset; + } + + // Now write master record, with version incremented by 1. + _active_area_version++; + ret = write_master_record(1 - _active_area, _active_area_version, next_offset); + if (ret != NVSTORE_SUCCESS) { + PR_ERR("nvstore_garbage_collection: write_master_record failed with ret %d\n", ret); + return ret; + } + + _free_space_offset = new_area_offset; + + // Only now we can switch to the new active area + _active_area = 1 - _active_area; + + // The older area doesn't concern us now. Erase it now. + if (flash_erase_area(1 - _active_area)) + return NVSTORE_WRITE_ERROR; + + return ret; +} + + +// Get API logics helper function. Serves both Get & Get item size APIs. +// Parameters : +// key - [IN] Item's key. +// buf_len_bytes - [IN] Item length in bytes. +// buf - [IN] Pointer to user buffer. +// actual_len_bytes - [OUT] Actual length of returned data. +// validate_only - [IN] Just validate (don't return user data). +// Return : NVSTORE_SUCCESS on success. Error code otherwise. +int NVStore::do_get(uint16_t key, uint16_t buf_len_bytes, uint32_t *buf, uint16_t &actual_len_bytes, + int validate_only) +{ + int ret = NVSTORE_SUCCESS; + uint32_t record_offset, next_offset; + uint8_t area; + uint16_t read_type, flags; + int valid; + + if (!_init_done) { + ret = init(); + if (ret != NVSTORE_SUCCESS) { + return ret; + } + } + + if (key >= _max_keys) { + return NVSTORE_BAD_VALUE; + } + + + if (!buf) + buf_len_bytes = 0; + + if (buf_len_bytes && !is_buf_aligned(buf, sizeof(uint32_t))) { + return NVSTORE_BUFF_NOT_ALIGNED; + } + + // We only have issues if we read during GC, so shared lock is required. + _lock.shared_lock(); + record_offset = _offset_by_key[key]; + + if (!record_offset) { + _lock.shared_unlock(); + return NVSTORE_NOT_FOUND; + } + + area = (uint8_t) (record_offset >> OFFS_BY_KEY_AREA_BIT_POS) & 1; + record_offset &= ~OFFS_BY_KEY_FLAG_MASK; + + ret = read_record(area, record_offset, buf_len_bytes, buf, + actual_len_bytes, validate_only, valid, + read_type, flags, next_offset); + if ((ret == NVSTORE_SUCCESS) && !valid) { + ret = NVSTORE_DATA_CORRUPT; + } + + _lock.shared_unlock(); + return ret; +} + +// Start of API functions + +int NVStore::get(uint16_t key, uint16_t buf_len_bytes, uint32_t *buf, uint16_t &actual_len_bytes) +{ + return do_get(key, buf_len_bytes, buf, actual_len_bytes, 0); +} + +int NVStore::get_item_size(uint16_t key, uint16_t &actual_len_bytes) +{ + return do_get(key, 0, NULL, actual_len_bytes, 1); +} + +int NVStore::do_set(uint16_t key, uint16_t buf_len_bytes, const uint32_t *buf, uint16_t flags) +{ + int ret = NVSTORE_SUCCESS; + uint32_t record_offset, record_size, new_free_space; + uint32_t next_offset; + uint8_t save_active_area; + + if (!_init_done) { + ret = init(); + if (ret != NVSTORE_SUCCESS) { + return ret; + } + } + + if (key >= _max_keys) { + return NVSTORE_BAD_VALUE; + } + + if (!buf) + buf_len_bytes = 0; + + if (buf_len_bytes && !is_buf_aligned(buf, sizeof(uint32_t))) { + return NVSTORE_BUFF_NOT_ALIGNED; + } + + if ((flags & DELETE_ITEM_FLAG) && !_offset_by_key[key]) { + return NVSTORE_NOT_FOUND; + } + + if (_offset_by_key[key] & OFFS_BY_KEY_SET_ONCE_MASK) { + return NVSTORE_ALREADY_EXISTS; + } + + // writers do not lock each other exclusively, but can operate in parallel. + // Shared lock is in order to prevent GC from operating (which uses exclusive lock). + _lock.shared_lock(); + + save_active_area = _active_area; + record_size = align_up(sizeof(record_header_t) + buf_len_bytes, FLASH_MINIMAL_PROG_UNIT); + + // Parallel operation of writers is allowed due to this atomic operation. This operation + // produces an offset on which each writer can work separately, without being interrupted + // by the other writer. The only mutual resource here is _free_space_offset - which + // gets the correct value because of this atomic increment. + new_free_space = safe_increment(_free_space_offset, record_size); + record_offset = new_free_space - record_size; + +retry: + // If we cross the area limit, we need to invoke GC. However, we should consider all the cases + // where writers work in parallel, and we only want the FIRST writer to invoke GC. + if (new_free_space >= _size) { + // In the case we have crossed the limit, but the initial offset was still before the limit, this + // means we are the first writer (common case). Exclusively lock _lock, and invoke GC. + if (record_offset < _size) { + _lock.promote(); + ret = garbage_collection(key, flags, buf_len_bytes, buf); + _lock.exclusive_unlock(); + return ret; + } + else { + // In the case we have crossed the limit, and the initial offset was also after the limit, + // this means we are not the first writer (uncommon case). Just wait for GC to complete. + // then retry the operation + _lock.shared_unlock(); + for (;;) { + rtos::Thread::wait(MEDITATE_TIME_MS); + // Retry operation + _lock.shared_lock(); + new_free_space = safe_increment(_free_space_offset, record_size); + goto retry; + } + } + } + + // Now write the record + ret = write_record(_active_area, record_offset, key, flags, buf_len_bytes, buf, next_offset); + if (ret != NVSTORE_SUCCESS) { + _lock.shared_unlock(); + return ret; + } + + // Update _offset_by_key. High bit indicates area. + if (flags & DELETE_ITEM_FLAG) + _offset_by_key[key] = 0; + else + _offset_by_key[key] = record_offset | (_active_area << OFFS_BY_KEY_AREA_BIT_POS) | + (((flags & SET_ONCE_FLAG) != 0) << OFFS_BY_KEY_SET_ONCE_BIT_POS); + + _lock.shared_unlock(); + + return NVSTORE_SUCCESS; +} + +int NVStore::set(uint16_t key, uint16_t buf_len_bytes, const uint32_t *buf) +{ + return do_set(key, buf_len_bytes, buf, 0); +} + +int NVStore::set_once(uint16_t key, uint16_t buf_len_bytes, const uint32_t *buf) +{ + return do_set(key, buf_len_bytes, buf, SET_ONCE_FLAG); +} + +int NVStore::remove(uint16_t key) +{ + return do_set(key, 0, NULL, DELETE_ITEM_FLAG); +} + +int NVStore::init() +{ + uint8_t area; + uint16_t key; + uint16_t flags; + int os_ret; + int ret = NVSTORE_SUCCESS; + uint32_t _init_attempts_val; + area_state_e area_state[NVSTORE_NUM_AREAS]; + uint32_t free_space_offset_of_area[NVSTORE_NUM_AREAS]; + uint16_t versions[NVSTORE_NUM_AREAS]; + uint32_t next_offset; + master_record_data_t master_rec; + uint16_t actual_len_bytes; + int valid; + + if (_init_done) + return NVSTORE_SUCCESS; + + // This handles the case that init function is called by more than one thread concurrently. + // Only the one who gets the value of 1 in _init_attempts_val will proceed, while others will + // wait until init is finished. + _init_attempts_val = safe_increment(_init_attempts, 1); + if (_init_attempts_val != 1) { + while(!_init_done) + rtos::Thread::wait(MEDITATE_TIME_MS); + return NVSTORE_SUCCESS; + } + + _offset_by_key = new uint32_t[_max_keys]; + MBED_ASSERT(_offset_by_key); + + for (key = 0; key < _max_keys; key++) { + _offset_by_key[key] = 0; + } + + _size = (uint32_t) -1; + nvstore_int_flash_init(); + for (area = 0; area < NVSTORE_NUM_AREAS; area++) { + area_state[area] = AREA_STATE_NONE; + free_space_offset_of_area[area] = 0; + versions[area] = 0; + + size_t sector_size = nvstore_int_flash_get_sector_size(flash_area_params[area].address); + MBED_ASSERT(flash_area_params[area].size >= sector_size); + MBED_ASSERT((flash_area_params[area].size % sector_size) == 0); + + _size = MIN(_size, flash_area_params[area].size); + + // Find start of empty space at the end of the area. This serves for both + // knowing whether the area is empty and for the record traversal at the end. + os_ret = calc_empty_space(area, free_space_offset_of_area[area]); + MBED_ASSERT(!os_ret); + + if (!free_space_offset_of_area[area]) { + area_state[area] = AREA_STATE_EMPTY; + continue; + } + + // Check validity of master record + ret = read_record(area, 0, sizeof(master_rec), (uint32_t *) &master_rec, + actual_len_bytes, 0, valid, + key, flags, next_offset); + MBED_ASSERT((ret == NVSTORE_SUCCESS) || (ret == NVSTORE_BUFF_TOO_SMALL)); + if (ret == NVSTORE_BUFF_TOO_SMALL) { + // Buf too small error means that we have a corrupt master record - + // treat it as such + valid = 0; + } + + // We have a non valid master record, in a non-empty area. Just erase the area. + if ((!valid) || (key != MASTER_RECORD_KEY)) { + os_ret = flash_erase_area(area); + MBED_ASSERT(!os_ret); + area_state[area] = AREA_STATE_EMPTY; + continue; + } + versions[area] = master_rec.version; + + // Place _free_space_offset after the master record (for the traversal, + // which takes place after this loop). + _free_space_offset = next_offset; + area_state[area] = AREA_STATE_VALID; + + // Unless both areas are valid (a case handled later), getting here means + // that we found our active area. + _active_area = area; + _active_area_version = versions[area]; + } + + // In case we have two empty areas, arbitrarily assign 0 to the active one. + if ((area_state[0] == AREA_STATE_EMPTY) && (area_state[1] == AREA_STATE_EMPTY)) { + _active_area = 0; + ret = write_master_record(_active_area, 1, _free_space_offset); + MBED_ASSERT(ret == NVSTORE_SUCCESS); + _init_done = 1; + return NVSTORE_SUCCESS; + } + + // In case we have two valid areas, choose the one having the higher version (or 0 + // in case of wrap around). Erase the other one. + if ((area_state[0] == AREA_STATE_VALID) && (area_state[1] == AREA_STATE_VALID)) { + if ((versions[0] > versions[1]) || (!versions[0])) + _active_area = 0; + else + _active_area = 1; + _active_area_version = versions[_active_area]; + os_ret = flash_erase_area(1 - _active_area); + MBED_ASSERT(!os_ret); + } + + // Traverse area until reaching the empty space at the end or until reaching a faulty record + while (_free_space_offset < free_space_offset_of_area[_active_area]) { + ret = read_record(_active_area, _free_space_offset, 0, NULL, + actual_len_bytes, 1, valid, + key, flags, next_offset); + MBED_ASSERT(ret == NVSTORE_SUCCESS); + + // In case we have a faulty record, this probably means that the system crashed when written. + // Perform a garbage collection, to make the the other area valid. + if (!valid) { + ret = garbage_collection(NO_KEY, 0, 0, NULL); + break; + } + if (flags & DELETE_ITEM_FLAG) + _offset_by_key[key] = 0; + else + _offset_by_key[key] = _free_space_offset | (_active_area << OFFS_BY_KEY_AREA_BIT_POS) | + (((flags & SET_ONCE_FLAG) != 0) << OFFS_BY_KEY_SET_ONCE_BIT_POS); + _free_space_offset = next_offset; + } + + _init_done = 1; + return NVSTORE_SUCCESS; +} + +int NVStore::deinit() +{ + if (_init_done) { + nvstore_int_flash_deinit(); + delete[] _offset_by_key; + } + + _init_attempts = 0; + _init_done = 0; + + return NVSTORE_SUCCESS; +} + +int NVStore::reset() +{ + uint8_t area; + int os_ret; + + // Erase both areas, and reinitialize the module. This is totally not thread safe, + // as init doesn't take the case of re-initialization into account. It's OK, as this function + // should only be called in pre-production cases. + for (area = 0; area < NVSTORE_NUM_AREAS; area++) { + os_ret = flash_erase_area(area); + if (os_ret) + return NVSTORE_WRITE_ERROR; + } + + deinit(); + return init(); +} + +uint32_t NVStore::size() +{ + if (!_init_done) { + init(); + } + + return _size; +} + +#ifdef NVSTORE_TESTING + +int NVStore::force_garbage_collection(void) +{ + int ret; + + if (!_init_done) { + ret = init(); + if (ret != NVSTORE_SUCCESS) + return ret; + } + + _lock.exclusive_lock(); + ret = garbage_collection(NO_KEY, 0, 0, NULL); + _lock.exclusive_release(); + return ret; +} + +#endif + + +int NVStore::probe(uint16_t key, uint16_t buf_len_bytes, uint32_t *buf, uint16_t &actual_len_bytes) +{ + + uint8_t area; + int sel_area = -1; + uint16_t read_type; + uint16_t flags; + int os_ret; + int ret = NVSTORE_SUCCESS, save_ret = NVSTORE_SUCCESS; + uint32_t free_space_offset_of_area = 0; + uint32_t curr_offset = 0, next_offset; + master_record_data_t master_rec; + uint16_t prev_version = 0; + uint16_t tmp_actual_len_bytes; + int valid; + int found = 0; + + for (area = 0; area < NVSTORE_NUM_AREAS; area++) { + // Check validity of master record + ret = read_record(area, 0, sizeof(master_rec), (uint32_t *) &master_rec, + actual_len_bytes, 0, valid, + read_type, flags, next_offset); + if (ret != NVSTORE_SUCCESS) { + if (ret == NVSTORE_BUFF_TOO_SMALL) { + // Buf too small error means that we have a corrupt master record - + // treat it as such, move to next area. + continue; + } + else { + PR_ERR("nvstore_probe_type: read_record failed with err code 0x%x\n", ret); + return ret; + } + } + + // We have a non valid master record, move to next area. + if ((!valid) || (read_type != MASTER_RECORD_KEY)) { + continue; + } + + // Use similar logic of init's way of handling two valid areas (without erasing them of course) + if ((area == 1) && (sel_area > 0)) { + if ((!prev_version) || (prev_version > master_rec.version)) { + // leave selected area as 0 + break; + } + } + + prev_version = master_rec.version; + curr_offset = next_offset; + sel_area = area; + } + + if (sel_area < 0) { + return NVSTORE_NOT_FOUND; + } + + area = (uint8_t) sel_area; + os_ret = calc_empty_space(area, free_space_offset_of_area); + if (os_ret) { + PR_ERR("nvstore_probe_type: calc_empty_space failed with err code 0x%lx\n", + (unsigned long) os_ret); + return NVSTORE_READ_ERROR; + } + + // Traverse area until reaching the empty space at the end or until reaching a faulty record + found = false; + while (curr_offset < free_space_offset_of_area) { + // first just verify, then read to user buffer + ret = read_record(area, curr_offset, 0, NULL, + tmp_actual_len_bytes, 1, valid, + read_type, flags, next_offset); + if (ret != NVSTORE_SUCCESS) { + PR_ERR("nvstore_probe_type: read_record failed with err code 0x%x\n", ret); + return ret; + } + if (!valid) { + break; + } + + if (read_type == key) { + if (flags & DELETE_ITEM_FLAG) { + found = false; + } + else { + save_ret = read_record(area, curr_offset, buf_len_bytes, buf, + actual_len_bytes, false, valid, + read_type, flags, next_offset); + found = true; + } + } + curr_offset = next_offset; + } + + if (!found) { + return NVSTORE_NOT_FOUND; + } + + return save_ret; +} + +#endif // NVSTORE_ENABLED diff --git a/features/nvstore/source/nvstore.h b/features/nvstore/source/nvstore.h new file mode 100644 index 00000000000..0d1eb4bfe55 --- /dev/null +++ b/features/nvstore/source/nvstore.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2018 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __NVSTORE_H +#define __NVSTORE_H + +// These addresses need to be configured according to board (in mbed_lib.json) +#if defined(NVSTORE_AREA_1_ADDRESS) && defined(NVSTORE_AREA_1_SIZE) && \ + defined(NVSTORE_AREA_2_ADDRESS) && defined(NVSTORE_AREA_2_SIZE) && \ + defined(DEVICE_FLASH) +#define NVSTORE_ENABLED 1 +#endif + +#if NVSTORE_ENABLED +#include +#include +#include "platform/NonCopyable.h" +#include "nvstore_int_flash_wrapper.h" +#include "nvstore_shared_lock.h" + +enum { + NVSTORE_SUCCESS = 0, + NVSTORE_READ_ERROR = -1, + NVSTORE_WRITE_ERROR = -2, + NVSTORE_NOT_FOUND = -3, + NVSTORE_DATA_CORRUPT = -4, + NVSTORE_BAD_VALUE = -5, + NVSTORE_BUFF_TOO_SMALL = -6, + NVSTORE_FLASH_AREA_TOO_SMALL = -7, + NVSTORE_OS_ERROR = -8, + NVSTORE_BUFF_NOT_ALIGNED = -9, + NVSTORE_ALREADY_EXISTS = -10, +}; + +#ifndef NVSTORE_MAX_KEYS +#define NVSTORE_MAX_KEYS 16 +#endif + +class NVStore : private mbed::NonCopyable { +public: + +/** + * @brief As a singleton, return the single instance of the class. + * Reason for this class being a singleton is the following: + * - Ease the use for users of this class not having to coordinate instantiations. + * - Lazy instantiation of internal data (which we can't achieve with simple static classes). + * + * @returns Singleton instance reference. + */ + static NVStore& get_instance() + { + // Use this implementation of singleton (Meyer's) rather than the one that allocates + // the instance on the heap, as it ensures destruction at program end (preventing warnings + // from memory checking tools such as valgrind). + static NVStore instance; + return instance; + } + + virtual ~NVStore(); + +/** + * @brief Returns number of keys. + * + * @returns Number of keys. + */ + uint16_t get_max_keys() const; + +/** + * @brief Set number of keys. + * + * @returns None. + */ + void set_max_keys(uint16_t num_keys); + +/** + * @brief Returns one item of data programmed on Flash, given key. + * + * @param[in] key Key of stored item. + * + * @param[in] buf_len_bytes Length of input buffer in bytes. + * + * @param[in] buf Buffer to store data on (must be aligned to a 32 bit boundary). + * + * @param[out] actual_len_bytes Actual length of returned data + * + * @returns NVSTORE_SUCCESS Value was found on Flash. + * NVSTORE_NOT_FOUND Value was not found on Flash. + * NVSTORE_READ_ERROR Physical error reading data. + * NVSTORE_DATA_CORRUPT Data on Flash is corrupt. + * NVSTORE_BAD_VALUE Bad value in any of the parameters. + * NVSTORE_BUFF_TOO_SMALL Not enough memory in user buffer. + * NVSTORE_BUFF_NOT_ALIGNED Buffer not aligned to 32 bits. + */ + int get(uint16_t key, uint16_t buf_len_bytes, uint32_t *buf, uint16_t &actual_len_bytes); + +/** + * @brief Returns one item of data programmed on Flash, given key. + * + * @param[in] key Key of stored item. + * + * @param[out] actual_len_bytes Actual length of item + * + * @returns NVSTORE_SUCCESS Value was found on Flash. + * NVSTORE_NOT_FOUND Value was not found on Flash. + * NVSTORE_READ_ERROR Physical error reading data. + * NVSTORE_DATA_CORRUPT Data on Flash is corrupt. + * NVSTORE_BAD_VALUE Bad value in any of the parameters. + */ + int get_item_size(uint16_t key, uint16_t &actual_len_bytes); + + +/** + * @brief Programs one item of data on Flash, given key. + * + * @param[in] key Key of stored item. + * + * @param[in] buf_len_bytes Item length in bytes. + * + * @param[in] buf Buffer containing data (must be aligned to a 32 bit boundary). + * + * @returns NVSTORE_SUCCESS Value was successfully written on Flash. + * NVSTORE_WRITE_ERROR Physical error writing data. + * NVSTORE_BAD_VALUE Bad value in any of the parameters. + * NVSTORE_FLASH_AREA_TOO_SMALL + * Not enough space in Flash area. + * NVSTORE_BUFF_NOT_ALIGNED Buffer not aligned to 32 bits. + * NVSTORE_ALREADY_EXISTS Item set with write once API already exists. + * + */ + int set(uint16_t key, uint16_t buf_len_bytes, const uint32_t *buf); + +/** + * @brief Programs one item of data on Flash, given key, allowing no consequent sets to this key. + * + * @param[in] key Key of stored item. + * + * @param[in] buf_len_bytes Item length in bytes. + * + * @param[in] buf Buffer containing data (must be aligned to a 32 bit boundary). + * + * @returns NVSTORE_SUCCESS Value was successfully written on Flash. + * NVSTORE_WRITE_ERROR Physical error writing data. + * NVSTORE_BAD_VALUE Bad value in any of the parameters. + * NVSTORE_FLASH_AREA_TOO_SMALL + * Not enough space in Flash area. + * NVSTORE_BUFF_NOT_ALIGNED Buffer not aligned to 32 bits. + * NVSTORE_ALREADY_EXISTS Item set with write once API already exists. + * + */ + int set_once(uint16_t key, uint16_t buf_len_bytes, const uint32_t *buf); + + +/** + * @brief Remove an item from flash. + * + * @param[in] key Key of stored item. + * + * @returns NVSTORE_SUCCESS Value was successfully written on Flash. + * NVSTORE_WRITE_ERROR Physical error writing data. + * NVSTORE_BAD_VALUE Bad value in any of the parameters. + * NVSTORE_FLASH_AREA_TOO_SMALL + * Not enough space in Flash area. + * NVSTORE_BUFF_NOT_ALIGNED Buffer not aligned to 32 bits. + * + */ + int remove(uint16_t key); + +/** + * @brief Initializes NVStore component. + * + * @returns NVSTORE_SUCCESS Initialization completed successfully. + * NVSTORE_READ_ERROR Physical error reading data. + * NVSTORE_WRITE_ERROR Physical error writing data (on recovery). + * NVSTORE_FLASH_AREA_TOO_SMALL + * Not enough space in Flash area. + */ + int init(); + +/** + * @brief Deinitializes NVStore component. + * Warning: This function is not thread safe and should not be called + * concurrently with other NVStore functions. + * + * @returns NVSTORE_SUCCESS Deinitialization completed successfully. + */ + int deinit(); + +/** + * @brief Reset Flash NVStore areas. + * Warning: This function is not thread safe and should not be called + * concurrently with other NVStore functions. + * + * @returns NVSTORE_SUCCESS Reset completed successfully. + * NVSTORE_READ_ERROR Physical error reading data. + * NVSTORE_WRITE_ERROR Physical error writing data. + */ + int reset(); + +/** + * @brief Return NVStore size (area size). + * + * @returns NVStore size. + */ + uint32_t size(); + + +#ifdef NVSTORE_TESTING + +/** + * @brief Initiate a forced garbage collection. + * + * @returns NVSTORE_SUCCESS GC completed successfully. + * NVSTORE_READ_ERROR Physical error reading data. + * NVSTORE_WRITE_ERROR Physical error writing data. + * NVSTORE_FLASH_AREA_TOO_SMALL + * Not enough space in Flash area. + */ + int force_garbage_collection(); +#endif + +/** + * @brief Returns one item of data programmed on Flash, given key. + * This is a self contained version of the get function (not requiring init), traversing the flash each time if triggered. + * This function is NOT thread safe. Its implementation is here for the case we want to minimise code size for clients + * such as boot loaders, performing minimal accesses to NVstore. In this case all other APIs can be commented out. + * + * @param[in] key Key of stored item (must be between 0-15). + * + * @param[in] buf_len_bytes Length of input buffer in bytes. + * + * @param[in] buf Buffer to store data on (must be aligned to a 32 bit boundary). + * + * @param[out] actual_len_bytes Actual length of returned data + * + * @returns NVSTORE_SUCCESS Value was found on Flash. + * NVSTORE_NOT_FOUND Value was not found on Flash. + * NVSTORE_READ_ERROR Physical error reading data. + * NVSTORE_DATA_CORRUPT Data on Flash is corrupt. + * NVSTORE_BAD_VALUE Bad value in any of the parameters. + * NVSTORE_BUFF_TOO_SMALL Not enough memory in user buffer. + * NVSTORE_BUFF_NOT_ALIGNED Buffer not aligned to 32 bits. + */ + int probe(uint16_t key, uint16_t buf_len_bytes, uint32_t *buf, uint16_t &actual_len_bytes); + +private: + int _init_done; + uint32_t _init_attempts; + uint8_t _active_area; + uint16_t _max_keys; + uint16_t _active_area_version; + uint32_t _free_space_offset; + uint32_t _size; + NVstoreSharedLock _lock; + uint32_t *_offset_by_key; + + // Private constructor, as class is a singleton + NVStore(); + + int flash_read_area(uint8_t area, uint32_t offset, uint32_t len_bytes, uint32_t *buf); + int flash_write_area(uint8_t area, uint32_t offset, uint32_t len_bytes, const uint32_t *buf); + int flash_erase_area(uint8_t area); + + int calc_empty_space(uint8_t area, uint32_t &offset); + + int read_record(uint8_t area, uint32_t offset, uint16_t buf_len_bytes, uint32_t *buf, + uint16_t &actual_len_bytes, int validate_only, int &valid, + uint16_t &key, uint16_t &flags, uint32_t &next_offset); + + int write_record(uint8_t area, uint32_t offset, uint16_t key, uint16_t flags, + uint32_t data_len, const uint32_t *data_buf, uint32_t &next_offset); + + int write_master_record(uint8_t area, uint16_t version, uint32_t &next_offset); + + int copy_record(uint8_t from_area, uint32_t from_offset, uint32_t to_offset, + uint32_t &next_offset); + + int garbage_collection(uint16_t key, uint16_t flags, uint16_t buf_len_bytes, const uint32_t *buf); + + int do_get(uint16_t key, uint16_t buf_len_bytes, uint32_t *buf, uint16_t &actual_len_bytes, + int validate_only); + + int do_set(uint16_t key, uint16_t buf_len_bytes, const uint32_t *buf, uint16_t flags); + +}; + +#endif // NVSTORE_ENABLED + +#endif + + diff --git a/features/nvstore/source/nvstore_int_flash_wrapper.cpp b/features/nvstore/source/nvstore_int_flash_wrapper.cpp new file mode 100644 index 00000000000..377f6bda7c7 --- /dev/null +++ b/features/nvstore/source/nvstore_int_flash_wrapper.cpp @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2018 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +// ----------------------------------------------------------- Includes ----------------------------------------------------------- + +#include "nvstore_int_flash_wrapper.h" +#include "nvstore_shared_lock.h" +#include "FlashIAP.h" +#include + +// --------------------------------------------------------- Definitions ---------------------------------------------------------- + +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#define MAX(a,b) ((a) > (b) ? (a) : (b)) + +#define MAX_PAGE_SIZE 16 + +static mbed::FlashIAP flash; + +static size_t get_page_size(void) +{ + return MIN(flash.get_page_size(), MAX_PAGE_SIZE); +} + +static int program_flash(size_t size, uint32_t address, const uint8_t *buffer) +{ + int ret; + uint32_t page_size, aligned_size, remainder; + uint8_t rem_buf[MAX_PAGE_SIZE]; + + page_size = get_page_size(); + remainder = size % page_size; + aligned_size = size - remainder; + if (aligned_size) { + ret = flash.program(buffer, address, aligned_size); + + if (ret) { + return -1; + } + address += aligned_size; + buffer += aligned_size; + } + + if (!remainder) { + return 0; + } + + memset(rem_buf, NVSTORE_BLANK_FLASH_VAL, page_size); + memcpy(rem_buf, buffer, remainder); + ret = flash.program(buffer, address, page_size); + if (ret) { + return -1; + } + + return 0; +} + +size_t nvstore_int_flash_get_sector_size(uint32_t address) +{ + return flash.get_sector_size(address); +} + +int nvstore_int_flash_init(void) +{ + int ret; + + ret = flash.init(); + if (ret) { + return -1; + } + + return 0; +} + +int nvstore_int_flash_deinit(void) +{ + int ret; + + ret = flash.deinit(); + if (ret) { + return -1; + } + + return 0; +} + +int nvstore_int_flash_read(size_t size, uint32_t address, uint32_t *buffer) +{ + int ret; + + if (!buffer) { + return -1; + } + + if (!size) + { + return -1; + } + ret = flash.read(buffer, address, size); + + if (ret) { + return -1; + } + + return 0; +} + + +int nvstore_int_flash_erase(uint32_t address, size_t size) +{ + int ret; + size_t sector_size = nvstore_int_flash_get_sector_size(address); + + if ((!size) || (size % sector_size) || (address % sector_size)) { + return -1; + } + + // No need to iterate over sectors - Flash driver's erase API does it for us + ret = flash.erase(address, sector_size); + if (ret) { + return -1; + } + + return 0; +} + + +int nvstore_int_flash_write(size_t size, uint32_t address, const uint32_t *buffer) +{ + int ret; + uint32_t page_size = get_page_size(); + uint32_t sector_size = nvstore_int_flash_get_sector_size(address); + uint32_t chunk; + uint8_t *buf = (uint8_t *) buffer; + + if ((!size) || (!buffer) || (address % page_size)) { + return -1; + } + + while (size) { + chunk = MIN(sector_size - (address % sector_size), size); + ret = program_flash(chunk, address, buf); + if (ret) { + return -1; + } + size -= chunk; + address += chunk; + buf += chunk; + sector_size = nvstore_int_flash_get_sector_size(address); + } + + return 0; +} + + diff --git a/features/nvstore/source/nvstore_int_flash_wrapper.h b/features/nvstore/source/nvstore_int_flash_wrapper.h new file mode 100644 index 00000000000..db3e32adec5 --- /dev/null +++ b/features/nvstore/source/nvstore_int_flash_wrapper.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2018 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#ifndef __NVSTORE_INT_FLASH_WRAPPER_H +#define __NVSTORE_INT_FLASH_WRAPPER_H + +#include + +/* + * This is a simple wrapper for the FlashIAP class, supplying basic flash functionality. + */ + +#define NVSTORE_NUM_AREAS 2 + +#define NVSTORE_BLANK_FLASH_VAL 0xFF + +/** + * @brief Returns flash sector size, given address. + * + * @param[in] address Flash address. + * + * @returns sector size (bytes). + */ +size_t nvstore_int_flash_get_sector_size(uint32_t address); + +/** + * @brief Initialises flash. + * + * @returns 0 on success, return code otherwise. + */ +int nvstore_int_flash_init(void); + +/** + * @brief Deinitialises flash. + * + * @returns 0 on success, return code otherwise. + */ +int nvstore_int_flash_deinit(void); + +/** + * @brief Reads from flash into user buffer, given address and size. + * + * @param[in] size Read size + * + * @param[in] address Flash address. + * + * @param[in] buffer User buffer. + * + * @returns 0 on success, return code otherwise. + */ +int nvstore_int_flash_read(size_t size, uint32_t address, uint32_t *buffer); + +/** + * @brief Erases a chain of sectors, given address and size. + * + * @param[in] size Erase size + * + * @param[in] address Flash address. + * + * @returns 0 on success, return code otherwise. + */ +int nvstore_int_flash_erase(uint32_t address, size_t size); + +/** + * @brief Writes from user buffer to the flash, given address and size. + * + * @param[in] size Write size + * + * @param[in] address Flash address. + * + * @param[in] buffer User buffer. + * + * @returns 0 on success, return code otherwise. + */ +int nvstore_int_flash_write(size_t size, uint32_t address, const uint32_t *buffer); + +#endif diff --git a/features/nvstore/source/nvstore_shared_lock.cpp b/features/nvstore/source/nvstore_shared_lock.cpp new file mode 100644 index 00000000000..a9301abc068 --- /dev/null +++ b/features/nvstore/source/nvstore_shared_lock.cpp @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2018 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +// ----------------------------------------------------------- Includes ----------------------------------------------------------- + +#include "nvstore_shared_lock.h" +#include "mbed_critical.h" +#include "Thread.h" +#include + + +// --------------------------------------------------------- Definitions ---------------------------------------------------------- + +#define MEDITATE_TIME_MS 1 + +// -------------------------------------------------- Functions Implementation ---------------------------------------------------- + + +NVstoreSharedLock::NVstoreSharedLock() : ctr(0) +{ +} + +NVstoreSharedLock::~NVstoreSharedLock() +{ +} + +int NVstoreSharedLock::shared_lock() +{ + mutex.lock(); + + core_util_atomic_incr_u32(&ctr, 1); + + mutex.unlock(); + return NVSTORE_OS_OK; +} + +int NVstoreSharedLock::shared_unlock() +{ + int val = core_util_atomic_decr_u32(&ctr, 1); + if (val < 0) { + return NVSTORE_OS_RTOS_ERR; + } + + return NVSTORE_OS_OK; +} + +int NVstoreSharedLock::exclusive_lock() +{ + mutex.lock(); + + while(ctr) + rtos::Thread::wait(MEDITATE_TIME_MS); + + return NVSTORE_OS_OK; +} + +int NVstoreSharedLock::exclusive_unlock() +{ + mutex.unlock(); + + return NVSTORE_OS_OK; +} + +int NVstoreSharedLock::promote() +{ + mutex.lock(); + while(ctr > 1) { + rtos::Thread::wait(MEDITATE_TIME_MS); + } + + if (ctr != 1) { + return NVSTORE_OS_RTOS_ERR; + } + + core_util_atomic_decr_u32(&ctr, 1); + + return NVSTORE_OS_OK; +} + diff --git a/features/nvstore/source/nvstore_shared_lock.h b/features/nvstore/source/nvstore_shared_lock.h new file mode 100644 index 00000000000..4439e958ef7 --- /dev/null +++ b/features/nvstore/source/nvstore_shared_lock.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2018 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#ifndef __NVSTORE_SHARED_LOCK_H +#define __NVSTORE_SHARED_LOCK_H + +#include +#include "rtos/Mutex.h" + +enum { + NVSTORE_OS_OK = 0, + NVSTORE_OS_RTOS_ERR = -1, + NVSTORE_OS_INV_ARG_ERR = -2, + NVSTORE_OS_NO_MEM_ERR = -3, +}; + +/** + * SharedLock, implements a shared/exclusive lock (AKA RW lock). + * This class doesn't implement this kind of lock in the classic manner (having two Mutexes and a counter). + * Instead, it uses one Mutex and one atomic counter, favouring the shared usage of the exclusive one. + */ + +class NVstoreSharedLock { +public: + NVstoreSharedLock(); + virtual ~NVstoreSharedLock(); + + /** + * @brief Locks the shared lock in a shared manner. + * + * @returns 0 for success, error code otherwise. + */ + int shared_lock(); + + /** + * @brief Unlocks the shared lock in a shared manner. + * + * @returns 0 for success, error code otherwise. + */ + int shared_unlock(); + + /** + * @brief Locks the shared lock in an exclusive manner. + * + * @returns 0 for success, error code otherwise. + */ + int exclusive_lock(); + + /** + * @brief Unlocks the shared lock in an exclusive manner. + * + * @returns 0 for success, error code otherwise. + */ + int exclusive_unlock(); + + /** + * @brief Promotes the shared lock from shared to exclusive. + * + * @returns 0 for success, error code otherwise. + */ + int promote(); + +private: + uint32_t ctr; + rtos::Mutex mutex; +}; + + +#endif diff --git a/features/unsupported/USBDevice/USBDevice/USBDevice.cpp b/features/unsupported/USBDevice/USBDevice/USBDevice.cpp index dc3efc96f4d..7ec03f2579b 100644 --- a/features/unsupported/USBDevice/USBDevice/USBDevice.cpp +++ b/features/unsupported/USBDevice/USBDevice/USBDevice.cpp @@ -187,27 +187,8 @@ bool USBDevice::controlOut(void) /* Check we should be transferring data OUT */ if (transfer.direction != HOST_TO_DEVICE) { -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) - /* - * We seem to have a pending device-to-host transfer. The host must have - * sent a new control request without waiting for us to finish processing - * the previous one. This appears to happen when we're connected to certain - * USB 3.0 host chip set. Do a zeor-length send to tell the host we're not - * ready for the new request - that'll make it resend - and then just - * pretend we were successful here so that the pending transfer can finish. - */ - uint8_t buf[1] = { 0 }; - EP0write(buf, 0); - - /* execute our pending ttransfer */ - controlIn(); - - /* indicate success */ - return true; - #else /* for other platforms, count on the HAL to handle this case */ return false; - #endif } /* Read from endpoint */ diff --git a/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp b/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp index b95437d219f..71bf5299008 100644 --- a/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp @@ -22,6 +22,7 @@ #include "fsl_common.h" #endif #include "USBHAL.h" +#include "mbed_critical.h" USBHAL * USBHAL::instance; @@ -64,6 +65,13 @@ typedef struct BDT { uint32_t address; // Addr } BDT; +typedef enum { + CTRL_XFER_READY, + CTRL_XFER_IN, + CTRL_XFER_NONE, + CTRL_XFER_OUT +} ctrl_xfer_t; + // there are: // * 4 bidirectionnal endpt -> 8 physical endpt // * as there are ODD and EVEN buffer -> 8*2 bdt @@ -73,6 +81,7 @@ uint8_t * endpoint_buffer[NUMBER_OF_PHYSICAL_ENDPOINTS * 2]; static uint8_t set_addr = 0; static uint8_t addr = 0; +static ctrl_xfer_t ctrl_xfer = CTRL_XFER_READY; static uint32_t Data1 = 0x55555555; @@ -223,11 +232,16 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran. bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket; bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf; - bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK; + bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_DTS_MASK; bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0; + if (log_endpoint == 0) { + // Prepare for setup packet + bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info |= BD_OWN_MASK; + } } - Data1 |= (1 << endpoint); + // First transfer will be a DATA0 packet + Data1 &= ~(1 << endpoint); return true; } @@ -239,13 +253,35 @@ void USBHAL::EP0setup(uint8_t *buffer) { } void USBHAL::EP0readStage(void) { - Data1 &= ~1UL; // set DATA0 - bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK); + // Not needed } void USBHAL::EP0read(void) { - uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0); - bdt[idx].byte_count = MAX_PACKET_SIZE_EP0; + if (ctrl_xfer == CTRL_XFER_READY) { + // Transfer is done so ignore call + return; + } + if (ctrl_xfer == CTRL_XFER_IN) { + ctrl_xfer = CTRL_XFER_READY; + // Control transfer with a data IN stage. + // The next packet received will be the status packet - an OUT packet using DATA1 + // + // PROBLEM: + // If a Setup packet is received after status packet of + // a Control In transfer has been received in the RX buffer + // but before the processor has had a chance the prepare + // this buffer for the Setup packet, the Setup packet + // will be dropped. + // + // WORKAROUND: + // Set data toggle to DATA0 so if the status stage of a + // Control In transfer arrives it will be ACKed by hardware + // but will be discarded without filling the RX buffer. + // This allows a subsequent SETUP packet to be stored + // without any processor intervention. + Data1 &= ~1UL; // set DATA0 + } + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); } uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { @@ -255,6 +291,15 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { } void USBHAL::EP0write(uint8_t *buffer, uint32_t size) { + if (ctrl_xfer == CTRL_XFER_READY) { + // Transfer is done so ignore call + return; + } + if ((ctrl_xfer == CTRL_XFER_NONE) || (ctrl_xfer == CTRL_XFER_OUT)) { + // Prepare for next setup packet + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); + ctrl_xfer = CTRL_XFER_READY; + } endpointWrite(EP0IN, buffer, size); } @@ -262,13 +307,34 @@ void USBHAL::EP0getWriteResult(void) { } void USBHAL::EP0stall(void) { + if (ctrl_xfer == CTRL_XFER_READY) { + // Transfer is done so ignore call + return; + } + ctrl_xfer = CTRL_XFER_READY; + core_util_critical_section_enter(); stallEndpoint(EP0OUT); + // Prepare for next setup packet + // Note - time between stalling and setting up the endpoint + // must be kept to a minimum to prevent a dropped SETUP + // packet. + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); + core_util_critical_section_exit(); } EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { - endpoint = PHY_TO_LOG(endpoint); - uint32_t idx = EP_BDT_IDX(endpoint, RX, 0); + uint8_t log_endpoint = PHY_TO_LOG(endpoint); + + uint32_t idx = EP_BDT_IDX(log_endpoint, RX, 0); bdt[idx].byte_count = maximumSize; + if ((Data1 >> endpoint) & 1) { + bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK; + } + else { + bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK; + } + + Data1 ^= (1 << endpoint); return EP_PENDING; } @@ -307,18 +373,14 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_ buffer[n] = ep_buf[n]; } - if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) { - if (setup && (buffer[6] == 0)) // if no setup data stage, - Data1 &= ~1UL; // set DATA0 - else - Data1 ^= (1 << endpoint); - } - - if (((Data1 >> endpoint) & 1)) { - bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK; - } - else { - bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK; + if (setup) { + // Record the setup type + if (buffer[6] == 0) { + ctrl_xfer = CTRL_XFER_NONE; + } else { + uint8_t in_xfer = (buffer[0] >> 7) & 1; + ctrl_xfer = in_xfer ? CTRL_XFER_IN : CTRL_XFER_OUT; + } } USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; @@ -351,9 +413,9 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) } if ((Data1 >> endpoint) & 1) { - bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK; - } else { bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK; + } else { + bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK; } Data1 ^= (1 << endpoint); @@ -450,7 +512,7 @@ void USBHAL::usbisr(void) { // setup packet if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) { - Data1 &= ~0x02; + Data1 |= 0x02 | 0x01; // set DATA1 for TX and RX bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK; bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK; diff --git a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp index 61dc87e0aac..6c047e8363b 100644 --- a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp @@ -275,11 +275,6 @@ uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { LPC_USB->USBCtrl = 0; - if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { - SIEselectEndpoint(endpoint); - SIEclearBuffer(); - } - return size; } @@ -431,7 +426,7 @@ void USBHAL::EP0setup(uint8_t *buffer) { } void USBHAL::EP0read(void) { - // Not required + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); } void USBHAL::EP0readStage(void) { @@ -456,6 +451,11 @@ void USBHAL::EP0stall(void) { } EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { + // Don't clear isochronous endpoints + if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { + SIEselectEndpoint(endpoint); + SIEclearBuffer(); + } return EP_PENDING; } @@ -590,6 +590,25 @@ void USBHAL::usbisr(void) { if (LPC_USB->USBDevIntSt & EP_SLOW) { // (Slow) Endpoint Interrupt + // Process IN packets before SETUP packets + // Note - order of OUT and SETUP does not matter as OUT packets + // are clobbered by SETUP packets and thus ignored. + // + // A SETUP packet can arrive at any time where as an IN packet is + // only sent after calling EP0write and an OUT packet after EP0read. + // The functions EP0write and EP0read are called only in response to + // a setup packet or IN/OUT packets sent in response to that + // setup packet. Therefore, if an IN or OUT packet is pending + // at the same time as a SETUP packet, the IN or OUT packet belongs + // to the previous control transfer and should either be processed + // before the SETUP packet (in the case of IN) or dropped (in the + // case of OUT as SETUP clobbers the OUT data). + if (LPC_USB->USBEpIntSt & EP(EP0IN)) { + selectEndpointClearInterrupt(EP0IN); + LPC_USB->USBDevIntClr = EP_SLOW; + EP0in(); + } + // Process each endpoint interrupt if (LPC_USB->USBEpIntSt & EP(EP0OUT)) { if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) { @@ -601,12 +620,6 @@ void USBHAL::usbisr(void) { LPC_USB->USBDevIntClr = EP_SLOW; } - if (LPC_USB->USBEpIntSt & EP(EP0IN)) { - selectEndpointClearInterrupt(EP0IN); - LPC_USB->USBDevIntClr = EP_SLOW; - EP0in(); - } - for (uint8_t num = 2; num < 16*2; num++) { if (LPC_USB->USBEpIntSt & EP(num)) { selectEndpointClearInterrupt(num); diff --git a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp index a5d7b444019..248dd63b19a 100644 --- a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp @@ -276,11 +276,6 @@ uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { LPC_USB->Ctrl = 0; - if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { - SIEselectEndpoint(endpoint); - SIEclearBuffer(); - } - return size; } @@ -436,7 +431,7 @@ void USBHAL::EP0setup(uint8_t *buffer) { } void USBHAL::EP0read(void) { - // Not required + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); } void USBHAL::EP0readStage(void) { @@ -461,6 +456,11 @@ void USBHAL::EP0stall(void) { } EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { + // Don't clear isochronous endpoints + if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { + SIEselectEndpoint(endpoint); + SIEclearBuffer(); + } return EP_PENDING; } @@ -595,6 +595,25 @@ void USBHAL::usbisr(void) { if (LPC_USB->DevIntSt & EP_SLOW) { // (Slow) Endpoint Interrupt + // Process IN packets before SETUP packets + // Note - order of OUT and SETUP does not matter as OUT packets + // are clobbered by SETUP packets and thus ignored. + // + // A SETUP packet can arrive at any time where as an IN packet is + // only sent after calling EP0write and an OUT packet after EP0read. + // The functions EP0write and EP0read are called only in response to + // a setup packet or IN/OUT packets sent in response to that + // setup packet. Therefore, if an IN or OUT packet is pending + // at the same time as a SETUP packet, the IN or OUT packet belongs + // to the previous control transfer and should either be processed + // before the SETUP packet (in the case of IN) or dropped (in the + // case of OUT as SETUP clobbers the OUT data). + if (LPC_USB->EpIntSt & EP(EP0IN)) { + selectEndpointClearInterrupt(EP0IN); + LPC_USB->DevIntClr = EP_SLOW; + EP0in(); + } + // Process each endpoint interrupt if (LPC_USB->EpIntSt & EP(EP0OUT)) { if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) { @@ -606,12 +625,6 @@ void USBHAL::usbisr(void) { LPC_USB->DevIntClr = EP_SLOW; } - if (LPC_USB->EpIntSt & EP(EP0IN)) { - selectEndpointClearInterrupt(EP0IN); - LPC_USB->DevIntClr = EP_SLOW; - EP0in(); - } - for (uint8_t num = 2; num < 16*2; num++) { if (LPC_USB->EpIntSt & EP(num)) { selectEndpointClearInterrupt(num); diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h index 7867b5431ec..84c535a04d7 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h @@ -140,12 +140,14 @@ USBHAL::USBHAL(void) { defined(TARGET_NUCLEO_F401RE) || \ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ defined(TARGET_NUCLEO_F429ZI) || \ defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_F446ZE) || \ defined(TARGET_NUCLEO_F767ZI) || \ defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_DISCO_F407VG) || \ + defined(TARGET_DISCO_F413ZH) || \ defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F746NG_OTG_FS) __HAL_RCC_GPIOA_CLK_ENABLE(); diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h index c9caa9c3d92..bb6cdda7408 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h @@ -22,12 +22,14 @@ defined(TARGET_NUCLEO_F401RE) || \ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ defined(TARGET_NUCLEO_F429ZI) || \ defined(TARGET_NUCLEO_F446RE) || \ defined(TARGET_NUCLEO_F446ZE) || \ defined(TARGET_NUCLEO_F767ZI) || \ defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_DISCO_F407VG) || \ + defined(TARGET_DISCO_F413ZH) || \ defined(TARGET_DISCO_F429ZI) || \ defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F746NG) || \ diff --git a/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/USBHAL_EFM32.cpp b/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/USBHAL_EFM32.cpp index ea424d97ec0..ba5b395fe06 100644 --- a/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/USBHAL_EFM32.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/USBHAL_EFM32.cpp @@ -23,8 +23,7 @@ #include "em_usbtypes.h" #include "em_usbhal.h" #include "em_usbd.h" - -#include "sleepmodes.h" +#include "mbed_sleep.h" enum USBISRCommand { CMD_HANDLED = 0, @@ -134,11 +133,6 @@ USBHAL::USBHAL(void) // be dynamically removed/reinstated to allow deeper sleep. usbhal_allow_em2(false); - // When in suspend / Vbus off we can go to EM2, but never below - // that as long as USB is being used. Despite the name the call here - // blocks entering modes _below_ EM2, but allows EM2. - blockSleepMode(EM2); - epCallback[EP0OUT] = NULL; epCallback[EP0IN ] = NULL; epCallback[EP1OUT] = &USBHAL::EP1_OUT_callback; @@ -193,17 +187,17 @@ USBHAL::~USBHAL(void) usbhal_free_buffers(); usbhal_allow_em2(true); - unblockSleepMode(EM2); } extern "C" void usbhal_allow_em2(bool allow_em2) { - if (allow_em2) { - // unblockSleepMode is safe to call even if we would unblock - // an already unblocked mode, so no checks here. - unblockSleepMode(EM1); - } else { - blockSleepMode(EM1); + static bool blocked = false; + if (allow_em2 && blocked) { + sleep_manager_unlock_deep_sleep(); + blocked = false; + } else if (!blocked) { + sleep_manager_lock_deep_sleep(); + blocked = true; } } diff --git a/features/unsupported/USBHost/USBHost/USBDeviceConnected.h b/features/unsupported/USBHost/USBHost/USBDeviceConnected.h index f74c4b6e4b9..88dd6dbbbfe 100644 --- a/features/unsupported/USBHost/USBHost/USBDeviceConnected.h +++ b/features/unsupported/USBHost/USBHost/USBDeviceConnected.h @@ -106,7 +106,7 @@ class USBDeviceConnected template inline void onDisconnect(uint8_t intf_nb, T* tptr, void (T::*mptr)(void)) { if ((mptr != NULL) && (tptr != NULL)) { - intf[intf_nb].detach.attach(tptr, mptr); + intf[intf_nb].detach = callback(tptr, mptr); } } @@ -118,7 +118,7 @@ class USBDeviceConnected */ inline void onDisconnect(uint8_t intf_nb, void (*fn)(void)) { if (fn != NULL) { - intf[intf_nb].detach.attach(fn); + intf[intf_nb].detach = fn; } } diff --git a/features/unsupported/USBHost/USBHost/USBEndpoint.h b/features/unsupported/USBHost/USBHost/USBEndpoint.h index 5b1287f4215..d0d9fd42313 100644 --- a/features/unsupported/USBHost/USBHost/USBEndpoint.h +++ b/features/unsupported/USBHost/USBHost/USBEndpoint.h @@ -89,7 +89,7 @@ class USBEndpoint template inline void attach(T* tptr, void (T::*mptr)(void)) { if((mptr != NULL) && (tptr != NULL)) { - rx.attach(tptr, mptr); + rx = callback(tptr, mptr); } } @@ -100,7 +100,7 @@ class USBEndpoint */ inline void attach(void (*fptr)(void)) { if(fptr != NULL) { - rx.attach(fptr); + rx = fptr; } } diff --git a/features/unsupported/USBHost/USBHost/USBHost.cpp b/features/unsupported/USBHost/USBHost/USBHost.cpp index b9424f73f1c..704e28001c6 100644 --- a/features/unsupported/USBHost/USBHost/USBHost.cpp +++ b/features/unsupported/USBHost/USBHost/USBHost.cpp @@ -88,11 +88,14 @@ void USBHost::usb_process() /* check that hub is connected to root port */ if (usb_msg->hub_parent) { /* a hub device must be present */ +#if MAX_HUB_NB + for (k = 0; k < MAX_HUB_NB; k++) { if ((&hubs[k] == usb_msg->hub_parent) && (hub_in_use[k])) { hub_unplugged=false; } } +#endif } else { hub_unplugged = false; } @@ -312,7 +315,7 @@ USBHost::USBHost() : usbThread(osPriorityNormal, USB_THREAD_STACK) } #endif - usbThread.start(this, &USBHost::usb_process); + usbThread.start(callback(this, &USBHost::usb_process)); } USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost) diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 64e2ac4af6f..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" - diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/USBHALHost_STM_TARGET.h deleted file mode 100644 index 466535271ac..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,20 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#define USBHALHOST_64pins -#include "USBHALHost_STM_144_64pins.h" - diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/USBHALHost_STM_TARGET.h deleted file mode 100644 index 7616b6c400a..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* 144 pins boards */ -#if defined(TARGET_NUCLEO_F429ZI) || defined(TARGET_NUCLEO_F446ZE) || defined(TARGET_NUCLEO_F207ZG) \ -|| defined(TARGET_NUCLEO_F767ZI) || defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_F412ZG) \ -|| defined(TARGET_DISCO_F413ZH) -#include "USBHALHost_STM_144_64pins.h" -#endif - -/* 64 pins boards */ -#if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_F411RE) -#define USBHALHOST_64pins -#include "USBHALHost_STM_144_64pins.h" -#endif - -/* DISCO board */ - -#ifdef TARGET_DISCO_F429ZI -#include "USBHALHost_DISCOF429ZI.h" -#endif - -#ifdef TARGET_DISCO_L476VG -#include "USBHALHost_DISCOL476VG.h" -#endif diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 64e2ac4af6f..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" - diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/USBHALHost_DISCOF429ZI.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/USBHALHost_DISCOF429ZI.h deleted file mode 100644 index 720f7324ce9..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/USBHALHost_DISCOF429ZI.h +++ /dev/null @@ -1,112 +0,0 @@ -/* mbed USBHost Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef USBHALHOST_DISCOF429ZI -#define USBHALHOST_DISCOF429ZI - -#define USBHAL_IRQn OTG_HS_IRQn - -#define HCCA_SIZE sizeof(HCD_HandleTypeDef) -#define ED_SIZE sizeof(HCED) -#define TD_SIZE sizeof(HCTD) - -#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE)) -/* STM device FS have 11 channels (definition is for 60 channels) */ -static volatile uint8_t usb_buf[TOTAL_SIZE]; -typedef struct -{ - /* store the request ongoing on each endpoit */ - /* 1st field of structure avoid giving knowledge of all structure to - * endpoint */ - volatile uint32_t addr[MAX_ENDPOINT]; - USBHALHost *inst; - void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent); - void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr); - void (USBHALHost::*transferCompleted)(volatile uint32_t addr); -}USBHALHost_Private_t; -/* CONFIGURATION for USB_VBUS - * on 64 bits board PC_0 is used (0 VBUS on, 1 VBUS off) - * on 144 pins board PG_6 is used ( 1 VBUS on, 0 VBUS on) - */ -static gpio_t gpio_vbus; - -#define VBUS_OFF 1 -#define VBUS_ON 0 -#define USB_VBUS_CONFIG \ - do {__HAL_RCC_GPIOC_CLK_ENABLE();\ - gpio_init_out_ex(&gpio_vbus, PC_4, VBUS_OFF);\ - }while(0); - - -void usb_vbus( uint8_t state) -{ - if(state == 0) - { - gpio_write(&gpio_vbus, VBUS_OFF); - } - else - { - gpio_write(&gpio_vbus, VBUS_ON); - } - wait(0.2); -} - - -USBHALHost::USBHALHost() { - gpio_t pin_vbus; - instHost = this; - HCD_HandleTypeDef *hhcd; - USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t); - memset(HALPriv, 0, sizeof(USBHALHost_Private_t)); - memInit(); - memset((void*)usb_hcca, 0, HCCA_SIZE); - hhcd = (HCD_HandleTypeDef *)usb_hcca; - hhcd->Instance = USB_OTG_HS; - hhcd->pData = (void*)HALPriv; - hhcd->Init.Host_channels = 11; - /* for now failed with dma */ - hhcd->Init.dma_enable = 0; - hhcd->Init.speed = HCD_SPEED_HIGH; - hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; - hhcd->Init.use_external_vbus = 1; - HALPriv->inst = this; - HALPriv->deviceConnected = &USBHALHost::deviceConnected; - HALPriv->deviceDisconnected = &USBHALHost::deviceDisconnected; - HALPriv->transferCompleted = &USBHALHost::transferCompleted; - for (int i = 0; i < MAX_ENDPOINT; i++) { - edBufAlloc[i] = false; - HALPriv->addr[i]=(uint32_t)-1; - } - for (int i = 0; i < MAX_TD; i++) { - tdBufAlloc[i] = false; - } - /* Configure USB HS GPIOs */ - __HAL_RCC_GPIOB_CLK_ENABLE(); - - /*USB DM and DP */ - pin_function(PB_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_OTG_HS_FS)); - pin_function(PB_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_OTG_HS_FS)); - /* Configure VBUS Pin */ - gpio_init_in(&pin_vbus, PB_13); - /* Configure POWER_SWITCH IO pin */ - USB_VBUS_CONFIG; - /* Enable USB HS Clocks */ - __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); - - /* Set USBFS Interrupt priority */ - HAL_NVIC_SetPriority(USBHAL_IRQn, 5, 0); - NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr); -} -#endif diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/USBHALHost_STM_TARGET.h deleted file mode 100644 index a2c64dec537..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_DISCOF429ZI.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/USBHALHost_STM_TARGET.h deleted file mode 100644 index 29d3666cf2b..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/USBHALHost_STM_TARGET.h deleted file mode 100644 index 29d3666cf2b..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/USBHALHost_STM_TARGET.h deleted file mode 100644 index 29d3666cf2b..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/USBHALHost_STM_TARGET.h deleted file mode 100644 index 64e2ac4af6f..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" - diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 29d3666cf2b..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 29d3666cf2b..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/USBHALHost_STM_TARGET.h deleted file mode 100644 index 64e2ac4af6f..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_STM_144_64pins.h" - diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/USBHALHost_DISCO_L475VG_IOT01A.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/USBHALHost_DISCO_L475VG_IOT01A.h deleted file mode 100644 index 21860af5361..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/USBHALHost_DISCO_L475VG_IOT01A.h +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright (c) 2017 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#ifndef USBHALHOST_DISCO_L475VG_IOT01A -#define USBHALHOST_DISCO_L475VG_IOT01A - -#define USBHAL_IRQn OTG_FS_IRQn - -#define HCCA_SIZE sizeof(HCD_HandleTypeDef) -#define ED_SIZE sizeof(HCED) -#define TD_SIZE sizeof(HCTD) - -#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE)) - -/* STM device FS have 11 channels (definition is for 60 channels) */ -static volatile uint8_t usb_buf[TOTAL_SIZE]; - -typedef struct { - /* store the request ongoing on each endpoit */ - /* 1st field of structure avoid giving knowledge of all structure to - * endpoint */ - volatile uint32_t addr[MAX_ENDPOINT]; - USBHALHost *inst; - void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent); - void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr); - void (USBHALHost::*transferCompleted)(volatile uint32_t addr); -} USBHALHost_Private_t; - -static gpio_t gpio_powerpin; - -#define USB_POWER_OFF 1 -#define USB_POWER_ON 0 -#define USB_POWERPIN_CONFIG {gpio_init_out_ex(&gpio_powerpin, PD_12, USB_POWER_OFF);} - - -void usb_vbus( uint8_t state) -{ - if (state == 0) { - gpio_write(&gpio_powerpin, USB_POWER_OFF); - } else { - gpio_write(&gpio_powerpin, USB_POWER_ON); - } - wait(0.2); -} - - -USBHALHost::USBHALHost() -{ - instHost = this; - HCD_HandleTypeDef *hhcd; - USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t); - - memset(HALPriv, 0, sizeof(USBHALHost_Private_t)); - memInit(); - memset((void*)usb_hcca, 0, HCCA_SIZE); - - hhcd = (HCD_HandleTypeDef *)usb_hcca; - hhcd->Instance = USB_OTG_FS; - hhcd->pData = (void*)HALPriv; - hhcd->Init.Host_channels = 11; - - /* for now failed with dma */ - hhcd->Init.dma_enable = 0; - hhcd->Init.speed = HCD_SPEED_FULL; - hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; - hhcd->Init.use_external_vbus = 1; - - HALPriv->inst = this; - HALPriv->deviceConnected = &USBHALHost::deviceConnected; - HALPriv->deviceDisconnected = &USBHALHost::deviceDisconnected; - HALPriv->transferCompleted = &USBHALHost::transferCompleted; - - for (int i = 0; i < MAX_ENDPOINT; i++) { - edBufAlloc[i] = false; - HALPriv->addr[i]=(uint32_t)-1; - } - - for (int i = 0; i < MAX_TD; i++) { - tdBufAlloc[i] = false; - } - - __HAL_RCC_PWR_CLK_ENABLE(); - -#ifdef TARGET_STM32L4 - HAL_PWREx_EnableVddUSB(); -#endif - - /* Configure USB GPIOs */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM pin - pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP pin - pin_function(PA_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS pin - - /* Configure USB POWER pin */ - USB_POWERPIN_CONFIG; - - /* Enable USB FS Clocks */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - - /* Set USBFS Interrupt priority */ - HAL_NVIC_SetPriority(USBHAL_IRQn, 5, 0); - NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr); -} - -#endif // USBHALHOST_DISCO_L475VG_IOT01A diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/USBHALHost_STM_TARGET.h deleted file mode 100644 index cfa73918229..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_DISCO_L475VG_IOT01A.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/USBHALHost_DISCOL476VG.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/USBHALHost_DISCOL476VG.h deleted file mode 100644 index 3e443f55ca1..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/USBHALHost_DISCOL476VG.h +++ /dev/null @@ -1,118 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#ifndef USBHALHOST_DISCOL476VG -#define USBHALHOST_DISCOL476VG - -#define USBHAL_IRQn OTG_FS_IRQn - -#define HCCA_SIZE sizeof(HCD_HandleTypeDef) -#define ED_SIZE sizeof(HCED) -#define TD_SIZE sizeof(HCTD) - -#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE)) -/* STM device FS have 11 channels (definition is for 60 channels) */ -static volatile uint8_t usb_buf[TOTAL_SIZE]; -typedef struct -{ - /* store the request ongoing on each endpoit */ - /* 1st field of structure avoid giving knowledge of all structure to - * endpoint */ - volatile uint32_t addr[MAX_ENDPOINT]; - USBHALHost *inst; - void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent); - void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr); - void (USBHALHost::*transferCompleted)(volatile uint32_t addr); -}USBHALHost_Private_t; - -static gpio_t gpio_vbus; - -#define VBUS_OFF 1 -#define VBUS_ON 0 -#define USB_VBUS_CONFIG \ - do {\ - gpio_init_out_ex(&gpio_vbus, PC_9, VBUS_OFF);\ - }while(0); - - -void usb_vbus( uint8_t state) -{ - if(state == 0) - { - gpio_write(&gpio_vbus, VBUS_OFF); - } - else - { - gpio_write(&gpio_vbus, VBUS_ON); - } - wait(0.2); -} - - -USBHALHost::USBHALHost() { - instHost = this; - HCD_HandleTypeDef *hhcd; - USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t); - memset(HALPriv, 0, sizeof(USBHALHost_Private_t)); - memInit(); - memset((void*)usb_hcca, 0, HCCA_SIZE); - hhcd = (HCD_HandleTypeDef *)usb_hcca; - hhcd->Instance = USB_OTG_FS; - hhcd->pData = (void*)HALPriv; - hhcd->Init.Host_channels = 11; - /* for now failed with dma */ - hhcd->Init.dma_enable = 0; - hhcd->Init.speed = HCD_SPEED_FULL; - hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; - hhcd->Init.use_external_vbus = 1; - HALPriv->inst = this; - HALPriv->deviceConnected = &USBHALHost::deviceConnected; - HALPriv->deviceDisconnected = &USBHALHost::deviceDisconnected; - HALPriv->transferCompleted = &USBHALHost::transferCompleted; - for (int i = 0; i < MAX_ENDPOINT; i++) { - edBufAlloc[i] = false; - HALPriv->addr[i]=(uint32_t)-1; - } - for (int i = 0; i < MAX_TD; i++) { - tdBufAlloc[i] = false; - } - __HAL_RCC_PWR_CLK_ENABLE(); -#ifdef TARGET_STM32L4 - HAL_PWREx_EnableVddUSB(); -#endif - - /* Configure USB HS GPIOs */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - - /*USB DM and DP */ - pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); - pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); - - /* Configure VBUS Pin */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); - /* Configure POWER_SWITCH IO pin */ - USB_VBUS_CONFIG; - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable USB FS Clocks */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - /* Set USBFS Interrupt priority */ - HAL_NVIC_SetPriority(USBHAL_IRQn, 5, 0); - NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr); -} -#endif diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 655bcb53f53..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#include "USBHALHost_DISCOL476VG.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 1615a0c29f6..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#define USBHALHOST_64pins -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/USBHALHost_STM_TARGET.h b/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/USBHALHost_STM_TARGET.h deleted file mode 100644 index 1615a0c29f6..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/USBHALHost_STM_TARGET.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016 mbed.org, MIT License -* -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software -* and associated documentation files (the "Software"), to deal in the Software without -* restriction, including without limitation the rights to use, copy, modify, merge, publish, -* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all copies or -* substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ -#define USBHALHOST_64pins -#include "USBHALHost_STM_144_64pins.h" diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp index 012889e1b1d..ec9d9785d88 100644 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp @@ -20,7 +20,7 @@ #include "dbg.h" #include "pinmap.h" -#include "USBHALHost_STM_TARGET.h" +#include "USBHALHost_STM.h" void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) { diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h new file mode 100644 index 00000000000..4f8b5c58a49 --- /dev/null +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h @@ -0,0 +1,284 @@ +/* Copyright (c) 2017 mbed.org, MIT License +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* and associated documentation files (the "Software"), to deal in the Software without +* restriction, including without limitation the rights to use, copy, modify, merge, publish, +* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ +#ifndef USBHALHOST_STM_H +#define USBHALHOST_STM_H + +#if defined(TARGET_DISCO_F746NG) +#if (MBED_CONF_TARGET_USB_SPEED == 1) // Defined in json configuration file +#define TARGET_DISCO_F746NG_HS +#else +#define TARGET_DISCO_F746NG_FS +#endif +#endif + +#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI) +#define USBHAL_IRQn OTG_HS_IRQn +#else +#define USBHAL_IRQn OTG_FS_IRQn +#endif + +#define HCCA_SIZE sizeof(HCD_HandleTypeDef) +#define ED_SIZE sizeof(HCED) +#define TD_SIZE sizeof(HCTD) + +#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT * ED_SIZE) + (MAX_TD * TD_SIZE)) + +/* STM device FS have 11 channels (definition is for 60 channels) */ +static volatile uint8_t usb_buf[TOTAL_SIZE]; + +typedef struct { + /* store the request ongoing on each endpoit */ + /* 1st field of structure avoid giving knowledge of all structure to + * endpoint */ + volatile uint32_t addr[MAX_ENDPOINT]; + USBHALHost *inst; + void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent); + void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr); + void (USBHALHost::*transferCompleted)(volatile uint32_t addr); +} USBHALHost_Private_t; + +static gpio_t gpio_powerpin; + +// NUCLEO_64 boards +#if defined(TARGET_NUCLEO_F401RE) || \ + defined(TARGET_NUCLEO_F411RE) || \ + defined(TARGET_NUCLEO_F446RE) || \ + defined(TARGET_NUCLEO_L476RG) || \ + defined(TARGET_NUCLEO_L486RG) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOC_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PC_0, USB_POWER_OFF);} + +// NUCLEO_144 boards +#elif defined(TARGET_NUCLEO_F207ZG) || \ + defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ + defined(TARGET_NUCLEO_F429ZI) || \ + defined(TARGET_NUCLEO_F439ZI) || \ + defined(TARGET_NUCLEO_F446ZE) || \ + defined(TARGET_NUCLEO_F767ZI) || \ + defined(TARGET_NUCLEO_F746ZG) || \ + defined(TARGET_NUCLEO_F756ZG) || \ + defined(TARGET_NUCLEO_F767ZI) +#define USB_POWER_ON 1 +#define USB_POWER_OFF 0 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOG_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PG_6, USB_POWER_OFF);} + +// DISCOVERY boards +#elif defined(TARGET_DISCO_F413ZH) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOG_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PG_8, USB_POWER_OFF);} + +#elif defined(TARGET_DISCO_F469NI) +#define USB_POWER_ON 1 +#define USB_POWER_OFF 0 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOB_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PB_2, USB_POWER_OFF);} + +#elif defined(TARGET_DISCO_F746NG_FS) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOD_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PD_5, USB_POWER_OFF);} + +#elif defined(TARGET_DISCO_F746NG_HS) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {} + +#elif defined(TARGET_DISCO_F769NI) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {} + +#elif defined(TARGET_DISCO_L475VG_IOT01A) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOD_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PD_12, USB_POWER_OFF);} + +#elif defined(TARGET_DISCO_L476VG) +#define USB_POWER_ON 0 +#define USB_POWER_OFF 1 +#define USB_POWERPIN_CONFIG {__HAL_RCC_GPIOC_CLK_ENABLE();gpio_init_out_ex(&gpio_powerpin, PC_9, USB_POWER_OFF);} + +#else +#error "USB power pin is not configured !" +#endif + + +void usb_vbus( uint8_t state) +{ + if (state == 0) { + gpio_write(&gpio_powerpin, USB_POWER_OFF); + } else { + gpio_write(&gpio_powerpin, USB_POWER_ON); + } + wait(0.2); +} + + +USBHALHost::USBHALHost() +{ + instHost = this; + HCD_HandleTypeDef *hhcd = {0}; + USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t); + + memset(HALPriv, 0, sizeof(USBHALHost_Private_t)); + memInit(); + memset((void*)usb_hcca, 0, HCCA_SIZE); + + hhcd = (HCD_HandleTypeDef *)usb_hcca; + hhcd->pData = (void*)HALPriv; + +#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI) + hhcd->Instance = USB_OTG_HS; + hhcd->Init.speed = HCD_SPEED_HIGH; + hhcd->Init.phy_itface = HCD_PHY_ULPI; +#else + hhcd->Instance = USB_OTG_FS; + hhcd->Init.speed = HCD_SPEED_FULL; + hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; +#endif + + hhcd->Init.Host_channels = 11; + hhcd->Init.dma_enable = 0; // for now failed with dma + hhcd->Init.low_power_enable = 0; + hhcd->Init.Sof_enable = 0; + hhcd->Init.vbus_sensing_enable = 0; + hhcd->Init.use_external_vbus = 1; + hhcd->Init.lpm_enable = 0; + + HALPriv->inst = this; + HALPriv->deviceConnected = &USBHALHost::deviceConnected; + HALPriv->deviceDisconnected = &USBHALHost::deviceDisconnected; + HALPriv->transferCompleted = &USBHALHost::transferCompleted; + + for (int i = 0; i < MAX_ENDPOINT; i++) { + edBufAlloc[i] = false; + HALPriv->addr[i] = (uint32_t)-1; + } + + for (int i = 0; i < MAX_TD; i++) { + tdBufAlloc[i] = false; + } + + __HAL_RCC_PWR_CLK_ENABLE(); + +#ifdef TARGET_STM32L4 + HAL_PWREx_EnableVddUSB(); +#endif + + // Configure USB pins +#if defined(TARGET_NUCLEO_F401RE) || \ + defined(TARGET_NUCLEO_F411RE) || \ + defined(TARGET_NUCLEO_F446RE) || \ + defined(TARGET_NUCLEO_L476RG) || \ + defined(TARGET_NUCLEO_L486RG) || \ + defined(TARGET_NUCLEO_F207ZG) || \ + defined(TARGET_NUCLEO_F412ZG) || \ + defined(TARGET_NUCLEO_F413ZH) || \ + defined(TARGET_NUCLEO_F429ZI) || \ + defined(TARGET_NUCLEO_F439ZI) || \ + defined(TARGET_NUCLEO_F446ZE) || \ + defined(TARGET_NUCLEO_F767ZI) || \ + defined(TARGET_NUCLEO_F746ZG) || \ + defined(TARGET_NUCLEO_F756ZG) || \ + defined(TARGET_NUCLEO_F767ZI) || \ + defined(TARGET_DISCO_F413ZH) || \ + defined(TARGET_DISCO_F469NI) || \ + defined(TARGET_DISCO_L475VG_IOT01A) + __HAL_RCC_GPIOA_CLK_ENABLE(); + pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM + pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP + pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID + pin_function(PA_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS + +#elif defined(TARGET_DISCO_F746NG_FS) + __HAL_RCC_GPIOA_CLK_ENABLE(); + pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM + pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP + pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID + __HAL_RCC_GPIOJ_CLK_ENABLE(); + pin_function(PJ_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS + +#elif defined(TARGET_DISCO_F746NG_HS) + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK + pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0 + pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1 + pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2 + pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3 + pin_function(PB_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D4 + pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5 + pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6 + pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7 + pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP + pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT + pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR + +#elif defined(TARGET_DISCO_F769NI) + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK + pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0 + pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1 + pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2 + pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3 + pin_function(PB_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D4 + pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5 + pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6 + pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7 + pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP + pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT + pin_function(PI_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR + +#elif defined(TARGET_DISCO_L476VG) + __HAL_RCC_GPIOA_CLK_ENABLE(); + pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM + pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP + pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID + pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS + +#else +#error "USB pins are not configured !" +#endif + + // Configure USB POWER pin + USB_POWERPIN_CONFIG; + + // Enable clocks + __HAL_RCC_SYSCFG_CLK_ENABLE(); + +#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI) + __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); +#else + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); +#endif + + // Set USB interrupt + HAL_NVIC_SetPriority(USBHAL_IRQn, 5, 0); + NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr); +} + +#endif // USBHALHOST_STM_H diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM_144_64pins.h b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM_144_64pins.h deleted file mode 100644 index 305b928d532..00000000000 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM_144_64pins.h +++ /dev/null @@ -1,121 +0,0 @@ -/* mbed USBHost Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef USBHALHOST_STM32_144_64 -#define USBHALHOST_STM32_144_64 - -#define USBHAL_IRQn OTG_FS_IRQn - -#define HCCA_SIZE sizeof(HCD_HandleTypeDef) -#define ED_SIZE sizeof(HCED) -#define TD_SIZE sizeof(HCTD) - -#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE)) -/* STM device FS have 11 channels (definition is for 60 channels) */ -static volatile uint8_t usb_buf[TOTAL_SIZE]; -typedef struct -{ - /* store the request ongoing on each endpoit */ - /* 1st field of structure avoid giving knowledge of all structure to - * endpoint */ - volatile uint32_t addr[MAX_ENDPOINT]; - USBHALHost *inst; - void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent); - void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr); - void (USBHALHost::*transferCompleted)(volatile uint32_t addr); -}USBHALHost_Private_t; - -/* CONFIGURATION for USB_VBUS - * on 64 bits board PC_0 is used (0 VBUS on, 1 VBUS off) - * on 144 pins board PG_6 is used ( 1 VBUS on, 0 VBUS on) - */ -static gpio_t gpio_vbus; - -#if defined(USBHALHOST_64pins) -#define VBUS_OFF 1 -#define VBUS_ON 0 -#define USB_VBUS_CONFIG \ - do {__HAL_RCC_GPIOC_CLK_ENABLE();\ - gpio_init_out_ex(&gpio_vbus, PC_0, VBUS_OFF);\ - }while(0); -#else -#define VBUS_OFF 0 -#define VBUS_ON 1 -#define USB_VBUS_CONFIG \ - do {__HAL_RCC_GPIOG_CLK_ENABLE();\ - gpio_init_out_ex(&gpio_vbus, PG_6, VBUS_OFF);\ - }while(0); -#endif - -void usb_vbus( uint8_t state) -{ - if(state == 0) - { - gpio_write(&gpio_vbus, VBUS_OFF); - } - else - { - gpio_write(&gpio_vbus, VBUS_ON); - } - wait(0.2); -} - -USBHALHost::USBHALHost() { - instHost = this; - HCD_HandleTypeDef *hhcd; - USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t); - memset(HALPriv, 0, sizeof(USBHALHost_Private_t)); - memInit(); - memset((void*)usb_hcca, 0, HCCA_SIZE); - hhcd = (HCD_HandleTypeDef *)usb_hcca; - hhcd->Instance = USB_OTG_FS; - hhcd->pData = (void*)HALPriv; - hhcd->Init.Host_channels = 11; - hhcd->Init.speed = HCD_SPEED_FULL; - hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; - HALPriv->inst = this; - HALPriv->deviceConnected = &USBHALHost::deviceConnected; - HALPriv->deviceDisconnected = &USBHALHost::deviceDisconnected; - HALPriv->transferCompleted = &USBHALHost::transferCompleted; - for (int i = 0; i < MAX_ENDPOINT; i++) { - edBufAlloc[i] = false; - HALPriv->addr[i]=(uint32_t)-1; - } - for (int i = 0; i < MAX_TD; i++) { - tdBufAlloc[i] = false; - } - __HAL_RCC_PWR_CLK_ENABLE(); -#ifdef TARGET_STM32L4 - HAL_PWREx_EnableVddUSB(); -#endif - /* Configure USB FS GPIOs */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - - /*USB DM and DP */ - pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); - pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); - /*USB ID */ - pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - /* Configure POWER_SWITCH IO pin */ - USB_VBUS_CONFIG; - /* Enable USB FS Clocks */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - - /* Set USBFS Interrupt priority */ - HAL_NVIC_SetPriority(OTG_FS_IRQn, 6, 0); -} -#endif diff --git a/features/unsupported/tests/mbed/can/main.cpp b/features/unsupported/tests/mbed/can/main.cpp index 6f58a3d18cf..6ecc386eaac 100644 --- a/features/unsupported/tests/mbed/can/main.cpp +++ b/features/unsupported/tests/mbed/can/main.cpp @@ -21,7 +21,8 @@ CAN can1(PD_0, PD_1); defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F103RB) || \ defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_L476RG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) + defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) || \ + defined(TARGET_NUCLEO_F413ZH) CAN can1(PA_11, PA_12); #elif defined(TARGET_DISCO_F469NI) ||defined(TARGET_DISCO_F746NG) CAN can1(PB_8, PB_9); @@ -36,7 +37,7 @@ CAN can2(p30, p29); #elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_DISCO_F746NG) + defined(TARGET_DISCO_F746NG) || defined(TARGET_NUCLEO_F413ZH) CAN can2(PB_5, PB_6); #endif char counter = 0; diff --git a/features/unsupported/tests/mbed/can_interrupt/main.cpp b/features/unsupported/tests/mbed/can_interrupt/main.cpp index 16e0709b696..289f569fdbd 100644 --- a/features/unsupported/tests/mbed/can_interrupt/main.cpp +++ b/features/unsupported/tests/mbed/can_interrupt/main.cpp @@ -21,7 +21,8 @@ CAN can1(PD_0, PD_1); defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F103RB) || \ defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_L476RG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) + defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC) || \ + defined(TARGET_NUCLEO_F413ZH) CAN can1(PA_11, PA_12); #elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) CAN can1(PB_8, PB_9); @@ -36,7 +37,7 @@ CAN can2(p30, p29); #elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_DISCO_F746NG) + defined(TARGET_DISCO_F746NG) || defined(TARGET_NUCLEO_F413ZH) CAN can2(PB_5, PB_6); #endif char counter = 0; diff --git a/features/unsupported/tests/mbed/can_loopback/main.cpp b/features/unsupported/tests/mbed/can_loopback/main.cpp index 76a6947d13e..f67377b723f 100644 --- a/features/unsupported/tests/mbed/can_loopback/main.cpp +++ b/features/unsupported/tests/mbed/can_loopback/main.cpp @@ -20,7 +20,8 @@ CAN can1(P5_9, P5_10); defined(TARGET_DISCO_F429ZI) || \ defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_DISCO_L476VG) || defined(TARGET_DISCO_L475VG_IOT01A) || \ defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || \ - defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L432KC) + defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L432KC) || \ + defined(TARGET_NUCLEO_F413ZH) CAN can1(PA_11, PA_12); #elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) || \ defined(TARGET_NUCLEO_F446ZE) || defined(TARGET_NUCLEO_F103RB) || \ diff --git a/hal/critical_section_api.h b/hal/critical_section_api.h new file mode 100644 index 00000000000..d5cb24296f4 --- /dev/null +++ b/hal/critical_section_api.h @@ -0,0 +1,107 @@ +/** \addtogroup hal */ +/** @{*/ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CRITICAL_SECTION_API_H +#define MBED_CRITICAL_SECTION_API_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup hal_critical Critical Section HAL functions + * @{ + */ + +/** + * Mark the start of a critical section + * + * This function will be called by core_util_critical_section_enter() each time + * the application requests to enter a critical section. The purpose of the + * critical section is to ensure mutual-exclusion synchronisation of the + * processor by preventing any change in processor control, the default + * behaviour requires storing the state of interrupts in the system before + * disabling them. + * + * The critical section code supports nesting. When a thread has entered a + * critical section it can make additional calls to + * core_util_critical_section_enter() without deadlocking itself. The critical + * section driver API tracks the number of nested calls to the critical section. + * The critical section will only be exited when + * core_util_critical_section_exit() has been called once for each time it + * entered the critical section. + * + * On the first call to enter a critical section this function MUST store the + * state of any interrupts or other application settings it will modify to + * facilitate the critical section. + * + * Each successive call to enter the critical section MUST ignore storing or + * modifying any application state. + * + * The default implementation of this function which will save the current state + * of interrupts before disabling them. This implementation can be found in + * mbed_critical_section_api.c. This behaviour is can be overridden on a per + * platform basis by providing a different implementation within the correct + * targets directory. + */ +void hal_critical_section_enter(void); + + +/** Mark the end of a critical section. + * + * The purpose of this function is to restore any state that was modified upon + * entering the critical section, allowing other threads or interrupts to change + * the processor control. + * + * This function will be called once by core_util_critical_section_exit() per + * critical section on last call to exit. When called, the application MUST + * restore the saved interrupt/application state that was saved when entering + * the critical section. + * + * There is a default implementation of this function, it will restore the state + * of interrupts that were previously saved when hal_critical_section_enter was + * first called, this implementation can be found in + * mbed_critical_section_api.c. This behaviour is overridable by providing a + * different function implementation within the correct targets directory. + */ +void hal_critical_section_exit(void); + + +/** Determine if the application is currently running in a critical section + * + * The purpose of this function is to inform the caller whether or not the + * application is running in a critical section. This is done by checking if + * the current interrupt state has been saved in the underlying implementation, + * this could also be done by checking the state of the interrupts at the time + * of calling. + * + * @return True if running in a critical section, false if not. + */ +bool hal_in_critical_section(void); + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif // MBED_CRITICAL_SECTION_API_H + +/** @}*/ diff --git a/hal/device_key_api.h b/hal/device_key_api.h new file mode 100644 index 00000000000..6c12d36e27c --- /dev/null +++ b/hal/device_key_api.h @@ -0,0 +1,70 @@ + +/** \addtogroup hal */ +/** @{*/ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * DEVICE_KEY - Root of Trust when provided by the platform is a secret and unique per-device value 128 or 256 bits long that will be used to generate additional keys. + * DEVICE_KEY API to be used to generate keys is presented by DEVICE_KEY driver. If DEVICE_KEY is not implemented in a platform, DEVICE_KEY driver will generate it from random. + * + */ + +#ifndef MBED_DEVICE_KEY_API_H +#define MBED_DEVICE_KEY_API_H + +#include "stddef.h" +#include "stdint.h" +#include "fsl_common.h" + + +#if DEVICE_DEVKEY +#define DEVICE_KEY_LEN 16 /* DEVICE_KEY key length in bytes */ + + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \defgroup hal_device_key DEVICE_KEY hal functions + * @{ + */ + +/** Get data for DeviceKey from the platform +* +* @param output The pointer to an output array +* @param length in: The size of output data buffer out: Size of actual data written +* @return 0 success, -1 fail +*/ +int device_key_get_value(uint32_t *output, size_t *length); + +/** Return the size of the device key in bytes + * + * @retrun the device key length + */ +int device_key_get_size_in_bytes(); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/** @}*/ diff --git a/hal/mbed_critical_section_api.c b/hal/mbed_critical_section_api.c new file mode 100644 index 00000000000..c8c19d7e4b6 --- /dev/null +++ b/hal/mbed_critical_section_api.c @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" +#include "hal/critical_section_api.h" +#include "platform/mbed_assert.h" +#include "platform/mbed_toolchain.h" + +#include + +static volatile bool critical_interrupts_enabled = false; +static volatile bool state_saved = false; + +static bool are_interrupts_enabled(void) +{ +#if defined(__CORTEX_A9) + return ((__get_CPSR() & 0x80) == 0); +#else + return ((__get_PRIMASK() & 0x1) == 0); +#endif +} + + +MBED_WEAK void hal_critical_section_enter(void) +{ + const bool interrupt_state = are_interrupts_enabled(); + + __disable_irq(); + + if (state_saved == true) { + return; + } + + critical_interrupts_enabled = interrupt_state; + state_saved = true; +} + +MBED_WEAK void hal_critical_section_exit(void) +{ +#ifndef FEATURE_UVISOR + // Interrupts must be disabled on invoking an exit from a critical section + MBED_ASSERT(!are_interrupts_enabled()); +#endif + state_saved = false; + + // Restore the IRQs to their state prior to entering the critical section + if (critical_interrupts_enabled == true) { + __enable_irq(); + } +} + +MBED_WEAK bool hal_in_critical_section(void) +{ + return (state_saved == true); +} diff --git a/logo.png b/logo.png new file mode 100644 index 00000000000..e869282c5a3 Binary files /dev/null and b/logo.png differ diff --git a/platform/CircularBuffer.h b/platform/CircularBuffer.h index c6de50f066d..abf24c40ac9 100644 --- a/platform/CircularBuffer.h +++ b/platform/CircularBuffer.h @@ -17,8 +17,26 @@ #define MBED_CIRCULARBUFFER_H #include "platform/mbed_critical.h" +#include "platform/mbed_assert.h" namespace mbed { + +namespace internal { +/* Detect if CounterType of the Circular buffer is of unsigned type. */ +template +struct is_unsigned { static const bool value = false; }; +template<> +struct is_unsigned { static const bool value = true; }; +template<> +struct is_unsigned { static const bool value = true; }; +template<> +struct is_unsigned { static const bool value = true; }; +template<> +struct is_unsigned { static const bool value = true; }; +template<> +struct is_unsigned { static const bool value = true; }; +}; + /** \addtogroup platform */ /** @{*/ /** @@ -29,11 +47,22 @@ namespace mbed { /** Templated Circular buffer class * * @note Synchronization level: Interrupt safe + * @note CounterType must be unsigned and consistent with BufferSize */ template class CircularBuffer { public: CircularBuffer() : _head(0), _tail(0), _full(false) { + MBED_STATIC_ASSERT( + internal::is_unsigned::value, + "CounterType must be unsigned" + ); + + MBED_STATIC_ASSERT( + (sizeof(CounterType) >= sizeof(uint32_t)) || + (BufferSize < (((uint64_t) 1) << (sizeof(CounterType) * 8))), + "Invalid BufferSize for the CounterType" + ); } ~CircularBuffer() { @@ -140,4 +169,3 @@ class CircularBuffer { } #endif - diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h index cb619769c8e..05649ba1985 100644 --- a/platform/CriticalSectionLock.h +++ b/platform/CriticalSectionLock.h @@ -33,14 +33,25 @@ namespace mbed { * Usage: * @code * - * void f() { - * // some code here - * { - * CriticalSectionLock lock; - * // Code in this block will run with interrupts disabled - * } - * // interrupts will be restored to their previous state + * // RAII style usage + * unsigned int atomic_counter_increment(unsigned int &counter) { + * CriticalSectionLock lock; + * // Code in this block will run with interrupts disabled + * // Interrupts will be restored to their previous state automatically + * // at the end of function scope + * return ++counter; * } + * + * // free locking usage + * unsigned int atomic_counter_decrement(unsigned int &counter) { + * CriticalSectionLock::enable(); + * // Code in this block will run with interrupts disabled + * counter--; + * CriticalSectionLock::disable(); // need explicitly to disable critical section lock + * // interrupts will be restored to their previous state here + * return counter; + * } + * * @endcode */ class CriticalSectionLock { @@ -56,20 +67,40 @@ class CriticalSectionLock { } /** Mark the start of a critical section - * + * */ + MBED_DEPRECATED_SINCE("mbed-os-5.8", + "This function is inconsistent with RAII and is being removed in the future." + "Replaced by static function CriticalSectionLock::enable.") void lock() { core_util_critical_section_enter(); } /** Mark the end of a critical section - * + * */ + MBED_DEPRECATED_SINCE("mbed-os-5.8", + "This function is inconsistent with RAII and is being removed in the future." + "Replaced by static function CriticalSectionLock::disable.") void unlock() { core_util_critical_section_exit(); } + + /** Mark the start of a critical section + */ + static void enable() + { + core_util_critical_section_enter(); + } + + /** Mark the end of a critical section + */ + static void disable() + { + core_util_critical_section_exit(); + } }; /**@}*/ diff --git a/platform/FileSystemHandle.cpp b/platform/FileSystemHandle.cpp index 3028d409cec..1823f8a43bb 100644 --- a/platform/FileSystemHandle.cpp +++ b/platform/FileSystemHandle.cpp @@ -42,3 +42,8 @@ int FileSystemHandle::mkdir(const char *path, mode_t mode) { return -ENOSYS; } + +int FileSystemHandle::statvfs(const char *path, struct statvfs *buf) +{ + return -ENOSYS; +} diff --git a/platform/FileSystemHandle.h b/platform/FileSystemHandle.h index 713d6e5d7a2..349e25855ee 100644 --- a/platform/FileSystemHandle.h +++ b/platform/FileSystemHandle.h @@ -94,6 +94,14 @@ class FileSystemHandle : private NonCopyable { * @return 0 on success, negative error code on failure */ virtual int mkdir(const char *path, mode_t mode); + + /** Store information about the mounted filesystem in a statvfs structure + * + * @param path The name of the file to find information about + * @param buf The stat buffer to write to + * @return 0 on success, negative error code on failure + */ + virtual int statvfs(const char *path, struct statvfs *buf); }; /**@}*/ diff --git a/platform/mbed_alloc_wrappers.cpp b/platform/mbed_alloc_wrappers.cpp index 94318114726..58f153c70d0 100644 --- a/platform/mbed_alloc_wrappers.cpp +++ b/platform/mbed_alloc_wrappers.cpp @@ -46,9 +46,6 @@ typedef struct { uint32_t pad; } alloc_info_t; -#ifdef MBED_MEM_TRACING_ENABLED -static SingletonPtr mem_trace_mutex; -#endif #ifdef MBED_HEAP_STATS_ENABLED static SingletonPtr malloc_stats_mutex; static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0}; @@ -84,13 +81,22 @@ extern "C" { void * __real__realloc_r(struct _reent * r, void * ptr, size_t size); void __real__free_r(struct _reent * r, void * ptr); void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size); + void* malloc_wrapper(struct _reent * r, size_t size, void * caller); + void free_wrapper(struct _reent * r, void * ptr, void* caller); } // TODO: memory tracing doesn't work with uVisor enabled. #if !defined(FEATURE_UVISOR) extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) { + return malloc_wrapper(r, size, MBED_CALLER_ADDR()); +} + +extern "C" void * malloc_wrapper(struct _reent * r, size_t size, void * caller) { void *ptr = NULL; +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED malloc_stats_mutex->lock(); alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t)); @@ -111,15 +117,17 @@ extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) { ptr = __real__malloc_r(r, size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); - mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_malloc(ptr, size, caller); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return ptr; } extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) { void *new_ptr = NULL; +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED // Implement realloc_r with malloc and free. // The function realloc_r can't be used here directly since @@ -151,14 +159,20 @@ extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) new_ptr = __real__realloc_r(r, ptr, size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return new_ptr; } extern "C" void __wrap__free_r(struct _reent * r, void * ptr) { + free_wrapper(r, ptr, MBED_CALLER_ADDR()); +} + +extern "C" void free_wrapper(struct _reent * r, void * ptr, void * caller) { +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED malloc_stats_mutex->lock(); alloc_info_t *alloc_info = NULL; @@ -173,14 +187,16 @@ extern "C" void __wrap__free_r(struct _reent * r, void * ptr) { __real__free_r(r, ptr); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); - mbed_mem_trace_free(ptr, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_free(ptr, caller); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED } extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) { void *ptr = NULL; +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED // Note - no lock needed since malloc is thread safe @@ -192,9 +208,8 @@ extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) ptr = __real__calloc_r(r, nmemb, size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return ptr; } @@ -240,10 +255,20 @@ extern "C" { void *SUPER_REALLOC(void *ptr, size_t size); void *SUPER_CALLOC(size_t nmemb, size_t size); void SUPER_FREE(void *ptr); + void *malloc_wrapper(size_t size, void* caller); + void free_wrapper(void *ptr, void* caller); } + extern "C" void* SUB_MALLOC(size_t size) { + return malloc_wrapper(size, MBED_CALLER_ADDR()); +} + +extern "C" void* malloc_wrapper(size_t size, void* caller) { void *ptr = NULL; +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED malloc_stats_mutex->lock(); alloc_info_t *alloc_info = (alloc_info_t*)SUPER_MALLOC(size + sizeof(alloc_info_t)); @@ -264,15 +289,18 @@ extern "C" void* SUB_MALLOC(size_t size) { ptr = SUPER_MALLOC(size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); - mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_malloc(ptr, size, caller); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return ptr; } + extern "C" void* SUB_REALLOC(void *ptr, size_t size) { void *new_ptr = NULL; +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED // Note - no lock needed since malloc and free are thread safe @@ -299,15 +327,17 @@ extern "C" void* SUB_REALLOC(void *ptr, size_t size) { new_ptr = SUPER_REALLOC(ptr, size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return new_ptr; } extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) { void *ptr = NULL; +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED // Note - no lock needed since malloc is thread safe ptr = malloc(nmemb * size); @@ -318,14 +348,20 @@ extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) { ptr = SUPER_CALLOC(nmemb, size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return ptr; } extern "C" void SUB_FREE(void *ptr) { + free_wrapper(ptr, MBED_CALLER_ADDR()); +} + +extern "C" void free_wrapper(void *ptr, void* caller) { +#ifdef MBED_MEM_TRACING_ENABLED + mbed_mem_trace_lock(); +#endif #ifdef MBED_HEAP_STATS_ENABLED malloc_stats_mutex->lock(); alloc_info_t *alloc_info = NULL; @@ -340,9 +376,8 @@ extern "C" void SUB_FREE(void *ptr) { SUPER_FREE(ptr); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mem_trace_mutex->lock(); - mbed_mem_trace_free(ptr, MBED_CALLER_ADDR()); - mem_trace_mutex->unlock(); + mbed_mem_trace_free(ptr, caller); + mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED } diff --git a/platform/mbed_critical.c b/platform/mbed_critical.c index d9aa0963ab3..98f14785205 100644 --- a/platform/mbed_critical.c +++ b/platform/mbed_critical.c @@ -17,14 +17,33 @@ /* Declare __STDC_LIMIT_MACROS so stdint.h defines UINT32_MAX when using C++ */ #define __STDC_LIMIT_MACROS -#include "platform/mbed_critical.h" +#include "hal/critical_section_api.h" #include "cmsis.h" #include "platform/mbed_assert.h" +#include "platform/mbed_critical.h" #include "platform/mbed_toolchain.h" -static volatile uint32_t interrupt_enable_counter = 0; -static volatile bool critical_interrupts_disabled = false; +// if __EXCLUSIVE_ACCESS rtx macro not defined, we need to get this via own-set architecture macros +#ifndef MBED_EXCLUSIVE_ACCESS +#ifndef __EXCLUSIVE_ACCESS +#if ((__ARM_ARCH_7M__ == 1U) || \ + (__ARM_ARCH_7EM__ == 1U) || \ + (__ARM_ARCH_8M_BASE__ == 1U) || \ + (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (__ARM_ARCH_7A__ == 1U) +#define MBED_EXCLUSIVE_ACCESS 1U +#elif (__ARM_ARCH_6M__ == 1U) +#define MBED_EXCLUSIVE_ACCESS 0U +#else +#error "Unknown architecture for exclusive access" +#endif +#else +#define MBED_EXCLUSIVE_ACCESS __EXCLUSIVE_ACCESS +#endif +#endif + +static volatile uint32_t critical_section_reentrancy_counter = 0; bool core_util_are_interrupts_enabled(void) { @@ -51,57 +70,46 @@ bool core_util_is_isr_active(void) #endif } -MBED_WEAK void core_util_critical_section_enter(void) +bool core_util_in_critical_section(void) { - bool interrupts_disabled = !core_util_are_interrupts_enabled(); - __disable_irq(); - - /* Save the interrupt disabled state as it was prior to any nested critical section lock use */ - if (!interrupt_enable_counter) { - critical_interrupts_disabled = interrupts_disabled; - } + return hal_in_critical_section(); +} - /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts - are enabled, then something has gone badly wrong thus assert an error. - */ - MBED_ASSERT(interrupt_enable_counter < UINT32_MAX); +void core_util_critical_section_enter(void) +{ // FIXME -#ifndef FEATURE_UVISOR - if (interrupt_enable_counter > 0) { - MBED_ASSERT(interrupts_disabled); - } +#ifdef FEATURE_UVISOR + #warning "core_util_critical_section_enter needs fixing to work from unprivileged code" #else -#warning "core_util_critical_section_enter needs fixing to work from unprivileged code" + // If the reentrancy counter overflows something has gone badly wrong. + MBED_ASSERT(critical_section_reentrancy_counter < UINT32_MAX); #endif /* FEATURE_UVISOR */ - interrupt_enable_counter++; + + hal_critical_section_enter(); + + ++critical_section_reentrancy_counter; } -MBED_WEAK void core_util_critical_section_exit(void) +void core_util_critical_section_exit(void) { - /* If critical_section_enter has not previously been called, do nothing */ - if (interrupt_enable_counter) { - // FIXME -#ifndef FEATURE_UVISOR - bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */ - - MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */ -#else -#warning "core_util_critical_section_exit needs fixing to work from unprivileged code" +#ifdef FEATURE_UVISOR + #warning "core_util_critical_section_exit needs fixing to work from unprivileged code" #endif /* FEATURE_UVISOR */ - interrupt_enable_counter--; + // If critical_section_enter has not previously been called, do nothing + if (critical_section_reentrancy_counter == 0) { + return; + } - /* Only re-enable interrupts if we are exiting the last of the nested critical sections and - interrupts were enabled on entry to the first critical section. - */ - if (!interrupt_enable_counter && !critical_interrupts_disabled) { - __enable_irq(); - } + --critical_section_reentrancy_counter; + + if (critical_section_reentrancy_counter == 0) { + hal_critical_section_exit(); } } -#if __EXCLUSIVE_ACCESS +#if MBED_EXCLUSIVE_ACCESS /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */ #if defined (__CC_ARM) diff --git a/platform/mbed_critical.h b/platform/mbed_critical.h index c1c56898891..f428e86032c 100644 --- a/platform/mbed_critical.h +++ b/platform/mbed_critical.h @@ -82,6 +82,13 @@ void core_util_critical_section_enter(void); */ void core_util_critical_section_exit(void); +/** + * Determine if we are currently in a critical section + * + * @return true if in a critical section, false otherwise. + */ +bool core_util_in_critical_section(void); + /** * Atomic compare and set. It compares the contents of a memory location to a * given value and, only if they are the same, modifies the contents of that diff --git a/platform/mbed_mem_trace.c b/platform/mbed_mem_trace.cpp similarity index 84% rename from platform/mbed_mem_trace.c rename to platform/mbed_mem_trace.cpp index ee00760a8cb..17326f78e57 100644 --- a/platform/mbed_mem_trace.c +++ b/platform/mbed_mem_trace.cpp @@ -19,6 +19,8 @@ #include #include "platform/mbed_mem_trace.h" #include "platform/mbed_critical.h" +#include "platform/SingletonPtr.h" +#include "platform/PlatformMutex.h" /****************************************************************************** * Internal variables, functions and helpers @@ -26,10 +28,14 @@ /* The callback function that will be called after a traced memory operations finishes. */ static mbed_mem_trace_cb_t mem_trace_cb; -/* 'trave_level' guards "trace inside trace" situations (for example, the implementation +/* 'trace_lock_count' guards "trace inside trace" situations (for example, the implementation * of realloc() might call malloc() internally, and since malloc() is also traced, this could * result in two calls to the callback function instead of one. */ -static uint8_t trace_level; +static uint8_t trace_lock_count; +static SingletonPtr mem_trace_mutex; + +#define TRACE_FIRST_LOCK() (trace_lock_count < 2) + /****************************************************************************** * Public interface @@ -39,42 +45,50 @@ void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) { mem_trace_cb = cb; } +void mbed_mem_trace_lock() +{ + mem_trace_mutex->lock(); + trace_lock_count++; +} + +void mbed_mem_trace_unlock() +{ + trace_lock_count--; + mem_trace_mutex->unlock(); +} + void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) { if (mem_trace_cb) { - if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + if (TRACE_FIRST_LOCK()) { mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size); } - core_util_atomic_decr_u8(&trace_level, 1); } return res; } void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) { if (mem_trace_cb) { - if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + if (TRACE_FIRST_LOCK()) { mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size); } - core_util_atomic_decr_u8(&trace_level, 1); } return res; } void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) { if (mem_trace_cb) { - if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + if (TRACE_FIRST_LOCK()) { mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size); } - core_util_atomic_decr_u8(&trace_level, 1); } return res; } void mbed_mem_trace_free(void *ptr, void *caller) { if (mem_trace_cb) { - if (core_util_atomic_incr_u8(&trace_level, 1) == 1) { + if (TRACE_FIRST_LOCK()) { mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr); } - core_util_atomic_decr_u8(&trace_level, 1); } } diff --git a/platform/mbed_mem_trace.h b/platform/mbed_mem_trace.h index 59da721e2fe..6b604a08a7b 100644 --- a/platform/mbed_mem_trace.h +++ b/platform/mbed_mem_trace.h @@ -72,6 +72,17 @@ typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void* caller, ...); */ void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb); +/** + * Trace lock. + * @note Locking prevent recursive tracing of malloc/free inside relloc/calloc + */ +void mbed_mem_trace_lock(); + +/** + * Trace unlock. + */ +void mbed_mem_trace_unlock(); + /** * Trace a call to 'malloc'. * @param res the result of running 'malloc'. diff --git a/platform/mbed_mktime.c b/platform/mbed_mktime.c index 6954e723f4f..cb1280c9c21 100644 --- a/platform/mbed_mktime.c +++ b/platform/mbed_mktime.c @@ -16,14 +16,17 @@ #include "mbed_mktime.h" -/* - * time constants - */ +/* Time constants. */ #define SECONDS_BY_MINUTES 60 #define MINUTES_BY_HOUR 60 #define SECONDS_BY_HOUR (SECONDS_BY_MINUTES * MINUTES_BY_HOUR) #define HOURS_BY_DAY 24 #define SECONDS_BY_DAY (SECONDS_BY_HOUR * HOURS_BY_DAY) +#define LAST_VALID_YEAR 206 + +/* Macros which will be used to determine if we are within valid range. */ +#define EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT 3220095 // 7th of February 1970 at 06:28:15 +#define EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT 3133695 // 6th of February 1970 at 06:28:15 /* * 2 dimensional array containing the number of seconds elapsed before a given @@ -63,10 +66,10 @@ static const uint32_t seconds_before_month[2][12] = { } }; -bool _rtc_is_leap_year(int year) { +bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support) { /* * since in practice, the value manipulated by this algorithm lie in the - * range [70 : 138], the algorith can be reduced to: year % 4. + * range: [70 : 206] the algorithm can be reduced to: year % 4 with exception for 200 (year 2100 is not leap year). * The algorithm valid over the full range of value is: year = 1900 + year; @@ -80,86 +83,108 @@ bool _rtc_is_leap_year(int year) { return true; */ + if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && year == 200) { + return false; // 2100 is not a leap year + } + return (year) % 4 ? false : true; } -time_t _rtc_mktime(const struct tm* time) { - // partial check for the upper bound of the range - // normalization might happen at the end of the function - // this solution is faster than checking if the input is after the 19th of - // january 2038 at 03:14:07. - if ((time->tm_year < 70) || (time->tm_year > 138)) { - return ((time_t) -1); +bool _rtc_maketime(const struct tm* time, time_t * seconds, rtc_leap_year_support_t leap_year_support) { + if (seconds == NULL || time == NULL) { + return false; + } + + /* Partial check for the upper bound of the range - check years only. Full check will be performed after the + * elapsed time since the beginning of the year is calculated. + */ + if ((time->tm_year < 70) || (time->tm_year > LAST_VALID_YEAR)) { + return false; } uint32_t result = time->tm_sec; result += time->tm_min * SECONDS_BY_MINUTES; result += time->tm_hour * SECONDS_BY_HOUR; result += (time->tm_mday - 1) * SECONDS_BY_DAY; - result += seconds_before_month[_rtc_is_leap_year(time->tm_year)][time->tm_mon]; + result += seconds_before_month[_rtc_is_leap_year(time->tm_year, leap_year_support)][time->tm_mon]; + + /* Check if we are within valid range. */ + if (time->tm_year == LAST_VALID_YEAR) { + if ((leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT) || + (leap_year_support == RTC_4_YEAR_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT)) { + return false; + } + } if (time->tm_year > 70) { - // valid in the range [70:138] + /* Valid in the range [70:206]. */ uint32_t count_of_leap_days = ((time->tm_year - 1) / 4) - (70 / 4); + if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT) { + if (time->tm_year > 200) { + count_of_leap_days--; // 2100 is not a leap year + } + } + result += (((time->tm_year - 70) * 365) + count_of_leap_days) * SECONDS_BY_DAY; } - if (result > INT32_MAX) { - return (time_t) -1; - } + *seconds = result; - return result; + return true; } -bool _rtc_localtime(time_t timestamp, struct tm* time_info) { - if (((int32_t) timestamp) < 0) { +bool _rtc_localtime(time_t timestamp, struct tm* time_info, rtc_leap_year_support_t leap_year_support) { + if (time_info == NULL) { return false; - } + } + + uint32_t seconds = (uint32_t)timestamp; - time_info->tm_sec = timestamp % 60; - timestamp = timestamp / 60; // timestamp in minutes - time_info->tm_min = timestamp % 60; - timestamp = timestamp / 60; // timestamp in hours - time_info->tm_hour = timestamp % 24; - timestamp = timestamp / 24; // timestamp in days; + time_info->tm_sec = seconds % 60; + seconds = seconds / 60; // timestamp in minutes + time_info->tm_min = seconds % 60; + seconds = seconds / 60; // timestamp in hours + time_info->tm_hour = seconds % 24; + seconds = seconds / 24; // timestamp in days; - // compute the weekday - // The 1st of January 1970 was a Thursday which is equal to 4 in the weekday - // representation ranging from [0:6] - time_info->tm_wday = (timestamp + 4) % 7; + /* Compute the weekday. + * The 1st of January 1970 was a Thursday which is equal to 4 in the weekday representation ranging from [0:6]. + */ + time_info->tm_wday = (seconds + 4) % 7; - // years start at 70 + /* Years start at 70. */ time_info->tm_year = 70; while (true) { - if (_rtc_is_leap_year(time_info->tm_year) && timestamp >= 366) { + if (_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 366) { ++time_info->tm_year; - timestamp -= 366; - } else if (!_rtc_is_leap_year(time_info->tm_year) && timestamp >= 365) { + seconds -= 366; + } else if (!_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 365) { ++time_info->tm_year; - timestamp -= 365; + seconds -= 365; } else { - // the remaining days are less than a years + /* The remaining days are less than a years. */ break; } } - time_info->tm_yday = timestamp; + time_info->tm_yday = seconds; - // convert days into seconds and find the current month - timestamp *= SECONDS_BY_DAY; + /* Convert days into seconds and find the current month. */ + seconds *= SECONDS_BY_DAY; time_info->tm_mon = 11; - bool leap = _rtc_is_leap_year(time_info->tm_year); + bool leap = _rtc_is_leap_year(time_info->tm_year, leap_year_support); for (uint32_t i = 0; i < 12; ++i) { - if ((uint32_t) timestamp < seconds_before_month[leap][i]) { + if ((uint32_t) seconds < seconds_before_month[leap][i]) { time_info->tm_mon = i - 1; break; } } - // remove month from timestamp and compute the number of days. - // note: unlike other fields, days are not 0 indexed. - timestamp -= seconds_before_month[leap][time_info->tm_mon]; - time_info->tm_mday = (timestamp / SECONDS_BY_DAY) + 1; + /* Remove month from timestamp and compute the number of days. + * Note: unlike other fields, days are not 0 indexed. + */ + seconds -= seconds_before_month[leap][time_info->tm_mon]; + time_info->tm_mday = (seconds / SECONDS_BY_DAY) + 1; return true; } diff --git a/platform/mbed_mktime.h b/platform/mbed_mktime.h index dd302702e40..f877512b9d2 100644 --- a/platform/mbed_mktime.h +++ b/platform/mbed_mktime.h @@ -33,14 +33,34 @@ extern "C" { * @{ */ +/* Time range across the whole 32-bit range should be supported which means that years in range 1970 - 2106 can be + * encoded. We have two types of RTC devices: + * a) RTCs which handles all leap years in the mentioned year range correctly. Leap year is determined by checking if + * the year counter value is divisible by 400, 100, and 4. No problem here. + * b) RTCs which handles leap years correctly up to 2100. The RTC does a simple bit comparison to see if the two + * lowest order bits of the year counter are zero. In this case 2100 year will be considered + * incorrectly as a leap year, so the last valid point in time will be 28.02.2100 23:59:59 and next day will be + * 29.02.2100 (invalid). So after 28.02.2100 the day counter will be off by a day. + */ +typedef enum { + RTC_FULL_LEAP_YEAR_SUPPORT, + RTC_4_YEAR_LEAP_YEAR_SUPPORT +} rtc_leap_year_support_t; + /** Compute if a year is a leap year or not. * - * @param year The year to test it shall be in the range [70:138]. Year 0 is + * @param year The year to test it shall be in the range [70:206]. Year 0 is * translated into year 1900 CE. + * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able + * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT. + * * @return true if the year in input is a leap year and false otherwise. - * @note - For use by the HAL only + * + * @note For use by the HAL only + * @note Year 2100 is treated differently for devices with full leap year support and devices with + * partial leap year support. Devices with partial leap year support treats 2100 as a leap year. */ -bool _rtc_is_leap_year(int year); +bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support); /* Convert a calendar time into time since UNIX epoch as a time_t. * @@ -48,7 +68,7 @@ bool _rtc_is_leap_year(int year); * tailored around RTC peripherals needs and is not by any mean a complete * replacement of mktime. * - * @param calendar_time The calendar time to convert into a time_t since epoch. + * @param time The calendar time to convert into a time_t since epoch. * The fields from tm used for the computation are: * - tm_sec * - tm_min @@ -57,17 +77,20 @@ bool _rtc_is_leap_year(int year); * - tm_mon * - tm_year * Other fields are ignored and won't be renormalized by a call to this function. - * A valid calendar time is comprised between the 1st january of 1970 at - * 00:00:00 and the 19th of january 2038 at 03:14:07. + * A valid calendar time is comprised between: + * the 1st of January 1970 at 00:00:00 to the 7th of February 2106 at 06:28:15. + * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able + * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT. + * @param seconds holder for the result - calendar time as seconds since UNIX epoch. * - * @return The calendar time as seconds since UNIX epoch if the input is in the - * valid range. Otherwise ((time_t) -1). + * @return true on success, false if conversion error occurred. * * @note Leap seconds are not supported. - * @note Values in output range from 0 to INT_MAX. - * @note - For use by the HAL only + * @note Values in output range from 0 to UINT_MAX. + * @note Full and partial leap years support. + * @note For use by the HAL only */ -time_t _rtc_mktime(const struct tm* calendar_time); +bool _rtc_maketime(const struct tm* time, time_t * seconds, rtc_leap_year_support_t leap_year_support); /* Convert a given time in seconds since epoch into calendar time. * @@ -76,7 +99,7 @@ time_t _rtc_mktime(const struct tm* calendar_time); * complete of localtime. * * @param timestamp The time (in seconds) to convert into calendar time. Valid - * input are in the range [0 : INT32_MAX]. + * input are in the range [0 : UINT32_MAX]. * @param calendar_time Pointer to the object which will contain the result of * the conversion. The tm fields filled by this function are: * - tm_sec @@ -88,11 +111,14 @@ time_t _rtc_mktime(const struct tm* calendar_time); * - tm_wday * - tm_yday * The object remains untouched if the time in input is invalid. + * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able + * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT. * @return true if the conversion was successful, false otherwise. * - * @note - For use by the HAL only + * @note For use by the HAL only. + * @note Full and partial leap years support. */ -bool _rtc_localtime(time_t timestamp, struct tm* calendar_time); +bool _rtc_localtime(time_t timestamp, struct tm* time_info, rtc_leap_year_support_t leap_year_support); /** @}*/ diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index a3bb0153349..34b0f538701 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -351,7 +351,9 @@ extern "C" void PREFIX(_exit)(int return_code) { } extern "C" void _ttywrch(int ch) { +#if DEVICE_SERIAL serial_putc(&stdio_uart, ch); +#endif } #endif @@ -709,6 +711,23 @@ extern "C" int stat(const char *path, struct stat *st) { } } +extern "C" int statvfs(const char *path, struct statvfs *buf) { + FilePath fp(path); + FileSystemHandle *fs = fp.fileSystem(); + if (fs == NULL) { + errno = ENODEV; + return -1; + } + + int err = fs->statvfs(fp.fileName(), buf); + if (err < 0) { + errno = -err; + return -1; + } else { + return 0; + } +} + #if defined(TOOLCHAIN_GCC) /* prevents the exception handling name demangling code getting pulled in */ #include "mbed_error.h" @@ -739,6 +758,7 @@ extern "C" int errno; // Dynamic memory allocation related syscall. #if defined(TARGET_NUVOTON) + // Overwrite _sbrk() to support two region model (heap and stack are two distinct regions). // __wrap__sbrk() is implemented in: // TARGET_NUMAKER_PFM_NUC472 targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c @@ -977,6 +997,10 @@ extern "C" void __env_unlock( struct _reent *_r ) __rtos_env_unlock(_r); } +#endif + +#if defined (__GNUC__) || defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #define CXA_GUARD_INIT_DONE (1 << 0) #define CXA_GUARD_INIT_IN_PROGRESS (1 << 1) #define CXA_GUARD_MASK (CXA_GUARD_INIT_DONE | CXA_GUARD_INIT_IN_PROGRESS) @@ -1015,6 +1039,99 @@ extern "C" void __cxa_guard_abort(int *guard_object_p) #endif +#if defined(MBED_MEM_TRACING_ENABLED) && (defined(__CC_ARM) || defined(__ICCARM__)) + +// If the memory tracing is enabled, the wrappers in mbed_alloc_wrappers.cpp +// provide the implementation for these. Note: this needs to use the wrappers +// instead of malloc()/free() as the caller address would point to wrappers, +// not the caller of "new" or "delete". +extern "C" void* malloc_wrapper(size_t size, const void* caller); +extern "C" void free_wrapper(void *ptr, const void* caller); + +void *operator new(std::size_t count) +{ + void *buffer = malloc_wrapper(count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new out of memory\r\n"); + } + return buffer; +} + +void *operator new[](std::size_t count) +{ + void *buffer = malloc_wrapper(count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new[] out of memory\r\n"); + } + return buffer; +} + +void *operator new(std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(count, MBED_CALLER_ADDR()); +} + +void *operator new[](std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(count, MBED_CALLER_ADDR()); +} + +void operator delete(void *ptr) +{ + free_wrapper(ptr, MBED_CALLER_ADDR()); +} +void operator delete[](void *ptr) +{ + free_wrapper(ptr, MBED_CALLER_ADDR()); +} + +#elif defined(MBED_MEM_TRACING_ENABLED) && defined(__GNUC__) + +#include + +extern "C" void* malloc_wrapper(struct _reent * r, size_t size, void * caller); +extern "C" void free_wrapper(struct _reent * r, void * ptr, void * caller); + +void *operator new(std::size_t count) +{ + void *buffer = malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new out of memory\r\n"); + } + return buffer; +} + +void *operator new[](std::size_t count) +{ + void *buffer = malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new[] out of memory\r\n"); + } + return buffer; +} + +void *operator new(std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); +} + +void *operator new[](std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); +} + +void operator delete(void *ptr) +{ + free_wrapper(_REENT, ptr, MBED_CALLER_ADDR()); +} + +void operator delete[](void *ptr) +{ + free_wrapper(_REENT, ptr, MBED_CALLER_ADDR()); +} + +#else + void *operator new(std::size_t count) { void *buffer = malloc(count); @@ -1052,6 +1169,8 @@ void operator delete[](void *ptr) free(ptr); } +#endif + /* @brief standard c library clock() function. * * This function returns the number of clock ticks elapsed since the start of the program. diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index ac1abc04ed9..c3e6cbd54da 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -28,8 +28,9 @@ /* We can get the following standard types from sys/types for gcc, but we * need to define the types ourselves for the other compilers that normally * target embedded systems */ -typedef signed int ssize_t; ///< Signed size type, usually encodes negative errors -typedef signed long off_t; ///< Offset in a data stream +typedef signed int ssize_t; ///< Signed size type, usually encodes negative errors +typedef signed long off_t; ///< Offset in a data stream +typedef unsigned long long fsblkcnt_t; ///< Count of file system blocks #if defined(__ARMCC_VERSION) || !defined(__GNUC__) typedef unsigned int mode_t; ///< Mode for opening files typedef unsigned int dev_t; ///< Device ID type @@ -62,7 +63,7 @@ typedef unsigned int gid_t; ///< Group ID /* DIR declarations must also be here */ #if __cplusplus namespace mbed { - + class FileHandle; class DirHandle; std::FILE *mbed_fdopen(FileHandle *fh, const char *mode); @@ -415,10 +416,24 @@ struct stat { time_t st_ctime; ///< Time of last status change }; +struct statvfs { + unsigned long f_bsize; ///< Filesystem block size + unsigned long f_frsize; ///< Fragment size (block size) + + fsblkcnt_t f_blocks; ///< Number of blocks + fsblkcnt_t f_bfree; ///< Number of free blocks + fsblkcnt_t f_bavail; ///< Number of free blocks for unprivileged users + + unsigned long f_fsid; ///< Filesystem ID + + unsigned long f_namemax; ///< Maximum filename length +}; + #if __cplusplus extern "C" { #endif int stat(const char *path, struct stat *st); + int statvfs(const char *path, struct statvfs *buf); #if __cplusplus }; #endif diff --git a/rtos/ConditionVariable.h b/rtos/ConditionVariable.h index dd091ec3d4e..c69722d8975 100644 --- a/rtos/ConditionVariable.h +++ b/rtos/ConditionVariable.h @@ -118,7 +118,10 @@ struct Waiter; */ class ConditionVariable : private mbed::NonCopyable { public: - /** Create and Initialize a ConditionVariable object */ + /** Create and Initialize a ConditionVariable object + * + * @note You may call this function from ISR context. + */ ConditionVariable(Mutex &mutex); /** Wait for a notification @@ -142,6 +145,8 @@ class ConditionVariable : private mbed::NonCopyable { * * mutex.unlock(); * @endcode + * + * @note You cannot call this function from ISR context. */ void wait(); @@ -176,21 +181,31 @@ class ConditionVariable : private mbed::NonCopyable { * * mutex.unlock(); * @endcode + * + * @note You cannot call this function from ISR context. */ bool wait_for(uint32_t millisec); /** Notify one waiter on this condition variable that a condition changed. * * @note - The thread calling this function must be the owner of the ConditionVariable's mutex + * + * @note This function may be called from ISR context. */ void notify_one(); /** Notify all waiters on this condition variable that a condition changed. * * @note - The thread calling this function must be the owner of the ConditionVariable's mutex + * + * @note This function may be called from ISR context. */ void notify_all(); + /** ConditionVariable destructor + * + * @note You may call this function from ISR context. + */ ~ConditionVariable(); protected: diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index 5beb5e5ef17..0571ec7b856 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -46,29 +46,40 @@ namespace rtos { */ class EventFlags : private mbed::NonCopyable { public: - /** Create and Initialize a EventFlags object */ + /** Create and Initialize an EventFlags object + * + * @note You cannot call this function from ISR context. + */ EventFlags(); /** Create and Initialize a EventFlags object @param name name to be used for this EventFlags. It has to stay allocated for the lifetime of the thread. + + @note You cannot call this function from ISR context. */ EventFlags(const char *name); /** Set the specified Event Flags. @param flags specifies the flags that shall be set. @return event flags after setting or error code if highest bit set (@a osFlagsError). + + @note This function may be called from ISR context. */ uint32_t set(uint32_t flags); /** Clear the specified Event Flags. @param flags specifies the flags that shall be cleared. (default: 0x7fffffff - all flags) @return event flags before clearing or error code if highest bit set (@a osFlagsError). + + @note You may call this function from ISR context. */ uint32_t clear(uint32_t flags = 0x7fffffff); /** Get the currently set Event Flags. @return set event flags. + + @note You may call this function from ISR context. */ uint32_t get() const; @@ -77,6 +88,8 @@ class EventFlags : private mbed::NonCopyable { @param timeout timeout value or 0 in case of no time-out. (default: osWaitForever) @param clear specifies wether to clear the flags after waiting for them. (default: true) @return event flags before clearing or error code if highest bit set (@a osFlagsError). + + @note You may call this function from ISR context if the timeout parameter is set to 0. */ uint32_t wait_all(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); @@ -85,9 +98,15 @@ class EventFlags : private mbed::NonCopyable { @param timeout timeout value or 0 in case of no time-out. (default: osWaitForever) @param clear specifies wether to clear the flags after waiting for them. (default: true) @return event flags before clearing or error code if highest bit set (@a osFlagsError). + + @note This function may be called from ISR context if the timeout parameter is set to 0. */ uint32_t wait_any(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); + /** Event flags destructor + + @note You cannot call this function from ISR context. + */ ~EventFlags(); private: diff --git a/rtos/Mail.h b/rtos/Mail.h index c9ae7f372f1..c0fdc76fc43 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -55,12 +55,17 @@ namespace rtos { template class Mail : private mbed::NonCopyable > { public: - /** Create and Initialise Mail queue. */ + /** Create and Initialize Mail queue. + * + * @note You cannot call this function from ISR context. + */ Mail() { }; /** Check if the mail queue is empty * * @return True if the mail queue is empty, false if not + * + * @note You may call this function from ISR context. */ bool empty() const { return _queue.empty(); @@ -69,6 +74,8 @@ class Mail : private mbed::NonCopyable > { /** Check if the mail queue is full * * @return True if the mail queue is full, false if not + * + * @note You may call this function from ISR context. */ bool full() const { return _queue.full(); @@ -77,6 +84,8 @@ class Mail : private mbed::NonCopyable > { /** Allocate a memory block of type T @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. + + @note You may call this function from ISR context if the millisec parameter is set to 0. */ T* alloc(uint32_t millisec=0) { return _pool.alloc(); @@ -85,6 +94,8 @@ class Mail : private mbed::NonCopyable > { /** Allocate a memory block of type T and set memory block to zero. @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. + + @note You may call this function from ISR context if the millisec parameter is set to 0. */ T* calloc(uint32_t millisec=0) { return _pool.calloc(); @@ -93,6 +104,8 @@ class Mail : private mbed::NonCopyable > { /** Put a mail in the queue. @param mptr memory block previously allocated with Mail::alloc or Mail::calloc. @return status code that indicates the execution status of the function. + + @note You may call this function from ISR context. */ osStatus put(T *mptr) { return _queue.put(mptr); @@ -101,6 +114,8 @@ class Mail : private mbed::NonCopyable > { /** Get a mail from a queue. @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return event that contains mail information or error code. + + @note You may call this function from ISR context if the millisec parameter is set to 0. */ osEvent get(uint32_t millisec=osWaitForever) { osEvent evt = _queue.get(millisec); @@ -113,6 +128,8 @@ class Mail : private mbed::NonCopyable > { /** Free a memory block from a mail. @param mptr pointer to the memory block that was obtained with Mail::get. @return status code that indicates the execution status of the function. + + @note You may call this function from ISR context. */ osStatus free(T *mptr) { return _pool.free(mptr); diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index d76a99e794f..bfcd392ecc9 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -50,7 +50,10 @@ template class MemoryPool : private mbed::NonCopyable > { MBED_STATIC_ASSERT(pool_sz > 0, "Invalid memory pool size. Must be greater than 0."); public: - /** Create and Initialize a memory pool. */ + /** Create and Initialize a memory pool. + * + * @note You cannot call this function from ISR context. + */ MemoryPool() { memset(_pool_mem, 0, sizeof(_pool_mem)); memset(&_obj_mem, 0, sizeof(_obj_mem)); @@ -63,13 +66,18 @@ class MemoryPool : private mbed::NonCopyable > { MBED_ASSERT(_id); } - /** Destroy a memory pool */ + /** Destroy a memory pool + * + * @note You cannot call this function from ISR context. + */ ~MemoryPool() { osMemoryPoolDelete(_id); } /** Allocate a memory block of type T from a memory pool. @return address of the allocated memory block or NULL in case of no memory available. + + @note You may call this function from ISR context. */ T* alloc(void) { return (T*)osMemoryPoolAlloc(_id, 0); @@ -77,6 +85,8 @@ class MemoryPool : private mbed::NonCopyable > { /** Allocate a memory block of type T from a memory pool and set memory block to zero. @return address of the allocated memory block or NULL in case of no memory available. + + @note You may call this function from ISR context. */ T* calloc(void) { T *item = (T*)osMemoryPoolAlloc(_id, 0); @@ -92,6 +102,7 @@ class MemoryPool : private mbed::NonCopyable > { is NULL or invalid, or osErrorResource if given memory block is in an invalid memory pool state. + @note You may call this function from ISR context. */ osStatus free(T *block) { return osMemoryPoolFree(_id, (void*)block); diff --git a/rtos/Mutex.h b/rtos/Mutex.h index 1b9e22a27ff..4273d14722d 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -40,18 +40,26 @@ namespace rtos { /** The Mutex class is used to synchronize the execution of threads. This is for example used to protect access to a shared resource. + @note You cannot use member functions of this class in ISR context. If you require Mutex functionality within + ISR handler, consider using @a Semaphore. + @note Memory considerations: The mutex control structures will be created on current thread's stack, both for the mbed OS and underlying RTOS objects (static or dynamic RTOS memory pools are not being used). */ class Mutex : private mbed::NonCopyable { public: - /** Create and Initialize a Mutex object */ + /** Create and Initialize a Mutex object + * + * @note You cannot call this function from ISR context. + */ Mutex(); /** Create and Initialize a Mutex object @param name name to be used for this mutex. It has to stay allocated for the lifetime of the thread. + + @note You cannot call this function from ISR context. */ Mutex(const char *name); @@ -63,11 +71,15 @@ class Mutex : private mbed::NonCopyable { @a osErrorParameter internal error. @a osErrorResource the mutex could not be obtained when no timeout was specified. @a osErrorISR this function cannot be called from the interrupt service routine. + + @note You cannot call this function from ISR context. */ osStatus lock(uint32_t millisec=osWaitForever); /** Try to lock the mutex, and return immediately @return true if the mutex was acquired, false otherwise. + + @note This function cannot be called from ISR context. */ bool trylock(); @@ -77,14 +89,22 @@ class Mutex : private mbed::NonCopyable { @a osErrorParameter internal error. @a osErrorResource the mutex was not locked or the current thread wasn't the owner. @a osErrorISR this function cannot be called from the interrupt service routine. + + @note This function cannot be called from ISR context. */ osStatus unlock(); /** Get the owner the this mutex @return the current owner of this mutex. + + @note You cannot call this function from ISR context. */ osThreadId get_owner(); + /** Mutex destructor + * + * @note You cannot call this function from ISR context. + */ ~Mutex(); private: diff --git a/rtos/Queue.h b/rtos/Queue.h index 67a04653dbd..0190c047f84 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -52,7 +52,10 @@ namespace rtos { template class Queue : private mbed::NonCopyable > { public: - /** Create and initialize a message Queue. */ + /** Create and initialize a message Queue. + * + * @note You cannot call this function from ISR context. + */ Queue() { memset(&_obj_mem, 0, sizeof(_obj_mem)); osMessageQueueAttr_t attr = { 0 }; @@ -63,7 +66,10 @@ class Queue : private mbed::NonCopyable > { _id = osMessageQueueNew(queue_sz, sizeof(T*), &attr); MBED_ASSERT(_id); } - + /** Queue destructor + * + * @note You cannot call this function from ISR context. + */ ~Queue() { osMessageQueueDelete(_id); } @@ -71,6 +77,8 @@ class Queue : private mbed::NonCopyable > { /** Check if the queue is empty * * @return True if the queue is empty, false if not + * + * @note You may call this function from ISR context. */ bool empty() const { return osMessageQueueGetCount(_id) == 0; @@ -79,6 +87,8 @@ class Queue : private mbed::NonCopyable > { /** Check if the queue is full * * @return True if the queue is full, false if not + * + * @note You may call this function from ISR context. */ bool full() const { return osMessageQueueGetSpace(_id) == 0; @@ -93,6 +103,8 @@ class Queue : private mbed::NonCopyable > { @a osErrorTimeout the message could not be put into the queue in the given time. @a osErrorResource not enough space in the queue. @a osErrorParameter internal error or non-zero timeout specified in an ISR. + + @note You may call this function from ISR context if the millisec parameter is set to 0. */ osStatus put(T* data, uint32_t millisec=0, uint8_t prio=0) { return osMessageQueuePut(_id, &data, prio, millisec); @@ -106,6 +118,8 @@ class Queue : private mbed::NonCopyable > { @a osOK no message is available in the queue and no timeout was specified. @a osEventTimeout no message has arrived during the given timeout period. @a osErrorParameter a parameter is invalid or outside of a permitted range. + + @note You may call this function from ISR context if the millisec parameter is set to 0. */ osEvent get(uint32_t millisec=osWaitForever) { osEvent event; diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index c5e6276468b..27e0c5aeee9 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -93,6 +93,8 @@ class RtosTimer : private mbed::NonCopyable { @deprecated Replaced with RtosTimer(Callback, os_timer_type) @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details + + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Replaced with RtosTimer(Callback, os_timer_type)") @@ -107,6 +109,8 @@ class RtosTimer : private mbed::NonCopyable { @param type osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic) @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details + + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.2", "The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details") @@ -123,6 +127,8 @@ class RtosTimer : private mbed::NonCopyable { RtosTimer(callback(obj, method), os_timer_type). @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details + + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -140,6 +146,8 @@ class RtosTimer : private mbed::NonCopyable { @a osErrorISR @a stop cannot be called from interrupt service routines. @a osErrorParameter internal error. @a osErrorResource the timer is not running. + + @note You cannot call this function from ISR context. */ osStatus stop(void); @@ -150,9 +158,15 @@ class RtosTimer : private mbed::NonCopyable { @a osErrorISR @a start cannot be called from interrupt service routines. @a osErrorParameter internal error or incorrect parameter value. @a osErrorResource internal error (the timer is in an invalid timer state). + + @note You cannot call this function from ISR context. */ osStatus start(uint32_t millisec); + /** RtosTimer destructor + * + * @note You cannot call this function from ISR context. + */ ~RtosTimer(); private: diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index 88b479c5e4f..e8fc22205ac 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -46,18 +46,24 @@ class Semaphore : private mbed::NonCopyable { public: /** Create and Initialize a Semaphore object used for managing resources. @param count number of available resources; maximum index value is (count-1). (default: 0). + + @note You cannot call this function from ISR context. */ Semaphore(int32_t count=0); /** Create and Initialize a Semaphore object used for managing resources. @param count number of available resources @param max_count maximum number of available resources + + @note You cannot call this function from ISR context. */ Semaphore(int32_t count, uint16_t max_count); /** Wait until a Semaphore resource becomes available. @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return number of available tokens, before taking one; or -1 in case of incorrect parameters + + @note You may call this function from ISR context if the millisec parameter is set to 0. */ int32_t wait(uint32_t millisec=osWaitForever); @@ -66,9 +72,15 @@ class Semaphore : private mbed::NonCopyable { @a osOK the token has been correctly released. @a osErrorResource the maximum token count has been reached. @a osErrorParameter internal error. + + @note You may call this function from ISR context. */ osStatus release(void); + /** Semaphore destructor + * + * @note You cannot call this function from ISR context. + */ ~Semaphore(); private: diff --git a/rtos/TARGET_CORTEX/mbed_boot.c b/rtos/TARGET_CORTEX/mbed_boot.c index 46bc1f1b115..4198b532255 100644 --- a/rtos/TARGET_CORTEX/mbed_boot.c +++ b/rtos/TARGET_CORTEX/mbed_boot.c @@ -423,9 +423,6 @@ void __rt_entry (void) { mbed_start_main(); } -typedef void *mutex; -mutex _static_mutexes[OS_MUTEX_NUM] = {NULL}; - /* ARM toolchain requires dynamically created mutexes to enforce thread safety. There's up to 8 static mutexes, protecting atexit, signalinit, stdin, stdout, stderr, stream_list, fp_trap_init and the heap. Additionally for each call to fopen one extra mutex will be @@ -436,6 +433,12 @@ mutex _static_mutexes[OS_MUTEX_NUM] = {NULL}; worry about freeing the allocated memory as library mutexes are only freed when the application finishes executing. */ + +typedef void *mutex; +#define OS_MUTEX_STATIC_NUM 8 +mutex _static_mutexes[OS_MUTEX_STATIC_NUM] = {NULL}; +mbed_rtos_storage_mutex_t _static_mutexes_mem[OS_MUTEX_STATIC_NUM] = {NULL}; + int _mutex_initialize(mutex *m) { osMutexAttr_t attr; @@ -445,10 +448,13 @@ int _mutex_initialize(mutex *m) mutex *slot = NULL; core_util_critical_section_enter(); - for (int i = 0; i < OS_MUTEX_NUM; i++) { + for (int i = 0; i < OS_MUTEX_STATIC_NUM; i++) { if (_static_mutexes[i] == NULL) { _static_mutexes[i] = (mutex)-1; // dummy value to reserve slot slot = &_static_mutexes[i]; + //Use the static attrs + attr.cb_size = sizeof(mbed_rtos_storage_mutex_t); + attr.cb_mem = &_static_mutexes_mem[i]; break; } } @@ -482,7 +488,7 @@ int _mutex_initialize(mutex *m) void _mutex_free(mutex *m) { mutex *slot = NULL; core_util_critical_section_enter(); - for (int i = 0; i < OS_MUTEX_NUM; i++) { + for (int i = 0; i < OS_MUTEX_STATIC_NUM; i++) { if (_static_mutexes[i] == *m) { slot = &_static_mutexes[i]; break; diff --git a/rtos/TARGET_CORTEX/mbed_rtx_conf.h b/rtos/TARGET_CORTEX/mbed_rtx_conf.h index a6cd655d9f3..dfc26c3087b 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_conf.h +++ b/rtos/TARGET_CORTEX/mbed_rtx_conf.h @@ -45,12 +45,6 @@ #error "OS Tickrate must be 1000 for system timing" #endif -#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -/* ARM toolchain uses up to 8 static mutexes, any further mutexes will be allocated on the heap. */ -#define OS_MUTEX_OBJ_MEM 1 -#define OS_MUTEX_NUM 8 -#endif - #if !defined(OS_STACK_WATERMARK) && (defined(MBED_STACK_STATS_ENABLED) && MBED_STACK_STATS_ENABLED) #define OS_STACK_WATERMARK 1 #endif diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index 32d5ead975e..bb2be1c421c 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -24,7 +24,6 @@ #include "platform/mbed_sleep.h" #include "TimerEvent.h" #include "lp_ticker_api.h" -#include "rtx_core_cm.h" #include "mbed_critical.h" #include "mbed_assert.h" #include diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S index 7963fdefc09..97b43d89bb4 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S @@ -384,19 +384,18 @@ osRtxContextSave VMRS R2, FPSCR STMDB R3!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment - IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16 - VSTMDB R3!, {D0-D15} - LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that VFP/D16 state is stacked - ORR R2, R2, #2 - STRB R2, [R0, #TCB_SP_FRAME] + + VSTMDB R3!, {D0-D15} ; Save D0-D15 + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + VSTMDB R3!, {D16-D31} ; Save D16-D31 ENDIF + LDRB R2, [R0, #TCB_SP_FRAME] IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 - VSTMDB R3!, {D0-D15} - VSTMDB R3!, {D16-D31} - LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that NEON/D32 state is stacked - ORR R2, R2, #4 - STRB R2, [R0, #TCB_SP_FRAME] + ORR R2, R2, #4 ; NEON state + ELSE + ORR R2, R2, #2 ; VFP state ENDIF + STRB R2, [R0, #TCB_SP_FRAME] ; Record VFP/NEON state osRtxContextSave1 STR R3, [R0, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr @@ -414,11 +413,11 @@ osRtxContextRestore BEQ osRtxContextRestore1 ; No VFP ISB ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 - VLDMIA R3!, {D16-D31} + VLDMIA R3!, {D16-D31} ; Restore D16-D31 ENDIF - VLDMIA R3!, {D0-D15} + VLDMIA R3!, {D0-D15} ; Restore D0-D15 LDR R2, [R3] - VMSR FPSCR, R2 + VMSR FPSCR, R2 ; Restore FPSCR ADD R3, R3, #8 osRtxContextRestore1 diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S index aa40e0d3649..72d20c0bdeb 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S @@ -361,93 +361,92 @@ osRtxContextSwitch: // R0 = osRtxInfo.thread.run.curr // R1 = osRtxInfo.thread.run.next - // R12 = &osRtxInfo.thread.run + // R12 = &osRtxInfo.thread.run - CMP R0, #0 // Is osRtxInfo.thread.run.curr == 0 - ADDEQ SP, SP, #32 // Equal, curr deleted, adjust current SP - BEQ osRtxContextRestore // Restore context, run.curr = run.next; + CMP R0, #0 // Is osRtxInfo.thread.run.curr == 0 + ADDEQ SP, SP, #32 // Equal, curr deleted, adjust current SP + BEQ osRtxContextRestore // Restore context, run.curr = run.next; osRtxContextSave: SUB SP, SP, #4 - STM SP, {SP}^ // Save SP_usr to current stack - POP {R3} // Pop SP_usr into R3 + STM SP, {SP}^ // Save SP_usr to current stack + POP {R3} // Pop SP_usr into R3 - SUB R3, R3, #64 // Adjust user sp to end of basic frame (R4) - STMIA R3!, {R4-R11} // Save R4-R11 to user - POP {R4-R8} // Pop current R0-R12 into R4-R8 - STMIA R3!, {R4-R8} // Store them to user stack - STM R3, {LR}^ // Store LR_usr directly - ADD R3, R3, #4 // Adjust user sp to PC - POP {R4-R6} // Pop current LR, PC, CPSR - STMIA R3!, {R5-R6} // Restore user PC and CPSR + SUB R3, R3, #64 // Adjust user sp to end of basic frame (R4) + STMIA R3!, {R4-R11} // Save R4-R11 to user + POP {R4-R8} // Pop current R0-R12 into R4-R8 + STMIA R3!, {R4-R8} // Store them to user stack + STM R3, {LR}^ // Store LR_usr directly + ADD R3, R3, #4 // Adjust user sp to PC + POP {R4-R6} // Pop current LR, PC, CPSR + STMIA R3!, {R5-R6} // Restore user PC and CPSR - SUB R3, R3, #64 // Adjust user sp to R4 + SUB R3, R3, #64 // Adjust user sp to R4 // Check if VFP state need to be saved - MRC p15, 0, R2, c1, c0, 2 // VFP/NEON access enabled? (CPACR) + MRC p15, 0, R2, c1, c0, 2 // VFP/NEON access enabled? (CPACR) AND R2, R2, #0x00F00000 CMP R2, #0x00F00000 - BNE osRtxContextSave1 // Continue, no VFP + BNE osRtxContextSave1 // Continue, no VFP VMRS R2, FPSCR - STMDB R3!, {R2,R12} // Push FPSCR, maintain 8-byte alignment - #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 16 - VSTMDB R3!, {D0-D15} - LDRB R2, [R0, #TCB_SP_FRAME] // Record in TCB that VFP/D16 state is stacked - ORR R2, R2, #2 - STRB R2, [R0, #TCB_SP_FRAME] + STMDB R3!, {R2,R12} // Push FPSCR, maintain 8-byte alignment + + VSTMDB R3!, {D0-D15} // Save D0-D15 + #if __ARM_NEON == 1 + VSTMDB R3!, {D16-D31} // Save D16-D31 #endif - #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 - VSTMDB R3!, {D0-D15} - VSTMDB R3!, {D16-D31} - LDRB R2, [R0, #TCB_SP_FRAME] // Record in TCB that NEON/D32 state is stacked - ORR R2, R2, #4 - STRB R2, [R0, #TCB_SP_FRAME] + LDRB R2, [R0, #TCB_SP_FRAME] + #if __ARM_NEON == 1 + ORR R2, R2, #4 // NEON state + #else + ORR R2, R2, #2 // VFP state #endif + STRB R2, [R0, #TCB_SP_FRAME] // Record VFP/NEON state osRtxContextSave1: - STR R3, [R0, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr + STR R3, [R0, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr osRtxContextRestore: - STR R1, [R12] // Store run.next to run.curr - LDR R3, [R1, #TCB_SP_OFS] // Load next osRtxThread_t.sp - LDRB R2, [R1, #TCB_SP_FRAME] // Load next osRtxThread_t.stack_frame - - ANDS R2, R2, #0x6 // Check stack frame for VFP context - MRC p15, 0, R2, c1, c0, 2 // Read CPACR - ANDEQ R2, R2, #0xFF0FFFFF // Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state - ORRNE R2, R2, #0x00F00000 // Enable VFP/NEON access if incoming task does have stacked VFP/NEON state - MCR p15, 0, R2, c1, c0, 2 // Write CPACR - BEQ osRtxContextRestore1 // No VFP - ISB // Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway - #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 - VLDMIA R3!, {D16-D31} + STR R1, [R12] // Store run.next to run.curr + LDR R3, [R1, #TCB_SP_OFS] // Load next osRtxThread_t.sp + LDRB R2, [R1, #TCB_SP_FRAME] // Load next osRtxThread_t.stack_frame + + ANDS R2, R2, #0x6 // Check stack frame for VFP context + MRC p15, 0, R2, c1, c0, 2 // Read CPACR + ANDEQ R2, R2, #0xFF0FFFFF // Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state + ORRNE R2, R2, #0x00F00000 // Enable VFP/NEON access if incoming task does have stacked VFP/NEON state + MCR p15, 0, R2, c1, c0, 2 // Write CPACR + BEQ osRtxContextRestore1 // No VFP + ISB // Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway + #if __ARM_NEON == 1 + VLDMIA R3!, {D16-D31} // Restore D16-D31 #endif - VLDMIA R3!, {D0-D15} + VLDMIA R3!, {D0-D15} // Restore D0-D15 LDR R2, [R3] - VMSR FPSCR, R2 + VMSR FPSCR, R2 // Restore FPSCR ADD R3, R3, #8 osRtxContextRestore1: - LDMIA R3!, {R4-R11} // Restore R4-R11 - MOV R12, R3 // Move sp pointer to R12 - ADD R3, R3, #32 // Adjust sp - PUSH {R3} // Push sp onto stack - LDMIA SP, {SP}^ // Restore SP_usr - ADD SP, SP, #4 // Adjust SP_svc - LDMIA R12!, {R0-R3} // Restore User R0-R3 - LDR LR, [R12, #12] // Load SPSR into LR - MSR SPSR_cxsf, LR // Restore SPSR - ADD R12, R12, #4 // Adjust pointer to LR - LDM R12, {LR}^ // Restore LR_usr directly into LR - LDR LR, [R12, #4] // Restore LR - LDR R12, [R12, #-4] // Restore R12 - - MOVS PC, LR // Return from exception + LDMIA R3!, {R4-R11} // Restore R4-R11 + MOV R12, R3 // Move sp pointer to R12 + ADD R3, R3, #32 // Adjust sp + PUSH {R3} // Push sp onto stack + LDMIA SP, {SP}^ // Restore SP_usr + ADD SP, SP, #4 // Adjust SP_svc + LDMIA R12!, {R0-R3} // Restore User R0-R3 + LDR LR, [R12, #12] // Load SPSR into LR + MSR SPSR_cxsf, LR // Restore SPSR + ADD R12, R12, #4 // Adjust pointer to LR + LDM R12, {LR}^ // Restore LR_usr directly into LR + LDR LR, [R12, #4] // Restore LR + LDR R12, [R12, #-4] // Restore R12 + + MOVS PC, LR // Return from exception osRtxContextExit: - POP {R0-R3, R12, LR} // Restore stacked APCS registers - RFEFD SP! // Return from exception + POP {R0-R3, R12, LR} // Restore stacked APCS registers + RFEFD SP! // Return from exception .fnend .size osRtxContextSwitch, .-osRtxContextSwitch diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S index acb2b12344d..5379a36b751 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S @@ -42,7 +42,6 @@ TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset PRESERVE8 - ARM SECTION .rodata:DATA:NOROOT(2) @@ -370,19 +369,18 @@ osRtxContextSave VMRS R2, FPSCR STMDB R3!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment - IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16 - VSTMDB R3!, {D0-D15} - LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that VFP/D16 state is stacked - ORR R2, R2, #2 - STRB R2, [R0, #TCB_SP_FRAME] - ENDIF - IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 - VSTMDB R3!, {D0-D15} - VSTMDB R3!, {D16-D31} - LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that NEON/D32 state is stacked - ORR R2, R2, #4 - STRB R2, [R0, #TCB_SP_FRAME] - ENDIF + + VSTMDB R3!, {D0-D15} ; Save D0-D15 + #ifdef __ARM_ADVANCED_SIMD__ + VSTMDB R3!, {D16-D31} ; Save D16-D31 + #endif + LDRB R2, [R0, #TCB_SP_FRAME] + #ifdef __ARM_ADVANCED_SIMD__ + ORR R2, R2, #4 ; NEON state + #else + ORR R2, R2, #2 ; VFP state + #endif + STRB R2, [R0, #TCB_SP_FRAME] ; Record VFP/NEON state osRtxContextSave1 STR R3, [R0, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr @@ -399,12 +397,12 @@ osRtxContextRestore MCR p15, 0, R2, c1, c0, 2 ; Write CPACR BEQ osRtxContextRestore1 ; No VFP ISB ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway - IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 - VLDMIA R3!, {D16-D31} - ENDIF - VLDMIA R3!, {D0-D15} + #ifdef __ARM_ADVANCED_SIMD__ + VLDMIA R3!, {D16-D31} ; Restore D16-D31 + #endif + VLDMIA R3!, {D0-D15} ; Restore D0-D15 LDR R2, [R3] - VMSR FPSCR, R2 + VMSR FPSCR, R2 ; Restore FPSCR ADD R3, R3, #8 osRtxContextRestore1 diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h index c3ee341889b..91d0179e547 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h @@ -73,12 +73,17 @@ static __asm uint32_t __get_PSP (void) { bx lr } #else +#ifdef __ICCARM__ +__arm +#endif __STATIC_INLINE uint32_t __get_PSP (void) { register uint32_t ret; - __asm volatile ( + __ASM volatile ( +#ifndef __ICCARM__ ".syntax unified\n\t" ".arm\n\t" +#endif "sub sp,sp,#4\n\t" "stm sp,{sp}^\n\t" "pop {%[ret]}\n\t" diff --git a/rtos/Thread.cpp b/rtos/Thread.cpp index 20c1a083de6..e773e63d843 100644 --- a/rtos/Thread.cpp +++ b/rtos/Thread.cpp @@ -129,7 +129,11 @@ osStatus Thread::terminate() { _tid = (osThreadId_t)NULL; if (!_finished) { _finished = true; - ret = osThreadTerminate(local_id); + // if local_id == 0 Thread was not started in first place + // and does not have to be terminated + if (local_id != 0) { + ret = osThreadTerminate(local_id); + } } _mutex.unlock(); return ret; diff --git a/rtos/Thread.h b/rtos/Thread.h index d67ad3acf81..9f82ec0ed0e 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -80,6 +80,8 @@ class Thread : private mbed::NonCopyable { @param stack_size stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE). @param stack_mem pointer to the stack area to be used by this thread (default: NULL). @param name name to be used for this thread. It has to stay allocated for the lifetime of the thread (default: NULL) + + @note You cannot call this function from ISR context. */ Thread(osPriority priority=osPriorityNormal, uint32_t stack_size=OS_STACK_SIZE, @@ -103,6 +105,8 @@ class Thread : private mbed::NonCopyable { error("oh no!"); } @endcode + + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Thread-spawning constructors hide errors. " @@ -131,6 +135,8 @@ class Thread : private mbed::NonCopyable { error("oh no!"); } @endcode + + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -161,6 +167,8 @@ class Thread : private mbed::NonCopyable { error("oh no!"); } @endcode + + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -192,6 +200,8 @@ class Thread : private mbed::NonCopyable { error("oh no!"); } @endcode + + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Thread-spawning constructors hide errors. " @@ -208,6 +218,8 @@ class Thread : private mbed::NonCopyable { @param task function to be executed by this thread. @return status code that indicates the execution status of the function. @note a thread can only be started once + + @note You cannot call this function ISR context. */ osStatus start(mbed::Callback task); @@ -217,6 +229,8 @@ class Thread : private mbed::NonCopyable { @return status code that indicates the execution status of the function. @deprecated The start function does not support cv-qualifiers. Replaced by start(callback(obj, method)). + + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -229,28 +243,38 @@ class Thread : private mbed::NonCopyable { /** Wait for thread to terminate @return status code that indicates the execution status of the function. @note not callable from interrupt + + @note You cannot call this function from ISR context. */ osStatus join(); /** Terminate execution of a thread and remove it from Active Threads @return status code that indicates the execution status of the function. + + @note You cannot call this function from ISR context. */ osStatus terminate(); /** Set priority of an active thread @param priority new priority value for the thread function. @return status code that indicates the execution status of the function. + + @note You cannot call this function from ISR context. */ osStatus set_priority(osPriority priority); /** Get priority of an active thread @return current priority value of the thread function. + + @note You cannot call this function from ISR context. */ osPriority get_priority(); /** Set the specified Thread Flags for the thread. @param signals specifies the signal flags of the thread that should be set. @return signal flags after setting or osFlagsError in case of incorrect parameters. + + @note You may call this function from ISR context. */ int32_t signal_set(int32_t signals); @@ -279,37 +303,51 @@ class Thread : private mbed::NonCopyable { /** State of this Thread @return the State of this Thread + + @note You cannot call this function from ISR context. */ State get_state(); /** Get the total stack memory size for this Thread @return the total stack memory size in bytes + + @note You cannot call this function from ISR context. */ uint32_t stack_size(); /** Get the currently unused stack memory for this Thread @return the currently unused stack memory in bytes + + @note You cannot call this function from ISR context. */ uint32_t free_stack(); /** Get the currently used stack memory for this Thread @return the currently used stack memory in bytes + + @note You cannot call this function from ISR context. */ uint32_t used_stack(); /** Get the maximum stack memory usage to date for this Thread @return the maximum stack memory usage to date in bytes + + @note You cannot call this function from ISR context. */ uint32_t max_stack(); /** Get thread name @return thread name or NULL if the name was not set. + + @note You may call this function from ISR context. */ const char *get_name(); /** Clears the specified Thread Flags of the currently running thread. @param signals specifies the signal flags of the thread that should be cleared. @return signal flags before clearing or osFlagsError in case of incorrect parameters. + + @note You cannot call this function from ISR context. */ static int32_t signal_clr(int32_t signals); @@ -317,38 +355,51 @@ class Thread : private mbed::NonCopyable { @param signals wait until all specified signal flags are set or 0 for any single signal flag. @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return event flag information or error code. @note if @a millisec is set to 0 and flag is no set the event carries osOK value. - @note not callable from interrupt + + @note You cannot call this function from ISR context. */ static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever); /** Wait for a specified time period in millisec: @param millisec time delay value @return status code that indicates the execution status of the function. - @note not callable from interrupt + + @note You cannot call this function from ISR context. */ static osStatus wait(uint32_t millisec); /** Pass control to next thread that is in state READY. @return status code that indicates the execution status of the function. - @note not callable from interrupt + + @note You cannot call this function from ISR context. */ static osStatus yield(); /** Get the thread id of the current running thread. @return thread ID for reference by other functions or NULL in case of error. + + @note You may call this function from ISR context. */ static osThreadId gettid(); /** Attach a function to be called by the RTOS idle task @param fptr pointer to the function to be called + + @note You may call this function from ISR context. */ static void attach_idle_hook(void (*fptr)(void)); /** Attach a function to be called when a task is killed @param fptr pointer to the function to be called + + @note You may call this function from ISR context. */ static void attach_terminate_hook(void (*fptr)(osThreadId id)); + /** Thread destructor + * + * @note You cannot call this function from ISR context. + */ virtual ~Thread(); private: diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c index be30d4c5e74..7593a5ae04e 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c @@ -45,7 +45,7 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * *****************************************************************************/ #include -#ifdef __CC_ARM +#ifdef __ARMCC_VERSION #include #endif #include @@ -61,8 +61,8 @@ extern void SramInit(void); /*---------------------------------------------------------------------------- Checksum options *----------------------------------------------------------------------------*/ - #if defined (__CC_ARM) -__attribute__ ((at(0x000001A0u))) +#if defined (__ARMCC_VERSION) +__attribute__((section(".ARM.__at_0x000001A0"))) #elif defined( __ICCARM__) __root #endif /* __ICCARM__ */ @@ -151,7 +151,7 @@ const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) = /*---------------------------------------------------------------------------- * Initialize .bss and .data for GNU *----------------------------------------------------------------------------*/ -#if defined( __GNUC__) && !defined (__CC_ARM) +#if defined( __GNUC__) && !defined (__ARMCC_VERSION) void zero_bss(void) { uint32_t *pSrc, *pDest; @@ -248,7 +248,7 @@ void Reset_Handler(void) may reside in DSRAM bank B. */ SramInit(); -#if defined(__GNUC__) && !defined (__CC_ARM) +#if defined(__GNUC__) && !defined (__ARMCC_VERSION) /* Clear the bss section for GCC build only */ zero_bss(); #endif @@ -263,7 +263,7 @@ void Reset_Handler(void) /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ -#if defined(__CC_ARM) || defined (__GNUC__) +#if defined(__ARMCC_VERSION) || defined (__GNUC__) void Default_Handler(void) { while(1); diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h index 32232566acf..768bae88f92 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h @@ -63,16 +63,14 @@ RESET_EXCPT_HNDLR #define VECTOR_SECTION ".vectors" -#ifdef __CC_ARM -extern unsigned Image$$ADUCM_HEAP$$Base[]; -extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[]; +#ifdef __ARMCC_VERSION void Default_Handler(void); -#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) -#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define SECTION_NAME(sectionname) __attribute__((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__((section(sectionname))) #define IVT_NAME __Vectors #define RESET_EXCPT_HNDLR __main #define COMPILER_NAME "ARMCC" -#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#define WEAK_FUNCTION(x) void x (void) __attribute__((weak, alias("Default_Handler"))); #elif defined(__ICCARM__) #pragma diag_suppress=Pm093,Pm140 diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c index 91905d61bd5..621c8b20387 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c @@ -47,7 +47,6 @@ #include "pinmap.h" #include "PeripheralPins.h" - #ifdef __cplusplus extern "C" { #endif @@ -80,7 +79,10 @@ void analogin_init(analogin_t *obj, PinName pin) ADCName peripheral; uint32_t function, channel; - peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + memset(obj, 0, sizeof(analogin_t) ); + memset( DeviceMemory, 0, sizeof( DeviceMemory ) ); + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral MBED_ASSERT(peripheral != (ADCName)NC); /* verify read function */ @@ -142,6 +144,7 @@ void analogin_init(analogin_t *obj, PinName pin) /* Set the acquisition time. (Application need to change it based on the impedence) */ adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles); + } /** Read the input voltage, represented as a float in the range [0.0, 1.0] @@ -165,6 +168,11 @@ uint16_t analogin_read_u16(analogin_t *obj) { ADI_ADC_HANDLE hDevice = obj->hDevice; ADI_ADC_BUFFER *pAdcBuffer; + uint32_t ADCsample; + + obj->UserBuffer.pDataBuffer = &ADCsample; + obj->UserBuffer.nNumConversionPasses = 1; + obj->UserBuffer.nBuffSize = 1; /* Submit the buffer to the driver */ adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); @@ -178,8 +186,9 @@ uint16_t analogin_read_u16(analogin_t *obj) return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); } -/* Retrieve te active channel correspondoing to the input pin */ -static uint32_t adi_pin2channel(PinName pin) { +/* Retrieve the active channel corresponding to the input pin */ +static uint32_t adi_pin2channel(PinName pin) +{ uint32_t activech; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c index fdaa7d603c2..86ca3b952ce 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c @@ -46,9 +46,12 @@ #define MUX_FUNC_0 0x0 #define NUM_GPIO_PORTS 4 - -extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; -extern uint8_t gpio_initialized; +/******************************************************************************* + ADI_GPIO_DEV_DATA Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ +extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; +extern uint8_t gpio_initialized; static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0}; static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0}; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c index 5e0d99ad8b0..838463fdc37 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c @@ -39,9 +39,12 @@ ******************************************************************************/ #include - +/******************************************************************************* + ADI_GPIO_DEV_DATA Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ // ADI GPIO device driver state memory. Only one state memory is required globally. -uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; // Flag to indicate whether the GPIO driver has been initialized -uint8_t gpio_initialized = 0; +uint8_t gpio_initialized = 0; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c index ea62c3d3bae..5fc3b59e2da 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c @@ -53,9 +53,12 @@ typedef struct { gpio_irq_event event; uint8_t int_enable; } gpio_chan_info_t; - -extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; -extern uint8_t gpio_initialized; +/******************************************************************************* + ADI_GPIO_DEV_DATA Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ +extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; +extern uint8_t gpio_initialized; static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; static gpio_irq_handler irq_handler = NULL; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c index 7f0b1c09837..6abd9bf79c1 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c @@ -57,7 +57,11 @@ int adi_i2c_memtype = 0; #endif #else -static uint8_t i2c_Mem[ADI_I2C_MEMORY_SIZE]; +/******************************************************************************* + ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ +static uint32_t i2c_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4]; static ADI_I2C_HANDLE i2c_Handle; #if defined(ADI_DEBUG) #warning "BUILD_I2C_MI_DYNAMIC is NOT defined. Memory allocation for I2C will be static" @@ -72,7 +76,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); ADI_I2C_HANDLE *pI2C_Handle; - uint8_t *I2C_Mem; + uint32_t *I2C_Mem; ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; uint32_t I2C_DevNum = I2C_0; /* ADuCM3029 only has 1 I2C port */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h index d57a3b21ded..73ed3c6f064 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h @@ -79,7 +79,11 @@ struct i2c_s { ADI_I2C_HANDLE *pI2C_Handle; #if defined(BUILD_I2C_MI_DYNAMIC) ADI_I2C_HANDLE I2C_Handle; - uint8_t I2C_Mem[ADI_I2C_MEMORY_SIZE]; +/******************************************************************************* + ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ + uint32_t I2C_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4]; #endif }; @@ -90,7 +94,11 @@ struct spi_s { ADI_SPI_HANDLE *pSPI_Handle; #if defined(BUILD_SPI_MI_DYNAMIC) ADI_SPI_HANDLE SPI_Handle; - uint8_t SPI_Mem[ADI_SPI_MEMORY_SIZE]; +/******************************************************************************* + ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ + uint32_t SPI_Mem[(ADI_SPI_MEMORY_SIZE + 3)/4]; #endif }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c index a1d6c95243c..c5638d69be2 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c @@ -46,7 +46,11 @@ #include "adi_pwr.h" #define RTC_DEVICE_NUM 0 -static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE]; +/******************************************************************************* + ADI_RTC_DEVICE Instance memory containing memory pointer should guarantee + 4 byte alignmnet. + *******************************************************************************/ +static uint32_t aRtcDevMem0[(ADI_RTC_MEMORY_SIZE + 3)/4]; static ADI_RTC_HANDLE hDevice0 = NULL; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c index f5ef0bc4157..dbecf7a1494 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c @@ -59,12 +59,16 @@ int adi_spi_memtype = 0; #endif #else +/******************************************************************************* + ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ ADI_SPI_HANDLE spi_Handle0; -uint8_t spi_Mem0[ADI_SPI_MEMORY_SIZE]; +uint32_t spi_Mem0[(ADI_SPI_MEMORY_SIZE + 3)/4]; ADI_SPI_HANDLE spi_Handle1; -uint8_t spi_Mem1[ADI_SPI_MEMORY_SIZE]; +uint32_t spi_Mem1[(ADI_SPI_MEMORY_SIZE + 3)/4]; ADI_SPI_HANDLE spi_Handle2; -uint8_t spi_Mem2[ADI_SPI_MEMORY_SIZE]; +uint32_t spi_Mem2[(ADI_SPI_MEMORY_SIZE + 3)/4]; #if defined(ADI_DEBUG) #warning "BUILD_SPI_MI_DYNAMIC is NOT defined. Memory allocation for SPI will be static" int adi_spi_memtype = 1; @@ -92,7 +96,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); ADI_SPI_HANDLE *pSPI_Handle; - uint8_t *SPI_Mem; + uint32_t *SPI_Mem; ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; uint32_t nDeviceNum = 0; ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c index cb346f9342f..a7c512ab633 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c @@ -54,8 +54,15 @@ #define TRNG_CNT_VAL 4095 #define TRNG_PRESCALER 2 -/* RNG Device memory */ -static uint8_t RngDevMem[ADI_RNG_MEMORY_SIZE]; +/******************************************************************************* + RNG Device memory is the instance of ADI_RNG_DEV_DATA_TYPE that contains + pointers and requires 4 byte alignment. The use of uint8_t may cause memory + access fault for some compilers which are not configured to handle unaligned + accesses to SRAM. The size in uint8_t for RngDevMem is ADI_RNG_MEMORY_SIZE. + The size in uint32_t for RngDevMem is recalculated to be + (ADI_RNG_MEMORY_SIZE + 3)/4. + *******************************************************************************/ +static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4]; void trng_init(trng_t *obj) { diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h index f9a61b742d0..8e2f650cb15 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h @@ -62,10 +62,6 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #pragma diag_suppress=Pm008,Pm093 #endif /* __ICCARM__ */ -#if defined (__CC_ARM) -#pragma anon_unions -#endif /* __CC_ARM */ - #define __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ #include diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c index 458e71a3975..45bb0f6ebf4 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c @@ -123,7 +123,7 @@ POSSIBILITY OF SUCH DAMAGE. #define __ADI_BYTE_SWAP(X) __REV(X) #elif defined (__GNUC__) #define __ADI_BYTE_SWAP(X) __builtin_bswap32(X) -#elif defined (__CC_ARM) +#elif defined (__ARMCC_VERSION) #define __ADI_BYTE_SWAP(X) __rev(X) #else #error "This toolchain is not supported" diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c index 7ced9f04492..66474469ea6 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c @@ -272,7 +272,7 @@ ADI_DMA_RESULT adi_dma_RegisterCallback ( /* ARM Cortex-M3/M4, GNU-ARM compiler */ #define ADI_CLZ(X) __builtin_clz(X) -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) /* ARM Cortex-M3/M4, Keil compiler */ #define ADI_CLZ(X) __clz(X) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h index 0540cea56ed..e6f8571f1b4 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h @@ -82,10 +82,10 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define ADI_ALIGNED_ATTRIBUTE(num) #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) #define ADI_UNUSED_ATTRIBUTE -#elif defined (__CC_ARM) +#elif defined (__ARMCC_VERSION) /* Keil uses a decorator which is placed in the same position as pragmas */ #define ADI_ALIGNED_ATTRIBUTE(num) - #define ADI_ALIGNED_PRAGMA(num) __align(##num) + #define ADI_ALIGNED_PRAGMA(num) __attribute__((aligned(num))) #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) #else #error "Toolchain not supported" diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h index b1dca858030..08c509962b8 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h @@ -25,12 +25,6 @@ /* pickup register bitfield and bit masks */ #include "ADuCM302x_typedefs.h" -#if defined ( __CC_ARM ) -#pragma push -#pragma anon_unions -#endif - - #ifndef __IO #ifdef __cplusplus #define __I volatile /* read-only */ @@ -1209,9 +1203,4 @@ typedef enum #pragma diag(pop) #endif /* _MISRA_RULES */ - -#if defined (__CC_ARM) -#pragma pop -#endif - #endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h index ea2c5d22ac7..a151f993fe3 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h @@ -22,12 +22,6 @@ #include #endif /* _LANGUAGE_C */ -#if defined ( __CC_ARM ) -#pragma push -#pragma anon_unions -#endif - - #if defined (_MISRA_RULES) /* anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. @@ -9556,9 +9550,4 @@ typedef struct _ADI_NVIC_INTCID3_t { #pragma diag(pop) #endif /* _MISRA_RULES */ - -#if defined (__CC_ARM) -#pragma pop -#endif - #endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c index f88ee01be89..3c06ae2b245 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c @@ -44,7 +44,7 @@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * *****************************************************************************/ -#ifdef __CC_ARM +#ifdef __ARMCC_VERSION #include #include #endif @@ -55,8 +55,8 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /*---------------------------------------------------------------------------- Checksum options *----------------------------------------------------------------------------*/ -#if defined (__CC_ARM) -__attribute__ ((at(0x000001A0u))) +#if defined (__ARMCC_VERSION) +__attribute__((section(".ARM.__at_0x000001A0"))) #elif defined(__ICCARM__) __root #endif @@ -155,7 +155,7 @@ const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) = { /*---------------------------------------------------------------------------- * Initialize .bss and .data for GNU *----------------------------------------------------------------------------*/ -#if defined( __GNUC__) && !defined (__CC_ARM) +#if defined( __GNUC__) && !defined (__ARMCC_VERSION) void zero_bss(void) { uint32_t *pSrc, *pDest; @@ -251,7 +251,7 @@ void Reset_Handler(void) /* Initialize SRAM configuration. */ SramInit(); -#if defined(__GNUC__) && !defined (__CC_ARM) +#if defined(__GNUC__) && !defined (__ARMCC_VERSION) zero_bss(); #endif @@ -265,7 +265,7 @@ void Reset_Handler(void) /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ -#if defined(__CC_ARM) || defined (__GNUC__) +#if defined(__ARMCC_VERSION) || defined (__GNUC__) void Default_Handler(void) { while(1); diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h index 98da5428c3a..d1485407633 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h @@ -63,16 +63,14 @@ RESET_EXCPT_HNDLR #include #define VECTOR_SECTION ".vectors" -#ifdef __CC_ARM -extern unsigned Image$$ADUCM_HEAP$$Base[]; -extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[]; +#ifdef __ARMCC_VERSION void Default_Handler(void); -#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) -#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define SECTION_NAME(sectionname) __attribute__((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__((section(sectionname))) #define IVT_NAME __Vectors #define RESET_EXCPT_HNDLR __main #define COMPILER_NAME "ARMCC" -#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#define WEAK_FUNCTION(x) void x (void) __attribute__((weak, alias("Default_Handler"))); #elif defined(__ICCARM__) /* * IAR MISRA C 2004 error suppressions: diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c index baa96a694ef..621c8b20387 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -79,7 +79,10 @@ void analogin_init(analogin_t *obj, PinName pin) ADCName peripheral; uint32_t function, channel; - peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + memset(obj, 0, sizeof(analogin_t) ); + memset( DeviceMemory, 0, sizeof( DeviceMemory ) ); + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral MBED_ASSERT(peripheral != (ADCName)NC); /* verify read function */ @@ -165,6 +168,11 @@ uint16_t analogin_read_u16(analogin_t *obj) { ADI_ADC_HANDLE hDevice = obj->hDevice; ADI_ADC_BUFFER *pAdcBuffer; + uint32_t ADCsample; + + obj->UserBuffer.pDataBuffer = &ADCsample; + obj->UserBuffer.nNumConversionPasses = 1; + obj->UserBuffer.nBuffSize = 1; /* Submit the buffer to the driver */ adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); @@ -178,7 +186,7 @@ uint16_t analogin_read_u16(analogin_t *obj) return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); } -/* Retrieve te active channel correspondoing to the input pin */ +/* Retrieve the active channel corresponding to the input pin */ static uint32_t adi_pin2channel(PinName pin) { diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c index 81d4be52cb7..c1549dc93f7 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c @@ -46,9 +46,12 @@ #define MUX_FUNC_0 0x0 #define NUM_GPIO_PORTS 4 - -extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; -extern uint8_t gpio_initialized; +/******************************************************************************* + ADI_GPIO_DEV_DATA Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ +extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; +extern uint8_t gpio_initialized; static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0}; static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0}; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c index 5e0d99ad8b0..bf61417b93f 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c @@ -39,9 +39,12 @@ ******************************************************************************/ #include - +/******************************************************************************* + ADI_GPIO_DEV_DATA Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ // ADI GPIO device driver state memory. Only one state memory is required globally. -uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE +3)/4]; // Flag to indicate whether the GPIO driver has been initialized -uint8_t gpio_initialized = 0; +uint8_t gpio_initialized = 0; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c index 3cf237218bd..93d637d28b2 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c @@ -52,9 +52,12 @@ typedef struct { gpio_irq_event event; uint8_t int_enable; } gpio_chan_info_t; - -extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; -extern uint8_t gpio_initialized; +/******************************************************************************* + ADI_GPIO_DEV_DATA Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ +extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; +extern uint8_t gpio_initialized; static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; static gpio_irq_handler irq_handler = NULL; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c index f25d80c9105..953cab289cd 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c @@ -57,7 +57,11 @@ int adi_i2c_memtype = 0; #endif #else -static uint8_t i2c_Mem[ADI_I2C_MEMORY_SIZE]; +/******************************************************************************* + ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ +static uint32_t i2c_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4]; static ADI_I2C_HANDLE i2c_Handle; #if defined(ADI_DEBUG) #warning "BUILD_I2C_MI_DYNAMIC is NOT defined. Memory allocation for I2C will be static" @@ -72,7 +76,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); ADI_I2C_HANDLE *pI2C_Handle; - uint8_t *I2C_Mem; + uint32_t *I2C_Mem; ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; uint32_t I2C_DevNum = I2C_0; /* ADuCM4050 only has 1 I2C port */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h index 495faf8c671..3ed6109d7d2 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h @@ -79,7 +79,11 @@ struct i2c_s { ADI_I2C_HANDLE *pI2C_Handle; #if defined(BUILD_I2C_MI_DYNAMIC) ADI_I2C_HANDLE I2C_Handle; - uint8_t I2C_Mem[ADI_I2C_MEMORY_SIZE]; +/******************************************************************************* + ADI_I2C_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ + uint32_t I2C_Mem[(ADI_I2C_MEMORY_SIZE + 3)/4]; #endif }; @@ -90,7 +94,11 @@ struct spi_s { ADI_SPI_HANDLE *pSPI_Handle; #if defined(BUILD_SPI_MI_DYNAMIC) ADI_SPI_HANDLE SPI_Handle; - uint8_t SPI_Mem[ADI_SPI_MEMORY_SIZE]; +/******************************************************************************* + ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ + uint32_t SPI_Mem[(ADI_SPI_MEMORY_SIZE + 3)/4]; #endif }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c index 8b650705fc6..9fd36be3383 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c @@ -46,7 +46,11 @@ #include "adi_pwr.h" #define RTC_DEVICE_NUM 0 -static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE]; +/******************************************************************************* + ADI_RTC_DEVICE Instance memory containing memory pointer should guarantee + 4 byte alignmnet. + *******************************************************************************/ +static uint32_t aRtcDevMem0[(ADI_RTC_MEMORY_SIZE + 3)/4]; static ADI_RTC_HANDLE hDevice0 = NULL; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c index a52406889b9..7f9fd048c5e 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -61,12 +61,16 @@ int adi_spi_memtype = 0; #endif #else +/******************************************************************************* + ADI_SPI_DEV_DATA_TYPE Instance memory containing memory pointer should + guarantee 4 byte alignmnet. + *******************************************************************************/ ADI_SPI_HANDLE spi_Handle0; -uint8_t spi_Mem0[ADI_SPI_MEMORY_SIZE]; +uint32_t spi_Mem0[(ADI_SPI_MEMORY_SIZE + 3)/4]; ADI_SPI_HANDLE spi_Handle1; -uint8_t spi_Mem1[ADI_SPI_MEMORY_SIZE]; +uint32_t spi_Mem1[(ADI_SPI_MEMORY_SIZE + 3)/4]; ADI_SPI_HANDLE spi_Handle2; -uint8_t spi_Mem2[ADI_SPI_MEMORY_SIZE]; +uint32_t spi_Mem2[(ADI_SPI_MEMORY_SIZE + 3)/4]; #if defined(ADI_DEBUG) #warning "BUILD_SPI_MI_DYNAMIC is NOT defined. Memory allocation for SPI will be static" int adi_spi_memtype = 1; @@ -94,7 +98,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); ADI_SPI_HANDLE *pSPI_Handle; - uint8_t *SPI_Mem; + uint32_t *SPI_Mem; ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; uint32_t nDeviceNum = 0; ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c index e9405571657..f46d62d45ea 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c @@ -121,7 +121,7 @@ POSSIBILITY OF SUCH DAMAGE. #define __ADI_BYTE_SWAP(X) __REV(X) #elif defined (__GNUC__) #define __ADI_BYTE_SWAP(X) __builtin_bswap32(X) -#elif defined (__CC_ARM) +#elif defined (__ARMCC_VERSION) #define __ADI_BYTE_SWAP(X) __rev(X) #else #error "This toolchain is not supported" diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c index 7ced9f04492..66474469ea6 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c @@ -272,7 +272,7 @@ ADI_DMA_RESULT adi_dma_RegisterCallback ( /* ARM Cortex-M3/M4, GNU-ARM compiler */ #define ADI_CLZ(X) __builtin_clz(X) -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) /* ARM Cortex-M3/M4, Keil compiler */ #define ADI_CLZ(X) __clz(X) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h index 0540cea56ed..e6f8571f1b4 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h @@ -82,10 +82,10 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define ADI_ALIGNED_ATTRIBUTE(num) #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) #define ADI_UNUSED_ATTRIBUTE -#elif defined (__CC_ARM) +#elif defined (__ARMCC_VERSION) /* Keil uses a decorator which is placed in the same position as pragmas */ #define ADI_ALIGNED_ATTRIBUTE(num) - #define ADI_ALIGNED_PRAGMA(num) __align(##num) + #define ADI_ALIGNED_PRAGMA(num) __attribute__((aligned(num))) #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) #else #error "Toolchain not supported" diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h index 858848297b3..3326f40824d 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h @@ -25,12 +25,6 @@ /* pickup register bitfield and bit masks */ #include "adi_ADuCM4050_typedefs.h" -#if defined ( __CC_ARM ) -#pragma push -#pragma anon_unions -#endif - - #ifndef __IO #ifdef __cplusplus #define __I volatile /* read-only */ @@ -1330,9 +1324,4 @@ typedef enum #pragma diag(pop) #endif /* _MISRA_RULES */ - -#if defined (__CC_ARM) -#pragma pop -#endif - #endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h index 356eea0165d..7872e766ded 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h @@ -22,12 +22,6 @@ #include #endif /* _LANGUAGE_C */ -#if defined ( __CC_ARM ) -#pragma push -#pragma anon_unions -#endif - - #if defined (_MISRA_RULES) /* anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. @@ -11244,9 +11238,4 @@ typedef struct _ADI_NVIC_INTCID3_t { #pragma diag(pop) #endif /* _MISRA_RULES */ - -#if defined (__CC_ARM) -#pragma pop -#endif - #endif diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c index 7a8ca2608eb..ebb7042922c 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c @@ -71,7 +71,11 @@ time_t rtc_read(void) timeinfo.tm_year = (ul_year - 1900); /* Convert to timestamp */ - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } + return t; } @@ -81,8 +85,9 @@ void rtc_write(time_t t) /* Initialize the RTC is not yet initialized */ rtc_init(); } + struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { return; } uint32_t ul_hour, ul_minute, ul_second; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct index 7cee92692d5..b41077400c6 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct @@ -55,14 +55,22 @@ #define __ram_vector_table_size__ 0x00000000 #endif -#define m_interrupts_start 0x00000000 +#if !defined(MBED_APP_START) + #define MBED_APP_START 0 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +#define m_interrupts_start MBED_APP_START #define m_interrupts_size 0x00000400 -#define m_flash_config_start 0x00000400 +#define m_flash_config_start MBED_APP_START + 0x400 #define m_flash_config_size 0x00000010 -#define m_text_start 0x00000410 -#define m_text_size 0x000FFBF0 +#define m_text_start MBED_APP_START + 0x410 +#define m_text_size MBED_APP_SIZE - 0x410 #define m_interrupts_ram_start 0x1FFF0000 #define m_interrupts_ram_size __ram_vector_table_size__ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld index 4847b765165..1bd9786a6c5 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld @@ -56,16 +56,24 @@ __ram_vector_table__ = 1; __stack_size__ = 0x8000; __heap_size__ = 0x10000; -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x8000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000; M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 + m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x400 + m_flash_config (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10 + m_text (RX) : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf index 4b753e15d1b..eaff80afa66 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf @@ -52,17 +52,25 @@ define symbol __ram_vector_table__ = 1; define symbol __stack_size__=0x8000; define symbol __heap_size__=0x10000; +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = 0; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = 0x100000; +} + define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; +define symbol m_interrupts_start = MBED_APP_START; +define symbol m_interrupts_end = MBED_APP_START + 0x3FF; -define symbol m_flash_config_start = 0x00000400; -define symbol m_flash_config_end = 0x0000040F; +define symbol m_flash_config_start = MBED_APP_START + 0x400; +define symbol m_flash_config_end = MBED_APP_START + 0x40F; -define symbol m_text_start = 0x00000410; -define symbol m_text_end = 0x000FFFFF; +define symbol m_text_start = MBED_APP_START + 0x410; +define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; define symbol m_interrupts_ram_start = 0x1FFF0000; define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device_key_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device_key_api.c new file mode 100644 index 00000000000..8079e7d8f74 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device_key_api.c @@ -0,0 +1,60 @@ +/* + * Return the values stored in registers UIDH, UIDMH, UIDML, UIDL. This value is predictable therefore not secure, but used as example + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * Reference: "K64 Sub-Family Reference Manual, Rev. 2", chapter 13.2.22 + */ + +#if defined(DEVICE_DEVKEY) + +#include +#include "cmsis.h" +#include "fsl_common.h" +#include "fsl_clock.h" +#include "device_key_api.h" + + +int device_key_get_value(uint32_t *output, size_t *length) +{ + unsigned int i; + + if (*length < DEVICE_KEY_LEN) + return -1; + + for (i=0;i<*length;i++){ + *(((char *)output)+i) = 0; + } + + *output++ = SIM->UIDH; + *output++ = SIM->UIDML; + *output++ = SIM->UIDMH; + *output++ = SIM->UIDL; + *length=sizeof(*output)*4; + + return 0; +} + + +int device_key_get_size_in_bytes() +{ + return DEVICE_KEY_LEN; +} + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct deleted file mode 100644 index 496f79dfea4..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct +++ /dev/null @@ -1,13 +0,0 @@ -LR_IROM1 0x21000 0x00DF000 { - ER_IROM1 0x21000 0x00DF000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM0 0x20003288 UNINIT 0x000000F8 { ;no init section - *(*noinit) - } - RW_IRAM1 0x20003380 0x0003cc80 { - .ANY (+RW +ZI) - } -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct new file mode 100644 index 00000000000..0aaa703e9f4 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct @@ -0,0 +1,23 @@ +#! armcc -E + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x21000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0xDF000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM0 0x20003288 UNINIT 0x000000F8 { ;no init section + *(*noinit) + } + RW_IRAM1 0x20003380 0x0003cc80 { + .ANY (+RW +ZI) + } +} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld index 16b5bf1d4f0..6f4fe7a0ec3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld @@ -16,9 +16,17 @@ /* Linker script to configure memory regions. */ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x21000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0xDF000 +#endif + MEMORY { - FLASH (rx) : ORIGIN = 0x21000, LENGTH = 0xDF000 + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = 0x20003288, LENGTH = 0x3cd78 } @@ -130,7 +138,7 @@ SECTIONS PROVIDE(__start_fs_data = .); KEEP(*(.fs_data)) PROVIDE(__stop_fs_data = .); - + *(.jcr) . = ALIGN(4); /* All data end */ @@ -146,7 +154,7 @@ SECTIONS KEEP(*(.noinit)) PROVIDE(__stop_noinit = .); } > RAM - + .bss : { . = ALIGN(4); diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf similarity index 82% rename from targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf index 6c0e4f7ebad..7561156daa9 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf @@ -1,15 +1,26 @@ /*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = 0x21000; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = 0xDF000; +} + /*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x21000; +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; + /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x21000; -define symbol __ICFEDIT_region_ROM_end__ = 0xfffff; +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_RAM_start__ = 0x20003288; define symbol __ICFEDIT_region_RAM_end__ = 0x2003ffff; export symbol __ICFEDIT_region_RAM_start__; export symbol __ICFEDIT_region_RAM_end__; + /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/ define symbol __ICFEDIT_size_cstack__ = 0x800; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h index f40e4576e2f..5e6392213bb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h @@ -1,28 +1,28 @@ -/* +/* * Copyright (c) 2013 Nordic Semiconductor ASA * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list + * + * 1. Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior * written permission. * - * 4. This software, with or without modification, must only be used with a + * 4. This software, with or without modification, must only be used with a * Nordic Semiconductor ASA integrated circuit. * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -33,7 +33,7 @@ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ @@ -57,7 +57,7 @@ #include "app_error.h" #include "app_util.h" -#define BLE_STACK_EVT_MSG_BUF_SIZE (sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT)) /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */ +#define BLE_STACK_EVT_MSG_BUF_SIZE (sizeof(ble_evt_t) + (3 * sizeof(ble_gattc_attr_info_t)) + (GATT_MTU_SIZE_DEFAULT)) /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */ #define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0 /**< The size of the scheduler event used by SoftDevice handler when passing BLE events using the @ref app_scheduler. */ /**@brief Application stack event handler type. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c index 4f942631964..f1937d3787d 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c @@ -15,43 +15,93 @@ * limitations under the License. */ -#include // uint32_t, UINT32_MAX -#include // uint32_t, UINT32_MAX -#include "cmsis.h" -#include "nrf_soc.h" -#include "nrf_sdm.h" -#include "nrf_nvic.h" +#include +#include "app_util_platform.h" -static uint8_t _sd_state = 0; -static volatile uint32_t _entry_count = 0; +#if defined(SOFTDEVICE_PRESENT) +static volatile bool state_saved = false; -void core_util_critical_section_enter() +static void nordic_nvic_critical_region_enter(void); +static void nordic_nvic_critical_region_exit(void); +#endif + +void hal_critical_section_enter() { - // if a critical section has already been entered, just update the counter - if (_entry_count) { - ++_entry_count; - return; - } +#ifdef NRF52 + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + nordic_nvic_critical_region_enter(); +#else + app_util_disable_irq(); +#endif +} - // in this path, a critical section has never been entered - // routine of SD V11 work even if the softdevice is not active - sd_nvic_critical_region_enter(&_sd_state); +void hal_critical_section_exit() +{ +#ifdef NRF52 + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif - assert(_entry_count == 0); // entry count should always be equal to 0 at this point - ++_entry_count; +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + nordic_nvic_critical_region_exit(); +#else + app_util_enable_irq(); +#endif } -void core_util_critical_section_exit() + +bool hal_in_critical_section(void) { - assert(_entry_count > 0); - --_entry_count; + return (state_saved != 0); +} + - // If their is other segments which have entered the critical section, just leave - if (_entry_count) { - return; +#if defined(SOFTDEVICE_PRESENT) +/**@brief Enters critical region. + * + * @post Application interrupts will be disabled. + * @sa nordic_nvic_critical_region_exit + */ +static inline void nordic_nvic_critical_region_enter(void) +{ + int was_masked = __sd_nvic_irq_disable(); + + if (state_saved == false) { + nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; +#ifdef NRF52 + nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; +#endif } - // This is the last segment of the critical section, state should be restored as before entering - // the critical section - sd_nvic_critical_region_exit(_sd_state); + state_saved = true; + + if (!was_masked) { + __sd_nvic_irq_enable(); + } +} + +/**@brief Exit critical region. + * + * @pre Application has entered a critical region using ::nordic_nvic_critical_region_enter. + * @post If not in a nested critical region, the application interrupts will restored to the state before ::nordic_nvic_critical_region_enter was called. + */ +static inline void nordic_nvic_critical_region_exit(void) +{ + state_saved = false; + + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; +#ifdef NRF52 + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; +#endif + if (!was_masked) { + __sd_nvic_irq_enable(); + } } +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c index 39f4e8e30ba..27589ccc39e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c @@ -37,6 +37,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c index fd3fa1b1a04..dc5e62bf245 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c @@ -94,7 +94,10 @@ time_t rtc_read(void) timeinfo.tm_sec = rtc_datetime.u32Second; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -104,10 +107,10 @@ void rtc_write(time_t t) if (! rtc_isenabled()) { rtc_init(); } - + // Convert timestamp to struct tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { return; } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c new file mode 100644 index 00000000000..808bfd38b8b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c @@ -0,0 +1,255 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "cmsis.h" +#include "mbed_assert.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" + +/* Track if AES H/W is available */ +static uint16_t crypto_aes_avail = 1; +/* Track if DES H/W is available */ +static uint16_t crypto_des_avail = 1; +/* Track if SHA H/W is available */ +static uint16_t crypto_sha_avail = 1; + +/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ +static uint16_t crypto_init_counter = 0U; + +static bool crypto_submodule_acquire(uint16_t *submodule_avail); +static void crypto_submodule_release(uint16_t *submodule_avail); + +/* Track if PRNG H/W operation is done */ +static volatile uint16_t crypto_prng_done; +/* Track if AES H/W operation is done */ +static volatile uint16_t crypto_aes_done; +/* Track if DES H/W operation is done */ +static volatile uint16_t crypto_des_done; + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done); +static bool crypto_submodule_wait(volatile uint16_t *submodule_done); + +/* As crypto init counter changes from 0 to 1: + * + * 1. Enable crypto clock + * 2. Enable crypto interrupt + */ +void crypto_init(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would overflow (> USHRT_MAX)"); + } + core_util_atomic_incr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 1) { + SYS_UnlockReg(); // Unlock protected register + CLK_EnableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + + NVIC_EnableIRQ(CRPT_IRQn); + } + core_util_critical_section_exit(); +} + +/* As crypto init counter changes from 1 to 0: + * + * 1. Disable crypto interrupt + * 2. Disable crypto clock + */ +void crypto_uninit(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == 0) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would underflow (< 0)"); + } + core_util_atomic_decr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 0) { + NVIC_DisableIRQ(CRPT_IRQn); + + SYS_UnlockReg(); // Unlock protected register + CLK_DisableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + } + core_util_critical_section_exit(); +} + +/* Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = (unsigned char*) v; + while (n--) { + *p++ = 0; + } +} + +bool crypto_aes_acquire(void) +{ + return crypto_submodule_acquire(&crypto_aes_avail); +} + +void crypto_aes_release(void) +{ + crypto_submodule_release(&crypto_aes_avail); +} + +bool crypto_des_acquire(void) +{ + return crypto_submodule_acquire(&crypto_des_avail); +} + +void crypto_des_release(void) +{ + crypto_submodule_release(&crypto_des_avail); +} + +bool crypto_sha_acquire(void) +{ + return crypto_submodule_acquire(&crypto_sha_avail); +} + +void crypto_sha_release(void) +{ + crypto_submodule_release(&crypto_sha_avail); +} + +void crypto_prng_prestart(void) +{ + crypto_submodule_prestart(&crypto_prng_done); +} + +bool crypto_prng_wait(void) +{ + return crypto_submodule_wait(&crypto_prng_done); +} + +void crypto_aes_prestart(void) +{ + crypto_submodule_prestart(&crypto_aes_done); +} + +bool crypto_aes_wait(void) +{ + return crypto_submodule_wait(&crypto_aes_done); +} + +void crypto_des_prestart(void) +{ + crypto_submodule_prestart(&crypto_des_done); +} + +bool crypto_des_wait(void) +{ + return crypto_submodule_wait(&crypto_des_done); +} + +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ + ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ + (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ +} + +/* Overlap cases + * + * 1. in_buff in front of out_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + * + * 2. out_buff in front of in_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) +{ + uint32_t in = (uint32_t) in_buff; + uint32_t in_end = in + in_buff_size; + uint32_t out = (uint32_t) out_buff; + uint32_t out_end = out + out_buff_size; + + bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); + + return overlap; +} + +static bool crypto_submodule_acquire(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 1; + return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); +} + +static void crypto_submodule_release(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 0; + while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); +} + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done) +{ + *submodule_done = 0; + + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); +} + +static bool crypto_submodule_wait(volatile uint16_t *submodule_done) +{ + while (! *submodule_done); + + /* Ensure while loop above and subsequent code are not reordered */ + __DSB(); + + return true; +} + +/* Crypto interrupt handler */ +void CRYPTO_IRQHandler() +{ + if (PRNG_GET_INT_FLAG()) { + crypto_prng_done = 1; + PRNG_CLR_INT_FLAG(); + } else if (AES_GET_INT_FLAG()) { + crypto_aes_done = 1; + AES_CLR_INT_FLAG(); + } else if (TDES_GET_INT_FLAG()) { + crypto_des_done = 1; + TDES_CLR_INT_FLAG(); + } +} diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h new file mode 100644 index 00000000000..f2cc89797f4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CRYPTO_MISC_H +#define MBED_CRYPTO_MISC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init/Uninit crypto module */ +void crypto_init(void); +void crypto_uninit(void); + +/* Clear buffer to zero + * Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n); + +/* Acquire/release ownership of AES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_aes_acquire(void); +void crypto_aes_release(void); + +/* Acquire/release ownership of DES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_des_acquire(void); +void crypto_des_release(void); + +/* Acquire/release ownership of SHA H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_sha_acquire(void); +void crypto_sha_release(void); + +/* Flow control between crypto/xxx start and crypto/xxx ISR + * + * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. + * + * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. + * + * On finish, return of crypto_xxx_wait indicates success or not: + * true if successful + * false if failed + * + * Example: Start AES H/W and wait for its finish + * crypto_aes_prestart(); + * AES_Start(); + * crypto_aes_wait(); + */ +void crypto_prng_prestart(void); +bool crypto_prng_wait(void); +void crypto_aes_prestart(void); +bool crypto_aes_wait(void); +void crypto_des_prestart(void); +bool crypto_des_wait(void); + + +/* Check if buffer can be used for crypto DMA. It has the following requirements: + * (1) Word-aligned buffer base address + * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. + * (3) Located in 0x20000000-0x2FFFFFFF region + */ +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); + +/* Check if input/output buffers are overlapped */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c index 1dac0de6af2..9b7b15503ed 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c @@ -37,6 +37,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c index 7535c3a72fa..1f9935109fe 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c @@ -96,7 +96,10 @@ time_t rtc_read(void) timeinfo.tm_sec = rtc_datetime.u32Second; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -109,7 +112,7 @@ void rtc_write(time_t t) // Convert timestamp to struct tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { return; } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c index 24d15537e44..305be2bd212 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c @@ -21,6 +21,7 @@ #include "cmsis.h" #include "us_ticker_api.h" #include "trng_api.h" +#include "crypto-misc.h" /* * Get Random number generator. @@ -28,25 +29,6 @@ #define PRNG_KEY_SIZE (0x20UL) -static volatile int g_PRNG_done; -volatile int g_AES_done; - -/* Implementation that should never be optimized out by the compiler */ -static void trng_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - -void CRYPTO_IRQHandler() -{ - if (PRNG_GET_INT_FLAG()) { - g_PRNG_done = 1; - PRNG_CLR_INT_FLAG(); - } else if (AES_GET_INT_FLAG()) { - g_AES_done = 1; - AES_CLR_INT_FLAG(); - } -} - static void trng_get(unsigned char *pConversionData) { uint32_t *p32ConversionData; @@ -54,8 +36,9 @@ static void trng_get(unsigned char *pConversionData) p32ConversionData = (uint32_t *)pConversionData; PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read()); + crypto_prng_prestart(); PRNG_Start(); - while (!g_PRNG_done); + crypto_prng_wait(); PRNG_Read(p32ConversionData); } @@ -63,23 +46,21 @@ static void trng_get(unsigned char *pConversionData) void trng_init(trng_t *obj) { (void)obj; - /* Unlock protected registers */ - SYS_UnlockReg(); - /* Enable IP clock */ - CLK_EnableModuleClock(CRPT_MODULE); - - /* Lock protected registers */ - SYS_LockReg(); - - NVIC_EnableIRQ(CRPT_IRQn); + + /* Init crypto module */ + crypto_init(); + PRNG_ENABLE_INT(); } void trng_free(trng_t *obj) { (void)obj; + PRNG_DISABLE_INT(); - NVIC_DisableIRQ(CRPT_IRQn); + + /* Uninit crypto module */ + crypto_uninit(); } int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) @@ -98,11 +79,10 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l trng_get(tmpBuff); memcpy(output, tmpBuff, length); cur_length += length; - trng_zeroize(tmpBuff, sizeof(tmpBuff)); + crypto_zeroize(tmpBuff, sizeof(tmpBuff)); } *output_length = cur_length; return 0; } #endif - diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c index 8a3a05332ff..ac7a896ee22 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c @@ -34,6 +34,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c index a4a6bc0675a..720124a71ee 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c @@ -94,7 +94,10 @@ time_t rtc_read(void) timeinfo.tm_sec = rtc_datetime.u32Second; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -104,10 +107,10 @@ void rtc_write(time_t t) if (! rtc_isenabled()) { rtc_init(); } - + // Convert timestamp to struct tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { return; } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c new file mode 100644 index 00000000000..808bfd38b8b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c @@ -0,0 +1,255 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "cmsis.h" +#include "mbed_assert.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" + +/* Track if AES H/W is available */ +static uint16_t crypto_aes_avail = 1; +/* Track if DES H/W is available */ +static uint16_t crypto_des_avail = 1; +/* Track if SHA H/W is available */ +static uint16_t crypto_sha_avail = 1; + +/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ +static uint16_t crypto_init_counter = 0U; + +static bool crypto_submodule_acquire(uint16_t *submodule_avail); +static void crypto_submodule_release(uint16_t *submodule_avail); + +/* Track if PRNG H/W operation is done */ +static volatile uint16_t crypto_prng_done; +/* Track if AES H/W operation is done */ +static volatile uint16_t crypto_aes_done; +/* Track if DES H/W operation is done */ +static volatile uint16_t crypto_des_done; + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done); +static bool crypto_submodule_wait(volatile uint16_t *submodule_done); + +/* As crypto init counter changes from 0 to 1: + * + * 1. Enable crypto clock + * 2. Enable crypto interrupt + */ +void crypto_init(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would overflow (> USHRT_MAX)"); + } + core_util_atomic_incr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 1) { + SYS_UnlockReg(); // Unlock protected register + CLK_EnableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + + NVIC_EnableIRQ(CRPT_IRQn); + } + core_util_critical_section_exit(); +} + +/* As crypto init counter changes from 1 to 0: + * + * 1. Disable crypto interrupt + * 2. Disable crypto clock + */ +void crypto_uninit(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == 0) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would underflow (< 0)"); + } + core_util_atomic_decr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 0) { + NVIC_DisableIRQ(CRPT_IRQn); + + SYS_UnlockReg(); // Unlock protected register + CLK_DisableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + } + core_util_critical_section_exit(); +} + +/* Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = (unsigned char*) v; + while (n--) { + *p++ = 0; + } +} + +bool crypto_aes_acquire(void) +{ + return crypto_submodule_acquire(&crypto_aes_avail); +} + +void crypto_aes_release(void) +{ + crypto_submodule_release(&crypto_aes_avail); +} + +bool crypto_des_acquire(void) +{ + return crypto_submodule_acquire(&crypto_des_avail); +} + +void crypto_des_release(void) +{ + crypto_submodule_release(&crypto_des_avail); +} + +bool crypto_sha_acquire(void) +{ + return crypto_submodule_acquire(&crypto_sha_avail); +} + +void crypto_sha_release(void) +{ + crypto_submodule_release(&crypto_sha_avail); +} + +void crypto_prng_prestart(void) +{ + crypto_submodule_prestart(&crypto_prng_done); +} + +bool crypto_prng_wait(void) +{ + return crypto_submodule_wait(&crypto_prng_done); +} + +void crypto_aes_prestart(void) +{ + crypto_submodule_prestart(&crypto_aes_done); +} + +bool crypto_aes_wait(void) +{ + return crypto_submodule_wait(&crypto_aes_done); +} + +void crypto_des_prestart(void) +{ + crypto_submodule_prestart(&crypto_des_done); +} + +bool crypto_des_wait(void) +{ + return crypto_submodule_wait(&crypto_des_done); +} + +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ + ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ + (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ +} + +/* Overlap cases + * + * 1. in_buff in front of out_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + * + * 2. out_buff in front of in_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) +{ + uint32_t in = (uint32_t) in_buff; + uint32_t in_end = in + in_buff_size; + uint32_t out = (uint32_t) out_buff; + uint32_t out_end = out + out_buff_size; + + bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); + + return overlap; +} + +static bool crypto_submodule_acquire(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 1; + return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); +} + +static void crypto_submodule_release(uint16_t *submodule_avail) +{ + uint16_t expectedCurrentValue = 0; + while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); +} + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done) +{ + *submodule_done = 0; + + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); +} + +static bool crypto_submodule_wait(volatile uint16_t *submodule_done) +{ + while (! *submodule_done); + + /* Ensure while loop above and subsequent code are not reordered */ + __DSB(); + + return true; +} + +/* Crypto interrupt handler */ +void CRYPTO_IRQHandler() +{ + if (PRNG_GET_INT_FLAG()) { + crypto_prng_done = 1; + PRNG_CLR_INT_FLAG(); + } else if (AES_GET_INT_FLAG()) { + crypto_aes_done = 1; + AES_CLR_INT_FLAG(); + } else if (TDES_GET_INT_FLAG()) { + crypto_des_done = 1; + TDES_CLR_INT_FLAG(); + } +} diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h new file mode 100644 index 00000000000..f2cc89797f4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CRYPTO_MISC_H +#define MBED_CRYPTO_MISC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init/Uninit crypto module */ +void crypto_init(void); +void crypto_uninit(void); + +/* Clear buffer to zero + * Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n); + +/* Acquire/release ownership of AES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_aes_acquire(void); +void crypto_aes_release(void); + +/* Acquire/release ownership of DES H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_des_acquire(void); +void crypto_des_release(void); + +/* Acquire/release ownership of SHA H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_sha_acquire(void); +void crypto_sha_release(void); + +/* Flow control between crypto/xxx start and crypto/xxx ISR + * + * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. + * + * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. + * + * On finish, return of crypto_xxx_wait indicates success or not: + * true if successful + * false if failed + * + * Example: Start AES H/W and wait for its finish + * crypto_aes_prestart(); + * AES_Start(); + * crypto_aes_wait(); + */ +void crypto_prng_prestart(void); +bool crypto_prng_wait(void); +void crypto_aes_prestart(void); +bool crypto_aes_wait(void); +void crypto_des_prestart(void); +bool crypto_des_wait(void); + + +/* Check if buffer can be used for crypto DMA. It has the following requirements: + * (1) Word-aligned buffer base address + * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. + * (3) Located in 0x20000000-0x2FFFFFFF region + */ +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); + +/* Check if input/output buffers are overlapped */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c index 379f6a1d306..10d37ed576c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c @@ -1,8 +1,8 @@ /**************************************************************************//** * @file crypto.c * @version V1.10 - * $Revision: 11 $ - * $Date: 14/10/03 1:54p $ + * $Revision: 12 $ + * $Date: 15/11/06 2:17p $ * @brief Cryptographic Accelerator driver source file * * @note @@ -141,13 +141,15 @@ void AES_Start(int32_t u32Channel, uint32_t u32DMAMode) */ void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) { - int i, wcnt; - uint32_t *key_ptr; + uint32_t i, wcnt, key_reg_addr; - key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3C)); - wcnt = 4 + u32KeySize*2; - for (i = 0; i < wcnt; i++, key_ptr++) - *key_ptr = au32Keys[i]; + key_reg_addr = (uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3CUL); + wcnt = 4UL + u32KeySize*2UL; + + for (i = 0U; i < wcnt; i++) { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } } /** @@ -158,12 +160,14 @@ void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) */ void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]) { - int i; - uint32_t *key_ptr; + uint32_t i, key_reg_addr; + + key_reg_addr = (uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3CUL); - key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3C)); - for (i = 0; i < 4; i++, key_ptr++) - *key_ptr = au32IV[i]; + for (i = 0U; i < 4U; i++) { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } } /** @@ -177,15 +181,24 @@ void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]) void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt) { - *(uint32_t *)((uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3C)) = u32SrcAddr; - *(uint32_t *)((uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3C)) = u32DstAddr; - *(uint32_t *)((uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3C)) = u32TransCnt; + uint32_t reg_addr; + + reg_addr = (uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3CUL); + outpw(reg_addr, u32TransCnt); } /** * @brief Open TDES encrypt/decrypt function. * @param[in] u32Channel TDES channel. Must be 0~3. * @param[in] u32EncDec 1: TDES encode; 0: TDES decode + * @param[in] Is3DES 1: TDES; 0: DES + * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode * @param[in] u32OpMode TDES operation mode, including: * - \ref TDES_MODE_ECB * - \ref TDES_MODE_CBC @@ -203,12 +216,18 @@ void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, * - \ref TDES_IN_OUT_WHL_SWAP * @return None */ -void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType) +void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, + uint32_t u32OpMode, uint32_t u32SwapType) { g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) | (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) | - u32OpMode | - (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + if (Is3DES) { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk; + } + if (Is3Key) { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk; + } } /** @@ -229,17 +248,21 @@ void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode) /** * @brief Set TDES keys * @param[in] u32Channel TDES channel. Must be 0~3. - * @param[in] au8Keys The TDES keys. + * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word. * @return None */ -void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]) +void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]) { - int i; - uint8_t *pu8TKey; + uint32_t i, reg_addr; + + reg_addr = (uint32_t)&CRPT->TDES0_KEY1H + (0x40UL * u32Channel); - pu8TKey = (uint8_t *)((uint32_t)&CRPT->TDES0_KEY1H + (0x40 * u32Channel)); - for (i = 0; i < 3; i++, pu8TKey+=8) - memcpy(pu8TKey, &au8Keys[i][0], 8); + for (i = 0U; i < 3U; i++) { + outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */ + reg_addr += 4UL; + outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */ + reg_addr += 4UL; + } } /** @@ -251,8 +274,13 @@ void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]) */ void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) { - *(uint32_t *)((uint32_t)&CRPT->TDES0_IVH + 0x40 * u32Channel) = u32IVH; - *(uint32_t *)((uint32_t)&CRPT->TDES0_IVL + 0x40 * u32Channel) = u32IVL; + uint32_t reg_addr; + + reg_addr = (uint32_t)&CRPT->TDES0_IVH + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVH); + + reg_addr = (uint32_t)&CRPT->TDES0_IVL + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVL); } /** @@ -266,9 +294,16 @@ void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt) { - *(uint32_t *)((uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40)) = u32SrcAddr; - *(uint32_t *)((uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40)) = u32DstAddr; - *(uint32_t *)((uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40)) = u32TransCnt; + uint32_t reg_addr; + + reg_addr = (uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40UL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40UL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40UL); + outpw(reg_addr, u32TransCnt); } /** diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h index c8210e5286c..4ffc9d2cd34 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h @@ -275,9 +275,9 @@ void AES_Start(int32_t u32Channel, uint32_t u32DMAMode); void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]); void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); -void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType); +void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType); void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode); -void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]); +void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]); void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL); void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType); diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c index 39f4e8e30ba..27589ccc39e 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c @@ -37,6 +37,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c index 41ec6042d9d..4f07c84f250 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c @@ -94,7 +94,10 @@ time_t rtc_read(void) timeinfo.tm_sec = rtc_datetime.u32Second; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -104,10 +107,10 @@ void rtc_write(time_t t) if (! rtc_isenabled()) { rtc_init(); } - + // Convert timestamp to struct tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { return; } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c index a1f55b48f6a..153e1ef42c3 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c @@ -23,9 +23,9 @@ #include #include #include "cmsis.h" -#include "NUC472_442.h" #include "us_ticker_api.h" #include "trng_api.h" +#include "crypto-misc.h" /* * Get Random number generator. @@ -33,25 +33,6 @@ #define PRNG_KEY_SIZE (0x20UL) -static volatile int g_PRNG_done; -volatile int g_AES_done; - -/* Implementation that should never be optimized out by the compiler */ -static void trng_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; -} - -void CRYPTO_IRQHandler() -{ - if (PRNG_GET_INT_FLAG()) { - g_PRNG_done = 1; - PRNG_CLR_INT_FLAG(); - } else if (AES_GET_INT_FLAG()) { - g_AES_done = 1; - AES_CLR_INT_FLAG(); - } -} - static void trng_get(unsigned char *pConversionData) { uint32_t *p32ConversionData; @@ -59,8 +40,9 @@ static void trng_get(unsigned char *pConversionData) p32ConversionData = (uint32_t *)pConversionData; PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read()); + crypto_prng_prestart(); PRNG_Start(); - while (!g_PRNG_done); + crypto_prng_wait(); PRNG_Read(p32ConversionData); } @@ -68,23 +50,21 @@ static void trng_get(unsigned char *pConversionData) void trng_init(trng_t *obj) { (void)obj; - /* Unlock protected registers */ - SYS_UnlockReg(); - /* Enable IP clock */ - CLK_EnableModuleClock(CRPT_MODULE); - /* Lock protected registers */ - SYS_LockReg(); + /* Init crypto module */ + crypto_init(); - NVIC_EnableIRQ(CRPT_IRQn); PRNG_ENABLE_INT(); } void trng_free(trng_t *obj) { (void)obj; + PRNG_DISABLE_INT(); - NVIC_DisableIRQ(CRPT_IRQn); + + /* Uninit crypto module */ + crypto_uninit(); } int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) @@ -103,11 +83,10 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l trng_get(tmpBuff); memcpy(output, tmpBuff, length); cur_length += length; - trng_zeroize(tmpBuff, sizeof(tmpBuff)); + crypto_zeroize(tmpBuff, sizeof(tmpBuff)); } *output_length = cur_length; return 0; } - -#endif +#endif diff --git a/targets/TARGET_NUVOTON/nu_timer.h b/targets/TARGET_NUVOTON/nu_timer.h new file mode 100644 index 00000000000..08683370fc4 --- /dev/null +++ b/targets/TARGET_NUVOTON/nu_timer.h @@ -0,0 +1,93 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef NU_TIMER_H +#define NU_TIMER_H + +#include +#include +#include "cmsis.h" +#include "mbed_sleep.h" +#include "mbed_critical.h" +#include "ticker_api.h" +#include "us_ticker_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* A simple count-down timer used for Nuvoton ported drivers + * + * NOTE: nu_countdown_init must be paired with nu_countdown_free. + * + * Example: + * nu_countdown_ctx_s ctx; + * + * // Set up 2 ms timeout + * nu_countdown_init(&ctx, 2000); + * + * // Timed-wait for a task + * while (true) { + * // Poll the task + * + * if (nu_countdown_expired(&ctx)) { + * // Timeout + * } + * } + * + * // Must pair nu_countdown_init with nu_countdown_free in the end + * nu_countdown_free(&ctx); + */ + +struct nu_countdown_ctx_s { + const ticker_data_t * _ticker_data; // Hold ticker_data_t + us_timestamp_t _interval_end_us; // End of interval in us + bool _expired; // Expired or not +}; + +__STATIC_INLINE void nu_countdown_init(struct nu_countdown_ctx_s *ctx, us_timestamp_t interval_us) +{ + core_util_critical_section_enter(); + sleep_manager_lock_deep_sleep(); + ctx->_ticker_data = get_us_ticker_data(); + ctx->_interval_end_us = ticker_read_us(ctx->_ticker_data) + interval_us; + ctx->_expired = false; + core_util_critical_section_exit(); +} + +__STATIC_INLINE bool nu_countdown_expired(struct nu_countdown_ctx_s *ctx) +{ + core_util_critical_section_enter(); + if (! ctx->_expired) { + ctx->_expired = ticker_read_us(ctx->_ticker_data) >= ctx->_interval_end_us; + } + core_util_critical_section_exit(); + + return ctx->_expired; +} + +__STATIC_INLINE void nu_countdown_free(struct nu_countdown_ctx_s *ctx) +{ + core_util_critical_section_enter(); + sleep_manager_unlock_deep_sleep(); + core_util_critical_section_exit(); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_LPC176X/rtc_api.c b/targets/TARGET_NXP/TARGET_LPC176X/rtc_api.c index 1db7b3c9f52..f770530bacc 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/rtc_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/rtc_api.c @@ -89,7 +89,10 @@ time_t rtc_read(void) { timeinfo.tm_year = LPC_RTC->YEAR - 1900; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -97,10 +100,10 @@ time_t rtc_read(void) { void rtc_write(time_t t) { // Convert the time in to a tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { return; } - + // Pause clock, and clear counter register (clears us count) LPC_RTC->CCR |= 2; diff --git a/targets/TARGET_NXP/TARGET_LPC408X/rtc_api.c b/targets/TARGET_NXP/TARGET_LPC408X/rtc_api.c index 5785e512d0c..e0980e70ec6 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/rtc_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/rtc_api.c @@ -88,7 +88,10 @@ time_t rtc_read(void) { timeinfo.tm_year = LPC_RTC->YEAR - 1900; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -96,10 +99,10 @@ time_t rtc_read(void) { void rtc_write(time_t t) { // Convert the time in to a tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { return; } - + // Pause clock, and clear counter register (clears us count) LPC_RTC->CCR |= 2; diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c index 52f68c25a19..cc4a06d2e2e 100644 --- a/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c +++ b/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c @@ -102,7 +102,10 @@ time_t rtc_read(void) { timeinfo.tm_year = LPC_RTC->TIME[RTC_TIMETYPE_YEAR] - 1900; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -110,10 +113,10 @@ time_t rtc_read(void) { void rtc_write(time_t t) { // Convert the time in to a tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { return; } - + // Pause clock, and clear counter register (clears us count) LPC_RTC->CCR |= 2; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c index bb555ca3b71..ca4d335efa3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c @@ -120,6 +120,6 @@ const PinMap PinMap_PWM[] = { {P0_19 , PWM_3, 4}, {P0_22 , PWM_4, 4}, {P0_28 , PWM_8, 4}, - {P0_29 , PWM_9, 4}, + {P1_31 , PWM_7, 4}, {NC , NC, 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h index bc22e8e4bce..c51fe2c23cd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h @@ -183,9 +183,9 @@ typedef enum { // mbed original LED naming - LED1 = P0_13, + LED1 = P1_3, LED2 = P1_27, - LED3 = P0_14, + LED3 = P1_26, LED4 = P1_28, @@ -223,7 +223,7 @@ typedef enum { p23 = P0_19, p24 = P0_22, p25 = P0_28, - p26 = P0_29, + p26 = P1_31, p27 = P1_30, p28 = P1_29, p29 = P0_0, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct deleted file mode 100644 index 9ae88afad3d..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct +++ /dev/null @@ -1,43 +0,0 @@ - - -LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM -{ - TTB +0 EMPTY 0x4000 - { } ; Level-1 Translation Table for MMU -} - -SFLASH 0x18000000 (0x08000000) -{ - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; S-Flash ROM : Executable cached region - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - BOOT_LOADER_BEGIN 0x18000000 FIXED - { - * ( BOOT_LOADER ) - } - - VECTORS 0x18004000 FIXED - { - * (RESET, +FIRST) ; Vector table and other (assembler) startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - } - - RO_DATA +0 - { * (+RO-DATA) } ; Application RO data (.constdata) - - RW_DATA 0x20020000 - { * (+RW) } ; Application RW data (.data) - - ZI_DATA +0 ALIGN 0x400 - { * (+ZI) } ; Application ZI data (.bss) - - RW_DATA_NC 0x60900000 0x00100000 - { * (NC_DATA) } ; Application RW data Non cached area - - ZI_DATA_NC +0 - { * (NC_BSS) } ; Application ZI data Non cached area -} - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_MBRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_MBRZA1H.S deleted file mode 100644 index bf399f592a1..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_MBRZA1H.S +++ /dev/null @@ -1,454 +0,0 @@ -;/***************************************************************************** -; * @file: startup_MBRZA1H.s -; * @purpose: CMSIS Cortex-A9 Core Device Startup File -; * for the NXP MBRZA1H Device Series -; * @version: V1.02, modified for mbed -; * @date: 27. July 2009, modified 3rd Aug 2009 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - -GICI_BASE EQU 0xe8202000 -ICCIAR_OFFSET EQU 0x0000000C -ICCEOIR_OFFSET EQU 0x00000010 -ICCHPIR_OFFSET EQU 0x00000018 - -GICD_BASE EQU 0xe8201000 -ICDISER0_OFFSET EQU 0x00000100 -ICDICER0_OFFSET EQU 0x00000180 -ICDISPR0_OFFSET EQU 0x00000200 -ICDABR0_OFFSET EQU 0x00000300 -ICDIPR0_OFFSET EQU 0x00000400 - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state - -GIC_ERRATA_CHECK_1 EQU 0x000003FE -GIC_ERRATA_CHECK_2 EQU 0x000003FF - - -Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable -Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable -Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0 -Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable -Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored) - -RAM_BASE EQU 0x80000000 -VRAM_BASE EQU 0x18000000 -SRAM_BASE EQU 0x2e000000 -ETHERNET EQU 0x1a000000 -CS3_PERIPHERAL_BASE EQU 0x1c000000 - -; Stack Configuration -; Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8> -; - -UND_Stack_Size EQU 0x00000100 -SVC_Stack_Size EQU 0x00008000 -ABT_Stack_Size EQU 0x00000100 -FIQ_Stack_Size EQU 0x00000100 -IRQ_Stack_Size EQU 0x00008000 -USR_Stack_Size EQU 0x00004000 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00080000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - ARM - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, CODE, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors LDR PC, Reset_Addr ; Address of Reset Handler - LDR PC, Undef_Addr ; Address of Undef Handler - LDR PC, SVC_Addr ; Address of SVC Handler - LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler - LDR PC, DAbt_Addr ; Address of Data Abort Handler - NOP ; Reserved Vector - LDR PC, IRQ_Addr ; Address of IRQ Handler - LDR PC, FIQ_Addr ; Address of FIQ Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SVC_Addr DCD SVC_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - - AREA |.text|, CODE, READONLY - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT InitMemorySubsystem - IMPORT __main - IMPORT RZ_A1_SetSramWriteEnable - - ; Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - -; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -; Enables Full Access i.e. in both privileged and non privileged modes - MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) - ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 - MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) - ISB - -; Switch on the VFP and NEON hardware - MOV r0, #0x40000000 - VMSR FPEXC, r0 ; Write FPEXC register, EN bit set - - MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register - ISB - -; Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =__Vectors - MCR p15, 0, R0, c12, c0, 0 - -; Setup Stack for each exceptional mode - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - -; Enter System Mode to complete initialization and enter kernel - MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit - MOV SP, R0 - - ISB - - LDR R0, =RZ_A1_SetSramWriteEnable - BLX R0 - - IMPORT create_translation_table - BL create_translation_table - -; USR/SYS stack pointer will be set during kernel init - - LDR R0, =SystemInit - BLX R0 - LDR R0, =InitMemorySubsystem - BLX R0 - LDR R0, =__main - BLX R0 - - ENDP - -Undef_Handler\ - PROC - EXPORT Undef_Handler [WEAK] - IMPORT CUndefHandler - SRSFD SP!, #Mode_UND - PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack - - MRS R0, SPSR - TST R0, #T_Bit ; Check mode - MOVEQ R1, #4 ; R1 = 4 ARM mode - MOVNE R1, #2 ; R1 = 2 Thumb mode - SUB R0, LR, R1 - LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction - BEQ undef_cont - - ;Thumb instruction - ;Determine if it is a 32-bit Thumb instruction - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont ;16-bit Thumb instruction - - ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - ;R0 Offending instruction - ;R1 =2 (Thumb) or =4 (ARM) - BL CUndefHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry - SUB LR, LR, R0 - LDR R0, [SP, #28] ; Restore stacked SPSR - MSR SPSR_CXSF, R0 - POP {R0-R4, R12} ; Restore stacked APCS registers - ADD SP, SP, #8 ; Adjust SP for already-restored banked registers - MOVS PC, LR - ENDP - -PAbt_Handler\ - PROC - EXPORT PAbt_Handler [WEAK] - IMPORT CPAbtHandler - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack - PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack - MRC p15, 0, R0, c5, c0, 1 ; IFSR - MRC p15, 0, R1, c6, c0, 2 ; IFAR - - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - BL CPAbtHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - POP {R0-R4, R12} ; Restore stack APCS registers - RFEFD SP! ; Return from exception - ENDP - - -DAbt_Handler\ - PROC - EXPORT DAbt_Handler [WEAK] - IMPORT CDAbtHandler - SUB LR, LR, #8 ; Pre-adjust LR - SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack - PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack - CLREX ; State of exclusive monitors unknown after taken data abort - MRC p15, 0, R0, c5, c0, 0 ; DFSR - MRC p15, 0, R1, c6, c0, 0 ; DFAR - - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - BL CDAbtHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - POP {R0-R4, R12} ; Restore stacked APCS registers - RFEFD SP! ; Return from exception - ENDP - -FIQ_Handler\ - PROC - EXPORT FIQ_Handler [WEAK] - ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - ;; so if a real FIQ Handler is implemented, this will be needed before returning: - ;; LDR R1, =GICI_BASE - ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - B . - ENDP - -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -IRQ_Handler\ - PROC - EXPORT IRQ_Handler [WEAK] - IMPORT IRQCount - IMPORT IRQTable - IMPORT IRQNestLevel - - ;prologue - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack - CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL - PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack - -; AND R1, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R1, R3, #4 - SUB SP, SP, R1 ; Adjust stack - PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack - - LDR R0, =IRQNestLevel ; Get address of nesting counter - LDR R1, [R0] - ADD R1, R1, #1 ; Increment nesting counter - STR R1, [R0] - - ;identify and acknowledge interrupt - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register) - DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts - - ; Workaround GIC 390 errata 733075 - ; If the ID is not 0, then service the interrupt as normal. - ; If the ID is 0 and active, then service interrupt ID 0 as normal. - ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - ; - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active ; If the ID is not 0, then service the interrupt - LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state - TST R3, #1 - BNE int_active ; If active, then service the interrupt -unlock_cpu - LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface - STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write - DSB ; Ensure the write completes before continuing - B ret_irq ; Do not service the spurious interrupt - ; End workaround - -int_active - LDR R2, =IRQCount ; Read number of IRQs - LDR R2, [R2] - CMP R0, R2 ; Clean up and return if no handler - BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling - LDR R2, =IRQTable ; Get address of handler - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 ; Clean up and return if handler address is 0 - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i ; Now safe to re-enable interrupts - BLX R2 ; Call handler. R0 will be IRQ number - CPSID i ; Disable interrupts again - - ;write EOIR (GIC CPU Interface register) - POP {R0,R1} - DSB ; Ensure that interrupt source is cleared before we write the EOIR -ret_irq - ;epilogue - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel ; Get address of nesting counter - LDR R1, [R0] - SUB R1, R1, #1 ; Decrement nesting counter - STR R1, [R0] - - POP {R1, LR} ; Get stack adjustment and restore LR_SVC - ADD SP, SP, R1 ; Unadjust stack - - POP {R0-R3,R12} ; Restore stacked APCS registers - RFEFD SP! ; Return from exception - ENDP - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ENDIF - - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S deleted file mode 100644 index f6cf2082bfc..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S +++ /dev/null @@ -1,532 +0,0 @@ -/* File: startup_ARMCM3.s - * Purpose: startup file for Cortex-M3/M4 devices. Should use with - * GNU Tools for ARM Embedded Processors - * Version: V1.1 - * Date: 17 June 2011 - * - * Copyright (C) 2011 ARM Limited. All rights reserved. - * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - */ - .syntax unified - .extern _start - -@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs - .equ USR_MODE , 0x10 - .equ FIQ_MODE , 0x11 - .equ IRQ_MODE , 0x12 - .equ SVC_MODE , 0x13 - .equ ABT_MODE , 0x17 - .equ UND_MODE , 0x1b - .equ SYS_MODE , 0x1f - .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit - - .equ GICI_BASE , 0xe8202000 - .equ ICCIAR_OFFSET , 0x0000000C - .equ ICCEOIR_OFFSET , 0x00000010 - .equ ICCHPIR_OFFSET , 0x00000018 - .equ GICD_BASE , 0xe8201000 - .equ ICDISER0_OFFSET , 0x00000100 - .equ ICDICER0_OFFSET , 0x00000180 - .equ ICDISPR0_OFFSET , 0x00000200 - .equ ICDABR0_OFFSET , 0x00000300 - .equ ICDIPR0_OFFSET , 0x00000400 - - .equ Mode_USR , 0x10 - .equ Mode_FIQ , 0x11 - .equ Mode_IRQ , 0x12 - .equ Mode_SVC , 0x13 - .equ Mode_ABT , 0x17 - .equ Mode_UND , 0x1B - .equ Mode_SYS , 0x1F - - .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled - .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled - .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state - - .equ GIC_ERRATA_CHECK_1, 0x000003FE - .equ GIC_ERRATA_CHECK_2, 0x000003FF - - .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 - .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 - .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable - .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable - .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 - .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0 - .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable - .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored) - - .equ RAM_BASE , 0x80000000 - .equ VRAM_BASE , 0x18000000 - .equ SRAM_BASE , 0x2e000000 - .equ ETHERNET , 0x1a000000 - .equ CS3_PERIPHERAL_BASE, 0x1c000000 - - -@ Stack Configuration - - .EQU UND_Stack_Size , 0x00000100 - .EQU SVC_Stack_Size , 0x00008000 - .EQU ABT_Stack_Size , 0x00000100 - .EQU FIQ_Stack_Size , 0x00000100 - .EQU IRQ_Stack_Size , 0x00008000 - .EQU USR_Stack_Size , 0x00004000 - - .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) - - .section .stack - .align 3 - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space ISR_Stack_Size -__initial_sp: - .space USR_Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - -@ Heap Configuration - - .EQU Heap_Size , 0x00080000 - - .section .heap - .align 3 - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long 0xe59ff018 /* 0x00 */ - .long 0xe59ff018 /* 0x04 */ - .long 0xe59ff018 /* 0x08 */ - .long 0xe59ff018 /* 0x0c */ - .long 0xe59ff018 /* 0x10 */ - .long 0xe59ff018 /* 0x14 */ - .long 0xe59ff018 /* 0x18 */ - .long 0xe59ff018 /* 0x1c */ - - .long Reset_Handler /* 0x20 */ - .long Undef_Handler /* 0x24 */ - .long SVC_Handler /* 0x28 */ - .long PAbt_Handler /* 0x2c */ - .long DAbt_Handler /* 0x30 */ - .long 0 /* Reserved */ - .long IRQ_Handler /* IRQ */ - .long FIQ_Handler /* FIQ */ - - - .size __isr_vector, . - __isr_vector - - .text - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - @ Put any cores other than 0 to sleep - mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR - ands r0, r0, #3 - -goToSleep: - wfine - bne goToSleep - -@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR) - isb - -@ Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 @ Write FPEXC register, EN bit set - - mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register - bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache - bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache - bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU - bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction - bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs - mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register - isb - -@ Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__isr_vector - mcr p15, 0, r0, c12, c0, 0 - -@ Setup Stack for each exceptional mode -/* ldr r0, =__StackTop */ - ldr r0, =(__StackTop - USR_Stack_Size) - -@ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #UND_Stack_Size - -@ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - -@ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - -@ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit) - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - -@ Enter Supervisor Mode and set its Stack Pointer - msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit) - mov sp, r0 - -@ Enter System Mode to complete initialization and enter kernel - msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) - mov sp, r0 - - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - .extern create_translation_table - bl create_translation_table - -@ USR/SYS stack pointer will be set during kernel init - ldr r0, =SystemInit - blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -@ fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 - - -@ data sections copy - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: - -@ bss sections clear - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: - - - ldr r0, =_start - bx r0 - - ldr r0, sf_boot @ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - .word boot_loader - - .pool - .size Reset_Handler, . - Reset_Handler - - - .text - -Undef_Handler: - .global Undef_Handler - .func Undef_Handler - .extern CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - .endfunc - -PAbt_Handler: - .global PAbt_Handler - .func PAbt_Handler - .extern CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -DAbt_Handler: - .global DAbt_Handler - .func DAbt_Handler - .extern CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -FIQ_Handler: - .global FIQ_Handler - .func FIQ_Handler - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ - B . - .endfunc - - .extern SVC_Handler /* refer RTX function */ - -IRQ_Handler: - .global IRQ_Handler - .func IRQ_Handler - .extern IRQCount - .extern IRQTable - .extern IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler SVC_Handler - - -/* User Initial Stack & Heap */ - - .ifdef __MICROLIB - - .global __initial_sp - .global __heap_base - .global __heap_limit - - .else - - .extern __use_two_region_memory - .global __user_initial_stackheap -__user_initial_stackheap: - - LDR R0, = __HeapBase - LDR R1, =(__StackTop) - LDR R2, = (__HeapBase + Heap_Size) - LDR R3, = (__StackTop - USR_Stack_Size) - BX LR - - .endif - - - .END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S deleted file mode 100644 index fb769e57202..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S +++ /dev/null @@ -1,505 +0,0 @@ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Part one of the system initialization code, -;; contains low-level -;; initialization. -;; -;; Copyright 2007 IAR Systems. All rights reserved. -;; -;; $Revision: 49919 $ -;; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - -; -; The module in this file are included in the libraries, and may be -; replaced by any user-defined modules that define the PUBLIC symbol -; __iar_program_start or a user defined start symbol. -; -; To override the cstartup defined in the library, simply add your -; modified version to the workbench project. - - SECTION .intvec:CODE:NOROOT(2) - - PUBLIC __vector_core_a9 - PUBLIC __RST_Handler - PUBLIC Undefined_Handler - EXTERN SWI_Handler - PUBLIC Prefetch_Handler - PUBLIC Abort_Handler - PUBLIC IRQ_Handler - PUBLIC FIQ_Handler - EXTERN VbarInit - EXTERN SetLowVectors - EXTERN init_TTB - EXTERN enable_mmu - EXTERN Peripheral_BasicInit - EXTERN initsct - EXTERN PowerON_Reset - PUBLIC FPUEnable - - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_core_a9: ; Make this a DATA label, so that stack usage - ; analysis doesn't consider it an uncalled fun - - ARM - - ; All default exception handlers (except reset) are - ; defined as weak symbol definitions. - ; If a handler is defined by the application it will take precedence. - LDR PC,Reset_Addr ; Reset - LDR PC,Undefined_Addr ; Undefined instructions - LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) - LDR PC,Prefetch_Addr ; Prefetch abort - LDR PC,Abort_Addr ; Data abort - DCD 0 ; RESERVED - LDR PC,IRQ_Addr ; IRQ - LDR PC,FIQ_Addr ; FIQ - - DATA - -Reset_Addr: DCD __RST_Handler -Undefined_Addr: DCD Undefined_Handler -SWI_Addr: DCD SWI_Handler -Prefetch_Addr: DCD Prefetch_Handler -Abort_Addr: DCD Abort_Handler -IRQ_Addr: DCD IRQ_Handler -FIQ_Addr: DCD FIQ_Handler - - -; -------------------------------------------------- -; ?cstartup -- low-level system initialization code. -; -; After a reset execution starts here, the mode is ARM, supervisor -; with interrupts disabled. -; - - - - SECTION .text:CODE:NOROOT(2) - EXTERN RZ_A1_SetSramWriteEnable - EXTERN create_translation_table - EXTERN SystemInit - EXTERN InitMemorySubsystem - EXTERN __iar_program_start - REQUIRE __vector_core_a9 - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - - - ARM - -__RST_Handler: -?cstartup: - - -;;; @ Put any cores other than 0 to sleep - mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR - ands r0, r0, #3 - -goToSleep: - wfine - bne goToSleep - - -//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -//@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) - isb - - -;; Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set - - mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register - bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache - bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache - bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU - bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction - bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs - mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register - isb - - -;; Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__vector_core_a9 - mcr p15, 0, r0, c12, c0, 0 - - -; -; Add initialization needed before setup of stackpointers here. -; - -; -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. -; - - -; -------------------- -; Mode, correspords to bits 0-5 in CPSR - -#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR - -#define USR_MODE 0x10 ; User mode -#define FIQ_MODE 0x11 ; Fast Interrupt Request mode -#define IRQ_MODE 0x12 ; Interrupt Request mode -#define SVC_MODE 0x13 ; Supervisor mode -#define ABT_MODE 0x17 ; Abort mode -#define UND_MODE 0x1B ; Undefined Instruction mode -#define SYS_MODE 0x1F ; System mode - -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define GICI_BASE 0xe8202000 -#define ICCIAR_OFFSET 0x0000000C -#define ICCEOIR_OFFSET 0x00000010 -#define ICCHPIR_OFFSET 0x00000018 -#define GICD_BASE 0xe8201000 -#define GIC_ERRATA_CHECK_1 0x000003FE -#define GIC_ERRATA_CHECK_2 0x000003FF -#define ICDABR0_OFFSET 0x00000300 -#define ICDIPR0_OFFSET 0x00000400 -#define T_Bit 0x20 ; when T bit is set, core is in Thumb state - - MRS r0, cpsr ; Original PSR value - - ;; Set up the SVC stack pointer. - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #SVC_MODE ; Set SVC mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the fast interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #FIQ_MODE ; Set FIR mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the ABT stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #ABT_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(ABT_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the UDF stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #UND_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(UND_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the normal stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #SYS_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(CSTACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - -;;; - - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - bl create_translation_table - -; USR/SYS stack pointer will be set during kernel init - ldr r0, =SystemInit - blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -; fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 - - - -;;; Continue to __cmain for C-level initialization. - - FUNCALL __RST_Handler, __iar_program_start - B __iar_program_start - - - ldr r0, sf_boot ;@ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - DC32 0x00000001 - -Undefined_Handler: - EXTERN CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - -Prefetch_Handler: - EXTERN CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - -Abort_Handler: - EXTERN CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - -FIQ_Handler: - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ - B . - - EXTERN SVC_Handler /* refer RTX function */ - -IRQ_Handler: - EXTERN IRQCount - EXTERN IRQTable - EXTERN IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ -;;; -;;; Add more initialization here -;;; -FPUEnable: - ARM - - //Permit access to VFP registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Enable VFP - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP registers to 0 - MOV R2,#0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.c deleted file mode 100644 index e33b11122df..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.c +++ /dev/null @@ -1,305 +0,0 @@ -/**************************************************************************//** - * @file gic.c - * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 19 Sept 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#include "MBRZA1H.h" - -#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ -#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ - -/* Globals for use of post-scatterloading code that must access GIC */ -const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE; -const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE; - -void GIC_EnableDistributor(void) -{ - GICDistributor->ICDDCR |= 1; //enable distributor -} - -void GIC_DisableDistributor(void) -{ - GICDistributor->ICDDCR &=~1; //disable distributor -} - -uint32_t GIC_DistributorInfo(void) -{ - return (uint32_t)(GICDistributor->ICDICTR); -} - -uint32_t GIC_DistributorImplementer(void) -{ - return (uint32_t)(GICDistributor->ICDIIDR); -} - -void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - *field = (uint8_t)cpu_target & 0xf; -} - -void GIC_SetICDICFR (const uint32_t *ICDICFRn) -{ - uint32_t i, num_irq; - - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - for (i = 0; i < (num_irq/16); i++) - { - GICDistributor->ICDISPR[i] = *ICDICFRn++; - } -} - -uint32_t GIC_GetTarget(IRQn_Type IRQn) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - return ((uint32_t)*field & 0xf); -} - -void GIC_EnableInterface(void) -{ - GICInterface->ICCICR |= 1; //enable interface -} - -void GIC_DisableInterface(void) -{ - GICInterface->ICCICR &=~1; //disable distributor -} - -IRQn_Type GIC_AcknowledgePending(void) -{ - return (IRQn_Type)(GICInterface->ICCIAR); -} - -void GIC_EndInterrupt(IRQn_Type IRQn) -{ - GICInterface->ICCEOIR = IRQn; -} - -void GIC_EnableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_DisableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_SetPendingIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]); - int bit_shift = (IRQn % 16)<<1; - uint8_t save_byte; - - field += (bit_shift / 8); - bit_shift %= 8; - - save_byte = *field; - save_byte &= ((uint8_t)~(3u << bit_shift)); - - *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift); -} - -void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += (IRQn % 4); - *field = (uint8_t)priority; -} - -uint32_t GIC_GetPriority(IRQn_Type IRQn) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += (IRQn % 4); - return (uint32_t)*field; -} - -void GIC_InterfacePriorityMask(uint32_t priority) -{ - GICInterface->ICCPMR = priority & 0xff; //set priority mask -} - -void GIC_SetBinaryPoint(uint32_t binary_point) -{ - GICInterface->ICCBPR = binary_point & 0x07; //set binary point -} - -uint32_t GIC_GetBinaryPoint(uint32_t binary_point) -{ - return (uint32_t)GICInterface->ICCBPR; -} - -uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) -{ - uint32_t pending, active; - - active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - - return ((active<<1) | pending); -} - -void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) -{ - GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); -} - -void GIC_DistInit(void) -{ - //IRQn_Type i; - uint32_t i; - uint32_t num_irq = 0; - uint32_t priority_field; - - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableDistributor(); - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); - - for (i = 32; i < num_irq; i++) - { - //Disable all SPI the interrupts - GIC_DisableIRQ((IRQn_Type)i); - //Set level-sensitive and N-N model - //GIC_SetLevelModel(i, 0, 0); - //Set priority - GIC_SetPriority((IRQn_Type)i, priority_field/2); - //Set target list to "all cpus" - GIC_SetTarget((IRQn_Type)i, 0xff); - } - /* Set level-edge and 1-N model */ - /* GICDistributor->ICDICFR[ 0] is read only */ - GICDistributor->ICDICFR[ 1] = 0x00000055; - GICDistributor->ICDICFR[ 2] = 0xFFFD5555; - GICDistributor->ICDICFR[ 3] = 0x555FFFFF; - GICDistributor->ICDICFR[ 4] = 0x55555555; - GICDistributor->ICDICFR[ 5] = 0x55555555; - GICDistributor->ICDICFR[ 6] = 0x55555555; - GICDistributor->ICDICFR[ 7] = 0x55555555; - GICDistributor->ICDICFR[ 8] = 0x5555F555; - GICDistributor->ICDICFR[ 9] = 0x55555555; - GICDistributor->ICDICFR[10] = 0x55555555; - GICDistributor->ICDICFR[11] = 0xF5555555; - GICDistributor->ICDICFR[12] = 0xF555F555; - GICDistributor->ICDICFR[13] = 0x5555F555; - GICDistributor->ICDICFR[14] = 0x55555555; - GICDistributor->ICDICFR[15] = 0x55555555; - GICDistributor->ICDICFR[16] = 0x55555555; - GICDistributor->ICDICFR[17] = 0xFD555555; - GICDistributor->ICDICFR[18] = 0x55555557; - GICDistributor->ICDICFR[19] = 0x55555555; - GICDistributor->ICDICFR[20] = 0xFFD55555; - GICDistributor->ICDICFR[21] = 0x5F55557F; - GICDistributor->ICDICFR[22] = 0xFD55555F; - GICDistributor->ICDICFR[23] = 0x55555557; - GICDistributor->ICDICFR[24] = 0x55555555; - GICDistributor->ICDICFR[25] = 0x55555555; - GICDistributor->ICDICFR[26] = 0x55555555; - GICDistributor->ICDICFR[27] = 0x55555555; - GICDistributor->ICDICFR[28] = 0x55555555; - GICDistributor->ICDICFR[29] = 0x55555555; - GICDistributor->ICDICFR[30] = 0x55555555; - GICDistributor->ICDICFR[31] = 0x55555555; - GICDistributor->ICDICFR[32] = 0x55555555; - GICDistributor->ICDICFR[33] = 0x55555555; - - //Enable distributor - GIC_EnableDistributor(); -} - -void GIC_CPUInterfaceInit(void) -{ - IRQn_Type i; - uint32_t priority_field; - - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableInterface(); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); - - //SGI and PPI - for (i = (IRQn_Type)0; i < 32; i++) - { - //Set level-sensitive and N-N model for PPI - //if(i > 15) - //GIC_SetLevelModel(i, 0, 0); - //Disable SGI and PPI interrupts - GIC_DisableIRQ(i); - //Set priority - GIC_SetPriority(i, priority_field/2); - } - //Enable interface - GIC_EnableInterface(); - //Set binary point to 0 - GIC_SetBinaryPoint(0); - //Set priority mask - GIC_InterfacePriorityMask(0xff); -} - -void GIC_Enable(void) -{ - GIC_DistInit(); - GIC_CPUInterfaceInit(); //per CPU -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_Renesas_RZ_A1.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_Renesas_RZ_A1.c deleted file mode 100644 index edd04b3e482..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_Renesas_RZ_A1.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************//** - * @file mmu_Renesas_RZ_A1.c - * @brief MMU Startup File for - * mmu_Renesas_RZ_A1 Device Series - * @version V1.01 - * @date 2 Aug 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings. -//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors place all memory in domain 0 -//There are no restrictions by privilege level (PL0 can access all memory) - -#include -#include "MBRZA1H.h" - -//Import symbols from linker -extern uint32_t Image$$VECTORS$$Base; -extern uint32_t Image$$RO_DATA$$Base; -extern uint32_t Image$$RW_DATA$$Base; -extern uint32_t Image$$ZI_DATA$$Base; -#if !defined ( __ICCARM__ ) -extern uint32_t Image$$TTB$$ZI$$Base; -#endif - -#if defined( __CC_ARM ) -#elif defined( __ICCARM__ ) -#else -extern uint32_t Image$$RW_DATA_NC$$Base; -extern uint32_t Image$$ZI_DATA_NC$$Base; -#endif - -extern uint32_t Image$$VECTORS$$Limit; -extern uint32_t Image$$RO_DATA$$Limit; -extern uint32_t Image$$RW_DATA$$Limit; -extern uint32_t Image$$ZI_DATA$$Limit; -#if defined( __CC_ARM ) -#else -extern uint32_t Image$$RW_DATA_NC$$Limit; -extern uint32_t Image$$ZI_DATA_NC$$Limit; -#endif - -#if defined( __ICCARM__ ) -#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) -#define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1) -#else -#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) -#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1) -#endif - -#if defined( __CC_ARM ) -#else -#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) -#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) -#endif - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -#if defined ( __ICCARM__ ) -__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; -uint32_t Image$$VECTORS$$Base; -uint32_t Image$$RO_DATA$$Base; -uint32_t Image$$RW_DATA$$Base; -uint32_t Image$$ZI_DATA$$Base; - -uint32_t Image$$VECTORS$$Limit; -uint32_t Image$$RO_DATA$$Limit; -uint32_t Image$$RW_DATA$$Limit; -uint32_t Image$$ZI_DATA$$Limit; -#endif - -void create_translation_table(void) -{ - mmu_region_attributes_Type region; -#if defined ( __ICCARM__ ) -#pragma section=".intvec" -#pragma section=".rodata" -#pragma section=".rwdata" -#pragma section=".bss" - - Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); - Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); - Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); - Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); - Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); - Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); - Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss"); - Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); -#endif - /* - * Generate descriptors. Refer to MBRZA1H.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - section_normal_nc(Sect_Normal_NC, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Create 4GB of faulting entries - __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); - - // R7S72100 memory map. - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); - -#if defined( __ICCARM__ ) - //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); -#else - //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); -#endif - -#if defined( __CC_ARM ) - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); -#elif defined ( __ICCARM__ ) - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); - -#else - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); -#endif - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x0 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x1 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x1 (Inner WB WA) */ - __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); -} - - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.c deleted file mode 100644 index 723ec247c82..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file pl310.c - * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions - * @version - * @date 3 December 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ -#include "MBRZA1H.h" - -//Cache Sync operation -void PL310_Sync(void) -{ - PL310->CACHE_SYNC = 0x0; -} - -//return Cache controller cache ID -int PL310_GetID (void) -{ - return PL310->CACHE_ID; -} - -//return Cache controller cache Type -int PL310_GetType (void) -{ - return PL310->CACHE_TYPE; -} - -//Invalidate all cache by way -void PL310_InvAllByWay (void) -{ - unsigned int assoc; - - if (PL310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - PL310->INV_WAY = (1 << assoc) - 1; - while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate - - PL310_Sync(); -} - -//Clean and Invalidate all cache by way -void PL310_CleanInvAllByWay (void) -{ - unsigned int assoc; - - if (PL310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - PL310->CLEAN_INV_WAY = (1 << assoc) - 1; - while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate - - PL310_Sync(); -} - -//Enable Cache -void PL310_Enable(void) -{ - PL310->CONTROL = 0; - PL310->INTERRUPT_CLEAR = 0x000001FFuL; - PL310->DEBUG_CONTROL = 0; - PL310->DATA_LOCK_0_WAY = 0; - PL310->CACHE_SYNC = 0; - - PL310->CONTROL = 0x01; - PL310_Sync(); -} -//Disable Cache -void PL310_Disable(void) -{ - PL310->CONTROL = 0x00; - PL310_Sync(); -} - -//Invalidate cache by physical address -void PL310_InvPa (void *pa) -{ - PL310->INV_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - -//Clean cache by physical address -void PL310_CleanPa (void *pa) -{ - PL310->CLEAN_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - -//Clean and invalidate cache by physical address -void PL310_CleanInvPa (void *pa) -{ - PL310->CLEAN_INV_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c deleted file mode 100644 index d8db0843e1a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c +++ /dev/null @@ -1,521 +0,0 @@ -/**************************************************************************//** - * @file system_MBRZA1H.c - * @brief CMSIS Device System Source File for - * ARM Cortex-A9 Device Series - * @version V1.00 - * @date 09 January 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#include -#include "MBRZA1H.h" -#include "RZ_A1_Init.h" - - -#if defined(__ARMCC_VERSION) -extern void $Super$$main(void); -__asm void FPUEnable(void); -#else -void FPUEnable(void); - -#endif - -#define FRQCR_IFC_MSK (0x0030) -#define FRQCR_IFC_SHFT (8) -#define FRQCR_IFC_1P1 (0) /* x1/1 */ -#define FRQCR_IFC_2P3 (1) /* x2/3 */ -#define FRQCR_IFC_1P3 (3) /* x1/3 */ - -uint32_t IRQNestLevel; -unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 -uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the cache. - * - * @param none - * @return none - * - * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. - */ -#if defined(__ARMCC_VERSION) -#pragma push -#pragma arm - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#pragma pop - -#elif defined(__GNUC__) - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#elif defined ( __ICCARM__ ) - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#else - -#endif - - -IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; - -uint32_t IRQCount = sizeof IRQTable / 4; - -uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) -{ - if (irq < IRQCount) { - IRQTable[irq] = handler; - return 0; - } - else { - return 1; - } -} - -uint32_t InterruptHandlerUnregister (IRQn_Type irq) -{ - if (irq < IRQCount) { - IRQTable[irq] = 0; - return 0; - } - else { - return 1; - } -} - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock. - */ -void SystemCoreClockUpdate (void) -{ - uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; - - switch (frqcr_ifc) { - case FRQCR_IFC_1P1: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; - break; - case FRQCR_IFC_2P3: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; - break; - case FRQCR_IFC_1P3: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; - break; - default: - /* do nothing */ - break; - } -} - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - IRQNestLevel = 0; -/* do not use global variables because this function is called before - reaching pre-main. RW section maybe overwritten afterwards. */ - RZ_A1_InitClock(); - RZ_A1_InitBus(); - - //Configure GIC ICDICFR GIC_SetICDICFR() - GIC_Enable(); - __enable_irq(); - -} - - -//Fault Status Register (IFSR/DFSR) definitions -#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup -#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external -#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external -#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external -#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external -#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external -#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal -#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal -#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal -#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal -#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal -#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal -#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal -#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal -#define FSR_DEBUG_EVENT 0x02 //internal -#define FSR_SYNC_EXT_ABORT 0x08 //sync/external -#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external -#define FSR_LOCKDOWN 0x14 //internal -#define FSR_COPROCESSOR_ABORT 0x1a //internal -#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external -#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external -#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external - -void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { - uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status - - switch(FS) { - //Synchronous parity errors - retry - case FSR_SYNC_PARITY_ERROR: - case FSR_SYNC_PARITY_TTB_WALK_FIRST: - case FSR_SYNC_PARITY_TTB_WALK_SECOND: - return; - - //Your code here. Value in DFAR is invalid for some fault statuses. - case FSR_ALIGNMENT_FAULT: - case FSR_INSTRUCTION_CACHE_MAINTENANCE: - case FSR_SYNC_EXT_TTB_WALK_FIRST: - case FSR_SYNC_EXT_TTB_WALK_SECOND: - case FSR_TRANSLATION_FAULT_FIRST: - case FSR_TRANSLATION_FAULT_SECOND: - case FSR_ACCESS_FLAG_FAULT_FIRST: - case FSR_ACCESS_FLAG_FAULT_SECOND: - case FSR_DOMAIN_FAULT_FIRST: - case FSR_DOMAIN_FAULT_SECOND: - case FSR_PERMISION_FAULT_FIRST: - case FSR_PERMISION_FAULT_SECOND: - case FSR_DEBUG_EVENT: - case FSR_SYNC_EXT_ABORT: - case FSR_TLB_CONFLICT_ABORT: - case FSR_LOCKDOWN: - case FSR_COPROCESSOR_ABORT: - case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid - case FSR_ASYNC_PARITY_ERROR: //DFAR invalid - default: - while(1); - } -} - -void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { - uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status - - switch(FS) { - //Synchronous parity errors - retry - case FSR_SYNC_PARITY_ERROR: - case FSR_SYNC_PARITY_TTB_WALK_FIRST: - case FSR_SYNC_PARITY_TTB_WALK_SECOND: - return; - - //Your code here. Value in IFAR is invalid for some fault statuses. - case FSR_SYNC_EXT_TTB_WALK_FIRST: - case FSR_SYNC_EXT_TTB_WALK_SECOND: - case FSR_TRANSLATION_FAULT_FIRST: - case FSR_TRANSLATION_FAULT_SECOND: - case FSR_ACCESS_FLAG_FAULT_FIRST: - case FSR_ACCESS_FLAG_FAULT_SECOND: - case FSR_DOMAIN_FAULT_FIRST: - case FSR_DOMAIN_FAULT_SECOND: - case FSR_PERMISION_FAULT_FIRST: - case FSR_PERMISION_FAULT_SECOND: - case FSR_DEBUG_EVENT: //IFAR invalid - case FSR_SYNC_EXT_ABORT: - case FSR_TLB_CONFLICT_ABORT: - case FSR_LOCKDOWN: - case FSR_COPROCESSOR_ABORT: - default: - while(1); - } -} - -//returns amount to decrement lr by -//this will be 0 when we have emulated the instruction and want to execute the next instruction -//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) -//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) -uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { - const unsigned int THUMB = 2; - const unsigned int ARM = 4; - //Lazy VFP/NEON initialisation and switching - - // (ARM ARM section A7.5) VFP data processing instruction? - // (ARM ARM section A7.6) VFP/NEON register load/store instruction? - // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? - // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? - if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || - (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { - if (((opcode & 0x00000E00) >> 9) == 5) { - FPUEnable(); - return state; - } - } - - // (ARM ARM section A7.4) NEON data processing instruction? - if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || - (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || - // (ARM ARM section A7.7) NEON load/store instruction? - (state == ARM && ((opcode >> 24) == 0xF4)) || - (state == THUMB && ((opcode >> 24) == 0xF9))) { - FPUEnable(); - return state; - } - - //Add code here for other Undef cases - while(1); -} - -#if defined(__ARMCC_VERSION) -#pragma push -#pragma arm -//Critical section, called from undef handler, so systick is disabled -__asm void FPUEnable(void) { - ARM - - //Permit access to VFP/NEON, registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - ISB - - //Enable VFP/NEON - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP/NEON registers to 0 - MOV R2,#0 - //Initialise D16 registers to 0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - //Initialise D32 registers to 0 - VMOV D16,R2,R2 - VMOV D17,R2,R2 - VMOV D18,R2,R2 - VMOV D19,R2,R2 - VMOV D20,R2,R2 - VMOV D21,R2,R2 - VMOV D22,R2,R2 - VMOV D23,R2,R2 - VMOV D24,R2,R2 - VMOV D25,R2,R2 - VMOV D26,R2,R2 - VMOV D27,R2,R2 - VMOV D28,R2,R2 - VMOV D29,R2,R2 - VMOV D30,R2,R2 - VMOV D31,R2,R2 - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR -} -#pragma pop - -#elif defined(__GNUC__) -void FPUEnable(void) { - __asm__ ( - ".ARM;" - - //Permit access to VFP/NEON, registers by modifying CPACR - "MRC p15,0,R1,c1,c0,2;" - "ORR R1,R1,#0x00F00000;" - "MCR p15,0,R1,c1,c0,2;" - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - "ISB;" - - //Enable VFP/NEON - "VMRS R1,FPEXC;" - "ORR R1,R1,#0x40000000;" - "VMSR FPEXC,R1;" - - //Initialise VFP/NEON registers to 0 - "MOV R2,#0;" - //Initialise D16 registers to 0 - "VMOV D0, R2,R2;" - "VMOV D1, R2,R2;" - "VMOV D2, R2,R2;" - "VMOV D3, R2,R2;" - "VMOV D4, R2,R2;" - "VMOV D5, R2,R2;" - "VMOV D6, R2,R2;" - "VMOV D7, R2,R2;" - "VMOV D8, R2,R2;" - "VMOV D9, R2,R2;" - "VMOV D10,R2,R2;" - "VMOV D11,R2,R2;" - "VMOV D12,R2,R2;" - "VMOV D13,R2,R2;" - "VMOV D14,R2,R2;" - "VMOV D15,R2,R2;" - //Initialise D32 registers to 0 - "VMOV D16,R2,R2;" - "VMOV D17,R2,R2;" - "VMOV D18,R2,R2;" - "VMOV D19,R2,R2;" - "VMOV D20,R2,R2;" - "VMOV D21,R2,R2;" - "VMOV D22,R2,R2;" - "VMOV D23,R2,R2;" - "VMOV D24,R2,R2;" - "VMOV D25,R2,R2;" - "VMOV D26,R2,R2;" - "VMOV D27,R2,R2;" - "VMOV D28,R2,R2;" - "VMOV D29,R2,R2;" - "VMOV D30,R2,R2;" - "VMOV D31,R2,R2;" - - //Initialise FPSCR to a known state - "VMRS R2,FPSCR;" - "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - "AND R2,R2,R3;" - "VMSR FPSCR,R2;" - - //"BX LR;" - : - : - :"r1", "r2", "r3"); - return; -} -#else -#endif - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.h deleted file mode 100644 index bd7ba038091..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************//** - * @file system_MBRZA1H.h - * @brief CMSIS Device System Header File for - * ARMCA9 Device Series - * @version V1.00 - * @date 11 June 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __SYSTEM_MBRZA1H -#define __SYSTEM_MBRZA1H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -typedef void(*IRQHandler)(); -uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); -uint32_t InterruptHandlerUnregister(IRQn_Type); - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the Systd short int16_t;emCoreClock variable. - */ -extern void SystemInit (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_MBRZA1H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c deleted file mode 100644 index 19f7876829f..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" -#include "gpio_addrdefine.h" - - -uint32_t gpio_set(PinName pin) { - pin_function(pin, 0); - return (1 << PINNO(pin)); -} - -void gpio_init(gpio_t *obj, PinName pin) { - int group ; - obj->pin = pin; - if(pin == NC) return; - - obj->mask = gpio_set(pin); - - group = PINGROUP(pin); - if (group > 11) return; - - obj->reg_set = (volatile uint32_t *) PSR(group); - obj->reg_in = (volatile uint32_t *) PPR(group); - obj->reg_dir = (volatile uint32_t *)PMSR(group); - obj->reg_buf = (volatile uint32_t *)PIBC(group); -} - -void gpio_mode(gpio_t *obj, PinMode mode) { -/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */ -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - switch (direction) { - case PIN_INPUT : - *obj->reg_dir = (obj->mask << 16) | obj->mask; - *obj->reg_buf |= obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir = (obj->mask << 16) | 0; - *obj->reg_buf &= ~obj->mask; - break; - } -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A1H/objects.h deleted file mode 100644 index 3ce9e0d3c74..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/objects.h +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "gpio_object.h" -#include "rspi_iodefine.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct i2c_s { - uint32_t i2c; - uint32_t dummy; - uint8_t pclk_bit; - uint8_t width_low; - uint8_t width_hi; - int bbsy_wait_cnt; - int last_stop_flag; -}; - -struct spi_s { - struct st_rspi *spi; - uint32_t bits; - int index; -}; - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; - uint8_t int_enable; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct serial_s { - struct st_scif *uart; - int index; -}; - -struct pwmout_s { - uint32_t ch; - PWMName pwm; -}; - -struct analogin_s { - ADCName adc; -}; - -struct can_s { - uint32_t ch; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c deleted file mode 100644 index a96727e9b27..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c +++ /dev/null @@ -1,172 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_addrdefine.h" - -PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ - -typedef struct { - PinName pin; - int function; - int pm; -} PinFunc; - -static const PinFunc PIPC_0_tbl[] = { -// pin func pm - {P4_0 , 2 , -1}, /* TIOC0A */ - {P5_0 , 6 , -1}, /* TIOC0A */ - {P7_0 , 7 , -1}, /* TIOC0A */ - {P10_4 , 2 , -1}, /* TIOC0A */ - {P4_1 , 2 , -1}, /* TIOC0B */ - {P5_1 , 6 , -1}, /* TIOC0B */ - {P7_1 , 7 , -1}, /* TIOC0B */ - {P10_5 , 2 , -1}, /* TIOC0B */ - {P4_2 , 2 , -1}, /* TIOC0C */ - {P5_5 , 6 , -1}, /* TIOC0C */ - {P7_2 , 7 , -1}, /* TIOC0C */ - {P10_6 , 2 , -1}, /* TIOC0C */ - {P4_3 , 2 , -1}, /* TIOC0D */ - {P5_7 , 6 , -1}, /* TIOC0D */ - {P7_3 , 7 , -1}, /* TIOC0D */ - {P10_7 , 2 , -1}, /* TIOC0D */ - {P2_11 , 5 , -1}, /* TIOC1A */ - {P6_0 , 5 , -1}, /* TIOC1A */ - {P7_4 , 7 , -1}, /* TIOC1A */ - {P8_8 , 5 , -1}, /* TIOC1A */ - {P9_7 , 4 , -1}, /* TIOC1A */ - {P10_8 , 2 , -1}, /* TIOC1A */ - {P2_12 , 8 , -1}, /* TIOC1B */ - {P5_2 , 6 , -1}, /* TIOC1B */ - {P6_1 , 5 , -1}, /* TIOC1B */ - {P7_5 , 7 , -1}, /* TIOC1B */ - {P8_9 , 5 , -1}, /* TIOC1B */ - {P10_9 , 2 , -1}, /* TIOC1B */ - {P2_1 , 6 , -1}, /* TIOC2A */ - {P6_2 , 6 , -1}, /* TIOC2A */ - {P7_6 , 7 , -1}, /* TIOC2A */ - {P8_14 , 4 , -1}, /* TIOC2A */ - {P10_10 , 2 , -1}, /* TIOC2A */ - {P2_2 , 6 , -1}, /* TIOC2B */ - {P6_3 , 6 , -1}, /* TIOC2B */ - {P7_7 , 7 , -1}, /* TIOC2B */ - {P8_15 , 4 , -1}, /* TIOC2B */ - {P10_11 , 2 , -1}, /* TIOC2B */ - {P10_11 , 2 , -1}, /* TIOC2B */ - {P3_4 , 6 , -1}, /* TIOC3A */ - {P7_8 , 7 , -1}, /* TIOC3A */ - {P8_10 , 4 , -1}, /* TIOC3A */ - {P3_5 , 6 , -1}, /* TIOC3B */ - {P7_9 , 7 , -1}, /* TIOC3B */ - {P8_11 , 4 , -1}, /* TIOC3B */ - {P3_6 , 6 , -1}, /* TIOC3C */ - {P5_3 , 6 , -1}, /* TIOC3C */ - {P7_10 , 7 , -1}, /* TIOC3C */ - {P8_12 , 4 , -1}, /* TIOC3C */ - {P3_7 , 6 , -1}, /* TIOC3D */ - {P5_4 , 6 , -1}, /* TIOC3D */ - {P7_11 , 7 , -1}, /* TIOC3D */ - {P8_13 , 4 , -1}, /* TIOC3D */ - {P3_8 , 6 , -1}, /* TIOC4A */ - {P4_4 , 3 , -1}, /* TIOC4A */ - {P7_12 , 7 , -1}, /* TIOC4A */ - {P11_0 , 2 , -1}, /* TIOC4A */ - {P3_9 , 6 , -1}, /* TIOC4B */ - {P4_5 , 3 , -1}, /* TIOC4B */ - {P7_13 , 7 , -1}, /* TIOC4B */ - {P11_1 , 2 , -1}, /* TIOC4B */ - {P3_10 , 6 , -1}, /* TIOC4C */ - {P4_6 , 3 , -1}, /* TIOC4C */ - {P7_14 , 7 , -1}, /* TIOC4C */ - {P11_2 , 2 , -1}, /* TIOC4C */ - {P3_11 , 6 , -1}, /* TIOC4D */ - {P4_7 , 3 , -1}, /* TIOC4D */ - {P7_15 , 7 , -1}, /* TIOC4D */ - {P11_3 , 2 , -1}, /* TIOC4D */ - {P5_7 , 1 , 1 }, /* TXOUT0M */ - {P5_6 , 1 , 1 }, /* TXOUT0P */ - {P5_5 , 1 , 1 }, /* TXOUT1M */ - {P5_4 , 1 , 1 }, /* TXOUT1P */ - {P5_3 , 1 , 1 }, /* TXOUT2M */ - {P5_2 , 1 , 1 }, /* TXOUT2P */ - {P5_1 , 1 , 1 }, /* TXCLKOUTM */ - {P5_0 , 1 , 1 }, /* TXCLKOUTP */ - {P2_11 , 4 , 0 }, /* SSITxD0 */ - {P4_7 , 5 , 0 }, /* SSITxD0 */ - {P7_4 , 6 , 0 }, /* SSITxD1 */ - {P10_15 , 2 , 0 }, /* SSITxD1 */ - {P4_15 , 6 , 0 }, /* SSITxD3 */ - {P7_11 , 2 , 0 }, /* SSITxD3 */ - {P2_7 , 4 , 0 }, /* SSITxD5 */ - {P4_11 , 5 , 0 }, /* SSITxD5 */ - {P8_10 , 8 , 0 }, /* SSITxD5 */ - {P3_7 , 8 , 0 }, /* WDTOVF */ - {NC , 0 , -1} -}; - -void pin_function(PinName pin, int function) { - if (pin == (PinName)NC) return; - - int n = pin >> 4; - int bitmask = 1<<(pin & 0xf); - const PinFunc * Pipc_0_func = PIPC_0_tbl; - int pipc_data = 1; - - if (gpio_multi_guard != pin) { - if (function == 0) { - // means GPIO mode - *PMC(n) &= ~bitmask; - } else { - // alt-function mode - --function; - - if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} - if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} - if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} - - while (Pipc_0_func->pin != NC) { - if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { - pipc_data = 0; - if (Pipc_0_func->pm == 0) { - *PMSR(n) = (bitmask << 16) | 0; - } else if (Pipc_0_func->pm == 1) { - *PMSR(n) = (bitmask << 16) | bitmask; - } else { - // Do Nothing - } - break; - } - Pipc_0_func++; - } - if (pipc_data == 1) { - *PIPC(n) |= bitmask; - } else { - *PIPC(n) &= ~bitmask; - } - - if (P1_0 <= pin && pin <= P1_7 && function == 0) { - *PBDC(n) |= bitmask; - } - *PMC(n) |= bitmask; - } - } else { - gpio_multi_guard = (PinName)NC; - } -} - -void pin_mode(PinName pin, PinMode mode) { -// if (pin == (PinName)NC) { return; } -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c deleted file mode 100644 index 5f9f16e4d53..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c +++ /dev/null @@ -1,65 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -PinName port_pin(PortName port, int pin_n) { - return (PinName)(0); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - // Do not use masking, because it prevents the use of the unmasked pins - // port_reg->FIOMASK = ~mask; - - uint32_t i; - // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - switch (dir) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; - } -} - -void port_write(port_t *obj, int value) { - *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) { - return (*obj->reg_in & obj->mask); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c deleted file mode 100644 index f526a221c39..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c +++ /dev/null @@ -1,378 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed_assert.h" -#include "device.h" - -#if DEVICE_RTC - -#include "rtc_api.h" -#include "rtc_iodefine.h" -#include "mbed_mktime.h" - - -#define RCR1_VAL_ON (0x08u) // AIE = 1 -#define RCR1_VAL_OFF (0x00u) -#define RCR2_VAL_ALLSTOP (0x00u) -#define RCR2_VAL_START (0x01u) // START = 1 -#define RCR2_VAL_RESET (0x02u) // RESET = 1 -#define RCR3_VAL (0x00u) -#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL -#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL -#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) -#define RFRL_VAL_13333 (0x2DCDu) // -#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF) -#define RFRL_VAL_MAX (0xFFFFu) // - -#define MASK_00_03_POS (0x000Fu) -#define MASK_04_07_POS (0x00F0u) -#define MASK_08_11_POS (0x0F00u) -#define MASK_12_15_POS (0xF000u) -#define MASK_16_20_POS (0x000F0000u) -#define SHIFT_1_HBYTE (4u) -#define SHIFT_2_HBYTE (8u) -#define SHIFT_3_HBYTE (12u) -#define SHIFT_1BYTE (8u) -#define SHIFT_2BYTE (16u) - -#define TIME_ERROR_VAL (0xFFFFFFFFu) - -static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); -static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); -static uint8_t rtc_hex8_to_dec(uint8_t hex_val); -static uint16_t rtc_hex16_to_dec(uint16_t hex_val); - - -/* - * Setup the RTC based on a time structure. - * The rtc_init function should be executed first. - * [in] - * None. - * [out] - * None. - */ -void rtc_init(void) { - volatile uint8_t dummy_read; - - // Set control register - RTC.RCR2 = RCR2_VAL_ALLSTOP; - RTC.RCR1 = RCR1_VAL_ON; - RTC.RCR3 = RCR3_VAL; - RTC.RCR5 = RCR5_VAL_EXTAL; - RTC.RFRH = RFRH_VAL_13333; - RTC.RFRL = RFRL_VAL_13333; - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - - RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - - // Set timer and alarm. Default value :01-01-1970 00:00:00 - RTC.RSECCNT = 0; - RTC.RMINCNT = 0; - RTC.RHRCNT = 0; - RTC.RWKCNT = 0; - RTC.RDAYCNT = 1; - RTC.RMONCNT = 1; - RTC.RYRCNT = 0x1970; - RTC.RSECAR = 0; - RTC.RMINAR = 0; - RTC.RHRAR = 0; - RTC.RWKAR = 0; - RTC.RDAYAR = 1; - RTC.RMONAR = 1; - RTC.RYRAR = 0x1970; - - // Dummy read - dummy_read = RTC.RYRCNT; - dummy_read = RTC.RYRCNT; - -} - - -/* - * Release the RTC based on a time structure. - * [in] - * None. - * [out] - * None. - */ -void rtc_free(void) { - volatile uint8_t dummy_read; - - // Set control register - RTC.RCR2 = RCR2_VAL_ALLSTOP; - RTC.RCR1 = RCR1_VAL_OFF; - RTC.RCR3 = RCR3_VAL; - RTC.RCR5 = RCR5_VAL_RTCX1; - RTC.RFRH = RFRH_VAL_MAX; - RTC.RFRL = RFRL_VAL_MAX; - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - - // Set timer and alarm. Default value :01-01-1970 00:00:00 - RTC.RSECCNT = 0; - RTC.RMINCNT = 0; - RTC.RHRCNT = 0; - RTC.RWKCNT = 0; - RTC.RDAYCNT = 1; - RTC.RMONCNT = 1; - RTC.RYRCNT = 0x1970; - RTC.RSECAR = 0; - RTC.RMINAR = 0; - RTC.RHRAR = 0; - RTC.RWKAR = 0; - RTC.RDAYAR = 1; - RTC.RMONAR = 1; - RTC.RYRAR = 0x1970; - - // Dummy read - dummy_read = RTC.RYRCNT; - dummy_read = RTC.RYRCNT; - -} - - -/* - * Check the RTC has been enabled. - * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled. - * [in] - * None. - * [out] - * 0:Disabled, 1:Enabled. - */ -int rtc_isenabled(void) { - int ret_val = 0; - - if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ? - ret_val = 1; - } - - return ret_val; -} - - -/* - * RTC read function. - * [in] - * None. - * [out] - * UNIX timestamp value. - */ -time_t rtc_read(void) { - - struct tm timeinfo; - int err = 0; - uint8_t tmp_regdata; - time_t t; - - if (rtc_isenabled() != 0) { - RTC.RCR1 &= ~0x10u; // CIE = 0 - do { - // before reading process - tmp_regdata = RTC.RCR1; - tmp_regdata &= ~0x80u; // CF = 0 - tmp_regdata |= 0x01u; // AF = 1 - RTC.RCR1 = tmp_regdata; - - // Read RTC register - err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec); - err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min); - err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour); - err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday); - err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon); - err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year); - } while ((RTC.RCR1 & 0x80u) != 0); - } else { - err = 1; - } - - if (err == 0) { - // Convert to timestamp - t = _rtc_mktime(&timeinfo); - } else { - // Error - t = TIME_ERROR_VAL; - } - - return t; -} - -/* - * Dec(8bit) to Hex function for RTC. - * [in] - * dec_val:Decimal value (from 0x00 to 0x99). - * offset:Subtract offset from dec_val. - * hex_val:Pointer of output hexadecimal value. - * [out] - * 0:Success - * 1:Error - */ -static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) { - int err = 0; - uint8_t ret_val; - - if (hex_val != NULL) { - if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || - ((dec_val & MASK_00_03_POS) >= 0x0A)) { - err = 1; - } else { - ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 + - (dec_val & MASK_00_03_POS); - if (ret_val < offset) { - err = 1; - } else { - *hex_val = ret_val - offset; - } - } - } else { - err = 1; - } - - return err; -} - -/* - * Dec(16bit) to Hex function for RTC - * [in] - * dec_val:Decimal value (from 0x0000 to 0x9999). - * offset:Subtract offset from dec_val. - * hex_val:Pointer of output hexadecimal value. - * [out] - * 0:Success - * 1:Error - */ -static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { - int err = 0; - uint16_t ret_val; - - if (hex_val != NULL) { - if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) || - ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) || - ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || - ((dec_val & MASK_00_03_POS) >= 0x0A)) { - err = 1; - *hex_val = 0; - } else { - ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 + - (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 + - (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 + - (dec_val & MASK_00_03_POS); - if (ret_val < offset) { - err = 1; - } else { - *hex_val = ret_val - offset; - } - } - } else { - err = 1; - } - return err; -} - -/* - * RTC write function - * [in] - * t:UNIX timestamp value - * [out] - * None. - */ -void rtc_write(time_t t) { - - struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { - return; - } - volatile uint16_t dummy_read; - - if (rtc_isenabled() != 0) { - RTC.RCR2 = RCR2_VAL_ALLSTOP; - dummy_read = (uint16_t)RTC.RCR2; - dummy_read = (uint16_t)RTC.RCR2; - RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 - dummy_read = (uint16_t)RTC.RCR2; - dummy_read = (uint16_t)RTC.RCR2; - - RTC.RSECCNT = rtc_hex8_to_dec(timeinfo.tm_sec); - RTC.RMINCNT = rtc_hex8_to_dec(timeinfo.tm_min); - RTC.RHRCNT = rtc_hex8_to_dec(timeinfo.tm_hour); - RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo.tm_mday); - RTC.RMONCNT = rtc_hex8_to_dec(timeinfo.tm_mon + 1); - RTC.RYRCNT = rtc_hex16_to_dec(timeinfo.tm_year + 1900); - dummy_read = (uint16_t)RTC.RYRCNT; - dummy_read = (uint16_t)RTC.RYRCNT; - - RTC.RCR2 = RCR2_VAL_START; // START = 1 - - dummy_read = (uint16_t)RTC.RCR2; - dummy_read = (uint16_t)RTC.RCR2; - } -} - -/* - * HEX to Dec(8bit) function for RTC. - * [in] - * hex_val:Hexadecimal value. - * [out] - * decimal value:From 0x00 to 0x99. - */ -static uint8_t rtc_hex8_to_dec(uint8_t hex_val) { - uint32_t calc_data; - - calc_data = hex_val / 10 * 0x10; - calc_data += hex_val % 10; - - if (calc_data > 0x99) { - calc_data = 0; - } - - return (uint8_t)calc_data; -} - -/* - * HEX to Dec(16bit) function for RTC. - * [in] - * hex_val:Hexadecimal value. - * [out] - * decimal value:From 0x0000 to 0x9999. - */ -static uint16_t rtc_hex16_to_dec(uint16_t hex_val) { - uint32_t calc_data; - calc_data = hex_val / 1000 * 0x1000; - calc_data += ((hex_val / 100) % 10) * 0x100; - calc_data += ((hex_val / 10) % 10) * 0x10; - calc_data += hex_val % 10; - - if (calc_data > 0x9999) { - calc_data = 0; - } - return (uint16_t)calc_data; - -} - -#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h new file mode 100644 index 00000000000..e25ceb20e1a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +typedef struct { + PinName pin; + int function; + int pm; +} PinFunc; + +/************IRQ***************/ +extern const PinMap PinMap_IRQ[]; + +/************PINMAP***************/ +extern const PinFunc PIPC_0_tbl[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************CAN***************/ +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h similarity index 53% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h index a1a385b36d9..58806d5257d 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h @@ -34,82 +34,31 @@ typedef enum { UART7, } UARTName; -// PWMType & 1 == 1 then have to use PWDTR[12] == 1 typedef enum { - PWM1A = 0, - PWM1B, - PWM1C, - PWM1D, - PWM1E, - PWM1F, - PWM1G, - PWM1H, - PWM2A = 0x10, - PWM2B, - PWM2C, - PWM2D, - PWM2E, - PWM2F, - PWM2G, - PWM2H, -} PWMType; - -typedef enum { - TIOC0A = 0, - TIOC0B, - TIOC0C, - TIOC0D, - TIOC1A = 0x10, - TIOC1B, - TIOC2A = 0x20, - TIOC2B, - TIOC3A = 0x30, - TIOC3B, - TIOC3C, - TIOC3D, - TIOC4A = 0x40, - TIOC4B, - TIOC4C, - TIOC4D, -} MTU2_PWMType; - -typedef enum { - PWM0_PIN = 0, - PWM1_PIN, - PWM2_PIN, - PWM3_PIN, - PWM4_PIN, - PWM5_PIN, - PWM6_PIN, - PWM7_PIN, - PWM8_PIN, - PWM9_PIN, - PWM10_PIN, - PWM11_PIN, - PWM12_PIN, - PWM13_PIN, - MTU2_PWM0_PIN = 0x20, - MTU2_PWM1_PIN, - MTU2_PWM2_PIN, - MTU2_PWM3_PIN, - MTU2_PWM4_PIN, - MTU2_PWM5_PIN, - MTU2_PWM6_PIN, - MTU2_PWM7_PIN, - MTU2_PWM8_PIN, - MTU2_PWM9_PIN, - MTU2_PWM10_PIN, - MTU2_PWM11_PIN, - MTU2_PWM12_PIN, - MTU2_PWM13_PIN, - MTU2_PWM14_PIN, - MTU2_PWM15_PIN, - MTU2_PWM16_PIN, - MTU2_PWM17_PIN, - MTU2_PWM18_PIN, - MTU2_PWM19_PIN, - MTU2_PWM20_PIN, - MTU2_PWM21_PIN, + PWM_PWM1A = 0, + PWM_PWM1B, + PWM_PWM1C, + PWM_PWM1D, + PWM_PWM1E, + PWM_PWM1F, + PWM_PWM1G, + PWM_PWM1H, + PWM_PWM2A, + PWM_PWM2B, + PWM_PWM2C, + PWM_PWM2D, + PWM_PWM2E, + PWM_PWM2F, + PWM_PWM2G, + PWM_PWM2H, + PWM_TIOC0A = 0x20, + PWM_TIOC0C, + PWM_TIOC1A, + PWM_TIOC2A, + PWM_TIOC3A, + PWM_TIOC3C, + PWM_TIOC4A, + PWM_TIOC4C, } PWMName; typedef enum { @@ -128,21 +77,22 @@ typedef enum { SPI_1, SPI_2, SPI_3, + SPI_4, } SPIName; typedef enum { I2C_0 = 0, I2C_1, I2C_2, - I2C_3 + I2C_3, } I2CName; typedef enum { CAN_0 = 0, CAN_1, CAN_2, - CAN_3, - CAN_4 + CAN_3, + CAN_4, } CANName; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c new file mode 100644 index 00000000000..bfc94f513aa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c @@ -0,0 +1,343 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************IRQ***************/ +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, +} IRQNo; +const PinMap PinMap_IRQ[] = { + {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4}, + {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3}, + {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11 + {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8}, + {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16 + {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3}, + {P3_9, IRQ6, 8}, // 20 + {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8}, + {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8}, + {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28 + {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31 + {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4}, + {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8}, + {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8}, + {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8}, + {P6_15, IRQ7, 8}, // 44 + {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8}, + {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8}, + {P7_14, IRQ6, 8}, // 51 + {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4}, + {P9_1, IRQ0, 4}, // 55 + {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57 + {NC, NC, 0} +}; + +/************PINMAP***************/ +const PinFunc PIPC_0_tbl[] = { +// pin func pm + {P4_0 , 2 , -1}, /* TIOC0A */ + {P5_0 , 6 , -1}, /* TIOC0A */ + {P7_0 , 7 , -1}, /* TIOC0A */ + {P10_4 , 2 , -1}, /* TIOC0A */ + {P4_1 , 2 , -1}, /* TIOC0B */ + {P5_1 , 6 , -1}, /* TIOC0B */ + {P7_1 , 7 , -1}, /* TIOC0B */ + {P10_5 , 2 , -1}, /* TIOC0B */ + {P4_2 , 2 , -1}, /* TIOC0C */ + {P5_5 , 6 , -1}, /* TIOC0C */ + {P7_2 , 7 , -1}, /* TIOC0C */ + {P10_6 , 2 , -1}, /* TIOC0C */ + {P4_3 , 2 , -1}, /* TIOC0D */ + {P5_7 , 6 , -1}, /* TIOC0D */ + {P7_3 , 7 , -1}, /* TIOC0D */ + {P10_7 , 2 , -1}, /* TIOC0D */ + {P2_11 , 5 , -1}, /* TIOC1A */ + {P6_0 , 5 , -1}, /* TIOC1A */ + {P7_4 , 7 , -1}, /* TIOC1A */ + {P8_8 , 5 , -1}, /* TIOC1A */ + {P9_7 , 4 , -1}, /* TIOC1A */ + {P10_8 , 2 , -1}, /* TIOC1A */ + {P2_12 , 8 , -1}, /* TIOC1B */ + {P5_2 , 6 , -1}, /* TIOC1B */ + {P6_1 , 5 , -1}, /* TIOC1B */ + {P7_5 , 7 , -1}, /* TIOC1B */ + {P8_9 , 5 , -1}, /* TIOC1B */ + {P10_9 , 2 , -1}, /* TIOC1B */ + {P2_1 , 6 , -1}, /* TIOC2A */ + {P6_2 , 6 , -1}, /* TIOC2A */ + {P7_6 , 7 , -1}, /* TIOC2A */ + {P8_14 , 4 , -1}, /* TIOC2A */ + {P10_10 , 2 , -1}, /* TIOC2A */ + {P2_2 , 6 , -1}, /* TIOC2B */ + {P6_3 , 6 , -1}, /* TIOC2B */ + {P7_7 , 7 , -1}, /* TIOC2B */ + {P8_15 , 4 , -1}, /* TIOC2B */ + {P10_11 , 2 , -1}, /* TIOC2B */ + {P10_11 , 2 , -1}, /* TIOC2B */ + {P3_4 , 6 , -1}, /* TIOC3A */ + {P7_8 , 7 , -1}, /* TIOC3A */ + {P8_10 , 4 , -1}, /* TIOC3A */ + {P3_5 , 6 , -1}, /* TIOC3B */ + {P7_9 , 7 , -1}, /* TIOC3B */ + {P8_11 , 4 , -1}, /* TIOC3B */ + {P3_6 , 6 , -1}, /* TIOC3C */ + {P5_3 , 6 , -1}, /* TIOC3C */ + {P7_10 , 7 , -1}, /* TIOC3C */ + {P8_12 , 4 , -1}, /* TIOC3C */ + {P3_7 , 6 , -1}, /* TIOC3D */ + {P5_4 , 6 , -1}, /* TIOC3D */ + {P7_11 , 7 , -1}, /* TIOC3D */ + {P8_13 , 4 , -1}, /* TIOC3D */ + {P3_8 , 6 , -1}, /* TIOC4A */ + {P4_4 , 3 , -1}, /* TIOC4A */ + {P7_12 , 7 , -1}, /* TIOC4A */ + {P11_0 , 2 , -1}, /* TIOC4A */ + {P3_9 , 6 , -1}, /* TIOC4B */ + {P4_5 , 3 , -1}, /* TIOC4B */ + {P7_13 , 7 , -1}, /* TIOC4B */ + {P11_1 , 2 , -1}, /* TIOC4B */ + {P3_10 , 6 , -1}, /* TIOC4C */ + {P4_6 , 3 , -1}, /* TIOC4C */ + {P7_14 , 7 , -1}, /* TIOC4C */ + {P11_2 , 2 , -1}, /* TIOC4C */ + {P3_11 , 6 , -1}, /* TIOC4D */ + {P4_7 , 3 , -1}, /* TIOC4D */ + {P7_15 , 7 , -1}, /* TIOC4D */ + {P11_3 , 2 , -1}, /* TIOC4D */ + {P5_7 , 1 , 1 }, /* TXOUT0M */ + {P5_6 , 1 , 1 }, /* TXOUT0P */ + {P5_5 , 1 , 1 }, /* TXOUT1M */ + {P5_4 , 1 , 1 }, /* TXOUT1P */ + {P5_3 , 1 , 1 }, /* TXOUT2M */ + {P5_2 , 1 , 1 }, /* TXOUT2P */ + {P5_1 , 1 , 1 }, /* TXCLKOUTM */ + {P5_0 , 1 , 1 }, /* TXCLKOUTP */ + {P2_11 , 4 , 0 }, /* SSITxD0 */ + {P4_7 , 5 , 0 }, /* SSITxD0 */ + {P7_4 , 6 , 0 }, /* SSITxD1 */ + {P10_15 , 2 , 0 }, /* SSITxD1 */ + {P4_15 , 6 , 0 }, /* SSITxD3 */ + {P7_11 , 2 , 0 }, /* SSITxD3 */ + {P2_7 , 4 , 0 }, /* SSITxD5 */ + {P4_11 , 5 , 0 }, /* SSITxD5 */ + {P8_10 , 8 , 0 }, /* SSITxD5 */ + {P3_7 , 8 , 0 }, /* WDTOVF */ + {NC , 0 , -1} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_14, AN6, 1}, + {P1_15, AN7, 1}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P2_14 , UART0, 6}, + {P2_5 , UART1, 6}, + {P4_12 , UART1, 7}, + {P6_3 , UART2, 7}, + {P4_14 , UART2, 7}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P8_14 , UART4, 7}, + {P8_13 , UART5, 5}, + {P11_10, UART5, 3}, + {P6_6 , UART5, 5}, + {P5_6 , UART6, 5}, + {P11_1 , UART6, 4}, + {P7_4 , UART7, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P2_15 , UART0, 6}, + {P2_6 , UART1, 6}, + {P4_13 , UART1, 7}, + {P6_2 , UART2, 7}, + {P4_15 , UART2, 7}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P8_15 , UART4, 7}, + {P8_11 , UART5, 5}, + {P11_11, UART5, 3}, + {P6_7 , UART5, 5}, + {P5_7 , UART6, 5}, + {P11_2 , UART6, 4}, + {P7_5 , UART7, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {P2_3 , UART1, 6}, + {P11_7 , UART5, 3}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {P2_7 , UART1, 6}, + {P11_8 , UART5, 3}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P10_12, SPI_0, 4}, + {P4_4 , SPI_1, 2}, + {P6_4 , SPI_1, 7}, + {P11_12, SPI_1, 2}, + {P8_3 , SPI_2, 3}, + {P5_0 , SPI_3, 8}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P10_14, SPI_0, 4}, + {P4_6 , SPI_1, 2}, + {P6_6 , SPI_1, 7}, + {P11_14, SPI_1, 2}, + {P8_5 , SPI_2, 3}, + {P5_2 , SPI_3, 8}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P10_15, SPI_0, 4}, + {P4_7 , SPI_1, 2}, + {P6_7 , SPI_1, 7}, + {P11_15, SPI_1, 2}, + {P8_6 , SPI_2, 3}, + {P5_3 , SPI_3, 8}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P10_13, SPI_0, 4}, + {P4_5 , SPI_1, 2}, + {P6_5 , SPI_1, 7}, + {P11_13, SPI_1, 2}, + {P8_4 , SPI_2, 3}, + {P5_1 , SPI_3, 8}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P2_1 , PWM_TIOC2A, 6}, + {P2_11 , PWM_TIOC1A, 5}, + {P3_8 , PWM_TIOC4A, 6}, + {P3_10 , PWM_TIOC4C, 6}, + {P4_0 , PWM_TIOC0A, 2}, + {P4_4 , PWM_TIOC4A, 3}, + {P4_6 , PWM_TIOC4C, 3}, + {P5_0 , PWM_TIOC0A, 6}, + {P5_3 , PWM_TIOC3C, 6}, + {P5_5 , PWM_TIOC0C, 6}, + {P7_2 , PWM_TIOC0C, 7}, + {P7_4 , PWM_TIOC1A, 7}, + {P7_6 , PWM_TIOC2A, 7}, + {P7_10 , PWM_TIOC3C, 7}, + {P7_12 , PWM_TIOC4A, 7}, + {P7_14 , PWM_TIOC4C, 7}, + {P8_8 , PWM_TIOC1A, 5}, + {P8_10 , PWM_TIOC3A, 4}, + {P8_12 , PWM_TIOC3C, 4}, + {P8_14 , PWM_TIOC2A, 4}, + {P11_0 , PWM_TIOC4A, 2}, + {P11_2 , PWM_TIOC4C, 2}, + {P4_4 , PWM_PWM2E , 4}, + {P3_2 , PWM_PWM2C , 7}, + {P4_6 , PWM_PWM2G , 4}, + {P4_7 , PWM_PWM2H , 4}, + {P8_14 , PWM_PWM1G , 6}, + {P8_15 , PWM_PWM1H , 6}, + {P8_13 , PWM_PWM1F , 6}, + {P8_11 , PWM_PWM1D , 6}, + {P8_8 , PWM_PWM1A , 6}, + {P10_0 , PWM_PWM2A , 3}, + {P8_12 , PWM_PWM1E , 6}, + {P8_9 , PWM_PWM1B , 6}, + {P8_10 , PWM_PWM1C , 6}, + {P4_5 , PWM_PWM2F , 4}, + {NC , NC , 0} +}; + +/************CAN***************/ +const PinMap PinMap_CAN_RD[] = { + {P7_8 , CAN_0, 4}, + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P7_11 , CAN_1, 4}, + {P11_12, CAN_1, 1}, + {P4_9 , CAN_2, 6}, + {P6_4 , CAN_2, 3}, + {P7_2 , CAN_2, 5}, + {P2_12 , CAN_3, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {P2_14 , CAN_4, 5}, + {NC , NC , 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {P7_9 , CAN_0, 4}, + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P7_10 , CAN_1, 4}, + {P11_13, CAN_1, 1}, + {P4_8 , CAN_2, 6}, + {P6_5 , CAN_2, 3}, + {P7_3 , CAN_2, 5}, + {P2_13 , CAN_3, 5}, + {P4_3 , CAN_3, 4}, + {P4_11 , CAN_4, 6}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +}; + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PinNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PinNames.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h similarity index 87% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h index 270cdeecb0c..b5c36327059 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h @@ -25,7 +25,14 @@ typedef enum { Port1 = 1, Port2 = 2, Port3 = 3, - Port4 = 4 + Port4 = 4, + Port5 = 5, + Port6 = 6, + Port7 = 7, + Port8 = 8, + Port9 = 9, + Port10 = 10, + Port11 = 11 } PortName; #ifdef __cplusplus diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/MBRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/MBRZA1H.h new file mode 100644 index 00000000000..49497bca7d0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/MBRZA1H.h @@ -0,0 +1 @@ +#include "RZ_A1H.h" diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct new file mode 100644 index 00000000000..88de0ab2cea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct @@ -0,0 +1,57 @@ +#! armcc -E +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +#include "mem_RZ_A1H.h" + +LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM +{ + TTB +0 EMPTY 0x4000 + { } ; Level-1 Translation Table for MMU +} + +SFLASH __ROM_BASE __ROM_SIZE ; load region size_region +{ + BOOT_LOADER_BEGIN __ROM_BASE FIXED + { + * (BOOT_LOADER) + } + + VECTORS __VECTOR_BASE FIXED + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA 0x20020000 + { * (+RW) } ; Application RW data (.data) + + RW_IRAM1 +0 ALIGN 0x10 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP +0 + { * (HEAP) } ; Application heap area (HEAP) + + ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; RAM-NC : Internal non-cached RAM region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE + { * (NC_DATA) } ; Application RW data Non cached area + + ZI_DATA_NC +0 + { * (NC_BSS) } ; Application ZI data Non cached area +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h new file mode 100644 index 00000000000..38a9986ddbc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h @@ -0,0 +1,77 @@ +/**************************************************************************//** + * @file mem_RZ_A1H.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_RZ_A1H_H +#define __MEM_RZ_A1H_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// ROM Base Address <0x0-0xFFFFFFFF:8> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x18000000 +#define __ROM_SIZE 0x08000000 + +#define __VECTOR_BASE 0x18004000 + +/*--------------------- RAM Configuration ----------------------------------- + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00A00000 +#define __NC_RAM_SIZE 0x00100000 +#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) +#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) + +#define __UND_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00008000 +#define __ABT_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x0000F000 +#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// TTB Base Address <0x0-0xFFFFFFFF:8> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x20000000 +#define __TTB_SIZE 0x00004000 + +#endif /* __MEM_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c new file mode 100644 index 00000000000..f01ea2d775c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c @@ -0,0 +1,162 @@ +/****************************************************************************** + * @file startup_RZ_A1H_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "MBRZA1H.h" +#include "mem_RZ_A1H.h" + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((section("RESET"))); +void Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +__ASM void Vectors(void) { + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__ASM void Reset_Handler(void) { + + // Mask interrupts + CPSID if + + // Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 // Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + // Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register + ISB + + // Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + // Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + //Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + // Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + // Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + // Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + // Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + // Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + // Call SystemInit + IMPORT SystemInit + BL SystemInit + + // Unmask interrupts + CPSIE if + + // Call __main + IMPORT __main + BL __main +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..dfa0bc6f1fc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2017 ARM Limited. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include +#endif + +#include +#include + +extern char Image$$ARM_LIB_HEAP$$Base[]; +extern char Image$$ARM_LIB_STACK$$Base[]; + +extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base; + uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base; + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld similarity index 95% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld index 3a27d14fea4..c30567eaedd 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld @@ -7,7 +7,7 @@ MEMORY BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000 + RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000 RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000 } @@ -51,7 +51,6 @@ SECTIONS Image$$VECTORS$$Base = .; * (RESET) - Image$$VECTORS$$Limit = .; . += 0x00000400; KEEP(*(.isr_vector)) @@ -74,6 +73,7 @@ SECTIONS *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) + Image$$VECTORS$$Limit = .; Image$$RO_DATA$$Base = .; *(.rodata*) @@ -163,34 +163,42 @@ SECTIONS } > RAM - - .bss ALIGN(0x400): + .bss ALIGN(0x10): { - Image$$ZI_DATA$$Base = .; + Image$$RW_IRAM1$$Base = .; __bss_start__ = .; *(.bss*) *(COMMON) __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; + Image$$RW_IRAM1$$Limit = .; } > RAM - .heap : { __end__ = .; end = __end__; *(.heap*) - __HeapLimit = .; } > RAM /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy : + .stack_dummy (COPY): { - *(.stack) + *(.stack*) } > RAM + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + __HeapLimit = __StackLimit; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + __etext2 = __etext + SIZEOF(.data); .nc_data : AT (__etext2) { @@ -213,15 +221,4 @@ SECTIONS __nc_bss_end = .; Image$$ZI_DATA_NC$$Limit = .; } > RAM_NC - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S new file mode 100644 index 00000000000..4c1a629bb59 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S @@ -0,0 +1,249 @@ +/* File: startup_ARMCM3.s + * Purpose: startup file for Cortex-M3/M4 devices. Should use with + * GNU Tools for ARM Embedded Processors + * Version: V1.1 + * Date: 17 June 2011 + * + * Copyright (C) 2011 ARM Limited. All rights reserved. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + */ + .syntax unified + .extern _start + +@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs + .equ Mode_USR , 0x10 + .equ Mode_FIQ , 0x11 + .equ Mode_IRQ , 0x12 + .equ Mode_SVC , 0x13 + .equ Mode_ABT , 0x17 + .equ Mode_UND , 0x1B + .equ Mode_SYS , 0x1F + + .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled + .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled + .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state + +@ Stack Configuration + + .EQU UND_Stack_Size , 0x00000100 + .EQU SVC_Stack_Size , 0x00008000 + .EQU ABT_Stack_Size , 0x00000100 + .EQU FIQ_Stack_Size , 0x00000100 + .EQU IRQ_Stack_Size , 0x0000F000 + + .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space ISR_Stack_Size +__initial_sp: + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +@ Heap Configuration + + .EQU Heap_Size , 0x00080000 + + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long 0xe59ff018 /* 0x00 */ + .long 0xe59ff018 /* 0x04 */ + .long 0xe59ff018 /* 0x08 */ + .long 0xe59ff018 /* 0x0c */ + .long 0xe59ff018 /* 0x10 */ + .long 0xe59ff018 /* 0x14 */ + .long 0xe59ff018 /* 0x18 */ + .long 0xe59ff018 /* 0x1c */ + + .long Reset_Handler /* 0x20 */ + .long Undef_Handler /* 0x24 */ + .long SVC_Handler /* 0x28 */ + .long PAbt_Handler /* 0x2c */ + .long DAbt_Handler /* 0x30 */ + .long 0 /* Reserved */ + .long IRQ_Handler /* IRQ */ + .long FIQ_Handler /* FIQ */ + + + .size __isr_vector, . - __isr_vector + + .text + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + @ Mask interrupts + CPSID if + + @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + ands r0, r0, #3 +goToSleep: + wfine + bne goToSleep + + @ Reset SCTLR Settings + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register + isb + + @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register + + @ Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__isr_vector + mcr p15, 0, r0, c12, c0, 0 + +@ Setup Stack for each exceptional mode + ldr r0, =__StackTop + +@ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #UND_Stack_Size + +@ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + +@ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + +@ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + +@ Enter Supervisor Mode and set its Stack Pointer + msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit) + mov sp, r0 + +@ Enter System Mode to complete initialization and enter kernel + msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) + mov sp, r0 + +@ USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + + @ Unmask interrupts + CPSIE if + +@ data sections copy + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +@ bss sections clear + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + + ldr r0, =_start + bx r0 + + ldr r0, sf_boot @ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + .word boot_loader + + .pool + .size Reset_Handler, . - Reset_Handler + + + .text + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler Undef_Handler + def_default_handler SVC_Handler + def_default_handler PAbt_Handler + def_default_handler DAbt_Handler + def_default_handler IRQ_Handler + def_default_handler FIQ_Handler + + .END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S new file mode 100644 index 00000000000..9f6858da6f0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S @@ -0,0 +1,226 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 49919 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector_table + PUBLIC __RST_Handler + EXTERN Undef_Handler + EXTERN SVC_Handler + EXTERN PAbt_Handler + EXTERN DAbt_Handler + EXTERN IRQ_Handler + PUBLIC FIQ_Handler + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __RST_Handler +Undefined_Addr: DCD Undef_Handler +SWI_Addr: DCD SVC_Handler +Prefetch_Addr: DCD PAbt_Handler +Abort_Addr: DCD DAbt_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + EXTERN SystemInit + EXTERN __iar_program_start + REQUIRE __vector_table + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__RST_Handler: +?cstartup: + +;;; @ Mask interrupts + CPSID if + +;;; @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + +;;; @ Reset SCTLR Settings + mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register + isb + +;;; @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register + +;; Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__vector_table + mcr p15, 0, r0, c12, c0, 0 + + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + + MRS r0, cpsr ; Original PSR value + + ;; Set up the SVC stack pointer. + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the ABT stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #ABT_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the UDF stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #UND_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + +;;; +; USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __RST_Handler, __iar_program_start + B __iar_program_start + + + ldr r0, sf_boot ;@ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + DC32 0x00000001 + +FIQ_Handler: + B . + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis_nvic.c similarity index 95% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis_nvic.c index 052c30c74bc..1eec60bca42 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis_nvic.c @@ -29,14 +29,13 @@ ******************************************************************************* */ #include "MBRZA1H.h" - -extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; +#include "irq_ctrl.h" void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { InterruptHandlerRegister(IRQn, (IRQHandler)vector); } uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t vectors = (uint32_t)IRQTable[IRQn]; + uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn); return vectors; } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h similarity index 63% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h index 27dc426d44b..4a08008dc7e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h @@ -1,65 +1,59 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** - * @file MBRZA1H.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for - * Renesas MBRZA1H Device Series - * @version - * @date 19 Sept 2013 +/****************************************************************************** + * @file RZ_A1H.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version V1.00 + * @data 10 Mar 2017 * * @note * ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ -#ifndef __MBRZA1H_H__ -#define __MBRZA1H_H__ +#ifndef __RZ_A1H_H__ +#define __RZ_A1H_H__ #ifdef __cplusplus extern "C" { #endif - /* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum IRQn { /****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, - SGI1_IRQn = 1, - SGI2_IRQn = 2, - SGI3_IRQn = 3, - SGI4_IRQn = 4, - SGI5_IRQn = 5, - SGI6_IRQn = 6, - SGI7_IRQn = 7, - SGI8_IRQn = 8, - SGI9_IRQn = 9, - SGI10_IRQn = 10, - SGI11_IRQn = 11, - SGI12_IRQn = 12, - SGI13_IRQn = 13, - SGI14_IRQn = 14, - SGI15_IRQn = 15, + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, /****** Cortex-A9 Processor Exceptions Numbers ****************************************/ /* 16 - 578 */ @@ -418,7 +412,6 @@ typedef enum IRQn /* 365-380 Reserved */ - H2XMLB_ERRINT_IRQn = 381, H2XIC1_ERRINT_IRQn = 382, X2HPERI1_ERRINT_IRQn = 383, @@ -440,6 +433,7 @@ typedef enum IRQn PFVEI1_IRQn = 398, /* 399-415 Reserved */ + TINT0_IRQn = 416, TINT1_IRQn = 417, TINT2_IRQn = 418, @@ -614,236 +608,53 @@ typedef enum IRQn } IRQn_Type; -#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn - -/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ -#define __CA9_REV 0x0000 /*!< Core revision r0 */ - -#define __MPU_PRESENT 1 /*!< MPU present or not */ - -#define __FPU_PRESENT 1 /*!< FPU present or not */ - -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -#include -#include "system_MBRZA1H.h" - +#define RZ_A1_IRQ_MAX TINT170_IRQn /******************************************************************************/ -/* Device Specific Peripheral Section */ +/* Peripheral memory map */ /******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals - Renesas_RZ_A1 Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#include "pl310.h" -#include "gic.h" -#include "nvic_wrapper.h" -#include "cmsis_nvic.h" -#include "ostm_iodefine.h" -#include "gpio_iodefine.h" -#include "cpg_iodefine.h" -#include "l2c_iodefine.h" +#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ +#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ +#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ +#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ +#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ +#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ +#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ +#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ +#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ +#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE +#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE +#define L2C_310_BASE RZ_A1_PL310_BASE +#define TIMER_BASE RZ_A1_PRIVATE_TIMER -#if defined ( __CC_ARM ) -#pragma no_anon_unions +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /*!< Core revision r0p0 */ +#define __CORTEX_A 9U /*!< Cortex-A9 Core */ +#if (__FPU_PRESENT != 1) +#undef __FPU_PRESENT +#define __FPU_PRESENT 1U /* FPU present */ #endif +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ -/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */ - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping - @{ -*/ - -/* R7S72100 CPU board */ -#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ -#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ -#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ -#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ -#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ -#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ -#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ -#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ -#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ -#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ -#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ -#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ - -//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map -//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0. -#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0. -#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_RO. Sect_Normal_Cod, but not executable -#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable -#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 -#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Device_RW. Sect_Device_RO, but writeable -#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 -#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); - -//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 -#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); - - -/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */ +#include "core_ca.h" +#include +#include "iodefine.h" /******************************************************************************/ /* Clock Settings */ /******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions - @{ -*/ - /* * Clock Mode 0 settings * SW1-4(MD_CLK):ON @@ -882,15 +693,9 @@ typedef enum IRQn #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) -/*@}*/ /* end of group Renesas_RZ_A1_Clocks */ - /******************************************************************************/ /* CPG Settings */ /******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions - @{ -*/ - #define CPG_FRQCR_SHIFT_CKOEN2 (14) #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) #define CPG_FRQCR_SHIFT_CKOEN0 (12) @@ -912,6 +717,7 @@ typedef enum IRQn #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ @@ -929,17 +735,17 @@ typedef enum IRQn #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ -#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ -#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */ -#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ -#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ @@ -948,6 +754,7 @@ typedef enum IRQn #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ @@ -975,7 +782,8 @@ typedef enum IRQn #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ -#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */ +#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ +#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ @@ -983,21 +791,8 @@ typedef enum IRQn #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ -#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */ -#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */ -#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */ -#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */ -#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */ -#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */ #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ -#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */ -#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */ -#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */ -#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */ #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ -#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */ -#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */ -#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */ #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ @@ -1012,16 +807,85 @@ typedef enum IRQn #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ - -/*@}*/ /* end of group Renesas_RZ_A1_CPG */ +#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ +#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ +#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ +#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ +#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ +#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ +#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ +#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ +#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ +#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ +#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ +#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ +#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ +#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ +#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ +#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ +#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ +#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ +#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ +#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ +#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ +#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ +#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ +#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ +#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ +#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ +#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ +#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ +#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ +#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ +#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ +#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ +#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ +#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ +#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ +#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ +#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ +#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ +#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ +#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ +#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ +#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ +#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ +#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ +#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ +#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ +#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ +#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ +#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ +#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ +#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ +#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ +#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ +#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ +#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ +#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ +#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ +#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ +#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ +#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ +#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ +#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ +#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ +#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ +#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ +#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ +#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ +#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ +#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ +#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ +#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ /******************************************************************************/ /* GPIO Settings */ /******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions - @{ -*/ - #define GPIO_BIT_N0 (1u << 0) #define GPIO_BIT_N1 (1u << 1) #define GPIO_BIT_N2 (1u << 2) @@ -1039,7 +903,6 @@ typedef enum IRQn #define GPIO_BIT_N14 (1u << 14) #define GPIO_BIT_N15 (1u << 15) - #define MD_BOOT10_MASK (0x3) #define MD_BOOT10_BM0 (0x0) @@ -1050,10 +913,9 @@ typedef enum IRQn #define MD_CLK (1u << 2) #define MD_CLKS (1u << 3) -/*@}*/ /* end of group Renesas_RZ_A1_GPIO */ #ifdef __cplusplus } #endif -#endif // __MBRZA1H_H__ +#endif // __RZ_A1H_H__ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefine.h new file mode 100644 index 00000000000..d01d74b0e69 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefine.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef R7S721000_IODEFINE_H +#define R7S721000_IODEFINE_H + +#include "iodefines/iodefine_typedef.h" /* (V2.00h) */ + +#include "iodefines/adc_iodefine.h" /* (V2.00h) */ +#include "iodefines/bsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ceu_iodefine.h" /* (V2.00h) */ +#include "iodefines/cpg_iodefine.h" /* (V2.00h) */ +#include "iodefines/disc_iodefine.h" /* (V2.00h) */ +#include "iodefines/dmac_iodefine.h" /* (V2.00h) */ +#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/ether_iodefine.h" /* (V2.00h) */ +#include "iodefines/flctl_iodefine.h" /* (V2.00h) */ +#include "iodefines/gpio_iodefine.h" /* (V2.00h) */ +#include "iodefines/ieb_iodefine.h" /* (V2.00h) */ +#include "iodefines/inb_iodefine.h" /* (V2.00h) */ +#include "iodefines/intc_iodefine.h" /* (V2.00h) */ +#include "iodefines/irda_iodefine.h" /* (V2.00h) */ +#include "iodefines/jcu_iodefine.h" /* (V2.00h) */ +#include "iodefines/l2c_iodefine.h" /* (V2.00h) */ +#include "iodefines/lin_iodefine.h" /* (V2.00h) */ +#include "iodefines/lvds_iodefine.h" /* (V2.00h) */ +#include "iodefines/mlb_iodefine.h" /* (V2.00h) */ +#include "iodefines/mmc_iodefine.h" /* (V2.00h) */ +#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */ +#include "iodefines/ostm_iodefine.h" /* (V2.00h) */ +#include "iodefines/pfv_iodefine.h" /* (V2.00h) */ +#include "iodefines/pwm_iodefine.h" /* (V2.00h) */ +#include "iodefines/riic_iodefine.h" /* (V2.00h) */ +#include "iodefines/romdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */ +#include "iodefines/rspi_iodefine.h" /* (V2.00h) */ +#include "iodefines/rtc_iodefine.h" /* (V2.00h) */ +#include "iodefines/scif_iodefine.h" /* (V2.00h) */ +#include "iodefines/scim_iodefine.h" /* (V2.00h) */ +#include "iodefines/scux_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdg_iodefine.h" /* (V2.00h) */ +#include "iodefines/spdif_iodefine.h" /* (V2.00h) */ +#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ssif_iodefine.h" /* (V2.00h) */ +#include "iodefines/usb20_iodefine.h" /* (V2.00h) */ +#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */ +#include "iodefines/wdt_iodefine.h" /* (V2.00h) */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h similarity index 76% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h index 55bc7ddd26b..a16183efcc9 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h @@ -18,20 +18,56 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : adc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ADC_IODEFINE_H #define ADC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_adc -{ /* ADC */ +#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ + + +#define ADCADDRA (ADC.ADDRA) +#define ADCADDRB (ADC.ADDRB) +#define ADCADDRC (ADC.ADDRC) +#define ADCADDRD (ADC.ADDRD) +#define ADCADDRE (ADC.ADDRE) +#define ADCADDRF (ADC.ADDRF) +#define ADCADDRG (ADC.ADDRG) +#define ADCADDRH (ADC.ADDRH) +#define ADCADCMPHA (ADC.ADCMPHA) +#define ADCADCMPLA (ADC.ADCMPLA) +#define ADCADCMPHB (ADC.ADCMPHB) +#define ADCADCMPLB (ADC.ADCMPLB) +#define ADCADCMPHC (ADC.ADCMPHC) +#define ADCADCMPLC (ADC.ADCMPLC) +#define ADCADCMPHD (ADC.ADCMPHD) +#define ADCADCMPLD (ADC.ADCMPLD) +#define ADCADCMPHE (ADC.ADCMPHE) +#define ADCADCMPLE (ADC.ADCMPLE) +#define ADCADCMPHF (ADC.ADCMPHF) +#define ADCADCMPLF (ADC.ADCMPLF) +#define ADCADCMPHG (ADC.ADCMPHG) +#define ADCADCMPLG (ADC.ADCMPLG) +#define ADCADCMPHH (ADC.ADCMPHH) +#define ADCADCMPLH (ADC.ADCMPLH) +#define ADCADCSR (ADC.ADCSR) +#define ADCADCMPER (ADC.ADCMPER) +#define ADCADCMPSR (ADC.ADCMPSR) + + +typedef struct st_adc +{ + /* ADC */ volatile uint16_t ADDRA; /* ADDRA */ volatile uint16_t ADDRB; /* ADDRB */ volatile uint16_t ADDRC; /* ADDRC */ @@ -61,38 +97,11 @@ struct st_adc volatile uint16_t ADCSR; /* ADCSR */ volatile uint16_t ADCMPER; /* ADCMPER */ volatile uint16_t ADCMPSR; /* ADCMPSR */ -}; - - -#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ +} r_io_adc_t; -#define ADCADDRA ADC.ADDRA -#define ADCADDRB ADC.ADDRB -#define ADCADDRC ADC.ADDRC -#define ADCADDRD ADC.ADDRD -#define ADCADDRE ADC.ADDRE -#define ADCADDRF ADC.ADDRF -#define ADCADDRG ADC.ADDRG -#define ADCADDRH ADC.ADDRH -#define ADCADCMPHA ADC.ADCMPHA -#define ADCADCMPLA ADC.ADCMPLA -#define ADCADCMPHB ADC.ADCMPHB -#define ADCADCMPLB ADC.ADCMPLB -#define ADCADCMPHC ADC.ADCMPHC -#define ADCADCMPLC ADC.ADCMPLC -#define ADCADCMPHD ADC.ADCMPHD -#define ADCADCMPLD ADC.ADCMPLD -#define ADCADCMPHE ADC.ADCMPHE -#define ADCADCMPLE ADC.ADCMPLE -#define ADCADCMPHF ADC.ADCMPHF -#define ADCADCMPLF ADC.ADCMPLF -#define ADCADCMPHG ADC.ADCMPHG -#define ADCADCMPLG ADC.ADCMPLG -#define ADCADCMPHH ADC.ADCMPHH -#define ADCADCMPLH ADC.ADCMPLH -#define ADCADCSR ADC.ADCSR -#define ADCADCMPER ADC.ADCMPER -#define ADCADCMPSR ADC.ADCMPSR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h similarity index 75% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h index 0d327ac7607..6665787ee7d 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h @@ -18,22 +18,61 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : bsc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef BSC_IODEFINE_H #define BSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_bsc -{ /* BSC */ +#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ + + +#define BSCCMNCR (BSC.CMNCR) +#define BSCCS0BCR (BSC.CS0BCR) +#define BSCCS1BCR (BSC.CS1BCR) +#define BSCCS2BCR (BSC.CS2BCR) +#define BSCCS3BCR (BSC.CS3BCR) +#define BSCCS4BCR (BSC.CS4BCR) +#define BSCCS5BCR (BSC.CS5BCR) +#define BSCCS0WCR (BSC.CS0WCR) +#define BSCCS1WCR (BSC.CS1WCR) +#define BSCCS2WCR (BSC.CS2WCR) +#define BSCCS3WCR (BSC.CS3WCR) +#define BSCCS4WCR (BSC.CS4WCR) +#define BSCCS5WCR (BSC.CS5WCR) +#define BSCSDCR (BSC.SDCR) +#define BSCRTCSR (BSC.RTCSR) +#define BSCRTCNT (BSC.RTCNT) +#define BSCRTCOR (BSC.RTCOR) +#define BSCTOSCOR0 (BSC.TOSCOR0) +#define BSCTOSCOR1 (BSC.TOSCOR1) +#define BSCTOSCOR2 (BSC.TOSCOR2) +#define BSCTOSCOR3 (BSC.TOSCOR3) +#define BSCTOSCOR4 (BSC.TOSCOR4) +#define BSCTOSCOR5 (BSC.TOSCOR5) +#define BSCTOSTR (BSC.TOSTR) +#define BSCTOENR (BSC.TOENR) + +#define BSC_CSnBCR_COUNT (6) +#define BSC_CSnWCR_COUNT (6) +#define BSC_TOSCORn_COUNT (6) + + +typedef struct st_bsc +{ + /* BSC */ volatile uint32_t CMNCR; /* CMNCR */ -#define BSC_CSnBCR_COUNT 6 + +/* #define BSC_CSnBCR_COUNT (6) */ volatile uint32_t CS0BCR; /* CS0BCR */ volatile uint32_t CS1BCR; /* CS1BCR */ volatile uint32_t CS2BCR; /* CS2BCR */ @@ -41,7 +80,8 @@ struct st_bsc volatile uint32_t CS4BCR; /* CS4BCR */ volatile uint32_t CS5BCR; /* CS5BCR */ volatile uint8_t dummy4[12]; /* */ -#define BSC_CSnWCR_COUNT 6 + +/* #define BSC_CSnWCR_COUNT (6) */ volatile uint32_t CS0WCR; /* CS0WCR */ volatile uint32_t CS1WCR; /* CS1WCR */ volatile uint32_t CS2WCR; /* CS2WCR */ @@ -54,7 +94,8 @@ struct st_bsc volatile uint32_t RTCNT; /* RTCNT */ volatile uint32_t RTCOR; /* RTCOR */ volatile uint8_t dummy6[4]; /* */ -#define BSC_TOSCORn_COUNT 6 + +/* #define BSC_TOSCORn_COUNT (6) */ volatile uint32_t TOSCOR0; /* TOSCOR0 */ volatile uint32_t TOSCOR1; /* TOSCOR1 */ volatile uint32_t TOSCOR2; /* TOSCOR2 */ @@ -64,36 +105,11 @@ struct st_bsc volatile uint8_t dummy7[8]; /* */ volatile uint32_t TOSTR; /* TOSTR */ volatile uint32_t TOENR; /* TOENR */ -}; - - -#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ +} r_io_bsc_t; -#define BSCCMNCR BSC.CMNCR -#define BSCCS0BCR BSC.CS0BCR -#define BSCCS1BCR BSC.CS1BCR -#define BSCCS2BCR BSC.CS2BCR -#define BSCCS3BCR BSC.CS3BCR -#define BSCCS4BCR BSC.CS4BCR -#define BSCCS5BCR BSC.CS5BCR -#define BSCCS0WCR BSC.CS0WCR -#define BSCCS1WCR BSC.CS1WCR -#define BSCCS2WCR BSC.CS2WCR -#define BSCCS3WCR BSC.CS3WCR -#define BSCCS4WCR BSC.CS4WCR -#define BSCCS5WCR BSC.CS5WCR -#define BSCSDCR BSC.SDCR -#define BSCRTCSR BSC.RTCSR -#define BSCRTCNT BSC.RTCNT -#define BSCRTCOR BSC.RTCOR -#define BSCTOSCOR0 BSC.TOSCOR0 -#define BSCTOSCOR1 BSC.TOSCOR1 -#define BSCTOSCOR2 BSC.TOSCOR2 -#define BSCTOSCOR3 BSC.TOSCOR3 -#define BSCTOSCOR4 BSC.TOSCOR4 -#define BSCTOSCOR5 BSC.TOSCOR5 -#define BSCTOSTR BSC.TOSTR -#define BSCTOENR BSC.TOENR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h similarity index 83% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h index 535b18bed04..a970bfd807a 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h @@ -18,20 +18,108 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ceu_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef CEU_IODEFINE_H #define CEU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ceu -{ /* CEU */ +#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ + + +/* Start of channel array defines of CEU */ + +/* Channel array defines of CEUn */ +/*(Sample) value = CEUn[ channel ]->CAMOR; */ +#define CEUn_COUNT (3) +#define CEUn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + (volatile struct st_ceu_n*)&CEU_A, \ + (volatile struct st_ceu_n*)&CEU_B, \ + (volatile struct st_ceu_n*)&CEU_M \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ +#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ +#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ + +/* End of channel array defines of CEU */ + + +#define CEUCAPSR (CEU.CAPSR) +#define CEUCAPCR (CEU.CAPCR) +#define CEUCAMCR (CEU.CAMCR) +#define CEUCMCYR (CEU.CMCYR) +#define CEUCAMOR_A (CEU.CAMOR_A) +#define CEUCAPWR_A (CEU.CAPWR_A) +#define CEUCAIFR (CEU.CAIFR) +#define CEUCRCNTR (CEU.CRCNTR) +#define CEUCRCMPR (CEU.CRCMPR) +#define CEUCFLCR_A (CEU.CFLCR_A) +#define CEUCFSZR_A (CEU.CFSZR_A) +#define CEUCDWDR_A (CEU.CDWDR_A) +#define CEUCDAYR_A (CEU.CDAYR_A) +#define CEUCDACR_A (CEU.CDACR_A) +#define CEUCDBYR_A (CEU.CDBYR_A) +#define CEUCDBCR_A (CEU.CDBCR_A) +#define CEUCBDSR_A (CEU.CBDSR_A) +#define CEUCFWCR (CEU.CFWCR) +#define CEUCLFCR_A (CEU.CLFCR_A) +#define CEUCDOCR_A (CEU.CDOCR_A) +#define CEUCEIER (CEU.CEIER) +#define CEUCETCR (CEU.CETCR) +#define CEUCSTSR (CEU.CSTSR) +#define CEUCDSSR (CEU.CDSSR) +#define CEUCDAYR2_A (CEU.CDAYR2_A) +#define CEUCDACR2_A (CEU.CDACR2_A) +#define CEUCDBYR2_A (CEU.CDBYR2_A) +#define CEUCDBCR2_A (CEU.CDBCR2_A) +#define CEUCAMOR_B (CEU.CAMOR_B) +#define CEUCAPWR_B (CEU.CAPWR_B) +#define CEUCFLCR_B (CEU.CFLCR_B) +#define CEUCFSZR_B (CEU.CFSZR_B) +#define CEUCDWDR_B (CEU.CDWDR_B) +#define CEUCDAYR_B (CEU.CDAYR_B) +#define CEUCDACR_B (CEU.CDACR_B) +#define CEUCDBYR_B (CEU.CDBYR_B) +#define CEUCDBCR_B (CEU.CDBCR_B) +#define CEUCBDSR_B (CEU.CBDSR_B) +#define CEUCLFCR_B (CEU.CLFCR_B) +#define CEUCDOCR_B (CEU.CDOCR_B) +#define CEUCDAYR2_B (CEU.CDAYR2_B) +#define CEUCDACR2_B (CEU.CDACR2_B) +#define CEUCDBYR2_B (CEU.CDBYR2_B) +#define CEUCDBCR2_B (CEU.CDBCR2_B) +#define CEUCAMOR_M (CEU.CAMOR_M) +#define CEUCAPWR_M (CEU.CAPWR_M) +#define CEUCFLCR_M (CEU.CFLCR_M) +#define CEUCFSZR_M (CEU.CFSZR_M) +#define CEUCDWDR_M (CEU.CDWDR_M) +#define CEUCDAYR_M (CEU.CDAYR_M) +#define CEUCDACR_M (CEU.CDACR_M) +#define CEUCDBYR_M (CEU.CDBYR_M) +#define CEUCDBCR_M (CEU.CDBCR_M) +#define CEUCBDSR_M (CEU.CBDSR_M) +#define CEUCLFCR_M (CEU.CLFCR_M) +#define CEUCDOCR_M (CEU.CDOCR_M) +#define CEUCDAYR2_M (CEU.CDAYR2_M) +#define CEUCDACR2_M (CEU.CDACR2_M) +#define CEUCDBYR2_M (CEU.CDBYR2_M) +#define CEUCDBCR2_M (CEU.CDBCR2_M) + + +typedef struct st_ceu +{ + /* CEU */ + /* start of struct st_ceu_n */ volatile uint32_t CAPSR; /* CAPSR */ volatile uint32_t CAPCR; /* CAPCR */ @@ -67,8 +155,10 @@ struct st_ceu volatile uint32_t CDACR2_A; /* CDACR2_A */ volatile uint32_t CDBYR2_A; /* CDBYR2_A */ volatile uint32_t CDBCR2_A; /* CDBCR2_A */ + /* end of struct st_ceu_n */ volatile uint8_t dummy3110[3936]; /* */ + /* start of struct st_ceu_n */ volatile uint8_t dummy3111[4]; /* */ volatile uint8_t dummy3112[4]; /* */ @@ -104,8 +194,10 @@ struct st_ceu volatile uint32_t CDACR2_B; /* CDACR2_B */ volatile uint32_t CDBYR2_B; /* CDBYR2_B */ volatile uint32_t CDBCR2_B; /* CDBCR2_B */ + /* end of struct st_ceu_n */ volatile uint8_t dummy3150[3936]; /* */ + /* start of struct st_ceu_n */ volatile uint8_t dummy3151[4]; /* */ volatile uint8_t dummy3152[4]; /* */ @@ -141,12 +233,14 @@ struct st_ceu volatile uint32_t CDACR2_M; /* CDACR2_M */ volatile uint32_t CDBYR2_M; /* CDBYR2_M */ volatile uint32_t CDBCR2_M; /* CDBCR2_M */ + /* end of struct st_ceu_n */ -}; +} r_io_ceu_t; -struct st_ceu_n +typedef struct st_ceu_n { + volatile uint32_t not_common1; /* */ volatile uint32_t not_common2; /* */ volatile uint32_t not_common3; /* */ @@ -181,89 +275,21 @@ struct st_ceu_n volatile uint32_t CDACR2; /* CDACR2 */ volatile uint32_t CDBYR2; /* CDBYR2 */ volatile uint32_t CDBCR2; /* CDBCR2 */ -}; - - -#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ - - -/* Start of channnel array defines of CEU */ +} r_io_ceu_n_t; -/* Channnel array defines of CEUn */ -/*(Sample) value = CEUn[ channel ]->CAMOR; */ -#define CEUn_COUNT 3 -#define CEUn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - (volatile struct st_ceu_n*)&CEU_A, \ - (volatile struct st_ceu_n*)&CEU_B, \ - (volatile struct st_ceu_n*)&CEU_M \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ -#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ -#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ -/* End of channnel array defines of CEU */ +/* Channel array defines of CEUn (2)*/ +#ifdef DECLARE_CEUn_CHANNELS +volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CEUn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CEUn_CHANNELS */ +/* End of channel array defines of CEUn (2)*/ -#define CEUCAPSR CEU.CAPSR -#define CEUCAPCR CEU.CAPCR -#define CEUCAMCR CEU.CAMCR -#define CEUCMCYR CEU.CMCYR -#define CEUCAMOR_A CEU.CAMOR_A -#define CEUCAPWR_A CEU.CAPWR_A -#define CEUCAIFR CEU.CAIFR -#define CEUCRCNTR CEU.CRCNTR -#define CEUCRCMPR CEU.CRCMPR -#define CEUCFLCR_A CEU.CFLCR_A -#define CEUCFSZR_A CEU.CFSZR_A -#define CEUCDWDR_A CEU.CDWDR_A -#define CEUCDAYR_A CEU.CDAYR_A -#define CEUCDACR_A CEU.CDACR_A -#define CEUCDBYR_A CEU.CDBYR_A -#define CEUCDBCR_A CEU.CDBCR_A -#define CEUCBDSR_A CEU.CBDSR_A -#define CEUCFWCR CEU.CFWCR -#define CEUCLFCR_A CEU.CLFCR_A -#define CEUCDOCR_A CEU.CDOCR_A -#define CEUCEIER CEU.CEIER -#define CEUCETCR CEU.CETCR -#define CEUCSTSR CEU.CSTSR -#define CEUCDSSR CEU.CDSSR -#define CEUCDAYR2_A CEU.CDAYR2_A -#define CEUCDACR2_A CEU.CDACR2_A -#define CEUCDBYR2_A CEU.CDBYR2_A -#define CEUCDBCR2_A CEU.CDBCR2_A -#define CEUCAMOR_B CEU.CAMOR_B -#define CEUCAPWR_B CEU.CAPWR_B -#define CEUCFLCR_B CEU.CFLCR_B -#define CEUCFSZR_B CEU.CFSZR_B -#define CEUCDWDR_B CEU.CDWDR_B -#define CEUCDAYR_B CEU.CDAYR_B -#define CEUCDACR_B CEU.CDACR_B -#define CEUCDBYR_B CEU.CDBYR_B -#define CEUCDBCR_B CEU.CDBCR_B -#define CEUCBDSR_B CEU.CBDSR_B -#define CEUCLFCR_B CEU.CLFCR_B -#define CEUCDOCR_B CEU.CDOCR_B -#define CEUCDAYR2_B CEU.CDAYR2_B -#define CEUCDACR2_B CEU.CDACR2_B -#define CEUCDBYR2_B CEU.CDBYR2_B -#define CEUCDBCR2_B CEU.CDBCR2_B -#define CEUCAMOR_M CEU.CAMOR_M -#define CEUCAPWR_M CEU.CAPWR_M -#define CEUCFLCR_M CEU.CFLCR_M -#define CEUCFSZR_M CEU.CFSZR_M -#define CEUCDWDR_M CEU.CDWDR_M -#define CEUCDAYR_M CEU.CDAYR_M -#define CEUCDACR_M CEU.CDACR_M -#define CEUCDBYR_M CEU.CDBYR_M -#define CEUCDBCR_M CEU.CDBCR_M -#define CEUCBDSR_M CEU.CBDSR_M -#define CEUCLFCR_M CEU.CLFCR_M -#define CEUCDOCR_M CEU.CDOCR_M -#define CEUCDAYR2_M CEU.CDAYR2_M -#define CEUCDACR2_M CEU.CDACR2_M -#define CEUCDBYR2_M CEU.CDBYR2_M -#define CEUCDBCR2_M CEU.CDBCR2_M /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h similarity index 78% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h index 5fc9890ff54..6260ad010e8 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h @@ -18,20 +18,109 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : cpg_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef CPG_IODEFINE_H #define CPG_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_cpg -{ /* CPG */ +#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ + + +/* Start of channel array defines of CPG */ + +/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ +#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3) +#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ +#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ +#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ + + +/* Channel array defines of CPG_FROM_STBCR3_ARRAY */ +/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ +#define CPG_FROM_STBCR3_ARRAY_COUNT (10) +#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ + &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ +#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ +#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ +#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ +#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ +#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ +#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ +#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ +#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ +#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ + + +/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ +#define CPG_FROM_SYSCR1_ARRAY_COUNT (3) +#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ +#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ +#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ + +/* End of channel array defines of CPG */ + + +#define CPGFRQCR (CPG.FRQCR) +#define CPGFRQCR2 (CPG.FRQCR2) +#define CPGCPUSTS (CPG.CPUSTS) +#define CPGSTBCR1 (CPG.STBCR1) +#define CPGSTBCR2 (CPG.STBCR2) +#define CPGSTBREQ1 (CPG.STBREQ1) +#define CPGSTBREQ2 (CPG.STBREQ2) +#define CPGSTBACK1 (CPG.STBACK1) +#define CPGSTBACK2 (CPG.STBACK2) +#define CPGSYSCR1 (CPG.SYSCR1) +#define CPGSYSCR2 (CPG.SYSCR2) +#define CPGSYSCR3 (CPG.SYSCR3) +#define CPGSTBCR3 (CPG.STBCR3) +#define CPGSTBCR4 (CPG.STBCR4) +#define CPGSTBCR5 (CPG.STBCR5) +#define CPGSTBCR6 (CPG.STBCR6) +#define CPGSTBCR7 (CPG.STBCR7) +#define CPGSTBCR8 (CPG.STBCR8) +#define CPGSTBCR9 (CPG.STBCR9) +#define CPGSTBCR10 (CPG.STBCR10) +#define CPGSTBCR11 (CPG.STBCR11) +#define CPGSTBCR12 (CPG.STBCR12) +#define CPGSWRSTCR1 (CPG.SWRSTCR1) +#define CPGSWRSTCR2 (CPG.SWRSTCR2) +#define CPGSWRSTCR3 (CPG.SWRSTCR3) +#define CPGSTBCR13 (CPG.STBCR13) +#define CPGRRAMKP (CPG.RRAMKP) +#define CPGDSCTR (CPG.DSCTR) +#define CPGDSSSR (CPG.DSSSR) +#define CPGDSESR (CPG.DSESR) +#define CPGDSFR (CPG.DSFR) +#define CPGXTALCTR (CPG.XTALCTR) + + +typedef struct st_cpg +{ + /* CPG */ volatile uint16_t FRQCR; /* FRQCR */ volatile uint8_t dummy319[2]; /* */ volatile uint16_t FRQCR2; /* FRQCR2 */ @@ -50,71 +139,103 @@ struct st_cpg volatile uint8_t dummy326[3]; /* */ volatile uint8_t STBACK2; /* STBACK2 */ volatile uint8_t dummy327[955]; /* */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR1; /* SYSCR1 */ volatile uint8_t dummy328[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR2; /* SYSCR2 */ volatile uint8_t dummy329[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR3; /* SYSCR3 */ volatile uint8_t dummy3300[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ volatile uint8_t dummy3301[20]; /* */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR3; /* STBCR3 */ volatile uint8_t dummy331[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR4; /* STBCR4 */ volatile uint8_t dummy332[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR5; /* STBCR5 */ volatile uint8_t dummy333[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR6; /* STBCR6 */ volatile uint8_t dummy334[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR7; /* STBCR7 */ volatile uint8_t dummy335[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR8; /* STBCR8 */ volatile uint8_t dummy336[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR9; /* STBCR9 */ volatile uint8_t dummy337[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR10; /* STBCR10 */ volatile uint8_t dummy338[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR11; /* STBCR11 */ volatile uint8_t dummy339[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR12; /* STBCR12 */ volatile uint8_t dummy3400[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ volatile uint8_t dummy3401[24]; /* */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ volatile uint8_t dummy341[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ volatile uint8_t dummy342[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR3; /* SWRSTCR3 */ volatile uint8_t dummy3430[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ volatile uint8_t dummy3431[4]; /* */ volatile uint8_t STBCR13; /* STBCR13 */ @@ -128,112 +249,59 @@ struct st_cpg volatile uint16_t DSFR; /* DSFR */ volatile uint8_t dummy347[6]; /* */ volatile uint8_t XTALCTR; /* XTALCTR */ -}; +} r_io_cpg_t; -struct st_cpg_from_syscr1 +typedef struct st_cpg_from_syscr1 { + volatile uint8_t SYSCR1; /* SYSCR1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_syscr1_t; -struct st_cpg_from_stbcr3 +typedef struct st_cpg_from_stbcr3 { + volatile uint8_t STBCR3; /* STBCR3 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_stbcr3_t; -struct st_cpg_from_swrstcr1 +typedef struct st_cpg_from_swrstcr1 { + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_swrstcr1_t; -#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ +/* Channel array defines of CPG (2)*/ +#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */ +#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS +volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */ -/* Start of channnel array defines of CPG */ +#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */ +/* End of channel array defines of CPG (2)*/ -/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ -#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3 -#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ -#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ -#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ - - -/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */ -/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ -#define CPG_FROM_STBCR3_ARRAY_COUNT 10 -#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ - &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ -#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ -#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ -#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ -#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ -#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ -#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ -#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ -#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ -#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ - - -/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ -#define CPG_FROM_SYSCR1_ARRAY_COUNT 3 -#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ -#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ -#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ -/* End of channnel array defines of CPG */ - - -#define CPGFRQCR CPG.FRQCR -#define CPGFRQCR2 CPG.FRQCR2 -#define CPGCPUSTS CPG.CPUSTS -#define CPGSTBCR1 CPG.STBCR1 -#define CPGSTBCR2 CPG.STBCR2 -#define CPGSTBREQ1 CPG.STBREQ1 -#define CPGSTBREQ2 CPG.STBREQ2 -#define CPGSTBACK1 CPG.STBACK1 -#define CPGSTBACK2 CPG.STBACK2 -#define CPGSYSCR1 CPG.SYSCR1 -#define CPGSYSCR2 CPG.SYSCR2 -#define CPGSYSCR3 CPG.SYSCR3 -#define CPGSTBCR3 CPG.STBCR3 -#define CPGSTBCR4 CPG.STBCR4 -#define CPGSTBCR5 CPG.STBCR5 -#define CPGSTBCR6 CPG.STBCR6 -#define CPGSTBCR7 CPG.STBCR7 -#define CPGSTBCR8 CPG.STBCR8 -#define CPGSTBCR9 CPG.STBCR9 -#define CPGSTBCR10 CPG.STBCR10 -#define CPGSTBCR11 CPG.STBCR11 -#define CPGSTBCR12 CPG.STBCR12 -#define CPGSWRSTCR1 CPG.SWRSTCR1 -#define CPGSWRSTCR2 CPG.SWRSTCR2 -#define CPGSWRSTCR3 CPG.SWRSTCR3 -#define CPGSTBCR13 CPG.STBCR13 -#define CPGRRAMKP CPG.RRAMKP -#define CPGDSCTR CPG.DSCTR -#define CPGDSSSR CPG.DSSSR -#define CPGDSESR CPG.DSESR -#define CPGDSFR CPG.DSFR -#define CPGXTALCTR CPG.XTALCTR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h similarity index 63% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h index 8844fa2afb7..dd2abd5e75c 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h @@ -18,20 +18,67 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : disc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DISC_IODEFINE_H #define DISC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_disc -{ /* DISC */ +#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ +#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ + + +/* Start of channel array defines of DISC */ + +/* Channel array defines of DISC */ +/*(Sample) value = DISC[ channel ]->DOCMCR; */ +#define DISC_COUNT (2) +#define DISC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DISC0, &DISC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of DISC */ + + +#define DISC0DOCMCR (DISC0.DOCMCR) +#define DISC0DOCMSTR (DISC0.DOCMSTR) +#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR) +#define DISC0DOCMIENR (DISC0.DOCMIENR) +#define DISC0DOCMPMR (DISC0.DOCMPMR) +#define DISC0DOCMECRCR (DISC0.DOCMECRCR) +#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR) +#define DISC0DOCMSPXR (DISC0.DOCMSPXR) +#define DISC0DOCMSPYR (DISC0.DOCMSPYR) +#define DISC0DOCMSZXR (DISC0.DOCMSZXR) +#define DISC0DOCMSZYR (DISC0.DOCMSZYR) +#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR) +#define DISC1DOCMCR (DISC1.DOCMCR) +#define DISC1DOCMSTR (DISC1.DOCMSTR) +#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR) +#define DISC1DOCMIENR (DISC1.DOCMIENR) +#define DISC1DOCMPMR (DISC1.DOCMPMR) +#define DISC1DOCMECRCR (DISC1.DOCMECRCR) +#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR) +#define DISC1DOCMSPXR (DISC1.DOCMSPXR) +#define DISC1DOCMSPYR (DISC1.DOCMSPYR) +#define DISC1DOCMSZXR (DISC1.DOCMSZXR) +#define DISC1DOCMSZYR (DISC1.DOCMSZYR) +#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR) + + +typedef struct st_disc +{ + /* DISC */ volatile uint32_t DOCMCR; /* DOCMCR */ volatile uint32_t DOCMSTR; /* DOCMSTR */ volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */ @@ -45,49 +92,21 @@ struct st_disc volatile uint32_t DOCMSZXR; /* DOCMSZXR */ volatile uint32_t DOCMSZYR; /* DOCMSZYR */ volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */ -}; - - -#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ -#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ - +} r_io_disc_t; -/* Start of channnel array defines of DISC */ - -/* Channnel array defines of DISC */ -/*(Sample) value = DISC[ channel ]->DOCMCR; */ -#define DISC_COUNT 2 -#define DISC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DISC0, &DISC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of DISC */ +/* Channel array defines of DISC (2)*/ +#ifdef DECLARE_DISC_CHANNELS +volatile struct st_disc* DISC[ DISC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DISC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DISC_CHANNELS */ +/* End of channel array defines of DISC (2)*/ -#define DISC0DOCMCR DISC0.DOCMCR -#define DISC0DOCMSTR DISC0.DOCMSTR -#define DISC0DOCMCLSTR DISC0.DOCMCLSTR -#define DISC0DOCMIENR DISC0.DOCMIENR -#define DISC0DOCMPMR DISC0.DOCMPMR -#define DISC0DOCMECRCR DISC0.DOCMECRCR -#define DISC0DOCMCCRCR DISC0.DOCMCCRCR -#define DISC0DOCMSPXR DISC0.DOCMSPXR -#define DISC0DOCMSPYR DISC0.DOCMSPYR -#define DISC0DOCMSZXR DISC0.DOCMSZXR -#define DISC0DOCMSZYR DISC0.DOCMSZYR -#define DISC0DOCMCRCIR DISC0.DOCMCRCIR -#define DISC1DOCMCR DISC1.DOCMCR -#define DISC1DOCMSTR DISC1.DOCMSTR -#define DISC1DOCMCLSTR DISC1.DOCMCLSTR -#define DISC1DOCMIENR DISC1.DOCMIENR -#define DISC1DOCMPMR DISC1.DOCMPMR -#define DISC1DOCMECRCR DISC1.DOCMECRCR -#define DISC1DOCMCCRCR DISC1.DOCMCCRCR -#define DISC1DOCMSPXR DISC1.DOCMSPXR -#define DISC1DOCMSPYR DISC1.DOCMSPYR -#define DISC1DOCMSZXR DISC1.DOCMSZXR -#define DISC1DOCMSZYR DISC1.DOCMSZYR -#define DISC1DOCMCRCIR DISC1.DOCMCRCIR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h similarity index 73% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h index 0faf27fbe00..a6d6865f866 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h @@ -18,21 +18,373 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : dmac_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DMAC_IODEFINE_H #define DMAC_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_dmac -{ /* DMAC */ + + +/* Channel array defines of DMACmm */ +#define DMACmm_COUNT (8) +#define DMACmm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ +#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ +#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ +#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ +#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ +#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ +#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ +#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ + + +/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ +#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ + + +/* Start of channel array defines of DMAC */ + +/* Channel array defines of DMACn */ +/*(Sample) value = DMACn[ channel ]->N0SA_n; */ +#define DMACn_COUNT (16) +#define DMACn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ + &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */ +#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */ +#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */ +#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */ +#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */ +#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */ +#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */ +#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */ +#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */ +#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */ +#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */ +#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */ +#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */ +#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */ +#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */ +#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ + + +/* Channel array defines of DMACnn */ +/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ +#define DMACnn_COUNT (2) +#define DMACnn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC07, &DMAC815 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ +#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ + +/* End of channel array defines of DMAC */ + + +#define DMACN0SA_0 (DMAC.N0SA_0) +#define DMACN0DA_0 (DMAC.N0DA_0) +#define DMACN0TB_0 (DMAC.N0TB_0) +#define DMACN1SA_0 (DMAC.N1SA_0) +#define DMACN1DA_0 (DMAC.N1DA_0) +#define DMACN1TB_0 (DMAC.N1TB_0) +#define DMACCRSA_0 (DMAC.CRSA_0) +#define DMACCRDA_0 (DMAC.CRDA_0) +#define DMACCRTB_0 (DMAC.CRTB_0) +#define DMACCHSTAT_0 (DMAC.CHSTAT_0) +#define DMACCHCTRL_0 (DMAC.CHCTRL_0) +#define DMACCHCFG_0 (DMAC.CHCFG_0) +#define DMACCHITVL_0 (DMAC.CHITVL_0) +#define DMACCHEXT_0 (DMAC.CHEXT_0) +#define DMACNXLA_0 (DMAC.NXLA_0) +#define DMACCRLA_0 (DMAC.CRLA_0) +#define DMACN0SA_1 (DMAC.N0SA_1) +#define DMACN0DA_1 (DMAC.N0DA_1) +#define DMACN0TB_1 (DMAC.N0TB_1) +#define DMACN1SA_1 (DMAC.N1SA_1) +#define DMACN1DA_1 (DMAC.N1DA_1) +#define DMACN1TB_1 (DMAC.N1TB_1) +#define DMACCRSA_1 (DMAC.CRSA_1) +#define DMACCRDA_1 (DMAC.CRDA_1) +#define DMACCRTB_1 (DMAC.CRTB_1) +#define DMACCHSTAT_1 (DMAC.CHSTAT_1) +#define DMACCHCTRL_1 (DMAC.CHCTRL_1) +#define DMACCHCFG_1 (DMAC.CHCFG_1) +#define DMACCHITVL_1 (DMAC.CHITVL_1) +#define DMACCHEXT_1 (DMAC.CHEXT_1) +#define DMACNXLA_1 (DMAC.NXLA_1) +#define DMACCRLA_1 (DMAC.CRLA_1) +#define DMACN0SA_2 (DMAC.N0SA_2) +#define DMACN0DA_2 (DMAC.N0DA_2) +#define DMACN0TB_2 (DMAC.N0TB_2) +#define DMACN1SA_2 (DMAC.N1SA_2) +#define DMACN1DA_2 (DMAC.N1DA_2) +#define DMACN1TB_2 (DMAC.N1TB_2) +#define DMACCRSA_2 (DMAC.CRSA_2) +#define DMACCRDA_2 (DMAC.CRDA_2) +#define DMACCRTB_2 (DMAC.CRTB_2) +#define DMACCHSTAT_2 (DMAC.CHSTAT_2) +#define DMACCHCTRL_2 (DMAC.CHCTRL_2) +#define DMACCHCFG_2 (DMAC.CHCFG_2) +#define DMACCHITVL_2 (DMAC.CHITVL_2) +#define DMACCHEXT_2 (DMAC.CHEXT_2) +#define DMACNXLA_2 (DMAC.NXLA_2) +#define DMACCRLA_2 (DMAC.CRLA_2) +#define DMACN0SA_3 (DMAC.N0SA_3) +#define DMACN0DA_3 (DMAC.N0DA_3) +#define DMACN0TB_3 (DMAC.N0TB_3) +#define DMACN1SA_3 (DMAC.N1SA_3) +#define DMACN1DA_3 (DMAC.N1DA_3) +#define DMACN1TB_3 (DMAC.N1TB_3) +#define DMACCRSA_3 (DMAC.CRSA_3) +#define DMACCRDA_3 (DMAC.CRDA_3) +#define DMACCRTB_3 (DMAC.CRTB_3) +#define DMACCHSTAT_3 (DMAC.CHSTAT_3) +#define DMACCHCTRL_3 (DMAC.CHCTRL_3) +#define DMACCHCFG_3 (DMAC.CHCFG_3) +#define DMACCHITVL_3 (DMAC.CHITVL_3) +#define DMACCHEXT_3 (DMAC.CHEXT_3) +#define DMACNXLA_3 (DMAC.NXLA_3) +#define DMACCRLA_3 (DMAC.CRLA_3) +#define DMACN0SA_4 (DMAC.N0SA_4) +#define DMACN0DA_4 (DMAC.N0DA_4) +#define DMACN0TB_4 (DMAC.N0TB_4) +#define DMACN1SA_4 (DMAC.N1SA_4) +#define DMACN1DA_4 (DMAC.N1DA_4) +#define DMACN1TB_4 (DMAC.N1TB_4) +#define DMACCRSA_4 (DMAC.CRSA_4) +#define DMACCRDA_4 (DMAC.CRDA_4) +#define DMACCRTB_4 (DMAC.CRTB_4) +#define DMACCHSTAT_4 (DMAC.CHSTAT_4) +#define DMACCHCTRL_4 (DMAC.CHCTRL_4) +#define DMACCHCFG_4 (DMAC.CHCFG_4) +#define DMACCHITVL_4 (DMAC.CHITVL_4) +#define DMACCHEXT_4 (DMAC.CHEXT_4) +#define DMACNXLA_4 (DMAC.NXLA_4) +#define DMACCRLA_4 (DMAC.CRLA_4) +#define DMACN0SA_5 (DMAC.N0SA_5) +#define DMACN0DA_5 (DMAC.N0DA_5) +#define DMACN0TB_5 (DMAC.N0TB_5) +#define DMACN1SA_5 (DMAC.N1SA_5) +#define DMACN1DA_5 (DMAC.N1DA_5) +#define DMACN1TB_5 (DMAC.N1TB_5) +#define DMACCRSA_5 (DMAC.CRSA_5) +#define DMACCRDA_5 (DMAC.CRDA_5) +#define DMACCRTB_5 (DMAC.CRTB_5) +#define DMACCHSTAT_5 (DMAC.CHSTAT_5) +#define DMACCHCTRL_5 (DMAC.CHCTRL_5) +#define DMACCHCFG_5 (DMAC.CHCFG_5) +#define DMACCHITVL_5 (DMAC.CHITVL_5) +#define DMACCHEXT_5 (DMAC.CHEXT_5) +#define DMACNXLA_5 (DMAC.NXLA_5) +#define DMACCRLA_5 (DMAC.CRLA_5) +#define DMACN0SA_6 (DMAC.N0SA_6) +#define DMACN0DA_6 (DMAC.N0DA_6) +#define DMACN0TB_6 (DMAC.N0TB_6) +#define DMACN1SA_6 (DMAC.N1SA_6) +#define DMACN1DA_6 (DMAC.N1DA_6) +#define DMACN1TB_6 (DMAC.N1TB_6) +#define DMACCRSA_6 (DMAC.CRSA_6) +#define DMACCRDA_6 (DMAC.CRDA_6) +#define DMACCRTB_6 (DMAC.CRTB_6) +#define DMACCHSTAT_6 (DMAC.CHSTAT_6) +#define DMACCHCTRL_6 (DMAC.CHCTRL_6) +#define DMACCHCFG_6 (DMAC.CHCFG_6) +#define DMACCHITVL_6 (DMAC.CHITVL_6) +#define DMACCHEXT_6 (DMAC.CHEXT_6) +#define DMACNXLA_6 (DMAC.NXLA_6) +#define DMACCRLA_6 (DMAC.CRLA_6) +#define DMACN0SA_7 (DMAC.N0SA_7) +#define DMACN0DA_7 (DMAC.N0DA_7) +#define DMACN0TB_7 (DMAC.N0TB_7) +#define DMACN1SA_7 (DMAC.N1SA_7) +#define DMACN1DA_7 (DMAC.N1DA_7) +#define DMACN1TB_7 (DMAC.N1TB_7) +#define DMACCRSA_7 (DMAC.CRSA_7) +#define DMACCRDA_7 (DMAC.CRDA_7) +#define DMACCRTB_7 (DMAC.CRTB_7) +#define DMACCHSTAT_7 (DMAC.CHSTAT_7) +#define DMACCHCTRL_7 (DMAC.CHCTRL_7) +#define DMACCHCFG_7 (DMAC.CHCFG_7) +#define DMACCHITVL_7 (DMAC.CHITVL_7) +#define DMACCHEXT_7 (DMAC.CHEXT_7) +#define DMACNXLA_7 (DMAC.NXLA_7) +#define DMACCRLA_7 (DMAC.CRLA_7) +#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7) +#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7) +#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7) +#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7) +#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7) +#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7) +#define DMACN0SA_8 (DMAC.N0SA_8) +#define DMACN0DA_8 (DMAC.N0DA_8) +#define DMACN0TB_8 (DMAC.N0TB_8) +#define DMACN1SA_8 (DMAC.N1SA_8) +#define DMACN1DA_8 (DMAC.N1DA_8) +#define DMACN1TB_8 (DMAC.N1TB_8) +#define DMACCRSA_8 (DMAC.CRSA_8) +#define DMACCRDA_8 (DMAC.CRDA_8) +#define DMACCRTB_8 (DMAC.CRTB_8) +#define DMACCHSTAT_8 (DMAC.CHSTAT_8) +#define DMACCHCTRL_8 (DMAC.CHCTRL_8) +#define DMACCHCFG_8 (DMAC.CHCFG_8) +#define DMACCHITVL_8 (DMAC.CHITVL_8) +#define DMACCHEXT_8 (DMAC.CHEXT_8) +#define DMACNXLA_8 (DMAC.NXLA_8) +#define DMACCRLA_8 (DMAC.CRLA_8) +#define DMACN0SA_9 (DMAC.N0SA_9) +#define DMACN0DA_9 (DMAC.N0DA_9) +#define DMACN0TB_9 (DMAC.N0TB_9) +#define DMACN1SA_9 (DMAC.N1SA_9) +#define DMACN1DA_9 (DMAC.N1DA_9) +#define DMACN1TB_9 (DMAC.N1TB_9) +#define DMACCRSA_9 (DMAC.CRSA_9) +#define DMACCRDA_9 (DMAC.CRDA_9) +#define DMACCRTB_9 (DMAC.CRTB_9) +#define DMACCHSTAT_9 (DMAC.CHSTAT_9) +#define DMACCHCTRL_9 (DMAC.CHCTRL_9) +#define DMACCHCFG_9 (DMAC.CHCFG_9) +#define DMACCHITVL_9 (DMAC.CHITVL_9) +#define DMACCHEXT_9 (DMAC.CHEXT_9) +#define DMACNXLA_9 (DMAC.NXLA_9) +#define DMACCRLA_9 (DMAC.CRLA_9) +#define DMACN0SA_10 (DMAC.N0SA_10) +#define DMACN0DA_10 (DMAC.N0DA_10) +#define DMACN0TB_10 (DMAC.N0TB_10) +#define DMACN1SA_10 (DMAC.N1SA_10) +#define DMACN1DA_10 (DMAC.N1DA_10) +#define DMACN1TB_10 (DMAC.N1TB_10) +#define DMACCRSA_10 (DMAC.CRSA_10) +#define DMACCRDA_10 (DMAC.CRDA_10) +#define DMACCRTB_10 (DMAC.CRTB_10) +#define DMACCHSTAT_10 (DMAC.CHSTAT_10) +#define DMACCHCTRL_10 (DMAC.CHCTRL_10) +#define DMACCHCFG_10 (DMAC.CHCFG_10) +#define DMACCHITVL_10 (DMAC.CHITVL_10) +#define DMACCHEXT_10 (DMAC.CHEXT_10) +#define DMACNXLA_10 (DMAC.NXLA_10) +#define DMACCRLA_10 (DMAC.CRLA_10) +#define DMACN0SA_11 (DMAC.N0SA_11) +#define DMACN0DA_11 (DMAC.N0DA_11) +#define DMACN0TB_11 (DMAC.N0TB_11) +#define DMACN1SA_11 (DMAC.N1SA_11) +#define DMACN1DA_11 (DMAC.N1DA_11) +#define DMACN1TB_11 (DMAC.N1TB_11) +#define DMACCRSA_11 (DMAC.CRSA_11) +#define DMACCRDA_11 (DMAC.CRDA_11) +#define DMACCRTB_11 (DMAC.CRTB_11) +#define DMACCHSTAT_11 (DMAC.CHSTAT_11) +#define DMACCHCTRL_11 (DMAC.CHCTRL_11) +#define DMACCHCFG_11 (DMAC.CHCFG_11) +#define DMACCHITVL_11 (DMAC.CHITVL_11) +#define DMACCHEXT_11 (DMAC.CHEXT_11) +#define DMACNXLA_11 (DMAC.NXLA_11) +#define DMACCRLA_11 (DMAC.CRLA_11) +#define DMACN0SA_12 (DMAC.N0SA_12) +#define DMACN0DA_12 (DMAC.N0DA_12) +#define DMACN0TB_12 (DMAC.N0TB_12) +#define DMACN1SA_12 (DMAC.N1SA_12) +#define DMACN1DA_12 (DMAC.N1DA_12) +#define DMACN1TB_12 (DMAC.N1TB_12) +#define DMACCRSA_12 (DMAC.CRSA_12) +#define DMACCRDA_12 (DMAC.CRDA_12) +#define DMACCRTB_12 (DMAC.CRTB_12) +#define DMACCHSTAT_12 (DMAC.CHSTAT_12) +#define DMACCHCTRL_12 (DMAC.CHCTRL_12) +#define DMACCHCFG_12 (DMAC.CHCFG_12) +#define DMACCHITVL_12 (DMAC.CHITVL_12) +#define DMACCHEXT_12 (DMAC.CHEXT_12) +#define DMACNXLA_12 (DMAC.NXLA_12) +#define DMACCRLA_12 (DMAC.CRLA_12) +#define DMACN0SA_13 (DMAC.N0SA_13) +#define DMACN0DA_13 (DMAC.N0DA_13) +#define DMACN0TB_13 (DMAC.N0TB_13) +#define DMACN1SA_13 (DMAC.N1SA_13) +#define DMACN1DA_13 (DMAC.N1DA_13) +#define DMACN1TB_13 (DMAC.N1TB_13) +#define DMACCRSA_13 (DMAC.CRSA_13) +#define DMACCRDA_13 (DMAC.CRDA_13) +#define DMACCRTB_13 (DMAC.CRTB_13) +#define DMACCHSTAT_13 (DMAC.CHSTAT_13) +#define DMACCHCTRL_13 (DMAC.CHCTRL_13) +#define DMACCHCFG_13 (DMAC.CHCFG_13) +#define DMACCHITVL_13 (DMAC.CHITVL_13) +#define DMACCHEXT_13 (DMAC.CHEXT_13) +#define DMACNXLA_13 (DMAC.NXLA_13) +#define DMACCRLA_13 (DMAC.CRLA_13) +#define DMACN0SA_14 (DMAC.N0SA_14) +#define DMACN0DA_14 (DMAC.N0DA_14) +#define DMACN0TB_14 (DMAC.N0TB_14) +#define DMACN1SA_14 (DMAC.N1SA_14) +#define DMACN1DA_14 (DMAC.N1DA_14) +#define DMACN1TB_14 (DMAC.N1TB_14) +#define DMACCRSA_14 (DMAC.CRSA_14) +#define DMACCRDA_14 (DMAC.CRDA_14) +#define DMACCRTB_14 (DMAC.CRTB_14) +#define DMACCHSTAT_14 (DMAC.CHSTAT_14) +#define DMACCHCTRL_14 (DMAC.CHCTRL_14) +#define DMACCHCFG_14 (DMAC.CHCFG_14) +#define DMACCHITVL_14 (DMAC.CHITVL_14) +#define DMACCHEXT_14 (DMAC.CHEXT_14) +#define DMACNXLA_14 (DMAC.NXLA_14) +#define DMACCRLA_14 (DMAC.CRLA_14) +#define DMACN0SA_15 (DMAC.N0SA_15) +#define DMACN0DA_15 (DMAC.N0DA_15) +#define DMACN0TB_15 (DMAC.N0TB_15) +#define DMACN1SA_15 (DMAC.N1SA_15) +#define DMACN1DA_15 (DMAC.N1DA_15) +#define DMACN1TB_15 (DMAC.N1TB_15) +#define DMACCRSA_15 (DMAC.CRSA_15) +#define DMACCRDA_15 (DMAC.CRDA_15) +#define DMACCRTB_15 (DMAC.CRTB_15) +#define DMACCHSTAT_15 (DMAC.CHSTAT_15) +#define DMACCHCTRL_15 (DMAC.CHCTRL_15) +#define DMACCHCFG_15 (DMAC.CHCFG_15) +#define DMACCHITVL_15 (DMAC.CHITVL_15) +#define DMACCHEXT_15 (DMAC.CHEXT_15) +#define DMACNXLA_15 (DMAC.NXLA_15) +#define DMACCRLA_15 (DMAC.CRLA_15) +#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15) +#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15) +#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15) +#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15) +#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15) +#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15) +#define DMACDMARS0 (DMAC.DMARS0) +#define DMACDMARS1 (DMAC.DMARS1) +#define DMACDMARS2 (DMAC.DMARS2) +#define DMACDMARS3 (DMAC.DMARS3) +#define DMACDMARS4 (DMAC.DMARS4) +#define DMACDMARS5 (DMAC.DMARS5) +#define DMACDMARS6 (DMAC.DMARS6) +#define DMACDMARS7 (DMAC.DMARS7) + + +typedef struct st_dmars_mm +{ + + volatile uint32_t DMARS; /* DMARS */ +} r_io_dmars_mm_t; + + +typedef struct st_dmac +{ + /* DMAC */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_0; /* N0SA_0 */ volatile uint32_t N0DA_0; /* N0DA_0 */ @@ -50,7 +402,9 @@ struct st_dmac volatile uint32_t CHEXT_0; /* CHEXT_0 */ volatile uint32_t NXLA_0; /* NXLA_0 */ volatile uint32_t CRLA_0; /* CRLA_0 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_1; /* N0SA_1 */ volatile uint32_t N0DA_1; /* N0DA_1 */ @@ -68,7 +422,9 @@ struct st_dmac volatile uint32_t CHEXT_1; /* CHEXT_1 */ volatile uint32_t NXLA_1; /* NXLA_1 */ volatile uint32_t CRLA_1; /* CRLA_1 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_2; /* N0SA_2 */ volatile uint32_t N0DA_2; /* N0DA_2 */ @@ -86,7 +442,9 @@ struct st_dmac volatile uint32_t CHEXT_2; /* CHEXT_2 */ volatile uint32_t NXLA_2; /* NXLA_2 */ volatile uint32_t CRLA_2; /* CRLA_2 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_3; /* N0SA_3 */ volatile uint32_t N0DA_3; /* N0DA_3 */ @@ -104,7 +462,9 @@ struct st_dmac volatile uint32_t CHEXT_3; /* CHEXT_3 */ volatile uint32_t NXLA_3; /* NXLA_3 */ volatile uint32_t CRLA_3; /* CRLA_3 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_4; /* N0SA_4 */ volatile uint32_t N0DA_4; /* N0DA_4 */ @@ -122,7 +482,9 @@ struct st_dmac volatile uint32_t CHEXT_4; /* CHEXT_4 */ volatile uint32_t NXLA_4; /* NXLA_4 */ volatile uint32_t CRLA_4; /* CRLA_4 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_5; /* N0SA_5 */ volatile uint32_t N0DA_5; /* N0DA_5 */ @@ -140,7 +502,9 @@ struct st_dmac volatile uint32_t CHEXT_5; /* CHEXT_5 */ volatile uint32_t NXLA_5; /* NXLA_5 */ volatile uint32_t CRLA_5; /* CRLA_5 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_6; /* N0SA_6 */ volatile uint32_t N0DA_6; /* N0DA_6 */ @@ -158,7 +522,9 @@ struct st_dmac volatile uint32_t CHEXT_6; /* CHEXT_6 */ volatile uint32_t NXLA_6; /* NXLA_6 */ volatile uint32_t CRLA_6; /* CRLA_6 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_7; /* N0SA_7 */ volatile uint32_t N0DA_7; /* N0DA_7 */ @@ -176,8 +542,10 @@ struct st_dmac volatile uint32_t CHEXT_7; /* CHEXT_7 */ volatile uint32_t NXLA_7; /* NXLA_7 */ volatile uint32_t CRLA_7; /* CRLA_7 */ + /* end of struct st_dmac_n */ volatile uint8_t dummy187[256]; /* */ + /* start of struct st_dmaccommon_n */ volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ volatile uint8_t dummy188[12]; /* */ @@ -186,8 +554,10 @@ struct st_dmac volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ + /* end of struct st_dmaccommon_n */ volatile uint8_t dummy189[220]; /* */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_8; /* N0SA_8 */ volatile uint32_t N0DA_8; /* N0DA_8 */ @@ -205,7 +575,9 @@ struct st_dmac volatile uint32_t CHEXT_8; /* CHEXT_8 */ volatile uint32_t NXLA_8; /* NXLA_8 */ volatile uint32_t CRLA_8; /* CRLA_8 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_9; /* N0SA_9 */ volatile uint32_t N0DA_9; /* N0DA_9 */ @@ -223,7 +595,9 @@ struct st_dmac volatile uint32_t CHEXT_9; /* CHEXT_9 */ volatile uint32_t NXLA_9; /* NXLA_9 */ volatile uint32_t CRLA_9; /* CRLA_9 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_10; /* N0SA_10 */ volatile uint32_t N0DA_10; /* N0DA_10 */ @@ -241,7 +615,9 @@ struct st_dmac volatile uint32_t CHEXT_10; /* CHEXT_10 */ volatile uint32_t NXLA_10; /* NXLA_10 */ volatile uint32_t CRLA_10; /* CRLA_10 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_11; /* N0SA_11 */ volatile uint32_t N0DA_11; /* N0DA_11 */ @@ -259,7 +635,9 @@ struct st_dmac volatile uint32_t CHEXT_11; /* CHEXT_11 */ volatile uint32_t NXLA_11; /* NXLA_11 */ volatile uint32_t CRLA_11; /* CRLA_11 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_12; /* N0SA_12 */ volatile uint32_t N0DA_12; /* N0DA_12 */ @@ -277,7 +655,9 @@ struct st_dmac volatile uint32_t CHEXT_12; /* CHEXT_12 */ volatile uint32_t NXLA_12; /* NXLA_12 */ volatile uint32_t CRLA_12; /* CRLA_12 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_13; /* N0SA_13 */ volatile uint32_t N0DA_13; /* N0DA_13 */ @@ -295,7 +675,9 @@ struct st_dmac volatile uint32_t CHEXT_13; /* CHEXT_13 */ volatile uint32_t NXLA_13; /* NXLA_13 */ volatile uint32_t CRLA_13; /* CRLA_13 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_14; /* N0SA_14 */ volatile uint32_t N0DA_14; /* N0DA_14 */ @@ -313,7 +695,9 @@ struct st_dmac volatile uint32_t CHEXT_14; /* CHEXT_14 */ volatile uint32_t NXLA_14; /* NXLA_14 */ volatile uint32_t CRLA_14; /* CRLA_14 */ + /* end of struct st_dmac_n */ + /* start of struct st_dmac_n */ volatile uint32_t N0SA_15; /* N0SA_15 */ volatile uint32_t N0DA_15; /* N0DA_15 */ @@ -331,8 +715,10 @@ struct st_dmac volatile uint32_t CHEXT_15; /* CHEXT_15 */ volatile uint32_t NXLA_15; /* NXLA_15 */ volatile uint32_t CRLA_15; /* CRLA_15 */ + /* end of struct st_dmac_n */ volatile uint8_t dummy190[256]; /* */ + /* start of struct st_dmaccommon_n */ volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ volatile uint8_t dummy191[12]; /* */ @@ -341,6 +727,7 @@ struct st_dmac volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ + /* end of struct st_dmaccommon_n */ volatile uint8_t dummy192[350095580]; /* */ volatile uint32_t DMARS0; /* DMARS0 */ @@ -351,11 +738,12 @@ struct st_dmac volatile uint32_t DMARS5; /* DMARS5 */ volatile uint32_t DMARS6; /* DMARS6 */ volatile uint32_t DMARS7; /* DMARS7 */ -}; +} r_io_dmac_t; -struct st_dmaccommon_n +typedef struct st_dmaccommon_n { + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ volatile uint8_t dummy1[12]; /* */ volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ @@ -363,11 +751,12 @@ struct st_dmaccommon_n volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ -}; +} r_io_dmaccommon_n_t; -struct st_dmac_n +typedef struct st_dmac_n { + volatile uint32_t N0SA_n; /* N0SA_n */ volatile uint32_t N0DA_n; /* N0DA_n */ volatile uint32_t N0TB_n; /* N0TB_n */ @@ -384,350 +773,35 @@ struct st_dmac_n volatile uint32_t CHEXT_n; /* CHEXT_n */ volatile uint32_t NXLA_n; /* NXLA_n */ volatile uint32_t CRLA_n; /* CRLA_n */ -}; - - -#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ +} r_io_dmac_n_t; -/* Start of channnel array defines of DMAC */ - -/* Channnel array defines of DMACn */ -/*(Sample) value = DMACn[ channel ]->N0SA_n; */ -#define DMACn_COUNT 16 -#define DMACn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ - &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */ -#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */ -#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */ -#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */ -#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */ -#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */ -#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */ -#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */ -#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */ -#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */ -#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */ -#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */ -#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */ -#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */ -#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */ -#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ - +/* Channel array defines of DMAC (2)*/ +#ifdef DECLARE_DMACmm_CHANNELS +volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACmm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACmm_CHANNELS */ -/* Channnel array defines of DMACnn */ -/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ -#define DMACnn_COUNT 2 -#define DMACnn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC07, &DMAC815 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ -#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ +#ifdef DECLARE_DMACn_CHANNELS +volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACn_CHANNELS */ +#ifdef DECLARE_DMACnn_CHANNELS +volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACnn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACnn_CHANNELS */ +/* End of channel array defines of DMAC (2)*/ -/* Channnel array defines of DMACmm */ -/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ -struct st_dmars_mm -{ - uint32_t DMARS; /* DMARS */ -}; -#define DMACmm_COUNT 8 -#define DMACmm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ -#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ -#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ -#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ -#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ -#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ -#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ -#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ -/* End of channnel array defines of DMAC */ - - -#define DMACN0SA_0 DMAC.N0SA_0 -#define DMACN0DA_0 DMAC.N0DA_0 -#define DMACN0TB_0 DMAC.N0TB_0 -#define DMACN1SA_0 DMAC.N1SA_0 -#define DMACN1DA_0 DMAC.N1DA_0 -#define DMACN1TB_0 DMAC.N1TB_0 -#define DMACCRSA_0 DMAC.CRSA_0 -#define DMACCRDA_0 DMAC.CRDA_0 -#define DMACCRTB_0 DMAC.CRTB_0 -#define DMACCHSTAT_0 DMAC.CHSTAT_0 -#define DMACCHCTRL_0 DMAC.CHCTRL_0 -#define DMACCHCFG_0 DMAC.CHCFG_0 -#define DMACCHITVL_0 DMAC.CHITVL_0 -#define DMACCHEXT_0 DMAC.CHEXT_0 -#define DMACNXLA_0 DMAC.NXLA_0 -#define DMACCRLA_0 DMAC.CRLA_0 -#define DMACN0SA_1 DMAC.N0SA_1 -#define DMACN0DA_1 DMAC.N0DA_1 -#define DMACN0TB_1 DMAC.N0TB_1 -#define DMACN1SA_1 DMAC.N1SA_1 -#define DMACN1DA_1 DMAC.N1DA_1 -#define DMACN1TB_1 DMAC.N1TB_1 -#define DMACCRSA_1 DMAC.CRSA_1 -#define DMACCRDA_1 DMAC.CRDA_1 -#define DMACCRTB_1 DMAC.CRTB_1 -#define DMACCHSTAT_1 DMAC.CHSTAT_1 -#define DMACCHCTRL_1 DMAC.CHCTRL_1 -#define DMACCHCFG_1 DMAC.CHCFG_1 -#define DMACCHITVL_1 DMAC.CHITVL_1 -#define DMACCHEXT_1 DMAC.CHEXT_1 -#define DMACNXLA_1 DMAC.NXLA_1 -#define DMACCRLA_1 DMAC.CRLA_1 -#define DMACN0SA_2 DMAC.N0SA_2 -#define DMACN0DA_2 DMAC.N0DA_2 -#define DMACN0TB_2 DMAC.N0TB_2 -#define DMACN1SA_2 DMAC.N1SA_2 -#define DMACN1DA_2 DMAC.N1DA_2 -#define DMACN1TB_2 DMAC.N1TB_2 -#define DMACCRSA_2 DMAC.CRSA_2 -#define DMACCRDA_2 DMAC.CRDA_2 -#define DMACCRTB_2 DMAC.CRTB_2 -#define DMACCHSTAT_2 DMAC.CHSTAT_2 -#define DMACCHCTRL_2 DMAC.CHCTRL_2 -#define DMACCHCFG_2 DMAC.CHCFG_2 -#define DMACCHITVL_2 DMAC.CHITVL_2 -#define DMACCHEXT_2 DMAC.CHEXT_2 -#define DMACNXLA_2 DMAC.NXLA_2 -#define DMACCRLA_2 DMAC.CRLA_2 -#define DMACN0SA_3 DMAC.N0SA_3 -#define DMACN0DA_3 DMAC.N0DA_3 -#define DMACN0TB_3 DMAC.N0TB_3 -#define DMACN1SA_3 DMAC.N1SA_3 -#define DMACN1DA_3 DMAC.N1DA_3 -#define DMACN1TB_3 DMAC.N1TB_3 -#define DMACCRSA_3 DMAC.CRSA_3 -#define DMACCRDA_3 DMAC.CRDA_3 -#define DMACCRTB_3 DMAC.CRTB_3 -#define DMACCHSTAT_3 DMAC.CHSTAT_3 -#define DMACCHCTRL_3 DMAC.CHCTRL_3 -#define DMACCHCFG_3 DMAC.CHCFG_3 -#define DMACCHITVL_3 DMAC.CHITVL_3 -#define DMACCHEXT_3 DMAC.CHEXT_3 -#define DMACNXLA_3 DMAC.NXLA_3 -#define DMACCRLA_3 DMAC.CRLA_3 -#define DMACN0SA_4 DMAC.N0SA_4 -#define DMACN0DA_4 DMAC.N0DA_4 -#define DMACN0TB_4 DMAC.N0TB_4 -#define DMACN1SA_4 DMAC.N1SA_4 -#define DMACN1DA_4 DMAC.N1DA_4 -#define DMACN1TB_4 DMAC.N1TB_4 -#define DMACCRSA_4 DMAC.CRSA_4 -#define DMACCRDA_4 DMAC.CRDA_4 -#define DMACCRTB_4 DMAC.CRTB_4 -#define DMACCHSTAT_4 DMAC.CHSTAT_4 -#define DMACCHCTRL_4 DMAC.CHCTRL_4 -#define DMACCHCFG_4 DMAC.CHCFG_4 -#define DMACCHITVL_4 DMAC.CHITVL_4 -#define DMACCHEXT_4 DMAC.CHEXT_4 -#define DMACNXLA_4 DMAC.NXLA_4 -#define DMACCRLA_4 DMAC.CRLA_4 -#define DMACN0SA_5 DMAC.N0SA_5 -#define DMACN0DA_5 DMAC.N0DA_5 -#define DMACN0TB_5 DMAC.N0TB_5 -#define DMACN1SA_5 DMAC.N1SA_5 -#define DMACN1DA_5 DMAC.N1DA_5 -#define DMACN1TB_5 DMAC.N1TB_5 -#define DMACCRSA_5 DMAC.CRSA_5 -#define DMACCRDA_5 DMAC.CRDA_5 -#define DMACCRTB_5 DMAC.CRTB_5 -#define DMACCHSTAT_5 DMAC.CHSTAT_5 -#define DMACCHCTRL_5 DMAC.CHCTRL_5 -#define DMACCHCFG_5 DMAC.CHCFG_5 -#define DMACCHITVL_5 DMAC.CHITVL_5 -#define DMACCHEXT_5 DMAC.CHEXT_5 -#define DMACNXLA_5 DMAC.NXLA_5 -#define DMACCRLA_5 DMAC.CRLA_5 -#define DMACN0SA_6 DMAC.N0SA_6 -#define DMACN0DA_6 DMAC.N0DA_6 -#define DMACN0TB_6 DMAC.N0TB_6 -#define DMACN1SA_6 DMAC.N1SA_6 -#define DMACN1DA_6 DMAC.N1DA_6 -#define DMACN1TB_6 DMAC.N1TB_6 -#define DMACCRSA_6 DMAC.CRSA_6 -#define DMACCRDA_6 DMAC.CRDA_6 -#define DMACCRTB_6 DMAC.CRTB_6 -#define DMACCHSTAT_6 DMAC.CHSTAT_6 -#define DMACCHCTRL_6 DMAC.CHCTRL_6 -#define DMACCHCFG_6 DMAC.CHCFG_6 -#define DMACCHITVL_6 DMAC.CHITVL_6 -#define DMACCHEXT_6 DMAC.CHEXT_6 -#define DMACNXLA_6 DMAC.NXLA_6 -#define DMACCRLA_6 DMAC.CRLA_6 -#define DMACN0SA_7 DMAC.N0SA_7 -#define DMACN0DA_7 DMAC.N0DA_7 -#define DMACN0TB_7 DMAC.N0TB_7 -#define DMACN1SA_7 DMAC.N1SA_7 -#define DMACN1DA_7 DMAC.N1DA_7 -#define DMACN1TB_7 DMAC.N1TB_7 -#define DMACCRSA_7 DMAC.CRSA_7 -#define DMACCRDA_7 DMAC.CRDA_7 -#define DMACCRTB_7 DMAC.CRTB_7 -#define DMACCHSTAT_7 DMAC.CHSTAT_7 -#define DMACCHCTRL_7 DMAC.CHCTRL_7 -#define DMACCHCFG_7 DMAC.CHCFG_7 -#define DMACCHITVL_7 DMAC.CHITVL_7 -#define DMACCHEXT_7 DMAC.CHEXT_7 -#define DMACNXLA_7 DMAC.NXLA_7 -#define DMACCRLA_7 DMAC.CRLA_7 -#define DMACDCTRL_0_7 DMAC.DCTRL_0_7 -#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7 -#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7 -#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7 -#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7 -#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7 -#define DMACN0SA_8 DMAC.N0SA_8 -#define DMACN0DA_8 DMAC.N0DA_8 -#define DMACN0TB_8 DMAC.N0TB_8 -#define DMACN1SA_8 DMAC.N1SA_8 -#define DMACN1DA_8 DMAC.N1DA_8 -#define DMACN1TB_8 DMAC.N1TB_8 -#define DMACCRSA_8 DMAC.CRSA_8 -#define DMACCRDA_8 DMAC.CRDA_8 -#define DMACCRTB_8 DMAC.CRTB_8 -#define DMACCHSTAT_8 DMAC.CHSTAT_8 -#define DMACCHCTRL_8 DMAC.CHCTRL_8 -#define DMACCHCFG_8 DMAC.CHCFG_8 -#define DMACCHITVL_8 DMAC.CHITVL_8 -#define DMACCHEXT_8 DMAC.CHEXT_8 -#define DMACNXLA_8 DMAC.NXLA_8 -#define DMACCRLA_8 DMAC.CRLA_8 -#define DMACN0SA_9 DMAC.N0SA_9 -#define DMACN0DA_9 DMAC.N0DA_9 -#define DMACN0TB_9 DMAC.N0TB_9 -#define DMACN1SA_9 DMAC.N1SA_9 -#define DMACN1DA_9 DMAC.N1DA_9 -#define DMACN1TB_9 DMAC.N1TB_9 -#define DMACCRSA_9 DMAC.CRSA_9 -#define DMACCRDA_9 DMAC.CRDA_9 -#define DMACCRTB_9 DMAC.CRTB_9 -#define DMACCHSTAT_9 DMAC.CHSTAT_9 -#define DMACCHCTRL_9 DMAC.CHCTRL_9 -#define DMACCHCFG_9 DMAC.CHCFG_9 -#define DMACCHITVL_9 DMAC.CHITVL_9 -#define DMACCHEXT_9 DMAC.CHEXT_9 -#define DMACNXLA_9 DMAC.NXLA_9 -#define DMACCRLA_9 DMAC.CRLA_9 -#define DMACN0SA_10 DMAC.N0SA_10 -#define DMACN0DA_10 DMAC.N0DA_10 -#define DMACN0TB_10 DMAC.N0TB_10 -#define DMACN1SA_10 DMAC.N1SA_10 -#define DMACN1DA_10 DMAC.N1DA_10 -#define DMACN1TB_10 DMAC.N1TB_10 -#define DMACCRSA_10 DMAC.CRSA_10 -#define DMACCRDA_10 DMAC.CRDA_10 -#define DMACCRTB_10 DMAC.CRTB_10 -#define DMACCHSTAT_10 DMAC.CHSTAT_10 -#define DMACCHCTRL_10 DMAC.CHCTRL_10 -#define DMACCHCFG_10 DMAC.CHCFG_10 -#define DMACCHITVL_10 DMAC.CHITVL_10 -#define DMACCHEXT_10 DMAC.CHEXT_10 -#define DMACNXLA_10 DMAC.NXLA_10 -#define DMACCRLA_10 DMAC.CRLA_10 -#define DMACN0SA_11 DMAC.N0SA_11 -#define DMACN0DA_11 DMAC.N0DA_11 -#define DMACN0TB_11 DMAC.N0TB_11 -#define DMACN1SA_11 DMAC.N1SA_11 -#define DMACN1DA_11 DMAC.N1DA_11 -#define DMACN1TB_11 DMAC.N1TB_11 -#define DMACCRSA_11 DMAC.CRSA_11 -#define DMACCRDA_11 DMAC.CRDA_11 -#define DMACCRTB_11 DMAC.CRTB_11 -#define DMACCHSTAT_11 DMAC.CHSTAT_11 -#define DMACCHCTRL_11 DMAC.CHCTRL_11 -#define DMACCHCFG_11 DMAC.CHCFG_11 -#define DMACCHITVL_11 DMAC.CHITVL_11 -#define DMACCHEXT_11 DMAC.CHEXT_11 -#define DMACNXLA_11 DMAC.NXLA_11 -#define DMACCRLA_11 DMAC.CRLA_11 -#define DMACN0SA_12 DMAC.N0SA_12 -#define DMACN0DA_12 DMAC.N0DA_12 -#define DMACN0TB_12 DMAC.N0TB_12 -#define DMACN1SA_12 DMAC.N1SA_12 -#define DMACN1DA_12 DMAC.N1DA_12 -#define DMACN1TB_12 DMAC.N1TB_12 -#define DMACCRSA_12 DMAC.CRSA_12 -#define DMACCRDA_12 DMAC.CRDA_12 -#define DMACCRTB_12 DMAC.CRTB_12 -#define DMACCHSTAT_12 DMAC.CHSTAT_12 -#define DMACCHCTRL_12 DMAC.CHCTRL_12 -#define DMACCHCFG_12 DMAC.CHCFG_12 -#define DMACCHITVL_12 DMAC.CHITVL_12 -#define DMACCHEXT_12 DMAC.CHEXT_12 -#define DMACNXLA_12 DMAC.NXLA_12 -#define DMACCRLA_12 DMAC.CRLA_12 -#define DMACN0SA_13 DMAC.N0SA_13 -#define DMACN0DA_13 DMAC.N0DA_13 -#define DMACN0TB_13 DMAC.N0TB_13 -#define DMACN1SA_13 DMAC.N1SA_13 -#define DMACN1DA_13 DMAC.N1DA_13 -#define DMACN1TB_13 DMAC.N1TB_13 -#define DMACCRSA_13 DMAC.CRSA_13 -#define DMACCRDA_13 DMAC.CRDA_13 -#define DMACCRTB_13 DMAC.CRTB_13 -#define DMACCHSTAT_13 DMAC.CHSTAT_13 -#define DMACCHCTRL_13 DMAC.CHCTRL_13 -#define DMACCHCFG_13 DMAC.CHCFG_13 -#define DMACCHITVL_13 DMAC.CHITVL_13 -#define DMACCHEXT_13 DMAC.CHEXT_13 -#define DMACNXLA_13 DMAC.NXLA_13 -#define DMACCRLA_13 DMAC.CRLA_13 -#define DMACN0SA_14 DMAC.N0SA_14 -#define DMACN0DA_14 DMAC.N0DA_14 -#define DMACN0TB_14 DMAC.N0TB_14 -#define DMACN1SA_14 DMAC.N1SA_14 -#define DMACN1DA_14 DMAC.N1DA_14 -#define DMACN1TB_14 DMAC.N1TB_14 -#define DMACCRSA_14 DMAC.CRSA_14 -#define DMACCRDA_14 DMAC.CRDA_14 -#define DMACCRTB_14 DMAC.CRTB_14 -#define DMACCHSTAT_14 DMAC.CHSTAT_14 -#define DMACCHCTRL_14 DMAC.CHCTRL_14 -#define DMACCHCFG_14 DMAC.CHCFG_14 -#define DMACCHITVL_14 DMAC.CHITVL_14 -#define DMACCHEXT_14 DMAC.CHEXT_14 -#define DMACNXLA_14 DMAC.NXLA_14 -#define DMACCRLA_14 DMAC.CRLA_14 -#define DMACN0SA_15 DMAC.N0SA_15 -#define DMACN0DA_15 DMAC.N0DA_15 -#define DMACN0TB_15 DMAC.N0TB_15 -#define DMACN1SA_15 DMAC.N1SA_15 -#define DMACN1DA_15 DMAC.N1DA_15 -#define DMACN1TB_15 DMAC.N1TB_15 -#define DMACCRSA_15 DMAC.CRSA_15 -#define DMACCRDA_15 DMAC.CRDA_15 -#define DMACCRTB_15 DMAC.CRTB_15 -#define DMACCHSTAT_15 DMAC.CHSTAT_15 -#define DMACCHCTRL_15 DMAC.CHCTRL_15 -#define DMACCHCFG_15 DMAC.CHCFG_15 -#define DMACCHITVL_15 DMAC.CHITVL_15 -#define DMACCHEXT_15 DMAC.CHEXT_15 -#define DMACNXLA_15 DMAC.NXLA_15 -#define DMACCRLA_15 DMAC.CRLA_15 -#define DMACDCTRL_8_15 DMAC.DCTRL_8_15 -#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15 -#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15 -#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15 -#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15 -#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15 -#define DMACDMARS0 DMAC.DMARS0 -#define DMACDMARS1 DMAC.DMARS1 -#define DMACDMARS2 DMAC.DMARS2 -#define DMACDMARS3 DMAC.DMARS3 -#define DMACDMARS4 DMAC.DMARS4 -#define DMACDMARS5 DMAC.DMARS5 -#define DMACDMARS6 DMAC.DMARS6 -#define DMACDMARS7 DMAC.DMARS7 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h similarity index 56% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h index 6c28acb009d..54bd656227e 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h @@ -18,40 +18,289 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : dvdec_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DVDEC_IODEFINE_H #define DVDEC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_dvdec -{ /* DVDEC */ +#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ +#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ + + +/* Start of channel array defines of DVDEC */ + +/* Channel array defines of DVDEC */ +/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ +#define DVDEC_COUNT (2) +#define DVDEC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DVDEC0, &DVDEC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of DVDEC */ + + +#define ADCCR1_1 (DVDEC1.ADCCR1) +#define TGCR1_1 (DVDEC1.TGCR1) +#define TGCR2_1 (DVDEC1.TGCR2) +#define TGCR3_1 (DVDEC1.TGCR3) +#define SYNSCR1_1 (DVDEC1.SYNSCR1) +#define SYNSCR2_1 (DVDEC1.SYNSCR2) +#define SYNSCR3_1 (DVDEC1.SYNSCR3) +#define SYNSCR4_1 (DVDEC1.SYNSCR4) +#define SYNSCR5_1 (DVDEC1.SYNSCR5) +#define HAFCCR1_1 (DVDEC1.HAFCCR1) +#define HAFCCR2_1 (DVDEC1.HAFCCR2) +#define HAFCCR3_1 (DVDEC1.HAFCCR3) +#define VCDWCR1_1 (DVDEC1.VCDWCR1) +#define DCPCR1_1 (DVDEC1.DCPCR1) +#define DCPCR2_1 (DVDEC1.DCPCR2) +#define DCPCR3_1 (DVDEC1.DCPCR3) +#define DCPCR4_1 (DVDEC1.DCPCR4) +#define DCPCR5_1 (DVDEC1.DCPCR5) +#define DCPCR6_1 (DVDEC1.DCPCR6) +#define DCPCR7_1 (DVDEC1.DCPCR7) +#define DCPCR8_1 (DVDEC1.DCPCR8) +#define NSDCR_1 (DVDEC1.NSDCR) +#define BTLCR_1 (DVDEC1.BTLCR) +#define BTGPCR_1 (DVDEC1.BTGPCR) +#define ACCCR1_1 (DVDEC1.ACCCR1) +#define ACCCR2_1 (DVDEC1.ACCCR2) +#define ACCCR3_1 (DVDEC1.ACCCR3) +#define TINTCR_1 (DVDEC1.TINTCR) +#define YCDCR_1 (DVDEC1.YCDCR) +#define AGCCR1_1 (DVDEC1.AGCCR1) +#define AGCCR2_1 (DVDEC1.AGCCR2) +#define PKLIMITCR_1 (DVDEC1.PKLIMITCR) +#define RGORCR1_1 (DVDEC1.RGORCR1) +#define RGORCR2_1 (DVDEC1.RGORCR2) +#define RGORCR3_1 (DVDEC1.RGORCR3) +#define RGORCR4_1 (DVDEC1.RGORCR4) +#define RGORCR5_1 (DVDEC1.RGORCR5) +#define RGORCR6_1 (DVDEC1.RGORCR6) +#define RGORCR7_1 (DVDEC1.RGORCR7) +#define AFCPFCR_1 (DVDEC1.AFCPFCR) +#define RUPDCR_1 (DVDEC1.RUPDCR) +#define VSYNCSR_1 (DVDEC1.VSYNCSR) +#define HSYNCSR_1 (DVDEC1.HSYNCSR) +#define DCPSR1_1 (DVDEC1.DCPSR1) +#define DCPSR2_1 (DVDEC1.DCPSR2) +#define NSDSR_1 (DVDEC1.NSDSR) +#define CROMASR1_1 (DVDEC1.CROMASR1) +#define CROMASR2_1 (DVDEC1.CROMASR2) +#define SYNCSSR_1 (DVDEC1.SYNCSSR) +#define AGCCSR1_1 (DVDEC1.AGCCSR1) +#define AGCCSR2_1 (DVDEC1.AGCCSR2) +#define YCSCR3_1 (DVDEC1.YCSCR3) +#define YCSCR4_1 (DVDEC1.YCSCR4) +#define YCSCR5_1 (DVDEC1.YCSCR5) +#define YCSCR6_1 (DVDEC1.YCSCR6) +#define YCSCR7_1 (DVDEC1.YCSCR7) +#define YCSCR8_1 (DVDEC1.YCSCR8) +#define YCSCR9_1 (DVDEC1.YCSCR9) +#define YCSCR11_1 (DVDEC1.YCSCR11) +#define YCSCR12_1 (DVDEC1.YCSCR12) +#define DCPCR9_1 (DVDEC1.DCPCR9) +#define YCTWA_F0_1 (DVDEC1.YCTWA_F0) +#define YCTWA_F1_1 (DVDEC1.YCTWA_F1) +#define YCTWA_F2_1 (DVDEC1.YCTWA_F2) +#define YCTWA_F3_1 (DVDEC1.YCTWA_F3) +#define YCTWA_F4_1 (DVDEC1.YCTWA_F4) +#define YCTWA_F5_1 (DVDEC1.YCTWA_F5) +#define YCTWA_F6_1 (DVDEC1.YCTWA_F6) +#define YCTWA_F7_1 (DVDEC1.YCTWA_F7) +#define YCTWA_F8_1 (DVDEC1.YCTWA_F8) +#define YCTWB_F0_1 (DVDEC1.YCTWB_F0) +#define YCTWB_F1_1 (DVDEC1.YCTWB_F1) +#define YCTWB_F2_1 (DVDEC1.YCTWB_F2) +#define YCTWB_F3_1 (DVDEC1.YCTWB_F3) +#define YCTWB_F4_1 (DVDEC1.YCTWB_F4) +#define YCTWB_F5_1 (DVDEC1.YCTWB_F5) +#define YCTWB_F6_1 (DVDEC1.YCTWB_F6) +#define YCTWB_F7_1 (DVDEC1.YCTWB_F7) +#define YCTWB_F8_1 (DVDEC1.YCTWB_F8) +#define YCTNA_F0_1 (DVDEC1.YCTNA_F0) +#define YCTNA_F1_1 (DVDEC1.YCTNA_F1) +#define YCTNA_F2_1 (DVDEC1.YCTNA_F2) +#define YCTNA_F3_1 (DVDEC1.YCTNA_F3) +#define YCTNA_F4_1 (DVDEC1.YCTNA_F4) +#define YCTNA_F5_1 (DVDEC1.YCTNA_F5) +#define YCTNA_F6_1 (DVDEC1.YCTNA_F6) +#define YCTNA_F7_1 (DVDEC1.YCTNA_F7) +#define YCTNA_F8_1 (DVDEC1.YCTNA_F8) +#define YCTNB_F0_1 (DVDEC1.YCTNB_F0) +#define YCTNB_F1_1 (DVDEC1.YCTNB_F1) +#define YCTNB_F2_1 (DVDEC1.YCTNB_F2) +#define YCTNB_F3_1 (DVDEC1.YCTNB_F3) +#define YCTNB_F4_1 (DVDEC1.YCTNB_F4) +#define YCTNB_F5_1 (DVDEC1.YCTNB_F5) +#define YCTNB_F6_1 (DVDEC1.YCTNB_F6) +#define YCTNB_F7_1 (DVDEC1.YCTNB_F7) +#define YCTNB_F8_1 (DVDEC1.YCTNB_F8) +#define YGAINCR_1 (DVDEC1.YGAINCR) +#define CBGAINCR_1 (DVDEC1.CBGAINCR) +#define CRGAINCR_1 (DVDEC1.CRGAINCR) +#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE) +#define PGACR_1 (DVDEC1.PGACR) +#define ADCCR2_1 (DVDEC1.ADCCR2) +#define ADCCR1_0 (DVDEC0.ADCCR1) +#define TGCR1_0 (DVDEC0.TGCR1) +#define TGCR2_0 (DVDEC0.TGCR2) +#define TGCR3_0 (DVDEC0.TGCR3) +#define SYNSCR1_0 (DVDEC0.SYNSCR1) +#define SYNSCR2_0 (DVDEC0.SYNSCR2) +#define SYNSCR3_0 (DVDEC0.SYNSCR3) +#define SYNSCR4_0 (DVDEC0.SYNSCR4) +#define SYNSCR5_0 (DVDEC0.SYNSCR5) +#define HAFCCR1_0 (DVDEC0.HAFCCR1) +#define HAFCCR2_0 (DVDEC0.HAFCCR2) +#define HAFCCR3_0 (DVDEC0.HAFCCR3) +#define VCDWCR1_0 (DVDEC0.VCDWCR1) +#define DCPCR1_0 (DVDEC0.DCPCR1) +#define DCPCR2_0 (DVDEC0.DCPCR2) +#define DCPCR3_0 (DVDEC0.DCPCR3) +#define DCPCR4_0 (DVDEC0.DCPCR4) +#define DCPCR5_0 (DVDEC0.DCPCR5) +#define DCPCR6_0 (DVDEC0.DCPCR6) +#define DCPCR7_0 (DVDEC0.DCPCR7) +#define DCPCR8_0 (DVDEC0.DCPCR8) +#define NSDCR_0 (DVDEC0.NSDCR) +#define BTLCR_0 (DVDEC0.BTLCR) +#define BTGPCR_0 (DVDEC0.BTGPCR) +#define ACCCR1_0 (DVDEC0.ACCCR1) +#define ACCCR2_0 (DVDEC0.ACCCR2) +#define ACCCR3_0 (DVDEC0.ACCCR3) +#define TINTCR_0 (DVDEC0.TINTCR) +#define YCDCR_0 (DVDEC0.YCDCR) +#define AGCCR1_0 (DVDEC0.AGCCR1) +#define AGCCR2_0 (DVDEC0.AGCCR2) +#define PKLIMITCR_0 (DVDEC0.PKLIMITCR) +#define RGORCR1_0 (DVDEC0.RGORCR1) +#define RGORCR2_0 (DVDEC0.RGORCR2) +#define RGORCR3_0 (DVDEC0.RGORCR3) +#define RGORCR4_0 (DVDEC0.RGORCR4) +#define RGORCR5_0 (DVDEC0.RGORCR5) +#define RGORCR6_0 (DVDEC0.RGORCR6) +#define RGORCR7_0 (DVDEC0.RGORCR7) +#define AFCPFCR_0 (DVDEC0.AFCPFCR) +#define RUPDCR_0 (DVDEC0.RUPDCR) +#define VSYNCSR_0 (DVDEC0.VSYNCSR) +#define HSYNCSR_0 (DVDEC0.HSYNCSR) +#define DCPSR1_0 (DVDEC0.DCPSR1) +#define DCPSR2_0 (DVDEC0.DCPSR2) +#define NSDSR_0 (DVDEC0.NSDSR) +#define CROMASR1_0 (DVDEC0.CROMASR1) +#define CROMASR2_0 (DVDEC0.CROMASR2) +#define SYNCSSR_0 (DVDEC0.SYNCSSR) +#define AGCCSR1_0 (DVDEC0.AGCCSR1) +#define AGCCSR2_0 (DVDEC0.AGCCSR2) +#define YCSCR3_0 (DVDEC0.YCSCR3) +#define YCSCR4_0 (DVDEC0.YCSCR4) +#define YCSCR5_0 (DVDEC0.YCSCR5) +#define YCSCR6_0 (DVDEC0.YCSCR6) +#define YCSCR7_0 (DVDEC0.YCSCR7) +#define YCSCR8_0 (DVDEC0.YCSCR8) +#define YCSCR9_0 (DVDEC0.YCSCR9) +#define YCSCR11_0 (DVDEC0.YCSCR11) +#define YCSCR12_0 (DVDEC0.YCSCR12) +#define DCPCR9_0 (DVDEC0.DCPCR9) +#define YCTWA_F0_0 (DVDEC0.YCTWA_F0) +#define YCTWA_F1_0 (DVDEC0.YCTWA_F1) +#define YCTWA_F2_0 (DVDEC0.YCTWA_F2) +#define YCTWA_F3_0 (DVDEC0.YCTWA_F3) +#define YCTWA_F4_0 (DVDEC0.YCTWA_F4) +#define YCTWA_F5_0 (DVDEC0.YCTWA_F5) +#define YCTWA_F6_0 (DVDEC0.YCTWA_F6) +#define YCTWA_F7_0 (DVDEC0.YCTWA_F7) +#define YCTWA_F8_0 (DVDEC0.YCTWA_F8) +#define YCTWB_F0_0 (DVDEC0.YCTWB_F0) +#define YCTWB_F1_0 (DVDEC0.YCTWB_F1) +#define YCTWB_F2_0 (DVDEC0.YCTWB_F2) +#define YCTWB_F3_0 (DVDEC0.YCTWB_F3) +#define YCTWB_F4_0 (DVDEC0.YCTWB_F4) +#define YCTWB_F5_0 (DVDEC0.YCTWB_F5) +#define YCTWB_F6_0 (DVDEC0.YCTWB_F6) +#define YCTWB_F7_0 (DVDEC0.YCTWB_F7) +#define YCTWB_F8_0 (DVDEC0.YCTWB_F8) +#define YCTNA_F0_0 (DVDEC0.YCTNA_F0) +#define YCTNA_F1_0 (DVDEC0.YCTNA_F1) +#define YCTNA_F2_0 (DVDEC0.YCTNA_F2) +#define YCTNA_F3_0 (DVDEC0.YCTNA_F3) +#define YCTNA_F4_0 (DVDEC0.YCTNA_F4) +#define YCTNA_F5_0 (DVDEC0.YCTNA_F5) +#define YCTNA_F6_0 (DVDEC0.YCTNA_F6) +#define YCTNA_F7_0 (DVDEC0.YCTNA_F7) +#define YCTNA_F8_0 (DVDEC0.YCTNA_F8) +#define YCTNB_F0_0 (DVDEC0.YCTNB_F0) +#define YCTNB_F1_0 (DVDEC0.YCTNB_F1) +#define YCTNB_F2_0 (DVDEC0.YCTNB_F2) +#define YCTNB_F3_0 (DVDEC0.YCTNB_F3) +#define YCTNB_F4_0 (DVDEC0.YCTNB_F4) +#define YCTNB_F5_0 (DVDEC0.YCTNB_F5) +#define YCTNB_F6_0 (DVDEC0.YCTNB_F6) +#define YCTNB_F7_0 (DVDEC0.YCTNB_F7) +#define YCTNB_F8_0 (DVDEC0.YCTNB_F8) +#define YGAINCR_0 (DVDEC0.YGAINCR) +#define CBGAINCR_0 (DVDEC0.CBGAINCR) +#define CRGAINCR_0 (DVDEC0.CRGAINCR) +#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE) +#define PGACR_0 (DVDEC0.PGACR) +#define ADCCR2_0 (DVDEC0.ADCCR2) + +#define DVDEC_TGCRn_COUNT (3) +#define DVDEC_SYNSCRn_COUNT (5) +#define DVDEC_HAFCCRn_COUNT (3) +#define DVDEC_DCPCRn_COUNT (8) +#define DVDEC_ACCCRn_COUNT (3) +#define DVDEC_AGCCRn_COUNT (2) +#define DVDEC_RGORCRn_COUNT (7) +#define DVDEC_DCPSRn_COUNT (2) +#define DVDEC_CROMASRn_COUNT (2) +#define DVDEC_AGCCSRn_COUNT (2) +#define DVDEC_YCSCRn_COUNT (7) +#define DVDEC_YCTWA_Fn_COUNT (9) +#define DVDEC_YCTWB_Fn_COUNT (9) +#define DVDEC_YCTNA_Fn_COUNT (9) +#define DVDEC_YCTNB_Fn_COUNT (9) + + +typedef struct st_dvdec +{ + /* DVDEC */ volatile uint16_t ADCCR1; /* ADCCR1 */ volatile uint8_t dummy1[4]; /* */ -#define DVDEC_TGCRn_COUNT 3 + +/* #define DVDEC_TGCRn_COUNT (3) */ volatile uint16_t TGCR1; /* TGCR1 */ volatile uint16_t TGCR2; /* TGCR2 */ volatile uint16_t TGCR3; /* TGCR3 */ volatile uint8_t dummy2[6]; /* */ -#define DVDEC_SYNSCRn_COUNT 5 + +/* #define DVDEC_SYNSCRn_COUNT (5) */ volatile uint16_t SYNSCR1; /* SYNSCR1 */ volatile uint16_t SYNSCR2; /* SYNSCR2 */ volatile uint16_t SYNSCR3; /* SYNSCR3 */ volatile uint16_t SYNSCR4; /* SYNSCR4 */ volatile uint16_t SYNSCR5; /* SYNSCR5 */ -#define DVDEC_HAFCCRn_COUNT 3 + +/* #define DVDEC_HAFCCRn_COUNT (3) */ volatile uint16_t HAFCCR1; /* HAFCCR1 */ volatile uint16_t HAFCCR2; /* HAFCCR2 */ volatile uint16_t HAFCCR3; /* HAFCCR3 */ volatile uint16_t VCDWCR1; /* VCDWCR1 */ volatile uint8_t dummy3[4]; /* */ -#define DVDEC_DCPCRn_COUNT 8 + +/* #define DVDEC_DCPCRn_COUNT (8) */ volatile uint16_t DCPCR1; /* DCPCR1 */ volatile uint16_t DCPCR2; /* DCPCR2 */ volatile uint16_t DCPCR3; /* DCPCR3 */ @@ -63,17 +312,20 @@ struct st_dvdec volatile uint16_t NSDCR; /* NSDCR */ volatile uint16_t BTLCR; /* BTLCR */ volatile uint16_t BTGPCR; /* BTGPCR */ -#define DVDEC_ACCCRn_COUNT 3 + +/* #define DVDEC_ACCCRn_COUNT (3) */ volatile uint16_t ACCCR1; /* ACCCR1 */ volatile uint16_t ACCCR2; /* ACCCR2 */ volatile uint16_t ACCCR3; /* ACCCR3 */ volatile uint16_t TINTCR; /* TINTCR */ volatile uint16_t YCDCR; /* YCDCR */ -#define DVDEC_AGCCRn_COUNT 2 + +/* #define DVDEC_AGCCRn_COUNT (2) */ volatile uint16_t AGCCR1; /* AGCCR1 */ volatile uint16_t AGCCR2; /* AGCCR2 */ volatile uint16_t PKLIMITCR; /* PKLIMITCR */ -#define DVDEC_RGORCRn_COUNT 7 + +/* #define DVDEC_RGORCRn_COUNT (7) */ volatile uint16_t RGORCR1; /* RGORCR1 */ volatile uint16_t RGORCR2; /* RGORCR2 */ volatile uint16_t RGORCR3; /* RGORCR3 */ @@ -86,20 +338,24 @@ struct st_dvdec volatile uint16_t RUPDCR; /* RUPDCR */ volatile uint16_t VSYNCSR; /* VSYNCSR */ volatile uint16_t HSYNCSR; /* HSYNCSR */ -#define DVDEC_DCPSRn_COUNT 2 + +/* #define DVDEC_DCPSRn_COUNT (2) */ volatile uint16_t DCPSR1; /* DCPSR1 */ volatile uint16_t DCPSR2; /* DCPSR2 */ volatile uint8_t dummy5[4]; /* */ volatile uint16_t NSDSR; /* NSDSR */ -#define DVDEC_CROMASRn_COUNT 2 + +/* #define DVDEC_CROMASRn_COUNT (2) */ volatile uint16_t CROMASR1; /* CROMASR1 */ volatile uint16_t CROMASR2; /* CROMASR2 */ volatile uint16_t SYNCSSR; /* SYNCSSR */ -#define DVDEC_AGCCSRn_COUNT 2 + +/* #define DVDEC_AGCCSRn_COUNT (2) */ volatile uint16_t AGCCSR1; /* AGCCSR1 */ volatile uint16_t AGCCSR2; /* AGCCSR2 */ volatile uint8_t dummy6[108]; /* */ -#define DVDEC_YCSCRn_COUNT 7 + +/* #define DVDEC_YCSCRn_COUNT (7) */ volatile uint16_t YCSCR3; /* YCSCR3 */ volatile uint16_t YCSCR4; /* YCSCR4 */ volatile uint16_t YCSCR5; /* YCSCR5 */ @@ -113,7 +369,8 @@ struct st_dvdec volatile uint8_t dummy8[104]; /* */ volatile uint16_t DCPCR9; /* DCPCR9 */ volatile uint8_t dummy9[16]; /* */ -#define DVDEC_YCTWA_Fn_COUNT 9 + +/* #define DVDEC_YCTWA_Fn_COUNT (9) */ volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ @@ -123,7 +380,8 @@ struct st_dvdec volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ -#define DVDEC_YCTWB_Fn_COUNT 9 + +/* #define DVDEC_YCTWB_Fn_COUNT (9) */ volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ @@ -133,7 +391,8 @@ struct st_dvdec volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ -#define DVDEC_YCTNA_Fn_COUNT 9 + +/* #define DVDEC_YCTNA_Fn_COUNT (9) */ volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ @@ -143,7 +402,8 @@ struct st_dvdec volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ -#define DVDEC_YCTNB_Fn_COUNT 9 + +/* #define DVDEC_YCTNB_Fn_COUNT (9) */ volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ @@ -161,231 +421,21 @@ struct st_dvdec volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ volatile uint16_t PGACR; /* PGACR */ volatile uint16_t ADCCR2; /* ADCCR2 */ -}; - +} r_io_dvdec_t; -#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ -#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ - - -/* Start of channnel array defines of DVDEC */ - -/* Channnel array defines of DVDEC */ -/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ -#define DVDEC_COUNT 2 -#define DVDEC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DVDEC0, &DVDEC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of DVDEC */ +/* Channel array defines of DVDEC (2)*/ +#ifdef DECLARE_DVDEC_CHANNELS +volatile struct st_dvdec* DVDEC[ DVDEC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DVDEC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DVDEC_CHANNELS */ +/* End of channel array defines of DVDEC (2)*/ -#define ADCCR1_1 DVDEC1.ADCCR1 -#define TGCR1_1 DVDEC1.TGCR1 -#define TGCR2_1 DVDEC1.TGCR2 -#define TGCR3_1 DVDEC1.TGCR3 -#define SYNSCR1_1 DVDEC1.SYNSCR1 -#define SYNSCR2_1 DVDEC1.SYNSCR2 -#define SYNSCR3_1 DVDEC1.SYNSCR3 -#define SYNSCR4_1 DVDEC1.SYNSCR4 -#define SYNSCR5_1 DVDEC1.SYNSCR5 -#define HAFCCR1_1 DVDEC1.HAFCCR1 -#define HAFCCR2_1 DVDEC1.HAFCCR2 -#define HAFCCR3_1 DVDEC1.HAFCCR3 -#define VCDWCR1_1 DVDEC1.VCDWCR1 -#define DCPCR1_1 DVDEC1.DCPCR1 -#define DCPCR2_1 DVDEC1.DCPCR2 -#define DCPCR3_1 DVDEC1.DCPCR3 -#define DCPCR4_1 DVDEC1.DCPCR4 -#define DCPCR5_1 DVDEC1.DCPCR5 -#define DCPCR6_1 DVDEC1.DCPCR6 -#define DCPCR7_1 DVDEC1.DCPCR7 -#define DCPCR8_1 DVDEC1.DCPCR8 -#define NSDCR_1 DVDEC1.NSDCR -#define BTLCR_1 DVDEC1.BTLCR -#define BTGPCR_1 DVDEC1.BTGPCR -#define ACCCR1_1 DVDEC1.ACCCR1 -#define ACCCR2_1 DVDEC1.ACCCR2 -#define ACCCR3_1 DVDEC1.ACCCR3 -#define TINTCR_1 DVDEC1.TINTCR -#define YCDCR_1 DVDEC1.YCDCR -#define AGCCR1_1 DVDEC1.AGCCR1 -#define AGCCR2_1 DVDEC1.AGCCR2 -#define PKLIMITCR_1 DVDEC1.PKLIMITCR -#define RGORCR1_1 DVDEC1.RGORCR1 -#define RGORCR2_1 DVDEC1.RGORCR2 -#define RGORCR3_1 DVDEC1.RGORCR3 -#define RGORCR4_1 DVDEC1.RGORCR4 -#define RGORCR5_1 DVDEC1.RGORCR5 -#define RGORCR6_1 DVDEC1.RGORCR6 -#define RGORCR7_1 DVDEC1.RGORCR7 -#define AFCPFCR_1 DVDEC1.AFCPFCR -#define RUPDCR_1 DVDEC1.RUPDCR -#define VSYNCSR_1 DVDEC1.VSYNCSR -#define HSYNCSR_1 DVDEC1.HSYNCSR -#define DCPSR1_1 DVDEC1.DCPSR1 -#define DCPSR2_1 DVDEC1.DCPSR2 -#define NSDSR_1 DVDEC1.NSDSR -#define CROMASR1_1 DVDEC1.CROMASR1 -#define CROMASR2_1 DVDEC1.CROMASR2 -#define SYNCSSR_1 DVDEC1.SYNCSSR -#define AGCCSR1_1 DVDEC1.AGCCSR1 -#define AGCCSR2_1 DVDEC1.AGCCSR2 -#define YCSCR3_1 DVDEC1.YCSCR3 -#define YCSCR4_1 DVDEC1.YCSCR4 -#define YCSCR5_1 DVDEC1.YCSCR5 -#define YCSCR6_1 DVDEC1.YCSCR6 -#define YCSCR7_1 DVDEC1.YCSCR7 -#define YCSCR8_1 DVDEC1.YCSCR8 -#define YCSCR9_1 DVDEC1.YCSCR9 -#define YCSCR11_1 DVDEC1.YCSCR11 -#define YCSCR12_1 DVDEC1.YCSCR12 -#define DCPCR9_1 DVDEC1.DCPCR9 -#define YCTWA_F0_1 DVDEC1.YCTWA_F0 -#define YCTWA_F1_1 DVDEC1.YCTWA_F1 -#define YCTWA_F2_1 DVDEC1.YCTWA_F2 -#define YCTWA_F3_1 DVDEC1.YCTWA_F3 -#define YCTWA_F4_1 DVDEC1.YCTWA_F4 -#define YCTWA_F5_1 DVDEC1.YCTWA_F5 -#define YCTWA_F6_1 DVDEC1.YCTWA_F6 -#define YCTWA_F7_1 DVDEC1.YCTWA_F7 -#define YCTWA_F8_1 DVDEC1.YCTWA_F8 -#define YCTWB_F0_1 DVDEC1.YCTWB_F0 -#define YCTWB_F1_1 DVDEC1.YCTWB_F1 -#define YCTWB_F2_1 DVDEC1.YCTWB_F2 -#define YCTWB_F3_1 DVDEC1.YCTWB_F3 -#define YCTWB_F4_1 DVDEC1.YCTWB_F4 -#define YCTWB_F5_1 DVDEC1.YCTWB_F5 -#define YCTWB_F6_1 DVDEC1.YCTWB_F6 -#define YCTWB_F7_1 DVDEC1.YCTWB_F7 -#define YCTWB_F8_1 DVDEC1.YCTWB_F8 -#define YCTNA_F0_1 DVDEC1.YCTNA_F0 -#define YCTNA_F1_1 DVDEC1.YCTNA_F1 -#define YCTNA_F2_1 DVDEC1.YCTNA_F2 -#define YCTNA_F3_1 DVDEC1.YCTNA_F3 -#define YCTNA_F4_1 DVDEC1.YCTNA_F4 -#define YCTNA_F5_1 DVDEC1.YCTNA_F5 -#define YCTNA_F6_1 DVDEC1.YCTNA_F6 -#define YCTNA_F7_1 DVDEC1.YCTNA_F7 -#define YCTNA_F8_1 DVDEC1.YCTNA_F8 -#define YCTNB_F0_1 DVDEC1.YCTNB_F0 -#define YCTNB_F1_1 DVDEC1.YCTNB_F1 -#define YCTNB_F2_1 DVDEC1.YCTNB_F2 -#define YCTNB_F3_1 DVDEC1.YCTNB_F3 -#define YCTNB_F4_1 DVDEC1.YCTNB_F4 -#define YCTNB_F5_1 DVDEC1.YCTNB_F5 -#define YCTNB_F6_1 DVDEC1.YCTNB_F6 -#define YCTNB_F7_1 DVDEC1.YCTNB_F7 -#define YCTNB_F8_1 DVDEC1.YCTNB_F8 -#define YGAINCR_1 DVDEC1.YGAINCR -#define CBGAINCR_1 DVDEC1.CBGAINCR -#define CRGAINCR_1 DVDEC1.CRGAINCR -#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE -#define PGACR_1 DVDEC1.PGACR -#define ADCCR2_1 DVDEC1.ADCCR2 -#define ADCCR1_0 DVDEC0.ADCCR1 -#define TGCR1_0 DVDEC0.TGCR1 -#define TGCR2_0 DVDEC0.TGCR2 -#define TGCR3_0 DVDEC0.TGCR3 -#define SYNSCR1_0 DVDEC0.SYNSCR1 -#define SYNSCR2_0 DVDEC0.SYNSCR2 -#define SYNSCR3_0 DVDEC0.SYNSCR3 -#define SYNSCR4_0 DVDEC0.SYNSCR4 -#define SYNSCR5_0 DVDEC0.SYNSCR5 -#define HAFCCR1_0 DVDEC0.HAFCCR1 -#define HAFCCR2_0 DVDEC0.HAFCCR2 -#define HAFCCR3_0 DVDEC0.HAFCCR3 -#define VCDWCR1_0 DVDEC0.VCDWCR1 -#define DCPCR1_0 DVDEC0.DCPCR1 -#define DCPCR2_0 DVDEC0.DCPCR2 -#define DCPCR3_0 DVDEC0.DCPCR3 -#define DCPCR4_0 DVDEC0.DCPCR4 -#define DCPCR5_0 DVDEC0.DCPCR5 -#define DCPCR6_0 DVDEC0.DCPCR6 -#define DCPCR7_0 DVDEC0.DCPCR7 -#define DCPCR8_0 DVDEC0.DCPCR8 -#define NSDCR_0 DVDEC0.NSDCR -#define BTLCR_0 DVDEC0.BTLCR -#define BTGPCR_0 DVDEC0.BTGPCR -#define ACCCR1_0 DVDEC0.ACCCR1 -#define ACCCR2_0 DVDEC0.ACCCR2 -#define ACCCR3_0 DVDEC0.ACCCR3 -#define TINTCR_0 DVDEC0.TINTCR -#define YCDCR_0 DVDEC0.YCDCR -#define AGCCR1_0 DVDEC0.AGCCR1 -#define AGCCR2_0 DVDEC0.AGCCR2 -#define PKLIMITCR_0 DVDEC0.PKLIMITCR -#define RGORCR1_0 DVDEC0.RGORCR1 -#define RGORCR2_0 DVDEC0.RGORCR2 -#define RGORCR3_0 DVDEC0.RGORCR3 -#define RGORCR4_0 DVDEC0.RGORCR4 -#define RGORCR5_0 DVDEC0.RGORCR5 -#define RGORCR6_0 DVDEC0.RGORCR6 -#define RGORCR7_0 DVDEC0.RGORCR7 -#define AFCPFCR_0 DVDEC0.AFCPFCR -#define RUPDCR_0 DVDEC0.RUPDCR -#define VSYNCSR_0 DVDEC0.VSYNCSR -#define HSYNCSR_0 DVDEC0.HSYNCSR -#define DCPSR1_0 DVDEC0.DCPSR1 -#define DCPSR2_0 DVDEC0.DCPSR2 -#define NSDSR_0 DVDEC0.NSDSR -#define CROMASR1_0 DVDEC0.CROMASR1 -#define CROMASR2_0 DVDEC0.CROMASR2 -#define SYNCSSR_0 DVDEC0.SYNCSSR -#define AGCCSR1_0 DVDEC0.AGCCSR1 -#define AGCCSR2_0 DVDEC0.AGCCSR2 -#define YCSCR3_0 DVDEC0.YCSCR3 -#define YCSCR4_0 DVDEC0.YCSCR4 -#define YCSCR5_0 DVDEC0.YCSCR5 -#define YCSCR6_0 DVDEC0.YCSCR6 -#define YCSCR7_0 DVDEC0.YCSCR7 -#define YCSCR8_0 DVDEC0.YCSCR8 -#define YCSCR9_0 DVDEC0.YCSCR9 -#define YCSCR11_0 DVDEC0.YCSCR11 -#define YCSCR12_0 DVDEC0.YCSCR12 -#define DCPCR9_0 DVDEC0.DCPCR9 -#define YCTWA_F0_0 DVDEC0.YCTWA_F0 -#define YCTWA_F1_0 DVDEC0.YCTWA_F1 -#define YCTWA_F2_0 DVDEC0.YCTWA_F2 -#define YCTWA_F3_0 DVDEC0.YCTWA_F3 -#define YCTWA_F4_0 DVDEC0.YCTWA_F4 -#define YCTWA_F5_0 DVDEC0.YCTWA_F5 -#define YCTWA_F6_0 DVDEC0.YCTWA_F6 -#define YCTWA_F7_0 DVDEC0.YCTWA_F7 -#define YCTWA_F8_0 DVDEC0.YCTWA_F8 -#define YCTWB_F0_0 DVDEC0.YCTWB_F0 -#define YCTWB_F1_0 DVDEC0.YCTWB_F1 -#define YCTWB_F2_0 DVDEC0.YCTWB_F2 -#define YCTWB_F3_0 DVDEC0.YCTWB_F3 -#define YCTWB_F4_0 DVDEC0.YCTWB_F4 -#define YCTWB_F5_0 DVDEC0.YCTWB_F5 -#define YCTWB_F6_0 DVDEC0.YCTWB_F6 -#define YCTWB_F7_0 DVDEC0.YCTWB_F7 -#define YCTWB_F8_0 DVDEC0.YCTWB_F8 -#define YCTNA_F0_0 DVDEC0.YCTNA_F0 -#define YCTNA_F1_0 DVDEC0.YCTNA_F1 -#define YCTNA_F2_0 DVDEC0.YCTNA_F2 -#define YCTNA_F3_0 DVDEC0.YCTNA_F3 -#define YCTNA_F4_0 DVDEC0.YCTNA_F4 -#define YCTNA_F5_0 DVDEC0.YCTNA_F5 -#define YCTNA_F6_0 DVDEC0.YCTNA_F6 -#define YCTNA_F7_0 DVDEC0.YCTNA_F7 -#define YCTNA_F8_0 DVDEC0.YCTNA_F8 -#define YCTNB_F0_0 DVDEC0.YCTNB_F0 -#define YCTNB_F1_0 DVDEC0.YCTNB_F1 -#define YCTNB_F2_0 DVDEC0.YCTNB_F2 -#define YCTNB_F3_0 DVDEC0.YCTNB_F3 -#define YCTNB_F4_0 DVDEC0.YCTNB_F4 -#define YCTNB_F5_0 DVDEC0.YCTNB_F5 -#define YCTNB_F6_0 DVDEC0.YCTNB_F6 -#define YCTNB_F7_0 DVDEC0.YCTNB_F7 -#define YCTNB_F8_0 DVDEC0.YCTNB_F8 -#define YGAINCR_0 DVDEC0.YGAINCR -#define CBGAINCR_0 DVDEC0.CBGAINCR -#define CRGAINCR_0 DVDEC0.CRGAINCR -#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE -#define PGACR_0 DVDEC0.PGACR -#define ADCCR2_0 DVDEC0.ADCCR2 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h similarity index 79% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h index 88b268ec7dd..fef3000ff96 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h @@ -18,21 +18,192 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ether_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ETHER_IODEFINE_H #define ETHER_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ether -{ /* ETHER */ +#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ + + +/* Start of channel array defines of ETHER */ + +/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ +/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ +#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32) +#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ + ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ + ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ + ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ +#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ +#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ +#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ +#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ +#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ +#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ +#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ +#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ +#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ +#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ +#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ +#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ +#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ +#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ +#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ +#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ +#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ +#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ +#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ +#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ +#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ +#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ +#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ +#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ +#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ +#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ +#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ +#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ +#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ +#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ +#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ + +/* End of channel array defines of ETHER */ + + +#define ETHEREDSR0 (ETHER.EDSR0) +#define ETHERTDLAR0 (ETHER.TDLAR0) +#define ETHERTDFAR0 (ETHER.TDFAR0) +#define ETHERTDFXR0 (ETHER.TDFXR0) +#define ETHERTDFFR0 (ETHER.TDFFR0) +#define ETHERRDLAR0 (ETHER.RDLAR0) +#define ETHERRDFAR0 (ETHER.RDFAR0) +#define ETHERRDFXR0 (ETHER.RDFXR0) +#define ETHERRDFFR0 (ETHER.RDFFR0) +#define ETHEREDMR0 (ETHER.EDMR0) +#define ETHEREDTRR0 (ETHER.EDTRR0) +#define ETHEREDRRR0 (ETHER.EDRRR0) +#define ETHEREESR0 (ETHER.EESR0) +#define ETHEREESIPR0 (ETHER.EESIPR0) +#define ETHERTRSCER0 (ETHER.TRSCER0) +#define ETHERRMFCR0 (ETHER.RMFCR0) +#define ETHERTFTR0 (ETHER.TFTR0) +#define ETHERFDR0 (ETHER.FDR0) +#define ETHERRMCR0 (ETHER.RMCR0) +#define ETHERRPADIR0 (ETHER.RPADIR0) +#define ETHERFCFTR0 (ETHER.FCFTR0) +#define ETHERCSMR (ETHER.CSMR) +#define ETHERCSSBM (ETHER.CSSBM) +#define ETHERCSSMR (ETHER.CSSMR) +#define ETHERECMR0 (ETHER.ECMR0) +#define ETHERRFLR0 (ETHER.RFLR0) +#define ETHERECSR0 (ETHER.ECSR0) +#define ETHERECSIPR0 (ETHER.ECSIPR0) +#define ETHERPIR0 (ETHER.PIR0) +#define ETHERAPR0 (ETHER.APR0) +#define ETHERMPR0 (ETHER.MPR0) +#define ETHERPFTCR0 (ETHER.PFTCR0) +#define ETHERPFRCR0 (ETHER.PFRCR0) +#define ETHERTPAUSER0 (ETHER.TPAUSER0) +#define ETHERMAHR0 (ETHER.MAHR0) +#define ETHERMALR0 (ETHER.MALR0) +#define ETHERCEFCR0 (ETHER.CEFCR0) +#define ETHERFRECR0 (ETHER.FRECR0) +#define ETHERTSFRCR0 (ETHER.TSFRCR0) +#define ETHERTLFRCR0 (ETHER.TLFRCR0) +#define ETHERRFCR0 (ETHER.RFCR0) +#define ETHERMAFCR0 (ETHER.MAFCR0) +#define ETHERARSTR (ETHER.ARSTR) +#define ETHERTSU_CTRST (ETHER.TSU_CTRST) +#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0) +#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY) +#define ETHERTSU_TEN (ETHER.TSU_TEN) +#define ETHERTXNLCR0 (ETHER.TXNLCR0) +#define ETHERTXALCR0 (ETHER.TXALCR0) +#define ETHERRXNLCR0 (ETHER.RXNLCR0) +#define ETHERRXALCR0 (ETHER.RXALCR0) +#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0) +#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0) +#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1) +#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1) +#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2) +#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2) +#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3) +#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3) +#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4) +#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4) +#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5) +#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5) +#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6) +#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6) +#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7) +#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7) +#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8) +#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8) +#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9) +#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9) +#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10) +#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10) +#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11) +#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11) +#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12) +#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12) +#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13) +#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13) +#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14) +#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14) +#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15) +#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15) +#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16) +#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16) +#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17) +#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17) +#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18) +#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18) +#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19) +#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19) +#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20) +#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20) +#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21) +#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21) +#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22) +#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22) +#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23) +#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23) +#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24) +#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24) +#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25) +#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25) +#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26) +#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26) +#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27) +#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27) +#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28) +#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28) +#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29) +#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29) +#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30) +#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30) +#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31) +#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31) + + +typedef struct st_ether +{ + /* ETHER */ volatile uint32_t EDSR0; /* EDSR0 */ volatile uint8_t dummy207[12]; /* */ volatile uint32_t TDLAR0; /* TDLAR0 */ @@ -118,310 +289,221 @@ struct st_ether volatile uint32_t RXNLCR0; /* RXNLCR0 */ volatile uint32_t RXALCR0; /* RXALCR0 */ volatile uint8_t dummy240[112]; /* */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ + /* end of struct st_ether_from_tsu_adrh0 */ -}; +} r_io_ether_t; -struct st_ether_from_tsu_adrh0 +typedef struct st_ether_from_tsu_adrh0 { + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ -}; +} r_io_ether_from_tsu_adrh0_t; -#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ - +/* Channel array defines of ETHER (2)*/ +#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS +volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */ +/* End of channel array defines of ETHER (2)*/ -/* Start of channnel array defines of ETHER */ - -/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ -/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ -#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32 -#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ - ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ - ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ - ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ -#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ -#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ -#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ -#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ -#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ -#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ -#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ -#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ -#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ -#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ -#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ -#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ -#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ -#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ -#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ -#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ -#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ -#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ -#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ -#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ -#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ -#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ -#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ -#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ -#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ -#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ -#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ -#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ -#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ -#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ -#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ -/* End of channnel array defines of ETHER */ - - -#define ETHEREDSR0 ETHER.EDSR0 -#define ETHERTDLAR0 ETHER.TDLAR0 -#define ETHERTDFAR0 ETHER.TDFAR0 -#define ETHERTDFXR0 ETHER.TDFXR0 -#define ETHERTDFFR0 ETHER.TDFFR0 -#define ETHERRDLAR0 ETHER.RDLAR0 -#define ETHERRDFAR0 ETHER.RDFAR0 -#define ETHERRDFXR0 ETHER.RDFXR0 -#define ETHERRDFFR0 ETHER.RDFFR0 -#define ETHEREDMR0 ETHER.EDMR0 -#define ETHEREDTRR0 ETHER.EDTRR0 -#define ETHEREDRRR0 ETHER.EDRRR0 -#define ETHEREESR0 ETHER.EESR0 -#define ETHEREESIPR0 ETHER.EESIPR0 -#define ETHERTRSCER0 ETHER.TRSCER0 -#define ETHERRMFCR0 ETHER.RMFCR0 -#define ETHERTFTR0 ETHER.TFTR0 -#define ETHERFDR0 ETHER.FDR0 -#define ETHERRMCR0 ETHER.RMCR0 -#define ETHERRPADIR0 ETHER.RPADIR0 -#define ETHERFCFTR0 ETHER.FCFTR0 -#define ETHERCSMR ETHER.CSMR -#define ETHERCSSBM ETHER.CSSBM -#define ETHERCSSMR ETHER.CSSMR -#define ETHERECMR0 ETHER.ECMR0 -#define ETHERRFLR0 ETHER.RFLR0 -#define ETHERECSR0 ETHER.ECSR0 -#define ETHERECSIPR0 ETHER.ECSIPR0 -#define ETHERPIR0 ETHER.PIR0 -#define ETHERAPR0 ETHER.APR0 -#define ETHERMPR0 ETHER.MPR0 -#define ETHERPFTCR0 ETHER.PFTCR0 -#define ETHERPFRCR0 ETHER.PFRCR0 -#define ETHERTPAUSER0 ETHER.TPAUSER0 -#define ETHERMAHR0 ETHER.MAHR0 -#define ETHERMALR0 ETHER.MALR0 -#define ETHERCEFCR0 ETHER.CEFCR0 -#define ETHERFRECR0 ETHER.FRECR0 -#define ETHERTSFRCR0 ETHER.TSFRCR0 -#define ETHERTLFRCR0 ETHER.TLFRCR0 -#define ETHERRFCR0 ETHER.RFCR0 -#define ETHERMAFCR0 ETHER.MAFCR0 -#define ETHERARSTR ETHER.ARSTR -#define ETHERTSU_CTRST ETHER.TSU_CTRST -#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0 -#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY -#define ETHERTSU_TEN ETHER.TSU_TEN -#define ETHERTXNLCR0 ETHER.TXNLCR0 -#define ETHERTXALCR0 ETHER.TXALCR0 -#define ETHERRXNLCR0 ETHER.RXNLCR0 -#define ETHERRXALCR0 ETHER.RXALCR0 -#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0 -#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0 -#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1 -#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1 -#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2 -#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2 -#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3 -#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3 -#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4 -#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4 -#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5 -#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5 -#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6 -#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6 -#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7 -#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7 -#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8 -#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8 -#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9 -#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9 -#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10 -#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10 -#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11 -#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11 -#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12 -#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12 -#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13 -#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13 -#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14 -#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14 -#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15 -#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15 -#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16 -#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16 -#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17 -#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17 -#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18 -#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18 -#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19 -#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19 -#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20 -#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20 -#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21 -#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21 -#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22 -#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22 -#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23 -#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23 -#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24 -#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24 -#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25 -#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25 -#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26 -#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26 -#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27 -#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27 -#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28 -#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28 -#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29 -#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29 -#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30 -#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30 -#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31 -#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h similarity index 77% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h index 3f8ec183c21..0e88e0cad28 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h @@ -18,20 +18,41 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : flctl_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef FLCTL_IODEFINE_H #define FLCTL_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_flctl -{ /* FLCTL */ +#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ + + +#define FLCTLFLCMNCR (FLCTL.FLCMNCR) +#define FLCTLFLCMDCR (FLCTL.FLCMDCR) +#define FLCTLFLCMCDR (FLCTL.FLCMCDR) +#define FLCTLFLADR (FLCTL.FLADR) +#define FLCTLFLDATAR (FLCTL.FLDATAR) +#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR) +#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR) +#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR) +#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT) +#define FLCTLFLTRCR (FLCTL.FLTRCR) +#define FLCTLFLADR2 (FLCTL.FLADR2) +#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO) + + +typedef struct st_flctl +{ + /* FLCTL */ volatile uint32_t FLCMNCR; /* FLCMNCR */ volatile uint32_t FLCMDCR; /* FLCMDCR */ volatile uint32_t FLCMCDR; /* FLCMCDR */ @@ -47,26 +68,11 @@ struct st_flctl volatile uint32_t FLADR2; /* FLADR2 */ volatile uint8_t dummy557[16]; /* */ volatile uint32_t FLDTFIFO; /* FLDTFIFO */ - volatile uint8_t dummy558[12]; /* */ - volatile uint32_t FLECFIFO; /* FLECFIFO */ -}; - - -#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ +} r_io_flctl_t; -#define FLCTLFLCMNCR FLCTL.FLCMNCR -#define FLCTLFLCMDCR FLCTL.FLCMDCR -#define FLCTLFLCMCDR FLCTL.FLCMCDR -#define FLCTLFLADR FLCTL.FLADR -#define FLCTLFLDATAR FLCTL.FLDATAR -#define FLCTLFLDTCNTR FLCTL.FLDTCNTR -#define FLCTLFLINTDMACR FLCTL.FLINTDMACR -#define FLCTLFLBSYTMR FLCTL.FLBSYTMR -#define FLCTLFLBSYCNT FLCTL.FLBSYCNT -#define FLCTLFLTRCR FLCTL.FLTRCR -#define FLCTLFLADR2 FLCTL.FLADR2 -#define FLCTLFLDTFIFO FLCTL.FLDTFIFO -#define FLCTLFLECFIFO FLCTL.FLECFIFO /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h similarity index 82% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h index 8bedb518ff3..05c30ecdf54 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h @@ -18,67 +18,503 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : gpio_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef GPIO_IODEFINE_H #define GPIO_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_gpio -{ /* GPIO */ +#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ + + +/* Start of channel array defines of GPIO */ + +/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ +#define GPIO_FROM_PIPC1_ARRAY_COUNT (11) +#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ + &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */ +#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */ +#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */ +#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */ +#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */ +#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */ +#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */ +#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */ +#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */ +#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */ +#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ + + +/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ +#define GPIO_FROM_PBDC1_ARRAY_COUNT (11) +#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ + &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */ +#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */ +#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */ +#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */ +#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */ +#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */ +#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */ +#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */ +#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */ +#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */ +#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ + + +/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ +#define GPIO_FROM_PIBC1_ARRAY_COUNT (12) +#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \ + &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */ +#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ +#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ +#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ +#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */ +#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */ +#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */ +#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */ +#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */ +#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */ +#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */ +#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ + + +/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ +#define GPIO_FROM_PFCAE1_ARRAY_COUNT (11) +#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ + &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */ +#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */ +#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */ +#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */ +#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */ +#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */ +#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */ +#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */ +#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */ +#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */ +#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ + + +/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */ +/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ +#define GPIO_FROM_PNOT1_ARRAY_COUNT (11) +#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ + &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */ +#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */ +#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */ +#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */ +#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */ +#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */ +#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */ +#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */ +#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */ +#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */ +#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ + + +/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ +#define GPIO_FROM_PFCE1_ARRAY_COUNT (11) +#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ + &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */ +#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */ +#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */ +#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */ +#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */ +#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */ +#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */ +#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */ +#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */ +#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */ +#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ + + +/* Channel array defines of GPIO_FROM_PFC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ +#define GPIO_FROM_PFC1_ARRAY_COUNT (11) +#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ + &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */ +#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */ +#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */ +#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */ +#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */ +#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */ +#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */ +#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */ +#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */ +#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */ +#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ + + +/* Channel array defines of GPIO_FROM_PMC0_ARRAY */ +/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ +#define GPIO_FROM_PMC0_ARRAY_COUNT (12) +#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ + &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */ +#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */ +#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */ +#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */ +#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */ +#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */ +#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */ +#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */ +#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */ +#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */ +#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */ +#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ + + +/* Channel array defines of GPIO_FROM_PM1_ARRAY */ +/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ +#define GPIO_FROM_PM1_ARRAY_COUNT (11) +#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ + &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */ +#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */ +#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */ +#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */ +#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */ +#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */ +#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */ +#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */ +#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */ +#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */ +#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ + + +/* Channel array defines of GPIO_FROM_PPR0_ARRAY */ +/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ +#define GPIO_FROM_PPR0_ARRAY_COUNT (12) +#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ + &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */ +#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */ +#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */ +#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */ +#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */ +#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */ +#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */ +#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */ +#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */ +#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */ +#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */ +#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ + + +/* Channel array defines of GPIO_FROM_P1_ARRAY */ +/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ +#define GPIO_FROM_P1_ARRAY_COUNT (11) +#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ + &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */ +#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */ +#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */ +#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */ +#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */ +#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */ +#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */ +#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */ +#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */ +#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ +#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ + +/* End of channel array defines of GPIO */ + + +#define GPIOP1 (GPIO.P1) +#define GPIOP2 (GPIO.P2) +#define GPIOP3 (GPIO.P3) +#define GPIOP4 (GPIO.P4) +#define GPIOP5 (GPIO.P5) +#define GPIOP6 (GPIO.P6) +#define GPIOP7 (GPIO.P7) +#define GPIOP8 (GPIO.P8) +#define GPIOP9 (GPIO.P9) +#define GPIOP10 (GPIO.P10) +#define GPIOP11 (GPIO.P11) +#define GPIOPSR1 (GPIO.PSR1) +#define GPIOPSR2 (GPIO.PSR2) +#define GPIOPSR3 (GPIO.PSR3) +#define GPIOPSR4 (GPIO.PSR4) +#define GPIOPSR5 (GPIO.PSR5) +#define GPIOPSR6 (GPIO.PSR6) +#define GPIOPSR7 (GPIO.PSR7) +#define GPIOPSR8 (GPIO.PSR8) +#define GPIOPSR9 (GPIO.PSR9) +#define GPIOPSR10 (GPIO.PSR10) +#define GPIOPSR11 (GPIO.PSR11) +#define GPIOPPR0 (GPIO.PPR0) +#define GPIOPPR1 (GPIO.PPR1) +#define GPIOPPR2 (GPIO.PPR2) +#define GPIOPPR3 (GPIO.PPR3) +#define GPIOPPR4 (GPIO.PPR4) +#define GPIOPPR5 (GPIO.PPR5) +#define GPIOPPR6 (GPIO.PPR6) +#define GPIOPPR7 (GPIO.PPR7) +#define GPIOPPR8 (GPIO.PPR8) +#define GPIOPPR9 (GPIO.PPR9) +#define GPIOPPR10 (GPIO.PPR10) +#define GPIOPPR11 (GPIO.PPR11) +#define GPIOPM1 (GPIO.PM1) +#define GPIOPM2 (GPIO.PM2) +#define GPIOPM3 (GPIO.PM3) +#define GPIOPM4 (GPIO.PM4) +#define GPIOPM5 (GPIO.PM5) +#define GPIOPM6 (GPIO.PM6) +#define GPIOPM7 (GPIO.PM7) +#define GPIOPM8 (GPIO.PM8) +#define GPIOPM9 (GPIO.PM9) +#define GPIOPM10 (GPIO.PM10) +#define GPIOPM11 (GPIO.PM11) +#define GPIOPMC0 (GPIO.PMC0) +#define GPIOPMC1 (GPIO.PMC1) +#define GPIOPMC2 (GPIO.PMC2) +#define GPIOPMC3 (GPIO.PMC3) +#define GPIOPMC4 (GPIO.PMC4) +#define GPIOPMC5 (GPIO.PMC5) +#define GPIOPMC6 (GPIO.PMC6) +#define GPIOPMC7 (GPIO.PMC7) +#define GPIOPMC8 (GPIO.PMC8) +#define GPIOPMC9 (GPIO.PMC9) +#define GPIOPMC10 (GPIO.PMC10) +#define GPIOPMC11 (GPIO.PMC11) +#define GPIOPFC1 (GPIO.PFC1) +#define GPIOPFC2 (GPIO.PFC2) +#define GPIOPFC3 (GPIO.PFC3) +#define GPIOPFC4 (GPIO.PFC4) +#define GPIOPFC5 (GPIO.PFC5) +#define GPIOPFC6 (GPIO.PFC6) +#define GPIOPFC7 (GPIO.PFC7) +#define GPIOPFC8 (GPIO.PFC8) +#define GPIOPFC9 (GPIO.PFC9) +#define GPIOPFC10 (GPIO.PFC10) +#define GPIOPFC11 (GPIO.PFC11) +#define GPIOPFCE1 (GPIO.PFCE1) +#define GPIOPFCE2 (GPIO.PFCE2) +#define GPIOPFCE3 (GPIO.PFCE3) +#define GPIOPFCE4 (GPIO.PFCE4) +#define GPIOPFCE5 (GPIO.PFCE5) +#define GPIOPFCE6 (GPIO.PFCE6) +#define GPIOPFCE7 (GPIO.PFCE7) +#define GPIOPFCE8 (GPIO.PFCE8) +#define GPIOPFCE9 (GPIO.PFCE9) +#define GPIOPFCE10 (GPIO.PFCE10) +#define GPIOPFCE11 (GPIO.PFCE11) +#define GPIOPNOT1 (GPIO.PNOT1) +#define GPIOPNOT2 (GPIO.PNOT2) +#define GPIOPNOT3 (GPIO.PNOT3) +#define GPIOPNOT4 (GPIO.PNOT4) +#define GPIOPNOT5 (GPIO.PNOT5) +#define GPIOPNOT6 (GPIO.PNOT6) +#define GPIOPNOT7 (GPIO.PNOT7) +#define GPIOPNOT8 (GPIO.PNOT8) +#define GPIOPNOT9 (GPIO.PNOT9) +#define GPIOPNOT10 (GPIO.PNOT10) +#define GPIOPNOT11 (GPIO.PNOT11) +#define GPIOPMSR1 (GPIO.PMSR1) +#define GPIOPMSR2 (GPIO.PMSR2) +#define GPIOPMSR3 (GPIO.PMSR3) +#define GPIOPMSR4 (GPIO.PMSR4) +#define GPIOPMSR5 (GPIO.PMSR5) +#define GPIOPMSR6 (GPIO.PMSR6) +#define GPIOPMSR7 (GPIO.PMSR7) +#define GPIOPMSR8 (GPIO.PMSR8) +#define GPIOPMSR9 (GPIO.PMSR9) +#define GPIOPMSR10 (GPIO.PMSR10) +#define GPIOPMSR11 (GPIO.PMSR11) +#define GPIOPMCSR0 (GPIO.PMCSR0) +#define GPIOPMCSR1 (GPIO.PMCSR1) +#define GPIOPMCSR2 (GPIO.PMCSR2) +#define GPIOPMCSR3 (GPIO.PMCSR3) +#define GPIOPMCSR4 (GPIO.PMCSR4) +#define GPIOPMCSR5 (GPIO.PMCSR5) +#define GPIOPMCSR6 (GPIO.PMCSR6) +#define GPIOPMCSR7 (GPIO.PMCSR7) +#define GPIOPMCSR8 (GPIO.PMCSR8) +#define GPIOPMCSR9 (GPIO.PMCSR9) +#define GPIOPMCSR10 (GPIO.PMCSR10) +#define GPIOPMCSR11 (GPIO.PMCSR11) +#define GPIOPFCAE1 (GPIO.PFCAE1) +#define GPIOPFCAE2 (GPIO.PFCAE2) +#define GPIOPFCAE3 (GPIO.PFCAE3) +#define GPIOPFCAE4 (GPIO.PFCAE4) +#define GPIOPFCAE5 (GPIO.PFCAE5) +#define GPIOPFCAE6 (GPIO.PFCAE6) +#define GPIOPFCAE7 (GPIO.PFCAE7) +#define GPIOPFCAE8 (GPIO.PFCAE8) +#define GPIOPFCAE9 (GPIO.PFCAE9) +#define GPIOPFCAE10 (GPIO.PFCAE10) +#define GPIOPFCAE11 (GPIO.PFCAE11) +#define GPIOSNCR (GPIO.SNCR) +#define GPIOPIBC0 (GPIO.PIBC0) +#define GPIOPIBC1 (GPIO.PIBC1) +#define GPIOPIBC2 (GPIO.PIBC2) +#define GPIOPIBC3 (GPIO.PIBC3) +#define GPIOPIBC4 (GPIO.PIBC4) +#define GPIOPIBC5 (GPIO.PIBC5) +#define GPIOPIBC6 (GPIO.PIBC6) +#define GPIOPIBC7 (GPIO.PIBC7) +#define GPIOPIBC8 (GPIO.PIBC8) +#define GPIOPIBC9 (GPIO.PIBC9) +#define GPIOPIBC10 (GPIO.PIBC10) +#define GPIOPIBC11 (GPIO.PIBC11) +#define GPIOPBDC1 (GPIO.PBDC1) +#define GPIOPBDC2 (GPIO.PBDC2) +#define GPIOPBDC3 (GPIO.PBDC3) +#define GPIOPBDC4 (GPIO.PBDC4) +#define GPIOPBDC5 (GPIO.PBDC5) +#define GPIOPBDC6 (GPIO.PBDC6) +#define GPIOPBDC7 (GPIO.PBDC7) +#define GPIOPBDC8 (GPIO.PBDC8) +#define GPIOPBDC9 (GPIO.PBDC9) +#define GPIOPBDC10 (GPIO.PBDC10) +#define GPIOPBDC11 (GPIO.PBDC11) +#define GPIOPIPC1 (GPIO.PIPC1) +#define GPIOPIPC2 (GPIO.PIPC2) +#define GPIOPIPC3 (GPIO.PIPC3) +#define GPIOPIPC4 (GPIO.PIPC4) +#define GPIOPIPC5 (GPIO.PIPC5) +#define GPIOPIPC6 (GPIO.PIPC6) +#define GPIOPIPC7 (GPIO.PIPC7) +#define GPIOPIPC8 (GPIO.PIPC8) +#define GPIOPIPC9 (GPIO.PIPC9) +#define GPIOPIPC10 (GPIO.PIPC10) +#define GPIOPIPC11 (GPIO.PIPC11) +#define GPIOJPPR0 (GPIO.JPPR0) +#define GPIOJPMC0 (GPIO.JPMC0) +#define GPIOJPMCSR0 (GPIO.JPMCSR0) +#define GPIOJPIBC0 (GPIO.JPIBC0) + +#define GPIO_PSRn_COUNT (11) +#define GPIO_PMSRn_COUNT (11) +#define GPIO_PMCSRn_COUNT (12) + + +typedef struct st_gpio +{ + /* GPIO */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P1; /* P1 */ volatile uint8_t dummy348[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P2; /* P2 */ volatile uint8_t dummy349[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P3; /* P3 */ volatile uint8_t dummy350[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P4; /* P4 */ volatile uint8_t dummy351[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P5; /* P5 */ volatile uint8_t dummy352[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P6; /* P6 */ volatile uint8_t dummy353[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P7; /* P7 */ volatile uint8_t dummy354[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P8; /* P8 */ volatile uint8_t dummy355[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P9; /* P9 */ volatile uint8_t dummy356[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P10; /* P10 */ volatile uint8_t dummy357[2]; /* */ + /* end of struct st_gpio_from_p1 */ + /* start of struct st_gpio_from_p1 */ volatile uint16_t P11; /* P11 */ volatile uint8_t dummy3580[2]; /* */ + /* end of struct st_gpio_from_p1 */ volatile uint8_t dummy3581[212]; /* */ -#define GPIO_PSRn_COUNT 11 + +/* #define GPIO_PSRn_COUNT (11) */ volatile uint32_t PSR1; /* PSR1 */ volatile uint32_t PSR2; /* PSR2 */ volatile uint32_t PSR3; /* PSR3 */ @@ -91,285 +527,422 @@ struct st_gpio volatile uint32_t PSR10; /* PSR10 */ volatile uint32_t PSR11; /* PSR11 */ volatile uint8_t dummy359[208]; /* */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR0; /* PPR0 */ volatile uint8_t dummy360[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR1; /* PPR1 */ volatile uint8_t dummy361[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR2; /* PPR2 */ volatile uint8_t dummy362[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR3; /* PPR3 */ volatile uint8_t dummy363[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR4; /* PPR4 */ volatile uint8_t dummy364[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR5; /* PPR5 */ volatile uint8_t dummy365[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR6; /* PPR6 */ volatile uint8_t dummy366[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR7; /* PPR7 */ volatile uint8_t dummy367[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR8; /* PPR8 */ volatile uint8_t dummy368[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR9; /* PPR9 */ volatile uint8_t dummy369[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR10; /* PPR10 */ volatile uint8_t dummy370[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ + /* start of struct st_gpio_from_ppr0 */ volatile uint16_t PPR11; /* PPR11 */ volatile uint8_t dummy3710[2]; /* */ + /* end of struct st_gpio_from_ppr0 */ volatile uint8_t dummy3711[212]; /* */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM1; /* PM1 */ volatile uint8_t dummy372[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM2; /* PM2 */ volatile uint8_t dummy373[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM3; /* PM3 */ volatile uint8_t dummy374[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM4; /* PM4 */ volatile uint8_t dummy375[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM5; /* PM5 */ volatile uint8_t dummy376[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM6; /* PM6 */ volatile uint8_t dummy377[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM7; /* PM7 */ volatile uint8_t dummy378[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM8; /* PM8 */ volatile uint8_t dummy379[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM9; /* PM9 */ volatile uint8_t dummy380[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM10; /* PM10 */ volatile uint8_t dummy381[2]; /* */ + /* end of struct st_gpio_from_pm1 */ + /* start of struct st_gpio_from_pm1 */ volatile uint16_t PM11; /* PM11 */ volatile uint8_t dummy3820[2]; /* */ + /* end of struct st_gpio_from_pm1 */ volatile uint8_t dummy3821[208]; /* */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC0; /* PMC0 */ volatile uint8_t dummy383[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC1; /* PMC1 */ volatile uint8_t dummy384[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC2; /* PMC2 */ volatile uint8_t dummy385[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC3; /* PMC3 */ volatile uint8_t dummy386[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC4; /* PMC4 */ volatile uint8_t dummy387[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC5; /* PMC5 */ volatile uint8_t dummy388[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC6; /* PMC6 */ volatile uint8_t dummy389[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC7; /* PMC7 */ volatile uint8_t dummy390[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC8; /* PMC8 */ volatile uint8_t dummy391[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC9; /* PMC9 */ volatile uint8_t dummy392[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC10; /* PMC10 */ volatile uint8_t dummy393[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ + /* start of struct st_gpio_from_pmc0 */ volatile uint16_t PMC11; /* PMC11 */ volatile uint8_t dummy3940[2]; /* */ + /* end of struct st_gpio_from_pmc0 */ volatile uint8_t dummy3941[212]; /* */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC1; /* PFC1 */ volatile uint8_t dummy395[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC2; /* PFC2 */ volatile uint8_t dummy396[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC3; /* PFC3 */ volatile uint8_t dummy397[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC4; /* PFC4 */ volatile uint8_t dummy398[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC5; /* PFC5 */ volatile uint8_t dummy399[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC6; /* PFC6 */ volatile uint8_t dummy400[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC7; /* PFC7 */ volatile uint8_t dummy401[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC8; /* PFC8 */ volatile uint8_t dummy402[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC9; /* PFC9 */ volatile uint8_t dummy403[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC10; /* PFC10 */ volatile uint8_t dummy404[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ + /* start of struct st_gpio_from_pfc1 */ volatile uint16_t PFC11; /* PFC11 */ volatile uint8_t dummy4050[2]; /* */ + /* end of struct st_gpio_from_pfc1 */ volatile uint8_t dummy4051[212]; /* */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE1; /* PFCE1 */ volatile uint8_t dummy406[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE2; /* PFCE2 */ volatile uint8_t dummy407[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE3; /* PFCE3 */ volatile uint8_t dummy408[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE4; /* PFCE4 */ volatile uint8_t dummy409[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE5; /* PFCE5 */ volatile uint8_t dummy410[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE6; /* PFCE6 */ volatile uint8_t dummy411[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE7; /* PFCE7 */ volatile uint8_t dummy412[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE8; /* PFCE8 */ volatile uint8_t dummy413[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE9; /* PFCE9 */ volatile uint8_t dummy414[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE10; /* PFCE10 */ volatile uint8_t dummy415[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ + /* start of struct st_gpio_from_pfce1 */ volatile uint16_t PFCE11; /* PFCE11 */ volatile uint8_t dummy4160[2]; /* */ + /* end of struct st_gpio_from_pfce1 */ volatile uint8_t dummy4161[212]; /* */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT1; /* PNOT1 */ volatile uint8_t dummy417[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT2; /* PNOT2 */ volatile uint8_t dummy418[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT3; /* PNOT3 */ volatile uint8_t dummy419[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT4; /* PNOT4 */ volatile uint8_t dummy420[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT5; /* PNOT5 */ volatile uint8_t dummy421[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT6; /* PNOT6 */ volatile uint8_t dummy422[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT7; /* PNOT7 */ volatile uint8_t dummy423[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT8; /* PNOT8 */ volatile uint8_t dummy424[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT9; /* PNOT9 */ volatile uint8_t dummy425[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT10; /* PNOT10 */ volatile uint8_t dummy426[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ + /* start of struct st_gpio_from_pnot1 */ volatile uint16_t PNOT11; /* PNOT11 */ volatile uint8_t dummy4270[2]; /* */ + /* end of struct st_gpio_from_pnot1 */ volatile uint8_t dummy4271[212]; /* */ -#define GPIO_PMSRn_COUNT 11 + +/* #define GPIO_PMSRn_COUNT (11) */ volatile uint32_t PMSR1; /* PMSR1 */ volatile uint32_t PMSR2; /* PMSR2 */ volatile uint32_t PMSR3; /* PMSR3 */ @@ -382,7 +955,8 @@ struct st_gpio volatile uint32_t PMSR10; /* PMSR10 */ volatile uint32_t PMSR11; /* PMSR11 */ volatile uint8_t dummy428[208]; /* */ -#define GPIO_PMCSRn_COUNT 12 + +/* #define GPIO_PMCSRn_COUNT (12) */ volatile uint32_t PMCSR0; /* PMCSR0 */ volatile uint32_t PMCSR1; /* PMCSR1 */ volatile uint32_t PMCSR2; /* PMCSR2 */ @@ -396,188 +970,280 @@ struct st_gpio volatile uint32_t PMCSR10; /* PMCSR10 */ volatile uint32_t PMCSR11; /* PMCSR11 */ volatile uint8_t dummy429[212]; /* */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE1; /* PFCAE1 */ volatile uint8_t dummy430[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE2; /* PFCAE2 */ volatile uint8_t dummy431[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE3; /* PFCAE3 */ volatile uint8_t dummy432[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE4; /* PFCAE4 */ volatile uint8_t dummy433[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE5; /* PFCAE5 */ volatile uint8_t dummy434[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE6; /* PFCAE6 */ volatile uint8_t dummy435[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE7; /* PFCAE7 */ volatile uint8_t dummy436[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE8; /* PFCAE8 */ volatile uint8_t dummy437[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE9; /* PFCAE9 */ volatile uint8_t dummy438[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE10; /* PFCAE10 */ volatile uint8_t dummy439[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ + /* start of struct st_gpio_from_pfcae1 */ volatile uint16_t PFCAE11; /* PFCAE11 */ volatile uint8_t dummy4400[2]; /* */ + /* end of struct st_gpio_from_pfcae1 */ volatile uint8_t dummy4401[464]; /* */ volatile uint32_t SNCR; /* SNCR */ volatile uint8_t dummy441[13308]; /* */ + +/* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC0; /* PIBC0 */ volatile uint8_t dummy442[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC1; /* PIBC1 */ volatile uint8_t dummy443[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC2; /* PIBC2 */ volatile uint8_t dummy444[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC3; /* PIBC3 */ volatile uint8_t dummy445[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC4; /* PIBC4 */ volatile uint8_t dummy446[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC5; /* PIBC5 */ volatile uint8_t dummy447[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC6; /* PIBC6 */ volatile uint8_t dummy448[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC7; /* PIBC7 */ volatile uint8_t dummy449[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC8; /* PIBC8 */ volatile uint8_t dummy450[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC9; /* PIBC9 */ volatile uint8_t dummy451[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC10; /* PIBC10 */ volatile uint8_t dummy452[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ + /* start of struct st_gpio_from_pibc1 */ volatile uint16_t PIBC11; /* PIBC11 */ volatile uint8_t dummy4530[2]; /* */ + /* end of struct st_gpio_from_pibc1 */ volatile uint8_t dummy4531[212]; /* */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC1; /* PBDC1 */ volatile uint8_t dummy454[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC2; /* PBDC2 */ volatile uint8_t dummy455[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC3; /* PBDC3 */ volatile uint8_t dummy456[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC4; /* PBDC4 */ volatile uint8_t dummy457[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC5; /* PBDC5 */ volatile uint8_t dummy458[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC6; /* PBDC6 */ volatile uint8_t dummy459[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC7; /* PBDC7 */ volatile uint8_t dummy460[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC8; /* PBDC8 */ volatile uint8_t dummy461[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC9; /* PBDC9 */ volatile uint8_t dummy462[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC10; /* PBDC10 */ volatile uint8_t dummy463[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ + /* start of struct st_gpio_from_pbdc1 */ volatile uint16_t PBDC11; /* PBDC11 */ volatile uint8_t dummy4640[2]; /* */ + /* end of struct st_gpio_from_pbdc1 */ volatile uint8_t dummy4641[212]; /* */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC1; /* PIPC1 */ volatile uint8_t dummy465[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC2; /* PIPC2 */ volatile uint8_t dummy466[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC3; /* PIPC3 */ volatile uint8_t dummy467[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC4; /* PIPC4 */ volatile uint8_t dummy468[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC5; /* PIPC5 */ volatile uint8_t dummy469[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC6; /* PIPC6 */ volatile uint8_t dummy470[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC7; /* PIPC7 */ volatile uint8_t dummy471[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC8; /* PIPC8 */ volatile uint8_t dummy472[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC9; /* PIPC9 */ volatile uint8_t dummy473[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC10; /* PIPC10 */ volatile uint8_t dummy474[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ + /* start of struct st_gpio_from_pipc1 */ volatile uint16_t PIPC11; /* PIPC11 */ volatile uint8_t dummy4750[2]; /* */ + /* end of struct st_gpio_from_pipc1 */ volatile uint8_t dummy4751[2288]; /* */ volatile uint16_t JPPR0; /* JPPR0 */ @@ -587,488 +1253,179 @@ struct st_gpio volatile uint32_t JPMCSR0; /* JPMCSR0 */ volatile uint8_t dummy478[876]; /* */ volatile uint16_t JPIBC0; /* JPIBC0 */ -}; +} r_io_gpio_t; -struct st_gpio_from_p1 +typedef struct st_gpio_from_p1 { + volatile uint16_t P1; /* P1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_gpio_from_p1_t; -struct st_gpio_from_ppr0 +typedef struct st_gpio_from_ppr0 { + volatile uint16_t PPR0; /* PPR0 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_ppr0_t; -struct st_gpio_from_pm1 +typedef struct st_gpio_from_pm1 { + volatile uint16_t PM1; /* PM1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pm1_t; -struct st_gpio_from_pmc0 +typedef struct st_gpio_from_pmc0 { + volatile uint16_t PMC0; /* PMC0 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pmc0_t; -struct st_gpio_from_pfc1 +typedef struct st_gpio_from_pfc1 { + volatile uint16_t PFC1; /* PFC1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pfc1_t; -struct st_gpio_from_pfce1 +typedef struct st_gpio_from_pfce1 { + volatile uint16_t PFCE1; /* PFCE1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pfce1_t; -struct st_gpio_from_pnot1 +typedef struct st_gpio_from_pnot1 { + volatile uint16_t PNOT1; /* PNOT1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pnot1_t; -struct st_gpio_from_pfcae1 +typedef struct st_gpio_from_pfcae1 { + volatile uint16_t PFCAE1; /* PFCAE1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pfcae1_t; -struct st_gpio_from_pibc1 +typedef struct st_gpio_from_pibc1 { + volatile uint16_t PIBC1; /* PIBC1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pibc1_t; -struct st_gpio_from_pbdc1 +typedef struct st_gpio_from_pbdc1 { + volatile uint16_t PBDC1; /* PBDC1 */ volatile uint8_t dummy1[2]; /* */ -}; +} r_io_gpio_from_pbdc1_t; -struct st_gpio_from_pipc1 +typedef struct st_gpio_from_pipc1 { + volatile uint16_t PIPC1; /* PIPC1 */ volatile uint8_t dummy1[2]; /* */ -}; - - -#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ - -/* Start of channnel array defines of GPIO */ - -/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ -#define GPIO_FROM_PIPC1_ARRAY_COUNT 11 -#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ - &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */ -#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */ -#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */ -#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */ -#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */ -#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */ -#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */ -#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */ -#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */ -#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */ -#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ - - -/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ -#define GPIO_FROM_PBDC1_ARRAY_COUNT 11 -#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ - &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */ -#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */ -#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */ -#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */ -#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */ -#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */ -#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */ -#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */ -#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */ -#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */ -#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ - - -/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ -#define GPIO_FROM_PIBC1_ARRAY_COUNT 11 -#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \ - &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ -#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ -#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ -#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */ -#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */ -#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */ -#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */ -#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */ -#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */ -#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */ -#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ - - -/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */ -/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ -#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11 -#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ - &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */ -#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */ -#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */ -#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */ -#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */ -#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */ -#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */ -#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */ -#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */ -#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */ -#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ +} r_io_gpio_from_pipc1_t; -/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */ -/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ -#define GPIO_FROM_PNOT1_ARRAY_COUNT 11 -#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ - &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */ -#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */ -#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */ -#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */ -#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */ -#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */ -#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */ -#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */ -#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */ -#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */ -#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ - +/* Channel array defines of GPIO (2)*/ +#ifdef DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pipc1* GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */ -/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */ -/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ -#define GPIO_FROM_PFCE1_ARRAY_COUNT 11 -#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ - &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */ -#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */ -#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */ -#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */ -#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */ -#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */ -#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */ -#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */ -#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */ -#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */ -#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ +#ifdef DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pbdc1* GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */ +#ifdef DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pibc1* GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */ -/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */ -/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ -#define GPIO_FROM_PFC1_ARRAY_COUNT 11 -#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ - &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */ -#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */ -#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */ -#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */ -#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */ -#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */ -#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */ -#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */ -#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */ -#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */ -#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ +#ifdef DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfcae1* GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */ +#ifdef DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS +volatile struct st_gpio_from_pnot1* GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */ -/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */ -/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ -#define GPIO_FROM_PMC0_ARRAY_COUNT 12 -#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ - &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */ -#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */ -#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */ -#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */ -#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */ -#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */ -#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */ -#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */ -#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */ -#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */ -#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */ -#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ +#ifdef DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfce1* GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */ +#ifdef DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfc1* GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */ -/* Channnel array defines of GPIO_FROM_PM1_ARRAY */ -/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ -#define GPIO_FROM_PM1_ARRAY_COUNT 11 -#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ - &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */ -#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */ -#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */ -#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */ -#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */ -#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */ -#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */ -#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */ -#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */ -#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */ -#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ +#ifdef DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS +volatile struct st_gpio_from_pmc0* GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */ +#ifdef DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS +volatile struct st_gpio_from_pm1* GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PM1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */ -/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */ -/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ -#define GPIO_FROM_PPR0_ARRAY_COUNT 12 -#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ - &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */ -#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */ -#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */ -#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */ -#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */ -#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */ -#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */ -#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */ -#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */ -#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */ -#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */ -#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ +#ifdef DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS +volatile struct st_gpio_from_ppr0* GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */ +#ifdef DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS +volatile struct st_gpio_from_p1* GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_P1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */ +/* End of channel array defines of GPIO (2)*/ -/* Channnel array defines of GPIO_FROM_P1_ARRAY */ -/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ -#define GPIO_FROM_P1_ARRAY_COUNT 11 -#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ - &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */ -#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */ -#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */ -#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */ -#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */ -#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */ -#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */ -#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */ -#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */ -#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ -#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ -/* End of channnel array defines of GPIO */ - - -#define GPIOP1 GPIO.P1 -#define GPIOP2 GPIO.P2 -#define GPIOP3 GPIO.P3 -#define GPIOP4 GPIO.P4 -#define GPIOP5 GPIO.P5 -#define GPIOP6 GPIO.P6 -#define GPIOP7 GPIO.P7 -#define GPIOP8 GPIO.P8 -#define GPIOP9 GPIO.P9 -#define GPIOP10 GPIO.P10 -#define GPIOP11 GPIO.P11 -#define GPIOPSR1 GPIO.PSR1 -#define GPIOPSR2 GPIO.PSR2 -#define GPIOPSR3 GPIO.PSR3 -#define GPIOPSR4 GPIO.PSR4 -#define GPIOPSR5 GPIO.PSR5 -#define GPIOPSR6 GPIO.PSR6 -#define GPIOPSR7 GPIO.PSR7 -#define GPIOPSR8 GPIO.PSR8 -#define GPIOPSR9 GPIO.PSR9 -#define GPIOPSR10 GPIO.PSR10 -#define GPIOPSR11 GPIO.PSR11 -#define GPIOPPR0 GPIO.PPR0 -#define GPIOPPR1 GPIO.PPR1 -#define GPIOPPR2 GPIO.PPR2 -#define GPIOPPR3 GPIO.PPR3 -#define GPIOPPR4 GPIO.PPR4 -#define GPIOPPR5 GPIO.PPR5 -#define GPIOPPR6 GPIO.PPR6 -#define GPIOPPR7 GPIO.PPR7 -#define GPIOPPR8 GPIO.PPR8 -#define GPIOPPR9 GPIO.PPR9 -#define GPIOPPR10 GPIO.PPR10 -#define GPIOPPR11 GPIO.PPR11 -#define GPIOPM1 GPIO.PM1 -#define GPIOPM2 GPIO.PM2 -#define GPIOPM3 GPIO.PM3 -#define GPIOPM4 GPIO.PM4 -#define GPIOPM5 GPIO.PM5 -#define GPIOPM6 GPIO.PM6 -#define GPIOPM7 GPIO.PM7 -#define GPIOPM8 GPIO.PM8 -#define GPIOPM9 GPIO.PM9 -#define GPIOPM10 GPIO.PM10 -#define GPIOPM11 GPIO.PM11 -#define GPIOPMC0 GPIO.PMC0 -#define GPIOPMC1 GPIO.PMC1 -#define GPIOPMC2 GPIO.PMC2 -#define GPIOPMC3 GPIO.PMC3 -#define GPIOPMC4 GPIO.PMC4 -#define GPIOPMC5 GPIO.PMC5 -#define GPIOPMC6 GPIO.PMC6 -#define GPIOPMC7 GPIO.PMC7 -#define GPIOPMC8 GPIO.PMC8 -#define GPIOPMC9 GPIO.PMC9 -#define GPIOPMC10 GPIO.PMC10 -#define GPIOPMC11 GPIO.PMC11 -#define GPIOPFC1 GPIO.PFC1 -#define GPIOPFC2 GPIO.PFC2 -#define GPIOPFC3 GPIO.PFC3 -#define GPIOPFC4 GPIO.PFC4 -#define GPIOPFC5 GPIO.PFC5 -#define GPIOPFC6 GPIO.PFC6 -#define GPIOPFC7 GPIO.PFC7 -#define GPIOPFC8 GPIO.PFC8 -#define GPIOPFC9 GPIO.PFC9 -#define GPIOPFC10 GPIO.PFC10 -#define GPIOPFC11 GPIO.PFC11 -#define GPIOPFCE1 GPIO.PFCE1 -#define GPIOPFCE2 GPIO.PFCE2 -#define GPIOPFCE3 GPIO.PFCE3 -#define GPIOPFCE4 GPIO.PFCE4 -#define GPIOPFCE5 GPIO.PFCE5 -#define GPIOPFCE6 GPIO.PFCE6 -#define GPIOPFCE7 GPIO.PFCE7 -#define GPIOPFCE8 GPIO.PFCE8 -#define GPIOPFCE9 GPIO.PFCE9 -#define GPIOPFCE10 GPIO.PFCE10 -#define GPIOPFCE11 GPIO.PFCE11 -#define GPIOPNOT1 GPIO.PNOT1 -#define GPIOPNOT2 GPIO.PNOT2 -#define GPIOPNOT3 GPIO.PNOT3 -#define GPIOPNOT4 GPIO.PNOT4 -#define GPIOPNOT5 GPIO.PNOT5 -#define GPIOPNOT6 GPIO.PNOT6 -#define GPIOPNOT7 GPIO.PNOT7 -#define GPIOPNOT8 GPIO.PNOT8 -#define GPIOPNOT9 GPIO.PNOT9 -#define GPIOPNOT10 GPIO.PNOT10 -#define GPIOPNOT11 GPIO.PNOT11 -#define GPIOPMSR1 GPIO.PMSR1 -#define GPIOPMSR2 GPIO.PMSR2 -#define GPIOPMSR3 GPIO.PMSR3 -#define GPIOPMSR4 GPIO.PMSR4 -#define GPIOPMSR5 GPIO.PMSR5 -#define GPIOPMSR6 GPIO.PMSR6 -#define GPIOPMSR7 GPIO.PMSR7 -#define GPIOPMSR8 GPIO.PMSR8 -#define GPIOPMSR9 GPIO.PMSR9 -#define GPIOPMSR10 GPIO.PMSR10 -#define GPIOPMSR11 GPIO.PMSR11 -#define GPIOPMCSR0 GPIO.PMCSR0 -#define GPIOPMCSR1 GPIO.PMCSR1 -#define GPIOPMCSR2 GPIO.PMCSR2 -#define GPIOPMCSR3 GPIO.PMCSR3 -#define GPIOPMCSR4 GPIO.PMCSR4 -#define GPIOPMCSR5 GPIO.PMCSR5 -#define GPIOPMCSR6 GPIO.PMCSR6 -#define GPIOPMCSR7 GPIO.PMCSR7 -#define GPIOPMCSR8 GPIO.PMCSR8 -#define GPIOPMCSR9 GPIO.PMCSR9 -#define GPIOPMCSR10 GPIO.PMCSR10 -#define GPIOPMCSR11 GPIO.PMCSR11 -#define GPIOPFCAE1 GPIO.PFCAE1 -#define GPIOPFCAE2 GPIO.PFCAE2 -#define GPIOPFCAE3 GPIO.PFCAE3 -#define GPIOPFCAE4 GPIO.PFCAE4 -#define GPIOPFCAE5 GPIO.PFCAE5 -#define GPIOPFCAE6 GPIO.PFCAE6 -#define GPIOPFCAE7 GPIO.PFCAE7 -#define GPIOPFCAE8 GPIO.PFCAE8 -#define GPIOPFCAE9 GPIO.PFCAE9 -#define GPIOPFCAE10 GPIO.PFCAE10 -#define GPIOPFCAE11 GPIO.PFCAE11 -#define GPIOSNCR GPIO.SNCR -#define GPIOPIBC0 GPIO.PIBC0 -#define GPIOPIBC1 GPIO.PIBC1 -#define GPIOPIBC2 GPIO.PIBC2 -#define GPIOPIBC3 GPIO.PIBC3 -#define GPIOPIBC4 GPIO.PIBC4 -#define GPIOPIBC5 GPIO.PIBC5 -#define GPIOPIBC6 GPIO.PIBC6 -#define GPIOPIBC7 GPIO.PIBC7 -#define GPIOPIBC8 GPIO.PIBC8 -#define GPIOPIBC9 GPIO.PIBC9 -#define GPIOPIBC10 GPIO.PIBC10 -#define GPIOPIBC11 GPIO.PIBC11 -#define GPIOPBDC1 GPIO.PBDC1 -#define GPIOPBDC2 GPIO.PBDC2 -#define GPIOPBDC3 GPIO.PBDC3 -#define GPIOPBDC4 GPIO.PBDC4 -#define GPIOPBDC5 GPIO.PBDC5 -#define GPIOPBDC6 GPIO.PBDC6 -#define GPIOPBDC7 GPIO.PBDC7 -#define GPIOPBDC8 GPIO.PBDC8 -#define GPIOPBDC9 GPIO.PBDC9 -#define GPIOPBDC10 GPIO.PBDC10 -#define GPIOPBDC11 GPIO.PBDC11 -#define GPIOPIPC1 GPIO.PIPC1 -#define GPIOPIPC2 GPIO.PIPC2 -#define GPIOPIPC3 GPIO.PIPC3 -#define GPIOPIPC4 GPIO.PIPC4 -#define GPIOPIPC5 GPIO.PIPC5 -#define GPIOPIPC6 GPIO.PIPC6 -#define GPIOPIPC7 GPIO.PIPC7 -#define GPIOPIPC8 GPIO.PIPC8 -#define GPIOPIPC9 GPIO.PIPC9 -#define GPIOPIPC10 GPIO.PIPC10 -#define GPIOPIPC11 GPIO.PIPC11 -#define GPIOJPPR0 GPIO.JPPR0 -#define GPIOJPMC0 GPIO.JPMC0 -#define GPIOJPMCSR0 GPIO.JPMCSR0 -#define GPIOJPIBC0 GPIO.JPIBC0 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h similarity index 83% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h index 8b76e23c6f2..5dee5fab31b 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h @@ -18,20 +18,55 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ieb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef IEB_IODEFINE_H #define IEB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ieb -{ /* IEB */ +#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ + + +#define IEBB0BCR (IEB.B0BCR) +#define IEBB0PSR (IEB.B0PSR) +#define IEBB0UAR (IEB.B0UAR) +#define IEBB0SAR (IEB.B0SAR) +#define IEBB0PAR (IEB.B0PAR) +#define IEBB0RSA (IEB.B0RSA) +#define IEBB0CDR (IEB.B0CDR) +#define IEBB0TCD (IEB.B0TCD) +#define IEBB0RCD (IEB.B0RCD) +#define IEBB0DLR (IEB.B0DLR) +#define IEBB0TDL (IEB.B0TDL) +#define IEBB0RDL (IEB.B0RDL) +#define IEBB0CKS (IEB.B0CKS) +#define IEBB0TMS (IEB.B0TMS) +#define IEBB0PCR (IEB.B0PCR) +#define IEBB0BSR (IEB.B0BSR) +#define IEBB0SSR (IEB.B0SSR) +#define IEBB0USR (IEB.B0USR) +#define IEBB0ISR (IEB.B0ISR) +#define IEBB0ESR (IEB.B0ESR) +#define IEBB0FSR (IEB.B0FSR) +#define IEBB0SCR (IEB.B0SCR) +#define IEBB0CCR (IEB.B0CCR) +#define IEBB0STC0 (IEB.B0STC0) +#define IEBB0STC1 (IEB.B0STC1) +#define IEBB0DR (IEB.B0DR) + + +typedef struct st_ieb +{ + /* IEB */ volatile uint8_t B0BCR; /* B0BCR */ volatile uint8_t dummy495[3]; /* */ volatile uint8_t B0PSR; /* B0PSR */ @@ -83,37 +118,11 @@ struct st_ieb volatile uint8_t B0STC1; /* B0STC1 */ volatile uint8_t dummy519[3]; /* */ volatile uint8_t B0DR; /* B0DR */ -}; - - -#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ +} r_io_ieb_t; -#define IEBB0BCR IEB.B0BCR -#define IEBB0PSR IEB.B0PSR -#define IEBB0UAR IEB.B0UAR -#define IEBB0SAR IEB.B0SAR -#define IEBB0PAR IEB.B0PAR -#define IEBB0RSA IEB.B0RSA -#define IEBB0CDR IEB.B0CDR -#define IEBB0TCD IEB.B0TCD -#define IEBB0RCD IEB.B0RCD -#define IEBB0DLR IEB.B0DLR -#define IEBB0TDL IEB.B0TDL -#define IEBB0RDL IEB.B0RDL -#define IEBB0CKS IEB.B0CKS -#define IEBB0TMS IEB.B0TMS -#define IEBB0PCR IEB.B0PCR -#define IEBB0BSR IEB.B0BSR -#define IEBB0SSR IEB.B0SSR -#define IEBB0USR IEB.B0USR -#define IEBB0ISR IEB.B0ISR -#define IEBB0ESR IEB.B0ESR -#define IEBB0FSR IEB.B0FSR -#define IEBB0SCR IEB.B0SCR -#define IEBB0CCR IEB.B0CCR -#define IEBB0STC0 IEB.B0STC0 -#define IEBB0STC1 IEB.B0STC1 -#define IEBB0DR IEB.B0DR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h similarity index 68% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h index f8175a69784..ea148b05d49 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h @@ -18,21 +18,61 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : inb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef INB_IODEFINE_H #define INB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_inb -{ /* INB */ +#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ + + +#define INBRMPR (INB.RMPR) +#define INBAXIBUSCTL0 (INB.AXIBUSCTL0) +#define INBAXIBUSCTL1 (INB.AXIBUSCTL1) +#define INBAXIBUSCTL2 (INB.AXIBUSCTL2) +#define INBAXIBUSCTL3 (INB.AXIBUSCTL3) +#define INBAXIBUSCTL4 (INB.AXIBUSCTL4) +#define INBAXIBUSCTL5 (INB.AXIBUSCTL5) +#define INBAXIBUSCTL6 (INB.AXIBUSCTL6) +#define INBAXIBUSCTL7 (INB.AXIBUSCTL7) +#define INBAXIBUSCTL8 (INB.AXIBUSCTL8) +#define INBAXIBUSCTL9 (INB.AXIBUSCTL9) +#define INBAXIBUSCTL10 (INB.AXIBUSCTL10) +#define INBAXIRERRCTL0 (INB.AXIRERRCTL0) +#define INBAXIRERRCTL1 (INB.AXIRERRCTL1) +#define INBAXIRERRCTL2 (INB.AXIRERRCTL2) +#define INBAXIRERRCTL3 (INB.AXIRERRCTL3) +#define INBAXIRERRST0 (INB.AXIRERRST0) +#define INBAXIRERRST1 (INB.AXIRERRST1) +#define INBAXIRERRST2 (INB.AXIRERRST2) +#define INBAXIRERRST3 (INB.AXIRERRST3) +#define INBAXIRERRCLR0 (INB.AXIRERRCLR0) +#define INBAXIRERRCLR1 (INB.AXIRERRCLR1) +#define INBAXIRERRCLR2 (INB.AXIRERRCLR2) +#define INBAXIRERRCLR3 (INB.AXIRERRCLR3) + +#define INB_AXIBUSCTLn_COUNT (11) +#define INB_AXIRERRCTLn_COUNT (4) +#define INB_AXIRERRSTn_COUNT (4) +#define INB_AXIRERRCLRn_COUNT (4) + + +typedef struct st_inb +{ + /* INB */ volatile uint32_t RMPR; /* RMPR */ -#define INB_AXIBUSCTLn_COUNT 11 + +/* #define INB_AXIBUSCTLn_COUNT (11) */ volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ @@ -44,49 +84,29 @@ struct st_inb volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */ volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ -#define INB_AXIRERRCTLn_COUNT 4 + +/* #define INB_AXIRERRCTLn_COUNT (4) */ volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ -#define INB_AXIRERRSTn_COUNT 4 + +/* #define INB_AXIRERRSTn_COUNT (4) */ volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ -#define INB_AXIRERRCLRn_COUNT 4 + +/* #define INB_AXIRERRCLRn_COUNT (4) */ volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ -}; - - -#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ +} r_io_inb_t; -#define INBRMPR INB.RMPR -#define INBAXIBUSCTL0 INB.AXIBUSCTL0 -#define INBAXIBUSCTL1 INB.AXIBUSCTL1 -#define INBAXIBUSCTL2 INB.AXIBUSCTL2 -#define INBAXIBUSCTL3 INB.AXIBUSCTL3 -#define INBAXIBUSCTL4 INB.AXIBUSCTL4 -#define INBAXIBUSCTL5 INB.AXIBUSCTL5 -#define INBAXIBUSCTL6 INB.AXIBUSCTL6 -#define INBAXIBUSCTL7 INB.AXIBUSCTL7 -#define INBAXIBUSCTL8 INB.AXIBUSCTL8 -#define INBAXIBUSCTL9 INB.AXIBUSCTL9 -#define INBAXIBUSCTL10 INB.AXIBUSCTL10 -#define INBAXIRERRCTL0 INB.AXIRERRCTL0 -#define INBAXIRERRCTL1 INB.AXIRERRCTL1 -#define INBAXIRERRCTL2 INB.AXIRERRCTL2 -#define INBAXIRERRCTL3 INB.AXIRERRCTL3 -#define INBAXIRERRST0 INB.AXIRERRST0 -#define INBAXIRERRST1 INB.AXIRERRST1 -#define INBAXIRERRST2 INB.AXIRERRST2 -#define INBAXIRERRST3 INB.AXIRERRST3 -#define INBAXIRERRCLR0 INB.AXIRERRCLR0 -#define INBAXIRERRCLR1 INB.AXIRERRCLR1 -#define INBAXIRERRCLR2 INB.AXIRERRCLR2 -#define INBAXIRERRCLR3 INB.AXIRERRCLR3 +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h similarity index 69% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h index 253d4b93995..6ee9ea1bab3 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h @@ -18,26 +18,525 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : intc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef INTC_IODEFINE_H #define INTC_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_intc -{ /* INTC */ +#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ + + +#define INTCICDDCR (INTC.ICDDCR) +#define INTCICDICTR (INTC.ICDICTR) +#define INTCICDIIDR (INTC.ICDIIDR) +#define INTCICDISR0 (INTC.ICDISR0) +#define INTCICDISR1 (INTC.ICDISR1) +#define INTCICDISR2 (INTC.ICDISR2) +#define INTCICDISR3 (INTC.ICDISR3) +#define INTCICDISR4 (INTC.ICDISR4) +#define INTCICDISR5 (INTC.ICDISR5) +#define INTCICDISR6 (INTC.ICDISR6) +#define INTCICDISR7 (INTC.ICDISR7) +#define INTCICDISR8 (INTC.ICDISR8) +#define INTCICDISR9 (INTC.ICDISR9) +#define INTCICDISR10 (INTC.ICDISR10) +#define INTCICDISR11 (INTC.ICDISR11) +#define INTCICDISR12 (INTC.ICDISR12) +#define INTCICDISR13 (INTC.ICDISR13) +#define INTCICDISR14 (INTC.ICDISR14) +#define INTCICDISR15 (INTC.ICDISR15) +#define INTCICDISR16 (INTC.ICDISR16) +#define INTCICDISR17 (INTC.ICDISR17) +#define INTCICDISR18 (INTC.ICDISR18) +#define INTCICDISER0 (INTC.ICDISER0) +#define INTCICDISER1 (INTC.ICDISER1) +#define INTCICDISER2 (INTC.ICDISER2) +#define INTCICDISER3 (INTC.ICDISER3) +#define INTCICDISER4 (INTC.ICDISER4) +#define INTCICDISER5 (INTC.ICDISER5) +#define INTCICDISER6 (INTC.ICDISER6) +#define INTCICDISER7 (INTC.ICDISER7) +#define INTCICDISER8 (INTC.ICDISER8) +#define INTCICDISER9 (INTC.ICDISER9) +#define INTCICDISER10 (INTC.ICDISER10) +#define INTCICDISER11 (INTC.ICDISER11) +#define INTCICDISER12 (INTC.ICDISER12) +#define INTCICDISER13 (INTC.ICDISER13) +#define INTCICDISER14 (INTC.ICDISER14) +#define INTCICDISER15 (INTC.ICDISER15) +#define INTCICDISER16 (INTC.ICDISER16) +#define INTCICDISER17 (INTC.ICDISER17) +#define INTCICDISER18 (INTC.ICDISER18) +#define INTCICDICER0 (INTC.ICDICER0) +#define INTCICDICER1 (INTC.ICDICER1) +#define INTCICDICER2 (INTC.ICDICER2) +#define INTCICDICER3 (INTC.ICDICER3) +#define INTCICDICER4 (INTC.ICDICER4) +#define INTCICDICER5 (INTC.ICDICER5) +#define INTCICDICER6 (INTC.ICDICER6) +#define INTCICDICER7 (INTC.ICDICER7) +#define INTCICDICER8 (INTC.ICDICER8) +#define INTCICDICER9 (INTC.ICDICER9) +#define INTCICDICER10 (INTC.ICDICER10) +#define INTCICDICER11 (INTC.ICDICER11) +#define INTCICDICER12 (INTC.ICDICER12) +#define INTCICDICER13 (INTC.ICDICER13) +#define INTCICDICER14 (INTC.ICDICER14) +#define INTCICDICER15 (INTC.ICDICER15) +#define INTCICDICER16 (INTC.ICDICER16) +#define INTCICDICER17 (INTC.ICDICER17) +#define INTCICDICER18 (INTC.ICDICER18) +#define INTCICDISPR0 (INTC.ICDISPR0) +#define INTCICDISPR1 (INTC.ICDISPR1) +#define INTCICDISPR2 (INTC.ICDISPR2) +#define INTCICDISPR3 (INTC.ICDISPR3) +#define INTCICDISPR4 (INTC.ICDISPR4) +#define INTCICDISPR5 (INTC.ICDISPR5) +#define INTCICDISPR6 (INTC.ICDISPR6) +#define INTCICDISPR7 (INTC.ICDISPR7) +#define INTCICDISPR8 (INTC.ICDISPR8) +#define INTCICDISPR9 (INTC.ICDISPR9) +#define INTCICDISPR10 (INTC.ICDISPR10) +#define INTCICDISPR11 (INTC.ICDISPR11) +#define INTCICDISPR12 (INTC.ICDISPR12) +#define INTCICDISPR13 (INTC.ICDISPR13) +#define INTCICDISPR14 (INTC.ICDISPR14) +#define INTCICDISPR15 (INTC.ICDISPR15) +#define INTCICDISPR16 (INTC.ICDISPR16) +#define INTCICDISPR17 (INTC.ICDISPR17) +#define INTCICDISPR18 (INTC.ICDISPR18) +#define INTCICDICPR0 (INTC.ICDICPR0) +#define INTCICDICPR1 (INTC.ICDICPR1) +#define INTCICDICPR2 (INTC.ICDICPR2) +#define INTCICDICPR3 (INTC.ICDICPR3) +#define INTCICDICPR4 (INTC.ICDICPR4) +#define INTCICDICPR5 (INTC.ICDICPR5) +#define INTCICDICPR6 (INTC.ICDICPR6) +#define INTCICDICPR7 (INTC.ICDICPR7) +#define INTCICDICPR8 (INTC.ICDICPR8) +#define INTCICDICPR9 (INTC.ICDICPR9) +#define INTCICDICPR10 (INTC.ICDICPR10) +#define INTCICDICPR11 (INTC.ICDICPR11) +#define INTCICDICPR12 (INTC.ICDICPR12) +#define INTCICDICPR13 (INTC.ICDICPR13) +#define INTCICDICPR14 (INTC.ICDICPR14) +#define INTCICDICPR15 (INTC.ICDICPR15) +#define INTCICDICPR16 (INTC.ICDICPR16) +#define INTCICDICPR17 (INTC.ICDICPR17) +#define INTCICDICPR18 (INTC.ICDICPR18) +#define INTCICDABR0 (INTC.ICDABR0) +#define INTCICDABR1 (INTC.ICDABR1) +#define INTCICDABR2 (INTC.ICDABR2) +#define INTCICDABR3 (INTC.ICDABR3) +#define INTCICDABR4 (INTC.ICDABR4) +#define INTCICDABR5 (INTC.ICDABR5) +#define INTCICDABR6 (INTC.ICDABR6) +#define INTCICDABR7 (INTC.ICDABR7) +#define INTCICDABR8 (INTC.ICDABR8) +#define INTCICDABR9 (INTC.ICDABR9) +#define INTCICDABR10 (INTC.ICDABR10) +#define INTCICDABR11 (INTC.ICDABR11) +#define INTCICDABR12 (INTC.ICDABR12) +#define INTCICDABR13 (INTC.ICDABR13) +#define INTCICDABR14 (INTC.ICDABR14) +#define INTCICDABR15 (INTC.ICDABR15) +#define INTCICDABR16 (INTC.ICDABR16) +#define INTCICDABR17 (INTC.ICDABR17) +#define INTCICDABR18 (INTC.ICDABR18) +#define INTCICDIPR0 (INTC.ICDIPR0) +#define INTCICDIPR1 (INTC.ICDIPR1) +#define INTCICDIPR2 (INTC.ICDIPR2) +#define INTCICDIPR3 (INTC.ICDIPR3) +#define INTCICDIPR4 (INTC.ICDIPR4) +#define INTCICDIPR5 (INTC.ICDIPR5) +#define INTCICDIPR6 (INTC.ICDIPR6) +#define INTCICDIPR7 (INTC.ICDIPR7) +#define INTCICDIPR8 (INTC.ICDIPR8) +#define INTCICDIPR9 (INTC.ICDIPR9) +#define INTCICDIPR10 (INTC.ICDIPR10) +#define INTCICDIPR11 (INTC.ICDIPR11) +#define INTCICDIPR12 (INTC.ICDIPR12) +#define INTCICDIPR13 (INTC.ICDIPR13) +#define INTCICDIPR14 (INTC.ICDIPR14) +#define INTCICDIPR15 (INTC.ICDIPR15) +#define INTCICDIPR16 (INTC.ICDIPR16) +#define INTCICDIPR17 (INTC.ICDIPR17) +#define INTCICDIPR18 (INTC.ICDIPR18) +#define INTCICDIPR19 (INTC.ICDIPR19) +#define INTCICDIPR20 (INTC.ICDIPR20) +#define INTCICDIPR21 (INTC.ICDIPR21) +#define INTCICDIPR22 (INTC.ICDIPR22) +#define INTCICDIPR23 (INTC.ICDIPR23) +#define INTCICDIPR24 (INTC.ICDIPR24) +#define INTCICDIPR25 (INTC.ICDIPR25) +#define INTCICDIPR26 (INTC.ICDIPR26) +#define INTCICDIPR27 (INTC.ICDIPR27) +#define INTCICDIPR28 (INTC.ICDIPR28) +#define INTCICDIPR29 (INTC.ICDIPR29) +#define INTCICDIPR30 (INTC.ICDIPR30) +#define INTCICDIPR31 (INTC.ICDIPR31) +#define INTCICDIPR32 (INTC.ICDIPR32) +#define INTCICDIPR33 (INTC.ICDIPR33) +#define INTCICDIPR34 (INTC.ICDIPR34) +#define INTCICDIPR35 (INTC.ICDIPR35) +#define INTCICDIPR36 (INTC.ICDIPR36) +#define INTCICDIPR37 (INTC.ICDIPR37) +#define INTCICDIPR38 (INTC.ICDIPR38) +#define INTCICDIPR39 (INTC.ICDIPR39) +#define INTCICDIPR40 (INTC.ICDIPR40) +#define INTCICDIPR41 (INTC.ICDIPR41) +#define INTCICDIPR42 (INTC.ICDIPR42) +#define INTCICDIPR43 (INTC.ICDIPR43) +#define INTCICDIPR44 (INTC.ICDIPR44) +#define INTCICDIPR45 (INTC.ICDIPR45) +#define INTCICDIPR46 (INTC.ICDIPR46) +#define INTCICDIPR47 (INTC.ICDIPR47) +#define INTCICDIPR48 (INTC.ICDIPR48) +#define INTCICDIPR49 (INTC.ICDIPR49) +#define INTCICDIPR50 (INTC.ICDIPR50) +#define INTCICDIPR51 (INTC.ICDIPR51) +#define INTCICDIPR52 (INTC.ICDIPR52) +#define INTCICDIPR53 (INTC.ICDIPR53) +#define INTCICDIPR54 (INTC.ICDIPR54) +#define INTCICDIPR55 (INTC.ICDIPR55) +#define INTCICDIPR56 (INTC.ICDIPR56) +#define INTCICDIPR57 (INTC.ICDIPR57) +#define INTCICDIPR58 (INTC.ICDIPR58) +#define INTCICDIPR59 (INTC.ICDIPR59) +#define INTCICDIPR60 (INTC.ICDIPR60) +#define INTCICDIPR61 (INTC.ICDIPR61) +#define INTCICDIPR62 (INTC.ICDIPR62) +#define INTCICDIPR63 (INTC.ICDIPR63) +#define INTCICDIPR64 (INTC.ICDIPR64) +#define INTCICDIPR65 (INTC.ICDIPR65) +#define INTCICDIPR66 (INTC.ICDIPR66) +#define INTCICDIPR67 (INTC.ICDIPR67) +#define INTCICDIPR68 (INTC.ICDIPR68) +#define INTCICDIPR69 (INTC.ICDIPR69) +#define INTCICDIPR70 (INTC.ICDIPR70) +#define INTCICDIPR71 (INTC.ICDIPR71) +#define INTCICDIPR72 (INTC.ICDIPR72) +#define INTCICDIPR73 (INTC.ICDIPR73) +#define INTCICDIPR74 (INTC.ICDIPR74) +#define INTCICDIPR75 (INTC.ICDIPR75) +#define INTCICDIPR76 (INTC.ICDIPR76) +#define INTCICDIPR77 (INTC.ICDIPR77) +#define INTCICDIPR78 (INTC.ICDIPR78) +#define INTCICDIPR79 (INTC.ICDIPR79) +#define INTCICDIPR80 (INTC.ICDIPR80) +#define INTCICDIPR81 (INTC.ICDIPR81) +#define INTCICDIPR82 (INTC.ICDIPR82) +#define INTCICDIPR83 (INTC.ICDIPR83) +#define INTCICDIPR84 (INTC.ICDIPR84) +#define INTCICDIPR85 (INTC.ICDIPR85) +#define INTCICDIPR86 (INTC.ICDIPR86) +#define INTCICDIPR87 (INTC.ICDIPR87) +#define INTCICDIPR88 (INTC.ICDIPR88) +#define INTCICDIPR89 (INTC.ICDIPR89) +#define INTCICDIPR90 (INTC.ICDIPR90) +#define INTCICDIPR91 (INTC.ICDIPR91) +#define INTCICDIPR92 (INTC.ICDIPR92) +#define INTCICDIPR93 (INTC.ICDIPR93) +#define INTCICDIPR94 (INTC.ICDIPR94) +#define INTCICDIPR95 (INTC.ICDIPR95) +#define INTCICDIPR96 (INTC.ICDIPR96) +#define INTCICDIPR97 (INTC.ICDIPR97) +#define INTCICDIPR98 (INTC.ICDIPR98) +#define INTCICDIPR99 (INTC.ICDIPR99) +#define INTCICDIPR100 (INTC.ICDIPR100) +#define INTCICDIPR101 (INTC.ICDIPR101) +#define INTCICDIPR102 (INTC.ICDIPR102) +#define INTCICDIPR103 (INTC.ICDIPR103) +#define INTCICDIPR104 (INTC.ICDIPR104) +#define INTCICDIPR105 (INTC.ICDIPR105) +#define INTCICDIPR106 (INTC.ICDIPR106) +#define INTCICDIPR107 (INTC.ICDIPR107) +#define INTCICDIPR108 (INTC.ICDIPR108) +#define INTCICDIPR109 (INTC.ICDIPR109) +#define INTCICDIPR110 (INTC.ICDIPR110) +#define INTCICDIPR111 (INTC.ICDIPR111) +#define INTCICDIPR112 (INTC.ICDIPR112) +#define INTCICDIPR113 (INTC.ICDIPR113) +#define INTCICDIPR114 (INTC.ICDIPR114) +#define INTCICDIPR115 (INTC.ICDIPR115) +#define INTCICDIPR116 (INTC.ICDIPR116) +#define INTCICDIPR117 (INTC.ICDIPR117) +#define INTCICDIPR118 (INTC.ICDIPR118) +#define INTCICDIPR119 (INTC.ICDIPR119) +#define INTCICDIPR120 (INTC.ICDIPR120) +#define INTCICDIPR121 (INTC.ICDIPR121) +#define INTCICDIPR122 (INTC.ICDIPR122) +#define INTCICDIPR123 (INTC.ICDIPR123) +#define INTCICDIPR124 (INTC.ICDIPR124) +#define INTCICDIPR125 (INTC.ICDIPR125) +#define INTCICDIPR126 (INTC.ICDIPR126) +#define INTCICDIPR127 (INTC.ICDIPR127) +#define INTCICDIPR128 (INTC.ICDIPR128) +#define INTCICDIPR129 (INTC.ICDIPR129) +#define INTCICDIPR130 (INTC.ICDIPR130) +#define INTCICDIPR131 (INTC.ICDIPR131) +#define INTCICDIPR132 (INTC.ICDIPR132) +#define INTCICDIPR133 (INTC.ICDIPR133) +#define INTCICDIPR134 (INTC.ICDIPR134) +#define INTCICDIPR135 (INTC.ICDIPR135) +#define INTCICDIPR136 (INTC.ICDIPR136) +#define INTCICDIPR137 (INTC.ICDIPR137) +#define INTCICDIPR138 (INTC.ICDIPR138) +#define INTCICDIPR139 (INTC.ICDIPR139) +#define INTCICDIPR140 (INTC.ICDIPR140) +#define INTCICDIPR141 (INTC.ICDIPR141) +#define INTCICDIPR142 (INTC.ICDIPR142) +#define INTCICDIPR143 (INTC.ICDIPR143) +#define INTCICDIPR144 (INTC.ICDIPR144) +#define INTCICDIPR145 (INTC.ICDIPR145) +#define INTCICDIPR146 (INTC.ICDIPR146) +#define INTCICDIPTR0 (INTC.ICDIPTR0) +#define INTCICDIPTR1 (INTC.ICDIPTR1) +#define INTCICDIPTR2 (INTC.ICDIPTR2) +#define INTCICDIPTR3 (INTC.ICDIPTR3) +#define INTCICDIPTR4 (INTC.ICDIPTR4) +#define INTCICDIPTR5 (INTC.ICDIPTR5) +#define INTCICDIPTR6 (INTC.ICDIPTR6) +#define INTCICDIPTR7 (INTC.ICDIPTR7) +#define INTCICDIPTR8 (INTC.ICDIPTR8) +#define INTCICDIPTR9 (INTC.ICDIPTR9) +#define INTCICDIPTR10 (INTC.ICDIPTR10) +#define INTCICDIPTR11 (INTC.ICDIPTR11) +#define INTCICDIPTR12 (INTC.ICDIPTR12) +#define INTCICDIPTR13 (INTC.ICDIPTR13) +#define INTCICDIPTR14 (INTC.ICDIPTR14) +#define INTCICDIPTR15 (INTC.ICDIPTR15) +#define INTCICDIPTR16 (INTC.ICDIPTR16) +#define INTCICDIPTR17 (INTC.ICDIPTR17) +#define INTCICDIPTR18 (INTC.ICDIPTR18) +#define INTCICDIPTR19 (INTC.ICDIPTR19) +#define INTCICDIPTR20 (INTC.ICDIPTR20) +#define INTCICDIPTR21 (INTC.ICDIPTR21) +#define INTCICDIPTR22 (INTC.ICDIPTR22) +#define INTCICDIPTR23 (INTC.ICDIPTR23) +#define INTCICDIPTR24 (INTC.ICDIPTR24) +#define INTCICDIPTR25 (INTC.ICDIPTR25) +#define INTCICDIPTR26 (INTC.ICDIPTR26) +#define INTCICDIPTR27 (INTC.ICDIPTR27) +#define INTCICDIPTR28 (INTC.ICDIPTR28) +#define INTCICDIPTR29 (INTC.ICDIPTR29) +#define INTCICDIPTR30 (INTC.ICDIPTR30) +#define INTCICDIPTR31 (INTC.ICDIPTR31) +#define INTCICDIPTR32 (INTC.ICDIPTR32) +#define INTCICDIPTR33 (INTC.ICDIPTR33) +#define INTCICDIPTR34 (INTC.ICDIPTR34) +#define INTCICDIPTR35 (INTC.ICDIPTR35) +#define INTCICDIPTR36 (INTC.ICDIPTR36) +#define INTCICDIPTR37 (INTC.ICDIPTR37) +#define INTCICDIPTR38 (INTC.ICDIPTR38) +#define INTCICDIPTR39 (INTC.ICDIPTR39) +#define INTCICDIPTR40 (INTC.ICDIPTR40) +#define INTCICDIPTR41 (INTC.ICDIPTR41) +#define INTCICDIPTR42 (INTC.ICDIPTR42) +#define INTCICDIPTR43 (INTC.ICDIPTR43) +#define INTCICDIPTR44 (INTC.ICDIPTR44) +#define INTCICDIPTR45 (INTC.ICDIPTR45) +#define INTCICDIPTR46 (INTC.ICDIPTR46) +#define INTCICDIPTR47 (INTC.ICDIPTR47) +#define INTCICDIPTR48 (INTC.ICDIPTR48) +#define INTCICDIPTR49 (INTC.ICDIPTR49) +#define INTCICDIPTR50 (INTC.ICDIPTR50) +#define INTCICDIPTR51 (INTC.ICDIPTR51) +#define INTCICDIPTR52 (INTC.ICDIPTR52) +#define INTCICDIPTR53 (INTC.ICDIPTR53) +#define INTCICDIPTR54 (INTC.ICDIPTR54) +#define INTCICDIPTR55 (INTC.ICDIPTR55) +#define INTCICDIPTR56 (INTC.ICDIPTR56) +#define INTCICDIPTR57 (INTC.ICDIPTR57) +#define INTCICDIPTR58 (INTC.ICDIPTR58) +#define INTCICDIPTR59 (INTC.ICDIPTR59) +#define INTCICDIPTR60 (INTC.ICDIPTR60) +#define INTCICDIPTR61 (INTC.ICDIPTR61) +#define INTCICDIPTR62 (INTC.ICDIPTR62) +#define INTCICDIPTR63 (INTC.ICDIPTR63) +#define INTCICDIPTR64 (INTC.ICDIPTR64) +#define INTCICDIPTR65 (INTC.ICDIPTR65) +#define INTCICDIPTR66 (INTC.ICDIPTR66) +#define INTCICDIPTR67 (INTC.ICDIPTR67) +#define INTCICDIPTR68 (INTC.ICDIPTR68) +#define INTCICDIPTR69 (INTC.ICDIPTR69) +#define INTCICDIPTR70 (INTC.ICDIPTR70) +#define INTCICDIPTR71 (INTC.ICDIPTR71) +#define INTCICDIPTR72 (INTC.ICDIPTR72) +#define INTCICDIPTR73 (INTC.ICDIPTR73) +#define INTCICDIPTR74 (INTC.ICDIPTR74) +#define INTCICDIPTR75 (INTC.ICDIPTR75) +#define INTCICDIPTR76 (INTC.ICDIPTR76) +#define INTCICDIPTR77 (INTC.ICDIPTR77) +#define INTCICDIPTR78 (INTC.ICDIPTR78) +#define INTCICDIPTR79 (INTC.ICDIPTR79) +#define INTCICDIPTR80 (INTC.ICDIPTR80) +#define INTCICDIPTR81 (INTC.ICDIPTR81) +#define INTCICDIPTR82 (INTC.ICDIPTR82) +#define INTCICDIPTR83 (INTC.ICDIPTR83) +#define INTCICDIPTR84 (INTC.ICDIPTR84) +#define INTCICDIPTR85 (INTC.ICDIPTR85) +#define INTCICDIPTR86 (INTC.ICDIPTR86) +#define INTCICDIPTR87 (INTC.ICDIPTR87) +#define INTCICDIPTR88 (INTC.ICDIPTR88) +#define INTCICDIPTR89 (INTC.ICDIPTR89) +#define INTCICDIPTR90 (INTC.ICDIPTR90) +#define INTCICDIPTR91 (INTC.ICDIPTR91) +#define INTCICDIPTR92 (INTC.ICDIPTR92) +#define INTCICDIPTR93 (INTC.ICDIPTR93) +#define INTCICDIPTR94 (INTC.ICDIPTR94) +#define INTCICDIPTR95 (INTC.ICDIPTR95) +#define INTCICDIPTR96 (INTC.ICDIPTR96) +#define INTCICDIPTR97 (INTC.ICDIPTR97) +#define INTCICDIPTR98 (INTC.ICDIPTR98) +#define INTCICDIPTR99 (INTC.ICDIPTR99) +#define INTCICDIPTR100 (INTC.ICDIPTR100) +#define INTCICDIPTR101 (INTC.ICDIPTR101) +#define INTCICDIPTR102 (INTC.ICDIPTR102) +#define INTCICDIPTR103 (INTC.ICDIPTR103) +#define INTCICDIPTR104 (INTC.ICDIPTR104) +#define INTCICDIPTR105 (INTC.ICDIPTR105) +#define INTCICDIPTR106 (INTC.ICDIPTR106) +#define INTCICDIPTR107 (INTC.ICDIPTR107) +#define INTCICDIPTR108 (INTC.ICDIPTR108) +#define INTCICDIPTR109 (INTC.ICDIPTR109) +#define INTCICDIPTR110 (INTC.ICDIPTR110) +#define INTCICDIPTR111 (INTC.ICDIPTR111) +#define INTCICDIPTR112 (INTC.ICDIPTR112) +#define INTCICDIPTR113 (INTC.ICDIPTR113) +#define INTCICDIPTR114 (INTC.ICDIPTR114) +#define INTCICDIPTR115 (INTC.ICDIPTR115) +#define INTCICDIPTR116 (INTC.ICDIPTR116) +#define INTCICDIPTR117 (INTC.ICDIPTR117) +#define INTCICDIPTR118 (INTC.ICDIPTR118) +#define INTCICDIPTR119 (INTC.ICDIPTR119) +#define INTCICDIPTR120 (INTC.ICDIPTR120) +#define INTCICDIPTR121 (INTC.ICDIPTR121) +#define INTCICDIPTR122 (INTC.ICDIPTR122) +#define INTCICDIPTR123 (INTC.ICDIPTR123) +#define INTCICDIPTR124 (INTC.ICDIPTR124) +#define INTCICDIPTR125 (INTC.ICDIPTR125) +#define INTCICDIPTR126 (INTC.ICDIPTR126) +#define INTCICDIPTR127 (INTC.ICDIPTR127) +#define INTCICDIPTR128 (INTC.ICDIPTR128) +#define INTCICDIPTR129 (INTC.ICDIPTR129) +#define INTCICDIPTR130 (INTC.ICDIPTR130) +#define INTCICDIPTR131 (INTC.ICDIPTR131) +#define INTCICDIPTR132 (INTC.ICDIPTR132) +#define INTCICDIPTR133 (INTC.ICDIPTR133) +#define INTCICDIPTR134 (INTC.ICDIPTR134) +#define INTCICDIPTR135 (INTC.ICDIPTR135) +#define INTCICDIPTR136 (INTC.ICDIPTR136) +#define INTCICDIPTR137 (INTC.ICDIPTR137) +#define INTCICDIPTR138 (INTC.ICDIPTR138) +#define INTCICDIPTR139 (INTC.ICDIPTR139) +#define INTCICDIPTR140 (INTC.ICDIPTR140) +#define INTCICDIPTR141 (INTC.ICDIPTR141) +#define INTCICDIPTR142 (INTC.ICDIPTR142) +#define INTCICDIPTR143 (INTC.ICDIPTR143) +#define INTCICDIPTR144 (INTC.ICDIPTR144) +#define INTCICDIPTR145 (INTC.ICDIPTR145) +#define INTCICDIPTR146 (INTC.ICDIPTR146) +#define INTCICDICFR0 (INTC.ICDICFR0) +#define INTCICDICFR1 (INTC.ICDICFR1) +#define INTCICDICFR2 (INTC.ICDICFR2) +#define INTCICDICFR3 (INTC.ICDICFR3) +#define INTCICDICFR4 (INTC.ICDICFR4) +#define INTCICDICFR5 (INTC.ICDICFR5) +#define INTCICDICFR6 (INTC.ICDICFR6) +#define INTCICDICFR7 (INTC.ICDICFR7) +#define INTCICDICFR8 (INTC.ICDICFR8) +#define INTCICDICFR9 (INTC.ICDICFR9) +#define INTCICDICFR10 (INTC.ICDICFR10) +#define INTCICDICFR11 (INTC.ICDICFR11) +#define INTCICDICFR12 (INTC.ICDICFR12) +#define INTCICDICFR13 (INTC.ICDICFR13) +#define INTCICDICFR14 (INTC.ICDICFR14) +#define INTCICDICFR15 (INTC.ICDICFR15) +#define INTCICDICFR16 (INTC.ICDICFR16) +#define INTCICDICFR17 (INTC.ICDICFR17) +#define INTCICDICFR18 (INTC.ICDICFR18) +#define INTCICDICFR19 (INTC.ICDICFR19) +#define INTCICDICFR20 (INTC.ICDICFR20) +#define INTCICDICFR21 (INTC.ICDICFR21) +#define INTCICDICFR22 (INTC.ICDICFR22) +#define INTCICDICFR23 (INTC.ICDICFR23) +#define INTCICDICFR24 (INTC.ICDICFR24) +#define INTCICDICFR25 (INTC.ICDICFR25) +#define INTCICDICFR26 (INTC.ICDICFR26) +#define INTCICDICFR27 (INTC.ICDICFR27) +#define INTCICDICFR28 (INTC.ICDICFR28) +#define INTCICDICFR29 (INTC.ICDICFR29) +#define INTCICDICFR30 (INTC.ICDICFR30) +#define INTCICDICFR31 (INTC.ICDICFR31) +#define INTCICDICFR32 (INTC.ICDICFR32) +#define INTCICDICFR33 (INTC.ICDICFR33) +#define INTCICDICFR34 (INTC.ICDICFR34) +#define INTCICDICFR35 (INTC.ICDICFR35) +#define INTCICDICFR36 (INTC.ICDICFR36) +#define INTCPPI_STATUS (INTC.PPI_STATUS) +#define INTCSPI_STATUS0 (INTC.SPI_STATUS0) +#define INTCSPI_STATUS1 (INTC.SPI_STATUS1) +#define INTCSPI_STATUS2 (INTC.SPI_STATUS2) +#define INTCSPI_STATUS3 (INTC.SPI_STATUS3) +#define INTCSPI_STATUS4 (INTC.SPI_STATUS4) +#define INTCSPI_STATUS5 (INTC.SPI_STATUS5) +#define INTCSPI_STATUS6 (INTC.SPI_STATUS6) +#define INTCSPI_STATUS7 (INTC.SPI_STATUS7) +#define INTCSPI_STATUS8 (INTC.SPI_STATUS8) +#define INTCSPI_STATUS9 (INTC.SPI_STATUS9) +#define INTCSPI_STATUS10 (INTC.SPI_STATUS10) +#define INTCSPI_STATUS11 (INTC.SPI_STATUS11) +#define INTCSPI_STATUS12 (INTC.SPI_STATUS12) +#define INTCSPI_STATUS13 (INTC.SPI_STATUS13) +#define INTCSPI_STATUS14 (INTC.SPI_STATUS14) +#define INTCSPI_STATUS15 (INTC.SPI_STATUS15) +#define INTCSPI_STATUS16 (INTC.SPI_STATUS16) +#define INTCICDSGIR (INTC.ICDSGIR) +#define INTCICCICR (INTC.ICCICR) +#define INTCICCPMR (INTC.ICCPMR) +#define INTCICCBPR (INTC.ICCBPR) +#define INTCICCIAR (INTC.ICCIAR) +#define INTCICCEOIR (INTC.ICCEOIR) +#define INTCICCRPR (INTC.ICCRPR) +#define INTCICCHPIR (INTC.ICCHPIR) +#define INTCICCABPR (INTC.ICCABPR) +#define INTCICCIIDR (INTC.ICCIIDR) +#define INTCICR0 (INTC.ICR0) +#define INTCICR1 (INTC.ICR1) +#define INTCIRQRR (INTC.IRQRR) + +#define INTC_ICDISR0_COUNT (19) +#define INTC_ICDISER0_COUNT (19) +#define INTC_ICDICER0_COUNT (19) +#define INTC_ICDISPR0_COUNT (19) +#define INTC_ICDICPR0_COUNT (19) +#define INTC_ICDABR0_COUNT (19) +#define INTC_ICDIPR0_COUNT (147) +#define INTC_ICDIPTR0_COUNT (147) +#define INTC_ICDICFR0_COUNT (37) +#define INTC_SPI_STATUS0_COUNT (17) + + +typedef struct st_intc +{ + /* INTC */ volatile uint32_t ICDDCR; /* ICDDCR */ volatile uint32_t ICDICTR; /* ICDICTR */ volatile uint32_t ICDIIDR; /* ICDIIDR */ volatile uint8_t dummy193[116]; /* */ -#define INTC_ICDISR0_COUNT 19 + +/* #define INTC_ICDISR0_COUNT (19) */ volatile uint32_t ICDISR0; /* ICDISR0 */ volatile uint32_t ICDISR1; /* ICDISR1 */ volatile uint32_t ICDISR2; /* ICDISR2 */ @@ -58,7 +557,8 @@ struct st_intc volatile uint32_t ICDISR17; /* ICDISR17 */ volatile uint32_t ICDISR18; /* ICDISR18 */ volatile uint8_t dummy194[52]; /* */ -#define INTC_ICDISER0_COUNT 19 + +/* #define INTC_ICDISER0_COUNT (19) */ volatile uint32_t ICDISER0; /* ICDISER0 */ volatile uint32_t ICDISER1; /* ICDISER1 */ volatile uint32_t ICDISER2; /* ICDISER2 */ @@ -79,7 +579,8 @@ struct st_intc volatile uint32_t ICDISER17; /* ICDISER17 */ volatile uint32_t ICDISER18; /* ICDISER18 */ volatile uint8_t dummy195[52]; /* */ -#define INTC_ICDICER0_COUNT 19 + +/* #define INTC_ICDICER0_COUNT (19) */ volatile uint32_t ICDICER0; /* ICDICER0 */ volatile uint32_t ICDICER1; /* ICDICER1 */ volatile uint32_t ICDICER2; /* ICDICER2 */ @@ -100,7 +601,8 @@ struct st_intc volatile uint32_t ICDICER17; /* ICDICER17 */ volatile uint32_t ICDICER18; /* ICDICER18 */ volatile uint8_t dummy196[52]; /* */ -#define INTC_ICDISPR0_COUNT 19 + +/* #define INTC_ICDISPR0_COUNT (19) */ volatile uint32_t ICDISPR0; /* ICDISPR0 */ volatile uint32_t ICDISPR1; /* ICDISPR1 */ volatile uint32_t ICDISPR2; /* ICDISPR2 */ @@ -121,7 +623,8 @@ struct st_intc volatile uint32_t ICDISPR17; /* ICDISPR17 */ volatile uint32_t ICDISPR18; /* ICDISPR18 */ volatile uint8_t dummy197[52]; /* */ -#define INTC_ICDICPR0_COUNT 19 + +/* #define INTC_ICDICPR0_COUNT (19) */ volatile uint32_t ICDICPR0; /* ICDICPR0 */ volatile uint32_t ICDICPR1; /* ICDICPR1 */ volatile uint32_t ICDICPR2; /* ICDICPR2 */ @@ -142,7 +645,8 @@ struct st_intc volatile uint32_t ICDICPR17; /* ICDICPR17 */ volatile uint32_t ICDICPR18; /* ICDICPR18 */ volatile uint8_t dummy198[52]; /* */ -#define INTC_ICDABR0_COUNT 19 + +/* #define INTC_ICDABR0_COUNT (19) */ volatile uint32_t ICDABR0; /* ICDABR0 */ volatile uint32_t ICDABR1; /* ICDABR1 */ volatile uint32_t ICDABR2; /* ICDABR2 */ @@ -163,7 +667,8 @@ struct st_intc volatile uint32_t ICDABR17; /* ICDABR17 */ volatile uint32_t ICDABR18; /* ICDABR18 */ volatile uint8_t dummy199[180]; /* */ -#define INTC_ICDIPR0_COUNT 147 + +/* #define INTC_ICDIPR0_COUNT (147) */ volatile uint32_t ICDIPR0; /* ICDIPR0 */ volatile uint32_t ICDIPR1; /* ICDIPR1 */ volatile uint32_t ICDIPR2; /* ICDIPR2 */ @@ -312,7 +817,8 @@ struct st_intc volatile uint32_t ICDIPR145; /* ICDIPR145 */ volatile uint32_t ICDIPR146; /* ICDIPR146 */ volatile uint8_t dummy200[436]; /* */ -#define INTC_ICDIPTR0_COUNT 147 + +/* #define INTC_ICDIPTR0_COUNT (147) */ volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ @@ -461,7 +967,8 @@ struct st_intc volatile uint32_t ICDIPTR145; /* ICDIPTR145 */ volatile uint32_t ICDIPTR146; /* ICDIPTR146 */ volatile uint8_t dummy201[436]; /* */ -#define INTC_ICDICFR0_COUNT 37 + +/* #define INTC_ICDICFR0_COUNT (37) */ volatile uint32_t ICDICFR0; /* ICDICFR0 */ volatile uint32_t ICDICFR1; /* ICDICFR1 */ volatile uint32_t ICDICFR2; /* ICDICFR2 */ @@ -501,7 +1008,8 @@ struct st_intc volatile uint32_t ICDICFR36; /* ICDICFR36 */ volatile uint8_t dummy202[108]; /* */ volatile uint32_t PPI_STATUS; /* PPI_STATUS */ -#define INTC_SPI_STATUS0_COUNT 17 + +/* #define INTC_SPI_STATUS0_COUNT (17) */ volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ @@ -536,491 +1044,11 @@ struct st_intc volatile uint16_t ICR0; /* ICR0 */ volatile uint16_t ICR1; /* ICR1 */ volatile uint16_t IRQRR; /* IRQRR */ -}; - - -#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ +} r_io_intc_t; -#define INTCICDDCR INTC.ICDDCR -#define INTCICDICTR INTC.ICDICTR -#define INTCICDIIDR INTC.ICDIIDR -#define INTCICDISR0 INTC.ICDISR0 -#define INTCICDISR1 INTC.ICDISR1 -#define INTCICDISR2 INTC.ICDISR2 -#define INTCICDISR3 INTC.ICDISR3 -#define INTCICDISR4 INTC.ICDISR4 -#define INTCICDISR5 INTC.ICDISR5 -#define INTCICDISR6 INTC.ICDISR6 -#define INTCICDISR7 INTC.ICDISR7 -#define INTCICDISR8 INTC.ICDISR8 -#define INTCICDISR9 INTC.ICDISR9 -#define INTCICDISR10 INTC.ICDISR10 -#define INTCICDISR11 INTC.ICDISR11 -#define INTCICDISR12 INTC.ICDISR12 -#define INTCICDISR13 INTC.ICDISR13 -#define INTCICDISR14 INTC.ICDISR14 -#define INTCICDISR15 INTC.ICDISR15 -#define INTCICDISR16 INTC.ICDISR16 -#define INTCICDISR17 INTC.ICDISR17 -#define INTCICDISR18 INTC.ICDISR18 -#define INTCICDISER0 INTC.ICDISER0 -#define INTCICDISER1 INTC.ICDISER1 -#define INTCICDISER2 INTC.ICDISER2 -#define INTCICDISER3 INTC.ICDISER3 -#define INTCICDISER4 INTC.ICDISER4 -#define INTCICDISER5 INTC.ICDISER5 -#define INTCICDISER6 INTC.ICDISER6 -#define INTCICDISER7 INTC.ICDISER7 -#define INTCICDISER8 INTC.ICDISER8 -#define INTCICDISER9 INTC.ICDISER9 -#define INTCICDISER10 INTC.ICDISER10 -#define INTCICDISER11 INTC.ICDISER11 -#define INTCICDISER12 INTC.ICDISER12 -#define INTCICDISER13 INTC.ICDISER13 -#define INTCICDISER14 INTC.ICDISER14 -#define INTCICDISER15 INTC.ICDISER15 -#define INTCICDISER16 INTC.ICDISER16 -#define INTCICDISER17 INTC.ICDISER17 -#define INTCICDISER18 INTC.ICDISER18 -#define INTCICDICER0 INTC.ICDICER0 -#define INTCICDICER1 INTC.ICDICER1 -#define INTCICDICER2 INTC.ICDICER2 -#define INTCICDICER3 INTC.ICDICER3 -#define INTCICDICER4 INTC.ICDICER4 -#define INTCICDICER5 INTC.ICDICER5 -#define INTCICDICER6 INTC.ICDICER6 -#define INTCICDICER7 INTC.ICDICER7 -#define INTCICDICER8 INTC.ICDICER8 -#define INTCICDICER9 INTC.ICDICER9 -#define INTCICDICER10 INTC.ICDICER10 -#define INTCICDICER11 INTC.ICDICER11 -#define INTCICDICER12 INTC.ICDICER12 -#define INTCICDICER13 INTC.ICDICER13 -#define INTCICDICER14 INTC.ICDICER14 -#define INTCICDICER15 INTC.ICDICER15 -#define INTCICDICER16 INTC.ICDICER16 -#define INTCICDICER17 INTC.ICDICER17 -#define INTCICDICER18 INTC.ICDICER18 -#define INTCICDISPR0 INTC.ICDISPR0 -#define INTCICDISPR1 INTC.ICDISPR1 -#define INTCICDISPR2 INTC.ICDISPR2 -#define INTCICDISPR3 INTC.ICDISPR3 -#define INTCICDISPR4 INTC.ICDISPR4 -#define INTCICDISPR5 INTC.ICDISPR5 -#define INTCICDISPR6 INTC.ICDISPR6 -#define INTCICDISPR7 INTC.ICDISPR7 -#define INTCICDISPR8 INTC.ICDISPR8 -#define INTCICDISPR9 INTC.ICDISPR9 -#define INTCICDISPR10 INTC.ICDISPR10 -#define INTCICDISPR11 INTC.ICDISPR11 -#define INTCICDISPR12 INTC.ICDISPR12 -#define INTCICDISPR13 INTC.ICDISPR13 -#define INTCICDISPR14 INTC.ICDISPR14 -#define INTCICDISPR15 INTC.ICDISPR15 -#define INTCICDISPR16 INTC.ICDISPR16 -#define INTCICDISPR17 INTC.ICDISPR17 -#define INTCICDISPR18 INTC.ICDISPR18 -#define INTCICDICPR0 INTC.ICDICPR0 -#define INTCICDICPR1 INTC.ICDICPR1 -#define INTCICDICPR2 INTC.ICDICPR2 -#define INTCICDICPR3 INTC.ICDICPR3 -#define INTCICDICPR4 INTC.ICDICPR4 -#define INTCICDICPR5 INTC.ICDICPR5 -#define INTCICDICPR6 INTC.ICDICPR6 -#define INTCICDICPR7 INTC.ICDICPR7 -#define INTCICDICPR8 INTC.ICDICPR8 -#define INTCICDICPR9 INTC.ICDICPR9 -#define INTCICDICPR10 INTC.ICDICPR10 -#define INTCICDICPR11 INTC.ICDICPR11 -#define INTCICDICPR12 INTC.ICDICPR12 -#define INTCICDICPR13 INTC.ICDICPR13 -#define INTCICDICPR14 INTC.ICDICPR14 -#define INTCICDICPR15 INTC.ICDICPR15 -#define INTCICDICPR16 INTC.ICDICPR16 -#define INTCICDICPR17 INTC.ICDICPR17 -#define INTCICDICPR18 INTC.ICDICPR18 -#define INTCICDABR0 INTC.ICDABR0 -#define INTCICDABR1 INTC.ICDABR1 -#define INTCICDABR2 INTC.ICDABR2 -#define INTCICDABR3 INTC.ICDABR3 -#define INTCICDABR4 INTC.ICDABR4 -#define INTCICDABR5 INTC.ICDABR5 -#define INTCICDABR6 INTC.ICDABR6 -#define INTCICDABR7 INTC.ICDABR7 -#define INTCICDABR8 INTC.ICDABR8 -#define INTCICDABR9 INTC.ICDABR9 -#define INTCICDABR10 INTC.ICDABR10 -#define INTCICDABR11 INTC.ICDABR11 -#define INTCICDABR12 INTC.ICDABR12 -#define INTCICDABR13 INTC.ICDABR13 -#define INTCICDABR14 INTC.ICDABR14 -#define INTCICDABR15 INTC.ICDABR15 -#define INTCICDABR16 INTC.ICDABR16 -#define INTCICDABR17 INTC.ICDABR17 -#define INTCICDABR18 INTC.ICDABR18 -#define INTCICDIPR0 INTC.ICDIPR0 -#define INTCICDIPR1 INTC.ICDIPR1 -#define INTCICDIPR2 INTC.ICDIPR2 -#define INTCICDIPR3 INTC.ICDIPR3 -#define INTCICDIPR4 INTC.ICDIPR4 -#define INTCICDIPR5 INTC.ICDIPR5 -#define INTCICDIPR6 INTC.ICDIPR6 -#define INTCICDIPR7 INTC.ICDIPR7 -#define INTCICDIPR8 INTC.ICDIPR8 -#define INTCICDIPR9 INTC.ICDIPR9 -#define INTCICDIPR10 INTC.ICDIPR10 -#define INTCICDIPR11 INTC.ICDIPR11 -#define INTCICDIPR12 INTC.ICDIPR12 -#define INTCICDIPR13 INTC.ICDIPR13 -#define INTCICDIPR14 INTC.ICDIPR14 -#define INTCICDIPR15 INTC.ICDIPR15 -#define INTCICDIPR16 INTC.ICDIPR16 -#define INTCICDIPR17 INTC.ICDIPR17 -#define INTCICDIPR18 INTC.ICDIPR18 -#define INTCICDIPR19 INTC.ICDIPR19 -#define INTCICDIPR20 INTC.ICDIPR20 -#define INTCICDIPR21 INTC.ICDIPR21 -#define INTCICDIPR22 INTC.ICDIPR22 -#define INTCICDIPR23 INTC.ICDIPR23 -#define INTCICDIPR24 INTC.ICDIPR24 -#define INTCICDIPR25 INTC.ICDIPR25 -#define INTCICDIPR26 INTC.ICDIPR26 -#define INTCICDIPR27 INTC.ICDIPR27 -#define INTCICDIPR28 INTC.ICDIPR28 -#define INTCICDIPR29 INTC.ICDIPR29 -#define INTCICDIPR30 INTC.ICDIPR30 -#define INTCICDIPR31 INTC.ICDIPR31 -#define INTCICDIPR32 INTC.ICDIPR32 -#define INTCICDIPR33 INTC.ICDIPR33 -#define INTCICDIPR34 INTC.ICDIPR34 -#define INTCICDIPR35 INTC.ICDIPR35 -#define INTCICDIPR36 INTC.ICDIPR36 -#define INTCICDIPR37 INTC.ICDIPR37 -#define INTCICDIPR38 INTC.ICDIPR38 -#define INTCICDIPR39 INTC.ICDIPR39 -#define INTCICDIPR40 INTC.ICDIPR40 -#define INTCICDIPR41 INTC.ICDIPR41 -#define INTCICDIPR42 INTC.ICDIPR42 -#define INTCICDIPR43 INTC.ICDIPR43 -#define INTCICDIPR44 INTC.ICDIPR44 -#define INTCICDIPR45 INTC.ICDIPR45 -#define INTCICDIPR46 INTC.ICDIPR46 -#define INTCICDIPR47 INTC.ICDIPR47 -#define INTCICDIPR48 INTC.ICDIPR48 -#define INTCICDIPR49 INTC.ICDIPR49 -#define INTCICDIPR50 INTC.ICDIPR50 -#define INTCICDIPR51 INTC.ICDIPR51 -#define INTCICDIPR52 INTC.ICDIPR52 -#define INTCICDIPR53 INTC.ICDIPR53 -#define INTCICDIPR54 INTC.ICDIPR54 -#define INTCICDIPR55 INTC.ICDIPR55 -#define INTCICDIPR56 INTC.ICDIPR56 -#define INTCICDIPR57 INTC.ICDIPR57 -#define INTCICDIPR58 INTC.ICDIPR58 -#define INTCICDIPR59 INTC.ICDIPR59 -#define INTCICDIPR60 INTC.ICDIPR60 -#define INTCICDIPR61 INTC.ICDIPR61 -#define INTCICDIPR62 INTC.ICDIPR62 -#define INTCICDIPR63 INTC.ICDIPR63 -#define INTCICDIPR64 INTC.ICDIPR64 -#define INTCICDIPR65 INTC.ICDIPR65 -#define INTCICDIPR66 INTC.ICDIPR66 -#define INTCICDIPR67 INTC.ICDIPR67 -#define INTCICDIPR68 INTC.ICDIPR68 -#define INTCICDIPR69 INTC.ICDIPR69 -#define INTCICDIPR70 INTC.ICDIPR70 -#define INTCICDIPR71 INTC.ICDIPR71 -#define INTCICDIPR72 INTC.ICDIPR72 -#define INTCICDIPR73 INTC.ICDIPR73 -#define INTCICDIPR74 INTC.ICDIPR74 -#define INTCICDIPR75 INTC.ICDIPR75 -#define INTCICDIPR76 INTC.ICDIPR76 -#define INTCICDIPR77 INTC.ICDIPR77 -#define INTCICDIPR78 INTC.ICDIPR78 -#define INTCICDIPR79 INTC.ICDIPR79 -#define INTCICDIPR80 INTC.ICDIPR80 -#define INTCICDIPR81 INTC.ICDIPR81 -#define INTCICDIPR82 INTC.ICDIPR82 -#define INTCICDIPR83 INTC.ICDIPR83 -#define INTCICDIPR84 INTC.ICDIPR84 -#define INTCICDIPR85 INTC.ICDIPR85 -#define INTCICDIPR86 INTC.ICDIPR86 -#define INTCICDIPR87 INTC.ICDIPR87 -#define INTCICDIPR88 INTC.ICDIPR88 -#define INTCICDIPR89 INTC.ICDIPR89 -#define INTCICDIPR90 INTC.ICDIPR90 -#define INTCICDIPR91 INTC.ICDIPR91 -#define INTCICDIPR92 INTC.ICDIPR92 -#define INTCICDIPR93 INTC.ICDIPR93 -#define INTCICDIPR94 INTC.ICDIPR94 -#define INTCICDIPR95 INTC.ICDIPR95 -#define INTCICDIPR96 INTC.ICDIPR96 -#define INTCICDIPR97 INTC.ICDIPR97 -#define INTCICDIPR98 INTC.ICDIPR98 -#define INTCICDIPR99 INTC.ICDIPR99 -#define INTCICDIPR100 INTC.ICDIPR100 -#define INTCICDIPR101 INTC.ICDIPR101 -#define INTCICDIPR102 INTC.ICDIPR102 -#define INTCICDIPR103 INTC.ICDIPR103 -#define INTCICDIPR104 INTC.ICDIPR104 -#define INTCICDIPR105 INTC.ICDIPR105 -#define INTCICDIPR106 INTC.ICDIPR106 -#define INTCICDIPR107 INTC.ICDIPR107 -#define INTCICDIPR108 INTC.ICDIPR108 -#define INTCICDIPR109 INTC.ICDIPR109 -#define INTCICDIPR110 INTC.ICDIPR110 -#define INTCICDIPR111 INTC.ICDIPR111 -#define INTCICDIPR112 INTC.ICDIPR112 -#define INTCICDIPR113 INTC.ICDIPR113 -#define INTCICDIPR114 INTC.ICDIPR114 -#define INTCICDIPR115 INTC.ICDIPR115 -#define INTCICDIPR116 INTC.ICDIPR116 -#define INTCICDIPR117 INTC.ICDIPR117 -#define INTCICDIPR118 INTC.ICDIPR118 -#define INTCICDIPR119 INTC.ICDIPR119 -#define INTCICDIPR120 INTC.ICDIPR120 -#define INTCICDIPR121 INTC.ICDIPR121 -#define INTCICDIPR122 INTC.ICDIPR122 -#define INTCICDIPR123 INTC.ICDIPR123 -#define INTCICDIPR124 INTC.ICDIPR124 -#define INTCICDIPR125 INTC.ICDIPR125 -#define INTCICDIPR126 INTC.ICDIPR126 -#define INTCICDIPR127 INTC.ICDIPR127 -#define INTCICDIPR128 INTC.ICDIPR128 -#define INTCICDIPR129 INTC.ICDIPR129 -#define INTCICDIPR130 INTC.ICDIPR130 -#define INTCICDIPR131 INTC.ICDIPR131 -#define INTCICDIPR132 INTC.ICDIPR132 -#define INTCICDIPR133 INTC.ICDIPR133 -#define INTCICDIPR134 INTC.ICDIPR134 -#define INTCICDIPR135 INTC.ICDIPR135 -#define INTCICDIPR136 INTC.ICDIPR136 -#define INTCICDIPR137 INTC.ICDIPR137 -#define INTCICDIPR138 INTC.ICDIPR138 -#define INTCICDIPR139 INTC.ICDIPR139 -#define INTCICDIPR140 INTC.ICDIPR140 -#define INTCICDIPR141 INTC.ICDIPR141 -#define INTCICDIPR142 INTC.ICDIPR142 -#define INTCICDIPR143 INTC.ICDIPR143 -#define INTCICDIPR144 INTC.ICDIPR144 -#define INTCICDIPR145 INTC.ICDIPR145 -#define INTCICDIPR146 INTC.ICDIPR146 -#define INTCICDIPTR0 INTC.ICDIPTR0 -#define INTCICDIPTR1 INTC.ICDIPTR1 -#define INTCICDIPTR2 INTC.ICDIPTR2 -#define INTCICDIPTR3 INTC.ICDIPTR3 -#define INTCICDIPTR4 INTC.ICDIPTR4 -#define INTCICDIPTR5 INTC.ICDIPTR5 -#define INTCICDIPTR6 INTC.ICDIPTR6 -#define INTCICDIPTR7 INTC.ICDIPTR7 -#define INTCICDIPTR8 INTC.ICDIPTR8 -#define INTCICDIPTR9 INTC.ICDIPTR9 -#define INTCICDIPTR10 INTC.ICDIPTR10 -#define INTCICDIPTR11 INTC.ICDIPTR11 -#define INTCICDIPTR12 INTC.ICDIPTR12 -#define INTCICDIPTR13 INTC.ICDIPTR13 -#define INTCICDIPTR14 INTC.ICDIPTR14 -#define INTCICDIPTR15 INTC.ICDIPTR15 -#define INTCICDIPTR16 INTC.ICDIPTR16 -#define INTCICDIPTR17 INTC.ICDIPTR17 -#define INTCICDIPTR18 INTC.ICDIPTR18 -#define INTCICDIPTR19 INTC.ICDIPTR19 -#define INTCICDIPTR20 INTC.ICDIPTR20 -#define INTCICDIPTR21 INTC.ICDIPTR21 -#define INTCICDIPTR22 INTC.ICDIPTR22 -#define INTCICDIPTR23 INTC.ICDIPTR23 -#define INTCICDIPTR24 INTC.ICDIPTR24 -#define INTCICDIPTR25 INTC.ICDIPTR25 -#define INTCICDIPTR26 INTC.ICDIPTR26 -#define INTCICDIPTR27 INTC.ICDIPTR27 -#define INTCICDIPTR28 INTC.ICDIPTR28 -#define INTCICDIPTR29 INTC.ICDIPTR29 -#define INTCICDIPTR30 INTC.ICDIPTR30 -#define INTCICDIPTR31 INTC.ICDIPTR31 -#define INTCICDIPTR32 INTC.ICDIPTR32 -#define INTCICDIPTR33 INTC.ICDIPTR33 -#define INTCICDIPTR34 INTC.ICDIPTR34 -#define INTCICDIPTR35 INTC.ICDIPTR35 -#define INTCICDIPTR36 INTC.ICDIPTR36 -#define INTCICDIPTR37 INTC.ICDIPTR37 -#define INTCICDIPTR38 INTC.ICDIPTR38 -#define INTCICDIPTR39 INTC.ICDIPTR39 -#define INTCICDIPTR40 INTC.ICDIPTR40 -#define INTCICDIPTR41 INTC.ICDIPTR41 -#define INTCICDIPTR42 INTC.ICDIPTR42 -#define INTCICDIPTR43 INTC.ICDIPTR43 -#define INTCICDIPTR44 INTC.ICDIPTR44 -#define INTCICDIPTR45 INTC.ICDIPTR45 -#define INTCICDIPTR46 INTC.ICDIPTR46 -#define INTCICDIPTR47 INTC.ICDIPTR47 -#define INTCICDIPTR48 INTC.ICDIPTR48 -#define INTCICDIPTR49 INTC.ICDIPTR49 -#define INTCICDIPTR50 INTC.ICDIPTR50 -#define INTCICDIPTR51 INTC.ICDIPTR51 -#define INTCICDIPTR52 INTC.ICDIPTR52 -#define INTCICDIPTR53 INTC.ICDIPTR53 -#define INTCICDIPTR54 INTC.ICDIPTR54 -#define INTCICDIPTR55 INTC.ICDIPTR55 -#define INTCICDIPTR56 INTC.ICDIPTR56 -#define INTCICDIPTR57 INTC.ICDIPTR57 -#define INTCICDIPTR58 INTC.ICDIPTR58 -#define INTCICDIPTR59 INTC.ICDIPTR59 -#define INTCICDIPTR60 INTC.ICDIPTR60 -#define INTCICDIPTR61 INTC.ICDIPTR61 -#define INTCICDIPTR62 INTC.ICDIPTR62 -#define INTCICDIPTR63 INTC.ICDIPTR63 -#define INTCICDIPTR64 INTC.ICDIPTR64 -#define INTCICDIPTR65 INTC.ICDIPTR65 -#define INTCICDIPTR66 INTC.ICDIPTR66 -#define INTCICDIPTR67 INTC.ICDIPTR67 -#define INTCICDIPTR68 INTC.ICDIPTR68 -#define INTCICDIPTR69 INTC.ICDIPTR69 -#define INTCICDIPTR70 INTC.ICDIPTR70 -#define INTCICDIPTR71 INTC.ICDIPTR71 -#define INTCICDIPTR72 INTC.ICDIPTR72 -#define INTCICDIPTR73 INTC.ICDIPTR73 -#define INTCICDIPTR74 INTC.ICDIPTR74 -#define INTCICDIPTR75 INTC.ICDIPTR75 -#define INTCICDIPTR76 INTC.ICDIPTR76 -#define INTCICDIPTR77 INTC.ICDIPTR77 -#define INTCICDIPTR78 INTC.ICDIPTR78 -#define INTCICDIPTR79 INTC.ICDIPTR79 -#define INTCICDIPTR80 INTC.ICDIPTR80 -#define INTCICDIPTR81 INTC.ICDIPTR81 -#define INTCICDIPTR82 INTC.ICDIPTR82 -#define INTCICDIPTR83 INTC.ICDIPTR83 -#define INTCICDIPTR84 INTC.ICDIPTR84 -#define INTCICDIPTR85 INTC.ICDIPTR85 -#define INTCICDIPTR86 INTC.ICDIPTR86 -#define INTCICDIPTR87 INTC.ICDIPTR87 -#define INTCICDIPTR88 INTC.ICDIPTR88 -#define INTCICDIPTR89 INTC.ICDIPTR89 -#define INTCICDIPTR90 INTC.ICDIPTR90 -#define INTCICDIPTR91 INTC.ICDIPTR91 -#define INTCICDIPTR92 INTC.ICDIPTR92 -#define INTCICDIPTR93 INTC.ICDIPTR93 -#define INTCICDIPTR94 INTC.ICDIPTR94 -#define INTCICDIPTR95 INTC.ICDIPTR95 -#define INTCICDIPTR96 INTC.ICDIPTR96 -#define INTCICDIPTR97 INTC.ICDIPTR97 -#define INTCICDIPTR98 INTC.ICDIPTR98 -#define INTCICDIPTR99 INTC.ICDIPTR99 -#define INTCICDIPTR100 INTC.ICDIPTR100 -#define INTCICDIPTR101 INTC.ICDIPTR101 -#define INTCICDIPTR102 INTC.ICDIPTR102 -#define INTCICDIPTR103 INTC.ICDIPTR103 -#define INTCICDIPTR104 INTC.ICDIPTR104 -#define INTCICDIPTR105 INTC.ICDIPTR105 -#define INTCICDIPTR106 INTC.ICDIPTR106 -#define INTCICDIPTR107 INTC.ICDIPTR107 -#define INTCICDIPTR108 INTC.ICDIPTR108 -#define INTCICDIPTR109 INTC.ICDIPTR109 -#define INTCICDIPTR110 INTC.ICDIPTR110 -#define INTCICDIPTR111 INTC.ICDIPTR111 -#define INTCICDIPTR112 INTC.ICDIPTR112 -#define INTCICDIPTR113 INTC.ICDIPTR113 -#define INTCICDIPTR114 INTC.ICDIPTR114 -#define INTCICDIPTR115 INTC.ICDIPTR115 -#define INTCICDIPTR116 INTC.ICDIPTR116 -#define INTCICDIPTR117 INTC.ICDIPTR117 -#define INTCICDIPTR118 INTC.ICDIPTR118 -#define INTCICDIPTR119 INTC.ICDIPTR119 -#define INTCICDIPTR120 INTC.ICDIPTR120 -#define INTCICDIPTR121 INTC.ICDIPTR121 -#define INTCICDIPTR122 INTC.ICDIPTR122 -#define INTCICDIPTR123 INTC.ICDIPTR123 -#define INTCICDIPTR124 INTC.ICDIPTR124 -#define INTCICDIPTR125 INTC.ICDIPTR125 -#define INTCICDIPTR126 INTC.ICDIPTR126 -#define INTCICDIPTR127 INTC.ICDIPTR127 -#define INTCICDIPTR128 INTC.ICDIPTR128 -#define INTCICDIPTR129 INTC.ICDIPTR129 -#define INTCICDIPTR130 INTC.ICDIPTR130 -#define INTCICDIPTR131 INTC.ICDIPTR131 -#define INTCICDIPTR132 INTC.ICDIPTR132 -#define INTCICDIPTR133 INTC.ICDIPTR133 -#define INTCICDIPTR134 INTC.ICDIPTR134 -#define INTCICDIPTR135 INTC.ICDIPTR135 -#define INTCICDIPTR136 INTC.ICDIPTR136 -#define INTCICDIPTR137 INTC.ICDIPTR137 -#define INTCICDIPTR138 INTC.ICDIPTR138 -#define INTCICDIPTR139 INTC.ICDIPTR139 -#define INTCICDIPTR140 INTC.ICDIPTR140 -#define INTCICDIPTR141 INTC.ICDIPTR141 -#define INTCICDIPTR142 INTC.ICDIPTR142 -#define INTCICDIPTR143 INTC.ICDIPTR143 -#define INTCICDIPTR144 INTC.ICDIPTR144 -#define INTCICDIPTR145 INTC.ICDIPTR145 -#define INTCICDIPTR146 INTC.ICDIPTR146 -#define INTCICDICFR0 INTC.ICDICFR0 -#define INTCICDICFR1 INTC.ICDICFR1 -#define INTCICDICFR2 INTC.ICDICFR2 -#define INTCICDICFR3 INTC.ICDICFR3 -#define INTCICDICFR4 INTC.ICDICFR4 -#define INTCICDICFR5 INTC.ICDICFR5 -#define INTCICDICFR6 INTC.ICDICFR6 -#define INTCICDICFR7 INTC.ICDICFR7 -#define INTCICDICFR8 INTC.ICDICFR8 -#define INTCICDICFR9 INTC.ICDICFR9 -#define INTCICDICFR10 INTC.ICDICFR10 -#define INTCICDICFR11 INTC.ICDICFR11 -#define INTCICDICFR12 INTC.ICDICFR12 -#define INTCICDICFR13 INTC.ICDICFR13 -#define INTCICDICFR14 INTC.ICDICFR14 -#define INTCICDICFR15 INTC.ICDICFR15 -#define INTCICDICFR16 INTC.ICDICFR16 -#define INTCICDICFR17 INTC.ICDICFR17 -#define INTCICDICFR18 INTC.ICDICFR18 -#define INTCICDICFR19 INTC.ICDICFR19 -#define INTCICDICFR20 INTC.ICDICFR20 -#define INTCICDICFR21 INTC.ICDICFR21 -#define INTCICDICFR22 INTC.ICDICFR22 -#define INTCICDICFR23 INTC.ICDICFR23 -#define INTCICDICFR24 INTC.ICDICFR24 -#define INTCICDICFR25 INTC.ICDICFR25 -#define INTCICDICFR26 INTC.ICDICFR26 -#define INTCICDICFR27 INTC.ICDICFR27 -#define INTCICDICFR28 INTC.ICDICFR28 -#define INTCICDICFR29 INTC.ICDICFR29 -#define INTCICDICFR30 INTC.ICDICFR30 -#define INTCICDICFR31 INTC.ICDICFR31 -#define INTCICDICFR32 INTC.ICDICFR32 -#define INTCICDICFR33 INTC.ICDICFR33 -#define INTCICDICFR34 INTC.ICDICFR34 -#define INTCICDICFR35 INTC.ICDICFR35 -#define INTCICDICFR36 INTC.ICDICFR36 -#define INTCPPI_STATUS INTC.PPI_STATUS -#define INTCSPI_STATUS0 INTC.SPI_STATUS0 -#define INTCSPI_STATUS1 INTC.SPI_STATUS1 -#define INTCSPI_STATUS2 INTC.SPI_STATUS2 -#define INTCSPI_STATUS3 INTC.SPI_STATUS3 -#define INTCSPI_STATUS4 INTC.SPI_STATUS4 -#define INTCSPI_STATUS5 INTC.SPI_STATUS5 -#define INTCSPI_STATUS6 INTC.SPI_STATUS6 -#define INTCSPI_STATUS7 INTC.SPI_STATUS7 -#define INTCSPI_STATUS8 INTC.SPI_STATUS8 -#define INTCSPI_STATUS9 INTC.SPI_STATUS9 -#define INTCSPI_STATUS10 INTC.SPI_STATUS10 -#define INTCSPI_STATUS11 INTC.SPI_STATUS11 -#define INTCSPI_STATUS12 INTC.SPI_STATUS12 -#define INTCSPI_STATUS13 INTC.SPI_STATUS13 -#define INTCSPI_STATUS14 INTC.SPI_STATUS14 -#define INTCSPI_STATUS15 INTC.SPI_STATUS15 -#define INTCSPI_STATUS16 INTC.SPI_STATUS16 -#define INTCICDSGIR INTC.ICDSGIR -#define INTCICCICR INTC.ICCICR -#define INTCICCPMR INTC.ICCPMR -#define INTCICCBPR INTC.ICCBPR -#define INTCICCIAR INTC.ICCIAR -#define INTCICCEOIR INTC.ICCEOIR -#define INTCICCRPR INTC.ICCRPR -#define INTCICCHPIR INTC.ICCHPIR -#define INTCICCABPR INTC.ICCABPR -#define INTCICCIIDR INTC.ICCIIDR -#define INTCICR0 INTC.ICR0 -#define INTCICR1 INTC.ICR1 -#define INTCIRQRR INTC.IRQRR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h new file mode 100644 index 00000000000..09ad7a584b8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine_typedef.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef IODEFINE_TYPEDEF_H +#define IODEFINE_TYPEDEF_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +/* Shared types and macros for iodefine.h */ + +/*********************************************************************** +* Macro: IODEFINE_H_VERSION +************************************************************************/ +#define IODEFINE_H_VERSION (200) + + +/*********************************************************************** +* Enum: iodefine_byte_select_t +* +* R_IO_L - Low 16bit or Low 8 bit +* R_IO_H - High 16bit or Low 8 bit +* R_IO_LL - Low 8 bit +* R_IO_LH - Middle Low 8 bit +* R_IO_HL - Middle High 8 bit +* R_IO_HH - High 8 bit +************************************************************************/ +typedef enum iodefine_byte_select_t +{ + R_IO_L = 0, R_IO_H = 1, + R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3 +} iodefine_byte_select_t; + + +/*********************************************************************** +* Type: iodefine_reg32_t +* 32/16/8 bit access register +* +* - Padding : sizeof(iodefine_reg32_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ + volatile uint8_t UINT8[4]; /* 8-bit Access */ +} iodefine_reg32_t; + + +/*********************************************************************** +* Type: iodefine_reg32_16_t +* 32/16 bit access register +* +* - Padding : sizeof(iodefine_reg32_16_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_16_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ +} iodefine_reg32_16_t; + + +/*********************************************************************** +* Type: iodefine_reg16_8_t +* 16/8 bit access register +* +* - Padding : sizeof(iodefine_reg16_8_t) == 2 +* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +} iodefine_reg16_8_t; + + +/* End of shared types and macros for iodefine.h */ +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h similarity index 77% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h index 14665ef2d68..eb5d8421389 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h @@ -18,25 +18,36 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : irda_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef IRDA_IODEFINE_H #define IRDA_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_irda -{ /* IRDA */ - volatile uint8_t IRCR; /* IRCR */ -}; +#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ -#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ +#define IRDAIRCR (IRDA.IRCR) + + +typedef struct st_irda +{ + /* IRDA */ + volatile uint8_t IRCR; /* IRCR */ +} r_io_irda_t; -#define IRDAIRCR IRDA.IRCR +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h similarity index 76% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h index fa34ce21502..de1db5846aa 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h @@ -18,20 +18,88 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : jcu_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef JCU_IODEFINE_H #define JCU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_jcu -{ /* JCU */ +#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ + + +/* Start of channel array defines of JCU */ + +/* Channel array defines of JCU_JCQTBL0 */ +/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ +#define JCU_JCQTBL0_COUNT (4) +#define JCU_JCQTBL0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ +#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ +#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ +#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ + +/* End of channel array defines of JCU */ + + +#define JCUJCMOD (JCU.JCMOD) +#define JCUJCCMD (JCU.JCCMD) +#define JCUJCQTN (JCU.JCQTN) +#define JCUJCHTN (JCU.JCHTN) +#define JCUJCDRIU (JCU.JCDRIU) +#define JCUJCDRID (JCU.JCDRID) +#define JCUJCVSZU (JCU.JCVSZU) +#define JCUJCVSZD (JCU.JCVSZD) +#define JCUJCHSZU (JCU.JCHSZU) +#define JCUJCHSZD (JCU.JCHSZD) +#define JCUJCDTCU (JCU.JCDTCU) +#define JCUJCDTCM (JCU.JCDTCM) +#define JCUJCDTCD (JCU.JCDTCD) +#define JCUJINTE0 (JCU.JINTE0) +#define JCUJINTS0 (JCU.JINTS0) +#define JCUJCDERR (JCU.JCDERR) +#define JCUJCRST (JCU.JCRST) +#define JCUJIFECNT (JCU.JIFECNT) +#define JCUJIFESA (JCU.JIFESA) +#define JCUJIFESOFST (JCU.JIFESOFST) +#define JCUJIFEDA (JCU.JIFEDA) +#define JCUJIFESLC (JCU.JIFESLC) +#define JCUJIFEDDC (JCU.JIFEDDC) +#define JCUJIFDCNT (JCU.JIFDCNT) +#define JCUJIFDSA (JCU.JIFDSA) +#define JCUJIFDDOFST (JCU.JIFDDOFST) +#define JCUJIFDDA (JCU.JIFDDA) +#define JCUJIFDSDC (JCU.JIFDSDC) +#define JCUJIFDDLC (JCU.JIFDDLC) +#define JCUJIFDADT (JCU.JIFDADT) +#define JCUJINTE1 (JCU.JINTE1) +#define JCUJINTS1 (JCU.JINTS1) +#define JCUJIFESVSZ (JCU.JIFESVSZ) +#define JCUJIFESHSZ (JCU.JIFESHSZ) +#define JCUJCQTBL0 (JCU.JCQTBL0) +#define JCUJCQTBL1 (JCU.JCQTBL1) +#define JCUJCQTBL2 (JCU.JCQTBL2) +#define JCUJCQTBL3 (JCU.JCQTBL3) +#define JCUJCHTBD0 (JCU.JCHTBD0) +#define JCUJCHTBA0 (JCU.JCHTBA0) +#define JCUJCHTBD1 (JCU.JCHTBD1) +#define JCUJCHTBA1 (JCU.JCHTBA1) + + +typedef struct st_jcu +{ + /* JCU */ volatile uint8_t JCMOD; /* JCMOD */ volatile uint8_t JCCMD; /* JCCMD */ volatile uint8_t dummy145[1]; /* */ @@ -70,21 +138,29 @@ struct st_jcu volatile uint32_t JIFESVSZ; /* JIFESVSZ */ volatile uint32_t JIFESHSZ; /* JIFESHSZ */ volatile uint8_t dummy148[100]; /* */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL0; /* JCQTBL0 */ volatile uint8_t dummy149[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL1; /* JCQTBL1 */ volatile uint8_t dummy150[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL2; /* JCQTBL2 */ volatile uint8_t dummy151[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL3; /* JCQTBL3 */ volatile uint8_t dummy152[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCHTBD0; /* JCHTBD0 */ volatile uint8_t dummy153[31]; /* */ @@ -93,77 +169,29 @@ struct st_jcu volatile uint8_t JCHTBD1; /* JCHTBD1 */ volatile uint8_t dummy155[31]; /* */ volatile uint8_t JCHTBA1; /* JCHTBA1 */ -}; +} r_io_jcu_t; -struct st_jcu_from_jcqtbl0 +typedef struct st_jcu_from_jcqtbl0 { + volatile uint8_t JCQTBL0; /* JCQTBL0 */ volatile uint8_t dummy1[63]; /* */ -}; - - -#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ +} r_io_jcu_from_jcqtbl0_t; -/* Start of channnel array defines of JCU */ +/* Channel array defines of JCU (2)*/ +#ifdef DECLARE_JCU_JCQTBL0_CHANNELS +volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + JCU_JCQTBL0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */ +/* End of channel array defines of JCU (2)*/ -/* Channnel array defines of JCU_JCQTBL0 */ -/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ -#define JCU_JCQTBL0_COUNT 4 -#define JCU_JCQTBL0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ -#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ -#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ -#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ -/* End of channnel array defines of JCU */ - - -#define JCUJCMOD JCU.JCMOD -#define JCUJCCMD JCU.JCCMD -#define JCUJCQTN JCU.JCQTN -#define JCUJCHTN JCU.JCHTN -#define JCUJCDRIU JCU.JCDRIU -#define JCUJCDRID JCU.JCDRID -#define JCUJCVSZU JCU.JCVSZU -#define JCUJCVSZD JCU.JCVSZD -#define JCUJCHSZU JCU.JCHSZU -#define JCUJCHSZD JCU.JCHSZD -#define JCUJCDTCU JCU.JCDTCU -#define JCUJCDTCM JCU.JCDTCM -#define JCUJCDTCD JCU.JCDTCD -#define JCUJINTE0 JCU.JINTE0 -#define JCUJINTS0 JCU.JINTS0 -#define JCUJCDERR JCU.JCDERR -#define JCUJCRST JCU.JCRST -#define JCUJIFECNT JCU.JIFECNT -#define JCUJIFESA JCU.JIFESA -#define JCUJIFESOFST JCU.JIFESOFST -#define JCUJIFEDA JCU.JIFEDA -#define JCUJIFESLC JCU.JIFESLC -#define JCUJIFEDDC JCU.JIFEDDC -#define JCUJIFDCNT JCU.JIFDCNT -#define JCUJIFDSA JCU.JIFDSA -#define JCUJIFDDOFST JCU.JIFDDOFST -#define JCUJIFDDA JCU.JIFDDA -#define JCUJIFDSDC JCU.JIFDSDC -#define JCUJIFDDLC JCU.JIFDDLC -#define JCUJIFDADT JCU.JIFDADT -#define JCUJINTE1 JCU.JINTE1 -#define JCUJINTS1 JCU.JINTS1 -#define JCUJIFESVSZ JCU.JIFESVSZ -#define JCUJIFESHSZ JCU.JIFESHSZ -#define JCUJCQTBL0 JCU.JCQTBL0 -#define JCUJCQTBL1 JCU.JCQTBL1 -#define JCUJCQTBL2 JCU.JCQTBL2 -#define JCUJCQTBL3 JCU.JCQTBL3 -#define JCUJCHTBD0 JCU.JCHTBD0 -#define JCUJCHTBA0 JCU.JCHTBA0 -#define JCUJCHTBD1 JCU.JCHTBD1 -#define JCUJCHTBA1 JCU.JCHTBA1 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h similarity index 72% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h index ba6cb180bfb..76604a953ff 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h @@ -18,20 +18,97 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : l2c_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef L2C_IODEFINE_H #define L2C_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_l2c -{ /* L2C */ +#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ + + +/* Start of channel array defines of L2C */ + +/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ +/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8) +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ +#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ +#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ +#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ +#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ +#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ +#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ +#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ + +/* End of channel array defines of L2C */ + + +#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID) +#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE) +#define L2CREG1_CONTROL (L2C.REG1_CONTROL) +#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL) +#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL) +#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL) +#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL) +#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG) +#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG) +#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1) +#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0) +#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK) +#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS) +#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS) +#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR) +#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC) +#define L2CREG7_INV_PA (L2C.REG7_INV_PA) +#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY) +#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA) +#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX) +#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY) +#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA) +#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX) +#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY) +#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0) +#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0) +#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1) +#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1) +#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2) +#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2) +#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3) +#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3) +#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4) +#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4) +#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5) +#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5) +#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6) +#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6) +#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7) +#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7) +#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN) +#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY) +#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START) +#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END) +#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL) +#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL) +#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL) + + +typedef struct st_l2c +{ + /* L2C */ volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ volatile uint8_t dummy8[248]; /* */ @@ -66,37 +143,53 @@ struct st_l2c volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ volatile uint8_t dummy17[256]; /* */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint8_t dummy18[16]; /* */ volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ @@ -110,86 +203,29 @@ struct st_l2c volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ volatile uint8_t dummy22[28]; /* */ volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ -}; +} r_io_l2c_t; -struct st_l2c_from_reg9_d_lockdown0 +typedef struct st_l2c_from_reg9_d_lockdown0 { + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ -}; - - -#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ +} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */; -/* Start of channnel array defines of L2C */ +/* Channel array defines of L2C (2)*/ +#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS +volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */ +/* End of channel array defines of L2C (2)*/ -/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ -/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8 -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ -#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ -#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ -#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ -#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ -#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ -#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ -#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ -/* End of channnel array defines of L2C */ - - -#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID -#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE -#define L2CREG1_CONTROL L2C.REG1_CONTROL -#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL -#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL -#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL -#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL -#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG -#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG -#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1 -#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0 -#define L2CREG2_INT_MASK L2C.REG2_INT_MASK -#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS -#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS -#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR -#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC -#define L2CREG7_INV_PA L2C.REG7_INV_PA -#define L2CREG7_INV_WAY L2C.REG7_INV_WAY -#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA -#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX -#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY -#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA -#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX -#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY -#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0 -#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0 -#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1 -#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1 -#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2 -#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2 -#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3 -#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3 -#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4 -#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4 -#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5 -#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5 -#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6 -#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6 -#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7 -#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7 -#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN -#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY -#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START -#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END -#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL -#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL -#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h similarity index 51% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h index d46e7770b39..6c0fcc08774 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h @@ -18,25 +18,101 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : lin_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef LIN_IODEFINE_H #define LIN_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_lin -{ /* LIN */ +#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ +#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ + + +/* Start of channel array defines of LIN */ + +/* Channel array defines of LIN */ +/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ +#define LIN_COUNT (2) +#define LIN_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &LIN0, &LIN1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of LIN */ + + +#define LIN0RLN30LWBR (LIN0.RLN3nLWBR) +#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0) +#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1) +#define LIN0RLN30LSTC (LIN0.RLN3nLSTC) +#define LIN0RLN30LMD (LIN0.RLN3nLMD) +#define LIN0RLN30LBFC (LIN0.RLN3nLBFC) +#define LIN0RLN30LSC (LIN0.RLN3nLSC) +#define LIN0RLN30LWUP (LIN0.RLN3nLWUP) +#define LIN0RLN30LIE (LIN0.RLN3nLIE) +#define LIN0RLN30LEDE (LIN0.RLN3nLEDE) +#define LIN0RLN30LCUC (LIN0.RLN3nLCUC) +#define LIN0RLN30LTRC (LIN0.RLN3nLTRC) +#define LIN0RLN30LMST (LIN0.RLN3nLMST) +#define LIN0RLN30LST (LIN0.RLN3nLST) +#define LIN0RLN30LEST (LIN0.RLN3nLEST) +#define LIN0RLN30LDFC (LIN0.RLN3nLDFC) +#define LIN0RLN30LIDB (LIN0.RLN3nLIDB) +#define LIN0RLN30LCBR (LIN0.RLN3nLCBR) +#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1) +#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2) +#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3) +#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4) +#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5) +#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6) +#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7) +#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8) +#define LIN1RLN31LWBR (LIN1.RLN3nLWBR) +#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0) +#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1) +#define LIN1RLN31LSTC (LIN1.RLN3nLSTC) +#define LIN1RLN31LMD (LIN1.RLN3nLMD) +#define LIN1RLN31LBFC (LIN1.RLN3nLBFC) +#define LIN1RLN31LSC (LIN1.RLN3nLSC) +#define LIN1RLN31LWUP (LIN1.RLN3nLWUP) +#define LIN1RLN31LIE (LIN1.RLN3nLIE) +#define LIN1RLN31LEDE (LIN1.RLN3nLEDE) +#define LIN1RLN31LCUC (LIN1.RLN3nLCUC) +#define LIN1RLN31LTRC (LIN1.RLN3nLTRC) +#define LIN1RLN31LMST (LIN1.RLN3nLMST) +#define LIN1RLN31LST (LIN1.RLN3nLST) +#define LIN1RLN31LEST (LIN1.RLN3nLEST) +#define LIN1RLN31LDFC (LIN1.RLN3nLDFC) +#define LIN1RLN31LIDB (LIN1.RLN3nLIDB) +#define LIN1RLN31LCBR (LIN1.RLN3nLCBR) +#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1) +#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2) +#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3) +#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4) +#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5) +#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6) +#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7) +#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8) + +#define LIN_LDBn_COUNT (8) + + +typedef struct st_lin +{ + /* LIN */ volatile uint8_t dummy1[1]; /* */ volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */ - union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */ - + volatile uint8_t RLN3nLBRP0; /* RLN3nLBRP0 */ + volatile uint8_t RLN3nLBRP1; /* RLN3nLBRP1 */ volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */ volatile uint8_t dummy2[3]; /* */ volatile uint8_t RLN3nLMD; /* RLN3nLMD */ @@ -54,8 +130,9 @@ struct st_lin volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */ volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */ volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */ - volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */ -#define LIN_LDBn_COUNT 8 + volatile uint8_t dummy4[1]; /* */ + +/* #define LIN_LDBn_COUNT (8) */ volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */ volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */ volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */ @@ -64,111 +141,21 @@ struct st_lin volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */ volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */ volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */ - volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */ - volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */ - volatile uint8_t dummy4[2]; /* */ - union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */ - union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */ - union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */ - -}; - - -#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ -#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ +} r_io_lin_t; -/* Start of channnel array defines of LIN */ - -/* Channnel array defines of LIN */ -/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ -#define LIN_COUNT 2 -#define LIN_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &LIN0, &LIN1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of LIN */ +/* Channel array defines of LIN (2)*/ +#ifdef DECLARE_LIN_CHANNELS +volatile struct st_lin* LIN[ LIN_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + LIN_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_LIN_CHANNELS */ +/* End of channel array defines of LIN (2)*/ -#define LIN0RLN30LWBR LIN0.RLN3nLWBR -#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16 -#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L] -#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H] -#define LIN0RLN30LSTC LIN0.RLN3nLSTC -#define LIN0RLN30LMD LIN0.RLN3nLMD -#define LIN0RLN30LBFC LIN0.RLN3nLBFC -#define LIN0RLN30LSC LIN0.RLN3nLSC -#define LIN0RLN30LWUP LIN0.RLN3nLWUP -#define LIN0RLN30LIE LIN0.RLN3nLIE -#define LIN0RLN30LEDE LIN0.RLN3nLEDE -#define LIN0RLN30LCUC LIN0.RLN3nLCUC -#define LIN0RLN30LTRC LIN0.RLN3nLTRC -#define LIN0RLN30LMST LIN0.RLN3nLMST -#define LIN0RLN30LST LIN0.RLN3nLST -#define LIN0RLN30LEST LIN0.RLN3nLEST -#define LIN0RLN30LDFC LIN0.RLN3nLDFC -#define LIN0RLN30LIDB LIN0.RLN3nLIDB -#define LIN0RLN30LCBR LIN0.RLN3nLCBR -#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0 -#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1 -#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2 -#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3 -#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4 -#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5 -#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6 -#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7 -#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8 -#define LIN0RLN30LUOER LIN0.RLN3nLUOER -#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1 -#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16 -#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L] -#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H] -#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16 -#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L] -#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H] -#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16 -#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L] -#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H] -#define LIN1RLN31LWBR LIN1.RLN3nLWBR -#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16 -#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L] -#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H] -#define LIN1RLN31LSTC LIN1.RLN3nLSTC -#define LIN1RLN31LMD LIN1.RLN3nLMD -#define LIN1RLN31LBFC LIN1.RLN3nLBFC -#define LIN1RLN31LSC LIN1.RLN3nLSC -#define LIN1RLN31LWUP LIN1.RLN3nLWUP -#define LIN1RLN31LIE LIN1.RLN3nLIE -#define LIN1RLN31LEDE LIN1.RLN3nLEDE -#define LIN1RLN31LCUC LIN1.RLN3nLCUC -#define LIN1RLN31LTRC LIN1.RLN3nLTRC -#define LIN1RLN31LMST LIN1.RLN3nLMST -#define LIN1RLN31LST LIN1.RLN3nLST -#define LIN1RLN31LEST LIN1.RLN3nLEST -#define LIN1RLN31LDFC LIN1.RLN3nLDFC -#define LIN1RLN31LIDB LIN1.RLN3nLIDB -#define LIN1RLN31LCBR LIN1.RLN3nLCBR -#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0 -#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1 -#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2 -#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3 -#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4 -#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5 -#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6 -#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7 -#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8 -#define LIN1RLN31LUOER LIN1.RLN3nLUOER -#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1 -#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16 -#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L] -#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H] -#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16 -#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L] -#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H] -#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16 -#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L] -#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H] /* <-SEC M1.10.1 */ /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h similarity index 79% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h index 64d52eef016..c32caa6952f 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h @@ -18,20 +18,34 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : lvds_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.01a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef LVDS_IODEFINE_H #define LVDS_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_lvds -{ /* LVDS */ +#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ + + +#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE) +#define LVDSLVDSFCL (LVDS.LVDSFCL) +#define LVDSLCLKSELR (LVDS.LCLKSELR) +#define LVDSLPLLSETR (LVDS.LPLLSETR) +#define LVDSLPHYACC (LVDS.LPHYACC) + + +typedef struct st_lvds +{ + /* LVDS */ volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */ volatile uint32_t LVDSFCL; /* LVDSFCL */ volatile uint8_t dummy608[24]; /* */ @@ -39,16 +53,11 @@ struct st_lvds volatile uint32_t LPLLSETR; /* LPLLSETR */ volatile uint8_t dummy609[4]; /* */ volatile uint32_t LPHYACC; /* LPHYACC */ -}; - - -#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ +} r_io_lvds_t; -#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE -#define LVDSLVDSFCL LVDS.LVDSFCL -#define LVDSLCLKSELR LVDS.LCLKSELR -#define LVDSLPLLSETR LVDS.LPLLSETR -#define LVDSLPHYACC LVDS.LPHYACC /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h similarity index 78% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h index ae973658724..d06c7670891 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h @@ -18,22 +18,243 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mlb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MLB_IODEFINE_H #define MLB_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mlb -{ /* MLB */ +#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ + + +/* Start of channel array defines of MLB */ + +/* Channel array defines of MLB_FROM_CECR0_ARRAY */ +/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ +#define MLB_FROM_CECR0_ARRAY_COUNT (31) +#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ + &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \ + &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \ + &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */ +#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */ +#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */ +#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */ +#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */ +#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */ +#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */ +#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */ +#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */ +#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */ +#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */ +#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */ +#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */ +#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */ +#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */ +#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */ +#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */ +#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */ +#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */ +#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */ +#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */ +#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */ +#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */ +#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */ +#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */ +#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */ +#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */ +#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */ +#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */ +#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ +#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ + +/* End of channel array defines of MLB */ + + +#define MLBDCCR (MLB.DCCR) +#define MLBSSCR (MLB.SSCR) +#define MLBSDCR (MLB.SDCR) +#define MLBSMCR (MLB.SMCR) +#define MLBVCCR (MLB.VCCR) +#define MLBSBCR (MLB.SBCR) +#define MLBABCR (MLB.ABCR) +#define MLBCBCR (MLB.CBCR) +#define MLBIBCR (MLB.IBCR) +#define MLBCICR (MLB.CICR) +#define MLBCECR0 (MLB.CECR0) +#define MLBCSCR0 (MLB.CSCR0) +#define MLBCCBCR0 (MLB.CCBCR0) +#define MLBCNBCR0 (MLB.CNBCR0) +#define MLBCECR1 (MLB.CECR1) +#define MLBCSCR1 (MLB.CSCR1) +#define MLBCCBCR1 (MLB.CCBCR1) +#define MLBCNBCR1 (MLB.CNBCR1) +#define MLBCECR2 (MLB.CECR2) +#define MLBCSCR2 (MLB.CSCR2) +#define MLBCCBCR2 (MLB.CCBCR2) +#define MLBCNBCR2 (MLB.CNBCR2) +#define MLBCECR3 (MLB.CECR3) +#define MLBCSCR3 (MLB.CSCR3) +#define MLBCCBCR3 (MLB.CCBCR3) +#define MLBCNBCR3 (MLB.CNBCR3) +#define MLBCECR4 (MLB.CECR4) +#define MLBCSCR4 (MLB.CSCR4) +#define MLBCCBCR4 (MLB.CCBCR4) +#define MLBCNBCR4 (MLB.CNBCR4) +#define MLBCECR5 (MLB.CECR5) +#define MLBCSCR5 (MLB.CSCR5) +#define MLBCCBCR5 (MLB.CCBCR5) +#define MLBCNBCR5 (MLB.CNBCR5) +#define MLBCECR6 (MLB.CECR6) +#define MLBCSCR6 (MLB.CSCR6) +#define MLBCCBCR6 (MLB.CCBCR6) +#define MLBCNBCR6 (MLB.CNBCR6) +#define MLBCECR7 (MLB.CECR7) +#define MLBCSCR7 (MLB.CSCR7) +#define MLBCCBCR7 (MLB.CCBCR7) +#define MLBCNBCR7 (MLB.CNBCR7) +#define MLBCECR8 (MLB.CECR8) +#define MLBCSCR8 (MLB.CSCR8) +#define MLBCCBCR8 (MLB.CCBCR8) +#define MLBCNBCR8 (MLB.CNBCR8) +#define MLBCECR9 (MLB.CECR9) +#define MLBCSCR9 (MLB.CSCR9) +#define MLBCCBCR9 (MLB.CCBCR9) +#define MLBCNBCR9 (MLB.CNBCR9) +#define MLBCECR10 (MLB.CECR10) +#define MLBCSCR10 (MLB.CSCR10) +#define MLBCCBCR10 (MLB.CCBCR10) +#define MLBCNBCR10 (MLB.CNBCR10) +#define MLBCECR11 (MLB.CECR11) +#define MLBCSCR11 (MLB.CSCR11) +#define MLBCCBCR11 (MLB.CCBCR11) +#define MLBCNBCR11 (MLB.CNBCR11) +#define MLBCECR12 (MLB.CECR12) +#define MLBCSCR12 (MLB.CSCR12) +#define MLBCCBCR12 (MLB.CCBCR12) +#define MLBCNBCR12 (MLB.CNBCR12) +#define MLBCECR13 (MLB.CECR13) +#define MLBCSCR13 (MLB.CSCR13) +#define MLBCCBCR13 (MLB.CCBCR13) +#define MLBCNBCR13 (MLB.CNBCR13) +#define MLBCECR14 (MLB.CECR14) +#define MLBCSCR14 (MLB.CSCR14) +#define MLBCCBCR14 (MLB.CCBCR14) +#define MLBCNBCR14 (MLB.CNBCR14) +#define MLBCECR15 (MLB.CECR15) +#define MLBCSCR15 (MLB.CSCR15) +#define MLBCCBCR15 (MLB.CCBCR15) +#define MLBCNBCR15 (MLB.CNBCR15) +#define MLBCECR16 (MLB.CECR16) +#define MLBCSCR16 (MLB.CSCR16) +#define MLBCCBCR16 (MLB.CCBCR16) +#define MLBCNBCR16 (MLB.CNBCR16) +#define MLBCECR17 (MLB.CECR17) +#define MLBCSCR17 (MLB.CSCR17) +#define MLBCCBCR17 (MLB.CCBCR17) +#define MLBCNBCR17 (MLB.CNBCR17) +#define MLBCECR18 (MLB.CECR18) +#define MLBCSCR18 (MLB.CSCR18) +#define MLBCCBCR18 (MLB.CCBCR18) +#define MLBCNBCR18 (MLB.CNBCR18) +#define MLBCECR19 (MLB.CECR19) +#define MLBCSCR19 (MLB.CSCR19) +#define MLBCCBCR19 (MLB.CCBCR19) +#define MLBCNBCR19 (MLB.CNBCR19) +#define MLBCECR20 (MLB.CECR20) +#define MLBCSCR20 (MLB.CSCR20) +#define MLBCCBCR20 (MLB.CCBCR20) +#define MLBCNBCR20 (MLB.CNBCR20) +#define MLBCECR21 (MLB.CECR21) +#define MLBCSCR21 (MLB.CSCR21) +#define MLBCCBCR21 (MLB.CCBCR21) +#define MLBCNBCR21 (MLB.CNBCR21) +#define MLBCECR22 (MLB.CECR22) +#define MLBCSCR22 (MLB.CSCR22) +#define MLBCCBCR22 (MLB.CCBCR22) +#define MLBCNBCR22 (MLB.CNBCR22) +#define MLBCECR23 (MLB.CECR23) +#define MLBCSCR23 (MLB.CSCR23) +#define MLBCCBCR23 (MLB.CCBCR23) +#define MLBCNBCR23 (MLB.CNBCR23) +#define MLBCECR24 (MLB.CECR24) +#define MLBCSCR24 (MLB.CSCR24) +#define MLBCCBCR24 (MLB.CCBCR24) +#define MLBCNBCR24 (MLB.CNBCR24) +#define MLBCECR25 (MLB.CECR25) +#define MLBCSCR25 (MLB.CSCR25) +#define MLBCCBCR25 (MLB.CCBCR25) +#define MLBCNBCR25 (MLB.CNBCR25) +#define MLBCECR26 (MLB.CECR26) +#define MLBCSCR26 (MLB.CSCR26) +#define MLBCCBCR26 (MLB.CCBCR26) +#define MLBCNBCR26 (MLB.CNBCR26) +#define MLBCECR27 (MLB.CECR27) +#define MLBCSCR27 (MLB.CSCR27) +#define MLBCCBCR27 (MLB.CCBCR27) +#define MLBCNBCR27 (MLB.CNBCR27) +#define MLBCECR28 (MLB.CECR28) +#define MLBCSCR28 (MLB.CSCR28) +#define MLBCCBCR28 (MLB.CCBCR28) +#define MLBCNBCR28 (MLB.CNBCR28) +#define MLBCECR29 (MLB.CECR29) +#define MLBCSCR29 (MLB.CSCR29) +#define MLBCCBCR29 (MLB.CCBCR29) +#define MLBCNBCR29 (MLB.CNBCR29) +#define MLBCECR30 (MLB.CECR30) +#define MLBCSCR30 (MLB.CSCR30) +#define MLBCCBCR30 (MLB.CCBCR30) +#define MLBCNBCR30 (MLB.CNBCR30) +#define MLBLCBCR0 (MLB.LCBCR0) +#define MLBLCBCR1 (MLB.LCBCR1) +#define MLBLCBCR2 (MLB.LCBCR2) +#define MLBLCBCR3 (MLB.LCBCR3) +#define MLBLCBCR4 (MLB.LCBCR4) +#define MLBLCBCR5 (MLB.LCBCR5) +#define MLBLCBCR6 (MLB.LCBCR6) +#define MLBLCBCR7 (MLB.LCBCR7) +#define MLBLCBCR8 (MLB.LCBCR8) +#define MLBLCBCR9 (MLB.LCBCR9) +#define MLBLCBCR10 (MLB.LCBCR10) +#define MLBLCBCR11 (MLB.LCBCR11) +#define MLBLCBCR12 (MLB.LCBCR12) +#define MLBLCBCR13 (MLB.LCBCR13) +#define MLBLCBCR14 (MLB.LCBCR14) +#define MLBLCBCR15 (MLB.LCBCR15) +#define MLBLCBCR16 (MLB.LCBCR16) +#define MLBLCBCR17 (MLB.LCBCR17) +#define MLBLCBCR18 (MLB.LCBCR18) +#define MLBLCBCR19 (MLB.LCBCR19) +#define MLBLCBCR20 (MLB.LCBCR20) +#define MLBLCBCR21 (MLB.LCBCR21) +#define MLBLCBCR22 (MLB.LCBCR22) +#define MLBLCBCR23 (MLB.LCBCR23) +#define MLBLCBCR24 (MLB.LCBCR24) +#define MLBLCBCR25 (MLB.LCBCR25) +#define MLBLCBCR26 (MLB.LCBCR26) +#define MLBLCBCR27 (MLB.LCBCR27) +#define MLBLCBCR28 (MLB.LCBCR28) +#define MLBLCBCR29 (MLB.LCBCR29) +#define MLBLCBCR30 (MLB.LCBCR30) + +#define MLB_LCBCR0_COUNT (31) + + +typedef struct st_mlb +{ + /* MLB */ volatile uint32_t DCCR; /* DCCR */ volatile uint32_t SSCR; /* SSCR */ volatile uint32_t SDCR; /* SDCR */ @@ -46,194 +267,257 @@ struct st_mlb volatile uint32_t IBCR; /* IBCR */ volatile uint32_t CICR; /* CICR */ volatile uint8_t dummy157[12]; /* */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR0; /* CECR0 */ volatile uint32_t CSCR0; /* CSCR0 */ volatile uint32_t CCBCR0; /* CCBCR0 */ volatile uint32_t CNBCR0; /* CNBCR0 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR1; /* CECR1 */ volatile uint32_t CSCR1; /* CSCR1 */ volatile uint32_t CCBCR1; /* CCBCR1 */ volatile uint32_t CNBCR1; /* CNBCR1 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR2; /* CECR2 */ volatile uint32_t CSCR2; /* CSCR2 */ volatile uint32_t CCBCR2; /* CCBCR2 */ volatile uint32_t CNBCR2; /* CNBCR2 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR3; /* CECR3 */ volatile uint32_t CSCR3; /* CSCR3 */ volatile uint32_t CCBCR3; /* CCBCR3 */ volatile uint32_t CNBCR3; /* CNBCR3 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR4; /* CECR4 */ volatile uint32_t CSCR4; /* CSCR4 */ volatile uint32_t CCBCR4; /* CCBCR4 */ volatile uint32_t CNBCR4; /* CNBCR4 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR5; /* CECR5 */ volatile uint32_t CSCR5; /* CSCR5 */ volatile uint32_t CCBCR5; /* CCBCR5 */ volatile uint32_t CNBCR5; /* CNBCR5 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR6; /* CECR6 */ volatile uint32_t CSCR6; /* CSCR6 */ volatile uint32_t CCBCR6; /* CCBCR6 */ volatile uint32_t CNBCR6; /* CNBCR6 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR7; /* CECR7 */ volatile uint32_t CSCR7; /* CSCR7 */ volatile uint32_t CCBCR7; /* CCBCR7 */ volatile uint32_t CNBCR7; /* CNBCR7 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR8; /* CECR8 */ volatile uint32_t CSCR8; /* CSCR8 */ volatile uint32_t CCBCR8; /* CCBCR8 */ volatile uint32_t CNBCR8; /* CNBCR8 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR9; /* CECR9 */ volatile uint32_t CSCR9; /* CSCR9 */ volatile uint32_t CCBCR9; /* CCBCR9 */ volatile uint32_t CNBCR9; /* CNBCR9 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR10; /* CECR10 */ volatile uint32_t CSCR10; /* CSCR10 */ volatile uint32_t CCBCR10; /* CCBCR10 */ volatile uint32_t CNBCR10; /* CNBCR10 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR11; /* CECR11 */ volatile uint32_t CSCR11; /* CSCR11 */ volatile uint32_t CCBCR11; /* CCBCR11 */ volatile uint32_t CNBCR11; /* CNBCR11 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR12; /* CECR12 */ volatile uint32_t CSCR12; /* CSCR12 */ volatile uint32_t CCBCR12; /* CCBCR12 */ volatile uint32_t CNBCR12; /* CNBCR12 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR13; /* CECR13 */ volatile uint32_t CSCR13; /* CSCR13 */ volatile uint32_t CCBCR13; /* CCBCR13 */ volatile uint32_t CNBCR13; /* CNBCR13 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR14; /* CECR14 */ volatile uint32_t CSCR14; /* CSCR14 */ volatile uint32_t CCBCR14; /* CCBCR14 */ volatile uint32_t CNBCR14; /* CNBCR14 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR15; /* CECR15 */ volatile uint32_t CSCR15; /* CSCR15 */ volatile uint32_t CCBCR15; /* CCBCR15 */ volatile uint32_t CNBCR15; /* CNBCR15 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR16; /* CECR16 */ volatile uint32_t CSCR16; /* CSCR16 */ volatile uint32_t CCBCR16; /* CCBCR16 */ volatile uint32_t CNBCR16; /* CNBCR16 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR17; /* CECR17 */ volatile uint32_t CSCR17; /* CSCR17 */ volatile uint32_t CCBCR17; /* CCBCR17 */ volatile uint32_t CNBCR17; /* CNBCR17 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR18; /* CECR18 */ volatile uint32_t CSCR18; /* CSCR18 */ volatile uint32_t CCBCR18; /* CCBCR18 */ volatile uint32_t CNBCR18; /* CNBCR18 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR19; /* CECR19 */ volatile uint32_t CSCR19; /* CSCR19 */ volatile uint32_t CCBCR19; /* CCBCR19 */ volatile uint32_t CNBCR19; /* CNBCR19 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR20; /* CECR20 */ volatile uint32_t CSCR20; /* CSCR20 */ volatile uint32_t CCBCR20; /* CCBCR20 */ volatile uint32_t CNBCR20; /* CNBCR20 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR21; /* CECR21 */ volatile uint32_t CSCR21; /* CSCR21 */ volatile uint32_t CCBCR21; /* CCBCR21 */ volatile uint32_t CNBCR21; /* CNBCR21 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR22; /* CECR22 */ volatile uint32_t CSCR22; /* CSCR22 */ volatile uint32_t CCBCR22; /* CCBCR22 */ volatile uint32_t CNBCR22; /* CNBCR22 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR23; /* CECR23 */ volatile uint32_t CSCR23; /* CSCR23 */ volatile uint32_t CCBCR23; /* CCBCR23 */ volatile uint32_t CNBCR23; /* CNBCR23 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR24; /* CECR24 */ volatile uint32_t CSCR24; /* CSCR24 */ volatile uint32_t CCBCR24; /* CCBCR24 */ volatile uint32_t CNBCR24; /* CNBCR24 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR25; /* CECR25 */ volatile uint32_t CSCR25; /* CSCR25 */ volatile uint32_t CCBCR25; /* CCBCR25 */ volatile uint32_t CNBCR25; /* CNBCR25 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR26; /* CECR26 */ volatile uint32_t CSCR26; /* CSCR26 */ volatile uint32_t CCBCR26; /* CCBCR26 */ volatile uint32_t CNBCR26; /* CNBCR26 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR27; /* CECR27 */ volatile uint32_t CSCR27; /* CSCR27 */ volatile uint32_t CCBCR27; /* CCBCR27 */ volatile uint32_t CNBCR27; /* CNBCR27 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR28; /* CECR28 */ volatile uint32_t CSCR28; /* CSCR28 */ volatile uint32_t CCBCR28; /* CCBCR28 */ volatile uint32_t CNBCR28; /* CNBCR28 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR29; /* CECR29 */ volatile uint32_t CSCR29; /* CSCR29 */ volatile uint32_t CCBCR29; /* CCBCR29 */ volatile uint32_t CNBCR29; /* CNBCR29 */ + /* end of struct st_mlb_from_cecr0 */ + /* start of struct st_mlb_from_cecr0 */ volatile uint32_t CECR30; /* CECR30 */ volatile uint32_t CSCR30; /* CSCR30 */ volatile uint32_t CCBCR30; /* CCBCR30 */ volatile uint32_t CNBCR30; /* CNBCR30 */ + /* end of struct st_mlb_from_cecr0 */ volatile uint8_t dummy158[80]; /* */ -#define MLB_LCBCR0_COUNT 31 + +/* #define MLB_LCBCR0_COUNT (31) */ volatile uint32_t LCBCR0; /* LCBCR0 */ volatile uint32_t LCBCR1; /* LCBCR1 */ volatile uint32_t LCBCR2; /* LCBCR2 */ @@ -265,234 +549,31 @@ struct st_mlb volatile uint32_t LCBCR28; /* LCBCR28 */ volatile uint32_t LCBCR29; /* LCBCR29 */ volatile uint32_t LCBCR30; /* LCBCR30 */ -}; +} r_io_mlb_t; -struct st_mlb_from_cecr0 +typedef struct st_mlb_from_cecr0 { + volatile uint32_t CECR0; /* CECR0 */ volatile uint32_t CSCR0; /* CSCR0 */ volatile uint32_t CCBCR0; /* CCBCR0 */ volatile uint32_t CNBCR0; /* CNBCR0 */ -}; +} r_io_mlb_from_cecr0_t; -#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ - +/* Channel array defines of MLB (2)*/ +#ifdef DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS +volatile struct st_mlb_from_cecr0* MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + MLB_FROM_CECR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */ +/* End of channel array defines of MLB (2)*/ -/* Start of channnel array defines of MLB */ - -/* Channnel array defines of MLB_FROM_CECR0_ARRAY */ -/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ -#define MLB_FROM_CECR0_ARRAY_COUNT 31 -#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ - &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \ - &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \ - &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */ -#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */ -#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */ -#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */ -#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */ -#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */ -#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */ -#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */ -#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */ -#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */ -#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */ -#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */ -#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */ -#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */ -#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */ -#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */ -#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */ -#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */ -#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */ -#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */ -#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */ -#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */ -#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */ -#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */ -#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */ -#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */ -#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */ -#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */ -#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */ -#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ -#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ -/* End of channnel array defines of MLB */ - - -#define MLBDCCR MLB.DCCR -#define MLBSSCR MLB.SSCR -#define MLBSDCR MLB.SDCR -#define MLBSMCR MLB.SMCR -#define MLBVCCR MLB.VCCR -#define MLBSBCR MLB.SBCR -#define MLBABCR MLB.ABCR -#define MLBCBCR MLB.CBCR -#define MLBIBCR MLB.IBCR -#define MLBCICR MLB.CICR -#define MLBCECR0 MLB.CECR0 -#define MLBCSCR0 MLB.CSCR0 -#define MLBCCBCR0 MLB.CCBCR0 -#define MLBCNBCR0 MLB.CNBCR0 -#define MLBCECR1 MLB.CECR1 -#define MLBCSCR1 MLB.CSCR1 -#define MLBCCBCR1 MLB.CCBCR1 -#define MLBCNBCR1 MLB.CNBCR1 -#define MLBCECR2 MLB.CECR2 -#define MLBCSCR2 MLB.CSCR2 -#define MLBCCBCR2 MLB.CCBCR2 -#define MLBCNBCR2 MLB.CNBCR2 -#define MLBCECR3 MLB.CECR3 -#define MLBCSCR3 MLB.CSCR3 -#define MLBCCBCR3 MLB.CCBCR3 -#define MLBCNBCR3 MLB.CNBCR3 -#define MLBCECR4 MLB.CECR4 -#define MLBCSCR4 MLB.CSCR4 -#define MLBCCBCR4 MLB.CCBCR4 -#define MLBCNBCR4 MLB.CNBCR4 -#define MLBCECR5 MLB.CECR5 -#define MLBCSCR5 MLB.CSCR5 -#define MLBCCBCR5 MLB.CCBCR5 -#define MLBCNBCR5 MLB.CNBCR5 -#define MLBCECR6 MLB.CECR6 -#define MLBCSCR6 MLB.CSCR6 -#define MLBCCBCR6 MLB.CCBCR6 -#define MLBCNBCR6 MLB.CNBCR6 -#define MLBCECR7 MLB.CECR7 -#define MLBCSCR7 MLB.CSCR7 -#define MLBCCBCR7 MLB.CCBCR7 -#define MLBCNBCR7 MLB.CNBCR7 -#define MLBCECR8 MLB.CECR8 -#define MLBCSCR8 MLB.CSCR8 -#define MLBCCBCR8 MLB.CCBCR8 -#define MLBCNBCR8 MLB.CNBCR8 -#define MLBCECR9 MLB.CECR9 -#define MLBCSCR9 MLB.CSCR9 -#define MLBCCBCR9 MLB.CCBCR9 -#define MLBCNBCR9 MLB.CNBCR9 -#define MLBCECR10 MLB.CECR10 -#define MLBCSCR10 MLB.CSCR10 -#define MLBCCBCR10 MLB.CCBCR10 -#define MLBCNBCR10 MLB.CNBCR10 -#define MLBCECR11 MLB.CECR11 -#define MLBCSCR11 MLB.CSCR11 -#define MLBCCBCR11 MLB.CCBCR11 -#define MLBCNBCR11 MLB.CNBCR11 -#define MLBCECR12 MLB.CECR12 -#define MLBCSCR12 MLB.CSCR12 -#define MLBCCBCR12 MLB.CCBCR12 -#define MLBCNBCR12 MLB.CNBCR12 -#define MLBCECR13 MLB.CECR13 -#define MLBCSCR13 MLB.CSCR13 -#define MLBCCBCR13 MLB.CCBCR13 -#define MLBCNBCR13 MLB.CNBCR13 -#define MLBCECR14 MLB.CECR14 -#define MLBCSCR14 MLB.CSCR14 -#define MLBCCBCR14 MLB.CCBCR14 -#define MLBCNBCR14 MLB.CNBCR14 -#define MLBCECR15 MLB.CECR15 -#define MLBCSCR15 MLB.CSCR15 -#define MLBCCBCR15 MLB.CCBCR15 -#define MLBCNBCR15 MLB.CNBCR15 -#define MLBCECR16 MLB.CECR16 -#define MLBCSCR16 MLB.CSCR16 -#define MLBCCBCR16 MLB.CCBCR16 -#define MLBCNBCR16 MLB.CNBCR16 -#define MLBCECR17 MLB.CECR17 -#define MLBCSCR17 MLB.CSCR17 -#define MLBCCBCR17 MLB.CCBCR17 -#define MLBCNBCR17 MLB.CNBCR17 -#define MLBCECR18 MLB.CECR18 -#define MLBCSCR18 MLB.CSCR18 -#define MLBCCBCR18 MLB.CCBCR18 -#define MLBCNBCR18 MLB.CNBCR18 -#define MLBCECR19 MLB.CECR19 -#define MLBCSCR19 MLB.CSCR19 -#define MLBCCBCR19 MLB.CCBCR19 -#define MLBCNBCR19 MLB.CNBCR19 -#define MLBCECR20 MLB.CECR20 -#define MLBCSCR20 MLB.CSCR20 -#define MLBCCBCR20 MLB.CCBCR20 -#define MLBCNBCR20 MLB.CNBCR20 -#define MLBCECR21 MLB.CECR21 -#define MLBCSCR21 MLB.CSCR21 -#define MLBCCBCR21 MLB.CCBCR21 -#define MLBCNBCR21 MLB.CNBCR21 -#define MLBCECR22 MLB.CECR22 -#define MLBCSCR22 MLB.CSCR22 -#define MLBCCBCR22 MLB.CCBCR22 -#define MLBCNBCR22 MLB.CNBCR22 -#define MLBCECR23 MLB.CECR23 -#define MLBCSCR23 MLB.CSCR23 -#define MLBCCBCR23 MLB.CCBCR23 -#define MLBCNBCR23 MLB.CNBCR23 -#define MLBCECR24 MLB.CECR24 -#define MLBCSCR24 MLB.CSCR24 -#define MLBCCBCR24 MLB.CCBCR24 -#define MLBCNBCR24 MLB.CNBCR24 -#define MLBCECR25 MLB.CECR25 -#define MLBCSCR25 MLB.CSCR25 -#define MLBCCBCR25 MLB.CCBCR25 -#define MLBCNBCR25 MLB.CNBCR25 -#define MLBCECR26 MLB.CECR26 -#define MLBCSCR26 MLB.CSCR26 -#define MLBCCBCR26 MLB.CCBCR26 -#define MLBCNBCR26 MLB.CNBCR26 -#define MLBCECR27 MLB.CECR27 -#define MLBCSCR27 MLB.CSCR27 -#define MLBCCBCR27 MLB.CCBCR27 -#define MLBCNBCR27 MLB.CNBCR27 -#define MLBCECR28 MLB.CECR28 -#define MLBCSCR28 MLB.CSCR28 -#define MLBCCBCR28 MLB.CCBCR28 -#define MLBCNBCR28 MLB.CNBCR28 -#define MLBCECR29 MLB.CECR29 -#define MLBCSCR29 MLB.CSCR29 -#define MLBCCBCR29 MLB.CCBCR29 -#define MLBCNBCR29 MLB.CNBCR29 -#define MLBCECR30 MLB.CECR30 -#define MLBCSCR30 MLB.CSCR30 -#define MLBCCBCR30 MLB.CCBCR30 -#define MLBCNBCR30 MLB.CNBCR30 -#define MLBLCBCR0 MLB.LCBCR0 -#define MLBLCBCR1 MLB.LCBCR1 -#define MLBLCBCR2 MLB.LCBCR2 -#define MLBLCBCR3 MLB.LCBCR3 -#define MLBLCBCR4 MLB.LCBCR4 -#define MLBLCBCR5 MLB.LCBCR5 -#define MLBLCBCR6 MLB.LCBCR6 -#define MLBLCBCR7 MLB.LCBCR7 -#define MLBLCBCR8 MLB.LCBCR8 -#define MLBLCBCR9 MLB.LCBCR9 -#define MLBLCBCR10 MLB.LCBCR10 -#define MLBLCBCR11 MLB.LCBCR11 -#define MLBLCBCR12 MLB.LCBCR12 -#define MLBLCBCR13 MLB.LCBCR13 -#define MLBLCBCR14 MLB.LCBCR14 -#define MLBLCBCR15 MLB.LCBCR15 -#define MLBLCBCR16 MLB.LCBCR16 -#define MLBLCBCR17 MLB.LCBCR17 -#define MLBLCBCR18 MLB.LCBCR18 -#define MLBLCBCR19 MLB.LCBCR19 -#define MLBLCBCR20 MLB.LCBCR20 -#define MLBLCBCR21 MLB.LCBCR21 -#define MLBLCBCR22 MLB.LCBCR22 -#define MLBLCBCR23 MLB.LCBCR23 -#define MLBLCBCR24 MLB.LCBCR24 -#define MLBLCBCR25 MLB.LCBCR25 -#define MLBLCBCR26 MLB.LCBCR26 -#define MLBLCBCR27 MLB.LCBCR27 -#define MLBLCBCR28 MLB.LCBCR28 -#define MLBLCBCR29 MLB.LCBCR29 -#define MLBLCBCR30 MLB.LCBCR30 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h similarity index 75% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h index 43a23670d03..cccfd79f66c 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h @@ -18,20 +18,53 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mmc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MMC_IODEFINE_H #define MMC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mmc -{ /* MMC */ +#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ + + +#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH) +#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL) +#define MMCCE_ARG (MMC.CE_ARG) +#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12) +#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL) +#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET) +#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL) +#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC) +#define MMCCE_RESP3 (MMC.CE_RESP3) +#define MMCCE_RESP2 (MMC.CE_RESP2) +#define MMCCE_RESP1 (MMC.CE_RESP1) +#define MMCCE_RESP0 (MMC.CE_RESP0) +#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12) +#define MMCCE_DATA (MMC.CE_DATA) +#define MMCCE_INT (MMC.CE_INT) +#define MMCCE_INT_EN (MMC.CE_INT_EN) +#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1) +#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2) +#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE) +#define MMCCE_DETECT (MMC.CE_DETECT) +#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE) +#define MMCCE_VERSION (MMC.CE_VERSION) + +#define MMC_CE_RESPn_COUNT (4) + + +typedef struct st_mmc +{ + /* MMC */ volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ volatile uint8_t dummy182[4]; /* */ @@ -41,7 +74,8 @@ struct st_mmc volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ -#define MMC_CE_RESPn_COUNT 4 + +/* #define MMC_CE_RESPn_COUNT (4) */ volatile uint32_t CE_RESP3; /* CE_RESP3 */ volatile uint32_t CE_RESP2; /* CE_RESP2 */ volatile uint32_t CE_RESP1; /* CE_RESP1 */ @@ -60,33 +94,11 @@ struct st_mmc volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ volatile uint8_t dummy186[4]; /* */ volatile uint32_t CE_VERSION; /* CE_VERSION */ -}; - - -#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ +} r_io_mmc_t; -#define MMCCE_CMD_SETH MMC.CE_CMD_SETH -#define MMCCE_CMD_SETL MMC.CE_CMD_SETL -#define MMCCE_ARG MMC.CE_ARG -#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12 -#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL -#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET -#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL -#define MMCCE_BUF_ACC MMC.CE_BUF_ACC -#define MMCCE_RESP3 MMC.CE_RESP3 -#define MMCCE_RESP2 MMC.CE_RESP2 -#define MMCCE_RESP1 MMC.CE_RESP1 -#define MMCCE_RESP0 MMC.CE_RESP0 -#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12 -#define MMCCE_DATA MMC.CE_DATA -#define MMCCE_INT MMC.CE_INT -#define MMCCE_INT_EN MMC.CE_INT_EN -#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1 -#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2 -#define MMCCE_DMA_MODE MMC.CE_DMA_MODE -#define MMCCE_DETECT MMC.CE_DETECT -#define MMCCE_ADD_MODE MMC.CE_ADD_MODE -#define MMCCE_VERSION MMC.CE_VERSION /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h similarity index 76% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h index c2d0aeec840..9e3248029f5 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h @@ -18,20 +18,108 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mtu2_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MTU2_IODEFINE_H #define MTU2_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mtu2 -{ /* MTU2 */ +#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ + + +#define MTU2TCR_2 (MTU2.TCR_2) +#define MTU2TMDR_2 (MTU2.TMDR_2) +#define MTU2TIOR_2 (MTU2.TIOR_2) +#define MTU2TIER_2 (MTU2.TIER_2) +#define MTU2TSR_2 (MTU2.TSR_2) +#define MTU2TCNT_2 (MTU2.TCNT_2) +#define MTU2TGRA_2 (MTU2.TGRA_2) +#define MTU2TGRB_2 (MTU2.TGRB_2) +#define MTU2TCR_3 (MTU2.TCR_3) +#define MTU2TCR_4 (MTU2.TCR_4) +#define MTU2TMDR_3 (MTU2.TMDR_3) +#define MTU2TMDR_4 (MTU2.TMDR_4) +#define MTU2TIORH_3 (MTU2.TIORH_3) +#define MTU2TIORL_3 (MTU2.TIORL_3) +#define MTU2TIORH_4 (MTU2.TIORH_4) +#define MTU2TIORL_4 (MTU2.TIORL_4) +#define MTU2TIER_3 (MTU2.TIER_3) +#define MTU2TIER_4 (MTU2.TIER_4) +#define MTU2TOER (MTU2.TOER) +#define MTU2TGCR (MTU2.TGCR) +#define MTU2TOCR1 (MTU2.TOCR1) +#define MTU2TOCR2 (MTU2.TOCR2) +#define MTU2TCNT_3 (MTU2.TCNT_3) +#define MTU2TCNT_4 (MTU2.TCNT_4) +#define MTU2TCDR (MTU2.TCDR) +#define MTU2TDDR (MTU2.TDDR) +#define MTU2TGRA_3 (MTU2.TGRA_3) +#define MTU2TGRB_3 (MTU2.TGRB_3) +#define MTU2TGRA_4 (MTU2.TGRA_4) +#define MTU2TGRB_4 (MTU2.TGRB_4) +#define MTU2TCNTS (MTU2.TCNTS) +#define MTU2TCBR (MTU2.TCBR) +#define MTU2TGRC_3 (MTU2.TGRC_3) +#define MTU2TGRD_3 (MTU2.TGRD_3) +#define MTU2TGRC_4 (MTU2.TGRC_4) +#define MTU2TGRD_4 (MTU2.TGRD_4) +#define MTU2TSR_3 (MTU2.TSR_3) +#define MTU2TSR_4 (MTU2.TSR_4) +#define MTU2TITCR (MTU2.TITCR) +#define MTU2TITCNT (MTU2.TITCNT) +#define MTU2TBTER (MTU2.TBTER) +#define MTU2TDER (MTU2.TDER) +#define MTU2TOLBR (MTU2.TOLBR) +#define MTU2TBTM_3 (MTU2.TBTM_3) +#define MTU2TBTM_4 (MTU2.TBTM_4) +#define MTU2TADCR (MTU2.TADCR) +#define MTU2TADCORA_4 (MTU2.TADCORA_4) +#define MTU2TADCORB_4 (MTU2.TADCORB_4) +#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4) +#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4) +#define MTU2TWCR (MTU2.TWCR) +#define MTU2TSTR (MTU2.TSTR) +#define MTU2TSYR (MTU2.TSYR) +#define MTU2TRWER (MTU2.TRWER) +#define MTU2TCR_0 (MTU2.TCR_0) +#define MTU2TMDR_0 (MTU2.TMDR_0) +#define MTU2TIORH_0 (MTU2.TIORH_0) +#define MTU2TIORL_0 (MTU2.TIORL_0) +#define MTU2TIER_0 (MTU2.TIER_0) +#define MTU2TSR_0 (MTU2.TSR_0) +#define MTU2TCNT_0 (MTU2.TCNT_0) +#define MTU2TGRA_0 (MTU2.TGRA_0) +#define MTU2TGRB_0 (MTU2.TGRB_0) +#define MTU2TGRC_0 (MTU2.TGRC_0) +#define MTU2TGRD_0 (MTU2.TGRD_0) +#define MTU2TGRE_0 (MTU2.TGRE_0) +#define MTU2TGRF_0 (MTU2.TGRF_0) +#define MTU2TIER2_0 (MTU2.TIER2_0) +#define MTU2TSR2_0 (MTU2.TSR2_0) +#define MTU2TBTM_0 (MTU2.TBTM_0) +#define MTU2TCR_1 (MTU2.TCR_1) +#define MTU2TMDR_1 (MTU2.TMDR_1) +#define MTU2TIOR_1 (MTU2.TIOR_1) +#define MTU2TIER_1 (MTU2.TIER_1) +#define MTU2TSR_1 (MTU2.TSR_1) +#define MTU2TCNT_1 (MTU2.TCNT_1) +#define MTU2TGRA_1 (MTU2.TGRA_1) +#define MTU2TGRB_1 (MTU2.TGRB_1) +#define MTU2TICCR (MTU2.TICCR) + + +typedef struct st_mtu2 +{ + /* MTU2 */ volatile uint8_t TCR_2; /* TCR_2 */ volatile uint8_t TMDR_2; /* TMDR_2 */ volatile uint8_t TIOR_2; /* TIOR_2 */ @@ -128,90 +216,11 @@ struct st_mtu2 volatile uint16_t TGRB_1; /* TGRB_1 */ volatile uint8_t dummy536[4]; /* */ volatile uint8_t TICCR; /* TICCR */ -}; - - -#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ +} r_io_mtu2_t; -#define MTU2TCR_2 MTU2.TCR_2 -#define MTU2TMDR_2 MTU2.TMDR_2 -#define MTU2TIOR_2 MTU2.TIOR_2 -#define MTU2TIER_2 MTU2.TIER_2 -#define MTU2TSR_2 MTU2.TSR_2 -#define MTU2TCNT_2 MTU2.TCNT_2 -#define MTU2TGRA_2 MTU2.TGRA_2 -#define MTU2TGRB_2 MTU2.TGRB_2 -#define MTU2TCR_3 MTU2.TCR_3 -#define MTU2TCR_4 MTU2.TCR_4 -#define MTU2TMDR_3 MTU2.TMDR_3 -#define MTU2TMDR_4 MTU2.TMDR_4 -#define MTU2TIORH_3 MTU2.TIORH_3 -#define MTU2TIORL_3 MTU2.TIORL_3 -#define MTU2TIORH_4 MTU2.TIORH_4 -#define MTU2TIORL_4 MTU2.TIORL_4 -#define MTU2TIER_3 MTU2.TIER_3 -#define MTU2TIER_4 MTU2.TIER_4 -#define MTU2TOER MTU2.TOER -#define MTU2TGCR MTU2.TGCR -#define MTU2TOCR1 MTU2.TOCR1 -#define MTU2TOCR2 MTU2.TOCR2 -#define MTU2TCNT_3 MTU2.TCNT_3 -#define MTU2TCNT_4 MTU2.TCNT_4 -#define MTU2TCDR MTU2.TCDR -#define MTU2TDDR MTU2.TDDR -#define MTU2TGRA_3 MTU2.TGRA_3 -#define MTU2TGRB_3 MTU2.TGRB_3 -#define MTU2TGRA_4 MTU2.TGRA_4 -#define MTU2TGRB_4 MTU2.TGRB_4 -#define MTU2TCNTS MTU2.TCNTS -#define MTU2TCBR MTU2.TCBR -#define MTU2TGRC_3 MTU2.TGRC_3 -#define MTU2TGRD_3 MTU2.TGRD_3 -#define MTU2TGRC_4 MTU2.TGRC_4 -#define MTU2TGRD_4 MTU2.TGRD_4 -#define MTU2TSR_3 MTU2.TSR_3 -#define MTU2TSR_4 MTU2.TSR_4 -#define MTU2TITCR MTU2.TITCR -#define MTU2TITCNT MTU2.TITCNT -#define MTU2TBTER MTU2.TBTER -#define MTU2TDER MTU2.TDER -#define MTU2TOLBR MTU2.TOLBR -#define MTU2TBTM_3 MTU2.TBTM_3 -#define MTU2TBTM_4 MTU2.TBTM_4 -#define MTU2TADCR MTU2.TADCR -#define MTU2TADCORA_4 MTU2.TADCORA_4 -#define MTU2TADCORB_4 MTU2.TADCORB_4 -#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4 -#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4 -#define MTU2TWCR MTU2.TWCR -#define MTU2TSTR MTU2.TSTR -#define MTU2TSYR MTU2.TSYR -#define MTU2TRWER MTU2.TRWER -#define MTU2TCR_0 MTU2.TCR_0 -#define MTU2TMDR_0 MTU2.TMDR_0 -#define MTU2TIORH_0 MTU2.TIORH_0 -#define MTU2TIORL_0 MTU2.TIORL_0 -#define MTU2TIER_0 MTU2.TIER_0 -#define MTU2TSR_0 MTU2.TSR_0 -#define MTU2TCNT_0 MTU2.TCNT_0 -#define MTU2TGRA_0 MTU2.TGRA_0 -#define MTU2TGRB_0 MTU2.TGRB_0 -#define MTU2TGRC_0 MTU2.TGRC_0 -#define MTU2TGRD_0 MTU2.TGRD_0 -#define MTU2TGRE_0 MTU2.TGRE_0 -#define MTU2TGRF_0 MTU2.TGRF_0 -#define MTU2TIER2_0 MTU2.TIER2_0 -#define MTU2TSR2_0 MTU2.TSR2_0 -#define MTU2TBTM_0 MTU2.TBTM_0 -#define MTU2TCR_1 MTU2.TCR_1 -#define MTU2TMDR_1 MTU2.TMDR_1 -#define MTU2TIOR_1 MTU2.TIOR_1 -#define MTU2TIER_1 MTU2.TIER_1 -#define MTU2TSR_1 MTU2.TSR_1 -#define MTU2TCNT_1 MTU2.TCNT_1 -#define MTU2TGRA_1 MTU2.TGRA_1 -#define MTU2TGRB_1 MTU2.TGRB_1 -#define MTU2TICCR MTU2.TICCR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h similarity index 69% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h index b0aa5587db3..f246dd37731 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h @@ -18,20 +18,55 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ostm_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef OSTM_IODEFINE_H #define OSTM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ostm -{ /* OSTM */ +#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ + + +/* Start of channel array defines of OSTM */ + +/* Channel array defines of OSTM */ +/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ +#define OSTM_COUNT (2) +#define OSTM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &OSTM0, &OSTM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of OSTM */ + + +#define OSTM0CMP (OSTM0.OSTMnCMP) +#define OSTM0CNT (OSTM0.OSTMnCNT) +#define OSTM0TE (OSTM0.OSTMnTE) +#define OSTM0TS (OSTM0.OSTMnTS) +#define OSTM0TT (OSTM0.OSTMnTT) +#define OSTM0CTL (OSTM0.OSTMnCTL) +#define OSTM1CMP (OSTM1.OSTMnCMP) +#define OSTM1CNT (OSTM1.OSTMnCNT) +#define OSTM1TE (OSTM1.OSTMnTE) +#define OSTM1TS (OSTM1.OSTMnTS) +#define OSTM1TT (OSTM1.OSTMnTT) +#define OSTM1CTL (OSTM1.OSTMnCTL) + + +typedef struct st_ostm +{ + /* OSTM */ volatile uint32_t OSTMnCMP; /* OSTMnCMP */ volatile uint32_t OSTMnCNT; /* OSTMnCNT */ volatile uint8_t dummy1[8]; /* */ @@ -42,37 +77,21 @@ struct st_ostm volatile uint8_t OSTMnTT; /* OSTMnTT */ volatile uint8_t dummy4[7]; /* */ volatile uint8_t OSTMnCTL; /* OSTMnCTL */ -}; - - -#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ -#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ - +} r_io_ostm_t; -/* Start of channnel array defines of OSTM */ - -/* Channnel array defines of OSTM */ -/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ -#define OSTM_COUNT 2 -#define OSTM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &OSTM0, &OSTM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of OSTM */ +/* Channel array defines of OSTM (2)*/ +#ifdef DECLARE_OSTM_CHANNELS +volatile struct st_ostm* OSTM[ OSTM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + OSTM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_OSTM_CHANNELS */ +/* End of channel array defines of OSTM (2)*/ -#define OSTM0CMP OSTM0.OSTMnCMP -#define OSTM0CNT OSTM0.OSTMnCNT -#define OSTM0TE OSTM0.OSTMnTE -#define OSTM0TS OSTM0.OSTMnTS -#define OSTM0TT OSTM0.OSTMnTT -#define OSTM0CTL OSTM0.OSTMnCTL -#define OSTM1CMP OSTM1.OSTMnCMP -#define OSTM1CNT OSTM1.OSTMnCNT -#define OSTM1TE OSTM1.OSTMnTE -#define OSTM1TS OSTM1.OSTMnTS -#define OSTM1TT OSTM1.OSTMnTT -#define OSTM1CTL OSTM1.OSTMnCTL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h similarity index 60% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h index 230dd62947d..e62a51cca31 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h @@ -18,25 +18,112 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : pfv_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef PFV_IODEFINE_H #define PFV_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_pfv -{ /* PFV */ +#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ +#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ + + +/* Start of channel array defines of PFV */ + +/* Channel array defines of PFV */ +/*(Sample) value = PFV[ channel ]->PFVCR; */ +#define PFV_COUNT (2) +#define PFV_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PFV0, &PFV1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of PFV */ + + +#define PFV0PFVCR (PFV0.PFVCR) +#define PFV0PFVICR (PFV0.PFVICR) +#define PFV0PFVISR (PFV0.PFVISR) +#define PFV0PFVID0 (PFV0.PFVID0) +#define PFV0PFVID1 (PFV0.PFVID1) +#define PFV0PFVID2 (PFV0.PFVID2) +#define PFV0PFVID3 (PFV0.PFVID3) +#define PFV0PFVID4 (PFV0.PFVID4) +#define PFV0PFVID5 (PFV0.PFVID5) +#define PFV0PFVID6 (PFV0.PFVID6) +#define PFV0PFVID7 (PFV0.PFVID7) +#define PFV0PFVOD0 (PFV0.PFVOD0) +#define PFV0PFVOD1 (PFV0.PFVOD1) +#define PFV0PFVOD2 (PFV0.PFVOD2) +#define PFV0PFVOD3 (PFV0.PFVOD3) +#define PFV0PFVOD4 (PFV0.PFVOD4) +#define PFV0PFVOD5 (PFV0.PFVOD5) +#define PFV0PFVOD6 (PFV0.PFVOD6) +#define PFV0PFVOD7 (PFV0.PFVOD7) +#define PFV0PFVIFSR (PFV0.PFVIFSR) +#define PFV0PFVOFSR (PFV0.PFVOFSR) +#define PFV0PFVACR (PFV0.PFVACR) +#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE) +#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0) +#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1) +#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0) +#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1) +#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0) +#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1) +#define PFV0PFVSZR (PFV0.PFVSZR) +#define PFV1PFVCR (PFV1.PFVCR) +#define PFV1PFVICR (PFV1.PFVICR) +#define PFV1PFVISR (PFV1.PFVISR) +#define PFV1PFVID0 (PFV1.PFVID0) +#define PFV1PFVID1 (PFV1.PFVID1) +#define PFV1PFVID2 (PFV1.PFVID2) +#define PFV1PFVID3 (PFV1.PFVID3) +#define PFV1PFVID4 (PFV1.PFVID4) +#define PFV1PFVID5 (PFV1.PFVID5) +#define PFV1PFVID6 (PFV1.PFVID6) +#define PFV1PFVID7 (PFV1.PFVID7) +#define PFV1PFVOD0 (PFV1.PFVOD0) +#define PFV1PFVOD1 (PFV1.PFVOD1) +#define PFV1PFVOD2 (PFV1.PFVOD2) +#define PFV1PFVOD3 (PFV1.PFVOD3) +#define PFV1PFVOD4 (PFV1.PFVOD4) +#define PFV1PFVOD5 (PFV1.PFVOD5) +#define PFV1PFVOD6 (PFV1.PFVOD6) +#define PFV1PFVOD7 (PFV1.PFVOD7) +#define PFV1PFVIFSR (PFV1.PFVIFSR) +#define PFV1PFVOFSR (PFV1.PFVOFSR) +#define PFV1PFVACR (PFV1.PFVACR) +#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE) +#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0) +#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1) +#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0) +#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1) +#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0) +#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1) +#define PFV1PFVSZR (PFV1.PFVSZR) + +#define PFVID_COUNT (8) +#define PFVOD_COUNT (8) + + +typedef struct st_pfv +{ + /* PFV */ volatile uint32_t PFVCR; /* PFVCR */ volatile uint32_t PFVICR; /* PFVICR */ volatile uint32_t PFVISR; /* PFVISR */ volatile uint8_t dummy1[20]; /* */ -#define PFVID_COUNT 8 + +/* #define PFVID_COUNT (8) */ volatile uint32_t PFVID0; /* PFVID0 */ volatile uint32_t PFVID1; /* PFVID1 */ volatile uint32_t PFVID2; /* PFVID2 */ @@ -45,7 +132,8 @@ struct st_pfv volatile uint32_t PFVID5; /* PFVID5 */ volatile uint32_t PFVID6; /* PFVID6 */ volatile uint32_t PFVID7; /* PFVID7 */ -#define PFVOD_COUNT 8 + +/* #define PFVOD_COUNT (8) */ volatile uint32_t PFVOD0; /* PFVOD0 */ volatile uint32_t PFVOD1; /* PFVOD1 */ volatile uint32_t PFVOD2; /* PFVOD2 */ @@ -66,85 +154,21 @@ struct st_pfv volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ volatile uint32_t PFVSZR; /* PFVSZR */ -}; +} r_io_pfv_t; -#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ -#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ - +/* Channel array defines of PFV (2)*/ +#ifdef DECLARE_PFV_CHANNELS +volatile struct st_pfv* PFV[ PFV_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + PFV_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_PFV_CHANNELS */ +/* End of channel array defines of PFV (2)*/ -/* Start of channnel array defines of PFV */ - -/* Channnel array defines of PFV */ -/*(Sample) value = PFV[ channel ]->PFVCR; */ -#define PFV_COUNT 2 -#define PFV_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &PFV0, &PFV1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of PFV */ - - -#define PFV0PFVCR PFV0.PFVCR -#define PFV0PFVICR PFV0.PFVICR -#define PFV0PFVISR PFV0.PFVISR -#define PFV0PFVID0 PFV0.PFVID0 -#define PFV0PFVID1 PFV0.PFVID1 -#define PFV0PFVID2 PFV0.PFVID2 -#define PFV0PFVID3 PFV0.PFVID3 -#define PFV0PFVID4 PFV0.PFVID4 -#define PFV0PFVID5 PFV0.PFVID5 -#define PFV0PFVID6 PFV0.PFVID6 -#define PFV0PFVID7 PFV0.PFVID7 -#define PFV0PFVOD0 PFV0.PFVOD0 -#define PFV0PFVOD1 PFV0.PFVOD1 -#define PFV0PFVOD2 PFV0.PFVOD2 -#define PFV0PFVOD3 PFV0.PFVOD3 -#define PFV0PFVOD4 PFV0.PFVOD4 -#define PFV0PFVOD5 PFV0.PFVOD5 -#define PFV0PFVOD6 PFV0.PFVOD6 -#define PFV0PFVOD7 PFV0.PFVOD7 -#define PFV0PFVIFSR PFV0.PFVIFSR -#define PFV0PFVOFSR PFV0.PFVOFSR -#define PFV0PFVACR PFV0.PFVACR -#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE -#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0 -#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1 -#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0 -#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1 -#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0 -#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1 -#define PFV0PFVSZR PFV0.PFVSZR -#define PFV1PFVCR PFV1.PFVCR -#define PFV1PFVICR PFV1.PFVICR -#define PFV1PFVISR PFV1.PFVISR -#define PFV1PFVID0 PFV1.PFVID0 -#define PFV1PFVID1 PFV1.PFVID1 -#define PFV1PFVID2 PFV1.PFVID2 -#define PFV1PFVID3 PFV1.PFVID3 -#define PFV1PFVID4 PFV1.PFVID4 -#define PFV1PFVID5 PFV1.PFVID5 -#define PFV1PFVID6 PFV1.PFVID6 -#define PFV1PFVID7 PFV1.PFVID7 -#define PFV1PFVOD0 PFV1.PFVOD0 -#define PFV1PFVOD1 PFV1.PFVOD1 -#define PFV1PFVOD2 PFV1.PFVOD2 -#define PFV1PFVOD3 PFV1.PFVOD3 -#define PFV1PFVOD4 PFV1.PFVOD4 -#define PFV1PFVOD5 PFV1.PFVOD5 -#define PFV1PFVOD6 PFV1.PFVOD6 -#define PFV1PFVOD7 PFV1.PFVOD7 -#define PFV1PFVIFSR PFV1.PFVIFSR -#define PFV1PFVOFSR PFV1.PFVOFSR -#define PFV1PFVACR PFV1.PFVACR -#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE -#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0 -#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1 -#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0 -#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1 -#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0 -#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1 -#define PFV1PFVSZR PFV1.PFVSZR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h similarity index 60% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h index a7143d481d2..128b1099d86 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h @@ -18,118 +18,118 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : pwm_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef PWM_IODEFINE_H #define PWM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -union reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -}; +#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ + + +/* Start of channel array defines of PWM */ + +/* Channel array defines of PWMn */ +/*(Sample) value = PWMn[ channel ]->PWCR_1; */ +#define PWMn_COUNT (2) +#define PWMn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PWM1, &PWM2 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ +#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ + +/* End of channel array defines of PWM */ + + +#define PWMPWBTCR (PWM.PWBTCR) +#define PWMPWCR_1 (PWM.PWCR_1) +#define PWMPWPR_1 (PWM.PWPR_1) +#define PWMPWCYR_1 (PWM.PWCYR_1) +#define PWMPWBFR_1A (PWM.PWBFR_1A) +#define PWMPWBFR_1C (PWM.PWBFR_1C) +#define PWMPWBFR_1E (PWM.PWBFR_1E) +#define PWMPWBFR_1G (PWM.PWBFR_1G) +#define PWMPWCR_2 (PWM.PWCR_2) +#define PWMPWPR_2 (PWM.PWPR_2) +#define PWMPWCYR_2 (PWM.PWCYR_2) +#define PWMPWBFR_2A (PWM.PWBFR_2A) +#define PWMPWBFR_2C (PWM.PWBFR_2C) +#define PWMPWBFR_2E (PWM.PWBFR_2E) +#define PWMPWBFR_2G (PWM.PWBFR_2G) + -struct st_pwm -{ /* PWM */ +typedef struct st_pwm +{ + /* PWM */ volatile uint8_t dummy559[2]; /* */ - union reg16_8_t PWBTCR; /* PWBTCR */ - - volatile uint8_t dummy560[216]; /* */ - + volatile uint8_t PWBTCR; /* PWBTCR */ + volatile uint8_t dummy560[217]; /* */ + /* start of struct st_pwm_common */ - union reg16_8_t PWCR_1; /* PWCR_1 */ - - volatile uint8_t dummy561[2]; /* */ - union reg16_8_t PWPR_1; /* PWPR_1 */ - + volatile uint8_t PWCR_1; /* PWCR_1 */ + volatile uint8_t dummy561[3]; /* */ + volatile uint8_t PWPR_1; /* PWPR_1 */ + volatile uint8_t dummy562[1]; /* */ volatile uint16_t PWCYR_1; /* PWCYR_1 */ volatile uint16_t PWBFR_1A; /* PWBFR_1A */ volatile uint16_t PWBFR_1C; /* PWBFR_1C */ volatile uint16_t PWBFR_1E; /* PWBFR_1E */ volatile uint16_t PWBFR_1G; /* PWBFR_1G */ + /* end of struct st_pwm_common */ - + /* start of struct st_pwm_common */ - union reg16_8_t PWCR_2; /* PWCR_2 */ - - volatile uint8_t dummy562[2]; /* */ - union reg16_8_t PWPR_2; /* PWPR_2 */ - + volatile uint8_t PWCR_2; /* PWCR_2 */ + volatile uint8_t dummy563[3]; /* */ + volatile uint8_t PWPR_2; /* PWPR_2 */ + volatile uint8_t dummy564[1]; /* */ volatile uint16_t PWCYR_2; /* PWCYR_2 */ volatile uint16_t PWBFR_2A; /* PWBFR_2A */ volatile uint16_t PWBFR_2C; /* PWBFR_2C */ volatile uint16_t PWBFR_2E; /* PWBFR_2E */ volatile uint16_t PWBFR_2G; /* PWBFR_2G */ + /* end of struct st_pwm_common */ -}; +} r_io_pwm_t; -struct st_pwm_common +typedef struct st_pwm_common { - union reg16_8_t PWCR_1; /* PWCR_1 */ - - volatile uint8_t dummy572[2]; /* */ - union reg16_8_t PWPR_1; /* PWPR_1 */ - + + volatile uint8_t PWCR_1; /* PWCR_1 */ + volatile uint8_t dummy562[3]; /* */ + volatile uint8_t PWPR_1; /* PWPR_1 */ + volatile uint8_t dummy563[1]; /* */ volatile uint16_t PWCYR_1; /* PWCYR_1 */ volatile uint16_t PWBFR_1A; /* PWBFR_1A */ volatile uint16_t PWBFR_1C; /* PWBFR_1C */ volatile uint16_t PWBFR_1E; /* PWBFR_1E */ volatile uint16_t PWBFR_1G; /* PWBFR_1G */ -}; - - -#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ +} r_io_pwm_common_t; -/* Start of channnel array defines of PWM */ +/* Channel array defines of PWMn (2)*/ +#ifdef DECLARE_PWMn_CHANNELS +volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + PWMn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_PWMn_CHANNELS */ +/* End of channel array defines of PWMn (2)*/ -/* Channnel array defines of PWMn */ -/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */ -#define PWMn_COUNT 2 -#define PWMn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &PWM1, &PWM2 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ -#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ -/* End of channnel array defines of PWM */ - - -#define PWMPWBTCR PWM.PWBTCR.UINT16 -#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0] -#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1] -#define PWMPWCR_1 PWM.PWCR_1.UINT16 -#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0] -#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1] -#define PWMPWPR_1 PWM.PWPR_1.UINT16 -#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0] -#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1] -#define PWMPWCYR_1 PWM.PWCYR_1 -#define PWMPWBFR_1A PWM.PWBFR_1A -#define PWMPWBFR_1C PWM.PWBFR_1C -#define PWMPWBFR_1E PWM.PWBFR_1E -#define PWMPWBFR_1G PWM.PWBFR_1G -#define PWMPWCR_2 PWM.PWCR_2.UINT16 -#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0] -#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1] -#define PWMPWPR_2 PWM.PWPR_2.UINT16 -#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0] -#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1] -#define PWMPWCYR_2 PWM.PWCYR_2 -#define PWMPWBFR_2A PWM.PWBFR_2A -#define PWMPWBFR_2C PWM.PWBFR_2C -#define PWMPWBFR_2E PWM.PWBFR_2E -#define PWMPWBFR_2G PWM.PWBFR_2G /* <-SEC M1.10.1 */ /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h new file mode 100644 index 00000000000..8fd2be68db8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h @@ -0,0 +1,584 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef RIIC_IODEFINE_H +#define RIIC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ +#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ +#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */ +#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ + + +/* Start of channel array defines of RIIC */ + +/* Channel array defines of RIIC */ +/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ +#define RIIC_COUNT (4) +#define RIIC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of RIIC */ + + +#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32) +#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L]) +#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H]) +#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32) +#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L]) +#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H]) +#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32) +#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L]) +#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H]) +#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32) +#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L]) +#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H]) +#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32) +#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L]) +#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H]) +#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC0FER (RIIC0.RIICnFER.UINT32) +#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L]) +#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL]) +#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH]) +#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H]) +#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL]) +#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH]) +#define RIIC0SER (RIIC0.RIICnSER.UINT32) +#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L]) +#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL]) +#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH]) +#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H]) +#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL]) +#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH]) +#define RIIC0IER (RIIC0.RIICnIER.UINT32) +#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L]) +#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL]) +#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH]) +#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H]) +#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL]) +#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH]) +#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32) +#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L]) +#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H]) +#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32) +#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L]) +#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H]) +#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32) +#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32) +#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32) +#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC0BRL (RIIC0.RIICnBRL.UINT32) +#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L]) +#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H]) +#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC0BRH (RIIC0.RIICnBRH.UINT32) +#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L]) +#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H]) +#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC0DRT (RIIC0.RIICnDRT.UINT32) +#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L]) +#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H]) +#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC0DRR (RIIC0.RIICnDRR.UINT32) +#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L]) +#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H]) +#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32) +#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L]) +#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H]) +#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32) +#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L]) +#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H]) +#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32) +#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L]) +#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H]) +#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32) +#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L]) +#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H]) +#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32) +#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L]) +#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H]) +#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC1FER (RIIC1.RIICnFER.UINT32) +#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L]) +#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL]) +#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH]) +#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H]) +#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL]) +#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH]) +#define RIIC1SER (RIIC1.RIICnSER.UINT32) +#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L]) +#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL]) +#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH]) +#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H]) +#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL]) +#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH]) +#define RIIC1IER (RIIC1.RIICnIER.UINT32) +#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L]) +#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL]) +#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH]) +#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H]) +#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL]) +#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH]) +#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32) +#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L]) +#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H]) +#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32) +#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L]) +#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H]) +#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32) +#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32) +#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32) +#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC1BRL (RIIC1.RIICnBRL.UINT32) +#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L]) +#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H]) +#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC1BRH (RIIC1.RIICnBRH.UINT32) +#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L]) +#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H]) +#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC1DRT (RIIC1.RIICnDRT.UINT32) +#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L]) +#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H]) +#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC1DRR (RIIC1.RIICnDRR.UINT32) +#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L]) +#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H]) +#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32) +#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L]) +#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H]) +#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32) +#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L]) +#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H]) +#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32) +#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L]) +#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H]) +#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32) +#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L]) +#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H]) +#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32) +#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L]) +#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H]) +#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC2FER (RIIC2.RIICnFER.UINT32) +#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L]) +#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL]) +#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH]) +#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H]) +#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL]) +#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH]) +#define RIIC2SER (RIIC2.RIICnSER.UINT32) +#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L]) +#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL]) +#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH]) +#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H]) +#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL]) +#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH]) +#define RIIC2IER (RIIC2.RIICnIER.UINT32) +#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L]) +#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL]) +#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH]) +#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H]) +#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL]) +#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH]) +#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32) +#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L]) +#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H]) +#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32) +#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L]) +#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H]) +#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32) +#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32) +#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32) +#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC2BRL (RIIC2.RIICnBRL.UINT32) +#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L]) +#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H]) +#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC2BRH (RIIC2.RIICnBRH.UINT32) +#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L]) +#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H]) +#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC2DRT (RIIC2.RIICnDRT.UINT32) +#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L]) +#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H]) +#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC2DRR (RIIC2.RIICnDRR.UINT32) +#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L]) +#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H]) +#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32) +#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L]) +#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H]) +#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32) +#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L]) +#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H]) +#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32) +#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L]) +#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H]) +#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32) +#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L]) +#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H]) +#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32) +#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L]) +#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H]) +#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC3FER (RIIC3.RIICnFER.UINT32) +#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L]) +#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL]) +#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH]) +#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H]) +#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL]) +#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH]) +#define RIIC3SER (RIIC3.RIICnSER.UINT32) +#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L]) +#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL]) +#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH]) +#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H]) +#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL]) +#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH]) +#define RIIC3IER (RIIC3.RIICnIER.UINT32) +#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L]) +#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL]) +#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH]) +#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H]) +#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL]) +#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH]) +#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32) +#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L]) +#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H]) +#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32) +#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L]) +#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H]) +#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32) +#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32) +#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32) +#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC3BRL (RIIC3.RIICnBRL.UINT32) +#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L]) +#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H]) +#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC3BRH (RIIC3.RIICnBRH.UINT32) +#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L]) +#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H]) +#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC3DRT (RIIC3.RIICnDRT.UINT32) +#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L]) +#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H]) +#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC3DRR (RIIC3.RIICnDRR.UINT32) +#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L]) +#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H]) +#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH]) + +#define RIICnCRm_COUNT (2) +#define RIICnMRm_COUNT (3) +#define RIICnSRm_COUNT (2) +#define RIICnSARm_COUNT (3) + + +typedef struct st_riic +{ + /* RIIC */ + +/* #define RIICnCRm_COUNT (2) */ + union iodefine_reg32_t RIICnCR1; /* RIICnCR1 */ + union iodefine_reg32_t RIICnCR2; /* RIICnCR2 */ + +/* #define RIICnMRm_COUNT (3) */ + union iodefine_reg32_t RIICnMR1; /* RIICnMR1 */ + union iodefine_reg32_t RIICnMR2; /* RIICnMR2 */ + union iodefine_reg32_t RIICnMR3; /* RIICnMR3 */ + union iodefine_reg32_t RIICnFER; /* RIICnFER */ + union iodefine_reg32_t RIICnSER; /* RIICnSER */ + union iodefine_reg32_t RIICnIER; /* RIICnIER */ + +/* #define RIICnSRm_COUNT (2) */ + union iodefine_reg32_t RIICnSR1; /* RIICnSR1 */ + union iodefine_reg32_t RIICnSR2; /* RIICnSR2 */ + +/* #define RIICnSARm_COUNT (3) */ + union iodefine_reg32_t RIICnSAR0; /* RIICnSAR0 */ + union iodefine_reg32_t RIICnSAR1; /* RIICnSAR1 */ + union iodefine_reg32_t RIICnSAR2; /* RIICnSAR2 */ + union iodefine_reg32_t RIICnBRL; /* RIICnBRL */ + union iodefine_reg32_t RIICnBRH; /* RIICnBRH */ + union iodefine_reg32_t RIICnDRT; /* RIICnDRT */ + union iodefine_reg32_t RIICnDRR; /* RIICnDRR */ + +} r_io_riic_t; + + +/* Channel array defines of RIIC (2)*/ +#ifdef DECLARE_RIIC_CHANNELS +volatile struct st_riic* RIIC[ RIIC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RIIC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RIIC_CHANNELS */ +/* End of channel array defines of RIIC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h similarity index 69% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h index cfcfda568db..7d6a207693d 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h @@ -18,30 +18,104 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : romdec_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ROMDEC_IODEFINE_H #define ROMDEC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_romdec -{ /* ROMDEC */ +#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ + + +#define ROMDECCROMEN (ROMDEC.CROMEN) +#define ROMDECCROMSY0 (ROMDEC.CROMSY0) +#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0) +#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1) +#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3) +#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4) +#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5) +#define ROMDECCROMST0 (ROMDEC.CROMST0) +#define ROMDECCROMST1 (ROMDEC.CROMST1) +#define ROMDECCROMST3 (ROMDEC.CROMST3) +#define ROMDECCROMST4 (ROMDEC.CROMST4) +#define ROMDECCROMST5 (ROMDEC.CROMST5) +#define ROMDECCROMST6 (ROMDEC.CROMST6) +#define ROMDECCBUFST0 (ROMDEC.CBUFST0) +#define ROMDECCBUFST1 (ROMDEC.CBUFST1) +#define ROMDECCBUFST2 (ROMDEC.CBUFST2) +#define ROMDECHEAD00 (ROMDEC.HEAD00) +#define ROMDECHEAD01 (ROMDEC.HEAD01) +#define ROMDECHEAD02 (ROMDEC.HEAD02) +#define ROMDECHEAD03 (ROMDEC.HEAD03) +#define ROMDECSHEAD00 (ROMDEC.SHEAD00) +#define ROMDECSHEAD01 (ROMDEC.SHEAD01) +#define ROMDECSHEAD02 (ROMDEC.SHEAD02) +#define ROMDECSHEAD03 (ROMDEC.SHEAD03) +#define ROMDECSHEAD04 (ROMDEC.SHEAD04) +#define ROMDECSHEAD05 (ROMDEC.SHEAD05) +#define ROMDECSHEAD06 (ROMDEC.SHEAD06) +#define ROMDECSHEAD07 (ROMDEC.SHEAD07) +#define ROMDECHEAD20 (ROMDEC.HEAD20) +#define ROMDECHEAD21 (ROMDEC.HEAD21) +#define ROMDECHEAD22 (ROMDEC.HEAD22) +#define ROMDECHEAD23 (ROMDEC.HEAD23) +#define ROMDECSHEAD20 (ROMDEC.SHEAD20) +#define ROMDECSHEAD21 (ROMDEC.SHEAD21) +#define ROMDECSHEAD22 (ROMDEC.SHEAD22) +#define ROMDECSHEAD23 (ROMDEC.SHEAD23) +#define ROMDECSHEAD24 (ROMDEC.SHEAD24) +#define ROMDECSHEAD25 (ROMDEC.SHEAD25) +#define ROMDECSHEAD26 (ROMDEC.SHEAD26) +#define ROMDECSHEAD27 (ROMDEC.SHEAD27) +#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0) +#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1) +#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2) +#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3) +#define ROMDECCROMST0M (ROMDEC.CROMST0M) +#define ROMDECROMDECRST (ROMDEC.ROMDECRST) +#define ROMDECRSTSTAT (ROMDEC.RSTSTAT) +#define ROMDECSSI (ROMDEC.SSI) +#define ROMDECINTHOLD (ROMDEC.INTHOLD) +#define ROMDECINHINT (ROMDEC.INHINT) +#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0) +#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2) +#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0) + +#define ROMDEC_CROMCTL0_COUNT (2) +#define ROMDEC_CROMST0_COUNT (2) +#define ROMDEC_CBUFST0_COUNT (3) +#define ROMDEC_HEAD00_COUNT (4) +#define ROMDEC_SHEAD00_COUNT (8) +#define ROMDEC_HEAD20_COUNT (4) +#define ROMDEC_SHEAD20_COUNT (8) +#define ROMDEC_CBUFCTL0_COUNT (4) +#define ROMDEC_STRMDIN0_COUNT (2) + + +typedef struct st_romdec +{ + /* ROMDEC */ volatile uint8_t CROMEN; /* CROMEN */ volatile uint8_t CROMSY0; /* CROMSY0 */ -#define ROMDEC_CROMCTL0_COUNT 2 + +/* #define ROMDEC_CROMCTL0_COUNT (2) */ volatile uint8_t CROMCTL0; /* CROMCTL0 */ volatile uint8_t CROMCTL1; /* CROMCTL1 */ volatile uint8_t dummy23[1]; /* */ volatile uint8_t CROMCTL3; /* CROMCTL3 */ volatile uint8_t CROMCTL4; /* CROMCTL4 */ volatile uint8_t CROMCTL5; /* CROMCTL5 */ -#define ROMDEC_CROMST0_COUNT 2 + +/* #define ROMDEC_CROMST0_COUNT (2) */ volatile uint8_t CROMST0; /* CROMST0 */ volatile uint8_t CROMST1; /* CROMST1 */ volatile uint8_t dummy24[1]; /* */ @@ -50,17 +124,20 @@ struct st_romdec volatile uint8_t CROMST5; /* CROMST5 */ volatile uint8_t CROMST6; /* CROMST6 */ volatile uint8_t dummy25[5]; /* */ -#define ROMDEC_CBUFST0_COUNT 3 + +/* #define ROMDEC_CBUFST0_COUNT (3) */ volatile uint8_t CBUFST0; /* CBUFST0 */ volatile uint8_t CBUFST1; /* CBUFST1 */ volatile uint8_t CBUFST2; /* CBUFST2 */ volatile uint8_t dummy26[1]; /* */ -#define ROMDEC_HEAD00_COUNT 4 + +/* #define ROMDEC_HEAD00_COUNT (4) */ volatile uint8_t HEAD00; /* HEAD00 */ volatile uint8_t HEAD01; /* HEAD01 */ volatile uint8_t HEAD02; /* HEAD02 */ volatile uint8_t HEAD03; /* HEAD03 */ -#define ROMDEC_SHEAD00_COUNT 8 + +/* #define ROMDEC_SHEAD00_COUNT (8) */ volatile uint8_t SHEAD00; /* SHEAD00 */ volatile uint8_t SHEAD01; /* SHEAD01 */ volatile uint8_t SHEAD02; /* SHEAD02 */ @@ -69,12 +146,14 @@ struct st_romdec volatile uint8_t SHEAD05; /* SHEAD05 */ volatile uint8_t SHEAD06; /* SHEAD06 */ volatile uint8_t SHEAD07; /* SHEAD07 */ -#define ROMDEC_HEAD20_COUNT 4 + +/* #define ROMDEC_HEAD20_COUNT (4) */ volatile uint8_t HEAD20; /* HEAD20 */ volatile uint8_t HEAD21; /* HEAD21 */ volatile uint8_t HEAD22; /* HEAD22 */ volatile uint8_t HEAD23; /* HEAD23 */ -#define ROMDEC_SHEAD20_COUNT 8 + +/* #define ROMDEC_SHEAD20_COUNT (8) */ volatile uint8_t SHEAD20; /* SHEAD20 */ volatile uint8_t SHEAD21; /* SHEAD21 */ volatile uint8_t SHEAD22; /* SHEAD22 */ @@ -84,7 +163,8 @@ struct st_romdec volatile uint8_t SHEAD26; /* SHEAD26 */ volatile uint8_t SHEAD27; /* SHEAD27 */ volatile uint8_t dummy27[16]; /* */ -#define ROMDEC_CBUFCTL0_COUNT 4 + +/* #define ROMDEC_CBUFCTL0_COUNT (4) */ volatile uint8_t CBUFCTL0; /* CBUFCTL0 */ volatile uint8_t CBUFCTL1; /* CBUFCTL1 */ volatile uint8_t CBUFCTL2; /* CBUFCTL2 */ @@ -99,68 +179,16 @@ struct st_romdec volatile uint8_t INTHOLD; /* INTHOLD */ volatile uint8_t INHINT; /* INHINT */ volatile uint8_t dummy31[246]; /* */ -#define ROMDEC_STRMDIN0_COUNT 2 + +/* #define ROMDEC_STRMDIN0_COUNT (2) */ volatile uint16_t STRMDIN0; /* STRMDIN0 */ volatile uint16_t STRMDIN2; /* STRMDIN2 */ volatile uint16_t STRMDOUT0; /* STRMDOUT0 */ -}; - - -#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ +} r_io_romdec_t; -#define ROMDECCROMEN ROMDEC.CROMEN -#define ROMDECCROMSY0 ROMDEC.CROMSY0 -#define ROMDECCROMCTL0 ROMDEC.CROMCTL0 -#define ROMDECCROMCTL1 ROMDEC.CROMCTL1 -#define ROMDECCROMCTL3 ROMDEC.CROMCTL3 -#define ROMDECCROMCTL4 ROMDEC.CROMCTL4 -#define ROMDECCROMCTL5 ROMDEC.CROMCTL5 -#define ROMDECCROMST0 ROMDEC.CROMST0 -#define ROMDECCROMST1 ROMDEC.CROMST1 -#define ROMDECCROMST3 ROMDEC.CROMST3 -#define ROMDECCROMST4 ROMDEC.CROMST4 -#define ROMDECCROMST5 ROMDEC.CROMST5 -#define ROMDECCROMST6 ROMDEC.CROMST6 -#define ROMDECCBUFST0 ROMDEC.CBUFST0 -#define ROMDECCBUFST1 ROMDEC.CBUFST1 -#define ROMDECCBUFST2 ROMDEC.CBUFST2 -#define ROMDECHEAD00 ROMDEC.HEAD00 -#define ROMDECHEAD01 ROMDEC.HEAD01 -#define ROMDECHEAD02 ROMDEC.HEAD02 -#define ROMDECHEAD03 ROMDEC.HEAD03 -#define ROMDECSHEAD00 ROMDEC.SHEAD00 -#define ROMDECSHEAD01 ROMDEC.SHEAD01 -#define ROMDECSHEAD02 ROMDEC.SHEAD02 -#define ROMDECSHEAD03 ROMDEC.SHEAD03 -#define ROMDECSHEAD04 ROMDEC.SHEAD04 -#define ROMDECSHEAD05 ROMDEC.SHEAD05 -#define ROMDECSHEAD06 ROMDEC.SHEAD06 -#define ROMDECSHEAD07 ROMDEC.SHEAD07 -#define ROMDECHEAD20 ROMDEC.HEAD20 -#define ROMDECHEAD21 ROMDEC.HEAD21 -#define ROMDECHEAD22 ROMDEC.HEAD22 -#define ROMDECHEAD23 ROMDEC.HEAD23 -#define ROMDECSHEAD20 ROMDEC.SHEAD20 -#define ROMDECSHEAD21 ROMDEC.SHEAD21 -#define ROMDECSHEAD22 ROMDEC.SHEAD22 -#define ROMDECSHEAD23 ROMDEC.SHEAD23 -#define ROMDECSHEAD24 ROMDEC.SHEAD24 -#define ROMDECSHEAD25 ROMDEC.SHEAD25 -#define ROMDECSHEAD26 ROMDEC.SHEAD26 -#define ROMDECSHEAD27 ROMDEC.SHEAD27 -#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0 -#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1 -#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2 -#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3 -#define ROMDECCROMST0M ROMDEC.CROMST0M -#define ROMDECROMDECRST ROMDEC.ROMDECRST -#define ROMDECRSTSTAT ROMDEC.RSTSTAT -#define ROMDECSSI ROMDEC.SSI -#define ROMDECINTHOLD ROMDEC.INTHOLD -#define ROMDECINHINT ROMDEC.INHINT -#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0 -#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2 -#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h new file mode 100644 index 00000000000..38bc282098a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h @@ -0,0 +1,9346 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rscan0_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef RSCAN0_IODEFINE_H +#define RSCAN0_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ + + +/* Start of channel array defines of RSCAN0 */ + +/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_CFIDm_COUNT (15) +#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ + &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */ +#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */ +#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */ +#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */ +#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */ +#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */ +#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */ +#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */ +#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */ +#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */ +#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */ +#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */ +#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */ +#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */ +#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_TMIDp_COUNT (80) +#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ + &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ + &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \ + &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \ + &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \ + &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \ + &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \ + &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \ + &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \ + &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */ +#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */ +#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */ +#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */ +#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */ +#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */ +#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */ +#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */ +#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */ +#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */ +#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */ +#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */ +#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */ +#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */ +#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */ +#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */ +#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */ +#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */ +#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */ +#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */ +#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */ +#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */ +#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */ +#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */ +#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */ +#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */ +#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */ +#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */ +#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */ +#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */ +#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */ +#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */ +#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */ +#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */ +#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */ +#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */ +#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */ +#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */ +#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */ +#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */ +#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */ +#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */ +#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */ +#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */ +#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */ +#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */ +#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */ +#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */ +#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */ +#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */ +#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */ +#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */ +#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */ +#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */ +#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */ +#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */ +#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */ +#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */ +#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */ +#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */ +#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */ +#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */ +#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */ +#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */ +#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */ +#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */ +#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */ +#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */ +#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */ +#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */ +#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */ +#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */ +#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */ +#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */ +#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */ +#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */ +#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */ +#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */ +#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */ +#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_RFIDm_COUNT (8) +#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */ +#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */ +#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */ +#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */ +#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */ +#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */ +#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */ +#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_RMIDp_COUNT (80) +#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ + &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ + &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \ + &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \ + &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \ + &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \ + &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \ + &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \ + &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \ + &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */ +#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */ +#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */ +#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */ +#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */ +#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */ +#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */ +#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */ +#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */ +#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */ +#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */ +#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */ +#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */ +#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */ +#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */ +#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */ +#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */ +#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */ +#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */ +#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */ +#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */ +#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */ +#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */ +#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */ +#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */ +#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */ +#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */ +#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */ +#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */ +#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */ +#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */ +#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */ +#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */ +#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */ +#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */ +#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */ +#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */ +#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */ +#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */ +#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */ +#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */ +#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */ +#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */ +#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */ +#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */ +#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */ +#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */ +#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */ +#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */ +#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */ +#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */ +#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */ +#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */ +#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */ +#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */ +#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */ +#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */ +#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */ +#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */ +#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */ +#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */ +#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */ +#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */ +#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */ +#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */ +#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */ +#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */ +#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */ +#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */ +#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */ +#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */ +#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */ +#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */ +#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */ +#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */ +#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */ +#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */ +#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */ +#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */ +#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */ +/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */ +#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT (16) +#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ + &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */ +#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */ +#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */ +#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */ +#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */ +#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */ +#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */ +#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */ +#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */ +#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */ +#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */ +#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */ +#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */ +#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */ +#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */ +#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ + + +/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */ +#define RSCAN_FROM_RSCAN0_CnCFG_COUNT (5) +#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */ +#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */ +#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */ +#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ +#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ + +/* End of channel array defines of RSCAN0 */ + + +#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32) +#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L]) +#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL]) +#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH]) +#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H]) +#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL]) +#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH]) +#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32) +#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L]) +#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL]) +#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH]) +#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H]) +#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL]) +#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH]) +#define RSCAN0C0STS (RSCAN0.C0STS.UINT32) +#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L]) +#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL]) +#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH]) +#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H]) +#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL]) +#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH]) +#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32) +#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L]) +#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL]) +#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH]) +#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H]) +#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL]) +#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH]) +#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32) +#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L]) +#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL]) +#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH]) +#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H]) +#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL]) +#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH]) +#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32) +#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L]) +#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL]) +#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH]) +#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H]) +#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL]) +#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH]) +#define RSCAN0C1STS (RSCAN0.C1STS.UINT32) +#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L]) +#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL]) +#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH]) +#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H]) +#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL]) +#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH]) +#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32) +#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L]) +#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL]) +#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH]) +#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H]) +#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL]) +#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH]) +#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32) +#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L]) +#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL]) +#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH]) +#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H]) +#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL]) +#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH]) +#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32) +#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L]) +#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL]) +#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH]) +#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H]) +#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL]) +#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH]) +#define RSCAN0C2STS (RSCAN0.C2STS.UINT32) +#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L]) +#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL]) +#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH]) +#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H]) +#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL]) +#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH]) +#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32) +#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L]) +#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL]) +#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH]) +#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H]) +#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL]) +#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH]) +#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32) +#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L]) +#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL]) +#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH]) +#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H]) +#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL]) +#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH]) +#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32) +#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L]) +#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL]) +#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH]) +#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H]) +#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL]) +#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH]) +#define RSCAN0C3STS (RSCAN0.C3STS.UINT32) +#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L]) +#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL]) +#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH]) +#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H]) +#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL]) +#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH]) +#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32) +#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L]) +#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL]) +#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH]) +#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H]) +#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL]) +#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH]) +#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32) +#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L]) +#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL]) +#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH]) +#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H]) +#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL]) +#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH]) +#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32) +#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L]) +#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL]) +#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH]) +#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H]) +#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL]) +#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH]) +#define RSCAN0C4STS (RSCAN0.C4STS.UINT32) +#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L]) +#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL]) +#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH]) +#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H]) +#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL]) +#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH]) +#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32) +#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L]) +#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL]) +#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH]) +#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H]) +#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL]) +#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH]) +#define RSCAN0GCFG (RSCAN0.GCFG.UINT32) +#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L]) +#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL]) +#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH]) +#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H]) +#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL]) +#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH]) +#define RSCAN0GCTR (RSCAN0.GCTR.UINT32) +#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L]) +#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL]) +#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH]) +#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H]) +#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL]) +#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH]) +#define RSCAN0GSTS (RSCAN0.GSTS.UINT32) +#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L]) +#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL]) +#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH]) +#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H]) +#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL]) +#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH]) +#define RSCAN0GERFL (RSCAN0.GERFL.UINT32) +#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L]) +#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL]) +#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH]) +#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H]) +#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL]) +#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH]) +#define RSCAN0GTSC (RSCAN0.GTSC.UINT32) +#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L]) +#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H]) +#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32) +#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L]) +#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL]) +#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH]) +#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H]) +#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL]) +#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32) +#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32) +#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH]) +#define RSCAN0RMNB (RSCAN0.RMNB.UINT32) +#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L]) +#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL]) +#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH]) +#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H]) +#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL]) +#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH]) +#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32) +#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L]) +#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL]) +#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH]) +#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H]) +#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL]) +#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH]) +#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32) +#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L]) +#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL]) +#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH]) +#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H]) +#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL]) +#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH]) +#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32) +#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L]) +#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL]) +#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH]) +#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H]) +#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL]) +#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH]) +#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32) +#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L]) +#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL]) +#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH]) +#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H]) +#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL]) +#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH]) +#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32) +#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L]) +#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL]) +#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH]) +#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H]) +#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL]) +#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH]) +#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32) +#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L]) +#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL]) +#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH]) +#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H]) +#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL]) +#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH]) +#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32) +#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L]) +#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL]) +#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH]) +#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H]) +#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL]) +#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH]) +#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32) +#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L]) +#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL]) +#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH]) +#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H]) +#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL]) +#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH]) +#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32) +#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L]) +#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL]) +#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH]) +#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H]) +#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL]) +#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH]) +#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32) +#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L]) +#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL]) +#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH]) +#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H]) +#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL]) +#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH]) +#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32) +#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L]) +#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL]) +#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH]) +#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H]) +#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL]) +#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH]) +#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32) +#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L]) +#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL]) +#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH]) +#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H]) +#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL]) +#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH]) +#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32) +#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L]) +#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL]) +#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH]) +#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H]) +#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL]) +#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH]) +#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32) +#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L]) +#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL]) +#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH]) +#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H]) +#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL]) +#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH]) +#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32) +#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L]) +#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL]) +#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH]) +#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H]) +#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL]) +#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH]) +#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32) +#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L]) +#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL]) +#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH]) +#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H]) +#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL]) +#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH]) +#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32) +#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L]) +#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL]) +#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH]) +#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H]) +#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL]) +#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH]) +#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32) +#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L]) +#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL]) +#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH]) +#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H]) +#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL]) +#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH]) +#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32) +#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L]) +#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL]) +#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH]) +#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H]) +#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL]) +#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32) +#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L]) +#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H]) +#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32) +#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L]) +#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H]) +#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32) +#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L]) +#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H]) +#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32) +#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L]) +#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H]) +#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32) +#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L]) +#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H]) +#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32) +#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L]) +#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H]) +#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32) +#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L]) +#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H]) +#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32) +#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L]) +#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H]) +#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32) +#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L]) +#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL]) +#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH]) +#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H]) +#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL]) +#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH]) +#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32) +#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L]) +#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL]) +#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH]) +#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H]) +#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL]) +#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH]) +#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32) +#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L]) +#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL]) +#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH]) +#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H]) +#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL]) +#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH]) +#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32) +#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L]) +#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL]) +#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH]) +#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H]) +#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL]) +#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH]) +#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32) +#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L]) +#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL]) +#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH]) +#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H]) +#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL]) +#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH]) +#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32) +#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L]) +#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL]) +#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH]) +#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H]) +#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL]) +#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH]) +#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32) +#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L]) +#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL]) +#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH]) +#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H]) +#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL]) +#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH]) +#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32) +#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L]) +#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL]) +#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH]) +#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H]) +#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL]) +#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH]) +#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32) +#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L]) +#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL]) +#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH]) +#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H]) +#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL]) +#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH]) +#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32) +#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L]) +#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL]) +#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH]) +#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H]) +#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL]) +#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH]) +#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32) +#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L]) +#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL]) +#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH]) +#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H]) +#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL]) +#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH]) +#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32) +#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L]) +#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL]) +#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH]) +#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H]) +#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL]) +#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH]) +#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32) +#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L]) +#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL]) +#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH]) +#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H]) +#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL]) +#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH]) +#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32) +#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L]) +#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL]) +#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH]) +#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H]) +#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL]) +#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH]) +#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32) +#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L]) +#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL]) +#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH]) +#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H]) +#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL]) +#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH]) +#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32) +#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L]) +#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL]) +#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH]) +#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H]) +#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL]) +#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH]) +#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32) +#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L]) +#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL]) +#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH]) +#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H]) +#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL]) +#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH]) +#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32) +#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L]) +#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL]) +#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH]) +#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H]) +#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL]) +#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH]) +#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32) +#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L]) +#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL]) +#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH]) +#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H]) +#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL]) +#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH]) +#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32) +#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L]) +#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL]) +#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH]) +#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H]) +#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL]) +#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH]) +#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32) +#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L]) +#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL]) +#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH]) +#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H]) +#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL]) +#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH]) +#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32) +#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L]) +#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL]) +#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH]) +#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H]) +#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL]) +#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH]) +#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32) +#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L]) +#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL]) +#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH]) +#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H]) +#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL]) +#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH]) +#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32) +#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L]) +#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL]) +#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH]) +#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H]) +#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL]) +#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH]) +#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32) +#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L]) +#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL]) +#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH]) +#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H]) +#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL]) +#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH]) +#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32) +#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L]) +#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL]) +#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH]) +#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H]) +#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL]) +#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH]) +#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32) +#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L]) +#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL]) +#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH]) +#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H]) +#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL]) +#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH]) +#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32) +#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L]) +#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL]) +#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH]) +#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H]) +#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL]) +#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH]) +#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32) +#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L]) +#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL]) +#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH]) +#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H]) +#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL]) +#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH]) +#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32) +#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L]) +#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL]) +#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH]) +#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H]) +#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL]) +#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32) +#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L]) +#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H]) +#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32) +#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L]) +#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H]) +#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32) +#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L]) +#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H]) +#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32) +#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L]) +#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H]) +#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32) +#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L]) +#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H]) +#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32) +#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L]) +#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H]) +#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32) +#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L]) +#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H]) +#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32) +#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L]) +#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H]) +#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32) +#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L]) +#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H]) +#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32) +#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L]) +#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H]) +#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32) +#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L]) +#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H]) +#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32) +#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L]) +#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H]) +#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32) +#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L]) +#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H]) +#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32) +#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L]) +#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H]) +#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32) +#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L]) +#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H]) +#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH]) +#define RSCAN0FESTS (RSCAN0.FESTS.UINT32) +#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L]) +#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL]) +#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH]) +#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H]) +#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL]) +#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH]) +#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32) +#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L]) +#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL]) +#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH]) +#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H]) +#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL]) +#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH]) +#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32) +#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L]) +#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL]) +#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH]) +#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H]) +#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL]) +#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH]) +#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32) +#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L]) +#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL]) +#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH]) +#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H]) +#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL]) +#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH]) +#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32) +#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L]) +#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL]) +#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH]) +#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H]) +#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL]) +#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH]) +#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32) +#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L]) +#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL]) +#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH]) +#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H]) +#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL]) +#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH]) +#define RSCAN0TMC0 (RSCAN0.TMC0) +#define RSCAN0TMC1 (RSCAN0.TMC1) +#define RSCAN0TMC2 (RSCAN0.TMC2) +#define RSCAN0TMC3 (RSCAN0.TMC3) +#define RSCAN0TMC4 (RSCAN0.TMC4) +#define RSCAN0TMC5 (RSCAN0.TMC5) +#define RSCAN0TMC6 (RSCAN0.TMC6) +#define RSCAN0TMC7 (RSCAN0.TMC7) +#define RSCAN0TMC8 (RSCAN0.TMC8) +#define RSCAN0TMC9 (RSCAN0.TMC9) +#define RSCAN0TMC10 (RSCAN0.TMC10) +#define RSCAN0TMC11 (RSCAN0.TMC11) +#define RSCAN0TMC12 (RSCAN0.TMC12) +#define RSCAN0TMC13 (RSCAN0.TMC13) +#define RSCAN0TMC14 (RSCAN0.TMC14) +#define RSCAN0TMC15 (RSCAN0.TMC15) +#define RSCAN0TMC16 (RSCAN0.TMC16) +#define RSCAN0TMC17 (RSCAN0.TMC17) +#define RSCAN0TMC18 (RSCAN0.TMC18) +#define RSCAN0TMC19 (RSCAN0.TMC19) +#define RSCAN0TMC20 (RSCAN0.TMC20) +#define RSCAN0TMC21 (RSCAN0.TMC21) +#define RSCAN0TMC22 (RSCAN0.TMC22) +#define RSCAN0TMC23 (RSCAN0.TMC23) +#define RSCAN0TMC24 (RSCAN0.TMC24) +#define RSCAN0TMC25 (RSCAN0.TMC25) +#define RSCAN0TMC26 (RSCAN0.TMC26) +#define RSCAN0TMC27 (RSCAN0.TMC27) +#define RSCAN0TMC28 (RSCAN0.TMC28) +#define RSCAN0TMC29 (RSCAN0.TMC29) +#define RSCAN0TMC30 (RSCAN0.TMC30) +#define RSCAN0TMC31 (RSCAN0.TMC31) +#define RSCAN0TMC32 (RSCAN0.TMC32) +#define RSCAN0TMC33 (RSCAN0.TMC33) +#define RSCAN0TMC34 (RSCAN0.TMC34) +#define RSCAN0TMC35 (RSCAN0.TMC35) +#define RSCAN0TMC36 (RSCAN0.TMC36) +#define RSCAN0TMC37 (RSCAN0.TMC37) +#define RSCAN0TMC38 (RSCAN0.TMC38) +#define RSCAN0TMC39 (RSCAN0.TMC39) +#define RSCAN0TMC40 (RSCAN0.TMC40) +#define RSCAN0TMC41 (RSCAN0.TMC41) +#define RSCAN0TMC42 (RSCAN0.TMC42) +#define RSCAN0TMC43 (RSCAN0.TMC43) +#define RSCAN0TMC44 (RSCAN0.TMC44) +#define RSCAN0TMC45 (RSCAN0.TMC45) +#define RSCAN0TMC46 (RSCAN0.TMC46) +#define RSCAN0TMC47 (RSCAN0.TMC47) +#define RSCAN0TMC48 (RSCAN0.TMC48) +#define RSCAN0TMC49 (RSCAN0.TMC49) +#define RSCAN0TMC50 (RSCAN0.TMC50) +#define RSCAN0TMC51 (RSCAN0.TMC51) +#define RSCAN0TMC52 (RSCAN0.TMC52) +#define RSCAN0TMC53 (RSCAN0.TMC53) +#define RSCAN0TMC54 (RSCAN0.TMC54) +#define RSCAN0TMC55 (RSCAN0.TMC55) +#define RSCAN0TMC56 (RSCAN0.TMC56) +#define RSCAN0TMC57 (RSCAN0.TMC57) +#define RSCAN0TMC58 (RSCAN0.TMC58) +#define RSCAN0TMC59 (RSCAN0.TMC59) +#define RSCAN0TMC60 (RSCAN0.TMC60) +#define RSCAN0TMC61 (RSCAN0.TMC61) +#define RSCAN0TMC62 (RSCAN0.TMC62) +#define RSCAN0TMC63 (RSCAN0.TMC63) +#define RSCAN0TMC64 (RSCAN0.TMC64) +#define RSCAN0TMC65 (RSCAN0.TMC65) +#define RSCAN0TMC66 (RSCAN0.TMC66) +#define RSCAN0TMC67 (RSCAN0.TMC67) +#define RSCAN0TMC68 (RSCAN0.TMC68) +#define RSCAN0TMC69 (RSCAN0.TMC69) +#define RSCAN0TMC70 (RSCAN0.TMC70) +#define RSCAN0TMC71 (RSCAN0.TMC71) +#define RSCAN0TMC72 (RSCAN0.TMC72) +#define RSCAN0TMC73 (RSCAN0.TMC73) +#define RSCAN0TMC74 (RSCAN0.TMC74) +#define RSCAN0TMC75 (RSCAN0.TMC75) +#define RSCAN0TMC76 (RSCAN0.TMC76) +#define RSCAN0TMC77 (RSCAN0.TMC77) +#define RSCAN0TMC78 (RSCAN0.TMC78) +#define RSCAN0TMC79 (RSCAN0.TMC79) +#define RSCAN0TMSTS0 (RSCAN0.TMSTS0) +#define RSCAN0TMSTS1 (RSCAN0.TMSTS1) +#define RSCAN0TMSTS2 (RSCAN0.TMSTS2) +#define RSCAN0TMSTS3 (RSCAN0.TMSTS3) +#define RSCAN0TMSTS4 (RSCAN0.TMSTS4) +#define RSCAN0TMSTS5 (RSCAN0.TMSTS5) +#define RSCAN0TMSTS6 (RSCAN0.TMSTS6) +#define RSCAN0TMSTS7 (RSCAN0.TMSTS7) +#define RSCAN0TMSTS8 (RSCAN0.TMSTS8) +#define RSCAN0TMSTS9 (RSCAN0.TMSTS9) +#define RSCAN0TMSTS10 (RSCAN0.TMSTS10) +#define RSCAN0TMSTS11 (RSCAN0.TMSTS11) +#define RSCAN0TMSTS12 (RSCAN0.TMSTS12) +#define RSCAN0TMSTS13 (RSCAN0.TMSTS13) +#define RSCAN0TMSTS14 (RSCAN0.TMSTS14) +#define RSCAN0TMSTS15 (RSCAN0.TMSTS15) +#define RSCAN0TMSTS16 (RSCAN0.TMSTS16) +#define RSCAN0TMSTS17 (RSCAN0.TMSTS17) +#define RSCAN0TMSTS18 (RSCAN0.TMSTS18) +#define RSCAN0TMSTS19 (RSCAN0.TMSTS19) +#define RSCAN0TMSTS20 (RSCAN0.TMSTS20) +#define RSCAN0TMSTS21 (RSCAN0.TMSTS21) +#define RSCAN0TMSTS22 (RSCAN0.TMSTS22) +#define RSCAN0TMSTS23 (RSCAN0.TMSTS23) +#define RSCAN0TMSTS24 (RSCAN0.TMSTS24) +#define RSCAN0TMSTS25 (RSCAN0.TMSTS25) +#define RSCAN0TMSTS26 (RSCAN0.TMSTS26) +#define RSCAN0TMSTS27 (RSCAN0.TMSTS27) +#define RSCAN0TMSTS28 (RSCAN0.TMSTS28) +#define RSCAN0TMSTS29 (RSCAN0.TMSTS29) +#define RSCAN0TMSTS30 (RSCAN0.TMSTS30) +#define RSCAN0TMSTS31 (RSCAN0.TMSTS31) +#define RSCAN0TMSTS32 (RSCAN0.TMSTS32) +#define RSCAN0TMSTS33 (RSCAN0.TMSTS33) +#define RSCAN0TMSTS34 (RSCAN0.TMSTS34) +#define RSCAN0TMSTS35 (RSCAN0.TMSTS35) +#define RSCAN0TMSTS36 (RSCAN0.TMSTS36) +#define RSCAN0TMSTS37 (RSCAN0.TMSTS37) +#define RSCAN0TMSTS38 (RSCAN0.TMSTS38) +#define RSCAN0TMSTS39 (RSCAN0.TMSTS39) +#define RSCAN0TMSTS40 (RSCAN0.TMSTS40) +#define RSCAN0TMSTS41 (RSCAN0.TMSTS41) +#define RSCAN0TMSTS42 (RSCAN0.TMSTS42) +#define RSCAN0TMSTS43 (RSCAN0.TMSTS43) +#define RSCAN0TMSTS44 (RSCAN0.TMSTS44) +#define RSCAN0TMSTS45 (RSCAN0.TMSTS45) +#define RSCAN0TMSTS46 (RSCAN0.TMSTS46) +#define RSCAN0TMSTS47 (RSCAN0.TMSTS47) +#define RSCAN0TMSTS48 (RSCAN0.TMSTS48) +#define RSCAN0TMSTS49 (RSCAN0.TMSTS49) +#define RSCAN0TMSTS50 (RSCAN0.TMSTS50) +#define RSCAN0TMSTS51 (RSCAN0.TMSTS51) +#define RSCAN0TMSTS52 (RSCAN0.TMSTS52) +#define RSCAN0TMSTS53 (RSCAN0.TMSTS53) +#define RSCAN0TMSTS54 (RSCAN0.TMSTS54) +#define RSCAN0TMSTS55 (RSCAN0.TMSTS55) +#define RSCAN0TMSTS56 (RSCAN0.TMSTS56) +#define RSCAN0TMSTS57 (RSCAN0.TMSTS57) +#define RSCAN0TMSTS58 (RSCAN0.TMSTS58) +#define RSCAN0TMSTS59 (RSCAN0.TMSTS59) +#define RSCAN0TMSTS60 (RSCAN0.TMSTS60) +#define RSCAN0TMSTS61 (RSCAN0.TMSTS61) +#define RSCAN0TMSTS62 (RSCAN0.TMSTS62) +#define RSCAN0TMSTS63 (RSCAN0.TMSTS63) +#define RSCAN0TMSTS64 (RSCAN0.TMSTS64) +#define RSCAN0TMSTS65 (RSCAN0.TMSTS65) +#define RSCAN0TMSTS66 (RSCAN0.TMSTS66) +#define RSCAN0TMSTS67 (RSCAN0.TMSTS67) +#define RSCAN0TMSTS68 (RSCAN0.TMSTS68) +#define RSCAN0TMSTS69 (RSCAN0.TMSTS69) +#define RSCAN0TMSTS70 (RSCAN0.TMSTS70) +#define RSCAN0TMSTS71 (RSCAN0.TMSTS71) +#define RSCAN0TMSTS72 (RSCAN0.TMSTS72) +#define RSCAN0TMSTS73 (RSCAN0.TMSTS73) +#define RSCAN0TMSTS74 (RSCAN0.TMSTS74) +#define RSCAN0TMSTS75 (RSCAN0.TMSTS75) +#define RSCAN0TMSTS76 (RSCAN0.TMSTS76) +#define RSCAN0TMSTS77 (RSCAN0.TMSTS77) +#define RSCAN0TMSTS78 (RSCAN0.TMSTS78) +#define RSCAN0TMSTS79 (RSCAN0.TMSTS79) +#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32) +#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32) +#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32) +#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32) +#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32) +#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32) +#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32) +#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32) +#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32) +#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32) +#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L]) +#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H]) +#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32) +#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L]) +#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H]) +#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32) +#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L]) +#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H]) +#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH]) +#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32) +#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L]) +#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL]) +#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH]) +#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H]) +#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL]) +#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH]) +#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32) +#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L]) +#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL]) +#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH]) +#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H]) +#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL]) +#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH]) +#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32) +#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L]) +#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL]) +#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH]) +#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H]) +#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL]) +#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH]) +#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32) +#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L]) +#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL]) +#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH]) +#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H]) +#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL]) +#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH]) +#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32) +#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L]) +#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL]) +#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH]) +#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H]) +#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL]) +#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH]) +#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32) +#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L]) +#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL]) +#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH]) +#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H]) +#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL]) +#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH]) +#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32) +#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L]) +#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL]) +#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH]) +#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H]) +#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL]) +#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH]) +#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32) +#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L]) +#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL]) +#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH]) +#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H]) +#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL]) +#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32) +#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L]) +#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H]) +#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32) +#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L]) +#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H]) +#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32) +#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L]) +#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H]) +#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32) +#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L]) +#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H]) +#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32) +#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L]) +#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H]) +#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32) +#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32) +#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32) +#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32) +#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32) +#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH]) +#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32) +#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L]) +#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL]) +#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH]) +#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H]) +#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL]) +#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH]) +#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32) +#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L]) +#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL]) +#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH]) +#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H]) +#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL]) +#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH]) +#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32) +#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L]) +#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL]) +#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH]) +#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H]) +#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL]) +#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH]) +#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32) +#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L]) +#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL]) +#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH]) +#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H]) +#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL]) +#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH]) +#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32) +#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L]) +#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL]) +#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH]) +#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H]) +#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL]) +#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH]) +#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32) +#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L]) +#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL]) +#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH]) +#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H]) +#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL]) +#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH]) +#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32) +#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L]) +#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL]) +#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH]) +#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H]) +#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL]) +#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH]) +#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32) +#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L]) +#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL]) +#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH]) +#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H]) +#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL]) +#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH]) +#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32) +#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L]) +#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL]) +#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH]) +#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H]) +#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL]) +#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH]) +#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32) +#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L]) +#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL]) +#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH]) +#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H]) +#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL]) +#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32) +#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L]) +#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H]) +#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32) +#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L]) +#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H]) +#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32) +#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L]) +#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H]) +#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32) +#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L]) +#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H]) +#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32) +#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L]) +#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H]) +#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32) +#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32) +#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH]) +#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32) +#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L]) +#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL]) +#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH]) +#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H]) +#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL]) +#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH]) +#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32) +#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L]) +#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL]) +#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH]) +#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H]) +#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL]) +#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH]) +#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32) +#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L]) +#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H]) +#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32) +#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L]) +#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL]) +#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH]) +#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H]) +#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL]) +#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH]) +#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32) +#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L]) +#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL]) +#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH]) +#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H]) +#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL]) +#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH]) +#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32) +#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L]) +#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL]) +#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH]) +#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H]) +#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL]) +#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH]) +#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32) +#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L]) +#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL]) +#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH]) +#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H]) +#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL]) +#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH]) +#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32) +#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L]) +#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL]) +#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH]) +#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H]) +#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL]) +#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH]) +#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32) +#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L]) +#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL]) +#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH]) +#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H]) +#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL]) +#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH]) +#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32) +#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L]) +#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL]) +#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH]) +#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H]) +#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL]) +#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH]) +#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32) +#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L]) +#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL]) +#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH]) +#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H]) +#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL]) +#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH]) +#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32) +#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L]) +#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL]) +#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH]) +#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H]) +#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL]) +#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH]) +#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32) +#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L]) +#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL]) +#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH]) +#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H]) +#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL]) +#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH]) +#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32) +#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L]) +#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL]) +#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH]) +#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H]) +#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL]) +#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH]) +#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32) +#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L]) +#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL]) +#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH]) +#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H]) +#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL]) +#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH]) +#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32) +#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L]) +#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL]) +#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH]) +#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H]) +#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL]) +#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH]) +#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32) +#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L]) +#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL]) +#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH]) +#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H]) +#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL]) +#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH]) +#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32) +#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L]) +#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL]) +#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH]) +#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H]) +#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL]) +#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH]) +#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32) +#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L]) +#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL]) +#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH]) +#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H]) +#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL]) +#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH]) +#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32) +#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L]) +#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL]) +#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH]) +#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H]) +#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL]) +#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH]) +#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32) +#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L]) +#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL]) +#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH]) +#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H]) +#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL]) +#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH]) +#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32) +#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L]) +#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL]) +#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH]) +#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H]) +#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL]) +#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH]) +#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32) +#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L]) +#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL]) +#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH]) +#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H]) +#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL]) +#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH]) +#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32) +#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L]) +#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL]) +#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH]) +#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H]) +#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL]) +#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH]) +#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32) +#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L]) +#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL]) +#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH]) +#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H]) +#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL]) +#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH]) +#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32) +#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L]) +#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL]) +#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH]) +#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H]) +#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL]) +#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH]) +#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32) +#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L]) +#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL]) +#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH]) +#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H]) +#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL]) +#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH]) +#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32) +#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L]) +#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL]) +#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH]) +#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H]) +#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL]) +#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH]) +#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32) +#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L]) +#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL]) +#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH]) +#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H]) +#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL]) +#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH]) +#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32) +#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L]) +#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL]) +#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH]) +#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H]) +#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL]) +#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH]) +#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32) +#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L]) +#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL]) +#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH]) +#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H]) +#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL]) +#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH]) +#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32) +#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L]) +#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL]) +#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH]) +#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H]) +#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL]) +#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH]) +#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32) +#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L]) +#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL]) +#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH]) +#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H]) +#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL]) +#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH]) +#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32) +#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L]) +#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL]) +#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH]) +#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H]) +#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL]) +#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH]) +#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32) +#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L]) +#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL]) +#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH]) +#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H]) +#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL]) +#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH]) +#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32) +#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L]) +#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL]) +#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH]) +#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H]) +#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL]) +#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH]) +#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32) +#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L]) +#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL]) +#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH]) +#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H]) +#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL]) +#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH]) +#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32) +#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L]) +#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL]) +#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH]) +#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H]) +#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL]) +#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH]) +#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32) +#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L]) +#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL]) +#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH]) +#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H]) +#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL]) +#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH]) +#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32) +#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L]) +#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL]) +#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH]) +#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H]) +#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL]) +#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH]) +#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32) +#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L]) +#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL]) +#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH]) +#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H]) +#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL]) +#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH]) +#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32) +#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L]) +#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL]) +#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH]) +#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H]) +#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL]) +#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH]) +#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32) +#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L]) +#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL]) +#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH]) +#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H]) +#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL]) +#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH]) +#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32) +#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L]) +#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL]) +#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH]) +#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H]) +#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL]) +#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH]) +#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32) +#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L]) +#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL]) +#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH]) +#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H]) +#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL]) +#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH]) +#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32) +#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L]) +#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL]) +#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH]) +#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H]) +#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL]) +#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH]) +#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32) +#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L]) +#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL]) +#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH]) +#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H]) +#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL]) +#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH]) +#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32) +#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L]) +#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL]) +#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH]) +#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H]) +#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL]) +#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH]) +#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32) +#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L]) +#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL]) +#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH]) +#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H]) +#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL]) +#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH]) +#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32) +#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L]) +#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL]) +#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH]) +#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H]) +#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL]) +#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH]) +#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32) +#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L]) +#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL]) +#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH]) +#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H]) +#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL]) +#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH]) +#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32) +#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L]) +#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL]) +#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH]) +#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H]) +#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL]) +#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH]) +#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32) +#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L]) +#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL]) +#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH]) +#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H]) +#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL]) +#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH]) +#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32) +#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L]) +#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL]) +#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH]) +#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H]) +#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL]) +#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH]) +#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32) +#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L]) +#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL]) +#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH]) +#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H]) +#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL]) +#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH]) +#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32) +#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L]) +#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL]) +#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH]) +#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H]) +#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL]) +#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH]) +#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32) +#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L]) +#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL]) +#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH]) +#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H]) +#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL]) +#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH]) +#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32) +#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L]) +#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL]) +#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH]) +#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H]) +#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL]) +#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH]) +#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32) +#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L]) +#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL]) +#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH]) +#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H]) +#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL]) +#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH]) +#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32) +#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L]) +#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL]) +#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH]) +#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H]) +#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL]) +#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH]) +#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32) +#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L]) +#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL]) +#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH]) +#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H]) +#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL]) +#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH]) +#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32) +#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L]) +#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL]) +#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH]) +#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H]) +#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL]) +#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH]) +#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32) +#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L]) +#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL]) +#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH]) +#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H]) +#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL]) +#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH]) +#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32) +#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L]) +#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL]) +#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH]) +#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H]) +#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL]) +#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH]) +#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32) +#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L]) +#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL]) +#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH]) +#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H]) +#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL]) +#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH]) +#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32) +#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L]) +#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL]) +#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH]) +#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H]) +#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL]) +#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH]) +#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32) +#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L]) +#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL]) +#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH]) +#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H]) +#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL]) +#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH]) +#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32) +#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L]) +#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL]) +#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH]) +#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H]) +#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL]) +#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH]) +#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32) +#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L]) +#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL]) +#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH]) +#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H]) +#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL]) +#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH]) +#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32) +#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L]) +#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL]) +#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH]) +#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H]) +#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL]) +#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH]) +#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32) +#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L]) +#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL]) +#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH]) +#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H]) +#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL]) +#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH]) +#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32) +#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L]) +#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL]) +#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH]) +#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H]) +#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL]) +#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH]) +#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32) +#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L]) +#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL]) +#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH]) +#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H]) +#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL]) +#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH]) +#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32) +#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L]) +#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL]) +#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH]) +#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H]) +#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL]) +#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH]) +#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32) +#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L]) +#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL]) +#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH]) +#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H]) +#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL]) +#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH]) +#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32) +#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L]) +#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL]) +#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH]) +#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H]) +#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL]) +#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH]) +#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32) +#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L]) +#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL]) +#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH]) +#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H]) +#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL]) +#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH]) +#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32) +#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L]) +#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL]) +#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH]) +#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H]) +#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL]) +#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH]) +#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32) +#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L]) +#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL]) +#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH]) +#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H]) +#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL]) +#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH]) +#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32) +#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L]) +#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL]) +#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH]) +#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H]) +#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL]) +#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH]) +#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32) +#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L]) +#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL]) +#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH]) +#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H]) +#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL]) +#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH]) +#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32) +#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L]) +#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL]) +#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH]) +#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H]) +#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL]) +#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH]) +#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32) +#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L]) +#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL]) +#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH]) +#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H]) +#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL]) +#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH]) +#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32) +#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L]) +#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL]) +#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH]) +#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H]) +#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL]) +#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH]) +#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32) +#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L]) +#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL]) +#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH]) +#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H]) +#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL]) +#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH]) +#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32) +#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L]) +#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL]) +#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH]) +#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H]) +#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL]) +#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH]) +#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32) +#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L]) +#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL]) +#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH]) +#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H]) +#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL]) +#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH]) +#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32) +#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L]) +#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL]) +#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH]) +#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H]) +#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL]) +#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH]) +#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32) +#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L]) +#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL]) +#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH]) +#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H]) +#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL]) +#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH]) +#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32) +#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L]) +#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL]) +#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH]) +#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H]) +#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL]) +#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH]) +#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32) +#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L]) +#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL]) +#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH]) +#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H]) +#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL]) +#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH]) +#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32) +#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L]) +#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL]) +#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH]) +#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H]) +#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL]) +#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH]) +#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32) +#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L]) +#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL]) +#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH]) +#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H]) +#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL]) +#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH]) +#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32) +#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L]) +#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL]) +#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH]) +#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H]) +#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL]) +#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH]) +#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32) +#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L]) +#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL]) +#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH]) +#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H]) +#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL]) +#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH]) +#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32) +#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L]) +#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL]) +#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH]) +#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H]) +#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL]) +#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH]) +#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32) +#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L]) +#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL]) +#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH]) +#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H]) +#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL]) +#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH]) +#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32) +#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L]) +#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL]) +#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH]) +#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H]) +#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL]) +#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH]) +#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32) +#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L]) +#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL]) +#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH]) +#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H]) +#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL]) +#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH]) +#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32) +#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L]) +#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL]) +#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH]) +#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H]) +#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL]) +#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH]) +#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32) +#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L]) +#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL]) +#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH]) +#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H]) +#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL]) +#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH]) +#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32) +#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L]) +#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL]) +#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH]) +#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H]) +#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL]) +#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH]) +#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32) +#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L]) +#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL]) +#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH]) +#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H]) +#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL]) +#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH]) +#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32) +#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L]) +#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL]) +#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH]) +#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H]) +#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL]) +#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH]) +#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32) +#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L]) +#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL]) +#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH]) +#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H]) +#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL]) +#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH]) +#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32) +#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L]) +#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL]) +#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH]) +#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H]) +#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL]) +#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH]) +#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32) +#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L]) +#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL]) +#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH]) +#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H]) +#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL]) +#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH]) +#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32) +#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L]) +#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL]) +#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH]) +#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H]) +#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL]) +#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH]) +#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32) +#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L]) +#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL]) +#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH]) +#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H]) +#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL]) +#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH]) +#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32) +#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L]) +#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL]) +#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH]) +#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H]) +#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL]) +#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH]) +#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32) +#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L]) +#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL]) +#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH]) +#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H]) +#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL]) +#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH]) +#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32) +#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L]) +#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL]) +#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH]) +#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H]) +#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL]) +#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH]) +#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32) +#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L]) +#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL]) +#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH]) +#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H]) +#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL]) +#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH]) +#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32) +#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L]) +#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL]) +#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH]) +#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H]) +#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL]) +#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH]) +#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32) +#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L]) +#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL]) +#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH]) +#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H]) +#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL]) +#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH]) +#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32) +#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L]) +#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL]) +#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH]) +#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H]) +#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL]) +#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH]) +#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32) +#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L]) +#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL]) +#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH]) +#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H]) +#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL]) +#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH]) +#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32) +#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L]) +#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL]) +#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH]) +#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H]) +#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL]) +#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH]) +#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32) +#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L]) +#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL]) +#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH]) +#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H]) +#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL]) +#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH]) +#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32) +#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L]) +#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL]) +#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH]) +#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H]) +#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL]) +#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH]) +#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32) +#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L]) +#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL]) +#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH]) +#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H]) +#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL]) +#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH]) +#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32) +#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L]) +#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL]) +#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH]) +#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H]) +#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL]) +#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH]) +#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32) +#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L]) +#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL]) +#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH]) +#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H]) +#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL]) +#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH]) +#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32) +#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L]) +#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL]) +#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH]) +#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H]) +#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL]) +#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH]) +#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32) +#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L]) +#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL]) +#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH]) +#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H]) +#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL]) +#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH]) +#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32) +#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L]) +#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL]) +#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH]) +#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H]) +#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL]) +#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH]) +#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32) +#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L]) +#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL]) +#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH]) +#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H]) +#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL]) +#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH]) +#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32) +#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L]) +#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL]) +#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH]) +#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H]) +#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL]) +#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH]) +#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32) +#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L]) +#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL]) +#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH]) +#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H]) +#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL]) +#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH]) +#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32) +#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L]) +#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL]) +#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH]) +#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H]) +#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL]) +#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH]) +#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32) +#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L]) +#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL]) +#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH]) +#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H]) +#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL]) +#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH]) +#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32) +#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L]) +#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL]) +#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH]) +#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H]) +#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL]) +#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH]) +#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32) +#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L]) +#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL]) +#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH]) +#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H]) +#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL]) +#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH]) +#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32) +#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L]) +#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL]) +#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH]) +#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H]) +#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL]) +#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH]) +#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32) +#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L]) +#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL]) +#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH]) +#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H]) +#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL]) +#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH]) +#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32) +#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L]) +#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL]) +#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH]) +#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H]) +#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL]) +#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH]) +#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32) +#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L]) +#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL]) +#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH]) +#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H]) +#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL]) +#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH]) +#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32) +#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L]) +#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL]) +#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH]) +#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H]) +#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL]) +#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH]) +#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32) +#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L]) +#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL]) +#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH]) +#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H]) +#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL]) +#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH]) +#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32) +#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L]) +#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL]) +#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH]) +#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H]) +#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL]) +#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH]) +#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32) +#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L]) +#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL]) +#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH]) +#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H]) +#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL]) +#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH]) +#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32) +#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L]) +#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL]) +#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH]) +#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H]) +#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL]) +#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH]) +#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32) +#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L]) +#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL]) +#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH]) +#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H]) +#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL]) +#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH]) +#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32) +#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L]) +#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL]) +#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH]) +#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H]) +#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL]) +#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH]) +#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32) +#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L]) +#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL]) +#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH]) +#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H]) +#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL]) +#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH]) +#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32) +#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L]) +#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL]) +#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH]) +#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H]) +#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL]) +#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH]) +#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32) +#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L]) +#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL]) +#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH]) +#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H]) +#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL]) +#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH]) +#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32) +#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L]) +#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL]) +#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH]) +#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H]) +#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL]) +#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH]) +#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32) +#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L]) +#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL]) +#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH]) +#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H]) +#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL]) +#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH]) +#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32) +#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L]) +#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL]) +#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH]) +#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H]) +#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL]) +#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH]) +#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32) +#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L]) +#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL]) +#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH]) +#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H]) +#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL]) +#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH]) +#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32) +#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L]) +#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL]) +#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH]) +#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H]) +#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL]) +#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH]) +#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32) +#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L]) +#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL]) +#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH]) +#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H]) +#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL]) +#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH]) +#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32) +#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L]) +#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL]) +#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH]) +#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H]) +#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL]) +#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH]) +#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32) +#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L]) +#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL]) +#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH]) +#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H]) +#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL]) +#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH]) +#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32) +#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L]) +#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL]) +#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH]) +#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H]) +#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL]) +#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH]) +#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32) +#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L]) +#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL]) +#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH]) +#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H]) +#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL]) +#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH]) +#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32) +#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L]) +#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL]) +#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH]) +#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H]) +#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL]) +#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH]) +#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32) +#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L]) +#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL]) +#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH]) +#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H]) +#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL]) +#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH]) +#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32) +#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L]) +#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL]) +#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH]) +#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H]) +#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL]) +#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH]) +#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32) +#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L]) +#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL]) +#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH]) +#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H]) +#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL]) +#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH]) +#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32) +#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L]) +#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL]) +#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH]) +#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H]) +#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL]) +#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH]) +#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32) +#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L]) +#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL]) +#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH]) +#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H]) +#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL]) +#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH]) +#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32) +#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L]) +#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL]) +#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH]) +#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H]) +#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL]) +#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH]) +#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32) +#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L]) +#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL]) +#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH]) +#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H]) +#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL]) +#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH]) +#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32) +#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L]) +#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL]) +#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH]) +#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H]) +#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL]) +#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH]) +#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32) +#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L]) +#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL]) +#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH]) +#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H]) +#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL]) +#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH]) +#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32) +#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L]) +#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL]) +#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH]) +#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H]) +#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL]) +#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH]) +#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32) +#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L]) +#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL]) +#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH]) +#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H]) +#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL]) +#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH]) +#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32) +#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L]) +#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL]) +#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH]) +#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H]) +#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL]) +#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH]) +#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32) +#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L]) +#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL]) +#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH]) +#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H]) +#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL]) +#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH]) +#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32) +#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L]) +#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL]) +#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH]) +#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H]) +#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL]) +#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH]) +#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32) +#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L]) +#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL]) +#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH]) +#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H]) +#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL]) +#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH]) +#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32) +#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L]) +#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL]) +#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH]) +#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H]) +#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL]) +#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH]) +#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32) +#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L]) +#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL]) +#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH]) +#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H]) +#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL]) +#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH]) +#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32) +#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L]) +#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL]) +#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH]) +#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H]) +#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL]) +#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH]) +#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32) +#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L]) +#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL]) +#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH]) +#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H]) +#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL]) +#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH]) +#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32) +#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L]) +#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL]) +#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH]) +#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H]) +#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL]) +#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH]) +#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32) +#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L]) +#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL]) +#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH]) +#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H]) +#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL]) +#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH]) +#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32) +#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L]) +#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL]) +#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH]) +#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H]) +#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL]) +#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH]) +#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32) +#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L]) +#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL]) +#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH]) +#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H]) +#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL]) +#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH]) +#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32) +#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L]) +#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL]) +#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH]) +#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H]) +#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL]) +#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH]) +#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32) +#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L]) +#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL]) +#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH]) +#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H]) +#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL]) +#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH]) +#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32) +#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L]) +#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL]) +#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH]) +#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H]) +#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL]) +#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH]) +#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32) +#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L]) +#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL]) +#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH]) +#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H]) +#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL]) +#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH]) +#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32) +#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L]) +#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL]) +#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH]) +#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H]) +#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL]) +#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH]) +#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32) +#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L]) +#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL]) +#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH]) +#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H]) +#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL]) +#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH]) +#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32) +#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L]) +#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL]) +#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH]) +#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H]) +#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL]) +#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH]) +#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32) +#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L]) +#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL]) +#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH]) +#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H]) +#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL]) +#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH]) +#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32) +#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L]) +#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL]) +#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH]) +#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H]) +#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL]) +#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH]) +#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32) +#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L]) +#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL]) +#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH]) +#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H]) +#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL]) +#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH]) +#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32) +#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L]) +#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL]) +#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH]) +#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H]) +#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL]) +#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH]) +#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32) +#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L]) +#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL]) +#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH]) +#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H]) +#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL]) +#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH]) +#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32) +#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L]) +#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL]) +#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH]) +#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H]) +#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL]) +#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH]) +#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32) +#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L]) +#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL]) +#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH]) +#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H]) +#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL]) +#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH]) +#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32) +#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L]) +#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL]) +#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH]) +#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H]) +#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL]) +#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH]) +#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32) +#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L]) +#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL]) +#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH]) +#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H]) +#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL]) +#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH]) +#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32) +#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L]) +#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL]) +#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH]) +#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H]) +#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL]) +#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH]) +#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32) +#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L]) +#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL]) +#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH]) +#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H]) +#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL]) +#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH]) +#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32) +#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L]) +#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL]) +#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH]) +#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H]) +#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL]) +#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH]) +#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32) +#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L]) +#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL]) +#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH]) +#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H]) +#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL]) +#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH]) +#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32) +#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L]) +#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL]) +#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH]) +#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H]) +#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL]) +#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH]) +#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32) +#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L]) +#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL]) +#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH]) +#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H]) +#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL]) +#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH]) +#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32) +#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L]) +#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL]) +#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH]) +#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H]) +#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL]) +#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH]) +#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32) +#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L]) +#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL]) +#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH]) +#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H]) +#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL]) +#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH]) +#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32) +#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L]) +#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL]) +#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH]) +#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H]) +#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL]) +#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH]) +#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32) +#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L]) +#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL]) +#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH]) +#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H]) +#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL]) +#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH]) +#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32) +#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L]) +#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL]) +#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH]) +#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H]) +#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL]) +#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH]) +#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32) +#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L]) +#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL]) +#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH]) +#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H]) +#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL]) +#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH]) +#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32) +#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L]) +#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL]) +#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH]) +#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H]) +#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL]) +#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH]) +#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32) +#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L]) +#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL]) +#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH]) +#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H]) +#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL]) +#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH]) +#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32) +#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L]) +#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL]) +#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH]) +#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H]) +#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL]) +#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH]) +#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32) +#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L]) +#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL]) +#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH]) +#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H]) +#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL]) +#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH]) +#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32) +#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L]) +#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL]) +#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH]) +#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H]) +#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL]) +#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH]) +#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32) +#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L]) +#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL]) +#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH]) +#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H]) +#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL]) +#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH]) +#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32) +#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L]) +#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL]) +#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH]) +#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H]) +#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL]) +#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH]) +#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32) +#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L]) +#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL]) +#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH]) +#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H]) +#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL]) +#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH]) +#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32) +#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L]) +#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL]) +#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH]) +#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H]) +#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL]) +#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH]) +#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32) +#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L]) +#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL]) +#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH]) +#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H]) +#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL]) +#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH]) +#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32) +#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L]) +#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL]) +#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH]) +#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H]) +#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL]) +#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH]) +#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32) +#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L]) +#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL]) +#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH]) +#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H]) +#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL]) +#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH]) +#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32) +#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L]) +#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL]) +#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH]) +#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H]) +#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL]) +#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH]) +#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32) +#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L]) +#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL]) +#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH]) +#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H]) +#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL]) +#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH]) +#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32) +#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L]) +#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL]) +#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH]) +#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H]) +#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL]) +#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH]) +#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32) +#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L]) +#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL]) +#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH]) +#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H]) +#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL]) +#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH]) +#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32) +#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L]) +#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL]) +#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH]) +#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H]) +#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL]) +#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH]) +#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32) +#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L]) +#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL]) +#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH]) +#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H]) +#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL]) +#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH]) +#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32) +#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L]) +#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL]) +#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH]) +#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H]) +#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL]) +#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH]) +#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32) +#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L]) +#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL]) +#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH]) +#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H]) +#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL]) +#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH]) +#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32) +#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L]) +#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL]) +#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH]) +#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H]) +#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL]) +#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH]) +#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32) +#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L]) +#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL]) +#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH]) +#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H]) +#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL]) +#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH]) +#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32) +#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L]) +#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL]) +#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH]) +#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H]) +#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL]) +#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH]) +#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32) +#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L]) +#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL]) +#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH]) +#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H]) +#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL]) +#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH]) +#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32) +#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L]) +#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL]) +#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH]) +#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H]) +#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL]) +#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH]) +#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32) +#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L]) +#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL]) +#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH]) +#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H]) +#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL]) +#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH]) +#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32) +#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L]) +#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL]) +#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH]) +#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H]) +#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL]) +#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH]) +#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32) +#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L]) +#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL]) +#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH]) +#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H]) +#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL]) +#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH]) +#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32) +#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L]) +#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL]) +#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH]) +#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H]) +#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL]) +#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH]) +#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32) +#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L]) +#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL]) +#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH]) +#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H]) +#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL]) +#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH]) +#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32) +#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L]) +#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL]) +#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH]) +#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H]) +#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL]) +#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH]) +#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32) +#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L]) +#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL]) +#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH]) +#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H]) +#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL]) +#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH]) +#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32) +#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L]) +#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL]) +#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH]) +#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H]) +#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL]) +#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH]) +#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32) +#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L]) +#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL]) +#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH]) +#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H]) +#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL]) +#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH]) +#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32) +#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L]) +#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL]) +#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH]) +#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H]) +#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL]) +#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH]) +#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32) +#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L]) +#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL]) +#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH]) +#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H]) +#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL]) +#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH]) +#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32) +#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L]) +#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL]) +#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH]) +#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H]) +#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL]) +#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH]) +#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32) +#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L]) +#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL]) +#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH]) +#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H]) +#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL]) +#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH]) +#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32) +#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L]) +#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL]) +#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH]) +#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H]) +#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL]) +#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH]) +#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32) +#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L]) +#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL]) +#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH]) +#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H]) +#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL]) +#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH]) +#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32) +#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L]) +#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL]) +#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH]) +#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H]) +#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL]) +#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH]) +#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32) +#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L]) +#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL]) +#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH]) +#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H]) +#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL]) +#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH]) +#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32) +#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L]) +#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL]) +#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH]) +#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H]) +#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL]) +#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH]) +#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32) +#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L]) +#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL]) +#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH]) +#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H]) +#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL]) +#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH]) +#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32) +#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L]) +#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL]) +#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH]) +#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H]) +#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL]) +#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH]) +#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32) +#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L]) +#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL]) +#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH]) +#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H]) +#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL]) +#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH]) +#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32) +#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L]) +#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL]) +#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH]) +#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H]) +#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL]) +#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH]) +#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32) +#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L]) +#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL]) +#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH]) +#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H]) +#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL]) +#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH]) +#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32) +#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L]) +#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL]) +#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH]) +#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H]) +#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL]) +#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH]) +#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32) +#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L]) +#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL]) +#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH]) +#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H]) +#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL]) +#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH]) +#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32) +#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L]) +#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL]) +#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH]) +#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H]) +#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL]) +#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH]) +#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32) +#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L]) +#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL]) +#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH]) +#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H]) +#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL]) +#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH]) +#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32) +#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L]) +#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL]) +#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH]) +#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H]) +#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL]) +#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH]) +#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32) +#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L]) +#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL]) +#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH]) +#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H]) +#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL]) +#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH]) +#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32) +#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L]) +#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL]) +#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH]) +#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H]) +#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL]) +#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH]) +#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32) +#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L]) +#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL]) +#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH]) +#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H]) +#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL]) +#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH]) +#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32) +#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L]) +#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL]) +#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH]) +#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H]) +#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL]) +#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH]) +#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32) +#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L]) +#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL]) +#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH]) +#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H]) +#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL]) +#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH]) +#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32) +#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L]) +#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL]) +#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH]) +#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H]) +#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL]) +#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH]) +#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32) +#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L]) +#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL]) +#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH]) +#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H]) +#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL]) +#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH]) +#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32) +#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L]) +#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL]) +#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH]) +#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H]) +#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL]) +#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH]) +#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32) +#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L]) +#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL]) +#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH]) +#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H]) +#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL]) +#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH]) +#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32) +#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L]) +#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL]) +#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH]) +#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H]) +#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL]) +#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH]) +#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32) +#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L]) +#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL]) +#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH]) +#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H]) +#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL]) +#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH]) +#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32) +#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L]) +#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL]) +#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH]) +#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H]) +#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL]) +#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH]) +#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32) +#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L]) +#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL]) +#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH]) +#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H]) +#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL]) +#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH]) +#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32) +#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L]) +#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL]) +#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH]) +#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H]) +#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL]) +#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH]) +#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32) +#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L]) +#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL]) +#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH]) +#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H]) +#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL]) +#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH]) +#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32) +#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L]) +#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL]) +#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH]) +#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H]) +#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL]) +#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH]) +#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32) +#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L]) +#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL]) +#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH]) +#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H]) +#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL]) +#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH]) +#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32) +#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L]) +#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL]) +#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH]) +#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H]) +#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL]) +#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH]) +#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32) +#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L]) +#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL]) +#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH]) +#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H]) +#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL]) +#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH]) +#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32) +#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L]) +#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL]) +#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH]) +#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H]) +#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL]) +#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH]) +#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32) +#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L]) +#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL]) +#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH]) +#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H]) +#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL]) +#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH]) +#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32) +#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L]) +#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL]) +#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH]) +#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H]) +#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL]) +#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH]) +#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32) +#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L]) +#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL]) +#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH]) +#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H]) +#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL]) +#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH]) +#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32) +#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L]) +#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL]) +#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH]) +#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H]) +#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL]) +#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH]) +#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32) +#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L]) +#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL]) +#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH]) +#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H]) +#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL]) +#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH]) +#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32) +#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L]) +#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL]) +#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH]) +#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H]) +#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL]) +#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH]) +#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32) +#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L]) +#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL]) +#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH]) +#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H]) +#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL]) +#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH]) +#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32) +#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L]) +#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL]) +#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH]) +#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H]) +#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL]) +#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH]) +#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32) +#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L]) +#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL]) +#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH]) +#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H]) +#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL]) +#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH]) +#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32) +#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L]) +#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL]) +#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH]) +#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H]) +#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL]) +#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH]) +#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32) +#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L]) +#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL]) +#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH]) +#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H]) +#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL]) +#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH]) +#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32) +#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L]) +#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL]) +#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH]) +#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H]) +#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL]) +#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH]) +#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32) +#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L]) +#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL]) +#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH]) +#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H]) +#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL]) +#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH]) +#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32) +#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L]) +#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL]) +#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH]) +#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H]) +#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL]) +#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH]) +#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32) +#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L]) +#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL]) +#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH]) +#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H]) +#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL]) +#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH]) +#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32) +#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L]) +#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL]) +#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH]) +#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H]) +#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL]) +#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH]) +#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32) +#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L]) +#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL]) +#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH]) +#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H]) +#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL]) +#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH]) +#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32) +#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L]) +#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL]) +#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH]) +#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H]) +#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL]) +#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH]) +#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32) +#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L]) +#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL]) +#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH]) +#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H]) +#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL]) +#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH]) +#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32) +#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L]) +#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL]) +#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH]) +#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H]) +#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL]) +#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH]) +#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32) +#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L]) +#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL]) +#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH]) +#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H]) +#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL]) +#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH]) +#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32) +#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L]) +#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL]) +#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH]) +#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H]) +#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL]) +#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH]) +#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32) +#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L]) +#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL]) +#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH]) +#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H]) +#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL]) +#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH]) +#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32) +#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L]) +#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL]) +#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH]) +#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H]) +#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL]) +#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH]) +#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32) +#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L]) +#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL]) +#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH]) +#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H]) +#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL]) +#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH]) +#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32) +#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L]) +#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL]) +#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH]) +#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H]) +#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL]) +#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH]) +#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32) +#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L]) +#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL]) +#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH]) +#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H]) +#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL]) +#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH]) +#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32) +#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L]) +#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL]) +#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH]) +#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H]) +#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL]) +#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH]) +#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32) +#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L]) +#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL]) +#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH]) +#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H]) +#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL]) +#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH]) +#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32) +#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L]) +#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL]) +#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH]) +#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H]) +#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL]) +#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH]) +#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32) +#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L]) +#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL]) +#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH]) +#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H]) +#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL]) +#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH]) +#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32) +#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L]) +#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL]) +#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH]) +#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H]) +#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL]) +#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH]) +#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32) +#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L]) +#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL]) +#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH]) +#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H]) +#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL]) +#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH]) +#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32) +#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L]) +#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL]) +#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH]) +#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H]) +#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL]) +#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH]) +#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32) +#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L]) +#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL]) +#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH]) +#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H]) +#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL]) +#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH]) +#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32) +#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L]) +#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL]) +#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH]) +#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H]) +#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL]) +#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH]) +#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32) +#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L]) +#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL]) +#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH]) +#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H]) +#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL]) +#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH]) +#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32) +#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L]) +#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL]) +#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH]) +#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H]) +#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL]) +#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH]) +#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32) +#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L]) +#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL]) +#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH]) +#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H]) +#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL]) +#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH]) +#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32) +#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L]) +#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL]) +#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH]) +#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H]) +#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL]) +#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH]) +#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32) +#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L]) +#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL]) +#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH]) +#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H]) +#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL]) +#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH]) +#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32) +#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L]) +#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL]) +#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH]) +#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H]) +#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL]) +#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH]) +#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32) +#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L]) +#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL]) +#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH]) +#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H]) +#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL]) +#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH]) +#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32) +#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L]) +#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL]) +#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH]) +#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H]) +#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL]) +#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH]) +#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32) +#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L]) +#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL]) +#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH]) +#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H]) +#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL]) +#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH]) +#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32) +#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L]) +#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL]) +#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH]) +#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H]) +#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL]) +#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH]) +#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32) +#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L]) +#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL]) +#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH]) +#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H]) +#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL]) +#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH]) +#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32) +#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L]) +#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL]) +#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH]) +#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H]) +#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL]) +#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH]) +#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32) +#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L]) +#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL]) +#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH]) +#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H]) +#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL]) +#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH]) +#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32) +#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L]) +#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL]) +#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH]) +#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H]) +#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL]) +#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH]) +#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32) +#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L]) +#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL]) +#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH]) +#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H]) +#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL]) +#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH]) +#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32) +#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L]) +#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL]) +#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH]) +#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H]) +#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL]) +#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH]) +#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32) +#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L]) +#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL]) +#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH]) +#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H]) +#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL]) +#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH]) +#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32) +#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L]) +#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL]) +#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH]) +#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H]) +#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL]) +#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH]) +#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32) +#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L]) +#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL]) +#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH]) +#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H]) +#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL]) +#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH]) +#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32) +#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L]) +#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL]) +#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH]) +#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H]) +#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL]) +#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH]) +#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32) +#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L]) +#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL]) +#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH]) +#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H]) +#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL]) +#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH]) +#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32) +#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L]) +#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL]) +#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH]) +#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H]) +#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL]) +#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH]) +#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32) +#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L]) +#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL]) +#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH]) +#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H]) +#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL]) +#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH]) +#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32) +#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L]) +#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL]) +#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH]) +#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H]) +#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL]) +#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH]) +#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32) +#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L]) +#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL]) +#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH]) +#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H]) +#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL]) +#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH]) +#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32) +#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L]) +#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL]) +#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH]) +#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H]) +#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL]) +#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH]) +#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32) +#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L]) +#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL]) +#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH]) +#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H]) +#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL]) +#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH]) +#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32) +#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L]) +#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL]) +#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH]) +#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H]) +#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL]) +#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH]) +#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32) +#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L]) +#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL]) +#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH]) +#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H]) +#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL]) +#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH]) +#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32) +#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L]) +#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL]) +#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH]) +#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H]) +#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL]) +#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH]) +#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32) +#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L]) +#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL]) +#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH]) +#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H]) +#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL]) +#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH]) +#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32) +#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L]) +#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL]) +#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH]) +#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H]) +#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL]) +#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH]) +#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32) +#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L]) +#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL]) +#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH]) +#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H]) +#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL]) +#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH]) +#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32) +#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L]) +#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL]) +#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH]) +#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H]) +#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL]) +#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH]) +#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32) +#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L]) +#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL]) +#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH]) +#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H]) +#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL]) +#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH]) +#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32) +#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L]) +#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL]) +#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH]) +#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H]) +#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL]) +#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH]) +#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32) +#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L]) +#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL]) +#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH]) +#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H]) +#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL]) +#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH]) +#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32) +#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L]) +#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL]) +#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH]) +#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H]) +#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL]) +#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH]) +#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32) +#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L]) +#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL]) +#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH]) +#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H]) +#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL]) +#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH]) +#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32) +#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L]) +#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL]) +#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH]) +#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H]) +#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL]) +#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH]) +#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32) +#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L]) +#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL]) +#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH]) +#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H]) +#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL]) +#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH]) +#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32) +#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L]) +#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL]) +#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH]) +#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H]) +#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL]) +#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH]) +#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32) +#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L]) +#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL]) +#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH]) +#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H]) +#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL]) +#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH]) +#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32) +#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L]) +#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL]) +#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH]) +#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H]) +#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL]) +#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH]) +#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32) +#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L]) +#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL]) +#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH]) +#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H]) +#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL]) +#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH]) +#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32) +#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L]) +#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL]) +#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH]) +#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H]) +#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL]) +#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH]) +#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32) +#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L]) +#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL]) +#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH]) +#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H]) +#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL]) +#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH]) +#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32) +#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L]) +#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL]) +#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH]) +#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H]) +#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL]) +#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH]) +#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32) +#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L]) +#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL]) +#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH]) +#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H]) +#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL]) +#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH]) +#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32) +#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L]) +#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL]) +#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH]) +#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H]) +#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL]) +#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH]) +#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32) +#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L]) +#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL]) +#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH]) +#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H]) +#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL]) +#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH]) +#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32) +#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L]) +#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL]) +#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH]) +#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H]) +#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL]) +#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH]) +#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32) +#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L]) +#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL]) +#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH]) +#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H]) +#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL]) +#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH]) +#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32) +#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L]) +#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL]) +#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH]) +#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H]) +#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL]) +#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH]) +#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32) +#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L]) +#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL]) +#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH]) +#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H]) +#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL]) +#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH]) +#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32) +#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L]) +#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL]) +#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH]) +#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H]) +#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL]) +#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH]) +#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32) +#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L]) +#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL]) +#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH]) +#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H]) +#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL]) +#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH]) +#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32) +#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L]) +#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL]) +#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH]) +#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H]) +#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL]) +#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH]) +#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32) +#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L]) +#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL]) +#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH]) +#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H]) +#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL]) +#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH]) +#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32) +#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L]) +#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL]) +#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH]) +#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H]) +#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL]) +#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH]) +#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32) +#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L]) +#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL]) +#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH]) +#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H]) +#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL]) +#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH]) +#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32) +#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L]) +#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL]) +#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH]) +#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H]) +#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL]) +#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH]) +#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32) +#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L]) +#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL]) +#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH]) +#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H]) +#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL]) +#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH]) +#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32) +#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L]) +#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL]) +#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH]) +#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H]) +#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL]) +#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH]) +#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32) +#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L]) +#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL]) +#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH]) +#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H]) +#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL]) +#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH]) +#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32) +#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L]) +#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL]) +#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH]) +#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H]) +#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL]) +#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH]) +#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32) +#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L]) +#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL]) +#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH]) +#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H]) +#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL]) +#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH]) +#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32) +#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L]) +#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL]) +#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH]) +#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H]) +#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL]) +#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH]) +#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32) +#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L]) +#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL]) +#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH]) +#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H]) +#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL]) +#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH]) +#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32) +#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L]) +#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL]) +#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH]) +#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H]) +#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL]) +#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH]) +#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32) +#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L]) +#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H]) +#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH]) +#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32) +#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L]) +#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL]) +#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH]) +#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H]) +#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL]) +#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH]) +#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32) +#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L]) +#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL]) +#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH]) +#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H]) +#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL]) +#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH]) +#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32) +#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L]) +#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL]) +#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH]) +#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H]) +#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL]) +#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH]) +#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32) +#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L]) +#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H]) +#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH]) +#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32) +#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L]) +#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL]) +#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH]) +#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H]) +#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL]) +#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH]) +#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32) +#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L]) +#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL]) +#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH]) +#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H]) +#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL]) +#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH]) +#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32) +#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L]) +#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL]) +#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH]) +#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H]) +#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL]) +#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH]) +#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32) +#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L]) +#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H]) +#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH]) +#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32) +#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L]) +#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL]) +#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH]) +#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H]) +#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL]) +#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH]) +#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32) +#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L]) +#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL]) +#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH]) +#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H]) +#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL]) +#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH]) +#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32) +#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L]) +#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL]) +#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH]) +#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H]) +#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL]) +#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH]) +#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32) +#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L]) +#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H]) +#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH]) +#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32) +#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L]) +#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL]) +#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH]) +#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H]) +#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL]) +#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH]) +#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32) +#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L]) +#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL]) +#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH]) +#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H]) +#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL]) +#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH]) +#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32) +#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L]) +#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL]) +#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH]) +#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H]) +#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL]) +#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH]) +#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32) +#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L]) +#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H]) +#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH]) +#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32) +#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L]) +#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL]) +#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH]) +#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H]) +#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL]) +#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH]) +#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32) +#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L]) +#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL]) +#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH]) +#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H]) +#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL]) +#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH]) +#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32) +#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L]) +#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL]) +#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH]) +#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H]) +#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL]) +#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH]) +#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32) +#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L]) +#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H]) +#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH]) +#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32) +#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L]) +#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL]) +#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH]) +#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H]) +#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL]) +#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH]) +#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32) +#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L]) +#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL]) +#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH]) +#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H]) +#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL]) +#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH]) +#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32) +#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L]) +#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL]) +#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH]) +#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H]) +#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL]) +#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH]) +#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32) +#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L]) +#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H]) +#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH]) +#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32) +#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L]) +#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL]) +#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH]) +#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H]) +#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL]) +#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH]) +#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32) +#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L]) +#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL]) +#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH]) +#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H]) +#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL]) +#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH]) +#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32) +#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L]) +#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL]) +#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH]) +#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H]) +#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL]) +#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH]) +#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32) +#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L]) +#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H]) +#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH]) +#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32) +#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L]) +#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL]) +#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH]) +#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H]) +#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL]) +#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH]) +#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32) +#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L]) +#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL]) +#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH]) +#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H]) +#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL]) +#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32) +#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L]) +#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL]) +#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH]) +#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H]) +#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL]) +#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH]) +#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32) +#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L]) +#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H]) +#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH]) +#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32) +#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L]) +#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL]) +#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH]) +#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H]) +#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL]) +#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH]) +#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32) +#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L]) +#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL]) +#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH]) +#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H]) +#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL]) +#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH]) +#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32) +#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L]) +#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL]) +#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH]) +#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H]) +#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL]) +#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH]) +#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32) +#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L]) +#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H]) +#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH]) +#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32) +#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L]) +#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL]) +#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH]) +#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H]) +#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL]) +#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH]) +#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32) +#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L]) +#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL]) +#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH]) +#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H]) +#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL]) +#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH]) +#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32) +#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L]) +#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL]) +#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH]) +#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H]) +#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL]) +#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH]) +#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32) +#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L]) +#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H]) +#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH]) +#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32) +#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L]) +#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL]) +#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH]) +#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H]) +#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL]) +#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH]) +#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32) +#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L]) +#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL]) +#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH]) +#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H]) +#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL]) +#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH]) +#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32) +#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L]) +#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL]) +#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH]) +#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H]) +#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL]) +#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH]) +#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32) +#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L]) +#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H]) +#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH]) +#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32) +#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L]) +#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL]) +#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH]) +#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H]) +#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL]) +#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH]) +#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32) +#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L]) +#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL]) +#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH]) +#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H]) +#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL]) +#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH]) +#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32) +#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L]) +#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL]) +#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH]) +#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H]) +#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL]) +#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH]) +#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32) +#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L]) +#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H]) +#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH]) +#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32) +#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L]) +#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL]) +#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH]) +#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H]) +#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL]) +#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH]) +#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32) +#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L]) +#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL]) +#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH]) +#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H]) +#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL]) +#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH]) +#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32) +#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L]) +#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL]) +#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH]) +#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H]) +#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL]) +#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH]) +#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32) +#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L]) +#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H]) +#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH]) +#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32) +#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L]) +#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL]) +#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH]) +#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H]) +#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL]) +#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH]) +#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32) +#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L]) +#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL]) +#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH]) +#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H]) +#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL]) +#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH]) +#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32) +#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L]) +#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL]) +#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH]) +#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H]) +#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL]) +#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH]) +#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32) +#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L]) +#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL]) +#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH]) +#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H]) +#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL]) +#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH]) +#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32) +#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L]) +#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL]) +#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH]) +#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H]) +#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL]) +#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH]) +#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32) +#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L]) +#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL]) +#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH]) +#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H]) +#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL]) +#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH]) +#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32) +#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L]) +#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL]) +#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH]) +#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H]) +#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL]) +#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH]) +#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32) +#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L]) +#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL]) +#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH]) +#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H]) +#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL]) +#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH]) +#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32) +#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L]) +#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL]) +#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH]) +#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H]) +#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL]) +#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH]) +#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32) +#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L]) +#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL]) +#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH]) +#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H]) +#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL]) +#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32) +#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L]) +#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL]) +#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH]) +#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H]) +#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL]) +#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH]) +#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32) +#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L]) +#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL]) +#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH]) +#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H]) +#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL]) +#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH]) +#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32) +#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L]) +#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL]) +#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH]) +#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H]) +#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL]) +#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH]) +#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32) +#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L]) +#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL]) +#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH]) +#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H]) +#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL]) +#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH]) +#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32) +#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L]) +#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL]) +#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH]) +#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H]) +#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL]) +#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH]) +#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32) +#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L]) +#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL]) +#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH]) +#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H]) +#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL]) +#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH]) +#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32) +#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L]) +#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL]) +#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH]) +#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H]) +#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL]) +#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH]) +#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32) +#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L]) +#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL]) +#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH]) +#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H]) +#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL]) +#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH]) +#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32) +#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L]) +#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL]) +#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH]) +#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H]) +#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL]) +#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH]) +#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32) +#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L]) +#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL]) +#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH]) +#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H]) +#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL]) +#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH]) +#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32) +#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L]) +#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL]) +#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH]) +#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H]) +#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL]) +#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH]) +#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32) +#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L]) +#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL]) +#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH]) +#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H]) +#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL]) +#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH]) +#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32) +#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L]) +#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL]) +#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH]) +#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H]) +#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL]) +#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH]) +#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32) +#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L]) +#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL]) +#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH]) +#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H]) +#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL]) +#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH]) +#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32) +#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L]) +#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL]) +#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH]) +#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H]) +#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL]) +#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH]) +#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32) +#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L]) +#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL]) +#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH]) +#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H]) +#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL]) +#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH]) +#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32) +#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L]) +#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL]) +#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH]) +#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H]) +#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL]) +#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH]) +#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32) +#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L]) +#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL]) +#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH]) +#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H]) +#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL]) +#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH]) +#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32) +#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L]) +#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL]) +#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH]) +#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H]) +#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL]) +#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH]) +#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32) +#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L]) +#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL]) +#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH]) +#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H]) +#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL]) +#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH]) +#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32) +#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L]) +#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL]) +#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH]) +#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H]) +#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL]) +#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH]) +#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32) +#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L]) +#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL]) +#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH]) +#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H]) +#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL]) +#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH]) +#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32) +#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L]) +#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL]) +#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH]) +#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H]) +#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL]) +#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH]) +#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32) +#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L]) +#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL]) +#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH]) +#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H]) +#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL]) +#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH]) +#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32) +#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L]) +#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL]) +#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH]) +#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H]) +#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL]) +#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH]) +#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32) +#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L]) +#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL]) +#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH]) +#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H]) +#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL]) +#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH]) +#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32) +#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L]) +#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL]) +#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH]) +#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H]) +#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL]) +#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH]) +#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32) +#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L]) +#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL]) +#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH]) +#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H]) +#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL]) +#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32) +#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L]) +#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL]) +#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH]) +#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H]) +#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL]) +#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH]) +#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32) +#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L]) +#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL]) +#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH]) +#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H]) +#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL]) +#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH]) +#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32) +#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L]) +#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL]) +#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH]) +#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H]) +#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL]) +#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH]) +#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32) +#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L]) +#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL]) +#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH]) +#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H]) +#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL]) +#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH]) +#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32) +#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L]) +#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL]) +#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH]) +#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H]) +#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL]) +#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH]) +#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32) +#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L]) +#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL]) +#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH]) +#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H]) +#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL]) +#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH]) +#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32) +#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L]) +#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL]) +#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH]) +#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H]) +#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL]) +#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH]) +#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32) +#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L]) +#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL]) +#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH]) +#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H]) +#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL]) +#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH]) +#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32) +#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L]) +#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL]) +#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH]) +#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H]) +#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL]) +#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH]) +#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32) +#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L]) +#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL]) +#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH]) +#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H]) +#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL]) +#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH]) +#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32) +#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L]) +#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL]) +#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH]) +#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H]) +#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL]) +#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH]) +#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32) +#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L]) +#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL]) +#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH]) +#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H]) +#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL]) +#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH]) +#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32) +#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L]) +#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL]) +#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH]) +#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H]) +#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL]) +#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH]) +#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32) +#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L]) +#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL]) +#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH]) +#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H]) +#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL]) +#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH]) +#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32) +#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L]) +#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL]) +#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH]) +#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H]) +#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL]) +#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH]) +#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32) +#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L]) +#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL]) +#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH]) +#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H]) +#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL]) +#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH]) +#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32) +#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L]) +#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL]) +#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH]) +#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H]) +#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL]) +#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH]) +#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32) +#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L]) +#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL]) +#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH]) +#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H]) +#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL]) +#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH]) +#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32) +#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L]) +#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL]) +#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH]) +#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H]) +#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL]) +#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH]) +#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32) +#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L]) +#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL]) +#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH]) +#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H]) +#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL]) +#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH]) +#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32) +#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L]) +#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL]) +#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH]) +#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H]) +#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL]) +#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH]) +#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32) +#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L]) +#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL]) +#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH]) +#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H]) +#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL]) +#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH]) +#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32) +#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L]) +#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL]) +#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH]) +#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H]) +#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL]) +#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH]) +#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32) +#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L]) +#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL]) +#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH]) +#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H]) +#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL]) +#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH]) +#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32) +#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L]) +#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL]) +#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH]) +#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H]) +#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL]) +#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH]) +#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32) +#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L]) +#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL]) +#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH]) +#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H]) +#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL]) +#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH]) +#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32) +#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L]) +#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL]) +#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH]) +#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H]) +#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL]) +#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH]) +#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32) +#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L]) +#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL]) +#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH]) +#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H]) +#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL]) +#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH]) +#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32) +#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L]) +#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL]) +#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH]) +#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H]) +#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL]) +#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH]) +#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32) +#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L]) +#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL]) +#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH]) +#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H]) +#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL]) +#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH]) +#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32) +#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L]) +#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL]) +#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH]) +#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H]) +#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL]) +#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH]) +#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32) +#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L]) +#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL]) +#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH]) +#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H]) +#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL]) +#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH]) +#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32) +#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L]) +#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL]) +#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH]) +#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H]) +#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL]) +#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH]) +#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32) +#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L]) +#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL]) +#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH]) +#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H]) +#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL]) +#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH]) +#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32) +#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L]) +#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL]) +#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH]) +#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H]) +#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL]) +#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH]) +#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32) +#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L]) +#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL]) +#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH]) +#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H]) +#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL]) +#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH]) +#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32) +#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L]) +#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL]) +#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH]) +#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H]) +#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL]) +#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH]) +#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32) +#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L]) +#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL]) +#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH]) +#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H]) +#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL]) +#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH]) +#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32) +#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L]) +#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL]) +#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH]) +#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H]) +#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL]) +#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH]) +#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32) +#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L]) +#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL]) +#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH]) +#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H]) +#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL]) +#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH]) +#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32) +#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L]) +#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL]) +#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH]) +#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H]) +#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL]) +#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH]) +#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32) +#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L]) +#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL]) +#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH]) +#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H]) +#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL]) +#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH]) +#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32) +#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L]) +#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL]) +#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH]) +#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H]) +#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL]) +#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH]) +#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32) +#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L]) +#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL]) +#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH]) +#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H]) +#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL]) +#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH]) +#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32) +#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L]) +#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL]) +#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH]) +#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H]) +#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL]) +#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH]) +#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32) +#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L]) +#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL]) +#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH]) +#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H]) +#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL]) +#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH]) +#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32) +#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L]) +#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL]) +#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH]) +#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H]) +#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL]) +#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH]) +#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32) +#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L]) +#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL]) +#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH]) +#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H]) +#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL]) +#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH]) +#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32) +#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L]) +#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL]) +#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH]) +#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H]) +#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL]) +#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH]) +#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32) +#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L]) +#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL]) +#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH]) +#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H]) +#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL]) +#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH]) +#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32) +#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L]) +#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL]) +#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH]) +#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H]) +#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL]) +#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH]) +#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32) +#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L]) +#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL]) +#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH]) +#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H]) +#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL]) +#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH]) +#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32) +#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L]) +#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL]) +#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH]) +#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H]) +#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL]) +#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH]) +#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32) +#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L]) +#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL]) +#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH]) +#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H]) +#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL]) +#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH]) +#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32) +#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L]) +#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL]) +#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH]) +#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H]) +#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL]) +#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH]) +#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32) +#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L]) +#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL]) +#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH]) +#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H]) +#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL]) +#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH]) +#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32) +#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L]) +#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL]) +#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH]) +#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H]) +#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL]) +#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH]) +#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32) +#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L]) +#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL]) +#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH]) +#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H]) +#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL]) +#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH]) +#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32) +#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L]) +#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL]) +#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH]) +#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H]) +#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL]) +#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH]) +#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32) +#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L]) +#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL]) +#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH]) +#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H]) +#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL]) +#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32) +#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L]) +#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL]) +#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH]) +#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H]) +#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL]) +#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH]) +#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32) +#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L]) +#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL]) +#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH]) +#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H]) +#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL]) +#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH]) +#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32) +#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L]) +#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL]) +#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH]) +#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H]) +#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL]) +#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH]) +#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32) +#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L]) +#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL]) +#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH]) +#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H]) +#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL]) +#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH]) +#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32) +#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L]) +#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL]) +#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH]) +#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H]) +#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL]) +#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH]) +#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32) +#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L]) +#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL]) +#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH]) +#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H]) +#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL]) +#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH]) +#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32) +#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L]) +#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL]) +#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH]) +#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H]) +#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL]) +#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH]) +#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32) +#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L]) +#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL]) +#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH]) +#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H]) +#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL]) +#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH]) +#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32) +#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L]) +#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL]) +#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH]) +#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H]) +#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL]) +#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH]) +#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32) +#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L]) +#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL]) +#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH]) +#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H]) +#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL]) +#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH]) +#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32) +#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L]) +#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL]) +#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH]) +#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H]) +#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL]) +#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH]) +#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32) +#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L]) +#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL]) +#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH]) +#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H]) +#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL]) +#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH]) +#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32) +#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L]) +#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL]) +#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH]) +#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H]) +#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL]) +#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH]) +#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32) +#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L]) +#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL]) +#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH]) +#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H]) +#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL]) +#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH]) +#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32) +#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L]) +#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL]) +#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH]) +#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H]) +#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL]) +#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH]) +#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32) +#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L]) +#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL]) +#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH]) +#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H]) +#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL]) +#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH]) +#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32) +#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L]) +#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL]) +#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH]) +#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H]) +#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL]) +#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH]) +#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32) +#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L]) +#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL]) +#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH]) +#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H]) +#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL]) +#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH]) +#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32) +#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L]) +#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL]) +#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH]) +#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H]) +#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL]) +#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH]) +#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32) +#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L]) +#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL]) +#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH]) +#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H]) +#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL]) +#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH]) +#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32) +#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L]) +#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL]) +#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH]) +#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H]) +#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL]) +#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH]) +#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32) +#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L]) +#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL]) +#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH]) +#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H]) +#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL]) +#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH]) +#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32) +#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L]) +#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL]) +#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH]) +#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H]) +#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL]) +#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH]) +#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32) +#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L]) +#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL]) +#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH]) +#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H]) +#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL]) +#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH]) +#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32) +#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L]) +#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL]) +#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH]) +#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H]) +#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL]) +#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH]) +#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32) +#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L]) +#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL]) +#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH]) +#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H]) +#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL]) +#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH]) +#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32) +#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L]) +#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL]) +#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH]) +#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H]) +#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL]) +#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH]) +#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32) +#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L]) +#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL]) +#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH]) +#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H]) +#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL]) +#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH]) +#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32) +#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L]) +#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL]) +#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH]) +#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H]) +#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL]) +#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH]) +#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32) +#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L]) +#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL]) +#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH]) +#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H]) +#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL]) +#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH]) +#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32) +#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L]) +#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL]) +#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH]) +#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H]) +#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL]) +#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH]) +#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32) +#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L]) +#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL]) +#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH]) +#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H]) +#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL]) +#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH]) +#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32) +#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L]) +#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL]) +#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH]) +#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H]) +#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL]) +#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH]) +#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32) +#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L]) +#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL]) +#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH]) +#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H]) +#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL]) +#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH]) +#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32) +#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L]) +#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL]) +#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH]) +#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H]) +#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL]) +#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH]) +#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32) +#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L]) +#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL]) +#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH]) +#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H]) +#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL]) +#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH]) +#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32) +#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L]) +#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL]) +#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH]) +#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H]) +#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL]) +#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH]) +#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32) +#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L]) +#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL]) +#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH]) +#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H]) +#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL]) +#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH]) +#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32) +#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L]) +#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL]) +#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH]) +#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H]) +#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL]) +#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH]) +#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32) +#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L]) +#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL]) +#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH]) +#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H]) +#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL]) +#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH]) +#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32) +#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L]) +#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL]) +#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH]) +#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H]) +#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL]) +#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH]) +#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32) +#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L]) +#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL]) +#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH]) +#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H]) +#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL]) +#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH]) +#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32) +#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L]) +#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL]) +#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH]) +#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H]) +#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL]) +#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH]) +#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32) +#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L]) +#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL]) +#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH]) +#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H]) +#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL]) +#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH]) +#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32) +#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L]) +#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL]) +#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH]) +#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H]) +#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL]) +#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH]) +#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32) +#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L]) +#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL]) +#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH]) +#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H]) +#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL]) +#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH]) +#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32) +#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L]) +#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL]) +#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH]) +#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H]) +#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL]) +#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH]) +#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32) +#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L]) +#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL]) +#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH]) +#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H]) +#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL]) +#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH]) +#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32) +#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L]) +#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL]) +#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH]) +#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H]) +#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL]) +#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH]) +#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32) +#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L]) +#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL]) +#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH]) +#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H]) +#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL]) +#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH]) +#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32) +#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L]) +#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL]) +#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH]) +#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H]) +#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL]) +#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH]) +#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32) +#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L]) +#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL]) +#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH]) +#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H]) +#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL]) +#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH]) +#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32) +#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L]) +#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL]) +#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH]) +#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H]) +#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL]) +#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH]) +#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32) +#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L]) +#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL]) +#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH]) +#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H]) +#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL]) +#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH]) +#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32) +#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L]) +#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL]) +#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH]) +#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H]) +#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL]) +#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH]) +#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32) +#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L]) +#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL]) +#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH]) +#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H]) +#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL]) +#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH]) +#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32) +#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L]) +#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL]) +#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH]) +#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H]) +#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL]) +#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH]) +#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32) +#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L]) +#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL]) +#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH]) +#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H]) +#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL]) +#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH]) +#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32) +#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L]) +#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL]) +#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH]) +#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H]) +#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL]) +#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH]) +#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32) +#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L]) +#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL]) +#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH]) +#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H]) +#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL]) +#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH]) +#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32) +#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L]) +#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL]) +#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH]) +#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H]) +#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL]) +#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH]) +#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32) +#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L]) +#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL]) +#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH]) +#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H]) +#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL]) +#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH]) +#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32) +#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L]) +#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL]) +#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH]) +#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H]) +#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL]) +#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH]) +#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32) +#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L]) +#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL]) +#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH]) +#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H]) +#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL]) +#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH]) +#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32) +#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L]) +#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL]) +#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH]) +#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H]) +#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL]) +#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH]) +#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32) +#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L]) +#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL]) +#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH]) +#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H]) +#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL]) +#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH]) +#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32) +#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L]) +#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL]) +#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH]) +#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H]) +#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL]) +#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH]) +#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32) +#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L]) +#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL]) +#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH]) +#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H]) +#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL]) +#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH]) +#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32) +#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L]) +#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL]) +#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH]) +#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H]) +#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL]) +#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH]) +#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32) +#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L]) +#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL]) +#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH]) +#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H]) +#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL]) +#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH]) +#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32) +#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L]) +#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL]) +#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH]) +#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H]) +#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL]) +#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH]) +#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32) +#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L]) +#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL]) +#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH]) +#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H]) +#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL]) +#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH]) +#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32) +#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L]) +#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL]) +#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH]) +#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H]) +#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL]) +#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH]) +#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32) +#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L]) +#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL]) +#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH]) +#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H]) +#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL]) +#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH]) +#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32) +#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L]) +#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL]) +#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH]) +#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H]) +#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL]) +#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH]) +#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32) +#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L]) +#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL]) +#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH]) +#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H]) +#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL]) +#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH]) +#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32) +#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L]) +#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL]) +#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH]) +#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H]) +#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL]) +#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH]) +#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32) +#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L]) +#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL]) +#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH]) +#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H]) +#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL]) +#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH]) +#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32) +#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L]) +#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL]) +#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH]) +#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H]) +#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL]) +#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH]) +#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32) +#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L]) +#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL]) +#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH]) +#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H]) +#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL]) +#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH]) +#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32) +#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L]) +#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL]) +#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH]) +#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H]) +#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL]) +#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH]) +#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32) +#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L]) +#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL]) +#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH]) +#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H]) +#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL]) +#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH]) +#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32) +#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L]) +#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL]) +#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH]) +#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H]) +#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL]) +#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH]) +#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32) +#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L]) +#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL]) +#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH]) +#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H]) +#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL]) +#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH]) +#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32) +#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L]) +#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL]) +#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH]) +#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H]) +#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL]) +#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH]) +#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32) +#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L]) +#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL]) +#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH]) +#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H]) +#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL]) +#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH]) +#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32) +#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L]) +#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL]) +#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH]) +#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H]) +#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL]) +#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH]) +#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32) +#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L]) +#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL]) +#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH]) +#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H]) +#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL]) +#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH]) +#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32) +#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L]) +#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL]) +#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH]) +#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H]) +#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL]) +#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH]) +#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32) +#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L]) +#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL]) +#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH]) +#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H]) +#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL]) +#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH]) +#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32) +#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L]) +#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL]) +#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH]) +#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H]) +#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL]) +#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH]) +#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32) +#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L]) +#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL]) +#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH]) +#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H]) +#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL]) +#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH]) +#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32) +#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L]) +#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL]) +#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH]) +#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H]) +#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL]) +#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH]) +#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32) +#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L]) +#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL]) +#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH]) +#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H]) +#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL]) +#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH]) +#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32) +#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L]) +#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL]) +#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH]) +#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H]) +#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL]) +#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH]) +#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32) +#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L]) +#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL]) +#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH]) +#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H]) +#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL]) +#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH]) +#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32) +#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L]) +#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL]) +#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH]) +#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H]) +#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL]) +#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH]) +#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32) +#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L]) +#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL]) +#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH]) +#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H]) +#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL]) +#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH]) +#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32) +#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L]) +#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL]) +#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH]) +#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H]) +#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL]) +#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH]) +#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32) +#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L]) +#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL]) +#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH]) +#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H]) +#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL]) +#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH]) +#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32) +#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L]) +#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL]) +#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH]) +#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H]) +#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL]) +#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH]) +#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32) +#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L]) +#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL]) +#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH]) +#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H]) +#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL]) +#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH]) +#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32) +#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L]) +#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL]) +#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH]) +#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H]) +#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL]) +#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH]) +#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32) +#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L]) +#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL]) +#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH]) +#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H]) +#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL]) +#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH]) +#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32) +#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L]) +#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL]) +#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH]) +#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H]) +#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL]) +#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH]) +#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32) +#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L]) +#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL]) +#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH]) +#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H]) +#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL]) +#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH]) +#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32) +#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L]) +#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL]) +#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH]) +#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H]) +#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL]) +#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH]) +#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32) +#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L]) +#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL]) +#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH]) +#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H]) +#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL]) +#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH]) +#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32) +#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L]) +#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL]) +#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH]) +#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H]) +#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL]) +#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH]) +#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32) +#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L]) +#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL]) +#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH]) +#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H]) +#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL]) +#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH]) +#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32) +#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L]) +#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL]) +#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH]) +#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H]) +#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL]) +#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH]) +#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32) +#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L]) +#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL]) +#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH]) +#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H]) +#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL]) +#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH]) +#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32) +#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L]) +#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL]) +#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH]) +#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H]) +#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL]) +#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH]) +#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32) +#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L]) +#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL]) +#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH]) +#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H]) +#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL]) +#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH]) +#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32) +#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L]) +#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL]) +#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH]) +#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H]) +#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL]) +#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH]) +#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32) +#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L]) +#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL]) +#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH]) +#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H]) +#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL]) +#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH]) +#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32) +#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L]) +#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL]) +#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH]) +#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H]) +#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL]) +#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH]) +#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32) +#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L]) +#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL]) +#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH]) +#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H]) +#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL]) +#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH]) +#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32) +#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L]) +#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL]) +#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH]) +#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H]) +#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL]) +#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH]) +#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32) +#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L]) +#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL]) +#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH]) +#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H]) +#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL]) +#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH]) +#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32) +#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L]) +#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL]) +#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH]) +#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H]) +#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL]) +#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH]) +#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32) +#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L]) +#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL]) +#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH]) +#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H]) +#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL]) +#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH]) +#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32) +#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L]) +#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL]) +#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH]) +#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H]) +#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL]) +#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH]) +#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32) +#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L]) +#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL]) +#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH]) +#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H]) +#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL]) +#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH]) +#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32) +#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L]) +#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL]) +#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH]) +#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H]) +#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL]) +#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH]) +#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32) +#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L]) +#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL]) +#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH]) +#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H]) +#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL]) +#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH]) +#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32) +#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L]) +#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL]) +#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH]) +#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H]) +#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL]) +#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH]) +#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32) +#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L]) +#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL]) +#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH]) +#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H]) +#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL]) +#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH]) +#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32) +#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L]) +#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL]) +#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH]) +#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H]) +#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL]) +#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH]) +#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32) +#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L]) +#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL]) +#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH]) +#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H]) +#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL]) +#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH]) +#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32) +#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L]) +#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL]) +#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH]) +#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H]) +#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL]) +#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH]) +#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32) +#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L]) +#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL]) +#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH]) +#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H]) +#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL]) +#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH]) +#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32) +#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L]) +#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL]) +#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH]) +#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H]) +#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL]) +#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH]) +#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32) +#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L]) +#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL]) +#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH]) +#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H]) +#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL]) +#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH]) +#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32) +#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L]) +#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL]) +#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH]) +#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H]) +#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL]) +#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH]) +#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32) +#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L]) +#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL]) +#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH]) +#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H]) +#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL]) +#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH]) +#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32) +#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L]) +#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL]) +#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH]) +#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H]) +#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL]) +#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH]) +#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32) +#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L]) +#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL]) +#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH]) +#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H]) +#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL]) +#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH]) +#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32) +#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L]) +#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL]) +#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH]) +#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H]) +#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL]) +#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH]) +#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32) +#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L]) +#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL]) +#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH]) +#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H]) +#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL]) +#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH]) +#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32) +#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L]) +#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL]) +#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH]) +#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H]) +#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL]) +#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH]) +#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32) +#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L]) +#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL]) +#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH]) +#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H]) +#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL]) +#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH]) +#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32) +#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L]) +#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL]) +#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH]) +#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H]) +#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL]) +#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH]) +#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32) +#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L]) +#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL]) +#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH]) +#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H]) +#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL]) +#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH]) +#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32) +#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L]) +#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL]) +#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH]) +#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H]) +#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL]) +#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH]) +#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32) +#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L]) +#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL]) +#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH]) +#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H]) +#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL]) +#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH]) +#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32) +#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L]) +#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL]) +#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH]) +#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H]) +#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL]) +#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH]) +#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32) +#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L]) +#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL]) +#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH]) +#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H]) +#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL]) +#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH]) +#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32) +#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L]) +#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL]) +#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH]) +#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H]) +#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL]) +#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH]) +#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32) +#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L]) +#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL]) +#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH]) +#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H]) +#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL]) +#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH]) +#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32) +#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L]) +#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL]) +#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH]) +#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H]) +#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL]) +#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH]) +#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32) +#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L]) +#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL]) +#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH]) +#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H]) +#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL]) +#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH]) +#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32) +#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L]) +#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL]) +#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH]) +#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H]) +#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL]) +#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH]) +#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32) +#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L]) +#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL]) +#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH]) +#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H]) +#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL]) +#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH]) +#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32) +#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L]) +#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL]) +#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH]) +#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H]) +#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL]) +#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH]) +#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32) +#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L]) +#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL]) +#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH]) +#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H]) +#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL]) +#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH]) +#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32) +#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L]) +#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL]) +#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH]) +#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H]) +#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL]) +#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH]) +#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32) +#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L]) +#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL]) +#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH]) +#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H]) +#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL]) +#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH]) +#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32) +#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L]) +#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL]) +#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH]) +#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H]) +#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL]) +#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH]) +#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32) +#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L]) +#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL]) +#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH]) +#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H]) +#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL]) +#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH]) +#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32) +#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L]) +#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL]) +#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH]) +#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H]) +#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL]) +#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH]) +#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32) +#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L]) +#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL]) +#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH]) +#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H]) +#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL]) +#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH]) +#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32) +#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L]) +#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL]) +#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH]) +#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H]) +#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL]) +#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH]) +#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32) +#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L]) +#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL]) +#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH]) +#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H]) +#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL]) +#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH]) +#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32) +#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L]) +#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL]) +#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH]) +#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H]) +#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL]) +#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH]) +#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32) +#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L]) +#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL]) +#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH]) +#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H]) +#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL]) +#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH]) +#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32) +#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L]) +#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL]) +#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH]) +#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H]) +#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL]) +#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH]) +#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32) +#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L]) +#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL]) +#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH]) +#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H]) +#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL]) +#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH]) +#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32) +#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L]) +#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL]) +#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH]) +#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H]) +#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL]) +#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH]) +#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32) +#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L]) +#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL]) +#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH]) +#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H]) +#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL]) +#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH]) +#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32) +#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L]) +#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL]) +#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH]) +#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H]) +#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL]) +#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH]) +#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32) +#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L]) +#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL]) +#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH]) +#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H]) +#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL]) +#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH]) +#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32) +#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L]) +#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL]) +#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH]) +#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H]) +#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL]) +#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH]) +#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32) +#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L]) +#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL]) +#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH]) +#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H]) +#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL]) +#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH]) +#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32) +#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L]) +#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL]) +#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH]) +#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H]) +#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL]) +#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH]) +#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32) +#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L]) +#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL]) +#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH]) +#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H]) +#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL]) +#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH]) +#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32) +#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L]) +#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL]) +#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH]) +#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H]) +#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL]) +#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH]) +#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32) +#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L]) +#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL]) +#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH]) +#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H]) +#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL]) +#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH]) +#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32) +#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L]) +#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL]) +#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH]) +#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H]) +#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL]) +#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH]) +#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32) +#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L]) +#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL]) +#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH]) +#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H]) +#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL]) +#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH]) +#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32) +#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L]) +#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL]) +#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH]) +#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H]) +#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL]) +#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH]) +#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32) +#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L]) +#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL]) +#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH]) +#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H]) +#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL]) +#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH]) +#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32) +#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L]) +#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL]) +#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH]) +#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H]) +#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL]) +#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH]) +#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32) +#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L]) +#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL]) +#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH]) +#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H]) +#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL]) +#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH]) +#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32) +#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L]) +#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL]) +#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH]) +#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H]) +#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL]) +#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH]) +#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32) +#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L]) +#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL]) +#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH]) +#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H]) +#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL]) +#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH]) +#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32) +#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L]) +#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL]) +#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH]) +#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H]) +#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL]) +#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH]) +#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32) +#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L]) +#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL]) +#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH]) +#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H]) +#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL]) +#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH]) +#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32) +#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L]) +#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL]) +#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH]) +#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H]) +#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL]) +#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH]) +#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32) +#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L]) +#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL]) +#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH]) +#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H]) +#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL]) +#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH]) +#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32) +#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L]) +#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL]) +#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH]) +#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H]) +#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL]) +#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH]) +#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32) +#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L]) +#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL]) +#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH]) +#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H]) +#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL]) +#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH]) +#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32) +#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L]) +#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL]) +#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH]) +#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H]) +#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL]) +#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH]) +#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32) +#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L]) +#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL]) +#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH]) +#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H]) +#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL]) +#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH]) +#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32) +#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L]) +#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL]) +#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH]) +#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H]) +#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL]) +#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH]) +#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32) +#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L]) +#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL]) +#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH]) +#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H]) +#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL]) +#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH]) +#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32) +#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L]) +#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL]) +#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH]) +#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H]) +#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL]) +#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH]) +#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32) +#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L]) +#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL]) +#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH]) +#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H]) +#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL]) +#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH]) +#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32) +#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L]) +#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL]) +#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH]) +#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H]) +#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL]) +#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH]) +#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32) +#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L]) +#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL]) +#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH]) +#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H]) +#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL]) +#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH]) +#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32) +#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L]) +#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL]) +#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH]) +#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H]) +#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL]) +#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH]) +#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32) +#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L]) +#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL]) +#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH]) +#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H]) +#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL]) +#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH]) +#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32) +#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L]) +#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL]) +#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH]) +#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H]) +#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL]) +#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH]) +#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32) +#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L]) +#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL]) +#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH]) +#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H]) +#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL]) +#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH]) +#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32) +#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L]) +#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL]) +#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH]) +#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H]) +#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL]) +#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH]) +#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32) +#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L]) +#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL]) +#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH]) +#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H]) +#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL]) +#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH]) +#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32) +#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L]) +#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL]) +#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH]) +#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H]) +#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL]) +#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH]) +#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32) +#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L]) +#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL]) +#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH]) +#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H]) +#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL]) +#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH]) +#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32) +#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L]) +#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL]) +#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH]) +#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H]) +#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL]) +#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH]) +#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32) +#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L]) +#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL]) +#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH]) +#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H]) +#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL]) +#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH]) +#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32) +#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L]) +#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL]) +#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH]) +#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H]) +#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL]) +#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH]) +#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32) +#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L]) +#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL]) +#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH]) +#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H]) +#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL]) +#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH]) +#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32) +#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L]) +#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL]) +#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH]) +#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H]) +#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL]) +#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH]) +#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32) +#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L]) +#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL]) +#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH]) +#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H]) +#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL]) +#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH]) +#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32) +#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L]) +#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL]) +#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH]) +#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H]) +#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL]) +#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH]) +#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32) +#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L]) +#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL]) +#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH]) +#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H]) +#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL]) +#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH]) +#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32) +#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L]) +#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL]) +#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH]) +#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H]) +#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL]) +#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH]) +#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32) +#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L]) +#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL]) +#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH]) +#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H]) +#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL]) +#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH]) +#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32) +#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L]) +#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL]) +#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH]) +#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H]) +#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL]) +#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH]) +#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32) +#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L]) +#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL]) +#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH]) +#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H]) +#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL]) +#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH]) +#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32) +#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L]) +#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL]) +#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH]) +#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H]) +#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL]) +#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH]) +#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32) +#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L]) +#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL]) +#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH]) +#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H]) +#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL]) +#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH]) +#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32) +#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L]) +#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL]) +#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH]) +#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H]) +#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL]) +#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH]) +#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32) +#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L]) +#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL]) +#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH]) +#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H]) +#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL]) +#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH]) +#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32) +#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L]) +#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL]) +#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH]) +#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H]) +#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL]) +#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH]) +#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32) +#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L]) +#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL]) +#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH]) +#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H]) +#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL]) +#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH]) +#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32) +#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L]) +#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL]) +#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH]) +#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H]) +#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL]) +#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH]) +#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32) +#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L]) +#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL]) +#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH]) +#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H]) +#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL]) +#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH]) +#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32) +#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L]) +#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL]) +#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH]) +#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H]) +#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL]) +#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH]) +#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32) +#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L]) +#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL]) +#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH]) +#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H]) +#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL]) +#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH]) +#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32) +#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L]) +#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL]) +#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH]) +#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H]) +#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL]) +#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH]) +#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32) +#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L]) +#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL]) +#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH]) +#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H]) +#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL]) +#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH]) +#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32) +#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L]) +#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL]) +#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH]) +#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H]) +#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL]) +#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH]) +#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32) +#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L]) +#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL]) +#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH]) +#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H]) +#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL]) +#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH]) +#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32) +#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L]) +#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL]) +#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH]) +#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H]) +#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL]) +#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH]) +#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32) +#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L]) +#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL]) +#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH]) +#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H]) +#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL]) +#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH]) +#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32) +#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L]) +#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL]) +#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH]) +#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H]) +#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL]) +#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH]) +#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32) +#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L]) +#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL]) +#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH]) +#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H]) +#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL]) +#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH]) +#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32) +#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L]) +#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL]) +#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH]) +#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H]) +#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL]) +#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH]) +#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32) +#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L]) +#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL]) +#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH]) +#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H]) +#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL]) +#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH]) +#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32) +#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L]) +#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL]) +#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH]) +#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H]) +#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL]) +#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH]) +#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32) +#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L]) +#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL]) +#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH]) +#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H]) +#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL]) +#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH]) +#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32) +#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L]) +#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL]) +#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH]) +#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H]) +#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL]) +#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH]) +#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32) +#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L]) +#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL]) +#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH]) +#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H]) +#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL]) +#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH]) +#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32) +#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L]) +#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL]) +#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH]) +#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H]) +#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL]) +#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH]) +#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32) +#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L]) +#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL]) +#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH]) +#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H]) +#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL]) +#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH]) +#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32) +#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L]) +#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL]) +#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH]) +#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H]) +#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL]) +#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH]) +#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32) +#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L]) +#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL]) +#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH]) +#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H]) +#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL]) +#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH]) +#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32) +#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L]) +#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL]) +#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH]) +#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H]) +#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL]) +#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH]) +#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32) +#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L]) +#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL]) +#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH]) +#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H]) +#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL]) +#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH]) +#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32) +#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L]) +#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL]) +#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH]) +#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H]) +#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL]) +#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH]) +#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32) +#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L]) +#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL]) +#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH]) +#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H]) +#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL]) +#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH]) +#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32) +#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L]) +#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL]) +#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH]) +#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H]) +#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL]) +#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH]) +#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32) +#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L]) +#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL]) +#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH]) +#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H]) +#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL]) +#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH]) +#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32) +#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L]) +#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL]) +#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH]) +#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H]) +#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL]) +#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH]) +#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32) +#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L]) +#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL]) +#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH]) +#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H]) +#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL]) +#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH]) +#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32) +#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L]) +#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL]) +#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH]) +#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H]) +#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL]) +#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH]) +#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32) +#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L]) +#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL]) +#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH]) +#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H]) +#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL]) +#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH]) +#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32) +#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L]) +#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL]) +#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH]) +#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H]) +#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL]) +#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH]) +#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32) +#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L]) +#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL]) +#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH]) +#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H]) +#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL]) +#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH]) +#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32) +#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L]) +#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL]) +#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH]) +#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H]) +#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL]) +#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH]) +#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32) +#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L]) +#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL]) +#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH]) +#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H]) +#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL]) +#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH]) +#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32) +#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L]) +#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL]) +#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH]) +#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H]) +#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL]) +#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH]) +#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32) +#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L]) +#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL]) +#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH]) +#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H]) +#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL]) +#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH]) +#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32) +#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L]) +#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL]) +#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH]) +#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H]) +#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL]) +#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH]) + +#define RSCAN0_GAFLCFG0_COUNT (2) +#define RSCAN0_RMND0_COUNT (3) +#define RSCAN0_RFCC0_COUNT (8) +#define RSCAN0_RFSTS0_COUNT (8) +#define RSCAN0_RFPCTR0_COUNT (8) +#define RSCAN0_CFCC0_COUNT (15) +#define RSCAN0_CFSTS0_COUNT (15) +#define RSCAN0_CFPCTR0_COUNT (15) +#define RSCAN0_TMC0_COUNT (80) +#define RSCAN0_TMSTS0_COUNT (80) +#define RSCAN0_TMTRSTS0_COUNT (3) +#define RSCAN0_TMTARSTS0_COUNT (3) +#define RSCAN0_TMTCSTS0_COUNT (3) +#define RSCAN0_TMTASTS0_COUNT (3) +#define RSCAN0_TMIEC0_COUNT (3) +#define RSCAN0_TXQCC0_COUNT (5) +#define RSCAN0_TXQSTS0_COUNT (5) +#define RSCAN0_TXQPCTR0_COUNT (5) +#define RSCAN0_THLCC0_COUNT (5) +#define RSCAN0_THLSTS0_COUNT (5) +#define RSCAN0_THLPCTR0_COUNT (5) +#define RSCAN0_GTINTSTS0_COUNT (2) +#define RSCAN0_THLACC0_COUNT (5) + + +typedef struct st_rscan0 +{ + /* RSCAN0 */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C0CFG; /* C0CFG */ + union iodefine_reg32_t C0CTR; /* C0CTR */ + union iodefine_reg32_t C0STS; /* C0STS */ + union iodefine_reg32_t C0ERFL; /* C0ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C1CFG; /* C1CFG */ + union iodefine_reg32_t C1CTR; /* C1CTR */ + union iodefine_reg32_t C1STS; /* C1STS */ + union iodefine_reg32_t C1ERFL; /* C1ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C2CFG; /* C2CFG */ + union iodefine_reg32_t C2CTR; /* C2CTR */ + union iodefine_reg32_t C2STS; /* C2STS */ + union iodefine_reg32_t C2ERFL; /* C2ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C3CFG; /* C3CFG */ + union iodefine_reg32_t C3CTR; /* C3CTR */ + union iodefine_reg32_t C3STS; /* C3STS */ + union iodefine_reg32_t C3ERFL; /* C3ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C4CFG; /* C4CFG */ + union iodefine_reg32_t C4CTR; /* C4CTR */ + union iodefine_reg32_t C4STS; /* C4STS */ + union iodefine_reg32_t C4ERFL; /* C4ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + + volatile uint8_t dummy159[52]; /* */ + union iodefine_reg32_t GCFG; /* GCFG */ + union iodefine_reg32_t GCTR; /* GCTR */ + union iodefine_reg32_t GSTS; /* GSTS */ + union iodefine_reg32_t GERFL; /* GERFL */ + union iodefine_reg32_16_t GTSC; /* GTSC */ + union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ + +/* #define RSCAN0_GAFLCFG0_COUNT (2) */ + union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ + union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ + union iodefine_reg32_t RMNB; /* RMNB */ + +/* #define RSCAN0_RMND0_COUNT (3) */ + union iodefine_reg32_t RMND0; /* RMND0 */ + union iodefine_reg32_t RMND1; /* RMND1 */ + union iodefine_reg32_t RMND2; /* RMND2 */ + + volatile uint8_t dummy160[4]; /* */ + +/* #define RSCAN0_RFCC0_COUNT (8) */ + union iodefine_reg32_t RFCC0; /* RFCC0 */ + union iodefine_reg32_t RFCC1; /* RFCC1 */ + union iodefine_reg32_t RFCC2; /* RFCC2 */ + union iodefine_reg32_t RFCC3; /* RFCC3 */ + union iodefine_reg32_t RFCC4; /* RFCC4 */ + union iodefine_reg32_t RFCC5; /* RFCC5 */ + union iodefine_reg32_t RFCC6; /* RFCC6 */ + union iodefine_reg32_t RFCC7; /* RFCC7 */ + +/* #define RSCAN0_RFSTS0_COUNT (8) */ + union iodefine_reg32_t RFSTS0; /* RFSTS0 */ + union iodefine_reg32_t RFSTS1; /* RFSTS1 */ + union iodefine_reg32_t RFSTS2; /* RFSTS2 */ + union iodefine_reg32_t RFSTS3; /* RFSTS3 */ + union iodefine_reg32_t RFSTS4; /* RFSTS4 */ + union iodefine_reg32_t RFSTS5; /* RFSTS5 */ + union iodefine_reg32_t RFSTS6; /* RFSTS6 */ + union iodefine_reg32_t RFSTS7; /* RFSTS7 */ + +/* #define RSCAN0_RFPCTR0_COUNT (8) */ + union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ + union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ + union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ + union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ + union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ + union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ + union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ + union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ + +/* #define RSCAN0_CFCC0_COUNT (15) */ + union iodefine_reg32_t CFCC0; /* CFCC0 */ + union iodefine_reg32_t CFCC1; /* CFCC1 */ + union iodefine_reg32_t CFCC2; /* CFCC2 */ + union iodefine_reg32_t CFCC3; /* CFCC3 */ + union iodefine_reg32_t CFCC4; /* CFCC4 */ + union iodefine_reg32_t CFCC5; /* CFCC5 */ + union iodefine_reg32_t CFCC6; /* CFCC6 */ + union iodefine_reg32_t CFCC7; /* CFCC7 */ + union iodefine_reg32_t CFCC8; /* CFCC8 */ + union iodefine_reg32_t CFCC9; /* CFCC9 */ + union iodefine_reg32_t CFCC10; /* CFCC10 */ + union iodefine_reg32_t CFCC11; /* CFCC11 */ + union iodefine_reg32_t CFCC12; /* CFCC12 */ + union iodefine_reg32_t CFCC13; /* CFCC13 */ + union iodefine_reg32_t CFCC14; /* CFCC14 */ + + volatile uint8_t dummy161[36]; /* */ + +/* #define RSCAN0_CFSTS0_COUNT (15) */ + union iodefine_reg32_t CFSTS0; /* CFSTS0 */ + union iodefine_reg32_t CFSTS1; /* CFSTS1 */ + union iodefine_reg32_t CFSTS2; /* CFSTS2 */ + union iodefine_reg32_t CFSTS3; /* CFSTS3 */ + union iodefine_reg32_t CFSTS4; /* CFSTS4 */ + union iodefine_reg32_t CFSTS5; /* CFSTS5 */ + union iodefine_reg32_t CFSTS6; /* CFSTS6 */ + union iodefine_reg32_t CFSTS7; /* CFSTS7 */ + union iodefine_reg32_t CFSTS8; /* CFSTS8 */ + union iodefine_reg32_t CFSTS9; /* CFSTS9 */ + union iodefine_reg32_t CFSTS10; /* CFSTS10 */ + union iodefine_reg32_t CFSTS11; /* CFSTS11 */ + union iodefine_reg32_t CFSTS12; /* CFSTS12 */ + union iodefine_reg32_t CFSTS13; /* CFSTS13 */ + union iodefine_reg32_t CFSTS14; /* CFSTS14 */ + + volatile uint8_t dummy162[36]; /* */ + +/* #define RSCAN0_CFPCTR0_COUNT (15) */ + union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ + union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ + union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ + union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ + union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ + union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ + union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ + union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ + union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ + union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ + union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ + union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ + union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ + union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ + union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ + + volatile uint8_t dummy163[36]; /* */ + union iodefine_reg32_t FESTS; /* FESTS */ + union iodefine_reg32_t FFSTS; /* FFSTS */ + union iodefine_reg32_t FMSTS; /* FMSTS */ + union iodefine_reg32_t RFISTS; /* RFISTS */ + union iodefine_reg32_t CFRISTS; /* CFRISTS */ + union iodefine_reg32_t CFTISTS; /* CFTISTS */ + + +/* #define RSCAN0_TMC0_COUNT (80) */ + volatile uint8_t TMC0; /* TMC0 */ + volatile uint8_t TMC1; /* TMC1 */ + volatile uint8_t TMC2; /* TMC2 */ + volatile uint8_t TMC3; /* TMC3 */ + volatile uint8_t TMC4; /* TMC4 */ + volatile uint8_t TMC5; /* TMC5 */ + volatile uint8_t TMC6; /* TMC6 */ + volatile uint8_t TMC7; /* TMC7 */ + volatile uint8_t TMC8; /* TMC8 */ + volatile uint8_t TMC9; /* TMC9 */ + volatile uint8_t TMC10; /* TMC10 */ + volatile uint8_t TMC11; /* TMC11 */ + volatile uint8_t TMC12; /* TMC12 */ + volatile uint8_t TMC13; /* TMC13 */ + volatile uint8_t TMC14; /* TMC14 */ + volatile uint8_t TMC15; /* TMC15 */ + volatile uint8_t TMC16; /* TMC16 */ + volatile uint8_t TMC17; /* TMC17 */ + volatile uint8_t TMC18; /* TMC18 */ + volatile uint8_t TMC19; /* TMC19 */ + volatile uint8_t TMC20; /* TMC20 */ + volatile uint8_t TMC21; /* TMC21 */ + volatile uint8_t TMC22; /* TMC22 */ + volatile uint8_t TMC23; /* TMC23 */ + volatile uint8_t TMC24; /* TMC24 */ + volatile uint8_t TMC25; /* TMC25 */ + volatile uint8_t TMC26; /* TMC26 */ + volatile uint8_t TMC27; /* TMC27 */ + volatile uint8_t TMC28; /* TMC28 */ + volatile uint8_t TMC29; /* TMC29 */ + volatile uint8_t TMC30; /* TMC30 */ + volatile uint8_t TMC31; /* TMC31 */ + volatile uint8_t TMC32; /* TMC32 */ + volatile uint8_t TMC33; /* TMC33 */ + volatile uint8_t TMC34; /* TMC34 */ + volatile uint8_t TMC35; /* TMC35 */ + volatile uint8_t TMC36; /* TMC36 */ + volatile uint8_t TMC37; /* TMC37 */ + volatile uint8_t TMC38; /* TMC38 */ + volatile uint8_t TMC39; /* TMC39 */ + volatile uint8_t TMC40; /* TMC40 */ + volatile uint8_t TMC41; /* TMC41 */ + volatile uint8_t TMC42; /* TMC42 */ + volatile uint8_t TMC43; /* TMC43 */ + volatile uint8_t TMC44; /* TMC44 */ + volatile uint8_t TMC45; /* TMC45 */ + volatile uint8_t TMC46; /* TMC46 */ + volatile uint8_t TMC47; /* TMC47 */ + volatile uint8_t TMC48; /* TMC48 */ + volatile uint8_t TMC49; /* TMC49 */ + volatile uint8_t TMC50; /* TMC50 */ + volatile uint8_t TMC51; /* TMC51 */ + volatile uint8_t TMC52; /* TMC52 */ + volatile uint8_t TMC53; /* TMC53 */ + volatile uint8_t TMC54; /* TMC54 */ + volatile uint8_t TMC55; /* TMC55 */ + volatile uint8_t TMC56; /* TMC56 */ + volatile uint8_t TMC57; /* TMC57 */ + volatile uint8_t TMC58; /* TMC58 */ + volatile uint8_t TMC59; /* TMC59 */ + volatile uint8_t TMC60; /* TMC60 */ + volatile uint8_t TMC61; /* TMC61 */ + volatile uint8_t TMC62; /* TMC62 */ + volatile uint8_t TMC63; /* TMC63 */ + volatile uint8_t TMC64; /* TMC64 */ + volatile uint8_t TMC65; /* TMC65 */ + volatile uint8_t TMC66; /* TMC66 */ + volatile uint8_t TMC67; /* TMC67 */ + volatile uint8_t TMC68; /* TMC68 */ + volatile uint8_t TMC69; /* TMC69 */ + volatile uint8_t TMC70; /* TMC70 */ + volatile uint8_t TMC71; /* TMC71 */ + volatile uint8_t TMC72; /* TMC72 */ + volatile uint8_t TMC73; /* TMC73 */ + volatile uint8_t TMC74; /* TMC74 */ + volatile uint8_t TMC75; /* TMC75 */ + volatile uint8_t TMC76; /* TMC76 */ + volatile uint8_t TMC77; /* TMC77 */ + volatile uint8_t TMC78; /* TMC78 */ + volatile uint8_t TMC79; /* TMC79 */ + volatile uint8_t dummy164[48]; /* */ + +/* #define RSCAN0_TMSTS0_COUNT (80) */ + volatile uint8_t TMSTS0; /* TMSTS0 */ + volatile uint8_t TMSTS1; /* TMSTS1 */ + volatile uint8_t TMSTS2; /* TMSTS2 */ + volatile uint8_t TMSTS3; /* TMSTS3 */ + volatile uint8_t TMSTS4; /* TMSTS4 */ + volatile uint8_t TMSTS5; /* TMSTS5 */ + volatile uint8_t TMSTS6; /* TMSTS6 */ + volatile uint8_t TMSTS7; /* TMSTS7 */ + volatile uint8_t TMSTS8; /* TMSTS8 */ + volatile uint8_t TMSTS9; /* TMSTS9 */ + volatile uint8_t TMSTS10; /* TMSTS10 */ + volatile uint8_t TMSTS11; /* TMSTS11 */ + volatile uint8_t TMSTS12; /* TMSTS12 */ + volatile uint8_t TMSTS13; /* TMSTS13 */ + volatile uint8_t TMSTS14; /* TMSTS14 */ + volatile uint8_t TMSTS15; /* TMSTS15 */ + volatile uint8_t TMSTS16; /* TMSTS16 */ + volatile uint8_t TMSTS17; /* TMSTS17 */ + volatile uint8_t TMSTS18; /* TMSTS18 */ + volatile uint8_t TMSTS19; /* TMSTS19 */ + volatile uint8_t TMSTS20; /* TMSTS20 */ + volatile uint8_t TMSTS21; /* TMSTS21 */ + volatile uint8_t TMSTS22; /* TMSTS22 */ + volatile uint8_t TMSTS23; /* TMSTS23 */ + volatile uint8_t TMSTS24; /* TMSTS24 */ + volatile uint8_t TMSTS25; /* TMSTS25 */ + volatile uint8_t TMSTS26; /* TMSTS26 */ + volatile uint8_t TMSTS27; /* TMSTS27 */ + volatile uint8_t TMSTS28; /* TMSTS28 */ + volatile uint8_t TMSTS29; /* TMSTS29 */ + volatile uint8_t TMSTS30; /* TMSTS30 */ + volatile uint8_t TMSTS31; /* TMSTS31 */ + volatile uint8_t TMSTS32; /* TMSTS32 */ + volatile uint8_t TMSTS33; /* TMSTS33 */ + volatile uint8_t TMSTS34; /* TMSTS34 */ + volatile uint8_t TMSTS35; /* TMSTS35 */ + volatile uint8_t TMSTS36; /* TMSTS36 */ + volatile uint8_t TMSTS37; /* TMSTS37 */ + volatile uint8_t TMSTS38; /* TMSTS38 */ + volatile uint8_t TMSTS39; /* TMSTS39 */ + volatile uint8_t TMSTS40; /* TMSTS40 */ + volatile uint8_t TMSTS41; /* TMSTS41 */ + volatile uint8_t TMSTS42; /* TMSTS42 */ + volatile uint8_t TMSTS43; /* TMSTS43 */ + volatile uint8_t TMSTS44; /* TMSTS44 */ + volatile uint8_t TMSTS45; /* TMSTS45 */ + volatile uint8_t TMSTS46; /* TMSTS46 */ + volatile uint8_t TMSTS47; /* TMSTS47 */ + volatile uint8_t TMSTS48; /* TMSTS48 */ + volatile uint8_t TMSTS49; /* TMSTS49 */ + volatile uint8_t TMSTS50; /* TMSTS50 */ + volatile uint8_t TMSTS51; /* TMSTS51 */ + volatile uint8_t TMSTS52; /* TMSTS52 */ + volatile uint8_t TMSTS53; /* TMSTS53 */ + volatile uint8_t TMSTS54; /* TMSTS54 */ + volatile uint8_t TMSTS55; /* TMSTS55 */ + volatile uint8_t TMSTS56; /* TMSTS56 */ + volatile uint8_t TMSTS57; /* TMSTS57 */ + volatile uint8_t TMSTS58; /* TMSTS58 */ + volatile uint8_t TMSTS59; /* TMSTS59 */ + volatile uint8_t TMSTS60; /* TMSTS60 */ + volatile uint8_t TMSTS61; /* TMSTS61 */ + volatile uint8_t TMSTS62; /* TMSTS62 */ + volatile uint8_t TMSTS63; /* TMSTS63 */ + volatile uint8_t TMSTS64; /* TMSTS64 */ + volatile uint8_t TMSTS65; /* TMSTS65 */ + volatile uint8_t TMSTS66; /* TMSTS66 */ + volatile uint8_t TMSTS67; /* TMSTS67 */ + volatile uint8_t TMSTS68; /* TMSTS68 */ + volatile uint8_t TMSTS69; /* TMSTS69 */ + volatile uint8_t TMSTS70; /* TMSTS70 */ + volatile uint8_t TMSTS71; /* TMSTS71 */ + volatile uint8_t TMSTS72; /* TMSTS72 */ + volatile uint8_t TMSTS73; /* TMSTS73 */ + volatile uint8_t TMSTS74; /* TMSTS74 */ + volatile uint8_t TMSTS75; /* TMSTS75 */ + volatile uint8_t TMSTS76; /* TMSTS76 */ + volatile uint8_t TMSTS77; /* TMSTS77 */ + volatile uint8_t TMSTS78; /* TMSTS78 */ + volatile uint8_t TMSTS79; /* TMSTS79 */ + volatile uint8_t dummy165[48]; /* */ + +/* #define RSCAN0_TMTRSTS0_COUNT (3) */ + union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ + union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ + union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ + + volatile uint8_t dummy166[4]; /* */ + +/* #define RSCAN0_TMTARSTS0_COUNT (3) */ + union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ + union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ + union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ + + volatile uint8_t dummy167[4]; /* */ + +/* #define RSCAN0_TMTCSTS0_COUNT (3) */ + union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ + union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ + union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ + + volatile uint8_t dummy168[4]; /* */ + +/* #define RSCAN0_TMTASTS0_COUNT (3) */ + union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ + union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ + union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ + + volatile uint8_t dummy169[4]; /* */ + +/* #define RSCAN0_TMIEC0_COUNT (3) */ + union iodefine_reg32_t TMIEC0; /* TMIEC0 */ + union iodefine_reg32_t TMIEC1; /* TMIEC1 */ + union iodefine_reg32_t TMIEC2; /* TMIEC2 */ + + volatile uint8_t dummy170[4]; /* */ + +/* #define RSCAN0_TXQCC0_COUNT (5) */ + union iodefine_reg32_t TXQCC0; /* TXQCC0 */ + union iodefine_reg32_t TXQCC1; /* TXQCC1 */ + union iodefine_reg32_t TXQCC2; /* TXQCC2 */ + union iodefine_reg32_t TXQCC3; /* TXQCC3 */ + union iodefine_reg32_t TXQCC4; /* TXQCC4 */ + + volatile uint8_t dummy171[12]; /* */ + +/* #define RSCAN0_TXQSTS0_COUNT (5) */ + union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ + union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ + union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ + union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ + union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ + + volatile uint8_t dummy172[12]; /* */ + +/* #define RSCAN0_TXQPCTR0_COUNT (5) */ + union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ + union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ + union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ + union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ + union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ + + volatile uint8_t dummy173[12]; /* */ + +/* #define RSCAN0_THLCC0_COUNT (5) */ + union iodefine_reg32_t THLCC0; /* THLCC0 */ + union iodefine_reg32_t THLCC1; /* THLCC1 */ + union iodefine_reg32_t THLCC2; /* THLCC2 */ + union iodefine_reg32_t THLCC3; /* THLCC3 */ + union iodefine_reg32_t THLCC4; /* THLCC4 */ + + volatile uint8_t dummy174[12]; /* */ + +/* #define RSCAN0_THLSTS0_COUNT (5) */ + union iodefine_reg32_t THLSTS0; /* THLSTS0 */ + union iodefine_reg32_t THLSTS1; /* THLSTS1 */ + union iodefine_reg32_t THLSTS2; /* THLSTS2 */ + union iodefine_reg32_t THLSTS3; /* THLSTS3 */ + union iodefine_reg32_t THLSTS4; /* THLSTS4 */ + + volatile uint8_t dummy175[12]; /* */ + +/* #define RSCAN0_THLPCTR0_COUNT (5) */ + union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ + union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ + union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ + union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ + union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ + + volatile uint8_t dummy176[12]; /* */ + +/* #define RSCAN0_GTINTSTS0_COUNT (2) */ + union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ + union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ + union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ + union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ + + volatile uint8_t dummy177[12]; /* */ + union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ + + volatile uint8_t dummy178[128]; /* */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID0; /* GAFLID0 */ + union iodefine_reg32_t GAFLM0; /* GAFLM0 */ + union iodefine_reg32_t GAFLP00; /* GAFLP00 */ + union iodefine_reg32_t GAFLP10; /* GAFLP10 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID1; /* GAFLID1 */ + union iodefine_reg32_t GAFLM1; /* GAFLM1 */ + union iodefine_reg32_t GAFLP01; /* GAFLP01 */ + union iodefine_reg32_t GAFLP11; /* GAFLP11 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID2; /* GAFLID2 */ + union iodefine_reg32_t GAFLM2; /* GAFLM2 */ + union iodefine_reg32_t GAFLP02; /* GAFLP02 */ + union iodefine_reg32_t GAFLP12; /* GAFLP12 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID3; /* GAFLID3 */ + union iodefine_reg32_t GAFLM3; /* GAFLM3 */ + union iodefine_reg32_t GAFLP03; /* GAFLP03 */ + union iodefine_reg32_t GAFLP13; /* GAFLP13 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID4; /* GAFLID4 */ + union iodefine_reg32_t GAFLM4; /* GAFLM4 */ + union iodefine_reg32_t GAFLP04; /* GAFLP04 */ + union iodefine_reg32_t GAFLP14; /* GAFLP14 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID5; /* GAFLID5 */ + union iodefine_reg32_t GAFLM5; /* GAFLM5 */ + union iodefine_reg32_t GAFLP05; /* GAFLP05 */ + union iodefine_reg32_t GAFLP15; /* GAFLP15 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID6; /* GAFLID6 */ + union iodefine_reg32_t GAFLM6; /* GAFLM6 */ + union iodefine_reg32_t GAFLP06; /* GAFLP06 */ + union iodefine_reg32_t GAFLP16; /* GAFLP16 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID7; /* GAFLID7 */ + union iodefine_reg32_t GAFLM7; /* GAFLM7 */ + union iodefine_reg32_t GAFLP07; /* GAFLP07 */ + union iodefine_reg32_t GAFLP17; /* GAFLP17 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID8; /* GAFLID8 */ + union iodefine_reg32_t GAFLM8; /* GAFLM8 */ + union iodefine_reg32_t GAFLP08; /* GAFLP08 */ + union iodefine_reg32_t GAFLP18; /* GAFLP18 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID9; /* GAFLID9 */ + union iodefine_reg32_t GAFLM9; /* GAFLM9 */ + union iodefine_reg32_t GAFLP09; /* GAFLP09 */ + union iodefine_reg32_t GAFLP19; /* GAFLP19 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID10; /* GAFLID10 */ + union iodefine_reg32_t GAFLM10; /* GAFLM10 */ + union iodefine_reg32_t GAFLP010; /* GAFLP010 */ + union iodefine_reg32_t GAFLP110; /* GAFLP110 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID11; /* GAFLID11 */ + union iodefine_reg32_t GAFLM11; /* GAFLM11 */ + union iodefine_reg32_t GAFLP011; /* GAFLP011 */ + union iodefine_reg32_t GAFLP111; /* GAFLP111 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID12; /* GAFLID12 */ + union iodefine_reg32_t GAFLM12; /* GAFLM12 */ + union iodefine_reg32_t GAFLP012; /* GAFLP012 */ + union iodefine_reg32_t GAFLP112; /* GAFLP112 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID13; /* GAFLID13 */ + union iodefine_reg32_t GAFLM13; /* GAFLM13 */ + union iodefine_reg32_t GAFLP013; /* GAFLP013 */ + union iodefine_reg32_t GAFLP113; /* GAFLP113 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID14; /* GAFLID14 */ + union iodefine_reg32_t GAFLM14; /* GAFLM14 */ + union iodefine_reg32_t GAFLP014; /* GAFLP014 */ + union iodefine_reg32_t GAFLP114; /* GAFLP114 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID15; /* GAFLID15 */ + union iodefine_reg32_t GAFLM15; /* GAFLM15 */ + union iodefine_reg32_t GAFLP015; /* GAFLP015 */ + union iodefine_reg32_t GAFLP115; /* GAFLP115 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID0; /* RMID0 */ + union iodefine_reg32_t RMPTR0; /* RMPTR0 */ + union iodefine_reg32_t RMDF00; /* RMDF00 */ + union iodefine_reg32_t RMDF10; /* RMDF10 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID1; /* RMID1 */ + union iodefine_reg32_t RMPTR1; /* RMPTR1 */ + union iodefine_reg32_t RMDF01; /* RMDF01 */ + union iodefine_reg32_t RMDF11; /* RMDF11 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID2; /* RMID2 */ + union iodefine_reg32_t RMPTR2; /* RMPTR2 */ + union iodefine_reg32_t RMDF02; /* RMDF02 */ + union iodefine_reg32_t RMDF12; /* RMDF12 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID3; /* RMID3 */ + union iodefine_reg32_t RMPTR3; /* RMPTR3 */ + union iodefine_reg32_t RMDF03; /* RMDF03 */ + union iodefine_reg32_t RMDF13; /* RMDF13 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID4; /* RMID4 */ + union iodefine_reg32_t RMPTR4; /* RMPTR4 */ + union iodefine_reg32_t RMDF04; /* RMDF04 */ + union iodefine_reg32_t RMDF14; /* RMDF14 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID5; /* RMID5 */ + union iodefine_reg32_t RMPTR5; /* RMPTR5 */ + union iodefine_reg32_t RMDF05; /* RMDF05 */ + union iodefine_reg32_t RMDF15; /* RMDF15 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID6; /* RMID6 */ + union iodefine_reg32_t RMPTR6; /* RMPTR6 */ + union iodefine_reg32_t RMDF06; /* RMDF06 */ + union iodefine_reg32_t RMDF16; /* RMDF16 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID7; /* RMID7 */ + union iodefine_reg32_t RMPTR7; /* RMPTR7 */ + union iodefine_reg32_t RMDF07; /* RMDF07 */ + union iodefine_reg32_t RMDF17; /* RMDF17 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID8; /* RMID8 */ + union iodefine_reg32_t RMPTR8; /* RMPTR8 */ + union iodefine_reg32_t RMDF08; /* RMDF08 */ + union iodefine_reg32_t RMDF18; /* RMDF18 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID9; /* RMID9 */ + union iodefine_reg32_t RMPTR9; /* RMPTR9 */ + union iodefine_reg32_t RMDF09; /* RMDF09 */ + union iodefine_reg32_t RMDF19; /* RMDF19 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID10; /* RMID10 */ + union iodefine_reg32_t RMPTR10; /* RMPTR10 */ + union iodefine_reg32_t RMDF010; /* RMDF010 */ + union iodefine_reg32_t RMDF110; /* RMDF110 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID11; /* RMID11 */ + union iodefine_reg32_t RMPTR11; /* RMPTR11 */ + union iodefine_reg32_t RMDF011; /* RMDF011 */ + union iodefine_reg32_t RMDF111; /* RMDF111 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID12; /* RMID12 */ + union iodefine_reg32_t RMPTR12; /* RMPTR12 */ + union iodefine_reg32_t RMDF012; /* RMDF012 */ + union iodefine_reg32_t RMDF112; /* RMDF112 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID13; /* RMID13 */ + union iodefine_reg32_t RMPTR13; /* RMPTR13 */ + union iodefine_reg32_t RMDF013; /* RMDF013 */ + union iodefine_reg32_t RMDF113; /* RMDF113 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID14; /* RMID14 */ + union iodefine_reg32_t RMPTR14; /* RMPTR14 */ + union iodefine_reg32_t RMDF014; /* RMDF014 */ + union iodefine_reg32_t RMDF114; /* RMDF114 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID15; /* RMID15 */ + union iodefine_reg32_t RMPTR15; /* RMPTR15 */ + union iodefine_reg32_t RMDF015; /* RMDF015 */ + union iodefine_reg32_t RMDF115; /* RMDF115 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID16; /* RMID16 */ + union iodefine_reg32_t RMPTR16; /* RMPTR16 */ + union iodefine_reg32_t RMDF016; /* RMDF016 */ + union iodefine_reg32_t RMDF116; /* RMDF116 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID17; /* RMID17 */ + union iodefine_reg32_t RMPTR17; /* RMPTR17 */ + union iodefine_reg32_t RMDF017; /* RMDF017 */ + union iodefine_reg32_t RMDF117; /* RMDF117 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID18; /* RMID18 */ + union iodefine_reg32_t RMPTR18; /* RMPTR18 */ + union iodefine_reg32_t RMDF018; /* RMDF018 */ + union iodefine_reg32_t RMDF118; /* RMDF118 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID19; /* RMID19 */ + union iodefine_reg32_t RMPTR19; /* RMPTR19 */ + union iodefine_reg32_t RMDF019; /* RMDF019 */ + union iodefine_reg32_t RMDF119; /* RMDF119 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID20; /* RMID20 */ + union iodefine_reg32_t RMPTR20; /* RMPTR20 */ + union iodefine_reg32_t RMDF020; /* RMDF020 */ + union iodefine_reg32_t RMDF120; /* RMDF120 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID21; /* RMID21 */ + union iodefine_reg32_t RMPTR21; /* RMPTR21 */ + union iodefine_reg32_t RMDF021; /* RMDF021 */ + union iodefine_reg32_t RMDF121; /* RMDF121 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID22; /* RMID22 */ + union iodefine_reg32_t RMPTR22; /* RMPTR22 */ + union iodefine_reg32_t RMDF022; /* RMDF022 */ + union iodefine_reg32_t RMDF122; /* RMDF122 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID23; /* RMID23 */ + union iodefine_reg32_t RMPTR23; /* RMPTR23 */ + union iodefine_reg32_t RMDF023; /* RMDF023 */ + union iodefine_reg32_t RMDF123; /* RMDF123 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID24; /* RMID24 */ + union iodefine_reg32_t RMPTR24; /* RMPTR24 */ + union iodefine_reg32_t RMDF024; /* RMDF024 */ + union iodefine_reg32_t RMDF124; /* RMDF124 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID25; /* RMID25 */ + union iodefine_reg32_t RMPTR25; /* RMPTR25 */ + union iodefine_reg32_t RMDF025; /* RMDF025 */ + union iodefine_reg32_t RMDF125; /* RMDF125 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID26; /* RMID26 */ + union iodefine_reg32_t RMPTR26; /* RMPTR26 */ + union iodefine_reg32_t RMDF026; /* RMDF026 */ + union iodefine_reg32_t RMDF126; /* RMDF126 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID27; /* RMID27 */ + union iodefine_reg32_t RMPTR27; /* RMPTR27 */ + union iodefine_reg32_t RMDF027; /* RMDF027 */ + union iodefine_reg32_t RMDF127; /* RMDF127 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID28; /* RMID28 */ + union iodefine_reg32_t RMPTR28; /* RMPTR28 */ + union iodefine_reg32_t RMDF028; /* RMDF028 */ + union iodefine_reg32_t RMDF128; /* RMDF128 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID29; /* RMID29 */ + union iodefine_reg32_t RMPTR29; /* RMPTR29 */ + union iodefine_reg32_t RMDF029; /* RMDF029 */ + union iodefine_reg32_t RMDF129; /* RMDF129 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID30; /* RMID30 */ + union iodefine_reg32_t RMPTR30; /* RMPTR30 */ + union iodefine_reg32_t RMDF030; /* RMDF030 */ + union iodefine_reg32_t RMDF130; /* RMDF130 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID31; /* RMID31 */ + union iodefine_reg32_t RMPTR31; /* RMPTR31 */ + union iodefine_reg32_t RMDF031; /* RMDF031 */ + union iodefine_reg32_t RMDF131; /* RMDF131 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID32; /* RMID32 */ + union iodefine_reg32_t RMPTR32; /* RMPTR32 */ + union iodefine_reg32_t RMDF032; /* RMDF032 */ + union iodefine_reg32_t RMDF132; /* RMDF132 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID33; /* RMID33 */ + union iodefine_reg32_t RMPTR33; /* RMPTR33 */ + union iodefine_reg32_t RMDF033; /* RMDF033 */ + union iodefine_reg32_t RMDF133; /* RMDF133 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID34; /* RMID34 */ + union iodefine_reg32_t RMPTR34; /* RMPTR34 */ + union iodefine_reg32_t RMDF034; /* RMDF034 */ + union iodefine_reg32_t RMDF134; /* RMDF134 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID35; /* RMID35 */ + union iodefine_reg32_t RMPTR35; /* RMPTR35 */ + union iodefine_reg32_t RMDF035; /* RMDF035 */ + union iodefine_reg32_t RMDF135; /* RMDF135 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID36; /* RMID36 */ + union iodefine_reg32_t RMPTR36; /* RMPTR36 */ + union iodefine_reg32_t RMDF036; /* RMDF036 */ + union iodefine_reg32_t RMDF136; /* RMDF136 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID37; /* RMID37 */ + union iodefine_reg32_t RMPTR37; /* RMPTR37 */ + union iodefine_reg32_t RMDF037; /* RMDF037 */ + union iodefine_reg32_t RMDF137; /* RMDF137 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID38; /* RMID38 */ + union iodefine_reg32_t RMPTR38; /* RMPTR38 */ + union iodefine_reg32_t RMDF038; /* RMDF038 */ + union iodefine_reg32_t RMDF138; /* RMDF138 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID39; /* RMID39 */ + union iodefine_reg32_t RMPTR39; /* RMPTR39 */ + union iodefine_reg32_t RMDF039; /* RMDF039 */ + union iodefine_reg32_t RMDF139; /* RMDF139 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID40; /* RMID40 */ + union iodefine_reg32_t RMPTR40; /* RMPTR40 */ + union iodefine_reg32_t RMDF040; /* RMDF040 */ + union iodefine_reg32_t RMDF140; /* RMDF140 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID41; /* RMID41 */ + union iodefine_reg32_t RMPTR41; /* RMPTR41 */ + union iodefine_reg32_t RMDF041; /* RMDF041 */ + union iodefine_reg32_t RMDF141; /* RMDF141 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID42; /* RMID42 */ + union iodefine_reg32_t RMPTR42; /* RMPTR42 */ + union iodefine_reg32_t RMDF042; /* RMDF042 */ + union iodefine_reg32_t RMDF142; /* RMDF142 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID43; /* RMID43 */ + union iodefine_reg32_t RMPTR43; /* RMPTR43 */ + union iodefine_reg32_t RMDF043; /* RMDF043 */ + union iodefine_reg32_t RMDF143; /* RMDF143 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID44; /* RMID44 */ + union iodefine_reg32_t RMPTR44; /* RMPTR44 */ + union iodefine_reg32_t RMDF044; /* RMDF044 */ + union iodefine_reg32_t RMDF144; /* RMDF144 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID45; /* RMID45 */ + union iodefine_reg32_t RMPTR45; /* RMPTR45 */ + union iodefine_reg32_t RMDF045; /* RMDF045 */ + union iodefine_reg32_t RMDF145; /* RMDF145 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID46; /* RMID46 */ + union iodefine_reg32_t RMPTR46; /* RMPTR46 */ + union iodefine_reg32_t RMDF046; /* RMDF046 */ + union iodefine_reg32_t RMDF146; /* RMDF146 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID47; /* RMID47 */ + union iodefine_reg32_t RMPTR47; /* RMPTR47 */ + union iodefine_reg32_t RMDF047; /* RMDF047 */ + union iodefine_reg32_t RMDF147; /* RMDF147 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID48; /* RMID48 */ + union iodefine_reg32_t RMPTR48; /* RMPTR48 */ + union iodefine_reg32_t RMDF048; /* RMDF048 */ + union iodefine_reg32_t RMDF148; /* RMDF148 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID49; /* RMID49 */ + union iodefine_reg32_t RMPTR49; /* RMPTR49 */ + union iodefine_reg32_t RMDF049; /* RMDF049 */ + union iodefine_reg32_t RMDF149; /* RMDF149 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID50; /* RMID50 */ + union iodefine_reg32_t RMPTR50; /* RMPTR50 */ + union iodefine_reg32_t RMDF050; /* RMDF050 */ + union iodefine_reg32_t RMDF150; /* RMDF150 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID51; /* RMID51 */ + union iodefine_reg32_t RMPTR51; /* RMPTR51 */ + union iodefine_reg32_t RMDF051; /* RMDF051 */ + union iodefine_reg32_t RMDF151; /* RMDF151 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID52; /* RMID52 */ + union iodefine_reg32_t RMPTR52; /* RMPTR52 */ + union iodefine_reg32_t RMDF052; /* RMDF052 */ + union iodefine_reg32_t RMDF152; /* RMDF152 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID53; /* RMID53 */ + union iodefine_reg32_t RMPTR53; /* RMPTR53 */ + union iodefine_reg32_t RMDF053; /* RMDF053 */ + union iodefine_reg32_t RMDF153; /* RMDF153 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID54; /* RMID54 */ + union iodefine_reg32_t RMPTR54; /* RMPTR54 */ + union iodefine_reg32_t RMDF054; /* RMDF054 */ + union iodefine_reg32_t RMDF154; /* RMDF154 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID55; /* RMID55 */ + union iodefine_reg32_t RMPTR55; /* RMPTR55 */ + union iodefine_reg32_t RMDF055; /* RMDF055 */ + union iodefine_reg32_t RMDF155; /* RMDF155 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID56; /* RMID56 */ + union iodefine_reg32_t RMPTR56; /* RMPTR56 */ + union iodefine_reg32_t RMDF056; /* RMDF056 */ + union iodefine_reg32_t RMDF156; /* RMDF156 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID57; /* RMID57 */ + union iodefine_reg32_t RMPTR57; /* RMPTR57 */ + union iodefine_reg32_t RMDF057; /* RMDF057 */ + union iodefine_reg32_t RMDF157; /* RMDF157 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID58; /* RMID58 */ + union iodefine_reg32_t RMPTR58; /* RMPTR58 */ + union iodefine_reg32_t RMDF058; /* RMDF058 */ + union iodefine_reg32_t RMDF158; /* RMDF158 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID59; /* RMID59 */ + union iodefine_reg32_t RMPTR59; /* RMPTR59 */ + union iodefine_reg32_t RMDF059; /* RMDF059 */ + union iodefine_reg32_t RMDF159; /* RMDF159 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID60; /* RMID60 */ + union iodefine_reg32_t RMPTR60; /* RMPTR60 */ + union iodefine_reg32_t RMDF060; /* RMDF060 */ + union iodefine_reg32_t RMDF160; /* RMDF160 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID61; /* RMID61 */ + union iodefine_reg32_t RMPTR61; /* RMPTR61 */ + union iodefine_reg32_t RMDF061; /* RMDF061 */ + union iodefine_reg32_t RMDF161; /* RMDF161 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID62; /* RMID62 */ + union iodefine_reg32_t RMPTR62; /* RMPTR62 */ + union iodefine_reg32_t RMDF062; /* RMDF062 */ + union iodefine_reg32_t RMDF162; /* RMDF162 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID63; /* RMID63 */ + union iodefine_reg32_t RMPTR63; /* RMPTR63 */ + union iodefine_reg32_t RMDF063; /* RMDF063 */ + union iodefine_reg32_t RMDF163; /* RMDF163 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID64; /* RMID64 */ + union iodefine_reg32_t RMPTR64; /* RMPTR64 */ + union iodefine_reg32_t RMDF064; /* RMDF064 */ + union iodefine_reg32_t RMDF164; /* RMDF164 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID65; /* RMID65 */ + union iodefine_reg32_t RMPTR65; /* RMPTR65 */ + union iodefine_reg32_t RMDF065; /* RMDF065 */ + union iodefine_reg32_t RMDF165; /* RMDF165 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID66; /* RMID66 */ + union iodefine_reg32_t RMPTR66; /* RMPTR66 */ + union iodefine_reg32_t RMDF066; /* RMDF066 */ + union iodefine_reg32_t RMDF166; /* RMDF166 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID67; /* RMID67 */ + union iodefine_reg32_t RMPTR67; /* RMPTR67 */ + union iodefine_reg32_t RMDF067; /* RMDF067 */ + union iodefine_reg32_t RMDF167; /* RMDF167 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID68; /* RMID68 */ + union iodefine_reg32_t RMPTR68; /* RMPTR68 */ + union iodefine_reg32_t RMDF068; /* RMDF068 */ + union iodefine_reg32_t RMDF168; /* RMDF168 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID69; /* RMID69 */ + union iodefine_reg32_t RMPTR69; /* RMPTR69 */ + union iodefine_reg32_t RMDF069; /* RMDF069 */ + union iodefine_reg32_t RMDF169; /* RMDF169 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID70; /* RMID70 */ + union iodefine_reg32_t RMPTR70; /* RMPTR70 */ + union iodefine_reg32_t RMDF070; /* RMDF070 */ + union iodefine_reg32_t RMDF170; /* RMDF170 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID71; /* RMID71 */ + union iodefine_reg32_t RMPTR71; /* RMPTR71 */ + union iodefine_reg32_t RMDF071; /* RMDF071 */ + union iodefine_reg32_t RMDF171; /* RMDF171 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID72; /* RMID72 */ + union iodefine_reg32_t RMPTR72; /* RMPTR72 */ + union iodefine_reg32_t RMDF072; /* RMDF072 */ + union iodefine_reg32_t RMDF172; /* RMDF172 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID73; /* RMID73 */ + union iodefine_reg32_t RMPTR73; /* RMPTR73 */ + union iodefine_reg32_t RMDF073; /* RMDF073 */ + union iodefine_reg32_t RMDF173; /* RMDF173 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID74; /* RMID74 */ + union iodefine_reg32_t RMPTR74; /* RMPTR74 */ + union iodefine_reg32_t RMDF074; /* RMDF074 */ + union iodefine_reg32_t RMDF174; /* RMDF174 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID75; /* RMID75 */ + union iodefine_reg32_t RMPTR75; /* RMPTR75 */ + union iodefine_reg32_t RMDF075; /* RMDF075 */ + union iodefine_reg32_t RMDF175; /* RMDF175 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID76; /* RMID76 */ + union iodefine_reg32_t RMPTR76; /* RMPTR76 */ + union iodefine_reg32_t RMDF076; /* RMDF076 */ + union iodefine_reg32_t RMDF176; /* RMDF176 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID77; /* RMID77 */ + union iodefine_reg32_t RMPTR77; /* RMPTR77 */ + union iodefine_reg32_t RMDF077; /* RMDF077 */ + union iodefine_reg32_t RMDF177; /* RMDF177 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID78; /* RMID78 */ + union iodefine_reg32_t RMPTR78; /* RMPTR78 */ + union iodefine_reg32_t RMDF078; /* RMDF078 */ + union iodefine_reg32_t RMDF178; /* RMDF178 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID79; /* RMID79 */ + union iodefine_reg32_t RMPTR79; /* RMPTR79 */ + union iodefine_reg32_t RMDF079; /* RMDF079 */ + union iodefine_reg32_t RMDF179; /* RMDF179 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + + volatile uint8_t dummy179[768]; /* */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID0; /* RFID0 */ + union iodefine_reg32_t RFPTR0; /* RFPTR0 */ + union iodefine_reg32_t RFDF00; /* RFDF00 */ + union iodefine_reg32_t RFDF10; /* RFDF10 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID1; /* RFID1 */ + union iodefine_reg32_t RFPTR1; /* RFPTR1 */ + union iodefine_reg32_t RFDF01; /* RFDF01 */ + union iodefine_reg32_t RFDF11; /* RFDF11 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID2; /* RFID2 */ + union iodefine_reg32_t RFPTR2; /* RFPTR2 */ + union iodefine_reg32_t RFDF02; /* RFDF02 */ + union iodefine_reg32_t RFDF12; /* RFDF12 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID3; /* RFID3 */ + union iodefine_reg32_t RFPTR3; /* RFPTR3 */ + union iodefine_reg32_t RFDF03; /* RFDF03 */ + union iodefine_reg32_t RFDF13; /* RFDF13 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID4; /* RFID4 */ + union iodefine_reg32_t RFPTR4; /* RFPTR4 */ + union iodefine_reg32_t RFDF04; /* RFDF04 */ + union iodefine_reg32_t RFDF14; /* RFDF14 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID5; /* RFID5 */ + union iodefine_reg32_t RFPTR5; /* RFPTR5 */ + union iodefine_reg32_t RFDF05; /* RFDF05 */ + union iodefine_reg32_t RFDF15; /* RFDF15 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID6; /* RFID6 */ + union iodefine_reg32_t RFPTR6; /* RFPTR6 */ + union iodefine_reg32_t RFDF06; /* RFDF06 */ + union iodefine_reg32_t RFDF16; /* RFDF16 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID7; /* RFID7 */ + union iodefine_reg32_t RFPTR7; /* RFPTR7 */ + union iodefine_reg32_t RFDF07; /* RFDF07 */ + union iodefine_reg32_t RFDF17; /* RFDF17 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID0; /* CFID0 */ + union iodefine_reg32_t CFPTR0; /* CFPTR0 */ + union iodefine_reg32_t CFDF00; /* CFDF00 */ + union iodefine_reg32_t CFDF10; /* CFDF10 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID1; /* CFID1 */ + union iodefine_reg32_t CFPTR1; /* CFPTR1 */ + union iodefine_reg32_t CFDF01; /* CFDF01 */ + union iodefine_reg32_t CFDF11; /* CFDF11 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID2; /* CFID2 */ + union iodefine_reg32_t CFPTR2; /* CFPTR2 */ + union iodefine_reg32_t CFDF02; /* CFDF02 */ + union iodefine_reg32_t CFDF12; /* CFDF12 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID3; /* CFID3 */ + union iodefine_reg32_t CFPTR3; /* CFPTR3 */ + union iodefine_reg32_t CFDF03; /* CFDF03 */ + union iodefine_reg32_t CFDF13; /* CFDF13 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID4; /* CFID4 */ + union iodefine_reg32_t CFPTR4; /* CFPTR4 */ + union iodefine_reg32_t CFDF04; /* CFDF04 */ + union iodefine_reg32_t CFDF14; /* CFDF14 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID5; /* CFID5 */ + union iodefine_reg32_t CFPTR5; /* CFPTR5 */ + union iodefine_reg32_t CFDF05; /* CFDF05 */ + union iodefine_reg32_t CFDF15; /* CFDF15 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID6; /* CFID6 */ + union iodefine_reg32_t CFPTR6; /* CFPTR6 */ + union iodefine_reg32_t CFDF06; /* CFDF06 */ + union iodefine_reg32_t CFDF16; /* CFDF16 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID7; /* CFID7 */ + union iodefine_reg32_t CFPTR7; /* CFPTR7 */ + union iodefine_reg32_t CFDF07; /* CFDF07 */ + union iodefine_reg32_t CFDF17; /* CFDF17 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID8; /* CFID8 */ + union iodefine_reg32_t CFPTR8; /* CFPTR8 */ + union iodefine_reg32_t CFDF08; /* CFDF08 */ + union iodefine_reg32_t CFDF18; /* CFDF18 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID9; /* CFID9 */ + union iodefine_reg32_t CFPTR9; /* CFPTR9 */ + union iodefine_reg32_t CFDF09; /* CFDF09 */ + union iodefine_reg32_t CFDF19; /* CFDF19 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID10; /* CFID10 */ + union iodefine_reg32_t CFPTR10; /* CFPTR10 */ + union iodefine_reg32_t CFDF010; /* CFDF010 */ + union iodefine_reg32_t CFDF110; /* CFDF110 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID11; /* CFID11 */ + union iodefine_reg32_t CFPTR11; /* CFPTR11 */ + union iodefine_reg32_t CFDF011; /* CFDF011 */ + union iodefine_reg32_t CFDF111; /* CFDF111 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID12; /* CFID12 */ + union iodefine_reg32_t CFPTR12; /* CFPTR12 */ + union iodefine_reg32_t CFDF012; /* CFDF012 */ + union iodefine_reg32_t CFDF112; /* CFDF112 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID13; /* CFID13 */ + union iodefine_reg32_t CFPTR13; /* CFPTR13 */ + union iodefine_reg32_t CFDF013; /* CFDF013 */ + union iodefine_reg32_t CFDF113; /* CFDF113 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID14; /* CFID14 */ + union iodefine_reg32_t CFPTR14; /* CFPTR14 */ + union iodefine_reg32_t CFDF014; /* CFDF014 */ + union iodefine_reg32_t CFDF114; /* CFDF114 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + + volatile uint8_t dummy180[144]; /* */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID0; /* TMID0 */ + union iodefine_reg32_t TMPTR0; /* TMPTR0 */ + union iodefine_reg32_t TMDF00; /* TMDF00 */ + union iodefine_reg32_t TMDF10; /* TMDF10 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID1; /* TMID1 */ + union iodefine_reg32_t TMPTR1; /* TMPTR1 */ + union iodefine_reg32_t TMDF01; /* TMDF01 */ + union iodefine_reg32_t TMDF11; /* TMDF11 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID2; /* TMID2 */ + union iodefine_reg32_t TMPTR2; /* TMPTR2 */ + union iodefine_reg32_t TMDF02; /* TMDF02 */ + union iodefine_reg32_t TMDF12; /* TMDF12 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID3; /* TMID3 */ + union iodefine_reg32_t TMPTR3; /* TMPTR3 */ + union iodefine_reg32_t TMDF03; /* TMDF03 */ + union iodefine_reg32_t TMDF13; /* TMDF13 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID4; /* TMID4 */ + union iodefine_reg32_t TMPTR4; /* TMPTR4 */ + union iodefine_reg32_t TMDF04; /* TMDF04 */ + union iodefine_reg32_t TMDF14; /* TMDF14 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID5; /* TMID5 */ + union iodefine_reg32_t TMPTR5; /* TMPTR5 */ + union iodefine_reg32_t TMDF05; /* TMDF05 */ + union iodefine_reg32_t TMDF15; /* TMDF15 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID6; /* TMID6 */ + union iodefine_reg32_t TMPTR6; /* TMPTR6 */ + union iodefine_reg32_t TMDF06; /* TMDF06 */ + union iodefine_reg32_t TMDF16; /* TMDF16 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID7; /* TMID7 */ + union iodefine_reg32_t TMPTR7; /* TMPTR7 */ + union iodefine_reg32_t TMDF07; /* TMDF07 */ + union iodefine_reg32_t TMDF17; /* TMDF17 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID8; /* TMID8 */ + union iodefine_reg32_t TMPTR8; /* TMPTR8 */ + union iodefine_reg32_t TMDF08; /* TMDF08 */ + union iodefine_reg32_t TMDF18; /* TMDF18 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID9; /* TMID9 */ + union iodefine_reg32_t TMPTR9; /* TMPTR9 */ + union iodefine_reg32_t TMDF09; /* TMDF09 */ + union iodefine_reg32_t TMDF19; /* TMDF19 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID10; /* TMID10 */ + union iodefine_reg32_t TMPTR10; /* TMPTR10 */ + union iodefine_reg32_t TMDF010; /* TMDF010 */ + union iodefine_reg32_t TMDF110; /* TMDF110 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID11; /* TMID11 */ + union iodefine_reg32_t TMPTR11; /* TMPTR11 */ + union iodefine_reg32_t TMDF011; /* TMDF011 */ + union iodefine_reg32_t TMDF111; /* TMDF111 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID12; /* TMID12 */ + union iodefine_reg32_t TMPTR12; /* TMPTR12 */ + union iodefine_reg32_t TMDF012; /* TMDF012 */ + union iodefine_reg32_t TMDF112; /* TMDF112 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID13; /* TMID13 */ + union iodefine_reg32_t TMPTR13; /* TMPTR13 */ + union iodefine_reg32_t TMDF013; /* TMDF013 */ + union iodefine_reg32_t TMDF113; /* TMDF113 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID14; /* TMID14 */ + union iodefine_reg32_t TMPTR14; /* TMPTR14 */ + union iodefine_reg32_t TMDF014; /* TMDF014 */ + union iodefine_reg32_t TMDF114; /* TMDF114 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID15; /* TMID15 */ + union iodefine_reg32_t TMPTR15; /* TMPTR15 */ + union iodefine_reg32_t TMDF015; /* TMDF015 */ + union iodefine_reg32_t TMDF115; /* TMDF115 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID16; /* TMID16 */ + union iodefine_reg32_t TMPTR16; /* TMPTR16 */ + union iodefine_reg32_t TMDF016; /* TMDF016 */ + union iodefine_reg32_t TMDF116; /* TMDF116 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID17; /* TMID17 */ + union iodefine_reg32_t TMPTR17; /* TMPTR17 */ + union iodefine_reg32_t TMDF017; /* TMDF017 */ + union iodefine_reg32_t TMDF117; /* TMDF117 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID18; /* TMID18 */ + union iodefine_reg32_t TMPTR18; /* TMPTR18 */ + union iodefine_reg32_t TMDF018; /* TMDF018 */ + union iodefine_reg32_t TMDF118; /* TMDF118 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID19; /* TMID19 */ + union iodefine_reg32_t TMPTR19; /* TMPTR19 */ + union iodefine_reg32_t TMDF019; /* TMDF019 */ + union iodefine_reg32_t TMDF119; /* TMDF119 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID20; /* TMID20 */ + union iodefine_reg32_t TMPTR20; /* TMPTR20 */ + union iodefine_reg32_t TMDF020; /* TMDF020 */ + union iodefine_reg32_t TMDF120; /* TMDF120 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID21; /* TMID21 */ + union iodefine_reg32_t TMPTR21; /* TMPTR21 */ + union iodefine_reg32_t TMDF021; /* TMDF021 */ + union iodefine_reg32_t TMDF121; /* TMDF121 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID22; /* TMID22 */ + union iodefine_reg32_t TMPTR22; /* TMPTR22 */ + union iodefine_reg32_t TMDF022; /* TMDF022 */ + union iodefine_reg32_t TMDF122; /* TMDF122 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID23; /* TMID23 */ + union iodefine_reg32_t TMPTR23; /* TMPTR23 */ + union iodefine_reg32_t TMDF023; /* TMDF023 */ + union iodefine_reg32_t TMDF123; /* TMDF123 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID24; /* TMID24 */ + union iodefine_reg32_t TMPTR24; /* TMPTR24 */ + union iodefine_reg32_t TMDF024; /* TMDF024 */ + union iodefine_reg32_t TMDF124; /* TMDF124 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID25; /* TMID25 */ + union iodefine_reg32_t TMPTR25; /* TMPTR25 */ + union iodefine_reg32_t TMDF025; /* TMDF025 */ + union iodefine_reg32_t TMDF125; /* TMDF125 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID26; /* TMID26 */ + union iodefine_reg32_t TMPTR26; /* TMPTR26 */ + union iodefine_reg32_t TMDF026; /* TMDF026 */ + union iodefine_reg32_t TMDF126; /* TMDF126 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID27; /* TMID27 */ + union iodefine_reg32_t TMPTR27; /* TMPTR27 */ + union iodefine_reg32_t TMDF027; /* TMDF027 */ + union iodefine_reg32_t TMDF127; /* TMDF127 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID28; /* TMID28 */ + union iodefine_reg32_t TMPTR28; /* TMPTR28 */ + union iodefine_reg32_t TMDF028; /* TMDF028 */ + union iodefine_reg32_t TMDF128; /* TMDF128 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID29; /* TMID29 */ + union iodefine_reg32_t TMPTR29; /* TMPTR29 */ + union iodefine_reg32_t TMDF029; /* TMDF029 */ + union iodefine_reg32_t TMDF129; /* TMDF129 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID30; /* TMID30 */ + union iodefine_reg32_t TMPTR30; /* TMPTR30 */ + union iodefine_reg32_t TMDF030; /* TMDF030 */ + union iodefine_reg32_t TMDF130; /* TMDF130 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID31; /* TMID31 */ + union iodefine_reg32_t TMPTR31; /* TMPTR31 */ + union iodefine_reg32_t TMDF031; /* TMDF031 */ + union iodefine_reg32_t TMDF131; /* TMDF131 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID32; /* TMID32 */ + union iodefine_reg32_t TMPTR32; /* TMPTR32 */ + union iodefine_reg32_t TMDF032; /* TMDF032 */ + union iodefine_reg32_t TMDF132; /* TMDF132 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID33; /* TMID33 */ + union iodefine_reg32_t TMPTR33; /* TMPTR33 */ + union iodefine_reg32_t TMDF033; /* TMDF033 */ + union iodefine_reg32_t TMDF133; /* TMDF133 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID34; /* TMID34 */ + union iodefine_reg32_t TMPTR34; /* TMPTR34 */ + union iodefine_reg32_t TMDF034; /* TMDF034 */ + union iodefine_reg32_t TMDF134; /* TMDF134 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID35; /* TMID35 */ + union iodefine_reg32_t TMPTR35; /* TMPTR35 */ + union iodefine_reg32_t TMDF035; /* TMDF035 */ + union iodefine_reg32_t TMDF135; /* TMDF135 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID36; /* TMID36 */ + union iodefine_reg32_t TMPTR36; /* TMPTR36 */ + union iodefine_reg32_t TMDF036; /* TMDF036 */ + union iodefine_reg32_t TMDF136; /* TMDF136 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID37; /* TMID37 */ + union iodefine_reg32_t TMPTR37; /* TMPTR37 */ + union iodefine_reg32_t TMDF037; /* TMDF037 */ + union iodefine_reg32_t TMDF137; /* TMDF137 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID38; /* TMID38 */ + union iodefine_reg32_t TMPTR38; /* TMPTR38 */ + union iodefine_reg32_t TMDF038; /* TMDF038 */ + union iodefine_reg32_t TMDF138; /* TMDF138 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID39; /* TMID39 */ + union iodefine_reg32_t TMPTR39; /* TMPTR39 */ + union iodefine_reg32_t TMDF039; /* TMDF039 */ + union iodefine_reg32_t TMDF139; /* TMDF139 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID40; /* TMID40 */ + union iodefine_reg32_t TMPTR40; /* TMPTR40 */ + union iodefine_reg32_t TMDF040; /* TMDF040 */ + union iodefine_reg32_t TMDF140; /* TMDF140 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID41; /* TMID41 */ + union iodefine_reg32_t TMPTR41; /* TMPTR41 */ + union iodefine_reg32_t TMDF041; /* TMDF041 */ + union iodefine_reg32_t TMDF141; /* TMDF141 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID42; /* TMID42 */ + union iodefine_reg32_t TMPTR42; /* TMPTR42 */ + union iodefine_reg32_t TMDF042; /* TMDF042 */ + union iodefine_reg32_t TMDF142; /* TMDF142 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID43; /* TMID43 */ + union iodefine_reg32_t TMPTR43; /* TMPTR43 */ + union iodefine_reg32_t TMDF043; /* TMDF043 */ + union iodefine_reg32_t TMDF143; /* TMDF143 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID44; /* TMID44 */ + union iodefine_reg32_t TMPTR44; /* TMPTR44 */ + union iodefine_reg32_t TMDF044; /* TMDF044 */ + union iodefine_reg32_t TMDF144; /* TMDF144 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID45; /* TMID45 */ + union iodefine_reg32_t TMPTR45; /* TMPTR45 */ + union iodefine_reg32_t TMDF045; /* TMDF045 */ + union iodefine_reg32_t TMDF145; /* TMDF145 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID46; /* TMID46 */ + union iodefine_reg32_t TMPTR46; /* TMPTR46 */ + union iodefine_reg32_t TMDF046; /* TMDF046 */ + union iodefine_reg32_t TMDF146; /* TMDF146 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID47; /* TMID47 */ + union iodefine_reg32_t TMPTR47; /* TMPTR47 */ + union iodefine_reg32_t TMDF047; /* TMDF047 */ + union iodefine_reg32_t TMDF147; /* TMDF147 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID48; /* TMID48 */ + union iodefine_reg32_t TMPTR48; /* TMPTR48 */ + union iodefine_reg32_t TMDF048; /* TMDF048 */ + union iodefine_reg32_t TMDF148; /* TMDF148 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID49; /* TMID49 */ + union iodefine_reg32_t TMPTR49; /* TMPTR49 */ + union iodefine_reg32_t TMDF049; /* TMDF049 */ + union iodefine_reg32_t TMDF149; /* TMDF149 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID50; /* TMID50 */ + union iodefine_reg32_t TMPTR50; /* TMPTR50 */ + union iodefine_reg32_t TMDF050; /* TMDF050 */ + union iodefine_reg32_t TMDF150; /* TMDF150 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID51; /* TMID51 */ + union iodefine_reg32_t TMPTR51; /* TMPTR51 */ + union iodefine_reg32_t TMDF051; /* TMDF051 */ + union iodefine_reg32_t TMDF151; /* TMDF151 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID52; /* TMID52 */ + union iodefine_reg32_t TMPTR52; /* TMPTR52 */ + union iodefine_reg32_t TMDF052; /* TMDF052 */ + union iodefine_reg32_t TMDF152; /* TMDF152 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID53; /* TMID53 */ + union iodefine_reg32_t TMPTR53; /* TMPTR53 */ + union iodefine_reg32_t TMDF053; /* TMDF053 */ + union iodefine_reg32_t TMDF153; /* TMDF153 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID54; /* TMID54 */ + union iodefine_reg32_t TMPTR54; /* TMPTR54 */ + union iodefine_reg32_t TMDF054; /* TMDF054 */ + union iodefine_reg32_t TMDF154; /* TMDF154 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID55; /* TMID55 */ + union iodefine_reg32_t TMPTR55; /* TMPTR55 */ + union iodefine_reg32_t TMDF055; /* TMDF055 */ + union iodefine_reg32_t TMDF155; /* TMDF155 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID56; /* TMID56 */ + union iodefine_reg32_t TMPTR56; /* TMPTR56 */ + union iodefine_reg32_t TMDF056; /* TMDF056 */ + union iodefine_reg32_t TMDF156; /* TMDF156 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID57; /* TMID57 */ + union iodefine_reg32_t TMPTR57; /* TMPTR57 */ + union iodefine_reg32_t TMDF057; /* TMDF057 */ + union iodefine_reg32_t TMDF157; /* TMDF157 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID58; /* TMID58 */ + union iodefine_reg32_t TMPTR58; /* TMPTR58 */ + union iodefine_reg32_t TMDF058; /* TMDF058 */ + union iodefine_reg32_t TMDF158; /* TMDF158 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID59; /* TMID59 */ + union iodefine_reg32_t TMPTR59; /* TMPTR59 */ + union iodefine_reg32_t TMDF059; /* TMDF059 */ + union iodefine_reg32_t TMDF159; /* TMDF159 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID60; /* TMID60 */ + union iodefine_reg32_t TMPTR60; /* TMPTR60 */ + union iodefine_reg32_t TMDF060; /* TMDF060 */ + union iodefine_reg32_t TMDF160; /* TMDF160 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID61; /* TMID61 */ + union iodefine_reg32_t TMPTR61; /* TMPTR61 */ + union iodefine_reg32_t TMDF061; /* TMDF061 */ + union iodefine_reg32_t TMDF161; /* TMDF161 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID62; /* TMID62 */ + union iodefine_reg32_t TMPTR62; /* TMPTR62 */ + union iodefine_reg32_t TMDF062; /* TMDF062 */ + union iodefine_reg32_t TMDF162; /* TMDF162 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID63; /* TMID63 */ + union iodefine_reg32_t TMPTR63; /* TMPTR63 */ + union iodefine_reg32_t TMDF063; /* TMDF063 */ + union iodefine_reg32_t TMDF163; /* TMDF163 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID64; /* TMID64 */ + union iodefine_reg32_t TMPTR64; /* TMPTR64 */ + union iodefine_reg32_t TMDF064; /* TMDF064 */ + union iodefine_reg32_t TMDF164; /* TMDF164 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID65; /* TMID65 */ + union iodefine_reg32_t TMPTR65; /* TMPTR65 */ + union iodefine_reg32_t TMDF065; /* TMDF065 */ + union iodefine_reg32_t TMDF165; /* TMDF165 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID66; /* TMID66 */ + union iodefine_reg32_t TMPTR66; /* TMPTR66 */ + union iodefine_reg32_t TMDF066; /* TMDF066 */ + union iodefine_reg32_t TMDF166; /* TMDF166 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID67; /* TMID67 */ + union iodefine_reg32_t TMPTR67; /* TMPTR67 */ + union iodefine_reg32_t TMDF067; /* TMDF067 */ + union iodefine_reg32_t TMDF167; /* TMDF167 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID68; /* TMID68 */ + union iodefine_reg32_t TMPTR68; /* TMPTR68 */ + union iodefine_reg32_t TMDF068; /* TMDF068 */ + union iodefine_reg32_t TMDF168; /* TMDF168 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID69; /* TMID69 */ + union iodefine_reg32_t TMPTR69; /* TMPTR69 */ + union iodefine_reg32_t TMDF069; /* TMDF069 */ + union iodefine_reg32_t TMDF169; /* TMDF169 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID70; /* TMID70 */ + union iodefine_reg32_t TMPTR70; /* TMPTR70 */ + union iodefine_reg32_t TMDF070; /* TMDF070 */ + union iodefine_reg32_t TMDF170; /* TMDF170 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID71; /* TMID71 */ + union iodefine_reg32_t TMPTR71; /* TMPTR71 */ + union iodefine_reg32_t TMDF071; /* TMDF071 */ + union iodefine_reg32_t TMDF171; /* TMDF171 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID72; /* TMID72 */ + union iodefine_reg32_t TMPTR72; /* TMPTR72 */ + union iodefine_reg32_t TMDF072; /* TMDF072 */ + union iodefine_reg32_t TMDF172; /* TMDF172 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID73; /* TMID73 */ + union iodefine_reg32_t TMPTR73; /* TMPTR73 */ + union iodefine_reg32_t TMDF073; /* TMDF073 */ + union iodefine_reg32_t TMDF173; /* TMDF173 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID74; /* TMID74 */ + union iodefine_reg32_t TMPTR74; /* TMPTR74 */ + union iodefine_reg32_t TMDF074; /* TMDF074 */ + union iodefine_reg32_t TMDF174; /* TMDF174 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID75; /* TMID75 */ + union iodefine_reg32_t TMPTR75; /* TMPTR75 */ + union iodefine_reg32_t TMDF075; /* TMDF075 */ + union iodefine_reg32_t TMDF175; /* TMDF175 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID76; /* TMID76 */ + union iodefine_reg32_t TMPTR76; /* TMPTR76 */ + union iodefine_reg32_t TMDF076; /* TMDF076 */ + union iodefine_reg32_t TMDF176; /* TMDF176 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID77; /* TMID77 */ + union iodefine_reg32_t TMPTR77; /* TMPTR77 */ + union iodefine_reg32_t TMDF077; /* TMDF077 */ + union iodefine_reg32_t TMDF177; /* TMDF177 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID78; /* TMID78 */ + union iodefine_reg32_t TMPTR78; /* TMPTR78 */ + union iodefine_reg32_t TMDF078; /* TMDF078 */ + union iodefine_reg32_t TMDF178; /* TMDF178 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID79; /* TMID79 */ + union iodefine_reg32_t TMPTR79; /* TMPTR79 */ + union iodefine_reg32_t TMDF079; /* TMDF079 */ + union iodefine_reg32_t TMDF179; /* TMDF179 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + + volatile uint8_t dummy181[768]; /* */ + +/* #define RSCAN0_THLACC0_COUNT (5) */ + union iodefine_reg32_t THLACC0; /* THLACC0 */ + union iodefine_reg32_t THLACC1; /* THLACC1 */ + union iodefine_reg32_t THLACC2; /* THLACC2 */ + union iodefine_reg32_t THLACC3; /* THLACC3 */ + union iodefine_reg32_t THLACC4; /* THLACC4 */ + +} r_io_rscan0_t; + + +typedef struct st_rscan_from_rscan0cncfg +{ + + union iodefine_reg32_t CnCFG; /* CnCFG */ + union iodefine_reg32_t CnCTR; /* CnCTR */ + union iodefine_reg32_t CnSTS; /* CnSTS */ + union iodefine_reg32_t CnERFL; /* CnERFL */ +} r_io_rscan_from_rscan0cncfg_t; + + +typedef struct st_rscan_from_rscan0gaflidj +{ + + union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ + union iodefine_reg32_t GAFLMj; /* GAFLMj */ + union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ + union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ +} r_io_rscan_from_rscan0gaflidj_t; + + +typedef struct st_rscan_from_rscan0rmidp +{ + + union iodefine_reg32_t RMIDp; /* RMIDp */ + union iodefine_reg32_t RMPTRp; /* RMPTRp */ + union iodefine_reg32_t RMDF0p; /* RMDF0p */ + union iodefine_reg32_t RMDF1p; /* RMDF1p */ +} r_io_rscan_from_rscan0rmidp_t; + + +typedef struct st_rscan_from_rscan0rfidm +{ + + union iodefine_reg32_t RFIDm; /* RFIDm */ + union iodefine_reg32_t RFPTRm; /* RFPTRm */ + union iodefine_reg32_t RFDF0m; /* RFDF0m */ + union iodefine_reg32_t RFDF1m; /* RFDF1m */ +} r_io_rscan_from_rscan0rfidm_t; + + +typedef struct st_rscan_from_rscan0tmidp +{ + + union iodefine_reg32_t TMIDp; /* TMIDp */ + union iodefine_reg32_t TMPTRp; /* TMPTRp */ + union iodefine_reg32_t TMDF0p; /* TMDF0p */ + union iodefine_reg32_t TMDF1p; /* TMDF1p */ +} r_io_rscan_from_rscan0tmidp_t; + + +typedef struct st_rscan_from_rscan0cfidm +{ + + union iodefine_reg32_t CFIDm; /* CFIDm */ + union iodefine_reg32_t CFPTRm; /* CFPTRm */ + union iodefine_reg32_t CFDF0m; /* CFDF0m */ + union iodefine_reg32_t CFDF1m; /* CFDF1m */ +} r_io_rscan_from_rscan0cfidm_t; + + +/* Channel array defines of RSCAN0 (2)*/ +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS +volatile struct st_rscan_from_rscan0cfidm* RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS +volatile struct st_rscan_from_rscan0tmidp* RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS +volatile struct st_rscan_from_rscan0rfidm* RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS +volatile struct st_rscan_from_rscan0rmidp* RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS +volatile struct st_rscan_from_rscan0gaflidj* RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS +volatile struct st_rscan_from_rscan0cncfg* RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */ +/* End of channel array defines of RSCAN0 (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h new file mode 100644 index 00000000000..5c63e293467 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h @@ -0,0 +1,224 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef RSPI_IODEFINE_H +#define RSPI_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ +#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ +#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ +#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ +#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ + + +/* Start of channel array defines of RSPI */ + +/* Channel array defines of RSPI */ +/*(Sample) value = RSPI[ channel ]->SPCR; */ +#define RSPI_COUNT (5) +#define RSPI_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of RSPI */ + + +#define SPCR_0 (RSPI0.SPCR) +#define SSLP_0 (RSPI0.SSLP) +#define SPPCR_0 (RSPI0.SPPCR) +#define SPSR_0 (RSPI0.SPSR) +#define SPDR_0 (RSPI0.SPDR.UINT32) +#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L]) +#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H]) +#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL]) +#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH]) +#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL]) +#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH]) +#define SPSCR_0 (RSPI0.SPSCR) +#define SPSSR_0 (RSPI0.SPSSR) +#define SPBR_0 (RSPI0.SPBR) +#define SPDCR_0 (RSPI0.SPDCR) +#define SPCKD_0 (RSPI0.SPCKD) +#define SSLND_0 (RSPI0.SSLND) +#define SPND_0 (RSPI0.SPND) +#define SPCMD0_0 (RSPI0.SPCMD0) +#define SPCMD1_0 (RSPI0.SPCMD1) +#define SPCMD2_0 (RSPI0.SPCMD2) +#define SPCMD3_0 (RSPI0.SPCMD3) +#define SPBFCR_0 (RSPI0.SPBFCR) +#define SPBFDR_0 (RSPI0.SPBFDR) +#define SPCR_1 (RSPI1.SPCR) +#define SSLP_1 (RSPI1.SSLP) +#define SPPCR_1 (RSPI1.SPPCR) +#define SPSR_1 (RSPI1.SPSR) +#define SPDR_1 (RSPI1.SPDR.UINT32) +#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L]) +#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H]) +#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL]) +#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH]) +#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL]) +#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH]) +#define SPSCR_1 (RSPI1.SPSCR) +#define SPSSR_1 (RSPI1.SPSSR) +#define SPBR_1 (RSPI1.SPBR) +#define SPDCR_1 (RSPI1.SPDCR) +#define SPCKD_1 (RSPI1.SPCKD) +#define SSLND_1 (RSPI1.SSLND) +#define SPND_1 (RSPI1.SPND) +#define SPCMD0_1 (RSPI1.SPCMD0) +#define SPCMD1_1 (RSPI1.SPCMD1) +#define SPCMD2_1 (RSPI1.SPCMD2) +#define SPCMD3_1 (RSPI1.SPCMD3) +#define SPBFCR_1 (RSPI1.SPBFCR) +#define SPBFDR_1 (RSPI1.SPBFDR) +#define SPCR_2 (RSPI2.SPCR) +#define SSLP_2 (RSPI2.SSLP) +#define SPPCR_2 (RSPI2.SPPCR) +#define SPSR_2 (RSPI2.SPSR) +#define SPDR_2 (RSPI2.SPDR.UINT32) +#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L]) +#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H]) +#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL]) +#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH]) +#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL]) +#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH]) +#define SPSCR_2 (RSPI2.SPSCR) +#define SPSSR_2 (RSPI2.SPSSR) +#define SPBR_2 (RSPI2.SPBR) +#define SPDCR_2 (RSPI2.SPDCR) +#define SPCKD_2 (RSPI2.SPCKD) +#define SSLND_2 (RSPI2.SSLND) +#define SPND_2 (RSPI2.SPND) +#define SPCMD0_2 (RSPI2.SPCMD0) +#define SPCMD1_2 (RSPI2.SPCMD1) +#define SPCMD2_2 (RSPI2.SPCMD2) +#define SPCMD3_2 (RSPI2.SPCMD3) +#define SPBFCR_2 (RSPI2.SPBFCR) +#define SPBFDR_2 (RSPI2.SPBFDR) +#define SPCR_3 (RSPI3.SPCR) +#define SSLP_3 (RSPI3.SSLP) +#define SPPCR_3 (RSPI3.SPPCR) +#define SPSR_3 (RSPI3.SPSR) +#define SPDR_3 (RSPI3.SPDR.UINT32) +#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L]) +#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H]) +#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL]) +#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH]) +#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL]) +#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH]) +#define SPSCR_3 (RSPI3.SPSCR) +#define SPSSR_3 (RSPI3.SPSSR) +#define SPBR_3 (RSPI3.SPBR) +#define SPDCR_3 (RSPI3.SPDCR) +#define SPCKD_3 (RSPI3.SPCKD) +#define SSLND_3 (RSPI3.SSLND) +#define SPND_3 (RSPI3.SPND) +#define SPCMD0_3 (RSPI3.SPCMD0) +#define SPCMD1_3 (RSPI3.SPCMD1) +#define SPCMD2_3 (RSPI3.SPCMD2) +#define SPCMD3_3 (RSPI3.SPCMD3) +#define SPBFCR_3 (RSPI3.SPBFCR) +#define SPBFDR_3 (RSPI3.SPBFDR) +#define SPCR_4 (RSPI4.SPCR) +#define SSLP_4 (RSPI4.SSLP) +#define SPPCR_4 (RSPI4.SPPCR) +#define SPSR_4 (RSPI4.SPSR) +#define SPDR_4 (RSPI4.SPDR.UINT32) +#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L]) +#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H]) +#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL]) +#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH]) +#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL]) +#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH]) +#define SPSCR_4 (RSPI4.SPSCR) +#define SPSSR_4 (RSPI4.SPSSR) +#define SPBR_4 (RSPI4.SPBR) +#define SPDCR_4 (RSPI4.SPDCR) +#define SPCKD_4 (RSPI4.SPCKD) +#define SSLND_4 (RSPI4.SSLND) +#define SPND_4 (RSPI4.SPND) +#define SPCMD0_4 (RSPI4.SPCMD0) +#define SPCMD1_4 (RSPI4.SPCMD1) +#define SPCMD2_4 (RSPI4.SPCMD2) +#define SPCMD3_4 (RSPI4.SPCMD3) +#define SPBFCR_4 (RSPI4.SPBFCR) +#define SPBFDR_4 (RSPI4.SPBFDR) + +#define SPCMD_COUNT (4) + + +typedef struct st_rspi +{ + /* RSPI */ + volatile uint8_t SPCR; /* SPCR */ + volatile uint8_t SSLP; /* SSLP */ + volatile uint8_t SPPCR; /* SPPCR */ + volatile uint8_t SPSR; /* SPSR */ + union iodefine_reg32_t SPDR; /* SPDR */ + + volatile uint8_t SPSCR; /* SPSCR */ + volatile uint8_t SPSSR; /* SPSSR */ + volatile uint8_t SPBR; /* SPBR */ + volatile uint8_t SPDCR; /* SPDCR */ + volatile uint8_t SPCKD; /* SPCKD */ + volatile uint8_t SSLND; /* SSLND */ + volatile uint8_t SPND; /* SPND */ + volatile uint8_t dummy1[1]; /* */ + +/* #define SPCMD_COUNT (4) */ + volatile uint16_t SPCMD0; /* SPCMD0 */ + volatile uint16_t SPCMD1; /* SPCMD1 */ + volatile uint16_t SPCMD2; /* SPCMD2 */ + volatile uint16_t SPCMD3; /* SPCMD3 */ + volatile uint8_t dummy2[8]; /* */ + volatile uint8_t SPBFCR; /* SPBFCR */ + volatile uint8_t dummy3[1]; /* */ + volatile uint16_t SPBFDR; /* SPBFDR */ +} r_io_rspi_t; + + +/* Channel array defines of RSPI (2)*/ +#ifdef DECLARE_RSPI_CHANNELS +volatile struct st_rspi* RSPI[ RSPI_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSPI_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSPI_CHANNELS */ +/* End of channel array defines of RSPI (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h similarity index 82% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h index 6cfb46dde33..1df2c7c3d17 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h @@ -18,20 +18,50 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rtc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RTC_IODEFINE_H #define RTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_rtc -{ /* RTC */ +#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ + + +#define RTCR64CNT (RTC.R64CNT) +#define RTCRSECCNT (RTC.RSECCNT) +#define RTCRMINCNT (RTC.RMINCNT) +#define RTCRHRCNT (RTC.RHRCNT) +#define RTCRWKCNT (RTC.RWKCNT) +#define RTCRDAYCNT (RTC.RDAYCNT) +#define RTCRMONCNT (RTC.RMONCNT) +#define RTCRYRCNT (RTC.RYRCNT) +#define RTCRSECAR (RTC.RSECAR) +#define RTCRMINAR (RTC.RMINAR) +#define RTCRHRAR (RTC.RHRAR) +#define RTCRWKAR (RTC.RWKAR) +#define RTCRDAYAR (RTC.RDAYAR) +#define RTCRMONAR (RTC.RMONAR) +#define RTCRCR1 (RTC.RCR1) +#define RTCRCR2 (RTC.RCR2) +#define RTCRYRAR (RTC.RYRAR) +#define RTCRCR3 (RTC.RCR3) +#define RTCRCR5 (RTC.RCR5) +#define RTCRFRH (RTC.RFRH) +#define RTCRFRL (RTC.RFRL) + + +typedef struct st_rtc +{ + /* RTC */ volatile uint8_t R64CNT; /* R64CNT */ volatile uint8_t dummy537[1]; /* */ volatile uint8_t RSECCNT; /* RSECCNT */ @@ -71,32 +101,11 @@ struct st_rtc volatile uint8_t dummy554[3]; /* */ volatile uint16_t RFRH; /* RFRH */ volatile uint16_t RFRL; /* RFRL */ -}; - - -#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ +} r_io_rtc_t; -#define RTCR64CNT RTC.R64CNT -#define RTCRSECCNT RTC.RSECCNT -#define RTCRMINCNT RTC.RMINCNT -#define RTCRHRCNT RTC.RHRCNT -#define RTCRWKCNT RTC.RWKCNT -#define RTCRDAYCNT RTC.RDAYCNT -#define RTCRMONCNT RTC.RMONCNT -#define RTCRYRCNT RTC.RYRCNT -#define RTCRSECAR RTC.RSECAR -#define RTCRMINAR RTC.RMINAR -#define RTCRHRAR RTC.RHRAR -#define RTCRWKAR RTC.RWKAR -#define RTCRDAYAR RTC.RDAYAR -#define RTCRMONAR RTC.RMONAR -#define RTCRCR1 RTC.RCR1 -#define RTCRCR2 RTC.RCR2 -#define RTCRYRAR RTC.RYRAR -#define RTCRCR3 RTC.RCR3 -#define RTCRCR5 RTC.RCR5 -#define RTCRFRH RTC.RFRH -#define RTCRFRL RTC.RFRL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h similarity index 55% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h index 9a710604ce8..de594577e2a 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h @@ -18,21 +18,137 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCIF_IODEFINE_H #define SCIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scif -{ /* SCIF */ +#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ +#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ +#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ +#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ +#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ +#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ +#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ +#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ + + +/* Start of channel array defines of SCIF */ + +/* Channel array defines of SCIF */ +/*(Sample) value = SCIF[ channel ]->SCSMR; */ +#define SCIF_COUNT (8) +#define SCIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIF */ + + +#define SCSMR_0 (SCIF0.SCSMR) +#define SCBRR_0 (SCIF0.SCBRR) +#define SCSCR_0 (SCIF0.SCSCR) +#define SCFTDR_0 (SCIF0.SCFTDR) +#define SCFSR_0 (SCIF0.SCFSR) +#define SCFRDR_0 (SCIF0.SCFRDR) +#define SCFCR_0 (SCIF0.SCFCR) +#define SCFDR_0 (SCIF0.SCFDR) +#define SCSPTR_0 (SCIF0.SCSPTR) +#define SCLSR_0 (SCIF0.SCLSR) +#define SCEMR_0 (SCIF0.SCEMR) +#define SCSMR_1 (SCIF1.SCSMR) +#define SCBRR_1 (SCIF1.SCBRR) +#define SCSCR_1 (SCIF1.SCSCR) +#define SCFTDR_1 (SCIF1.SCFTDR) +#define SCFSR_1 (SCIF1.SCFSR) +#define SCFRDR_1 (SCIF1.SCFRDR) +#define SCFCR_1 (SCIF1.SCFCR) +#define SCFDR_1 (SCIF1.SCFDR) +#define SCSPTR_1 (SCIF1.SCSPTR) +#define SCLSR_1 (SCIF1.SCLSR) +#define SCEMR_1 (SCIF1.SCEMR) +#define SCSMR_2 (SCIF2.SCSMR) +#define SCBRR_2 (SCIF2.SCBRR) +#define SCSCR_2 (SCIF2.SCSCR) +#define SCFTDR_2 (SCIF2.SCFTDR) +#define SCFSR_2 (SCIF2.SCFSR) +#define SCFRDR_2 (SCIF2.SCFRDR) +#define SCFCR_2 (SCIF2.SCFCR) +#define SCFDR_2 (SCIF2.SCFDR) +#define SCSPTR_2 (SCIF2.SCSPTR) +#define SCLSR_2 (SCIF2.SCLSR) +#define SCEMR_2 (SCIF2.SCEMR) +#define SCSMR_3 (SCIF3.SCSMR) +#define SCBRR_3 (SCIF3.SCBRR) +#define SCSCR_3 (SCIF3.SCSCR) +#define SCFTDR_3 (SCIF3.SCFTDR) +#define SCFSR_3 (SCIF3.SCFSR) +#define SCFRDR_3 (SCIF3.SCFRDR) +#define SCFCR_3 (SCIF3.SCFCR) +#define SCFDR_3 (SCIF3.SCFDR) +#define SCSPTR_3 (SCIF3.SCSPTR) +#define SCLSR_3 (SCIF3.SCLSR) +#define SCEMR_3 (SCIF3.SCEMR) +#define SCSMR_4 (SCIF4.SCSMR) +#define SCBRR_4 (SCIF4.SCBRR) +#define SCSCR_4 (SCIF4.SCSCR) +#define SCFTDR_4 (SCIF4.SCFTDR) +#define SCFSR_4 (SCIF4.SCFSR) +#define SCFRDR_4 (SCIF4.SCFRDR) +#define SCFCR_4 (SCIF4.SCFCR) +#define SCFDR_4 (SCIF4.SCFDR) +#define SCSPTR_4 (SCIF4.SCSPTR) +#define SCLSR_4 (SCIF4.SCLSR) +#define SCEMR_4 (SCIF4.SCEMR) +#define SCSMR_5 (SCIF5.SCSMR) +#define SCBRR_5 (SCIF5.SCBRR) +#define SCSCR_5 (SCIF5.SCSCR) +#define SCFTDR_5 (SCIF5.SCFTDR) +#define SCFSR_5 (SCIF5.SCFSR) +#define SCFRDR_5 (SCIF5.SCFRDR) +#define SCFCR_5 (SCIF5.SCFCR) +#define SCFDR_5 (SCIF5.SCFDR) +#define SCSPTR_5 (SCIF5.SCSPTR) +#define SCLSR_5 (SCIF5.SCLSR) +#define SCEMR_5 (SCIF5.SCEMR) +#define SCSMR_6 (SCIF6.SCSMR) +#define SCBRR_6 (SCIF6.SCBRR) +#define SCSCR_6 (SCIF6.SCSCR) +#define SCFTDR_6 (SCIF6.SCFTDR) +#define SCFSR_6 (SCIF6.SCFSR) +#define SCFRDR_6 (SCIF6.SCFRDR) +#define SCFCR_6 (SCIF6.SCFCR) +#define SCFDR_6 (SCIF6.SCFDR) +#define SCSPTR_6 (SCIF6.SCSPTR) +#define SCLSR_6 (SCIF6.SCLSR) +#define SCEMR_6 (SCIF6.SCEMR) +#define SCSMR_7 (SCIF7.SCSMR) +#define SCBRR_7 (SCIF7.SCBRR) +#define SCSCR_7 (SCIF7.SCSCR) +#define SCFTDR_7 (SCIF7.SCFTDR) +#define SCFSR_7 (SCIF7.SCFSR) +#define SCFRDR_7 (SCIF7.SCFRDR) +#define SCFCR_7 (SCIF7.SCFCR) +#define SCFDR_7 (SCIF7.SCFDR) +#define SCSPTR_7 (SCIF7.SCSPTR) +#define SCLSR_7 (SCIF7.SCLSR) +#define SCEMR_7 (SCIF7.SCEMR) + + +typedef struct st_scif +{ + /* SCIF */ volatile uint16_t SCSMR; /* SCSMR */ volatile uint8_t dummy1[2]; /* */ volatile uint8_t SCBRR; /* SCBRR */ @@ -54,129 +170,21 @@ struct st_scif volatile uint16_t SCLSR; /* SCLSR */ volatile uint8_t dummy10[2]; /* */ volatile uint16_t SCEMR; /* SCEMR */ -}; - +} r_io_scif_t; -#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ -#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ -#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ -#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ -#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ -#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ -#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ -#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ - -#define P_SCIF0 (0xE8007000uL) /* SCIF0 */ -#define P_SCIF1 (0xE8007800uL) /* SCIF1 */ -#define P_SCIF2 (0xE8008000uL) /* SCIF2 */ -#define P_SCIF3 (0xE8008800uL) /* SCIF3 */ -#define P_SCIF4 (0xE8009000uL) /* SCIF4 */ -#define P_SCIF5 (0xE8009800uL) /* SCIF5 */ -#define P_SCIF6 (0xE800A000uL) /* SCIF6 */ -#define P_SCIF7 (0xE800A800uL) /* SCIF7 */ - - -/* Start of channnel array defines of SCIF */ - -/* Channnel array defines of SCIF */ -/*(Sample) value = SCIF[ channel ]->SCSMR; */ -#define SCIF_COUNT 8 -#define SCIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of SCIF */ +/* Channel array defines of SCIF (2)*/ +#ifdef DECLARE_SCIF_CHANNELS +volatile struct st_scif* SCIF[ SCIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIF_CHANNELS */ +/* End of channel array defines of SCIF (2)*/ -#define SCSMR_0 SCIF0.SCSMR -#define SCBRR_0 SCIF0.SCBRR -#define SCSCR_0 SCIF0.SCSCR -#define SCFTDR_0 SCIF0.SCFTDR -#define SCFSR_0 SCIF0.SCFSR -#define SCFRDR_0 SCIF0.SCFRDR -#define SCFCR_0 SCIF0.SCFCR -#define SCFDR_0 SCIF0.SCFDR -#define SCSPTR_0 SCIF0.SCSPTR -#define SCLSR_0 SCIF0.SCLSR -#define SCEMR_0 SCIF0.SCEMR -#define SCSMR_1 SCIF1.SCSMR -#define SCBRR_1 SCIF1.SCBRR -#define SCSCR_1 SCIF1.SCSCR -#define SCFTDR_1 SCIF1.SCFTDR -#define SCFSR_1 SCIF1.SCFSR -#define SCFRDR_1 SCIF1.SCFRDR -#define SCFCR_1 SCIF1.SCFCR -#define SCFDR_1 SCIF1.SCFDR -#define SCSPTR_1 SCIF1.SCSPTR -#define SCLSR_1 SCIF1.SCLSR -#define SCEMR_1 SCIF1.SCEMR -#define SCSMR_2 SCIF2.SCSMR -#define SCBRR_2 SCIF2.SCBRR -#define SCSCR_2 SCIF2.SCSCR -#define SCFTDR_2 SCIF2.SCFTDR -#define SCFSR_2 SCIF2.SCFSR -#define SCFRDR_2 SCIF2.SCFRDR -#define SCFCR_2 SCIF2.SCFCR -#define SCFDR_2 SCIF2.SCFDR -#define SCSPTR_2 SCIF2.SCSPTR -#define SCLSR_2 SCIF2.SCLSR -#define SCEMR_2 SCIF2.SCEMR -#define SCSMR_3 SCIF3.SCSMR -#define SCBRR_3 SCIF3.SCBRR -#define SCSCR_3 SCIF3.SCSCR -#define SCFTDR_3 SCIF3.SCFTDR -#define SCFSR_3 SCIF3.SCFSR -#define SCFRDR_3 SCIF3.SCFRDR -#define SCFCR_3 SCIF3.SCFCR -#define SCFDR_3 SCIF3.SCFDR -#define SCSPTR_3 SCIF3.SCSPTR -#define SCLSR_3 SCIF3.SCLSR -#define SCEMR_3 SCIF3.SCEMR -#define SCSMR_4 SCIF4.SCSMR -#define SCBRR_4 SCIF4.SCBRR -#define SCSCR_4 SCIF4.SCSCR -#define SCFTDR_4 SCIF4.SCFTDR -#define SCFSR_4 SCIF4.SCFSR -#define SCFRDR_4 SCIF4.SCFRDR -#define SCFCR_4 SCIF4.SCFCR -#define SCFDR_4 SCIF4.SCFDR -#define SCSPTR_4 SCIF4.SCSPTR -#define SCLSR_4 SCIF4.SCLSR -#define SCEMR_4 SCIF4.SCEMR -#define SCSMR_5 SCIF5.SCSMR -#define SCBRR_5 SCIF5.SCBRR -#define SCSCR_5 SCIF5.SCSCR -#define SCFTDR_5 SCIF5.SCFTDR -#define SCFSR_5 SCIF5.SCFSR -#define SCFRDR_5 SCIF5.SCFRDR -#define SCFCR_5 SCIF5.SCFCR -#define SCFDR_5 SCIF5.SCFDR -#define SCSPTR_5 SCIF5.SCSPTR -#define SCLSR_5 SCIF5.SCLSR -#define SCEMR_5 SCIF5.SCEMR -#define SCSMR_6 SCIF6.SCSMR -#define SCBRR_6 SCIF6.SCBRR -#define SCSCR_6 SCIF6.SCSCR -#define SCFTDR_6 SCIF6.SCFTDR -#define SCFSR_6 SCIF6.SCFSR -#define SCFRDR_6 SCIF6.SCFRDR -#define SCFCR_6 SCIF6.SCFCR -#define SCFDR_6 SCIF6.SCFDR -#define SCSPTR_6 SCIF6.SCSPTR -#define SCLSR_6 SCIF6.SCLSR -#define SCEMR_6 SCIF6.SCEMR -#define SCSMR_7 SCIF7.SCSMR -#define SCBRR_7 SCIF7.SCBRR -#define SCSCR_7 SCIF7.SCSCR -#define SCFTDR_7 SCIF7.SCFTDR -#define SCFSR_7 SCIF7.SCFSR -#define SCFRDR_7 SCIF7.SCFRDR -#define SCFCR_7 SCIF7.SCFCR -#define SCFDR_7 SCIF7.SCFDR -#define SCSPTR_7 SCIF7.SCSPTR -#define SCLSR_7 SCIF7.SCLSR -#define SCEMR_7 SCIF7.SCEMR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h similarity index 68% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h index 2ddf1e61d90..fad306aca18 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h @@ -18,20 +18,63 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scim_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCIM_IODEFINE_H #define SCIM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scim -{ /* SCIM */ +#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ +#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ + + +/* Start of channel array defines of SCIM */ + +/* Channel array defines of SCIM */ +/*(Sample) value = SCIM[ channel ]->SMR; */ +#define SCIM_COUNT (2) +#define SCIM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIM0, &SCIM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIM */ + + +#define SMR0 (SCIM0.SMR) +#define BRR0 (SCIM0.BRR) +#define SCR0 (SCIM0.SCR) +#define TDR0 (SCIM0.TDR) +#define SSR0 (SCIM0.SSR) +#define RDR0 (SCIM0.RDR) +#define SCMR0 (SCIM0.SCMR) +#define SEMR0 (SCIM0.SEMR) +#define SNFR0 (SCIM0.SNFR) +#define SECR0 (SCIM0.SECR) +#define SMR1 (SCIM1.SMR) +#define BRR1 (SCIM1.BRR) +#define SCR1 (SCIM1.SCR) +#define TDR1 (SCIM1.TDR) +#define SSR1 (SCIM1.SSR) +#define RDR1 (SCIM1.RDR) +#define SCMR1 (SCIM1.SCMR) +#define SEMR1 (SCIM1.SEMR) +#define SNFR1 (SCIM1.SNFR) +#define SECR1 (SCIM1.SECR) + + +typedef struct st_scim +{ + /* SCIM */ volatile uint8_t SMR; /* SMR */ volatile uint8_t BRR; /* BRR */ volatile uint8_t SCR; /* SCR */ @@ -43,45 +86,21 @@ struct st_scim volatile uint8_t SNFR; /* SNFR */ volatile uint8_t dummy1[4]; /* */ volatile uint8_t SECR; /* SECR */ -}; - - -#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ -#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ - +} r_io_scim_t; -/* Start of channnel array defines of SCIM */ - -/* Channnel array defines of SCIM */ -/*(Sample) value = SCIM[ channel ]->SMR; */ -#define SCIM_COUNT 2 -#define SCIM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIM0, &SCIM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of SCIM */ +/* Channel array defines of SCIM (2)*/ +#ifdef DECLARE_SCIM_CHANNELS +volatile struct st_scim* SCIM[ SCIM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIM_CHANNELS */ +/* End of channel array defines of SCIM (2)*/ -#define SMR0 SCIM0.SMR -#define BRR0 SCIM0.BRR -#define SCR0 SCIM0.SCR -#define TDR0 SCIM0.TDR -#define SSR0 SCIM0.SSR -#define RDR0 SCIM0.RDR -#define SCMR0 SCIM0.SCMR -#define SEMR0 SCIM0.SEMR -#define SNFR0 SCIM0.SNFR -#define SECR0 SCIM0.SECR -#define SMR1 SCIM1.SMR -#define BRR1 SCIM1.BRR -#define SCR1 SCIM1.SCR -#define TDR1 SCIM1.TDR -#define SSR1 SCIM1.SSR -#define RDR1 SCIM1.RDR -#define SCMR1 SCIM1.SCMR -#define SEMR1 SCIM1.SEMR -#define SNFR1 SCIM1.SNFR -#define SECR1 SCIM1.SECR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h similarity index 70% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h index a6d5646dcc6..4293ec42774 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h @@ -18,61 +18,427 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scux_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCUX_IODEFINE_H #define SCUX_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scux -{ /* SCUX */ +#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ + + +/* Start of channel array defines of SCUX */ + +/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ +#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ +#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ +#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ + + +/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2) +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ +#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ + + +/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ +#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ +#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ +#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ + + +/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ +#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ +#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ +#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ + + +/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ +#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ +#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ +#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ + + +/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ +#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ +#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ +#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ + +/* End of channel array defines of SCUX */ + + +#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0) +#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0) +#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1) +#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1) +#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2) +#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2) +#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3) +#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3) +#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0) +#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0) +#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1) +#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1) +#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2) +#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2) +#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3) +#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3) +#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0) +#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0) +#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0) +#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0) +#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0) +#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0) +#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0) +#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1) +#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1) +#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1) +#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1) +#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1) +#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1) +#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1) +#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2) +#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2) +#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2) +#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2) +#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2) +#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2) +#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2) +#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3) +#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3) +#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3) +#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3) +#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3) +#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3) +#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3) +#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0) +#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0) +#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0) +#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0) +#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0) +#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0) +#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1) +#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1) +#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1) +#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1) +#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1) +#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1) +#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2) +#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2) +#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2) +#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2) +#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2) +#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2) +#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3) +#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3) +#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3) +#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3) +#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3) +#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3) +#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0) +#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0) +#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0) +#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0) +#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0) +#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0) +#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0) +#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0) +#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0) +#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0) +#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0) +#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0) +#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0) +#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0) +#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0) +#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0) +#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0) +#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0) +#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0) +#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0) +#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0) +#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0) +#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0) +#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0) +#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0) +#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1) +#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1) +#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1) +#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1) +#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1) +#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1) +#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1) +#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1) +#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1) +#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1) +#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1) +#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1) +#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1) +#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1) +#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1) +#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1) +#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1) +#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1) +#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1) +#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1) +#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1) +#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1) +#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1) +#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1) +#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1) +#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0) +#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0) +#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0) +#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0) +#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0) +#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0) +#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0) +#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0) +#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0) +#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0) +#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0) +#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0) +#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0) +#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0) +#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0) +#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0) +#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0) +#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0) +#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0) +#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0) +#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0) +#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1) +#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1) +#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1) +#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1) +#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1) +#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1) +#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1) +#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1) +#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1) +#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1) +#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1) +#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1) +#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1) +#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1) +#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1) +#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1) +#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1) +#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1) +#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1) +#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1) +#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1) +#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2) +#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2) +#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2) +#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2) +#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2) +#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2) +#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2) +#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2) +#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2) +#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2) +#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2) +#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2) +#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2) +#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2) +#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2) +#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2) +#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2) +#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2) +#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2) +#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2) +#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2) +#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3) +#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3) +#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3) +#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3) +#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3) +#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3) +#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3) +#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3) +#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3) +#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3) +#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3) +#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3) +#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3) +#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3) +#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3) +#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3) +#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3) +#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3) +#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3) +#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3) +#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3) +#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0) +#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0) +#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0) +#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0) +#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0) +#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0) +#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0) +#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0) +#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0) +#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0) +#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0) +#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM) +#define SCUXDMACR_CIM (SCUX.DMACR_CIM) +#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32) +#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L]) +#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H]) +#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32) +#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L]) +#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H]) +#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32) +#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L]) +#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H]) +#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32) +#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L]) +#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H]) +#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32) +#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L]) +#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H]) +#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32) +#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L]) +#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H]) +#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32) +#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L]) +#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H]) +#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32) +#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L]) +#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H]) +#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM) +#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM) +#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM) +#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM) +#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM) +#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM) +#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM) +#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM) +#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM) +#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM) +#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM) +#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM) +#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM) +#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM) +#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM) +#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM) + +#define SCUX_DMATDnCIM_COUNT (4) +#define SCUX_DMATUnCIM_COUNT (4) +#define SCUX_FDTSELnCIM_COUNT (4) +#define SCUX_FUTSELnCIM_COUNT (4) +#define SCUX_SRCRSELnCIM_COUNT (4) + + +typedef struct st_scux +{ + /* SCUX */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ volatile uint8_t dummy259[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ volatile uint8_t dummy260[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ volatile uint8_t dummy261[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ volatile uint8_t dummy262[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ volatile uint8_t dummy263[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ volatile uint8_t dummy264[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ volatile uint8_t dummy265[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ volatile uint8_t dummy266[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ @@ -82,8 +448,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ volatile uint8_t dummy267[4]; /* */ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy268[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ @@ -93,8 +461,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ volatile uint8_t dummy269[4]; /* */ volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy270[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ @@ -104,8 +474,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ volatile uint8_t dummy271[4]; /* */ volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy272[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ @@ -115,8 +487,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ volatile uint8_t dummy273[4]; /* */ volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy274[224]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ @@ -125,8 +499,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ volatile uint8_t dummy275[4]; /* */ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy276[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ @@ -135,8 +511,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ volatile uint8_t dummy277[4]; /* */ volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy278[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ @@ -145,8 +523,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ volatile uint8_t dummy279[4]; /* */ volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy280[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ @@ -155,8 +535,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ volatile uint8_t dummy281[4]; /* */ volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy282[228]; /* */ + /* start of struct st_scux_from_srcir0_2src0_n */ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ @@ -185,8 +567,10 @@ struct st_scux volatile uint8_t dummy284[4]; /* */ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ + /* end of struct st_scux_from_srcir0_2src0_n */ volatile uint8_t dummy285[148]; /* */ + /* start of struct st_scux_from_srcir0_2src0_n */ volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ @@ -215,8 +599,10 @@ struct st_scux volatile uint8_t dummy287[4]; /* */ volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ + /* end of struct st_scux_from_srcir0_2src0_n */ volatile uint8_t dummy288[148]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ @@ -240,8 +626,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ volatile uint8_t dummy289[4]; /* */ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy290[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ @@ -265,8 +653,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ volatile uint8_t dummy291[4]; /* */ volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy292[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ @@ -290,8 +680,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ volatile uint8_t dummy293[4]; /* */ volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy294[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ @@ -315,6 +707,7 @@ struct st_scux volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ volatile uint8_t dummy295[4]; /* */ volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy296[168]; /* */ volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ @@ -331,12 +724,14 @@ struct st_scux volatile uint8_t dummy297[212]; /* */ volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ volatile uint32_t DMACR_CIM; /* DMACR_CIM */ -#define SCUX_DMATDn_CIM_COUNT 4 + +/* #define SCUX_DMATDnCIM_COUNT (4) */ union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ -#define SCUX_DMATUn_CIM_COUNT 4 + +/* #define SCUX_DMATUnCIM_COUNT (4) */ union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ @@ -344,45 +739,51 @@ struct st_scux volatile uint8_t dummy298[16]; /* */ volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ -#define SCUX_FDTSELn_CIM_COUNT 4 + +/* #define SCUX_FDTSELnCIM_COUNT (4) */ volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ -#define SCUX_FUTSELn_CIM_COUNT 4 + +/* #define SCUX_FUTSELnCIM_COUNT (4) */ volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ -#define SCUX_SRCRSELn_CIM_COUNT 4 + +/* #define SCUX_SRCRSELnCIM_COUNT (4) */ volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ -}; +} r_io_scux_t; -struct st_scux_from_ipcir_ipc0_n +typedef struct st_scux_from_ipcir_ipc0_n { + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ volatile uint8_t dummy1[248]; /* */ -}; +} r_io_scux_from_ipcir_ipc0_n_t; -struct st_scux_from_opcir_opc0_n +typedef struct st_scux_from_opcir_opc0_n { + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ volatile uint8_t dummy1[248]; /* */ -}; +} r_io_scux_from_opcir_opc0_n_t; -struct st_scux_from_ffdir_ffd0_n +typedef struct st_scux_from_ffdir_ffd0_n { + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ @@ -391,11 +792,12 @@ struct st_scux_from_ffdir_ffd0_n volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ -}; +} r_io_scux_from_ffdir_ffd0_n_t; -struct st_scux_from_ffuir_ffu0_n +typedef struct st_scux_from_ffuir_ffu0_n { + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ @@ -403,11 +805,12 @@ struct st_scux_from_ffuir_ffu0_n volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ -}; +} r_io_scux_from_ffuir_ffu0_n_t; -struct st_scux_from_srcir0_2src0_n +typedef struct st_scux_from_srcir0_2src0_n { + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ @@ -435,11 +838,12 @@ struct st_scux_from_srcir0_2src0_n volatile uint8_t dummy2[4]; /* */ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ -}; +} r_io_scux_from_srcir0_2src0_n_t; -struct st_scux_from_dvuir_dvu0_n +typedef struct st_scux_from_dvuir_dvu0_n { + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ @@ -462,347 +866,56 @@ struct st_scux_from_dvuir_dvu0_n volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ -}; +} r_io_scux_from_dvuir_dvu0_n_t; -#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ +/* Channel array defines of SCUX (2)*/ +#ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */ +#ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */ -/* Start of channnel array defines of SCUX */ +#ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */ -/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ -#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ -#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ -#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ +#ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */ +#ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */ -/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ -#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ - +#ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */ +/* End of channel array defines of SCUX (2)*/ -/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ -#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ -#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ -#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ - - -/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ -#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ -#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ -#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ - - -/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ -#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ -#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ -#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ - - -/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ -#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ -#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ -#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ -/* End of channnel array defines of SCUX */ - - -#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 -#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 -#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 -#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 -#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 -#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 -#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 -#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 -#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 -#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 -#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 -#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 -#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 -#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 -#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 -#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 -#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 -#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 -#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 -#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 -#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 -#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 -#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 -#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 -#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 -#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 -#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 -#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 -#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 -#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 -#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 -#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 -#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 -#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 -#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 -#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 -#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 -#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 -#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 -#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 -#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 -#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 -#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 -#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 -#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 -#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 -#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 -#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 -#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 -#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 -#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 -#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 -#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 -#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 -#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 -#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 -#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 -#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 -#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 -#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 -#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 -#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 -#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 -#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 -#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 -#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 -#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 -#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 -#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 -#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 -#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 -#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 -#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 -#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 -#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 -#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 -#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 -#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 -#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 -#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 -#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 -#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 -#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 -#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 -#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 -#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 -#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 -#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 -#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 -#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 -#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 -#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 -#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 -#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 -#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 -#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 -#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 -#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 -#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 -#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 -#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 -#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 -#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 -#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 -#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 -#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 -#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 -#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 -#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 -#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 -#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 -#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 -#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 -#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 -#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 -#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 -#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 -#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 -#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 -#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 -#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 -#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 -#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 -#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 -#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 -#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 -#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 -#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 -#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 -#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 -#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 -#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 -#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 -#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 -#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 -#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 -#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 -#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 -#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 -#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 -#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 -#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 -#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 -#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 -#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 -#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 -#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 -#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 -#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 -#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 -#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 -#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 -#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 -#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 -#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 -#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 -#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 -#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 -#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 -#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 -#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 -#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 -#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 -#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 -#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 -#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 -#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 -#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 -#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 -#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 -#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 -#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 -#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 -#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 -#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 -#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 -#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 -#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 -#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 -#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 -#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 -#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 -#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 -#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 -#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 -#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 -#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 -#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 -#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 -#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 -#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 -#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 -#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 -#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 -#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 -#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 -#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 -#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 -#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 -#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 -#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 -#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 -#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 -#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 -#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 -#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 -#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 -#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 -#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 -#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 -#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 -#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 -#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 -#define SCUXSWRSR_CIM SCUX.SWRSR_CIM -#define SCUXDMACR_CIM SCUX.DMACR_CIM -#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 -#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] -#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] -#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 -#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] -#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] -#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 -#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] -#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] -#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 -#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] -#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] -#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 -#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] -#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] -#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 -#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] -#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] -#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 -#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] -#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] -#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 -#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] -#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] -#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM -#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM -#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM -#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM -#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM -#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM -#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM -#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM -#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM -#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM -#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM -#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM -#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM -#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM -#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM -#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h similarity index 62% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h index 78abfc08e86..dd6dee41d84 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h @@ -18,27 +18,20 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : sdg_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SDG_IODEFINE_H #define SDG_IODEFINE_H - -struct st_sdg -{ /* SDG */ - volatile uint8_t SGCR1; /* SGCR1 */ - volatile uint8_t SGCSR; /* SGCSR */ - volatile uint8_t SGCR2; /* SGCR2 */ - volatile uint8_t SGLR; /* SGLR */ - volatile uint8_t SGTFR; /* SGTFR */ - volatile uint8_t SGSFR; /* SGSFR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */ #define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */ @@ -46,41 +39,69 @@ struct st_sdg #define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */ -/* Start of channnel array defines of SDG */ +/* Start of channel array defines of SDG */ -/* Channnel array defines of SDG */ +/* Channel array defines of SDG */ /*(Sample) value = SDG[ channel ]->SGCR1; */ -#define SDG_COUNT 4 +#define SDG_COUNT (4) #define SDG_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &SDG0, &SDG1, &SDG2, &SDG3 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of SDG */ +/* End of channel array defines of SDG */ + + +#define SGCR1_0 (SDG0.SGCR1) +#define SGCSR_0 (SDG0.SGCSR) +#define SGCR2_0 (SDG0.SGCR2) +#define SGLR_0 (SDG0.SGLR) +#define SGTFR_0 (SDG0.SGTFR) +#define SGSFR_0 (SDG0.SGSFR) +#define SGCR1_1 (SDG1.SGCR1) +#define SGCSR_1 (SDG1.SGCSR) +#define SGCR2_1 (SDG1.SGCR2) +#define SGLR_1 (SDG1.SGLR) +#define SGTFR_1 (SDG1.SGTFR) +#define SGSFR_1 (SDG1.SGSFR) +#define SGCR1_2 (SDG2.SGCR1) +#define SGCSR_2 (SDG2.SGCSR) +#define SGCR2_2 (SDG2.SGCR2) +#define SGLR_2 (SDG2.SGLR) +#define SGTFR_2 (SDG2.SGTFR) +#define SGSFR_2 (SDG2.SGSFR) +#define SGCR1_3 (SDG3.SGCR1) +#define SGCSR_3 (SDG3.SGCSR) +#define SGCR2_3 (SDG3.SGCR2) +#define SGLR_3 (SDG3.SGLR) +#define SGTFR_3 (SDG3.SGTFR) +#define SGSFR_3 (SDG3.SGSFR) + + +typedef struct st_sdg +{ + /* SDG */ + volatile uint8_t SGCR1; /* SGCR1 */ + volatile uint8_t SGCSR; /* SGCSR */ + volatile uint8_t SGCR2; /* SGCR2 */ + volatile uint8_t SGLR; /* SGLR */ + volatile uint8_t SGTFR; /* SGTFR */ + volatile uint8_t SGSFR; /* SGSFR */ +} r_io_sdg_t; + + +/* Channel array defines of SDG (2)*/ +#ifdef DECLARE_SDG_CHANNELS +volatile struct st_sdg* SDG[ SDG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SDG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SDG_CHANNELS */ +/* End of channel array defines of SDG (2)*/ -#define SGCR1_0 SDG0.SGCR1 -#define SGCSR_0 SDG0.SGCSR -#define SGCR2_0 SDG0.SGCR2 -#define SGLR_0 SDG0.SGLR -#define SGTFR_0 SDG0.SGTFR -#define SGSFR_0 SDG0.SGSFR -#define SGCR1_1 SDG1.SGCR1 -#define SGCSR_1 SDG1.SGCSR -#define SGCR2_1 SDG1.SGCR2 -#define SGLR_1 SDG1.SGLR -#define SGTFR_1 SDG1.SGTFR -#define SGSFR_1 SDG1.SGSFR -#define SGCR1_2 SDG2.SGCR1 -#define SGCSR_2 SDG2.SGCSR -#define SGCR2_2 SDG2.SGCR2 -#define SGLR_2 SDG2.SGLR -#define SGTFR_2 SDG2.SGTFR -#define SGSFR_2 SDG2.SGSFR -#define SGCR1_3 SDG3.SGCR1 -#define SGCSR_3 SDG3.SGCSR -#define SGCR2_3 SDG3.SGCR2 -#define SGLR_3 SDG3.SGLR -#define SGTFR_3 SDG3.SGTFR -#define SGSFR_3 SDG3.SGSFR +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h similarity index 76% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h index 6f69f808507..a7e4c825290 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h @@ -18,19 +18,43 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : spdif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SPDIF_IODEFINE_H #define SPDIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_spdif -{ /* SPDIF */ +#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ + + +#define SPDIFTLCA (SPDIF.TLCA) +#define SPDIFTRCA (SPDIF.TRCA) +#define SPDIFTLCS (SPDIF.TLCS) +#define SPDIFTRCS (SPDIF.TRCS) +#define SPDIFTUI (SPDIF.TUI) +#define SPDIFRLCA (SPDIF.RLCA) +#define SPDIFRRCA (SPDIF.RRCA) +#define SPDIFRLCS (SPDIF.RLCS) +#define SPDIFRRCS (SPDIF.RRCS) +#define SPDIFRUI (SPDIF.RUI) +#define SPDIFCTRL (SPDIF.CTRL) +#define SPDIFSTAT (SPDIF.STAT) +#define SPDIFTDAD (SPDIF.TDAD) +#define SPDIFRDAD (SPDIF.RDAD) + + +typedef struct st_spdif +{ + /* SPDIF */ volatile uint32_t TLCA; /* TLCA */ volatile uint32_t TRCA; /* TRCA */ volatile uint32_t TLCS; /* TLCS */ @@ -45,24 +69,11 @@ struct st_spdif volatile uint32_t STAT; /* STAT */ volatile uint32_t TDAD; /* TDAD */ volatile uint32_t RDAD; /* RDAD */ -}; - - -#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ +} r_io_spdif_t; -#define SPDIFTLCA SPDIF.TLCA -#define SPDIFTRCA SPDIF.TRCA -#define SPDIFTLCS SPDIF.TLCS -#define SPDIFTRCS SPDIF.TRCS -#define SPDIFTUI SPDIF.TUI -#define SPDIFRLCA SPDIF.RLCA -#define SPDIFRRCA SPDIF.RRCA -#define SPDIFRLCS SPDIF.RLCS -#define SPDIFRRCS SPDIF.RRCS -#define SPDIFRUI SPDIF.RUI -#define SPDIFCTRL SPDIF.CTRL -#define SPDIFSTAT SPDIF.STAT -#define SPDIFTDAD SPDIF.TDAD -#define SPDIFRDAD SPDIF.RDAD +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h new file mode 100644 index 00000000000..6615aea8f7e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h @@ -0,0 +1,199 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spibsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef SPIBSC_IODEFINE_H +#define SPIBSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ +#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ + + +/* Start of channel array defines of SPIBSC */ + +/* Channel array defines of SPIBSC */ +/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ +#define SPIBSC_COUNT (2) +#define SPIBSC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SPIBSC0, &SPIBSC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SPIBSC */ + + +#define CMNCR_0 (SPIBSC0.CMNCR) +#define SSLDR_0 (SPIBSC0.SSLDR) +#define SPBCR_0 (SPIBSC0.SPBCR) +#define DRCR_0 (SPIBSC0.DRCR) +#define DRCMR_0 (SPIBSC0.DRCMR) +#define DREAR_0 (SPIBSC0.DREAR) +#define DROPR_0 (SPIBSC0.DROPR) +#define DRENR_0 (SPIBSC0.DRENR) +#define SMCR_0 (SPIBSC0.SMCR) +#define SMCMR_0 (SPIBSC0.SMCMR) +#define SMADR_0 (SPIBSC0.SMADR) +#define SMOPR_0 (SPIBSC0.SMOPR) +#define SMENR_0 (SPIBSC0.SMENR) +#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32) +#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32) +#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32) +#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32) +#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_0 (SPIBSC0.CMNSR) +#define CKDLY_0 (SPIBSC0.CKDLY) +#define DRDMCR_0 (SPIBSC0.DRDMCR) +#define DRDRENR_0 (SPIBSC0.DRDRENR) +#define SMDMCR_0 (SPIBSC0.SMDMCR) +#define SMDRENR_0 (SPIBSC0.SMDRENR) +#define SPODLY_0 (SPIBSC0.SPODLY) +#define CMNCR_1 (SPIBSC1.CMNCR) +#define SSLDR_1 (SPIBSC1.SSLDR) +#define SPBCR_1 (SPIBSC1.SPBCR) +#define DRCR_1 (SPIBSC1.DRCR) +#define DRCMR_1 (SPIBSC1.DRCMR) +#define DREAR_1 (SPIBSC1.DREAR) +#define DROPR_1 (SPIBSC1.DROPR) +#define DRENR_1 (SPIBSC1.DRENR) +#define SMCR_1 (SPIBSC1.SMCR) +#define SMCMR_1 (SPIBSC1.SMCMR) +#define SMADR_1 (SPIBSC1.SMADR) +#define SMOPR_1 (SPIBSC1.SMOPR) +#define SMENR_1 (SPIBSC1.SMENR) +#define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32) +#define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32) +#define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32) +#define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32) +#define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_1 (SPIBSC1.CMNSR) +#define CKDLY_1 (SPIBSC1.CKDLY) +#define DRDMCR_1 (SPIBSC1.DRDMCR) +#define DRDRENR_1 (SPIBSC1.DRDRENR) +#define SMDMCR_1 (SPIBSC1.SMDMCR) +#define SMDRENR_1 (SPIBSC1.SMDRENR) +#define SPODLY_1 (SPIBSC1.SPODLY) + + +typedef struct st_spibsc +{ + /* SPIBSC */ + volatile uint32_t CMNCR; /* CMNCR */ + volatile uint32_t SSLDR; /* SSLDR */ + volatile uint32_t SPBCR; /* SPBCR */ + volatile uint32_t DRCR; /* DRCR */ + volatile uint32_t DRCMR; /* DRCMR */ + volatile uint32_t DREAR; /* DREAR */ + volatile uint32_t DROPR; /* DROPR */ + volatile uint32_t DRENR; /* DRENR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint32_t SMCMR; /* SMCMR */ + volatile uint32_t SMADR; /* SMADR */ + volatile uint32_t SMOPR; /* SMOPR */ + volatile uint32_t SMENR; /* SMENR */ + volatile uint8_t dummy1[4]; /* */ + union iodefine_reg32_t SMRDR0; /* SMRDR0 */ + union iodefine_reg32_t SMRDR1; /* SMRDR1 */ + union iodefine_reg32_t SMWDR0; /* SMWDR0 */ + union iodefine_reg32_t SMWDR1; /* SMWDR1 */ + + volatile uint32_t CMNSR; /* CMNSR */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t CKDLY; /* CKDLY */ + volatile uint8_t dummy3[4]; /* */ + volatile uint32_t DRDMCR; /* DRDMCR */ + volatile uint32_t DRDRENR; /* DRDRENR */ + volatile uint32_t SMDMCR; /* SMDMCR */ + volatile uint32_t SMDRENR; /* SMDRENR */ + volatile uint32_t SPODLY; /* SPODLY */ +} r_io_spibsc_t; + + +/* Channel array defines of SPIBSC (2)*/ +#ifdef DECLARE_SPIBSC_CHANNELS +volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SPIBSC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SPIBSC_CHANNELS */ +/* End of channel array defines of SPIBSC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h similarity index 53% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h index 045551c9f23..c0134a5d629 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h @@ -18,34 +18,21 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ssif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SSIF_IODEFINE_H #define SSIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ssif -{ /* SSIF */ - volatile uint32_t SSICR; /* SSICR */ - volatile uint32_t SSISR; /* SSISR */ - volatile uint8_t dummy1[8]; /* */ - volatile uint32_t SSIFCR; /* SSIFCR */ - volatile uint32_t SSIFSR; /* SSIFSR */ - volatile uint32_t SSIFTDR; /* SSIFTDR */ - volatile uint32_t SSIFRDR; /* SSIFRDR */ - volatile uint32_t SSITDMR; /* SSITDMR */ - volatile uint32_t SSIFCCR; /* SSIFCCR */ - volatile uint32_t SSIFCMR; /* SSIFCMR */ - volatile uint32_t SSIFCSR; /* SSIFCSR */ -}; - - #define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ #define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ #define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ @@ -54,78 +41,110 @@ struct st_ssif #define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ -/* Start of channnel array defines of SSIF */ +/* Start of channel array defines of SSIF */ -/* Channnel array defines of SSIF */ +/* Channel array defines of SSIF */ /*(Sample) value = SSIF[ channel ]->SSICR; */ -#define SSIF_COUNT 6 +#define SSIF_COUNT (6) #define SSIF_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of SSIF */ +/* End of channel array defines of SSIF */ + + +#define SSICR_0 (SSIF0.SSICR) +#define SSISR_0 (SSIF0.SSISR) +#define SSIFCR_0 (SSIF0.SSIFCR) +#define SSIFSR_0 (SSIF0.SSIFSR) +#define SSIFTDR_0 (SSIF0.SSIFTDR) +#define SSIFRDR_0 (SSIF0.SSIFRDR) +#define SSITDMR_0 (SSIF0.SSITDMR) +#define SSIFCCR_0 (SSIF0.SSIFCCR) +#define SSIFCMR_0 (SSIF0.SSIFCMR) +#define SSIFCSR_0 (SSIF0.SSIFCSR) +#define SSICR_1 (SSIF1.SSICR) +#define SSISR_1 (SSIF1.SSISR) +#define SSIFCR_1 (SSIF1.SSIFCR) +#define SSIFSR_1 (SSIF1.SSIFSR) +#define SSIFTDR_1 (SSIF1.SSIFTDR) +#define SSIFRDR_1 (SSIF1.SSIFRDR) +#define SSITDMR_1 (SSIF1.SSITDMR) +#define SSIFCCR_1 (SSIF1.SSIFCCR) +#define SSIFCMR_1 (SSIF1.SSIFCMR) +#define SSIFCSR_1 (SSIF1.SSIFCSR) +#define SSICR_2 (SSIF2.SSICR) +#define SSISR_2 (SSIF2.SSISR) +#define SSIFCR_2 (SSIF2.SSIFCR) +#define SSIFSR_2 (SSIF2.SSIFSR) +#define SSIFTDR_2 (SSIF2.SSIFTDR) +#define SSIFRDR_2 (SSIF2.SSIFRDR) +#define SSITDMR_2 (SSIF2.SSITDMR) +#define SSIFCCR_2 (SSIF2.SSIFCCR) +#define SSIFCMR_2 (SSIF2.SSIFCMR) +#define SSIFCSR_2 (SSIF2.SSIFCSR) +#define SSICR_3 (SSIF3.SSICR) +#define SSISR_3 (SSIF3.SSISR) +#define SSIFCR_3 (SSIF3.SSIFCR) +#define SSIFSR_3 (SSIF3.SSIFSR) +#define SSIFTDR_3 (SSIF3.SSIFTDR) +#define SSIFRDR_3 (SSIF3.SSIFRDR) +#define SSITDMR_3 (SSIF3.SSITDMR) +#define SSIFCCR_3 (SSIF3.SSIFCCR) +#define SSIFCMR_3 (SSIF3.SSIFCMR) +#define SSIFCSR_3 (SSIF3.SSIFCSR) +#define SSICR_4 (SSIF4.SSICR) +#define SSISR_4 (SSIF4.SSISR) +#define SSIFCR_4 (SSIF4.SSIFCR) +#define SSIFSR_4 (SSIF4.SSIFSR) +#define SSIFTDR_4 (SSIF4.SSIFTDR) +#define SSIFRDR_4 (SSIF4.SSIFRDR) +#define SSITDMR_4 (SSIF4.SSITDMR) +#define SSIFCCR_4 (SSIF4.SSIFCCR) +#define SSIFCMR_4 (SSIF4.SSIFCMR) +#define SSIFCSR_4 (SSIF4.SSIFCSR) +#define SSICR_5 (SSIF5.SSICR) +#define SSISR_5 (SSIF5.SSISR) +#define SSIFCR_5 (SSIF5.SSIFCR) +#define SSIFSR_5 (SSIF5.SSIFSR) +#define SSIFTDR_5 (SSIF5.SSIFTDR) +#define SSIFRDR_5 (SSIF5.SSIFRDR) +#define SSITDMR_5 (SSIF5.SSITDMR) +#define SSIFCCR_5 (SSIF5.SSIFCCR) +#define SSIFCMR_5 (SSIF5.SSIFCMR) +#define SSIFCSR_5 (SSIF5.SSIFCSR) + + +typedef struct st_ssif +{ + /* SSIF */ + volatile uint32_t SSICR; /* SSICR */ + volatile uint32_t SSISR; /* SSISR */ + volatile uint8_t dummy1[8]; /* */ + volatile uint32_t SSIFCR; /* SSIFCR */ + volatile uint32_t SSIFSR; /* SSIFSR */ + volatile uint32_t SSIFTDR; /* SSIFTDR */ + volatile uint32_t SSIFRDR; /* SSIFRDR */ + volatile uint32_t SSITDMR; /* SSITDMR */ + volatile uint32_t SSIFCCR; /* SSIFCCR */ + volatile uint32_t SSIFCMR; /* SSIFCMR */ + volatile uint32_t SSIFCSR; /* SSIFCSR */ +} r_io_ssif_t; + + +/* Channel array defines of SSIF (2)*/ +#ifdef DECLARE_SSIF_CHANNELS +volatile struct st_ssif* SSIF[ SSIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SSIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SSIF_CHANNELS */ +/* End of channel array defines of SSIF (2)*/ -#define SSICR_0 SSIF0.SSICR -#define SSISR_0 SSIF0.SSISR -#define SSIFCR_0 SSIF0.SSIFCR -#define SSIFSR_0 SSIF0.SSIFSR -#define SSIFTDR_0 SSIF0.SSIFTDR -#define SSIFRDR_0 SSIF0.SSIFRDR -#define SSITDMR_0 SSIF0.SSITDMR -#define SSIFCCR_0 SSIF0.SSIFCCR -#define SSIFCMR_0 SSIF0.SSIFCMR -#define SSIFCSR_0 SSIF0.SSIFCSR -#define SSICR_1 SSIF1.SSICR -#define SSISR_1 SSIF1.SSISR -#define SSIFCR_1 SSIF1.SSIFCR -#define SSIFSR_1 SSIF1.SSIFSR -#define SSIFTDR_1 SSIF1.SSIFTDR -#define SSIFRDR_1 SSIF1.SSIFRDR -#define SSITDMR_1 SSIF1.SSITDMR -#define SSIFCCR_1 SSIF1.SSIFCCR -#define SSIFCMR_1 SSIF1.SSIFCMR -#define SSIFCSR_1 SSIF1.SSIFCSR -#define SSICR_2 SSIF2.SSICR -#define SSISR_2 SSIF2.SSISR -#define SSIFCR_2 SSIF2.SSIFCR -#define SSIFSR_2 SSIF2.SSIFSR -#define SSIFTDR_2 SSIF2.SSIFTDR -#define SSIFRDR_2 SSIF2.SSIFRDR -#define SSITDMR_2 SSIF2.SSITDMR -#define SSIFCCR_2 SSIF2.SSIFCCR -#define SSIFCMR_2 SSIF2.SSIFCMR -#define SSIFCSR_2 SSIF2.SSIFCSR -#define SSICR_3 SSIF3.SSICR -#define SSISR_3 SSIF3.SSISR -#define SSIFCR_3 SSIF3.SSIFCR -#define SSIFSR_3 SSIF3.SSIFSR -#define SSIFTDR_3 SSIF3.SSIFTDR -#define SSIFRDR_3 SSIF3.SSIFRDR -#define SSITDMR_3 SSIF3.SSITDMR -#define SSIFCCR_3 SSIF3.SSIFCCR -#define SSIFCMR_3 SSIF3.SSIFCMR -#define SSIFCSR_3 SSIF3.SSIFCSR -#define SSICR_4 SSIF4.SSICR -#define SSISR_4 SSIF4.SSISR -#define SSIFCR_4 SSIF4.SSIFCR -#define SSIFSR_4 SSIF4.SSIFSR -#define SSIFTDR_4 SSIF4.SSIFTDR -#define SSIFRDR_4 SSIF4.SSIFRDR -#define SSITDMR_4 SSIF4.SSITDMR -#define SSIFCCR_4 SSIF4.SSIFCCR -#define SSIFCMR_4 SSIF4.SSIFCMR -#define SSIFCSR_4 SSIF4.SSIFCSR -#define SSICR_5 SSIF5.SSICR -#define SSISR_5 SSIF5.SSISR -#define SSIFCR_5 SSIF5.SSIFCR -#define SSIFSR_5 SSIF5.SSIFSR -#define SSIFTDR_5 SSIF5.SSIFTDR -#define SSIFRDR_5 SSIF5.SSIFRDR -#define SSITDMR_5 SSIF5.SSITDMR -#define SSIFCCR_5 SSIF5.SSIFCCR -#define SSIFCMR_5 SSIF5.SSIFCMR -#define SSIFCSR_5 SSIF5.SSIFCSR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h similarity index 58% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h index 97e15c8455b..a8e60a2647b 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h @@ -18,20 +18,365 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : usb20_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef USB20_IODEFINE_H #define USB20_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_usb20 -{ /* USB20 */ +#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ +#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ + + +/* Start of channel array defines of USB20 */ + +/* Channel array defines of USB20 */ +/*(Sample) value = USB20[ channel ]->SYSCFG0; */ +#define USB20_COUNT (2) +#define USB20_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &USB200, &USB201 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of USB20_FROM_D0FIFOB0 */ +/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ +#define USB20_FROM_D0FIFOB0_COUNT (2) +#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ + &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ +#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ +#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ +#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ + + + + +/* Channel array defines of USB20_FROM_PIPE1ATRE */ +/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ +#define USB20_FROM_PIPE1ATRE_COUNT (5) +#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ + &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ +#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ +#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ +#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ +#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ +#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ +#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ +#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ +#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ +#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ + + + + +/* Channel array defines of USB20_FROM_D0FIFOSEL */ +/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ +#define USB20_FROM_D0FIFOSEL_COUNT (2) +#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ + &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ +#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ +#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ +#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ + + +/* End of channel array defines of USB20 */ + + +#define SYSCFG0_0 (USB200.SYSCFG0) +#define BUSWAIT_0 (USB200.BUSWAIT) +#define SYSSTS0_0 (USB200.SYSSTS0) +#define DVSTCTR0_0 (USB200.DVSTCTR0) +#define TESTMODE_0 (USB200.TESTMODE) +#define D0FBCFG_0 (USB200.D0FBCFG) +#define D1FBCFG_0 (USB200.D1FBCFG) +#define CFIFO_0 (USB200.CFIFO.UINT32) +#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L]) +#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H]) +#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_0 (USB200.D0FIFO.UINT32) +#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_0 (USB200.D1FIFO.UINT32) +#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_0 (USB200.CFIFOSEL) +#define CFIFOCTR_0 (USB200.CFIFOCTR) +#define D0FIFOSEL_0 (USB200.D0FIFOSEL) +#define D0FIFOCTR_0 (USB200.D0FIFOCTR) +#define D1FIFOSEL_0 (USB200.D1FIFOSEL) +#define D1FIFOCTR_0 (USB200.D1FIFOCTR) +#define INTENB0_0 (USB200.INTENB0) +#define INTENB1_0 (USB200.INTENB1) +#define BRDYENB_0 (USB200.BRDYENB) +#define NRDYENB_0 (USB200.NRDYENB) +#define BEMPENB_0 (USB200.BEMPENB) +#define SOFCFG_0 (USB200.SOFCFG) +#define INTSTS0_0 (USB200.INTSTS0) +#define INTSTS1_0 (USB200.INTSTS1) +#define BRDYSTS_0 (USB200.BRDYSTS) +#define NRDYSTS_0 (USB200.NRDYSTS) +#define BEMPSTS_0 (USB200.BEMPSTS) +#define FRMNUM_0 (USB200.FRMNUM) +#define UFRMNUM_0 (USB200.UFRMNUM) +#define USBADDR_0 (USB200.USBADDR) +#define USBREQ_0 (USB200.USBREQ) +#define USBVAL_0 (USB200.USBVAL) +#define USBINDX_0 (USB200.USBINDX) +#define USBLENG_0 (USB200.USBLENG) +#define DCPCFG_0 (USB200.DCPCFG) +#define DCPMAXP_0 (USB200.DCPMAXP) +#define DCPCTR_0 (USB200.DCPCTR) +#define PIPESEL_0 (USB200.PIPESEL) +#define PIPECFG_0 (USB200.PIPECFG) +#define PIPEBUF_0 (USB200.PIPEBUF) +#define PIPEMAXP_0 (USB200.PIPEMAXP) +#define PIPEPERI_0 (USB200.PIPEPERI) +#define PIPE1CTR_0 (USB200.PIPE1CTR) +#define PIPE2CTR_0 (USB200.PIPE2CTR) +#define PIPE3CTR_0 (USB200.PIPE3CTR) +#define PIPE4CTR_0 (USB200.PIPE4CTR) +#define PIPE5CTR_0 (USB200.PIPE5CTR) +#define PIPE6CTR_0 (USB200.PIPE6CTR) +#define PIPE7CTR_0 (USB200.PIPE7CTR) +#define PIPE8CTR_0 (USB200.PIPE8CTR) +#define PIPE9CTR_0 (USB200.PIPE9CTR) +#define PIPEACTR_0 (USB200.PIPEACTR) +#define PIPEBCTR_0 (USB200.PIPEBCTR) +#define PIPECCTR_0 (USB200.PIPECCTR) +#define PIPEDCTR_0 (USB200.PIPEDCTR) +#define PIPEECTR_0 (USB200.PIPEECTR) +#define PIPEFCTR_0 (USB200.PIPEFCTR) +#define PIPE1TRE_0 (USB200.PIPE1TRE) +#define PIPE1TRN_0 (USB200.PIPE1TRN) +#define PIPE2TRE_0 (USB200.PIPE2TRE) +#define PIPE2TRN_0 (USB200.PIPE2TRN) +#define PIPE3TRE_0 (USB200.PIPE3TRE) +#define PIPE3TRN_0 (USB200.PIPE3TRN) +#define PIPE4TRE_0 (USB200.PIPE4TRE) +#define PIPE4TRN_0 (USB200.PIPE4TRN) +#define PIPE5TRE_0 (USB200.PIPE5TRE) +#define PIPE5TRN_0 (USB200.PIPE5TRN) +#define PIPEBTRE_0 (USB200.PIPEBTRE) +#define PIPEBTRN_0 (USB200.PIPEBTRN) +#define PIPECTRE_0 (USB200.PIPECTRE) +#define PIPECTRN_0 (USB200.PIPECTRN) +#define PIPEDTRE_0 (USB200.PIPEDTRE) +#define PIPEDTRN_0 (USB200.PIPEDTRN) +#define PIPEETRE_0 (USB200.PIPEETRE) +#define PIPEETRN_0 (USB200.PIPEETRN) +#define PIPEFTRE_0 (USB200.PIPEFTRE) +#define PIPEFTRN_0 (USB200.PIPEFTRN) +#define PIPE9TRE_0 (USB200.PIPE9TRE) +#define PIPE9TRN_0 (USB200.PIPE9TRN) +#define PIPEATRE_0 (USB200.PIPEATRE) +#define PIPEATRN_0 (USB200.PIPEATRN) +#define DEVADD0_0 (USB200.DEVADD0) +#define DEVADD1_0 (USB200.DEVADD1) +#define DEVADD2_0 (USB200.DEVADD2) +#define DEVADD3_0 (USB200.DEVADD3) +#define DEVADD4_0 (USB200.DEVADD4) +#define DEVADD5_0 (USB200.DEVADD5) +#define DEVADD6_0 (USB200.DEVADD6) +#define DEVADD7_0 (USB200.DEVADD7) +#define DEVADD8_0 (USB200.DEVADD8) +#define DEVADD9_0 (USB200.DEVADD9) +#define DEVADDA_0 (USB200.DEVADDA) +#define SUSPMODE_0 (USB200.SUSPMODE) +#define D0FIFOB0_0 (USB200.D0FIFOB0) +#define D0FIFOB1_0 (USB200.D0FIFOB1) +#define D0FIFOB2_0 (USB200.D0FIFOB2) +#define D0FIFOB3_0 (USB200.D0FIFOB3) +#define D0FIFOB4_0 (USB200.D0FIFOB4) +#define D0FIFOB5_0 (USB200.D0FIFOB5) +#define D0FIFOB6_0 (USB200.D0FIFOB6) +#define D0FIFOB7_0 (USB200.D0FIFOB7) +#define D1FIFOB0_0 (USB200.D1FIFOB0) +#define D1FIFOB1_0 (USB200.D1FIFOB1) +#define D1FIFOB2_0 (USB200.D1FIFOB2) +#define D1FIFOB3_0 (USB200.D1FIFOB3) +#define D1FIFOB4_0 (USB200.D1FIFOB4) +#define D1FIFOB5_0 (USB200.D1FIFOB5) +#define D1FIFOB6_0 (USB200.D1FIFOB6) +#define D1FIFOB7_0 (USB200.D1FIFOB7) +#define SYSCFG0_1 (USB201.SYSCFG0) +#define BUSWAIT_1 (USB201.BUSWAIT) +#define SYSSTS0_1 (USB201.SYSSTS0) +#define DVSTCTR0_1 (USB201.DVSTCTR0) +#define TESTMODE_1 (USB201.TESTMODE) +#define D0FBCFG_1 (USB201.D0FBCFG) +#define D1FBCFG_1 (USB201.D1FBCFG) +#define CFIFO_1 (USB201.CFIFO.UINT32) +#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L]) +#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H]) +#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_1 (USB201.D0FIFO.UINT32) +#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_1 (USB201.D1FIFO.UINT32) +#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_1 (USB201.CFIFOSEL) +#define CFIFOCTR_1 (USB201.CFIFOCTR) +#define D0FIFOSEL_1 (USB201.D0FIFOSEL) +#define D0FIFOCTR_1 (USB201.D0FIFOCTR) +#define D1FIFOSEL_1 (USB201.D1FIFOSEL) +#define D1FIFOCTR_1 (USB201.D1FIFOCTR) +#define INTENB0_1 (USB201.INTENB0) +#define INTENB1_1 (USB201.INTENB1) +#define BRDYENB_1 (USB201.BRDYENB) +#define NRDYENB_1 (USB201.NRDYENB) +#define BEMPENB_1 (USB201.BEMPENB) +#define SOFCFG_1 (USB201.SOFCFG) +#define INTSTS0_1 (USB201.INTSTS0) +#define INTSTS1_1 (USB201.INTSTS1) +#define BRDYSTS_1 (USB201.BRDYSTS) +#define NRDYSTS_1 (USB201.NRDYSTS) +#define BEMPSTS_1 (USB201.BEMPSTS) +#define FRMNUM_1 (USB201.FRMNUM) +#define UFRMNUM_1 (USB201.UFRMNUM) +#define USBADDR_1 (USB201.USBADDR) +#define USBREQ_1 (USB201.USBREQ) +#define USBVAL_1 (USB201.USBVAL) +#define USBINDX_1 (USB201.USBINDX) +#define USBLENG_1 (USB201.USBLENG) +#define DCPCFG_1 (USB201.DCPCFG) +#define DCPMAXP_1 (USB201.DCPMAXP) +#define DCPCTR_1 (USB201.DCPCTR) +#define PIPESEL_1 (USB201.PIPESEL) +#define PIPECFG_1 (USB201.PIPECFG) +#define PIPEBUF_1 (USB201.PIPEBUF) +#define PIPEMAXP_1 (USB201.PIPEMAXP) +#define PIPEPERI_1 (USB201.PIPEPERI) +#define PIPE1CTR_1 (USB201.PIPE1CTR) +#define PIPE2CTR_1 (USB201.PIPE2CTR) +#define PIPE3CTR_1 (USB201.PIPE3CTR) +#define PIPE4CTR_1 (USB201.PIPE4CTR) +#define PIPE5CTR_1 (USB201.PIPE5CTR) +#define PIPE6CTR_1 (USB201.PIPE6CTR) +#define PIPE7CTR_1 (USB201.PIPE7CTR) +#define PIPE8CTR_1 (USB201.PIPE8CTR) +#define PIPE9CTR_1 (USB201.PIPE9CTR) +#define PIPEACTR_1 (USB201.PIPEACTR) +#define PIPEBCTR_1 (USB201.PIPEBCTR) +#define PIPECCTR_1 (USB201.PIPECCTR) +#define PIPEDCTR_1 (USB201.PIPEDCTR) +#define PIPEECTR_1 (USB201.PIPEECTR) +#define PIPEFCTR_1 (USB201.PIPEFCTR) +#define PIPE1TRE_1 (USB201.PIPE1TRE) +#define PIPE1TRN_1 (USB201.PIPE1TRN) +#define PIPE2TRE_1 (USB201.PIPE2TRE) +#define PIPE2TRN_1 (USB201.PIPE2TRN) +#define PIPE3TRE_1 (USB201.PIPE3TRE) +#define PIPE3TRN_1 (USB201.PIPE3TRN) +#define PIPE4TRE_1 (USB201.PIPE4TRE) +#define PIPE4TRN_1 (USB201.PIPE4TRN) +#define PIPE5TRE_1 (USB201.PIPE5TRE) +#define PIPE5TRN_1 (USB201.PIPE5TRN) +#define PIPEBTRE_1 (USB201.PIPEBTRE) +#define PIPEBTRN_1 (USB201.PIPEBTRN) +#define PIPECTRE_1 (USB201.PIPECTRE) +#define PIPECTRN_1 (USB201.PIPECTRN) +#define PIPEDTRE_1 (USB201.PIPEDTRE) +#define PIPEDTRN_1 (USB201.PIPEDTRN) +#define PIPEETRE_1 (USB201.PIPEETRE) +#define PIPEETRN_1 (USB201.PIPEETRN) +#define PIPEFTRE_1 (USB201.PIPEFTRE) +#define PIPEFTRN_1 (USB201.PIPEFTRN) +#define PIPE9TRE_1 (USB201.PIPE9TRE) +#define PIPE9TRN_1 (USB201.PIPE9TRN) +#define PIPEATRE_1 (USB201.PIPEATRE) +#define PIPEATRN_1 (USB201.PIPEATRN) +#define DEVADD0_1 (USB201.DEVADD0) +#define DEVADD1_1 (USB201.DEVADD1) +#define DEVADD2_1 (USB201.DEVADD2) +#define DEVADD3_1 (USB201.DEVADD3) +#define DEVADD4_1 (USB201.DEVADD4) +#define DEVADD5_1 (USB201.DEVADD5) +#define DEVADD6_1 (USB201.DEVADD6) +#define DEVADD7_1 (USB201.DEVADD7) +#define DEVADD8_1 (USB201.DEVADD8) +#define DEVADD9_1 (USB201.DEVADD9) +#define DEVADDA_1 (USB201.DEVADDA) +#define SUSPMODE_1 (USB201.SUSPMODE) +#define D0FIFOB0_1 (USB201.D0FIFOB0) +#define D0FIFOB1_1 (USB201.D0FIFOB1) +#define D0FIFOB2_1 (USB201.D0FIFOB2) +#define D0FIFOB3_1 (USB201.D0FIFOB3) +#define D0FIFOB4_1 (USB201.D0FIFOB4) +#define D0FIFOB5_1 (USB201.D0FIFOB5) +#define D0FIFOB6_1 (USB201.D0FIFOB6) +#define D0FIFOB7_1 (USB201.D0FIFOB7) +#define D1FIFOB0_1 (USB201.D1FIFOB0) +#define D1FIFOB1_1 (USB201.D1FIFOB1) +#define D1FIFOB2_1 (USB201.D1FIFOB2) +#define D1FIFOB3_1 (USB201.D1FIFOB3) +#define D1FIFOB4_1 (USB201.D1FIFOB4) +#define D1FIFOB5_1 (USB201.D1FIFOB5) +#define D1FIFOB6_1 (USB201.D1FIFOB6) +#define D1FIFOB7_1 (USB201.D1FIFOB7) + +#define USB20_D0FBCFG_COUNT (2) +#define USB20_D0FIFO_COUNT (2) +#define USB20_INTENB0_COUNT (2) +#define USB20_INTSTS0_COUNT (2) +#define USB20_PIPE1CTR_COUNT (0xF) +#define USB20_DEVADD0_COUNT (0xB) +#define USB20_D0FIFOB0_COUNT (0x8) + + +typedef struct st_usb20 +{ + /* USB20 */ volatile uint16_t SYSCFG0; /* SYSCFG0 */ volatile uint16_t BUSWAIT; /* BUSWAIT */ volatile uint16_t SYSSTS0; /* SYSSTS0 */ @@ -40,26 +385,33 @@ struct st_usb20 volatile uint8_t dummy2[2]; /* */ volatile uint16_t TESTMODE; /* TESTMODE */ volatile uint8_t dummy3[2]; /* */ -#define USB20_D0FBCFG_COUNT 2 + +/* #define USB20_D0FBCFG_COUNT (2) */ volatile uint16_t D0FBCFG; /* D0FBCFG */ volatile uint16_t D1FBCFG; /* D1FBCFG */ union iodefine_reg32_t CFIFO; /* CFIFO */ -#define USB20_D0FIFO_COUNT 2 + +/* #define USB20_D0FIFO_COUNT (2) */ union iodefine_reg32_t D0FIFO; /* D0FIFO */ union iodefine_reg32_t D1FIFO; /* D1FIFO */ volatile uint16_t CFIFOSEL; /* CFIFOSEL */ volatile uint16_t CFIFOCTR; /* CFIFOCTR */ volatile uint8_t dummy4[4]; /* */ + /* start of struct st_usb20_from_d0fifosel */ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ + /* end of struct st_usb20_from_d0fifosel */ + /* start of struct st_usb20_from_d0fifosel */ volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ + /* end of struct st_usb20_from_d0fifosel */ -#define USB20_INTENB0_COUNT 2 + +/* #define USB20_INTENB0_COUNT (2) */ volatile uint16_t INTENB0; /* INTENB0 */ volatile uint16_t INTENB1; /* INTENB1 */ volatile uint8_t dummy5[2]; /* */ @@ -68,7 +420,8 @@ struct st_usb20 volatile uint16_t BEMPENB; /* BEMPENB */ volatile uint16_t SOFCFG; /* SOFCFG */ volatile uint8_t dummy6[2]; /* */ -#define USB20_INTSTS0_COUNT 2 + +/* #define USB20_INTSTS0_COUNT (2) */ volatile uint16_t INTSTS0; /* INTSTS0 */ volatile uint16_t INTSTS1; /* INTSTS1 */ volatile uint8_t dummy7[2]; /* */ @@ -93,7 +446,8 @@ struct st_usb20 volatile uint16_t PIPEBUF; /* PIPEBUF */ volatile uint16_t PIPEMAXP; /* PIPEMAXP */ volatile uint16_t PIPEPERI; /* PIPEPERI */ -#define USB20_PIPE1CTR_COUNT 0xF + +/* #define USB20_PIPE1CTR_COUNT (0xF) */ volatile uint16_t PIPE1CTR; /* PIPE1CTR */ volatile uint16_t PIPE2CTR; /* PIPE2CTR */ volatile uint16_t PIPE3CTR; /* PIPE3CTR */ @@ -110,25 +464,35 @@ struct st_usb20 volatile uint16_t PIPEECTR; /* PIPEECTR */ volatile uint16_t PIPEFCTR; /* PIPEFCTR */ volatile uint8_t dummy11[2]; /* */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE1TRE; /* PIPE1TRE */ volatile uint16_t PIPE1TRN; /* PIPE1TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE2TRE; /* PIPE2TRE */ volatile uint16_t PIPE2TRN; /* PIPE2TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE3TRE; /* PIPE3TRE */ volatile uint16_t PIPE3TRN; /* PIPE3TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE4TRE; /* PIPE4TRE */ volatile uint16_t PIPE4TRN; /* PIPE4TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE5TRE; /* PIPE5TRE */ volatile uint16_t PIPE5TRN; /* PIPE5TRN */ + /* end of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPEBTRE; /* PIPEBTRE */ volatile uint16_t PIPEBTRN; /* PIPEBTRN */ @@ -145,7 +509,8 @@ struct st_usb20 volatile uint16_t PIPEATRE; /* PIPEATRE */ volatile uint16_t PIPEATRN; /* PIPEATRN */ volatile uint8_t dummy12[16]; /* */ -#define USB20_DEVADD0_COUNT 0xB + +/* #define USB20_DEVADD0_COUNT (0xB) */ volatile uint16_t DEVADD0; /* DEVADD0 */ volatile uint16_t DEVADD1; /* DEVADD1 */ volatile uint16_t DEVADD2; /* DEVADD2 */ @@ -160,6 +525,7 @@ struct st_usb20 volatile uint8_t dummy13[28]; /* */ volatile uint16_t SUSPMODE; /* SUSPMODE */ volatile uint8_t dummy14[92]; /* */ + /* start of struct st_usb20_from_dmfifob0 */ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ @@ -169,7 +535,9 @@ struct st_usb20 volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ + /* end of struct st_usb20_from_dmfifob0 */ + /* start of struct st_usb20_from_dmfifob0 */ volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ @@ -179,27 +547,32 @@ struct st_usb20 volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ + /* end of struct st_usb20_from_dmfifob0 */ -}; +} r_io_usb20_t; -struct st_usb20_from_d0fifosel +typedef struct st_usb20_from_d0fifosel { + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ -}; +} r_io_usb20_from_d0fifosel_t; -struct st_usb20_from_pipe1tre +typedef struct st_usb20_from_pipe1tre { + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ volatile uint16_t PIPE1TRN; /* PIPE1TRN */ -}; +} r_io_usb20_from_pipe1tre_t; -struct st_usb20_from_dmfifob0 +typedef struct st_usb20_from_dmfifob0 { -#define USB20_D0FIFOB0_COUNT 0x8 + + +/* #define USB20_D0FIFOB0_COUNT (0x8) */ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ @@ -208,339 +581,42 @@ struct st_usb20_from_dmfifob0 volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ -}; - - -#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ -#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ - - -/* Start of channnel array defines of USB20 */ - -/* Channnel array defines of USB20 */ -/*(Sample) value = USB20[ channel ]->SYSCFG0; */ -#define USB20_COUNT 2 -#define USB20_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &USB200, &USB201 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channnel array defines of USB20_FROM_D0FIFOB0 */ -/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ -#define USB20_FROM_D0FIFOB0_COUNT 2 -#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ - &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ -#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ -#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ -#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ +} r_io_usb20_from_dmfifob0_t; +/* Channel array defines of USB20 (2)*/ +#ifdef DECLARE_USB20_CHANNELS +volatile struct st_usb20* USB20[ USB20_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_CHANNELS */ +#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS +volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOB0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */ -/* Channnel array defines of USB20_FROM_PIPE1ATRE */ -/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ -#define USB20_FROM_PIPE1ATRE_COUNT 5 -#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ - &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ -#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ -#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ -#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ -#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ -#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ -#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ -#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ -#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ -#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ - +#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS +volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_PIPE1ATRE_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */ +#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS +volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOSEL_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */ +/* End of channel array defines of USB20 (2)*/ -/* Channnel array defines of USB20_FROM_D0FIFOSEL */ -/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ -#define USB20_FROM_D0FIFOSEL_COUNT 2 -#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ - &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ -#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ -#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ -#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ - - -/* End of channnel array defines of USB20 */ - - -#define SYSCFG0_0 USB200.SYSCFG0 -#define BUSWAIT_0 USB200.BUSWAIT -#define SYSSTS0_0 USB200.SYSSTS0 -#define DVSTCTR0_0 USB200.DVSTCTR0 -#define TESTMODE_0 USB200.TESTMODE -#define D0FBCFG_0 USB200.D0FBCFG -#define D1FBCFG_0 USB200.D1FBCFG -#define CFIFO_0 USB200.CFIFO.UINT32 -#define CFIFO_0L USB200.CFIFO.UINT16[L] -#define CFIFO_0H USB200.CFIFO.UINT16[H] -#define CFIFO_0LL USB200.CFIFO.UINT8[LL] -#define CFIFO_0LH USB200.CFIFO.UINT8[LH] -#define CFIFO_0HL USB200.CFIFO.UINT8[HL] -#define CFIFO_0HH USB200.CFIFO.UINT8[HH] -#define D0FIFO_0 USB200.D0FIFO.UINT32 -#define D0FIFO_0L USB200.D0FIFO.UINT16[L] -#define D0FIFO_0H USB200.D0FIFO.UINT16[H] -#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL] -#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH] -#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL] -#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH] -#define D1FIFO_0 USB200.D1FIFO.UINT32 -#define D1FIFO_0L USB200.D1FIFO.UINT16[L] -#define D1FIFO_0H USB200.D1FIFO.UINT16[H] -#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL] -#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH] -#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL] -#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH] -#define CFIFOSEL_0 USB200.CFIFOSEL -#define CFIFOCTR_0 USB200.CFIFOCTR -#define D0FIFOSEL_0 USB200.D0FIFOSEL -#define D0FIFOCTR_0 USB200.D0FIFOCTR -#define D1FIFOSEL_0 USB200.D1FIFOSEL -#define D1FIFOCTR_0 USB200.D1FIFOCTR -#define INTENB0_0 USB200.INTENB0 -#define INTENB1_0 USB200.INTENB1 -#define BRDYENB_0 USB200.BRDYENB -#define NRDYENB_0 USB200.NRDYENB -#define BEMPENB_0 USB200.BEMPENB -#define SOFCFG_0 USB200.SOFCFG -#define INTSTS0_0 USB200.INTSTS0 -#define INTSTS1_0 USB200.INTSTS1 -#define BRDYSTS_0 USB200.BRDYSTS -#define NRDYSTS_0 USB200.NRDYSTS -#define BEMPSTS_0 USB200.BEMPSTS -#define FRMNUM_0 USB200.FRMNUM -#define UFRMNUM_0 USB200.UFRMNUM -#define USBADDR_0 USB200.USBADDR -#define USBREQ_0 USB200.USBREQ -#define USBVAL_0 USB200.USBVAL -#define USBINDX_0 USB200.USBINDX -#define USBLENG_0 USB200.USBLENG -#define DCPCFG_0 USB200.DCPCFG -#define DCPMAXP_0 USB200.DCPMAXP -#define DCPCTR_0 USB200.DCPCTR -#define PIPESEL_0 USB200.PIPESEL -#define PIPECFG_0 USB200.PIPECFG -#define PIPEBUF_0 USB200.PIPEBUF -#define PIPEMAXP_0 USB200.PIPEMAXP -#define PIPEPERI_0 USB200.PIPEPERI -#define PIPE1CTR_0 USB200.PIPE1CTR -#define PIPE2CTR_0 USB200.PIPE2CTR -#define PIPE3CTR_0 USB200.PIPE3CTR -#define PIPE4CTR_0 USB200.PIPE4CTR -#define PIPE5CTR_0 USB200.PIPE5CTR -#define PIPE6CTR_0 USB200.PIPE6CTR -#define PIPE7CTR_0 USB200.PIPE7CTR -#define PIPE8CTR_0 USB200.PIPE8CTR -#define PIPE9CTR_0 USB200.PIPE9CTR -#define PIPEACTR_0 USB200.PIPEACTR -#define PIPEBCTR_0 USB200.PIPEBCTR -#define PIPECCTR_0 USB200.PIPECCTR -#define PIPEDCTR_0 USB200.PIPEDCTR -#define PIPEECTR_0 USB200.PIPEECTR -#define PIPEFCTR_0 USB200.PIPEFCTR -#define PIPE1TRE_0 USB200.PIPE1TRE -#define PIPE1TRN_0 USB200.PIPE1TRN -#define PIPE2TRE_0 USB200.PIPE2TRE -#define PIPE2TRN_0 USB200.PIPE2TRN -#define PIPE3TRE_0 USB200.PIPE3TRE -#define PIPE3TRN_0 USB200.PIPE3TRN -#define PIPE4TRE_0 USB200.PIPE4TRE -#define PIPE4TRN_0 USB200.PIPE4TRN -#define PIPE5TRE_0 USB200.PIPE5TRE -#define PIPE5TRN_0 USB200.PIPE5TRN -#define PIPEBTRE_0 USB200.PIPEBTRE -#define PIPEBTRN_0 USB200.PIPEBTRN -#define PIPECTRE_0 USB200.PIPECTRE -#define PIPECTRN_0 USB200.PIPECTRN -#define PIPEDTRE_0 USB200.PIPEDTRE -#define PIPEDTRN_0 USB200.PIPEDTRN -#define PIPEETRE_0 USB200.PIPEETRE -#define PIPEETRN_0 USB200.PIPEETRN -#define PIPEFTRE_0 USB200.PIPEFTRE -#define PIPEFTRN_0 USB200.PIPEFTRN -#define PIPE9TRE_0 USB200.PIPE9TRE -#define PIPE9TRN_0 USB200.PIPE9TRN -#define PIPEATRE_0 USB200.PIPEATRE -#define PIPEATRN_0 USB200.PIPEATRN -#define DEVADD0_0 USB200.DEVADD0 -#define DEVADD1_0 USB200.DEVADD1 -#define DEVADD2_0 USB200.DEVADD2 -#define DEVADD3_0 USB200.DEVADD3 -#define DEVADD4_0 USB200.DEVADD4 -#define DEVADD5_0 USB200.DEVADD5 -#define DEVADD6_0 USB200.DEVADD6 -#define DEVADD7_0 USB200.DEVADD7 -#define DEVADD8_0 USB200.DEVADD8 -#define DEVADD9_0 USB200.DEVADD9 -#define DEVADDA_0 USB200.DEVADDA -#define SUSPMODE_0 USB200.SUSPMODE -#define D0FIFOB0_0 USB200.D0FIFOB0 -#define D0FIFOB1_0 USB200.D0FIFOB1 -#define D0FIFOB2_0 USB200.D0FIFOB2 -#define D0FIFOB3_0 USB200.D0FIFOB3 -#define D0FIFOB4_0 USB200.D0FIFOB4 -#define D0FIFOB5_0 USB200.D0FIFOB5 -#define D0FIFOB6_0 USB200.D0FIFOB6 -#define D0FIFOB7_0 USB200.D0FIFOB7 -#define D1FIFOB0_0 USB200.D1FIFOB0 -#define D1FIFOB1_0 USB200.D1FIFOB1 -#define D1FIFOB2_0 USB200.D1FIFOB2 -#define D1FIFOB3_0 USB200.D1FIFOB3 -#define D1FIFOB4_0 USB200.D1FIFOB4 -#define D1FIFOB5_0 USB200.D1FIFOB5 -#define D1FIFOB6_0 USB200.D1FIFOB6 -#define D1FIFOB7_0 USB200.D1FIFOB7 -#define SYSCFG0_1 USB201.SYSCFG0 -#define BUSWAIT_1 USB201.BUSWAIT -#define SYSSTS0_1 USB201.SYSSTS0 -#define DVSTCTR0_1 USB201.DVSTCTR0 -#define TESTMODE_1 USB201.TESTMODE -#define D0FBCFG_1 USB201.D0FBCFG -#define D1FBCFG_1 USB201.D1FBCFG -#define CFIFO_1 USB201.CFIFO.UINT32 -#define CFIFO_1L USB201.CFIFO.UINT16[L] -#define CFIFO_1H USB201.CFIFO.UINT16[H] -#define CFIFO_1LL USB201.CFIFO.UINT8[LL] -#define CFIFO_1LH USB201.CFIFO.UINT8[LH] -#define CFIFO_1HL USB201.CFIFO.UINT8[HL] -#define CFIFO_1HH USB201.CFIFO.UINT8[HH] -#define D0FIFO_1 USB201.D0FIFO.UINT32 -#define D0FIFO_1L USB201.D0FIFO.UINT16[L] -#define D0FIFO_1H USB201.D0FIFO.UINT16[H] -#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL] -#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH] -#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL] -#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH] -#define D1FIFO_1 USB201.D1FIFO.UINT32 -#define D1FIFO_1L USB201.D1FIFO.UINT16[L] -#define D1FIFO_1H USB201.D1FIFO.UINT16[H] -#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL] -#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH] -#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL] -#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH] -#define CFIFOSEL_1 USB201.CFIFOSEL -#define CFIFOCTR_1 USB201.CFIFOCTR -#define D0FIFOSEL_1 USB201.D0FIFOSEL -#define D0FIFOCTR_1 USB201.D0FIFOCTR -#define D1FIFOSEL_1 USB201.D1FIFOSEL -#define D1FIFOCTR_1 USB201.D1FIFOCTR -#define INTENB0_1 USB201.INTENB0 -#define INTENB1_1 USB201.INTENB1 -#define BRDYENB_1 USB201.BRDYENB -#define NRDYENB_1 USB201.NRDYENB -#define BEMPENB_1 USB201.BEMPENB -#define SOFCFG_1 USB201.SOFCFG -#define INTSTS0_1 USB201.INTSTS0 -#define INTSTS1_1 USB201.INTSTS1 -#define BRDYSTS_1 USB201.BRDYSTS -#define NRDYSTS_1 USB201.NRDYSTS -#define BEMPSTS_1 USB201.BEMPSTS -#define FRMNUM_1 USB201.FRMNUM -#define UFRMNUM_1 USB201.UFRMNUM -#define USBADDR_1 USB201.USBADDR -#define USBREQ_1 USB201.USBREQ -#define USBVAL_1 USB201.USBVAL -#define USBINDX_1 USB201.USBINDX -#define USBLENG_1 USB201.USBLENG -#define DCPCFG_1 USB201.DCPCFG -#define DCPMAXP_1 USB201.DCPMAXP -#define DCPCTR_1 USB201.DCPCTR -#define PIPESEL_1 USB201.PIPESEL -#define PIPECFG_1 USB201.PIPECFG -#define PIPEBUF_1 USB201.PIPEBUF -#define PIPEMAXP_1 USB201.PIPEMAXP -#define PIPEPERI_1 USB201.PIPEPERI -#define PIPE1CTR_1 USB201.PIPE1CTR -#define PIPE2CTR_1 USB201.PIPE2CTR -#define PIPE3CTR_1 USB201.PIPE3CTR -#define PIPE4CTR_1 USB201.PIPE4CTR -#define PIPE5CTR_1 USB201.PIPE5CTR -#define PIPE6CTR_1 USB201.PIPE6CTR -#define PIPE7CTR_1 USB201.PIPE7CTR -#define PIPE8CTR_1 USB201.PIPE8CTR -#define PIPE9CTR_1 USB201.PIPE9CTR -#define PIPEACTR_1 USB201.PIPEACTR -#define PIPEBCTR_1 USB201.PIPEBCTR -#define PIPECCTR_1 USB201.PIPECCTR -#define PIPEDCTR_1 USB201.PIPEDCTR -#define PIPEECTR_1 USB201.PIPEECTR -#define PIPEFCTR_1 USB201.PIPEFCTR -#define PIPE1TRE_1 USB201.PIPE1TRE -#define PIPE1TRN_1 USB201.PIPE1TRN -#define PIPE2TRE_1 USB201.PIPE2TRE -#define PIPE2TRN_1 USB201.PIPE2TRN -#define PIPE3TRE_1 USB201.PIPE3TRE -#define PIPE3TRN_1 USB201.PIPE3TRN -#define PIPE4TRE_1 USB201.PIPE4TRE -#define PIPE4TRN_1 USB201.PIPE4TRN -#define PIPE5TRE_1 USB201.PIPE5TRE -#define PIPE5TRN_1 USB201.PIPE5TRN -#define PIPEBTRE_1 USB201.PIPEBTRE -#define PIPEBTRN_1 USB201.PIPEBTRN -#define PIPECTRE_1 USB201.PIPECTRE -#define PIPECTRN_1 USB201.PIPECTRN -#define PIPEDTRE_1 USB201.PIPEDTRE -#define PIPEDTRN_1 USB201.PIPEDTRN -#define PIPEETRE_1 USB201.PIPEETRE -#define PIPEETRN_1 USB201.PIPEETRN -#define PIPEFTRE_1 USB201.PIPEFTRE -#define PIPEFTRN_1 USB201.PIPEFTRN -#define PIPE9TRE_1 USB201.PIPE9TRE -#define PIPE9TRN_1 USB201.PIPE9TRN -#define PIPEATRE_1 USB201.PIPEATRE -#define PIPEATRN_1 USB201.PIPEATRN -#define DEVADD0_1 USB201.DEVADD0 -#define DEVADD1_1 USB201.DEVADD1 -#define DEVADD2_1 USB201.DEVADD2 -#define DEVADD3_1 USB201.DEVADD3 -#define DEVADD4_1 USB201.DEVADD4 -#define DEVADD5_1 USB201.DEVADD5 -#define DEVADD6_1 USB201.DEVADD6 -#define DEVADD7_1 USB201.DEVADD7 -#define DEVADD8_1 USB201.DEVADD8 -#define DEVADD9_1 USB201.DEVADD9 -#define DEVADDA_1 USB201.DEVADDA -#define SUSPMODE_1 USB201.SUSPMODE -#define D0FIFOB0_1 USB201.D0FIFOB0 -#define D0FIFOB1_1 USB201.D0FIFOB1 -#define D0FIFOB2_1 USB201.D0FIFOB2 -#define D0FIFOB3_1 USB201.D0FIFOB3 -#define D0FIFOB4_1 USB201.D0FIFOB4 -#define D0FIFOB5_1 USB201.D0FIFOB5 -#define D0FIFOB6_1 USB201.D0FIFOB6 -#define D0FIFOB7_1 USB201.D0FIFOB7 -#define D1FIFOB0_1 USB201.D1FIFOB0 -#define D1FIFOB1_1 USB201.D1FIFOB1 -#define D1FIFOB2_1 USB201.D1FIFOB2 -#define D1FIFOB3_1 USB201.D1FIFOB3 -#define D1FIFOB4_1 USB201.D1FIFOB4 -#define D1FIFOB5_1 USB201.D1FIFOB5 -#define D1FIFOB6_1 USB201.D1FIFOB6 -#define D1FIFOB7_1 USB201.D1FIFOB7 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h similarity index 54% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h index d20922524ee..3c962342e5a 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h @@ -18,21 +18,1004 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : vdc5_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef VDC5_IODEFINE_H #define VDC5_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_vdc5 -{ /* VDC5 */ +#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ +#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ + + +/* Start of channel array defines of VDC5 */ + +/* Channel array defines of VDC5 */ +/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ +#define VDC5_COUNT (2) +#define VDC5_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &VDC50, &VDC51 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ + &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ +#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ +#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ + &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ +#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ +#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */ +/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ +#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2) +#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ + &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ +#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ +#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ +#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ + + + + +/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ +#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ + &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ +#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ +#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ +#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ +#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ + &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ +#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ +#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ +#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ + &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ +#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ +#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ +#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ + &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ +#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ +#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ +#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ + + +/* End of channel array defines of VDC5 */ + + +#define VDC50INP_UPDATE (VDC50.INP_UPDATE) +#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) +#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) +#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) +#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) +#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) +#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) +#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) +#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) +#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) +#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) +#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) +#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) +#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) +#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) +#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG) +#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) +#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) +#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) +#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) +#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) +#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) +#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) +#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) +#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) +#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) +#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) +#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) +#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) +#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) +#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) +#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) +#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) +#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) +#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) +#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) +#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) +#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) +#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) +#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) +#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) +#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) +#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) +#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) +#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) +#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) +#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) +#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) +#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) +#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) +#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) +#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) +#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) +#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) +#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) +#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) +#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) +#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) +#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) +#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) +#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) +#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) +#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) +#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) +#define VDC50GR0_FLM1 (VDC50.GR0_FLM1) +#define VDC50GR0_FLM2 (VDC50.GR0_FLM2) +#define VDC50GR0_FLM3 (VDC50.GR0_FLM3) +#define VDC50GR0_FLM4 (VDC50.GR0_FLM4) +#define VDC50GR0_FLM5 (VDC50.GR0_FLM5) +#define VDC50GR0_FLM6 (VDC50.GR0_FLM6) +#define VDC50GR0_AB1 (VDC50.GR0_AB1) +#define VDC50GR0_AB2 (VDC50.GR0_AB2) +#define VDC50GR0_AB3 (VDC50.GR0_AB3) +#define VDC50GR0_AB7 (VDC50.GR0_AB7) +#define VDC50GR0_AB8 (VDC50.GR0_AB8) +#define VDC50GR0_AB9 (VDC50.GR0_AB9) +#define VDC50GR0_AB10 (VDC50.GR0_AB10) +#define VDC50GR0_AB11 (VDC50.GR0_AB11) +#define VDC50GR0_BASE (VDC50.GR0_BASE) +#define VDC50GR0_CLUT (VDC50.GR0_CLUT) +#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) +#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) +#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) +#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) +#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) +#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) +#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) +#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) +#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) +#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) +#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) +#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) +#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) +#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) +#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) +#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) +#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) +#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) +#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) +#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) +#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) +#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) +#define VDC50GR2_FLM1 (VDC50.GR2_FLM1) +#define VDC50GR2_FLM2 (VDC50.GR2_FLM2) +#define VDC50GR2_FLM3 (VDC50.GR2_FLM3) +#define VDC50GR2_FLM4 (VDC50.GR2_FLM4) +#define VDC50GR2_FLM5 (VDC50.GR2_FLM5) +#define VDC50GR2_FLM6 (VDC50.GR2_FLM6) +#define VDC50GR2_AB1 (VDC50.GR2_AB1) +#define VDC50GR2_AB2 (VDC50.GR2_AB2) +#define VDC50GR2_AB3 (VDC50.GR2_AB3) +#define VDC50GR2_AB4 (VDC50.GR2_AB4) +#define VDC50GR2_AB5 (VDC50.GR2_AB5) +#define VDC50GR2_AB6 (VDC50.GR2_AB6) +#define VDC50GR2_AB7 (VDC50.GR2_AB7) +#define VDC50GR2_AB8 (VDC50.GR2_AB8) +#define VDC50GR2_AB9 (VDC50.GR2_AB9) +#define VDC50GR2_AB10 (VDC50.GR2_AB10) +#define VDC50GR2_AB11 (VDC50.GR2_AB11) +#define VDC50GR2_BASE (VDC50.GR2_BASE) +#define VDC50GR2_CLUT (VDC50.GR2_CLUT) +#define VDC50GR2_MON (VDC50.GR2_MON) +#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) +#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) +#define VDC50GR3_FLM1 (VDC50.GR3_FLM1) +#define VDC50GR3_FLM2 (VDC50.GR3_FLM2) +#define VDC50GR3_FLM3 (VDC50.GR3_FLM3) +#define VDC50GR3_FLM4 (VDC50.GR3_FLM4) +#define VDC50GR3_FLM5 (VDC50.GR3_FLM5) +#define VDC50GR3_FLM6 (VDC50.GR3_FLM6) +#define VDC50GR3_AB1 (VDC50.GR3_AB1) +#define VDC50GR3_AB2 (VDC50.GR3_AB2) +#define VDC50GR3_AB3 (VDC50.GR3_AB3) +#define VDC50GR3_AB4 (VDC50.GR3_AB4) +#define VDC50GR3_AB5 (VDC50.GR3_AB5) +#define VDC50GR3_AB6 (VDC50.GR3_AB6) +#define VDC50GR3_AB7 (VDC50.GR3_AB7) +#define VDC50GR3_AB8 (VDC50.GR3_AB8) +#define VDC50GR3_AB9 (VDC50.GR3_AB9) +#define VDC50GR3_AB10 (VDC50.GR3_AB10) +#define VDC50GR3_AB11 (VDC50.GR3_AB11) +#define VDC50GR3_BASE (VDC50.GR3_BASE) +#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) +#define VDC50GR3_MON (VDC50.GR3_MON) +#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) +#define VDC50GAM_SW (VDC50.GAM_SW) +#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) +#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) +#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) +#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) +#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) +#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) +#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) +#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) +#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) +#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) +#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) +#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) +#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) +#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) +#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) +#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) +#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) +#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) +#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) +#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) +#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) +#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) +#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) +#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) +#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) +#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) +#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) +#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) +#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) +#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) +#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) +#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) +#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) +#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) +#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) +#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) +#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) +#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) +#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) +#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) +#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) +#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) +#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) +#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) +#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) +#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) +#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) +#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) +#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) +#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) +#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) +#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) +#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) +#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) +#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) +#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) +#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) +#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) +#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) +#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) +#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) +#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) +#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) +#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) +#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) +#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) +#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) +#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) +#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) +#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) +#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) +#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) +#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) +#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) +#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) +#define VDC50TCON_TIM (VDC50.TCON_TIM) +#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) +#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) +#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) +#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) +#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) +#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) +#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) +#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) +#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) +#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) +#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) +#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) +#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) +#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) +#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) +#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) +#define VDC50OUT_SET (VDC50.OUT_SET) +#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) +#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) +#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) +#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) +#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) +#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) +#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) +#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3) +#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) +#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) +#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6) +#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) +#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) +#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE) +#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1) +#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2) +#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3) +#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4) +#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5) +#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6) +#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7) +#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9) +#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0) +#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT) +#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1) +#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2) +#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3) +#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4) +#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5) +#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6) +#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7) +#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1) +#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2) +#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3) +#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4) +#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5) +#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6) +#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7) +#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8) +#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1) +#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE) +#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1) +#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2) +#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3) +#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4) +#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5) +#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6) +#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7) +#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8) +#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9) +#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10) +#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11) +#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1) +#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0) +#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1) +#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2) +#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3) +#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD) +#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT) +#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE) +#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD) +#define VDC50GR1_FLM1 (VDC50.GR1_FLM1) +#define VDC50GR1_FLM2 (VDC50.GR1_FLM2) +#define VDC50GR1_FLM3 (VDC50.GR1_FLM3) +#define VDC50GR1_FLM4 (VDC50.GR1_FLM4) +#define VDC50GR1_FLM5 (VDC50.GR1_FLM5) +#define VDC50GR1_FLM6 (VDC50.GR1_FLM6) +#define VDC50GR1_AB1 (VDC50.GR1_AB1) +#define VDC50GR1_AB2 (VDC50.GR1_AB2) +#define VDC50GR1_AB3 (VDC50.GR1_AB3) +#define VDC50GR1_AB4 (VDC50.GR1_AB4) +#define VDC50GR1_AB5 (VDC50.GR1_AB5) +#define VDC50GR1_AB6 (VDC50.GR1_AB6) +#define VDC50GR1_AB7 (VDC50.GR1_AB7) +#define VDC50GR1_AB8 (VDC50.GR1_AB8) +#define VDC50GR1_AB9 (VDC50.GR1_AB9) +#define VDC50GR1_AB10 (VDC50.GR1_AB10) +#define VDC50GR1_AB11 (VDC50.GR1_AB11) +#define VDC50GR1_BASE (VDC50.GR1_BASE) +#define VDC50GR1_CLUT (VDC50.GR1_CLUT) +#define VDC50GR1_MON (VDC50.GR1_MON) +#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE) +#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET) +#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1) +#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2) +#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3) +#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1) +#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2) +#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3) +#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4) +#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5) +#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6) +#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1) +#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2) +#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE) +#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0) +#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1) +#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0) +#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1) +#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0) +#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1) +#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) +#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) +#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2) +#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3) +#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4) +#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5) +#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6) +#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7) +#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE) +#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON) +#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE) +#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1) +#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2) +#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3) +#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4) +#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5) +#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6) +#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7) +#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1) +#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2) +#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3) +#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7) +#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1) +#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2) +#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3) +#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8) +#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1) +#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE) +#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1) +#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2) +#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3) +#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4) +#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5) +#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6) +#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7) +#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE) +#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD) +#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1) +#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2) +#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3) +#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4) +#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5) +#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6) +#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1) +#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2) +#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3) +#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7) +#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8) +#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9) +#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10) +#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11) +#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE) +#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT) +#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON) +#define VDC51INP_UPDATE (VDC51.INP_UPDATE) +#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT) +#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT) +#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ) +#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ) +#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE) +#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0) +#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1) +#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE) +#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0) +#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1) +#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0) +#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1) +#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0) +#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1) +#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG) +#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE) +#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1) +#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2) +#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3) +#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4) +#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5) +#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6) +#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7) +#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9) +#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0) +#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT) +#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1) +#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2) +#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3) +#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4) +#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5) +#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6) +#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7) +#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1) +#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2) +#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3) +#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4) +#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5) +#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6) +#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7) +#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8) +#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1) +#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE) +#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1) +#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2) +#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3) +#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4) +#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5) +#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6) +#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7) +#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8) +#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9) +#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10) +#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11) +#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1) +#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0) +#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1) +#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2) +#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3) +#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD) +#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT) +#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE) +#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD) +#define VDC51GR0_FLM1 (VDC51.GR0_FLM1) +#define VDC51GR0_FLM2 (VDC51.GR0_FLM2) +#define VDC51GR0_FLM3 (VDC51.GR0_FLM3) +#define VDC51GR0_FLM4 (VDC51.GR0_FLM4) +#define VDC51GR0_FLM5 (VDC51.GR0_FLM5) +#define VDC51GR0_FLM6 (VDC51.GR0_FLM6) +#define VDC51GR0_AB1 (VDC51.GR0_AB1) +#define VDC51GR0_AB2 (VDC51.GR0_AB2) +#define VDC51GR0_AB3 (VDC51.GR0_AB3) +#define VDC51GR0_AB7 (VDC51.GR0_AB7) +#define VDC51GR0_AB8 (VDC51.GR0_AB8) +#define VDC51GR0_AB9 (VDC51.GR0_AB9) +#define VDC51GR0_AB10 (VDC51.GR0_AB10) +#define VDC51GR0_AB11 (VDC51.GR0_AB11) +#define VDC51GR0_BASE (VDC51.GR0_BASE) +#define VDC51GR0_CLUT (VDC51.GR0_CLUT) +#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE) +#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET) +#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1) +#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2) +#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3) +#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1) +#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2) +#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3) +#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4) +#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5) +#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6) +#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1) +#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2) +#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE) +#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0) +#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1) +#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0) +#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1) +#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0) +#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1) +#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE) +#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD) +#define VDC51GR2_FLM1 (VDC51.GR2_FLM1) +#define VDC51GR2_FLM2 (VDC51.GR2_FLM2) +#define VDC51GR2_FLM3 (VDC51.GR2_FLM3) +#define VDC51GR2_FLM4 (VDC51.GR2_FLM4) +#define VDC51GR2_FLM5 (VDC51.GR2_FLM5) +#define VDC51GR2_FLM6 (VDC51.GR2_FLM6) +#define VDC51GR2_AB1 (VDC51.GR2_AB1) +#define VDC51GR2_AB2 (VDC51.GR2_AB2) +#define VDC51GR2_AB3 (VDC51.GR2_AB3) +#define VDC51GR2_AB4 (VDC51.GR2_AB4) +#define VDC51GR2_AB5 (VDC51.GR2_AB5) +#define VDC51GR2_AB6 (VDC51.GR2_AB6) +#define VDC51GR2_AB7 (VDC51.GR2_AB7) +#define VDC51GR2_AB8 (VDC51.GR2_AB8) +#define VDC51GR2_AB9 (VDC51.GR2_AB9) +#define VDC51GR2_AB10 (VDC51.GR2_AB10) +#define VDC51GR2_AB11 (VDC51.GR2_AB11) +#define VDC51GR2_BASE (VDC51.GR2_BASE) +#define VDC51GR2_CLUT (VDC51.GR2_CLUT) +#define VDC51GR2_MON (VDC51.GR2_MON) +#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE) +#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD) +#define VDC51GR3_FLM1 (VDC51.GR3_FLM1) +#define VDC51GR3_FLM2 (VDC51.GR3_FLM2) +#define VDC51GR3_FLM3 (VDC51.GR3_FLM3) +#define VDC51GR3_FLM4 (VDC51.GR3_FLM4) +#define VDC51GR3_FLM5 (VDC51.GR3_FLM5) +#define VDC51GR3_FLM6 (VDC51.GR3_FLM6) +#define VDC51GR3_AB1 (VDC51.GR3_AB1) +#define VDC51GR3_AB2 (VDC51.GR3_AB2) +#define VDC51GR3_AB3 (VDC51.GR3_AB3) +#define VDC51GR3_AB4 (VDC51.GR3_AB4) +#define VDC51GR3_AB5 (VDC51.GR3_AB5) +#define VDC51GR3_AB6 (VDC51.GR3_AB6) +#define VDC51GR3_AB7 (VDC51.GR3_AB7) +#define VDC51GR3_AB8 (VDC51.GR3_AB8) +#define VDC51GR3_AB9 (VDC51.GR3_AB9) +#define VDC51GR3_AB10 (VDC51.GR3_AB10) +#define VDC51GR3_AB11 (VDC51.GR3_AB11) +#define VDC51GR3_BASE (VDC51.GR3_BASE) +#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT) +#define VDC51GR3_MON (VDC51.GR3_MON) +#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE) +#define VDC51GAM_SW (VDC51.GAM_SW) +#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1) +#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2) +#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3) +#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4) +#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5) +#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6) +#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7) +#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8) +#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9) +#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10) +#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11) +#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12) +#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13) +#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14) +#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15) +#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16) +#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1) +#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2) +#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3) +#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4) +#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5) +#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6) +#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7) +#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8) +#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE) +#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1) +#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2) +#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3) +#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4) +#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5) +#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6) +#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7) +#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8) +#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9) +#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10) +#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11) +#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12) +#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13) +#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14) +#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15) +#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16) +#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1) +#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2) +#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3) +#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4) +#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5) +#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6) +#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7) +#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8) +#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE) +#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1) +#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2) +#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3) +#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4) +#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5) +#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6) +#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7) +#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8) +#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9) +#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10) +#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11) +#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12) +#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13) +#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14) +#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15) +#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16) +#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1) +#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2) +#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3) +#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4) +#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5) +#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6) +#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7) +#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8) +#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE) +#define VDC51TCON_TIM (VDC51.TCON_TIM) +#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1) +#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2) +#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1) +#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2) +#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1) +#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2) +#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1) +#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2) +#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1) +#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2) +#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1) +#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2) +#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1) +#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2) +#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE) +#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE) +#define VDC51OUT_SET (VDC51.OUT_SET) +#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1) +#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2) +#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST) +#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA) +#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE) +#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1) +#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2) +#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3) +#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4) +#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5) +#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6) +#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK) +#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT) +#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE) +#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1) +#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2) +#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3) +#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4) +#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5) +#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6) +#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7) +#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9) +#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0) +#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT) +#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1) +#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2) +#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3) +#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4) +#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5) +#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6) +#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7) +#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1) +#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2) +#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3) +#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4) +#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5) +#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6) +#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7) +#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8) +#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1) +#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE) +#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1) +#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2) +#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3) +#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4) +#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5) +#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6) +#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7) +#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8) +#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9) +#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10) +#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11) +#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1) +#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0) +#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1) +#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2) +#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3) +#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD) +#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT) +#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE) +#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD) +#define VDC51GR1_FLM1 (VDC51.GR1_FLM1) +#define VDC51GR1_FLM2 (VDC51.GR1_FLM2) +#define VDC51GR1_FLM3 (VDC51.GR1_FLM3) +#define VDC51GR1_FLM4 (VDC51.GR1_FLM4) +#define VDC51GR1_FLM5 (VDC51.GR1_FLM5) +#define VDC51GR1_FLM6 (VDC51.GR1_FLM6) +#define VDC51GR1_AB1 (VDC51.GR1_AB1) +#define VDC51GR1_AB2 (VDC51.GR1_AB2) +#define VDC51GR1_AB3 (VDC51.GR1_AB3) +#define VDC51GR1_AB4 (VDC51.GR1_AB4) +#define VDC51GR1_AB5 (VDC51.GR1_AB5) +#define VDC51GR1_AB6 (VDC51.GR1_AB6) +#define VDC51GR1_AB7 (VDC51.GR1_AB7) +#define VDC51GR1_AB8 (VDC51.GR1_AB8) +#define VDC51GR1_AB9 (VDC51.GR1_AB9) +#define VDC51GR1_AB10 (VDC51.GR1_AB10) +#define VDC51GR1_AB11 (VDC51.GR1_AB11) +#define VDC51GR1_BASE (VDC51.GR1_BASE) +#define VDC51GR1_CLUT (VDC51.GR1_CLUT) +#define VDC51GR1_MON (VDC51.GR1_MON) +#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE) +#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET) +#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1) +#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2) +#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3) +#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1) +#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2) +#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3) +#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4) +#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5) +#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6) +#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1) +#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2) +#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE) +#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0) +#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1) +#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0) +#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1) +#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0) +#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1) +#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE) +#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1) +#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2) +#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3) +#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4) +#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5) +#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6) +#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7) +#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE) +#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON) +#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE) +#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1) +#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2) +#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3) +#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4) +#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5) +#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6) +#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7) +#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1) +#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2) +#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3) +#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7) +#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1) +#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2) +#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3) +#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8) +#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1) +#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE) +#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1) +#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2) +#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3) +#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4) +#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5) +#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6) +#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7) +#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE) +#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD) +#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1) +#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2) +#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3) +#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4) +#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5) +#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6) +#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1) +#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2) +#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3) +#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7) +#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8) +#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9) +#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10) +#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11) +#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE) +#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT) +#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON) + +#define VDC5_IMGCNT_NR_CNT0_COUNT (2) +#define VDC5_SC0_SCL0_FRC1_COUNT (7) +#define VDC5_SC0_SCL0_DS1_COUNT (7) +#define VDC5_SC0_SCL0_US1_COUNT (8) +#define VDC5_SC0_SCL1_WR1_COUNT (4) +#define VDC5_SC0_SCL1_PBUF0_COUNT (4) +#define VDC5_GR0_FLM1_COUNT (6) +#define VDC5_GR0_AB1_COUNT (3) +#define VDC5_ADJ0_ENH_TIM1_COUNT (3) +#define VDC5_ADJ0_ENH_SHP1_COUNT (6) +#define VDC5_ADJ0_ENH_LTI1_COUNT (2) +#define VDC5_GR2_FLM1_COUNT (6) +#define VDC5_GR2_AB1_COUNT (3) +#define VDC5_GR3_FLM1_COUNT (6) +#define VDC5_GR3_AB1_COUNT (3) +#define VDC5_GAM_G_LUT1_COUNT (16) +#define VDC5_GAM_G_AREA1_COUNT (8) +#define VDC5_GAM_B_LUT1_COUNT (16) +#define VDC5_GAM_B_AREA1_COUNT (8) +#define VDC5_GAM_R_LUT1_COUNT (16) +#define VDC5_GAM_R_AREA1_COUNT (8) +#define VDC5_TCON_TIM_STVA1_COUNT (2) +#define VDC5_TCON_TIM_STVB1_COUNT (2) +#define VDC5_TCON_TIM_STH1_COUNT (2) +#define VDC5_TCON_TIM_STB1_COUNT (2) +#define VDC5_TCON_TIM_CPV1_COUNT (2) +#define VDC5_TCON_TIM_POLA1_COUNT (2) +#define VDC5_TCON_TIM_POLB1_COUNT (2) +#define VDC5_OUT_BRIGHT1_COUNT (2) +#define VDC5_SYSCNT_INT1_COUNT (6) +#define VDC5_SC1_SCL0_FRC1_COUNT (7) +#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) +#define VDC5_SC1_SC1_SCL0_US1_COUNT (8) +#define VDC5_SC1_SCL1_WR1_COUNT (4) +#define VDC5_SC1_SCL1_PBUF0_COUNT (4) +#define VDC5_GR1_FLM1_COUNT (6) +#define VDC5_GR1_AB1_COUNT (3) +#define VDC5_ADJ1_ENH_TIM1_COUNT (3) +#define VDC5_ADJ1_ENH_SHP1_COUNT (6) +#define VDC5_ADJ1_ENH_LTI1_COUNT (2) +#define VDC5_GR_VIN_AB1_COUNT (7) +#define VDC5_OIR_SCL0_FRC1_COUNT (7) +#define VDC5_OIR_SCL0_DS1_COUNT (3) +#define VDC5_OIR_SCL1_WR1_COUNT (4) +#define VDC5_GR_OIR_FLM1_COUNT (6) +#define VDC5_GR_OIR_AB1_COUNT (3) + + +typedef struct st_vdc5 +{ + /* VDC5 */ volatile uint32_t INP_UPDATE; /* INP_UPDATE */ volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ @@ -40,7 +1023,8 @@ struct st_vdc5 volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ volatile uint8_t dummy1[108]; /* */ volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ -#define VDC5_IMGCNT_NR_CNT0_COUNT 2 + +/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ volatile uint8_t dummy2[20]; /* */ @@ -54,9 +1038,11 @@ struct st_vdc5 volatile uint8_t dummy3[4]; /* */ volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ volatile uint8_t dummy4[60]; /* */ + /* start of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ -#define VDC5_SC0_SCL0_FRC1_COUNT 7 + +/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ @@ -68,7 +1054,8 @@ struct st_vdc5 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ -#define VDC5_SC0_SCL0_DS1_COUNT 7 + +/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ @@ -76,7 +1063,8 @@ struct st_vdc5 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ -#define VDC5_SC0_SCL0_US1_COUNT 8 + +/* #define VDC5_SC0_SCL0_US1_COUNT (8) */ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ @@ -90,7 +1078,8 @@ struct st_vdc5 volatile uint8_t dummy7[16]; /* */ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ volatile uint8_t dummy8[4]; /* */ -#define VDC5_SC0_SCL1_WR1_COUNT 4 + +/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ @@ -102,35 +1091,44 @@ struct st_vdc5 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ + /* end of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ + /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ -#define VDC5_SC0_SCL1_PBUF0_COUNT 4 + +/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ + /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ volatile uint8_t dummy10[44]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ -#define VDC5_GR0_FLM1_COUNT 6 + +/* #define VDC5_GR0_FLM1_COUNT (6) */ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ -#define VDC5_GR0_AB1_COUNT 3 + +/* #define VDC5_GR0_AB1_COUNT (3) */ volatile uint32_t GR0_AB1; /* GR0_AB1 */ volatile uint32_t GR0_AB2; /* GR0_AB2 */ volatile uint32_t GR0_AB3; /* GR0_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint8_t dummy11[12]; /* */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR0_AB7; /* GR0_AB7 */ volatile uint32_t GR0_AB8; /* GR0_AB8 */ @@ -138,24 +1136,29 @@ struct st_vdc5 volatile uint32_t GR0_AB10; /* GR0_AB10 */ volatile uint32_t GR0_AB11; /* GR0_AB11 */ volatile uint32_t GR0_BASE; /* GR0_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR0_CLUT; /* GR0_CLUT */ volatile uint8_t dummy12[44]; /* */ + /* start of struct st_vdc5_from_adj0_update */ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ -#define VDC5_ADJ0_ENH_TIM1_COUNT 3 + +/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ -#define VDC5_ADJ0_ENH_SHP1_COUNT 6 + +/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ -#define VDC5_ADJ0_ENH_LTI1_COUNT 2 + +/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ @@ -165,26 +1168,32 @@ struct st_vdc5 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ + /* end of struct st_vdc5_from_adj0_update */ volatile uint8_t dummy13[48]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ -#define VDC5_GR2_FLM1_COUNT 6 + +/* #define VDC5_GR2_FLM1_COUNT (6) */ volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ -#define VDC5_GR2_AB1_COUNT 3 + +/* #define VDC5_GR2_AB1_COUNT (3) */ volatile uint32_t GR2_AB1; /* GR2_AB1 */ volatile uint32_t GR2_AB2; /* GR2_AB2 */ volatile uint32_t GR2_AB3; /* GR2_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR2_AB4; /* GR2_AB4 */ volatile uint32_t GR2_AB5; /* GR2_AB5 */ volatile uint32_t GR2_AB6; /* GR2_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR2_AB7; /* GR2_AB7 */ volatile uint32_t GR2_AB8; /* GR2_AB8 */ @@ -192,28 +1201,34 @@ struct st_vdc5 volatile uint32_t GR2_AB10; /* GR2_AB10 */ volatile uint32_t GR2_AB11; /* GR2_AB11 */ volatile uint32_t GR2_BASE; /* GR2_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR2_CLUT; /* GR2_CLUT */ volatile uint32_t GR2_MON; /* GR2_MON */ volatile uint8_t dummy14[40]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ -#define VDC5_GR3_FLM1_COUNT 6 + +/* #define VDC5_GR3_FLM1_COUNT (6) */ volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ -#define VDC5_GR3_AB1_COUNT 3 + +/* #define VDC5_GR3_AB1_COUNT (3) */ volatile uint32_t GR3_AB1; /* GR3_AB1 */ volatile uint32_t GR3_AB2; /* GR3_AB2 */ volatile uint32_t GR3_AB3; /* GR3_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR3_AB4; /* GR3_AB4 */ volatile uint32_t GR3_AB5; /* GR3_AB5 */ volatile uint32_t GR3_AB6; /* GR3_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR3_AB7; /* GR3_AB7 */ volatile uint32_t GR3_AB8; /* GR3_AB8 */ @@ -221,13 +1236,15 @@ struct st_vdc5 volatile uint32_t GR3_AB10; /* GR3_AB10 */ volatile uint32_t GR3_AB11; /* GR3_AB11 */ volatile uint32_t GR3_BASE; /* GR3_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ volatile uint32_t GR3_MON; /* GR3_MON */ volatile uint8_t dummy15[40]; /* */ volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ volatile uint32_t GAM_SW; /* GAM_SW */ -#define VDC5_GAM_G_LUT1_COUNT 16 + +/* #define VDC5_GAM_G_LUT1_COUNT (16) */ volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ @@ -244,7 +1261,8 @@ struct st_vdc5 volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ -#define VDC5_GAM_G_AREA1_COUNT 8 + +/* #define VDC5_GAM_G_AREA1_COUNT (8) */ volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ @@ -256,7 +1274,8 @@ struct st_vdc5 volatile uint8_t dummy16[24]; /* */ volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ volatile uint8_t dummy17[4]; /* */ -#define VDC5_GAM_B_LUT1_COUNT 16 + +/* #define VDC5_GAM_B_LUT1_COUNT (16) */ volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ @@ -273,7 +1292,8 @@ struct st_vdc5 volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ -#define VDC5_GAM_B_AREA1_COUNT 8 + +/* #define VDC5_GAM_B_AREA1_COUNT (8) */ volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ @@ -285,7 +1305,8 @@ struct st_vdc5 volatile uint8_t dummy18[24]; /* */ volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ volatile uint8_t dummy19[4]; /* */ -#define VDC5_GAM_R_LUT1_COUNT 16 + +/* #define VDC5_GAM_R_LUT1_COUNT (16) */ volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ @@ -302,7 +1323,8 @@ struct st_vdc5 volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ -#define VDC5_GAM_R_AREA1_COUNT 8 + +/* #define VDC5_GAM_R_AREA1_COUNT (8) */ volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ @@ -314,32 +1336,40 @@ struct st_vdc5 volatile uint8_t dummy20[24]; /* */ volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ volatile uint32_t TCON_TIM; /* TCON_TIM */ -#define VDC5_TCON_TIM_STVA1_COUNT 2 + +/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ -#define VDC5_TCON_TIM_STVB1_COUNT 2 + +/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ -#define VDC5_TCON_TIM_STH1_COUNT 2 + +/* #define VDC5_TCON_TIM_STH1_COUNT (2) */ volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ -#define VDC5_TCON_TIM_STB1_COUNT 2 + +/* #define VDC5_TCON_TIM_STB1_COUNT (2) */ volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ -#define VDC5_TCON_TIM_CPV1_COUNT 2 + +/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ -#define VDC5_TCON_TIM_POLA1_COUNT 2 + +/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ -#define VDC5_TCON_TIM_POLB1_COUNT 2 + +/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ volatile uint8_t dummy21[60]; /* */ volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ volatile uint32_t OUT_SET; /* OUT_SET */ -#define VDC5_OUT_BRIGHT1_COUNT 2 + +/* #define VDC5_OUT_BRIGHT1_COUNT (2) */ volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ @@ -347,7 +1377,8 @@ struct st_vdc5 volatile uint8_t dummy22[12]; /* */ volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ volatile uint8_t dummy23[88]; /* */ -#define VDC5_SYSCNT_INT1_COUNT 6 + +/* #define VDC5_SYSCNT_INT1_COUNT (6) */ volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ @@ -357,9 +1388,11 @@ struct st_vdc5 volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ volatile uint8_t dummy24[356]; /* */ + /* start of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ -#define VDC5_SC1_SCL0_FRC1_COUNT 7 + +/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */ volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ @@ -371,7 +1404,8 @@ struct st_vdc5 volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ -#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7 + +/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */ volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ @@ -379,7 +1413,8 @@ struct st_vdc5 volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ -#define VDC5_SC1_SC1_SCL0_US1_COUNT 8 + +/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */ volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ @@ -393,7 +1428,8 @@ struct st_vdc5 volatile uint8_t dummy27[16]; /* */ volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ volatile uint8_t dummy28[4]; /* */ -#define VDC5_SC1_SCL1_WR1_COUNT 4 + +/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */ volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ @@ -405,37 +1441,46 @@ struct st_vdc5 volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ + /* end of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ + /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ -#define VDC5_SC1_SCL1_PBUF0_COUNT 4 + +/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */ volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ + /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ volatile uint8_t dummy30[44]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ -#define VDC5_GR1_FLM1_COUNT 6 + +/* #define VDC5_GR1_FLM1_COUNT (6) */ volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ -#define VDC5_GR1_AB1_COUNT 3 + +/* #define VDC5_GR1_AB1_COUNT (3) */ volatile uint32_t GR1_AB1; /* GR1_AB1 */ volatile uint32_t GR1_AB2; /* GR1_AB2 */ volatile uint32_t GR1_AB3; /* GR1_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR1_AB4; /* GR1_AB4 */ volatile uint32_t GR1_AB5; /* GR1_AB5 */ volatile uint32_t GR1_AB6; /* GR1_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR1_AB7; /* GR1_AB7 */ volatile uint32_t GR1_AB8; /* GR1_AB8 */ @@ -443,25 +1488,30 @@ struct st_vdc5 volatile uint32_t GR1_AB10; /* GR1_AB10 */ volatile uint32_t GR1_AB11; /* GR1_AB11 */ volatile uint32_t GR1_BASE; /* GR1_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR1_CLUT; /* GR1_CLUT */ volatile uint32_t GR1_MON; /* GR1_MON */ volatile uint8_t dummy31[40]; /* */ + /* start of struct st_vdc5_from_adj0_update */ volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ -#define VDC5_ADJ1_ENH_TIM1_COUNT 3 + +/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */ volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ -#define VDC5_ADJ1_ENH_SHP1_COUNT 6 + +/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */ volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ -#define VDC5_ADJ1_ENH_LTI1_COUNT 2 + +/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */ volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ @@ -471,11 +1521,13 @@ struct st_vdc5 volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ + /* end of struct st_vdc5_from_adj0_update */ volatile uint8_t dummy32[48]; /* */ volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ volatile uint8_t dummy33[28]; /* */ -#define VDC5_GR_VIN_AB1_COUNT 7 + +/* #define VDC5_GR_VIN_AB1_COUNT (7) */ volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ @@ -489,7 +1541,8 @@ struct st_vdc5 volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ volatile uint8_t dummy36[40]; /* */ volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ -#define VDC5_OIR_SCL0_FRC1_COUNT 7 + +/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */ volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ @@ -498,7 +1551,8 @@ struct st_vdc5 volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ volatile uint8_t dummy37[12]; /* */ -#define VDC5_OIR_SCL0_DS1_COUNT 3 + +/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */ volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ @@ -514,7 +1568,8 @@ struct st_vdc5 volatile uint8_t dummy41[16]; /* */ volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ volatile uint8_t dummy42[4]; /* */ -#define VDC5_OIR_SCL1_WR1_COUNT 4 + +/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */ volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ @@ -526,14 +1581,16 @@ struct st_vdc5 volatile uint8_t dummy44[88]; /* */ volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ -#define VDC5_GR_OIR_FLM1_COUNT 6 + +/* #define VDC5_GR_OIR_FLM1_COUNT (6) */ volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ -#define VDC5_GR_OIR_AB1_COUNT 3 + +/* #define VDC5_GR_OIR_AB1_COUNT (3) */ volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ @@ -546,11 +1603,12 @@ struct st_vdc5 volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ -}; +} r_io_vdc5_t; -struct st_vdc5_from_gr0_update +typedef struct st_vdc5_from_gr0_update { + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ @@ -562,22 +1620,24 @@ struct st_vdc5_from_gr0_update volatile uint32_t GR0_AB1; /* GR0_AB1 */ volatile uint32_t GR0_AB2; /* GR0_AB2 */ volatile uint32_t GR0_AB3; /* GR0_AB3 */ -}; +} r_io_vdc5_from_gr0_update_t; -struct st_vdc5_from_gr0_ab7 +typedef struct st_vdc5_from_gr0_ab7 { + volatile uint32_t GR0_AB7; /* GR0_AB7 */ volatile uint32_t GR0_AB8; /* GR0_AB8 */ volatile uint32_t GR0_AB9; /* GR0_AB9 */ volatile uint32_t GR0_AB10; /* GR0_AB10 */ volatile uint32_t GR0_AB11; /* GR0_AB11 */ volatile uint32_t GR0_BASE; /* GR0_BASE */ -}; +} r_io_vdc5_from_gr0_ab7_t; -struct st_vdc5_from_adj0_update +typedef struct st_vdc5_from_adj0_update { + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ @@ -598,11 +1658,12 @@ struct st_vdc5_from_adj0_update volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ -}; +} r_io_vdc5_from_adj0_update_t; -struct st_vdc5_from_sc0_scl0_update +typedef struct st_vdc5_from_sc0_scl0_update { + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ @@ -646,951 +1707,82 @@ struct st_vdc5_from_sc0_scl0_update volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ -}; +} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */; -struct st_vdc5_from_sc0_scl1_pbuf0 +typedef struct st_vdc5_from_sc0_scl1_pbuf0 { + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ -}; - - -#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ -#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ - - -/* Start of channnel array defines of VDC5 */ - -/* Channnel array defines of VDC5 */ -/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ -#define VDC5_COUNT 2 -#define VDC5_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &VDC50, &VDC51 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2 -#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ - &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ -#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ -#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ -#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ - - - +} r_io_vdc5_from_sc0_scl1_pbuf0_t; -/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ - &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ -#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ -#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ -#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */ -/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ -#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2 -#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ - &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ -#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ -#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ -#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ - - - - -/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ -#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ - &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ -#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ -#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ -#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ -#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ - &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ -#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ -#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ -#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ +/* Channel array defines of VDC5 (2)*/ +#ifdef DECLARE_VDC5_CHANNELS +volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC5_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC5_CHANNELS */ +#ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ +#ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ -/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2 -#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ - &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ -#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ -#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ -#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ +#ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS +volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */ +#ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */ +#ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */ +#ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ -/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ - &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ -#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ -#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ -#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ +#ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ +/* End of channel array defines of VDC5 (2)*/ -/* End of channnel array defines of VDC5 */ - - -#define VDC50INP_UPDATE VDC50.INP_UPDATE -#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT -#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT -#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ -#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ -#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE -#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0 -#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1 -#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE -#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0 -#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1 -#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0 -#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1 -#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0 -#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1 -#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG -#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE -#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1 -#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2 -#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3 -#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4 -#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5 -#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6 -#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7 -#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9 -#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0 -#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT -#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1 -#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2 -#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3 -#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4 -#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5 -#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6 -#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7 -#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1 -#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2 -#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3 -#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4 -#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5 -#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6 -#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7 -#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8 -#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1 -#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE -#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1 -#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2 -#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3 -#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4 -#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5 -#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6 -#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7 -#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8 -#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9 -#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10 -#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11 -#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1 -#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0 -#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1 -#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2 -#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3 -#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD -#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT -#define VDC50GR0_UPDATE VDC50.GR0_UPDATE -#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD -#define VDC50GR0_FLM1 VDC50.GR0_FLM1 -#define VDC50GR0_FLM2 VDC50.GR0_FLM2 -#define VDC50GR0_FLM3 VDC50.GR0_FLM3 -#define VDC50GR0_FLM4 VDC50.GR0_FLM4 -#define VDC50GR0_FLM5 VDC50.GR0_FLM5 -#define VDC50GR0_FLM6 VDC50.GR0_FLM6 -#define VDC50GR0_AB1 VDC50.GR0_AB1 -#define VDC50GR0_AB2 VDC50.GR0_AB2 -#define VDC50GR0_AB3 VDC50.GR0_AB3 -#define VDC50GR0_AB7 VDC50.GR0_AB7 -#define VDC50GR0_AB8 VDC50.GR0_AB8 -#define VDC50GR0_AB9 VDC50.GR0_AB9 -#define VDC50GR0_AB10 VDC50.GR0_AB10 -#define VDC50GR0_AB11 VDC50.GR0_AB11 -#define VDC50GR0_BASE VDC50.GR0_BASE -#define VDC50GR0_CLUT VDC50.GR0_CLUT -#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE -#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET -#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1 -#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2 -#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3 -#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1 -#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2 -#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3 -#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4 -#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5 -#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6 -#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1 -#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2 -#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE -#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0 -#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1 -#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0 -#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1 -#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0 -#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1 -#define VDC50GR2_UPDATE VDC50.GR2_UPDATE -#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD -#define VDC50GR2_FLM1 VDC50.GR2_FLM1 -#define VDC50GR2_FLM2 VDC50.GR2_FLM2 -#define VDC50GR2_FLM3 VDC50.GR2_FLM3 -#define VDC50GR2_FLM4 VDC50.GR2_FLM4 -#define VDC50GR2_FLM5 VDC50.GR2_FLM5 -#define VDC50GR2_FLM6 VDC50.GR2_FLM6 -#define VDC50GR2_AB1 VDC50.GR2_AB1 -#define VDC50GR2_AB2 VDC50.GR2_AB2 -#define VDC50GR2_AB3 VDC50.GR2_AB3 -#define VDC50GR2_AB4 VDC50.GR2_AB4 -#define VDC50GR2_AB5 VDC50.GR2_AB5 -#define VDC50GR2_AB6 VDC50.GR2_AB6 -#define VDC50GR2_AB7 VDC50.GR2_AB7 -#define VDC50GR2_AB8 VDC50.GR2_AB8 -#define VDC50GR2_AB9 VDC50.GR2_AB9 -#define VDC50GR2_AB10 VDC50.GR2_AB10 -#define VDC50GR2_AB11 VDC50.GR2_AB11 -#define VDC50GR2_BASE VDC50.GR2_BASE -#define VDC50GR2_CLUT VDC50.GR2_CLUT -#define VDC50GR2_MON VDC50.GR2_MON -#define VDC50GR3_UPDATE VDC50.GR3_UPDATE -#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD -#define VDC50GR3_FLM1 VDC50.GR3_FLM1 -#define VDC50GR3_FLM2 VDC50.GR3_FLM2 -#define VDC50GR3_FLM3 VDC50.GR3_FLM3 -#define VDC50GR3_FLM4 VDC50.GR3_FLM4 -#define VDC50GR3_FLM5 VDC50.GR3_FLM5 -#define VDC50GR3_FLM6 VDC50.GR3_FLM6 -#define VDC50GR3_AB1 VDC50.GR3_AB1 -#define VDC50GR3_AB2 VDC50.GR3_AB2 -#define VDC50GR3_AB3 VDC50.GR3_AB3 -#define VDC50GR3_AB4 VDC50.GR3_AB4 -#define VDC50GR3_AB5 VDC50.GR3_AB5 -#define VDC50GR3_AB6 VDC50.GR3_AB6 -#define VDC50GR3_AB7 VDC50.GR3_AB7 -#define VDC50GR3_AB8 VDC50.GR3_AB8 -#define VDC50GR3_AB9 VDC50.GR3_AB9 -#define VDC50GR3_AB10 VDC50.GR3_AB10 -#define VDC50GR3_AB11 VDC50.GR3_AB11 -#define VDC50GR3_BASE VDC50.GR3_BASE -#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT -#define VDC50GR3_MON VDC50.GR3_MON -#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE -#define VDC50GAM_SW VDC50.GAM_SW -#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1 -#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2 -#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3 -#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4 -#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5 -#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6 -#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7 -#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8 -#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9 -#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10 -#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11 -#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12 -#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13 -#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14 -#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15 -#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16 -#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1 -#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2 -#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3 -#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4 -#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5 -#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6 -#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7 -#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8 -#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE -#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1 -#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2 -#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3 -#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4 -#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5 -#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6 -#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7 -#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8 -#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9 -#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10 -#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11 -#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12 -#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13 -#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14 -#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15 -#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16 -#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1 -#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2 -#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3 -#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4 -#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5 -#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6 -#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7 -#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8 -#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE -#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1 -#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2 -#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3 -#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4 -#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5 -#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6 -#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7 -#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8 -#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9 -#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10 -#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11 -#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12 -#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13 -#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14 -#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15 -#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16 -#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1 -#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2 -#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3 -#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4 -#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5 -#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6 -#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7 -#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8 -#define VDC50TCON_UPDATE VDC50.TCON_UPDATE -#define VDC50TCON_TIM VDC50.TCON_TIM -#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1 -#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2 -#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1 -#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2 -#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1 -#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2 -#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1 -#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2 -#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1 -#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2 -#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1 -#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2 -#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1 -#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2 -#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE -#define VDC50OUT_UPDATE VDC50.OUT_UPDATE -#define VDC50OUT_SET VDC50.OUT_SET -#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1 -#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2 -#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST -#define VDC50OUT_PDTHA VDC50.OUT_PDTHA -#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE -#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1 -#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2 -#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3 -#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4 -#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5 -#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6 -#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK -#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT -#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE -#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1 -#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2 -#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3 -#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4 -#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5 -#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6 -#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7 -#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9 -#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0 -#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT -#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1 -#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2 -#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3 -#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4 -#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5 -#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6 -#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7 -#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1 -#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2 -#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3 -#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4 -#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5 -#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6 -#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7 -#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8 -#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1 -#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE -#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1 -#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2 -#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3 -#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4 -#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5 -#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6 -#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7 -#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8 -#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9 -#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10 -#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11 -#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1 -#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0 -#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1 -#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2 -#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3 -#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD -#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT -#define VDC50GR1_UPDATE VDC50.GR1_UPDATE -#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD -#define VDC50GR1_FLM1 VDC50.GR1_FLM1 -#define VDC50GR1_FLM2 VDC50.GR1_FLM2 -#define VDC50GR1_FLM3 VDC50.GR1_FLM3 -#define VDC50GR1_FLM4 VDC50.GR1_FLM4 -#define VDC50GR1_FLM5 VDC50.GR1_FLM5 -#define VDC50GR1_FLM6 VDC50.GR1_FLM6 -#define VDC50GR1_AB1 VDC50.GR1_AB1 -#define VDC50GR1_AB2 VDC50.GR1_AB2 -#define VDC50GR1_AB3 VDC50.GR1_AB3 -#define VDC50GR1_AB4 VDC50.GR1_AB4 -#define VDC50GR1_AB5 VDC50.GR1_AB5 -#define VDC50GR1_AB6 VDC50.GR1_AB6 -#define VDC50GR1_AB7 VDC50.GR1_AB7 -#define VDC50GR1_AB8 VDC50.GR1_AB8 -#define VDC50GR1_AB9 VDC50.GR1_AB9 -#define VDC50GR1_AB10 VDC50.GR1_AB10 -#define VDC50GR1_AB11 VDC50.GR1_AB11 -#define VDC50GR1_BASE VDC50.GR1_BASE -#define VDC50GR1_CLUT VDC50.GR1_CLUT -#define VDC50GR1_MON VDC50.GR1_MON -#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE -#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET -#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1 -#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2 -#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3 -#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1 -#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2 -#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3 -#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4 -#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5 -#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6 -#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1 -#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2 -#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE -#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0 -#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1 -#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0 -#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1 -#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0 -#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1 -#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE -#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1 -#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2 -#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3 -#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4 -#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5 -#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6 -#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7 -#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE -#define VDC50GR_VIN_MON VDC50.GR_VIN_MON -#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE -#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1 -#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2 -#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3 -#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4 -#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5 -#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6 -#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7 -#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1 -#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2 -#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3 -#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7 -#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1 -#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2 -#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3 -#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8 -#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1 -#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE -#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1 -#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2 -#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3 -#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4 -#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5 -#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6 -#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7 -#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE -#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD -#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1 -#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2 -#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3 -#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4 -#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5 -#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6 -#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1 -#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2 -#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3 -#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7 -#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8 -#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9 -#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10 -#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11 -#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE -#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT -#define VDC50GR_OIR_MON VDC50.GR_OIR_MON -#define VDC51INP_UPDATE VDC51.INP_UPDATE -#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT -#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT -#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ -#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ -#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE -#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0 -#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1 -#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE -#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0 -#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1 -#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0 -#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1 -#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0 -#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1 -#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG -#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE -#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1 -#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2 -#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3 -#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4 -#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5 -#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6 -#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7 -#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9 -#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0 -#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT -#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1 -#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2 -#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3 -#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4 -#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5 -#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6 -#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7 -#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1 -#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2 -#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3 -#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4 -#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5 -#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6 -#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7 -#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8 -#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1 -#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE -#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1 -#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2 -#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3 -#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4 -#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5 -#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6 -#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7 -#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8 -#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9 -#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10 -#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11 -#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1 -#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0 -#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1 -#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2 -#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3 -#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD -#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT -#define VDC51GR0_UPDATE VDC51.GR0_UPDATE -#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD -#define VDC51GR0_FLM1 VDC51.GR0_FLM1 -#define VDC51GR0_FLM2 VDC51.GR0_FLM2 -#define VDC51GR0_FLM3 VDC51.GR0_FLM3 -#define VDC51GR0_FLM4 VDC51.GR0_FLM4 -#define VDC51GR0_FLM5 VDC51.GR0_FLM5 -#define VDC51GR0_FLM6 VDC51.GR0_FLM6 -#define VDC51GR0_AB1 VDC51.GR0_AB1 -#define VDC51GR0_AB2 VDC51.GR0_AB2 -#define VDC51GR0_AB3 VDC51.GR0_AB3 -#define VDC51GR0_AB7 VDC51.GR0_AB7 -#define VDC51GR0_AB8 VDC51.GR0_AB8 -#define VDC51GR0_AB9 VDC51.GR0_AB9 -#define VDC51GR0_AB10 VDC51.GR0_AB10 -#define VDC51GR0_AB11 VDC51.GR0_AB11 -#define VDC51GR0_BASE VDC51.GR0_BASE -#define VDC51GR0_CLUT VDC51.GR0_CLUT -#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE -#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET -#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1 -#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2 -#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3 -#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1 -#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2 -#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3 -#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4 -#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5 -#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6 -#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1 -#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2 -#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE -#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0 -#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1 -#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0 -#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1 -#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0 -#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1 -#define VDC51GR2_UPDATE VDC51.GR2_UPDATE -#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD -#define VDC51GR2_FLM1 VDC51.GR2_FLM1 -#define VDC51GR2_FLM2 VDC51.GR2_FLM2 -#define VDC51GR2_FLM3 VDC51.GR2_FLM3 -#define VDC51GR2_FLM4 VDC51.GR2_FLM4 -#define VDC51GR2_FLM5 VDC51.GR2_FLM5 -#define VDC51GR2_FLM6 VDC51.GR2_FLM6 -#define VDC51GR2_AB1 VDC51.GR2_AB1 -#define VDC51GR2_AB2 VDC51.GR2_AB2 -#define VDC51GR2_AB3 VDC51.GR2_AB3 -#define VDC51GR2_AB4 VDC51.GR2_AB4 -#define VDC51GR2_AB5 VDC51.GR2_AB5 -#define VDC51GR2_AB6 VDC51.GR2_AB6 -#define VDC51GR2_AB7 VDC51.GR2_AB7 -#define VDC51GR2_AB8 VDC51.GR2_AB8 -#define VDC51GR2_AB9 VDC51.GR2_AB9 -#define VDC51GR2_AB10 VDC51.GR2_AB10 -#define VDC51GR2_AB11 VDC51.GR2_AB11 -#define VDC51GR2_BASE VDC51.GR2_BASE -#define VDC51GR2_CLUT VDC51.GR2_CLUT -#define VDC51GR2_MON VDC51.GR2_MON -#define VDC51GR3_UPDATE VDC51.GR3_UPDATE -#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD -#define VDC51GR3_FLM1 VDC51.GR3_FLM1 -#define VDC51GR3_FLM2 VDC51.GR3_FLM2 -#define VDC51GR3_FLM3 VDC51.GR3_FLM3 -#define VDC51GR3_FLM4 VDC51.GR3_FLM4 -#define VDC51GR3_FLM5 VDC51.GR3_FLM5 -#define VDC51GR3_FLM6 VDC51.GR3_FLM6 -#define VDC51GR3_AB1 VDC51.GR3_AB1 -#define VDC51GR3_AB2 VDC51.GR3_AB2 -#define VDC51GR3_AB3 VDC51.GR3_AB3 -#define VDC51GR3_AB4 VDC51.GR3_AB4 -#define VDC51GR3_AB5 VDC51.GR3_AB5 -#define VDC51GR3_AB6 VDC51.GR3_AB6 -#define VDC51GR3_AB7 VDC51.GR3_AB7 -#define VDC51GR3_AB8 VDC51.GR3_AB8 -#define VDC51GR3_AB9 VDC51.GR3_AB9 -#define VDC51GR3_AB10 VDC51.GR3_AB10 -#define VDC51GR3_AB11 VDC51.GR3_AB11 -#define VDC51GR3_BASE VDC51.GR3_BASE -#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT -#define VDC51GR3_MON VDC51.GR3_MON -#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE -#define VDC51GAM_SW VDC51.GAM_SW -#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1 -#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2 -#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3 -#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4 -#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5 -#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6 -#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7 -#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8 -#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9 -#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10 -#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11 -#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12 -#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13 -#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14 -#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15 -#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16 -#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1 -#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2 -#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3 -#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4 -#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5 -#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6 -#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7 -#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8 -#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE -#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1 -#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2 -#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3 -#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4 -#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5 -#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6 -#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7 -#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8 -#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9 -#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10 -#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11 -#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12 -#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13 -#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14 -#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15 -#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16 -#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1 -#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2 -#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3 -#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4 -#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5 -#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6 -#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7 -#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8 -#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE -#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1 -#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2 -#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3 -#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4 -#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5 -#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6 -#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7 -#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8 -#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9 -#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10 -#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11 -#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12 -#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13 -#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14 -#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15 -#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16 -#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1 -#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2 -#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3 -#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4 -#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5 -#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6 -#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7 -#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8 -#define VDC51TCON_UPDATE VDC51.TCON_UPDATE -#define VDC51TCON_TIM VDC51.TCON_TIM -#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1 -#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2 -#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1 -#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2 -#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1 -#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2 -#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1 -#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2 -#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1 -#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2 -#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1 -#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2 -#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1 -#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2 -#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE -#define VDC51OUT_UPDATE VDC51.OUT_UPDATE -#define VDC51OUT_SET VDC51.OUT_SET -#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1 -#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2 -#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST -#define VDC51OUT_PDTHA VDC51.OUT_PDTHA -#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE -#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1 -#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2 -#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3 -#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4 -#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5 -#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6 -#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK -#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT -#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE -#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1 -#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2 -#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3 -#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4 -#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5 -#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6 -#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7 -#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9 -#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0 -#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT -#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1 -#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2 -#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3 -#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4 -#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5 -#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6 -#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7 -#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1 -#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2 -#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3 -#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4 -#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5 -#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6 -#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7 -#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8 -#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1 -#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE -#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1 -#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2 -#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3 -#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4 -#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5 -#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6 -#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7 -#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8 -#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9 -#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10 -#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11 -#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1 -#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0 -#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1 -#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2 -#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3 -#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD -#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT -#define VDC51GR1_UPDATE VDC51.GR1_UPDATE -#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD -#define VDC51GR1_FLM1 VDC51.GR1_FLM1 -#define VDC51GR1_FLM2 VDC51.GR1_FLM2 -#define VDC51GR1_FLM3 VDC51.GR1_FLM3 -#define VDC51GR1_FLM4 VDC51.GR1_FLM4 -#define VDC51GR1_FLM5 VDC51.GR1_FLM5 -#define VDC51GR1_FLM6 VDC51.GR1_FLM6 -#define VDC51GR1_AB1 VDC51.GR1_AB1 -#define VDC51GR1_AB2 VDC51.GR1_AB2 -#define VDC51GR1_AB3 VDC51.GR1_AB3 -#define VDC51GR1_AB4 VDC51.GR1_AB4 -#define VDC51GR1_AB5 VDC51.GR1_AB5 -#define VDC51GR1_AB6 VDC51.GR1_AB6 -#define VDC51GR1_AB7 VDC51.GR1_AB7 -#define VDC51GR1_AB8 VDC51.GR1_AB8 -#define VDC51GR1_AB9 VDC51.GR1_AB9 -#define VDC51GR1_AB10 VDC51.GR1_AB10 -#define VDC51GR1_AB11 VDC51.GR1_AB11 -#define VDC51GR1_BASE VDC51.GR1_BASE -#define VDC51GR1_CLUT VDC51.GR1_CLUT -#define VDC51GR1_MON VDC51.GR1_MON -#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE -#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET -#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1 -#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2 -#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3 -#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1 -#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2 -#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3 -#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4 -#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5 -#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6 -#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1 -#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2 -#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE -#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0 -#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1 -#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0 -#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1 -#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0 -#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1 -#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE -#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1 -#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2 -#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3 -#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4 -#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5 -#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6 -#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7 -#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE -#define VDC51GR_VIN_MON VDC51.GR_VIN_MON -#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE -#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1 -#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2 -#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3 -#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4 -#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5 -#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6 -#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7 -#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1 -#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2 -#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3 -#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7 -#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1 -#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2 -#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3 -#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8 -#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1 -#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE -#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1 -#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2 -#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3 -#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4 -#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5 -#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6 -#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7 -#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE -#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD -#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1 -#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2 -#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3 -#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4 -#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5 -#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6 -#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1 -#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2 -#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3 -#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7 -#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8 -#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9 -#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10 -#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11 -#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE -#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT -#define VDC51GR_OIR_MON VDC51.GR_OIR_MON /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h similarity index 77% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h index 0ee2a53210a..82b448e56c1 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h @@ -18,29 +18,40 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : wdt_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef WDT_IODEFINE_H #define WDT_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_wdt -{ /* WDT */ +#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ + + +#define WDTWTCSR (WDT.WTCSR) +#define WDTWTCNT (WDT.WTCNT) +#define WDTWRCSR (WDT.WRCSR) + + +typedef struct st_wdt +{ + /* WDT */ volatile uint16_t WTCSR; /* WTCSR */ volatile uint16_t WTCNT; /* WTCNT */ volatile uint16_t WRCSR; /* WRCSR */ -}; - - -#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ +} r_io_wdt_t; -#define WDTWTCSR WDT.WTCSR -#define WDTWTCNT WDT.WTCNT -#define WDTWRCSR WDT.WRCSR +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/reg32_t.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/reg32_t.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/reg32_t.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/reg32_t.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mbed_sf_boot.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c new file mode 100644 index 00000000000..75d9da0c623 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file mmu_RZ_A1H.c + * @brief MMU Configuration for RZ_A1H Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf + + Memory Type +0xffffffff |--------------------------| ------------ + | Peripherals | Device +0xfcf00000 |--------------------------| ------------ + | Page Fault | Fault +0xe8300000 |--------------------------| ------------ + | Peripherals | Device +0xe8000000 |--------------------------| ------------ + | Page Fault | Fault +0x60A00000 |--------------------------| ------------ + | On Chip RAM (10M) Mirror | Fault +0x60000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x5c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x58000000 |--------------------------| ------------ + | CS5 Mirror | Fault +0x54000000 |--------------------------| ------------ + | CS4 Mirror | Fault +0x50000000 |--------------------------| ------------ + | CS3 Mirror | Fault +0x4c000000 |--------------------------| ------------ + | CS2 Mirror | Fault +0x48000000 |--------------------------| ------------ + | CS1 Mirror | Fault +0x44000000 |--------------------------| ------------ + | CS0 Mirror | Fault +0x40000000 |--------------------------| ------------ + | BSC | RW +0x3ff00000 |--------------------------| ------------ + | SPI_MIO_BASE | RW +0x3fe00000 |--------------------------| ------------ + | Page Fault | Fault +0x20A00000 |--------------------------| ------------ + | On Chip RAM (10M) | RW +0x20000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x1c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x18000000 |--------------------------| ------------ + | CS5 User Area 64MB | RW +0x14000000 |--------------------------| ------------ + | CS4 User Area 64MB | RW +0x10000000 |--------------------------| ------------ + | CS3 SDRAM 64MB | RW +0x0c000000 |--------------------------| ------------ + | CS2 SDRAM 64MB | RW +0x08000000 |--------------------------| ------------ + | CS1 NOR Flash 64MB | RO +0x04000000 |--------------------------| ------------ + | CS0 NOR Flash 64MB | RO +0x00000000 |--------------------------| ------------ +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + + +#include "RZ_A1H.h" + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RO_DATA$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$RW_IRAM1$$Base; +#if !defined ( __ICCARM__ ) +extern uint32_t Image$$TTB$$ZI$$Base; +#endif + +#if defined( __CC_ARM ) +#elif defined( __ICCARM__ ) +#else +extern uint32_t Image$$RW_DATA_NC$$Base; +extern uint32_t Image$$ZI_DATA_NC$$Base; +#endif + +extern uint32_t Image$$VECTORS$$Limit; +extern uint32_t Image$$RO_DATA$$Limit; +extern uint32_t Image$$RW_DATA$$Limit; +extern uint32_t Image$$RW_IRAM1$$Limit; +#if defined( __CC_ARM ) +#else +extern uint32_t Image$$RW_DATA_NC$$Limit; +extern uint32_t Image$$ZI_DATA_NC$$Limit; +#endif + +#if defined( __ICCARM__ ) +#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1) +#else +#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) +#endif + +#if defined( __CC_ARM ) +#else +#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) +#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) +#endif + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +#if defined ( __ICCARM__ ) +__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; +uint32_t Image$$VECTORS$$Base; +uint32_t Image$$RO_DATA$$Base; +uint32_t Image$$RW_DATA$$Base; +uint32_t Image$$RW_IRAM1$$Base; + +uint32_t Image$$VECTORS$$Limit; +uint32_t Image$$RO_DATA$$Limit; +uint32_t Image$$RW_DATA$$Limit; +uint32_t Image$$RW_IRAM1$$Limit; +#endif + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; +#if defined ( __ICCARM__ ) +#pragma section=".intvec" +#pragma section=".rodata" +#pragma section=".rwdata" +#pragma section=".bss" + + Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); + Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); + Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); + Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); + Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); + Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); + Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss"); + Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); +#endif + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + section_normal_nc(Sect_Normal_NC, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Create 4GB of faulting entries + MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // R7S72100 memory map. + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); + +#if defined( __ICCARM__ ) + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#else + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#endif + +#if defined( __CC_ARM ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); +#elif defined ( __ICCARM__ ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); + +#else + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); +#endif + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/nvic_wrapper.c similarity index 99% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/nvic_wrapper.c index 6a09dcf067d..6a8b0fb0d23 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/nvic_wrapper.c @@ -33,7 +33,6 @@ Includes , "Project Includes" #include "MBRZA1H.h" #include "wdt_iodefine.h" #include "nvic_wrapper.h" -#include "gic.h" /****************************************************************************** Typedef definitions @@ -71,7 +70,7 @@ void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) uint32_t NVIC_GetPriorityGrouping(void) { - return GIC_GetBinaryPoint(0); + return GIC_GetBinaryPoint(); } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c new file mode 100644 index 00000000000..bebd3e114f2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file os_tick_ostm.c + * @brief CMSIS OS Tick implementation for OS Timer + * @version V1.0.1 + * @date 19. September 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef MBED_CONF_RTOS_PRESENT + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include + +#include + + +// Define OS TImer interrupt priority +#ifndef OSTM_IRQ_PRIORITY +#define OSTM_IRQ_PRIORITY 0xFFU +#endif + +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + + +static uint32_t OSTM_Clock; // Timer tick frequency +static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag + + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t clock; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + OSTM_PendIRQ = 0U; + + // Get CPG.FRQCR[IFC] bits + clock = (CPG.FRQCR >> 8) & 0x03; + + // Determine Divider 2 output clock by using SystemCoreClock + if (clock == 0x03U) { + clock = (SystemCoreClock * 3U); + } + else if (clock == 0x01U) { + clock = (SystemCoreClock * 3U)/2U; + } + else { + clock = SystemCoreClock; + } + + // Determine tick frequency + clock = clock / freq; + + // Save frequency for later + OSTM_Clock = clock; + + // Enable OSTM clock + CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + // Set interval timer mode and disable interrupts when counting starts + OSTM.OSTMnCTL = 0x00U; + + // Set compare value + OSTM.OSTMnCMP = clock - 1U; + + // Disable corresponding IRQ + IRQ_Disable (OSTM_IRQn); + IRQ_ClearPending(OSTM_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (OSTM_IRQn, 0xFFU); + + prio = IRQ_GetPriority (OSTM_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set OSTM interrupt priority + IRQ_SetPriority(OSTM_IRQn, prio-1U); + + // Set edge-triggered, non-secure, single CPU targeted IRQ + IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler); + + // Enable corresponding IRQ + IRQ_Enable (OSTM_IRQn); + + return (0); +} + +/// Enable OS Tick. +int32_t OS_Tick_Enable (void) { + + if (OSTM_PendIRQ != 0U) { + OSTM_PendIRQ = 0U; + IRQ_SetPending (OSTM_IRQn); + } + + // Start the OSTM counter + OSTM.OSTMnTS = 0x01U; + + return (0); +} + +/// Disable OS Tick. +int32_t OS_Tick_Disable (void) { + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + if (IRQ_GetPending(OSTM_IRQn) != 0) { + IRQ_ClearPending (OSTM_IRQn); + OSTM_PendIRQ = 1U; + } + + return (0); +} + +// Acknowledge OS Tick IRQ. +int32_t OS_Tick_AcknowledgeIRQ (void) { + return (IRQ_ClearPending (OSTM_IRQn)); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (OSTM_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (OSTM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (OSTM.OSTMnCMP + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t cmp = OSTM.OSTMnCMP; + return (cmp - OSTM.OSTMnCNT); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (IRQ_GetPending(OSTM_IRQn)); +} + +#endif + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c new file mode 100644 index 00000000000..5d064f64e30 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * @file system_RZ_A1H_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "RZ_A1_Init.h" +#include "irq_ctrl.h" + +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +/* + Port 0 (P0) MD pin assignment + P0_0: MD_BOOT0 + P0_1: MD_BOOT1 + P0_2: MD_CLK + P0_3: MD_CLKS + */ + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + uint32_t freq; + uint16_t mode; + uint16_t ifc; + + mode = (GPIO.PPR0 >> 2U) & 0x01U; + + if (mode == 0) { + /* Clock Mode 0 */ + /* CLKIN is between 10MHz and 13.33MHz */ + /* Divider 1 uses 1/1 ratio, PLL x30 is ON */ + freq = CM0_RENESAS_RZ_A1_CLKIN * 30U; + } else { + /* Clock Mode 1 */ + /* CLKIN is 48MHz */ + /* Divider 1 uses 1/4 ratio, PLL x32 is ON */ + freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U; + } + + /* Get CPG.FRQCR[IFC] bits */ + ifc = (CPG.FRQCR >> 8U) & 0x03U; + + /* Determine Divider 2 output clock */ + if (ifc == 0x03U) { + /* Division ratio is 1/3 */ + freq = (freq / 3U); + } + else { + if (ifc == 0x01U) { + /* Division ratio is 2/3 */ + freq = (freq * 2U) / 3U; + } + } + + SystemCoreClock = freq; +} + +/*---------------------------------------------------------------------------- + IRQ Handler Register/Unregister + *----------------------------------------------------------------------------*/ +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + return IRQ_SetHandler(irq, handler); +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + return IRQ_SetHandler(irq, (IRQHandler_t)NULL); +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ + + // Enable SRAM write access + CPG.SYSCR3 = 0x0F; + + RZ_A1_InitClock(); + RZ_A1_InitBus(); + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + L2C_InvAllByWay(); + // Enable L2C + L2C_Enable(); +#endif + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h new file mode 100644 index 00000000000..3dcb9a2eec8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * @file system_RZ_A1H.h + * @brief CMSIS Device System Header File for ARM Cortex-A Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_RZ_A1H_H +#define __SYSTEM_RZ_A1H_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Interrupt Handler Register. + + Registers an Interrupt Handler into the IRQ Table. + */ +extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); + +/** + \brief Interrupt Handler Unregister. + + Unregisters an Interrupt Handler from the IRQ Table. + */ +extern uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_RZ_A1H_H */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h similarity index 64% rename from features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h index 8d554497120..827ad7fce33 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/crypto-misc.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton + * Copyright (c) 2006-2017 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,20 +14,22 @@ * limitations under the License. */ -#ifndef MBED_CRYPTO_MISC_H -#define MBED_CRYPTO_MISC_H +#ifndef MBED_DRV_CFG_H +#define MBED_DRV_CFG_H -#ifdef __cplusplus -extern "C" { -#endif +/* can_api.c */ +#define CAN_TEST_GLOBAL_CH 1 -void crypto_init(void); -void crypto_zeroize(void *v, size_t n); -int crypto_sha_acquire(void); -void crypto_sha_release(void); +/* gpio_api.c */ +#define GPIO_GROUP_MAX 11 -#ifdef __cplusplus -} -#endif +/* pwmout_api.c */ +#define FUNC_MOTOR_CTL_PWM +#define FUMC_MTU2_PWM + +/* rtc_api.c */ +//#define USE_RTCX1_CLK +#define USE_EXTAL_CLK +//#define USE_RTCX3_CLK #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h new file mode 100644 index 00000000000..a8c7fb6df0b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h @@ -0,0 +1,109 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART0, + UART1, + UART2, + UART3, + UART4, + UART5, + UART6, + UART7, +} UARTName; + +typedef enum { + PWM_PWM1A = 0, + PWM_PWM1B, + PWM_PWM1C, + PWM_PWM1D, + PWM_PWM1E, + PWM_PWM1F, + PWM_PWM1G, + PWM_PWM1H, + PWM_PWM2A, + PWM_PWM2B, + PWM_PWM2C, + PWM_PWM2D, + PWM_PWM2E, + PWM_PWM2F, + PWM_PWM2G, + PWM_PWM2H, + PWM_TIOC0A = 0x20, + PWM_TIOC0C, + PWM_TIOC1A, + PWM_TIOC2A, + PWM_TIOC3A, + PWM_TIOC3C, + PWM_TIOC4A, + PWM_TIOC4C, +} PWMName; + +typedef enum { + AN0= 0, + AN1= 1, + AN2= 2, + AN3= 3, + AN4= 4, + AN5= 5, + AN6= 6, + AN7= 7, +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1, + SPI_2, + SPI_3, + SPI_4, +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, +} I2CName; + +typedef enum { + CAN_0 = 0, + CAN_1, + CAN_2, + CAN_3, + CAN_4, +} CANName; + + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART3 + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c new file mode 100644 index 00000000000..d5fd4b1d922 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c @@ -0,0 +1,540 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************IRQ***************/ +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, +} IRQNo; +const PinMap PinMap_IRQ[] = { +#ifdef MAX_PERI + {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, + {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, + {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, + {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, + {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, + {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, + {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, + {NC, NC, 0} +#else + {P9_1, IRQ0, 4}, + {P7_8, IRQ1, 8}, + {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, + {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, + {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, + {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, + {NC, NC, 0} +#endif +}; + +/************PINMAP***************/ +const PinFunc PIPC_0_tbl[] = { +#ifdef MAX_PERI +// pin func pm + {P4_0 , 2 , -1}, /* TIOC0A */ + {P5_0 , 6 , -1}, /* TIOC0A */ + {P7_0 , 7 , -1}, /* TIOC0A */ + {P4_1 , 2 , -1}, /* TIOC0B */ + {P5_1 , 6 , -1}, /* TIOC0B */ + {P7_1 , 7 , -1}, /* TIOC0B */ + {P4_2 , 2 , -1}, /* TIOC0C */ + {P5_5 , 6 , -1}, /* TIOC0C */ + {P7_2 , 7 , -1}, /* TIOC0C */ + {P4_3 , 2 , -1}, /* TIOC0D */ + {P5_7 , 6 , -1}, /* TIOC0D */ + {P7_3 , 7 , -1}, /* TIOC0D */ + {P2_11 , 5 , -1}, /* TIOC1A */ + {P6_0 , 5 , -1}, /* TIOC1A */ + {P7_4 , 7 , -1}, /* TIOC1A */ + {P8_8 , 5 , -1}, /* TIOC1A */ + {P9_7 , 4 , -1}, /* TIOC1A */ + {P2_12 , 8 , -1}, /* TIOC1B */ + {P5_2 , 6 , -1}, /* TIOC1B */ + {P6_1 , 5 , -1}, /* TIOC1B */ + {P7_5 , 7 , -1}, /* TIOC1B */ + {P8_9 , 5 , -1}, /* TIOC1B */ + {P2_1 , 6 , -1}, /* TIOC2A */ + {P6_2 , 6 , -1}, /* TIOC2A */ + {P7_6 , 7 , -1}, /* TIOC2A */ + {P8_14 , 4 , -1}, /* TIOC2A */ + {P2_2 , 6 , -1}, /* TIOC2B */ + {P6_3 , 6 , -1}, /* TIOC2B */ + {P7_7 , 7 , -1}, /* TIOC2B */ + {P8_15 , 4 , -1}, /* TIOC2B */ + {P3_4 , 6 , -1}, /* TIOC3A */ + {P7_8 , 7 , -1}, /* TIOC3A */ + {P8_10 , 4 , -1}, /* TIOC3A */ + {P3_5 , 6 , -1}, /* TIOC3B */ + {P7_9 , 7 , -1}, /* TIOC3B */ + {P8_11 , 4 , -1}, /* TIOC3B */ + {P3_6 , 6 , -1}, /* TIOC3C */ + {P5_3 , 6 , -1}, /* TIOC3C */ + {P7_10 , 7 , -1}, /* TIOC3C */ + {P8_12 , 4 , -1}, /* TIOC3C */ + {P3_7 , 6 , -1}, /* TIOC3D */ + {P5_4 , 6 , -1}, /* TIOC3D */ + {P7_11 , 7 , -1}, /* TIOC3D */ + {P8_13 , 4 , -1}, /* TIOC3D */ + {P3_8 , 6 , -1}, /* TIOC4A */ + {P4_4 , 3 , -1}, /* TIOC4A */ + {P7_12 , 7 , -1}, /* TIOC4A */ + {P3_9 , 6 , -1}, /* TIOC4B */ + {P4_5 , 3 , -1}, /* TIOC4B */ + {P7_13 , 7 , -1}, /* TIOC4B */ + {P3_10 , 6 , -1}, /* TIOC4C */ + {P4_6 , 3 , -1}, /* TIOC4C */ + {P7_14 , 7 , -1}, /* TIOC4C */ + {P3_11 , 6 , -1}, /* TIOC4D */ + {P4_7 , 3 , -1}, /* TIOC4D */ + {P7_15 , 7 , -1}, /* TIOC4D */ + {P5_7 , 1 , 1 }, /* TXOUT0M */ + {P5_6 , 1 , 1 }, /* TXOUT0P */ + {P5_5 , 1 , 1 }, /* TXOUT1M */ + {P5_4 , 1 , 1 }, /* TXOUT1P */ + {P5_3 , 1 , 1 }, /* TXOUT2M */ + {P5_2 , 1 , 1 }, /* TXOUT2P */ + {P5_1 , 1 , 1 }, /* TXCLKOUTM */ + {P5_0 , 1 , 1 }, /* TXCLKOUTP */ + {P2_11 , 4 , 0 }, /* SSITxD0 */ + {P4_7 , 5 , 0 }, /* SSITxD0 */ + {P7_4 , 6 , 0 }, /* SSITxD1 */ + {P4_15 , 6 , 0 }, /* SSITxD3 */ + {P7_11 , 2 , 0 }, /* SSITxD3 */ + {P2_7 , 4 , 0 }, /* SSITxD5 */ + {P4_11 , 5 , 0 }, /* SSITxD5 */ + {P8_10 , 8 , 0 }, /* SSITxD5 */ + {P3_7 , 8 , 0 }, /* WDTOVF */ + {NC , 0 , -1} +#else + // pin func pm + {P4_0 , 2 , -1}, // TIOC0A + {P5_0 , 6 , -1}, // TIOC0A + {P4_2 , 2 , -1}, // TIOC0C + {P5_5 , 6 , -1}, // TIOC0C + // + {P8_14 , 4 , -1}, // TIOC2A + // + {P8_10 , 4 , -1}, // TIOC3A + {P5_3 , 6 , -1}, // TIOC3C + {P8_12 , 4 , -1}, // TIOC3C + // + {P3_8 , 6 , -1}, // TIOC4A + {P4_4 , 3 , -1}, // TIOC4A + {P3_10 , 6 , -1}, // TIOC4C + {P4_6 , 3 , -1}, // TIOC4C + // + {P5_7 , 1 , 1 }, // TXOUT0M + {P5_6 , 1 , 1 }, // TXOUT0P + {P5_5 , 1 , 1 }, // TXOUT1M + {P5_4 , 1 , 1 }, // TXOUT1P + {P5_3 , 1 , 1 }, // TXOUT2M + {P5_2 , 1 , 1 }, // TXOUT2P + {P5_1 , 1 , 1 }, // TXCLKOUTM + {P5_0 , 1 , 1 }, // TXCLKOUTP + {P4_7 , 5 , 0 }, // SSITxD0 + {P8_10 , 8 , 0 }, // SSITxD5 + {P3_7 , 8 , 0 }, // WDTOVF + {NC , 0 , -1} +#endif +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { +#ifdef MAX_PERI + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_14, AN6, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +#else + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +#endif +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_5 , I2C_2, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_4 , I2C_2, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { +#ifdef MAX_PERI + {P2_14 , UART0, 6}, + {P4_9 , UART0, 7}, + {P6_9 , UART0, 5}, + {P2_5 , UART1, 6}, + {P4_12 , UART1, 7}, + {P6_12 , UART1, 5}, + {P9_3 , UART1, 4}, + {P3_0 , UART2, 6}, + {P3_1 , UART2, 4}, + {P4_2 , UART2, 5}, + {P4_14 , UART2, 7}, + {P6_3 , UART2, 7}, + {P8_6 , UART2, 7}, + {P3_5 , UART3, 7}, + {P5_3 , UART3, 5}, + {P6_1 , UART3, 7}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P7_1 , UART4, 4}, + {P8_14 , UART4, 7}, + {P6_6 , UART5, 5}, + {P8_1 , UART5, 4}, + {P8_13 , UART5, 5}, + {P5_6 , UART6, 5}, + {P6_14 , UART6, 4}, + {P7_4 , UART7, 4}, + {NC , NC , 0} +#else + {P3_0 , UART2, 6}, + {P3_1 , UART2, 4}, + {P4_2 , UART2, 5}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P8_14 , UART4, 7}, + {P8_13 , UART5, 5}, + {P5_6 , UART6, 5}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_UART_RX[] = { +#ifdef MAX_PERI + {P2_15 , UART0, 6}, + {P4_10 , UART0, 7}, + {P6_10 , UART0, 5}, + {P2_6 , UART1, 6}, + {P4_13 , UART1, 7}, + {P6_13 , UART1, 5}, + {P9_4 , UART1, 4}, + {P3_2 , UART2, 4}, + {P4_3 , UART2, 5}, + {P4_15 , UART2, 7}, + {P6_2 , UART2, 7}, + {P8_4 , UART2, 7}, + {P3_6 , UART3, 7}, + {P5_4 , UART3, 5}, + {P6_0 , UART3, 7}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P7_2 , UART4, 4}, + {P8_15 , UART4, 7}, + {P6_7 , UART5, 5}, + {P8_2 , UART5, 4}, + {P8_11 , UART5, 5}, + {P5_7 , UART6, 5}, + {P6_15 , UART6, 4}, + {P7_5 , UART7, 4}, + {NC , NC , 0} +#else + {P3_2 , UART2, 4}, + {P4_3 , UART2, 5}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P8_15 , UART4, 7}, + {P8_11 , UART5, 5}, + {P5_7 , UART6, 5}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_UART_CTS[] = { +#ifdef MAX_PERI + {P2_3 , UART1, 6}, + {P9_5 , UART1, 4}, + {P6_3 , UART5, 5}, + {P7_15 , UART5, 4}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +#else + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_UART_RTS[] = { +#ifdef MAX_PERI + {P2_7 , UART1, 6}, + {P9_6 , UART1, 4}, + {P6_4 , UART5, 5}, + {P8_3 , UART5, 4}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +#else + {NC , NC , 0} +#endif +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { +#ifdef MAX_PERI + {P2_12 , SPI_0, 2}, + {P7_15 , SPI_0, 2}, + {P4_4 , SPI_1, 2}, + {P6_4 , SPI_1, 7}, + {P8_3 , SPI_2, 3}, + {P8_14 , SPI_2, 5}, + {P3_0 , SPI_3, 8}, + {P5_0 , SPI_3, 8}, + {P2_8 , SPI_4, 8}, + {P4_0 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_4 , SPI_1, 2}, + {P8_14 , SPI_2, 5}, + {P5_0 , SPI_3, 8}, + {P4_0 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_SPI_MOSI[] = { +#ifdef MAX_PERI + {P2_14 , SPI_0, 2}, + {P8_1 , SPI_0, 2}, + {P4_6 , SPI_1, 2}, + {P6_6 , SPI_1, 7}, + {P8_5 , SPI_2, 3}, + {P9_0 , SPI_2, 5}, + {P3_2 , SPI_3, 8}, + {P5_2 , SPI_3, 8}, + {P2_10 , SPI_4, 8}, + {P4_2 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_6 , SPI_1, 2}, + {P9_0 , SPI_2, 5}, + {P5_2 , SPI_3, 8}, + {P4_2 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_SPI_MISO[] = { +#ifdef MAX_PERI + {P2_15 , SPI_0, 2}, + {P8_2 , SPI_0, 2}, + {P4_7 , SPI_1, 2}, + {P6_7 , SPI_1, 7}, + {P8_6 , SPI_2, 3}, + {P9_1 , SPI_2, 5}, + {P3_3 , SPI_3, 8}, + {P5_3 , SPI_3, 8}, + {P2_11 , SPI_4, 8}, + {P4_3 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_7 , SPI_1, 2}, + {P9_1 , SPI_2, 5}, + {P5_3 , SPI_3, 8}, + {P4_3 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_SPI_SSEL[] = { +#ifdef MAX_PERI + {P2_13 , SPI_0, 2}, + {P8_0 , SPI_0, 2}, + {P4_5 , SPI_1, 2}, + {P6_5 , SPI_1, 7}, + {P8_4 , SPI_2, 3}, + {P8_15 , SPI_2, 5}, + {P3_1 , SPI_3, 8}, + {P5_1 , SPI_3, 8}, + {P2_9 , SPI_4, 8}, + {P4_1 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_5 , SPI_1, 2}, + {P8_15 , SPI_2, 5}, + {P5_1 , SPI_3, 8}, + {P4_1 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { +#ifdef MAX_PERI + // TIOC0 A,C + {P4_0 , PWM_TIOC0A, 2}, //TIOC0A + {P5_0 , PWM_TIOC0A, 6}, //TIOC0A + {P7_0 , PWM_TIOC0A, 7}, //TIOC0A + {P4_2 , PWM_TIOC0C, 2}, //TIOC0C + {P5_5 , PWM_TIOC0C, 6}, //TIOC0C + {P7_2 , PWM_TIOC0C, 7}, //TIOC0C + //TIOC1 A + {P2_11 , PWM_TIOC1A, 5}, //TIOC1A + {P6_0 , PWM_TIOC1A, 5}, //TIOC1A + {P7_4 , PWM_TIOC1A, 7}, //TIOC1A + {P8_8 , PWM_TIOC1A, 5}, //TIOC1A + {P9_7 , PWM_TIOC1A, 4}, //TIOC1A + //TIOC2 A + {P2_1 , PWM_TIOC2A, 6}, //TIOC2A + {P6_2 , PWM_TIOC2A, 6}, //TIOC2A + {P7_6 , PWM_TIOC2A, 7}, //TIOC2A + {P8_14 , PWM_TIOC2A, 4}, //TIOC2A + //TIOC3 A,C + {P3_4 , PWM_TIOC3A, 6}, //TIOC3A + {P7_8 , PWM_TIOC3A, 7}, //TIOC3A + {P8_10 , PWM_TIOC3A, 4}, //TIOC3A + {P3_6 , PWM_TIOC3C, 6}, //TIOC3C + {P7_10 , PWM_TIOC3C, 7}, //TIOC3C + {P8_12 , PWM_TIOC3C, 4}, //TIOC3C + //TIOC4 A,C + {P3_8 , PWM_TIOC4A, 6}, //TIOC4A + {P4_4 , PWM_TIOC4A, 3}, //TIOC4A + {P7_12 , PWM_TIOC4A, 7}, //TIOC4A + {P3_10 , PWM_TIOC4C, 6}, //TIOC4C + {P4_6 , PWM_TIOC4C, 3}, //TIOC4C + {P7_14 , PWM_TIOC4C, 7}, //TIOC4C + //PWM1 + {P8_8 , PWM_PWM1A , 6}, //PWM1A + {P8_9 , PWM_PWM1B , 6}, //PWM1B + {P8_10 , PWM_PWM1C , 6}, //PWM1C + {P8_11 , PWM_PWM1D , 6}, //PWM1D + {P8_12 , PWM_PWM1E , 6}, //PWM1E + {P8_13 , PWM_PWM1F , 6}, //PWM1F + {P8_14 , PWM_PWM1G , 6}, //PWM1G + {P8_15 , PWM_PWM1H , 6}, //PWM1H + //PWM2 + {P3_0 , PWM_PWM2A , 7}, //PWM2A + {P3_1 , PWM_PWM2B , 7}, //PWM2B + {P3_2 , PWM_PWM2C , 7}, //PWM2C + {P3_3 , PWM_PWM2D , 7}, //PWM2D + {P4_4 , PWM_PWM2E , 4}, //PWM2E + {P4_5 , PWM_PWM2F , 4}, //PWM2F + {P4_6 , PWM_PWM2G , 4}, //PWM2G + {P4_7 , PWM_PWM2H , 4}, //PWM2H + {NC , NC , 0} +#else + //TIOC0 A,C + {P4_0 , PWM_TIOC0A, 2}, //TIOC0A + {P5_0 , PWM_TIOC0A, 6}, //TIOC0A + {P4_2 , PWM_TIOC0C, 2}, //TIOC0C + {P5_5 , PWM_TIOC0C, 6}, //TIOC0C + //TIOC2 A + {P8_14 , PWM_TIOC2A, 4}, //TIOC2A + //TIOC3 A,C + {P8_10 , PWM_TIOC3A, 4}, //TIOC3A + {P5_3 , PWM_TIOC3C, 6}, //TIOC3C + {P8_12 , PWM_TIOC3C, 4}, //TIOC3C + //TIOC4 A,C + {P3_8 , PWM_TIOC4A, 6}, //TIOC4A + {P4_4 , PWM_TIOC4A, 3}, //TIOC4A + {P3_10 , PWM_TIOC4C, 6}, //TIOC4C + {P4_6 , PWM_TIOC4C, 3}, //TIOC4C + //PWM1 + {P8_10 , PWM_PWM1C , 6}, //PWM1C + {P8_11 , PWM_PWM1D , 6}, //PWM1D + {P8_12 , PWM_PWM1E , 6}, //PWM1E + {P8_13 , PWM_PWM1F , 6}, //PWM1F + {P8_14 , PWM_PWM1G , 6}, //PWM1G + {P8_15 , PWM_PWM1H , 6}, //PWM1H + //PWM2 + {P3_0 , PWM_PWM2A , 7}, //PWM2A + {P3_1 , PWM_PWM2B , 7}, //PWM2B + {P3_2 , PWM_PWM2C , 7}, //PWM2C + {P4_4 , PWM_PWM2E , 4}, //PWM2E + {P4_5 , PWM_PWM2F , 4}, //PWM2F + {P4_6 , PWM_PWM2G , 4}, //PWM2G + {P4_7 , PWM_PWM2H , 4}, //PWM2H + {NC , NC , 0} +#endif +}; + +/************CAN***************/ +const PinMap PinMap_CAN_RD[] = { +#ifdef MAX_PERI + {P7_8 , CAN_0, 4}, + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P7_11 , CAN_1, 4}, + {P4_9 , CAN_2, 6}, + {P6_4 , CAN_2, 3}, + {P7_2 , CAN_2, 5}, + {P2_12 , CAN_3, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {P2_14 , CAN_4, 5}, + {NC , NC , 0} +#else + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_CAN_TD[] = { +#ifdef MAX_PERI + {P7_9 , CAN_0, 4}, + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P7_10 , CAN_1, 4}, + {P4_8 , CAN_2, 6}, + {P6_5 , CAN_2, 3}, + {P7_3 , CAN_2, 5}, + {P2_13 , CAN_3, 5}, + {P4_3 , CAN_3, 4}, + {P4_11 , CAN_4, 6}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +#else + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P4_3 , CAN_3, 4}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +#endif +}; + diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h similarity index 99% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h index 644e9882540..0a79f4c8e83 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h @@ -626,9 +626,9 @@ typedef enum IRQn #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#include +#include "core_ca.h" #include "system_VKRZA1H.h" - +#include "iodefine.h" /******************************************************************************/ /* Device Specific Peripheral Section */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/reg32_t.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/reg32_t.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/pl310.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h similarity index 64% rename from features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h index 8d554497120..9b3c35d31f8 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/crypto-misc.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton + * Copyright (c) 2006-2017 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,20 +14,22 @@ * limitations under the License. */ -#ifndef MBED_CRYPTO_MISC_H -#define MBED_CRYPTO_MISC_H +#ifndef MBED_DRV_CFG_H +#define MBED_DRV_CFG_H -#ifdef __cplusplus -extern "C" { -#endif +/* can_api.c */ +#define CAN_TEST_GLOBAL_CH 1 -void crypto_init(void); -void crypto_zeroize(void *v, size_t n); -int crypto_sha_acquire(void); -void crypto_sha_release(void); +/* gpio_api.c */ +#define GPIO_GROUP_MAX 9 -#ifdef __cplusplus -} -#endif +/* pwmout_api.c */ +#define FUNC_MOTOR_CTL_PWM +#define FUMC_MTU2_PWM + +/* rtc_api.c */ +#define USE_RTCX1_CLK +//#define USE_EXTAL_CLK +//#define USE_RTCX3_CLK #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c similarity index 89% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c index 90dc113be42..c3eaac79619 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c @@ -17,25 +17,12 @@ #include "analogin_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" -#include "adc_iodefine.h" -#include "cpg_iodefine.h" +#include "iodefine.h" #define ANALOGIN_MEDIAN_FILTER 0 -static const PinMap PinMap_ADC[] = { - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_14, AN6, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -}; - static volatile uint16_t *ADCDR[] = { &ADCADDRA, &ADCADDRB, diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c similarity index 94% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c index 2b813fcf6ab..b91e608f870 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c @@ -18,12 +18,16 @@ #include "can_api.h" #include "RZ_A1_Init.h" #include "cmsis.h" -#include "pinmap.h" -#include "rscan0_iodefine.h" +#include "PeripheralPins.h" +#include "iodefine.h" #include "r_typedefs.h" -#include "MBRZA1H.h" +#include "mbed_drv_cfg.h" +#if defined(TARGET_RZA1H) #define CAN_NUM 5 +#else +#define CAN_NUM 2 +#endif #define CAN_SND_RCV 2 #define IRQ_NUM 8 @@ -31,40 +35,43 @@ static void can_rec_irq(uint32_t ch); static void can_trx_irq(uint32_t ch); static void can_err_irq(uint32_t ch, CanIrqType type); static void can0_rec_irq(void); -static void can1_rec_irq(void); -static void can2_rec_irq(void); -static void can3_rec_irq(void); -static void can4_rec_irq(void); static void can0_trx_irq(void); -static void can1_trx_irq(void); -static void can2_trx_irq(void); -static void can3_trx_irq(void); -static void can4_trx_irq(void); static void can0_err_warning_irq(void); -static void can1_err_warning_irq(void); -static void can2_err_warning_irq(void); -static void can3_err_warning_irq(void); -static void can4_err_warning_irq(void); static void can0_overrun_irq(void); -static void can1_overrun_irq(void); -static void can2_overrun_irq(void); -static void can3_overrun_irq(void); -static void can4_overrun_irq(void); static void can0_passive_irq(void); -static void can1_passive_irq(void); -static void can2_passive_irq(void); -static void can3_passive_irq(void); -static void can4_passive_irq(void); static void can0_arb_lost_irq(void); -static void can1_arb_lost_irq(void); -static void can2_arb_lost_irq(void); -static void can3_arb_lost_irq(void); -static void can4_arb_lost_irq(void); static void can0_bus_err_irq(void); +static void can1_rec_irq(void); +static void can1_trx_irq(void); +static void can1_err_warning_irq(void); +static void can1_overrun_irq(void); +static void can1_passive_irq(void); +static void can1_arb_lost_irq(void); static void can1_bus_err_irq(void); +#if defined(TARGET_RZA1H) +static void can2_rec_irq(void); +static void can2_trx_irq(void); +static void can2_err_warning_irq(void); +static void can2_overrun_irq(void); +static void can2_passive_irq(void); +static void can2_arb_lost_irq(void); static void can2_bus_err_irq(void); +static void can3_rec_irq(void); +static void can3_trx_irq(void); +static void can3_err_warning_irq(void); +static void can3_overrun_irq(void); +static void can3_passive_irq(void); +static void can3_arb_lost_irq(void); static void can3_bus_err_irq(void); +static void can4_rec_irq(void); +static void can4_trx_irq(void); +static void can4_err_warning_irq(void); +static void can4_overrun_irq(void); +static void can4_passive_irq(void); +static void can4_arb_lost_irq(void); static void can4_bus_err_irq(void); +#endif + static void can_reset_reg(can_t *obj); static void can_reset_recv_rule(can_t *obj); static void can_reset_buffer(can_t *obj); @@ -99,53 +106,25 @@ static can_irq_handler irq_handler; static uint32_t can_irq_id[CAN_NUM]; static int can_initialized[CAN_NUM] = {0}; -static const PinMap PinMap_CAN_RD[] = { - {P7_8 , CAN_0, 4}, - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P7_11 , CAN_1, 4}, - {P11_12, CAN_1, 1}, - {P4_9 , CAN_2, 6}, - {P6_4 , CAN_2, 3}, - {P7_2 , CAN_2, 5}, - {P2_12 , CAN_3, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {P2_14 , CAN_4, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_CAN_TD[] = { - {P7_9 , CAN_0, 4}, - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P7_10 , CAN_1, 4}, - {P11_13, CAN_1, 1}, - {P4_8 , CAN_2, 6}, - {P6_5 , CAN_2, 3}, - {P7_3 , CAN_2, 5}, - {P2_13 , CAN_3, 5}, - {P4_3 , CAN_3, 4}, - {P4_11 , CAN_4, 6}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -}; static __IO uint32_t *CTR_MATCH[] = { &RSCAN0C0CTR, &RSCAN0C1CTR, +#if defined(TARGET_RZA1H) &RSCAN0C2CTR, &RSCAN0C3CTR, &RSCAN0C4CTR, +#endif }; static __IO uint32_t *CFG_MATCH[] = { &RSCAN0C0CFG, &RSCAN0C1CFG, +#if defined(TARGET_RZA1H) &RSCAN0C2CFG, &RSCAN0C3CFG, &RSCAN0C4CFG, +#endif }; static __IO uint32_t *RFCC_MATCH[] = { @@ -162,89 +141,111 @@ static __IO uint32_t *RFCC_MATCH[] = { static __IO uint32_t *TXQCC_MATCH[] = { &RSCAN0TXQCC0, &RSCAN0TXQCC1, +#if defined(TARGET_RZA1H) &RSCAN0TXQCC2, &RSCAN0TXQCC3, &RSCAN0TXQCC4, +#endif }; static __IO uint32_t *THLCC_MATCH[] = { &RSCAN0THLCC0, &RSCAN0THLCC1, +#if defined(TARGET_RZA1H) &RSCAN0THLCC2, &RSCAN0THLCC3, &RSCAN0THLCC4, +#endif }; static __IO uint32_t *STS_MATCH[] = { &RSCAN0C0STS, &RSCAN0C1STS, +#if defined(TARGET_RZA1H) &RSCAN0C2STS, &RSCAN0C3STS, &RSCAN0C4STS, +#endif }; static __IO uint32_t *ERFL_MATCH[] = { &RSCAN0C0ERFL, &RSCAN0C1ERFL, +#if defined(TARGET_RZA1H) &RSCAN0C2ERFL, &RSCAN0C3ERFL, &RSCAN0C4ERFL, +#endif }; static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFCC0 , &RSCAN0CFCC1 }, { &RSCAN0CFCC3 , &RSCAN0CFCC4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFCC6 , &RSCAN0CFCC7 }, { &RSCAN0CFCC9 , &RSCAN0CFCC10 }, - { &RSCAN0CFCC12, &RSCAN0CFCC13 } + { &RSCAN0CFCC12, &RSCAN0CFCC13 }, +#endif }; static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 }, { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 }, { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 }, - { &RSCAN0CFSTS12, &RSCAN0CFSTS13 } + { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }, +#endif }; static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 }, { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 }, { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 }, - { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 } + { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }, +#endif }; static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFID0 , &RSCAN0CFID1 }, { &RSCAN0CFID3 , &RSCAN0CFID4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFID6 , &RSCAN0CFID7 }, { &RSCAN0CFID9 , &RSCAN0CFID10 }, - { &RSCAN0CFID12, &RSCAN0CFID13 } + { &RSCAN0CFID12, &RSCAN0CFID13 }, +#endif }; static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 }, { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 }, { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 }, { &RSCAN0CFPTR12, &RSCAN0CFPTR13 } +#endif }; static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFDF00 , &RSCAN0CFDF01 }, { &RSCAN0CFDF03 , &RSCAN0CFDF04 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFDF06 , &RSCAN0CFDF07 }, { &RSCAN0CFDF09 , &RSCAN0CFDF010 }, - { &RSCAN0CFDF012, &RSCAN0CFDF013 } + { &RSCAN0CFDF012, &RSCAN0CFDF013 }, +#endif }; static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFDF10 , &RSCAN0CFDF11 }, { &RSCAN0CFDF13 , &RSCAN0CFDF14 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFDF16 , &RSCAN0CFDF17 }, { &RSCAN0CFDF19 , &RSCAN0CFDF110 }, - { &RSCAN0CFDF112, &RSCAN0CFDF113 } + { &RSCAN0CFDF112, &RSCAN0CFDF113 }, +#endif }; static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = @@ -269,6 +270,7 @@ static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */ { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */ }, +#if defined(TARGET_RZA1H) { /* ch2 */ { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */ { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */ @@ -298,7 +300,8 @@ static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */ { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */ { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */ - } + }, +#endif }; static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0; @@ -340,6 +343,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { } InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler); GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5); + GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1); GIC_EnableIRQ(can_int_info[obj->ch][type].int_num); } else { GIC_DisableIRQ(can_int_info[obj->ch][type].int_num); @@ -403,141 +407,143 @@ static void can0_rec_irq(void) { can_rec_irq(CAN_0); } -static void can1_rec_irq(void) { - can_rec_irq(CAN_1); +static void can0_trx_irq(void) { + can_trx_irq(CAN_0); } -static void can2_rec_irq(void) { - can_rec_irq(CAN_2); +static void can0_err_warning_irq(void) { + can_err_irq(CAN_0, IRQ_ERROR); } -static void can3_rec_irq(void) { - can_rec_irq(CAN_3); +static void can0_overrun_irq(void) { + can_err_irq(CAN_0, IRQ_OVERRUN); } -static void can4_rec_irq(void) { - can_rec_irq(CAN_4); +static void can0_passive_irq(void) { + can_err_irq(CAN_0, IRQ_PASSIVE); } -static void can0_trx_irq(void) { - can_trx_irq(CAN_0); +static void can0_arb_lost_irq(void) { + can_err_irq(CAN_0, IRQ_ARB); } -static void can1_trx_irq(void) { - can_trx_irq(CAN_1); +static void can0_bus_err_irq(void) { + can_err_irq(CAN_0, IRQ_BUS); } -static void can2_trx_irq(void) { - can_trx_irq(CAN_2); +static void can1_rec_irq(void) { + can_rec_irq(CAN_1); } -static void can3_trx_irq(void) { - can_trx_irq(CAN_3); +static void can1_trx_irq(void) { + can_trx_irq(CAN_1); } -static void can4_trx_irq(void) { - can_trx_irq(CAN_4); +static void can1_err_warning_irq(void) { + can_err_irq(CAN_1, IRQ_ERROR); } -static void can0_err_warning_irq(void) { - can_err_irq(CAN_0, IRQ_ERROR); +static void can1_overrun_irq(void) { + can_err_irq(CAN_1, IRQ_OVERRUN); } -static void can1_err_warning_irq(void) { - can_err_irq(CAN_1, IRQ_ERROR); +static void can1_passive_irq(void) { + can_err_irq(CAN_1, IRQ_PASSIVE); } -static void can2_err_warning_irq(void) { - can_err_irq(CAN_2, IRQ_ERROR); +static void can1_arb_lost_irq(void) { + can_err_irq(CAN_1, IRQ_ARB); } -static void can3_err_warning_irq(void) { - can_err_irq(CAN_3, IRQ_ERROR); +static void can1_bus_err_irq(void) { + can_err_irq(CAN_1, IRQ_BUS); } -static void can4_err_warning_irq(void) { - can_err_irq(CAN_4, IRQ_ERROR); +#if defined(TARGET_RZA1H) +static void can2_rec_irq(void) { + can_rec_irq(CAN_2); } -static void can0_overrun_irq(void) { - can_err_irq(CAN_0, IRQ_OVERRUN); +static void can2_trx_irq(void) { + can_trx_irq(CAN_2); } -static void can1_overrun_irq(void) { - can_err_irq(CAN_1, IRQ_OVERRUN); +static void can2_err_warning_irq(void) { + can_err_irq(CAN_2, IRQ_ERROR); } static void can2_overrun_irq(void) { can_err_irq(CAN_2, IRQ_OVERRUN); } -static void can3_overrun_irq(void) { - can_err_irq(CAN_3, IRQ_OVERRUN); +static void can2_passive_irq(void) { + can_err_irq(CAN_2, IRQ_PASSIVE); } -static void can4_overrun_irq(void) { - can_err_irq(CAN_4, IRQ_OVERRUN); +static void can2_arb_lost_irq(void) { + can_err_irq(CAN_2, IRQ_ARB); } -static void can0_passive_irq(void) { - can_err_irq(CAN_0, IRQ_PASSIVE); +static void can2_bus_err_irq(void) { + can_err_irq(CAN_2, IRQ_BUS); } -static void can1_passive_irq(void) { - can_err_irq(CAN_1, IRQ_PASSIVE); +static void can3_rec_irq(void) { + can_rec_irq(CAN_3); } -static void can2_passive_irq(void) { - can_err_irq(CAN_2, IRQ_PASSIVE); +static void can3_trx_irq(void) { + can_trx_irq(CAN_3); } -static void can3_passive_irq(void) { - can_err_irq(CAN_3, IRQ_PASSIVE); +static void can3_err_warning_irq(void) { + can_err_irq(CAN_3, IRQ_ERROR); } -static void can4_passive_irq(void) { - can_err_irq(CAN_4, IRQ_PASSIVE); +static void can3_overrun_irq(void) { + can_err_irq(CAN_3, IRQ_OVERRUN); } -static void can0_arb_lost_irq(void) { - can_err_irq(CAN_0, IRQ_ARB); +static void can3_passive_irq(void) { + can_err_irq(CAN_3, IRQ_PASSIVE); } -static void can1_arb_lost_irq(void) { - can_err_irq(CAN_1, IRQ_ARB); +static void can3_arb_lost_irq(void) { + can_err_irq(CAN_3, IRQ_ARB); } -static void can2_arb_lost_irq(void) { - can_err_irq(CAN_2, IRQ_ARB); +static void can3_bus_err_irq(void) { + can_err_irq(CAN_3, IRQ_BUS); } -static void can3_arb_lost_irq(void) { - can_err_irq(CAN_3, IRQ_ARB); +static void can4_rec_irq(void) { + can_rec_irq(CAN_4); } -static void can4_arb_lost_irq(void) { - can_err_irq(CAN_4, IRQ_ARB); +static void can4_trx_irq(void) { + can_trx_irq(CAN_4); } -static void can0_bus_err_irq(void) { - can_err_irq(CAN_0, IRQ_BUS); +static void can4_err_warning_irq(void) { + can_err_irq(CAN_4, IRQ_ERROR); } -static void can1_bus_err_irq(void) { - can_err_irq(CAN_1, IRQ_BUS); +static void can4_overrun_irq(void) { + can_err_irq(CAN_4, IRQ_OVERRUN); } -static void can2_bus_err_irq(void) { - can_err_irq(CAN_2, IRQ_BUS); +static void can4_passive_irq(void) { + can_err_irq(CAN_4, IRQ_PASSIVE); } -static void can3_bus_err_irq(void) { - can_err_irq(CAN_3, IRQ_BUS); +static void can4_arb_lost_irq(void) { + can_err_irq(CAN_4, IRQ_ARB); } static void can4_bus_err_irq(void) { can_err_irq(CAN_4, IRQ_BUS); } +#endif void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) { __IO uint32_t *dmy_ctr; @@ -762,9 +768,9 @@ int can_mode(can_t *obj, CanMode mode) { can_set_channel_mode(obj->ch, CH_COMM); break; case MODE_TEST_GLOBAL: - /* set the channel between the communication test on channel 1 and channel 2 */ + /* set the channel between the communication test on CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */ /* set Channel Hold mode */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { + for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) { dmy_sts = STS_MATCH[tmp_obj->ch]; if ((*dmy_sts & 0x04) == 0x04) { /* Channel Stop mode */ @@ -776,11 +782,11 @@ int can_mode(can_t *obj, CanMode mode) { can_set_channel_mode(tmp_obj->ch, CH_HOLD); } can_set_global_mode(GL_TEST); - /* enable communication test between channel1 and channel2 */ + /* enable communication test between CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */ RSCAN0GTSTCFG = 0x06; RSCAN0GTSTCTR = 0x01; /* send and receive setting of channel1 and channel2 */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { + for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) { can_reset_buffer(tmp_obj); /* set global interrrupt */ /* THLEIE, MEIE and DEIE interrupts are disable */ @@ -887,7 +893,9 @@ static void can_reset_reg(can_t *obj) { static void can_reset_recv_rule(can_t *obj) { /* number of receive rules of each chanel = 64 */ RSCAN0GAFLCFG0 = 0x40404040; +#if defined(TARGET_RZA1H) RSCAN0GAFLCFG1 = 0x40000000; +#endif /* enable receive rule table writing */ RSCAN0GAFLECTR = 0x00000100; /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */ @@ -938,8 +946,10 @@ static void can_reset_buffer(can_t *obj) { *dmy_cfcc |= 0x02; /* TMIEp interrupt is disable */ RSCAN0TMIEC0 = 0x00000000; +#if defined(TARGET_RZA1H) RSCAN0TMIEC1 = 0x00000000; RSCAN0TMIEC2 = 0x00000000; +#endif } static void can_reconfigure_channel(void) { @@ -1002,9 +1012,9 @@ static void can_set_frequency(can_t *obj, int f) { static void can_set_global_mode(int mode) { /* set Global mode */ - RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode); + RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | (uint32_t)mode); /* Wait to cahnge into Global XXXX mode */ - while ((RSCAN0GSTS & 0x07) != mode) { + while ((RSCAN0GSTS & 0x07) != (uint32_t)mode) { __NOP(); } } @@ -1015,10 +1025,10 @@ static void can_set_channel_mode(uint32_t ch, int mode) { /* set Channel mode */ dmy_ctr = CTR_MATCH[ch]; - *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode); + *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | (uint32_t)mode); /* Wait to cahnge into Channel XXXX mode */ dmy_sts = STS_MATCH[ch]; - while ((*dmy_sts & 0x07) != mode) { + while ((*dmy_sts & 0x07) != (uint32_t)mode) { __NOP(); } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/RZ_A1_Init.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/RZ_A1_Init.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/cmsis_nvic.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/cmsis_nvic.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/dev_drv.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/dev_drv.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/dev_drv.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/dev_drv.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/nvic_wrapper.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/nvic_wrapper.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/r_typedefs.h similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/r_typedefs.h index 188c22218d7..158c75cf54c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/r_typedefs.h @@ -35,17 +35,17 @@ Includes , "Project Includes" #include #include #include - #if defined(__ARM_NEON__) - #include +#endif /* __ARM_NEON__ */ -#else /* __ARM_NEON__ */ - +#ifndef float32_t typedef float float32_t; +#endif +#ifndef float64_t typedef double float64_t; +#endif -#endif /* __ARM_NEON__ */ /****************************************************************************** Typedef definitions diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/rza_io_regrw.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/rza_io_regrw.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/rza_io_regrw.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/rza_io_regrw.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/vfp_neon_push_pop.h similarity index 92% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/vfp_neon_push_pop.h index 15945a11e79..a140aeea1c3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/vfp_neon_push_pop.h @@ -6,7 +6,7 @@ /* ARM armcc specific functions */ #pragma push #pragma arm -__STATIC_ASM void __vfp_neon_push(void) { +static __asm void __vfp_neon_push(void) { ARM VMRS R2,FPSCR @@ -19,7 +19,7 @@ __STATIC_ASM void __vfp_neon_push(void) { #pragma push #pragma arm -__STATIC_ASM void __vfp_neon_pop(void) { +static __asm void __vfp_neon_pop(void) { ARM VLDMIA SP!,{D16-D31} @@ -34,7 +34,7 @@ __STATIC_ASM void __vfp_neon_pop(void) { #pragma push #pragma arm -__STATIC_ASM void __vfp_push(void) { +static __asm void __vfp_push(void) { ARM VMRS R2,FPSCR @@ -46,7 +46,7 @@ __STATIC_ASM void __vfp_push(void) { #pragma push #pragma arm -__STATIC_ASM void __vfp_pop(void) { +static __asm void __vfp_pop(void) { ARM VLDMIA SP!,{D0-D15} @@ -111,7 +111,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_push(void) "VSTMDB SP!,{D0-D15};" "VSTMDB SP!,{D16-D31};" : - : "i"(MODE_USR) + : : ); return; } @@ -127,7 +127,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_pop(void) "VMSR FPSCR,R2;" "ADD SP,SP,#8;" : - : "i"(MODE_USR) + : : ); return; } @@ -141,7 +141,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_push(void) "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment "VSTMDB SP!,{D0-D15};" : - : "i"(MODE_USR) + : : ); return; } @@ -156,7 +156,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_pop(void) "VMSR FPSCR,R2;" "ADD SP,SP,#8;" : - : "i"(MODE_USR) + : : ); return; } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c similarity index 93% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c index e8dddea30da..ae3317b20d1 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c @@ -19,9 +19,11 @@ #include "mbed_interface.h" #include "mbed_toolchain.h" #include "mbed_error.h" -#include "ether_iodefine.h" +#include "iodefine.h" #include "ethernetext_api.h" +#if DEVICE_ETHERNET + /* Descriptor info */ #define NUM_OF_TX_DESCRIPTOR (16) #define NUM_OF_RX_DESCRIPTOR (16) @@ -87,6 +89,10 @@ /* 0x00000001 : Receive frame CRC error */ #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ +void ethernet_address(char *); +void ethernet_set_link(int, int); + + /* Send descriptor */ typedef struct tag_edmac_send_desc { uint32_t td0; @@ -156,6 +162,7 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) { CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ +#if defined(TARGET_RZ_A1H) /* P4_2(PHY Reset) */ GPIOP4 &= ~0x0004; /* Outputs low level */ GPIOPMC4 &= ~0x0004; /* Port mode */ @@ -197,6 +204,41 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) { wait_100us(250); /* 25msec */ GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ wait_100us(100); /* 10msec */ +#elif defined(TARGET_VK_RZ_A1H) + /* -->4F<-- P1_14(ET_COL) */ + GPIOPMC1 |= 0x4000; + GPIOPFCAE1 &= ~0x4000; + GPIOPFCE1 |= 0x4000; + GPIOPFC1 |= 0x4000; + GPIOPIPC1 |= 0x4000; + + /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0), + P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */ + GPIOPMC2 |= 0x0FFF; + GPIOPFCAE2 &= ~0x0FFF; + GPIOPFCE2 &= ~0x0FFF; + GPIOPFC2 |= 0x0FFF; + GPIOPIPC2 |= 0x0FFF; + + /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ + GPIOPMC3 |= 0x0078; + GPIOPFCAE3 &= ~0x0078; + GPIOPFCE3 &= ~0x0078; + GPIOPFC3 |= 0x0078; + GPIOPIPC3 |= 0x0078; + + /* -->3F<-- P7_0(ET_MDC) */ + GPIOPMC7 |= 0x0001; + GPIOPFCAE7 &= ~0x0001; + GPIOPFCE7 |= 0x0001; + GPIOPFC7 &= ~0x0001; + GPIOPIPC7 |= 0x0001; + + /* Resets the E-MAC,E-DMAC */ + lan_reg_reset(); +#else +#error "There is no initialization processing." +#endif /* Resets the PHY-LSI */ phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); @@ -532,12 +574,12 @@ static void lan_desc_create(void) { static void lan_reg_set(int32_t link) { /* MAC address setting */ - ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24) - | ((uint32_t)mac_addr[1] << 16) - | ((uint32_t)mac_addr[2] << 8) - | (uint32_t)mac_addr[3]; - ETHERMALR0 = ((uint32_t)mac_addr[4] << 8) - | (uint32_t)mac_addr[5]; + ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24) + | ((uint8_t)mac_addr[1] << 16) + | ((uint8_t)mac_addr[2] << 8) + | (uint8_t)mac_addr[3]; + ETHERMALR0 = ((uint8_t)mac_addr[4] << 8) + | (uint8_t)mac_addr[5]; /* E-DMAC */ ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; @@ -578,6 +620,7 @@ static void lan_reg_set(int32_t link) { ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ + GIC_SetConfiguration(ETHERI_IRQn, 1); GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ } @@ -703,3 +746,4 @@ static void wait_100us(int32_t wait_cnt) { /* Do Nothing */ } } +#endif /* DEVICE_ETHERNET */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernetext_api.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernetext_api.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernetext_api.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernetext_api.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_addrdefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_addrdefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c similarity index 96% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c index a0540aa825f..ea1351c769e 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c @@ -16,6 +16,7 @@ #include "gpio_api.h" #include "pinmap.h" #include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" uint32_t gpio_set(PinName pin) { @@ -31,7 +32,7 @@ void gpio_init(gpio_t *obj, PinName pin) { obj->mask = gpio_set(pin); group = PINGROUP(pin); - if (group > 9) return; + if (group > GPIO_GROUP_MAX) return; obj->reg_set = (volatile uint32_t *) PSR(group); obj->reg_in = (volatile uint32_t *) PPR(group); diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c similarity index 77% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c index a4d780bff22..5c0950f556e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c @@ -16,8 +16,8 @@ #include #include "gpio_irq_api.h" -#include "intc_iodefine.h" -#include "pinmap.h" +#include "iodefine.h" +#include "PeripheralPins.h" #include "cmsis.h" #include "gpio_addrdefine.h" @@ -37,14 +37,6 @@ static gpio_irq_handler irq_handler; static const int nIRQn_h = 32; extern PinName gpio_multi_guard; -enum { - IRQ0,IRQ1, - IRQ2,IRQ3, - IRQ4,IRQ5, - IRQ6,IRQ7, - -} IRQNo; - static const IRQHandler irq_tbl[CHANNEL_NUM] = { &gpio_irq0, &gpio_irq1, @@ -56,34 +48,6 @@ static const IRQHandler irq_tbl[CHANNEL_NUM] = { &gpio_irq7, }; -static const PinMap PinMap_IRQ[] = { - {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4}, - {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3}, - {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11 - {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8}, - {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16 - {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3}, - {P3_9, IRQ6, 8}, // 20 - {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8}, - {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8}, - {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28 - {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31 - {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4}, - {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8}, - {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8}, - {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8}, - {P6_15, IRQ7, 8}, // 44 - {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8}, - {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8}, - {P7_14, IRQ6, 8}, // 51 - {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4}, - {P9_1, IRQ0, 4}, // 55 - {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57 - - {NC, NC, 0} -}; - static void handle_interrupt_in(int irq_num) { uint16_t irqs; uint16_t edge_req; @@ -166,6 +130,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]); INTCICR1 &= ~(0x3 << shift); GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); + GIC_SetConfiguration((IRQn_Type)(nIRQn_h + obj->ch), 1); obj->int_enable = 1; __enable_irq(); diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_object.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_object.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c index 20d4d94801e..227ac68f4ee 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c @@ -17,12 +17,11 @@ #include "dma_api.h" #include "i2c_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "r_typedefs.h" -#include "riic_iodefine.h" +#include "iodefine.h" #include "RZ_A1_Init.h" -#include "MBRZA1H.h" volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; @@ -61,20 +60,6 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ -static const PinMap PinMap_I2C_SDA[] = { - {P1_1 , I2C_0, 1}, - {P1_3 , I2C_1, 1}, - {P1_7 , I2C_3, 1}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {P1_0 , I2C_0, 1}, - {P1_2 , I2C_1, 1}, - {P1_6 , I2C_3, 1}, - {NC , NC, 0} -}; - static inline int i2c_status(i2c_t *obj) { return REG(SR2.UINT8[0]); } @@ -220,6 +205,7 @@ static inline void i2c_power_enable(i2c_t *obj) { break; } dummy = CPGSTBCR9; + (void)dummy; } void i2c_init(i2c_t *obj, PinName sda, PinName scl) { @@ -414,7 +400,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count = 0; int status; int value; - volatile uint32_t work_reg = 0; i2c_set_MR3_ACK(obj); /* There is a STOP condition for last processing */ @@ -1062,6 +1047,11 @@ static void i2c_irqs_set(i2c_t *obj, uint32_t enable) if (enable) { InterruptHandlerRegister(irqTable[i], handlerTable[i]); GIC_SetPriority(irqTable[i], 5); + if (i == 1) { + GIC_SetConfiguration(irqTable[i], 3); + } else { + GIC_SetConfiguration(irqTable[i], 1); + } GIC_EnableIRQ(irqTable[i]); } else { GIC_DisableIRQ(irqTable[i]); diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h similarity index 98% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h index e6b0455d889..be1a9e54872 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h @@ -22,7 +22,6 @@ #include "PeripheralNames.h" #include "PinNames.h" #include "gpio_object.h" -#include "rspi_iodefine.h" #ifdef __cplusplus extern "C" { @@ -41,6 +40,7 @@ struct i2c_s { struct spi_s { struct st_rspi *spi; uint32_t bits; + int index; }; struct gpio_irq_s { diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c new file mode 100644 index 00000000000..aa096aa1a1f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PeripheralPins.h" +#include "mbed_error.h" +#include "gpio_addrdefine.h" + +PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ + +void pin_function(PinName pin, int function) { + if (pin == (PinName)NC) return; + + int n = pin >> 4; + int bitmask = 1<<(pin & 0xf); + const PinFunc * Pipc_0_func = PIPC_0_tbl; + int pipc_data = 1; + + if (gpio_multi_guard != pin) { + if (function == 0) { + // means GPIO mode + *PMC(n) &= ~bitmask; + } else { + // alt-function mode + --function; + + if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} + if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} + if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} + + while (Pipc_0_func->pin != NC) { + if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { + pipc_data = 0; + if (Pipc_0_func->pm == 0) { + *PMSR(n) = (bitmask << 16) | 0; + } else if (Pipc_0_func->pm == 1) { + *PMSR(n) = (bitmask << 16) | bitmask; + } else { + // Do Nothing + } + break; + } + Pipc_0_func++; + } + if (pipc_data == 1) { + *PIPC(n) |= bitmask; + } else { + *PIPC(n) &= ~bitmask; + } + + if (P1_0 <= pin && pin <= P1_7 && function == 0) { + *PBDC(n) |= bitmask; + } + *PMC(n) |= bitmask; + } + } else { + gpio_multi_guard = (PinName)NC; + } +} + +void pin_mode(PinName pin, PinMode mode) { +// if (pin == (PinName)NC) { return; } +} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c similarity index 86% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c index a3300770189..91cc3056cb6 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c @@ -23,20 +23,20 @@ PinName port_pin(PortName port, int pin_n) { } void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + uint32_t i; + obj->port = port; obj->mask = mask; - obj->reg_dir = (volatile uint32_t *)PMSR(port); obj->reg_out = (volatile uint32_t *)PORT(port); obj->reg_in = (volatile uint32_t *)PPR(port); obj->reg_buf = (volatile uint32_t *)PIBC(port); // Do not use masking, because it prevents the use of the unmasked pins // port_reg->FIOMASK = ~mask; - - uint32_t i; + // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<mask & (1 << i)) { gpio_set(port_pin(obj->port, i)); } } @@ -47,8 +47,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { void port_mode(port_t *obj, PinMode mode) { uint32_t i; // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<mask & (1 << i)) { pin_mode(port_pin(obj->port, i), mode); } } @@ -57,11 +57,14 @@ void port_mode(port_t *obj, PinMode mode) { void port_dir(port_t *obj, PinDirection dir) { switch (dir) { case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask; - *obj->reg_buf |= obj->mask; - break; + *obj->reg_buf |= obj->mask; + break; case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask; - *obj->reg_buf &= ~obj->mask; - break; + *obj->reg_buf &= ~obj->mask; + break; + default: + // do nothing + break; } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c similarity index 70% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c index f0d9b8cb3e6..0bed1c4aa39 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c @@ -16,139 +16,120 @@ #include "mbed_assert.h" #include "pwmout_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "RZ_A1_Init.h" -#include "cpg_iodefine.h" -#include "pwm_iodefine.h" +#include "iodefine.h" #include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" -#define MTU2_PWM_NUM 22 -#define MTU2_PWM_SIGNAL 2 #define MTU2_PWM_OFFSET 0x20 -// PORT ID, PWM ID, Pin function -static const PinMap PinMap_PWM[] = { - {P2_1 , MTU2_PWM0_PIN , 6}, - {P2_11 , MTU2_PWM1_PIN , 5}, - {P3_8 , MTU2_PWM2_PIN , 6}, - {P3_10 , MTU2_PWM3_PIN , 6}, - {P4_0 , MTU2_PWM4_PIN , 2}, - {P4_4 , MTU2_PWM5_PIN , 3}, - {P4_6 , MTU2_PWM6_PIN , 3}, - {P5_0 , MTU2_PWM7_PIN , 6}, - {P5_3 , MTU2_PWM8_PIN , 6}, - {P5_5 , MTU2_PWM9_PIN , 6}, - {P7_2 , MTU2_PWM10_PIN , 7}, - {P7_4 , MTU2_PWM11_PIN , 7}, - {P7_6 , MTU2_PWM12_PIN , 7}, - {P7_10 , MTU2_PWM13_PIN , 7}, - {P7_12 , MTU2_PWM14_PIN , 7}, - {P7_14 , MTU2_PWM15_PIN , 7}, - {P8_8 , MTU2_PWM16_PIN , 5}, - {P8_10 , MTU2_PWM17_PIN , 4}, - {P8_12 , MTU2_PWM18_PIN , 4}, - {P8_14 , MTU2_PWM19_PIN , 4}, - {P11_0 , MTU2_PWM20_PIN , 2}, - {P11_2 , MTU2_PWM21_PIN , 2}, - {P4_4 , PWM0_PIN , 4}, - {P3_2 , PWM1_PIN , 7}, - {P4_6 , PWM2_PIN , 4}, - {P4_7 , PWM3_PIN , 4}, - {P8_14 , PWM4_PIN , 6}, - {P8_15 , PWM5_PIN , 6}, - {P8_13 , PWM6_PIN , 6}, - {P8_11 , PWM7_PIN , 6}, - {P8_8 , PWM8_PIN , 6}, - {P10_0 , PWM9_PIN , 3}, - {P8_12 , PWM10_PIN , 6}, - {P8_9 , PWM11_PIN , 6}, - {P8_10 , PWM12_PIN , 6}, - {P4_5 , PWM13_PIN , 4}, - {NC , NC , 0} -}; +#ifdef FUNC_MOTOR_CTL_PWM +typedef enum { + PWM1A = 0, + PWM1B, + PWM1C, + PWM1D, + PWM1E, + PWM1F, + PWM1G, + PWM1H, + PWM2A = 0x10, + PWM2B, + PWM2C, + PWM2D, + PWM2E, + PWM2F, + PWM2G, + PWM2H, +} PWMType; static const PWMType PORT[] = { - PWM2E, // PWM0_PIN - PWM2C, // PWM1_PIN - PWM2G, // PWM2_PIN - PWM2H, // PWM3_PIN - PWM1G, // PWM4_PIN - PWM1H, // PWM5_PIN - PWM1F, // PWM6_PIN - PWM1D, // PWM7_PIN - PWM1A, // PWM8_PIN - PWM2A, // PWM9_PIN - PWM1E, // PWM10_PIN - PWM1B, // PWM11_PIN - PWM1C, // PWM12_PIN - PWM2F, // PWM13_PIN + PWM1A, // PWM_PWM1A + PWM1B, // PWM_PWM1B + PWM1C, // PWM_PWM1C + PWM1D, // PWM_PWM1D + PWM1E, // PWM_PWM1E + PWM1F, // PWM_PWM1F + PWM1G, // PWM_PWM1G + PWM1H, // PWM_PWM1H + PWM2A, // PWM_PWM2A + PWM2B, // PWM_PWM2B + PWM2C, // PWM_PWM2C + PWM2D, // PWM_PWM2D + PWM2E, // PWM_PWM2E + PWM2F, // PWM_PWM2F + PWM2G, // PWM_PWM2G + PWM2H, // PWM_PWM2H }; -static const MTU2_PWMType MTU2_PORT[] = { - TIOC2A, // MTU2_PWM0_PIN - TIOC1A, // MTU2_PWM1_PIN - TIOC4A, // MTU2_PWM2_PIN - TIOC4C, // MTU2_PWM3_PIN - TIOC0A, // MTU2_PWM4_PIN - TIOC4A, // MTU2_PWM5_PIN - TIOC4C, // MTU2_PWM6_PIN - TIOC0A, // MTU2_PWM7_PIN - TIOC3C, // MTU2_PWM8_PIN - TIOC0C, // MTU2_PWM9_PIN - TIOC0C, // MTU2_PWM10_PIN - TIOC1A, // MTU2_PWM11_PIN - TIOC2A, // MTU2_PWM12_PIN - TIOC3C, // MTU2_PWM13_PIN - TIOC4A, // MTU2_PWM14_PIN - TIOC4C, // MTU2_PWM15_PIN - TIOC1A, // MTU2_PWM16_PIN - TIOC3A, // MTU2_PWM17_PIN - TIOC3C, // MTU2_PWM18_PIN - TIOC2A, // MTU2_PWM19_PIN - TIOC4A, // MTU2_PWM20_PIN - TIOC4C, // MTU2_PWM21_PIN +static __IO uint16_t *PWM_MATCH[] = { + &PWMPWBFR_1A, // PWM_PWM1A + &PWMPWBFR_1A, // PWM_PWM1B + &PWMPWBFR_1C, // PWM_PWM1C + &PWMPWBFR_1C, // PWM_PWM1D + &PWMPWBFR_1E, // PWM_PWM1E + &PWMPWBFR_1E, // PWM_PWM1F + &PWMPWBFR_1G, // PWM_PWM1G + &PWMPWBFR_1G, // PWM_PWM1H + &PWMPWBFR_2A, // PWM_PWM2A + &PWMPWBFR_2A, // PWM_PWM2B + &PWMPWBFR_2C, // PWM_PWM2C + &PWMPWBFR_2C, // PWM_PWM2D + &PWMPWBFR_2E, // PWM_PWM2E + &PWMPWBFR_2E, // PWM_PWM2F + &PWMPWBFR_2G, // PWM_PWM2G + &PWMPWBFR_2G, // PWM_PWM2H }; -static __IO uint16_t *PWM_MATCH[] = { - &PWMPWBFR_2E, // PWM0_PIN - &PWMPWBFR_2C, // PWM1_PIN - &PWMPWBFR_2G, // PWM2_PIN - &PWMPWBFR_2G, // PWM3_PIN - &PWMPWBFR_1G, // PWM4_PIN - &PWMPWBFR_1G, // PWM5_PIN - &PWMPWBFR_1E, // PWM6_PIN - &PWMPWBFR_1C, // PWM7_PIN - &PWMPWBFR_1A, // PWM8_PIN - &PWMPWBFR_2A, // PWM9_PIN - &PWMPWBFR_1E, // PWM10_PIN - &PWMPWBFR_1A, // PWM11_PIN - &PWMPWBFR_1C, // PWM12_PIN - &PWMPWBFR_2E, // PWM13_PIN +static uint16_t init_period_ch1 = 0; +static uint16_t init_period_ch2 = 0; +static int32_t period_ch1 = 1; +static int32_t period_ch2 = 1; +#endif + +#ifdef FUMC_MTU2_PWM +#define MTU2_PWM_SIGNAL 2 + +typedef enum { + TIOC0A = 0, + TIOC0B, + TIOC0C, + TIOC0D, + TIOC1A = 0x10, + TIOC1B, + TIOC2A = 0x20, + TIOC2B, + TIOC3A = 0x30, + TIOC3B, + TIOC3C, + TIOC3D, + TIOC4A = 0x40, + TIOC4B, + TIOC4C, + TIOC4D, +} MTU2_PWMType; + +static const MTU2_PWMType MTU2_PORT[] = { + TIOC0A, // PWM_TIOC0A + TIOC0C, // PWM_TIOC0C + TIOC1A, // PWM_TIOC1A + TIOC2A, // PWM_TIOC2A + TIOC3A, // PWM_TIOC3A + TIOC3C, // PWM_TIOC3C + TIOC4A, // PWM_TIOC4A + TIOC4C, // PWM_TIOC4C }; -static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN +static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = { + { &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A + { &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C + { &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A + { &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A + { &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A + { &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C + { &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A + { &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C }; static __IO uint8_t *TCR_MATCH[] = { @@ -212,12 +193,9 @@ typedef enum { MTU2_PERIOD } MTU2Signal; -static uint16_t init_period_ch1 = 0; -static uint16_t init_period_ch2 = 0; static uint16_t init_mtu2_period_ch[5] = {0}; -static int32_t period_ch1 = 1; -static int32_t period_ch2 = 1; static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; +#endif void pwmout_init(pwmout_t* obj, PinName pin) { // determine the channel @@ -225,6 +203,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { MBED_ASSERT(pwm != (PWMName)NC); if (pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ int tmp_pwm; @@ -260,7 +239,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pwmout_period_us(obj, 1000); init_mtu2_period_ch[obj->ch] = 1; } +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ // power on CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); @@ -268,10 +249,10 @@ void pwmout_init(pwmout_t* obj, PinName pin) { obj->pwm = pwm; if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) { obj->ch = 2; - PWMPWPR_2_BYTE_L = 0x00; + PWMPWPR_2 = 0x00; } else { obj->ch = 1; - PWMPWPR_1_BYTE_L = 0x00; + PWMPWPR_1 = 0x00; } // Wire pinout @@ -287,6 +268,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pwmout_period_us(obj, 491); init_period_ch1 = 1; } +#endif } } @@ -296,12 +278,12 @@ void pwmout_free(pwmout_t* obj) { void pwmout_write(pwmout_t* obj, float value) { uint32_t wk_cycle; - uint16_t v; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ int tmp_pwm; - + if (value < 0.0f) { value = 0.0f; } else if (value > 1.0f) { @@ -312,8 +294,16 @@ void pwmout_write(pwmout_t* obj, float value) { tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; // set channel match to percentage - *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); + if (value == 1.0f) { + *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1); + } else { + *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); + } +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM + uint16_t v; + /* PWM */ if (value < 0.0f) { value = 0.0f; @@ -332,6 +322,7 @@ void pwmout_write(pwmout_t* obj, float value) { // set channel match to percentage v = (uint16_t)((float)wk_cycle * value); *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); +#endif } } @@ -340,6 +331,7 @@ float pwmout_read(pwmout_t* obj) { float value; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ uint32_t wk_pulse; int tmp_pwm; @@ -348,7 +340,9 @@ float pwmout_read(pwmout_t* obj) { wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; value = ((float)wk_pulse / (float)wk_cycle); +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ if (obj->ch == 2) { wk_cycle = PWMPWCYR_2 & 0x03ff; @@ -356,6 +350,7 @@ float pwmout_read(pwmout_t* obj) { wk_cycle = PWMPWCYR_1 & 0x03ff; } value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); +#endif } return (value > 1.0f) ? (1.0f) : (value); @@ -369,6 +364,7 @@ void pwmout_period_ms(pwmout_t* obj, int ms) { pwmout_period_us(obj, ms * 1000); } +#ifdef FUNC_MOTOR_CTL_PWM static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ uint16_t wk_pwmpbfr; float value; @@ -379,7 +375,9 @@ static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16 v = (uint16_t)((float)new_cycle * value); *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); } +#endif +#ifdef FUMC_MTU2_PWM static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ uint16_t wk_pwmpbfr; float value; @@ -388,17 +386,20 @@ static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, u value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); *p_pwmpbfr = (uint16_t)((float)new_cycle * value); } +#endif // Set the PWM period, keeping the duty cycle the same. void pwmout_period_us(pwmout_t* obj, int us) { - uint64_t wk_cycle_mtu2; uint32_t pclk_base; uint32_t wk_cycle; uint32_t wk_cks = 0; uint16_t wk_last_cycle; - int max_us = 0; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM + uint64_t wk_cycle_mtu2; + int max_us = 0; + /* PWM by MTU2 */ int tmp_pwm; uint8_t tmp_tcr_up; @@ -432,7 +433,7 @@ void pwmout_period_us(pwmout_t* obj, int us) { wk_cks++; } wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); - + tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { tmp_tcr_up = 0xC0; @@ -468,7 +469,9 @@ void pwmout_period_us(pwmout_t* obj, int us) { MTU2TSTR |= tmp_tstr_st; // Save for future use mtu2_period_ch[obj->ch] = us; +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ if (us > 491) { us = 491; @@ -493,7 +496,7 @@ void pwmout_period_us(pwmout_t* obj, int us) { if (obj->ch == 2) { wk_last_cycle = PWMPWCYR_2 & 0x03ff; - PWMPWCR_2_BYTE_L = 0xc0 | wk_cks; + PWMPWCR_2 = 0xc0 | wk_cks; PWMPWCYR_2 = (uint16_t)wk_cycle; // Set duty again @@ -503,13 +506,13 @@ void pwmout_period_us(pwmout_t* obj, int us) { set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle); // Counter Start - PWMPWCR_2_BYTE_L |= 0x08; + PWMPWCR_2 |= 0x08; // Save for future use period_ch2 = us; } else { wk_last_cycle = PWMPWCYR_1 & 0x03ff; - PWMPWCR_1_BYTE_L = 0xc0 | wk_cks; + PWMPWCR_1 = 0xc0 | wk_cks; PWMPWCYR_1 = (uint16_t)wk_cycle; // Set duty again @@ -519,11 +522,12 @@ void pwmout_period_us(pwmout_t* obj, int us) { set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle); // Counter Start - PWMPWCR_1_BYTE_L |= 0x08; + PWMPWCR_1 |= 0x08; // Save for future use period_ch1 = us; } +#endif } } @@ -539,11 +543,14 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) { float value = 0; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ if (mtu2_period_ch[obj->ch] != 0) { value = (float)us / (float)mtu2_period_ch[obj->ch]; } +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ if (obj->ch == 2) { if (period_ch2 != 0) { @@ -554,6 +561,7 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) { value = (float)us / (float)period_ch1; } } +#endif } pwmout_write(obj, value); } diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c similarity index 96% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c index 8754a5d2575..51347827f58 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c @@ -19,15 +19,11 @@ #if DEVICE_RTC -#define USE_RTCX1_CLK -//#define USE_EXTAL_CLK -//#define USE_RTCX3_CLK - #include "rtc_api.h" -#include "rtc_iodefine.h" +#include "iodefine.h" +#include "mbed_drv_cfg.h" #include "mbed_mktime.h" - #define RCR1_VAL_ON (0x08u) // AIE = 1 #define RCR1_VAL_OFF (0x00u) #define RCR3_VAL (0x00u) @@ -70,7 +66,7 @@ #define SHIFT_1BYTE (8u) #define SHIFT_2BYTE (16u) -#define TIME_ERROR_VAL (0xFFFFFFFFu) +#define TIME_ERROR_VAL (0u) static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); @@ -138,6 +134,7 @@ void rtc_init(void) { // Dummy read dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT; + (void)dummy_read; } @@ -188,6 +185,7 @@ void rtc_free(void) { // Dummy read dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT; + (void)dummy_read; } @@ -248,7 +246,9 @@ time_t rtc_read(void) { if (err == 0) { // Convert to timestamp - t = _rtc_mktime(&timeinfo); + if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { + return TIME_ERROR_VAL; + } } else { // Error t = TIME_ERROR_VAL; @@ -339,9 +339,10 @@ static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { void rtc_write(time_t t) { struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) { return; } + volatile uint16_t dummy_read; if (rtc_isenabled() != 0) { @@ -365,6 +366,7 @@ void rtc_write(time_t t) { dummy_read = (uint16_t)RTC.RCR2; dummy_read = (uint16_t)RTC.RCR2; + (void)dummy_read; } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c similarity index 71% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c index 3dff1c42d83..e658c302140 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c @@ -21,102 +21,55 @@ #include "serial_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "gpio_api.h" +#include "RZ_A1_Init.h" -#include "scif_iodefine.h" -#include "cpg_iodefine.h" +#include "iodefine.h" +#include "mbed_drv_cfg.h" +#include "mbed_critical.h" /****************************************************************************** * INITIALIZATION ******************************************************************************/ -#define PCLK (66666666) // Define the peripheral clock P1 frequency. - +#if defined(TARGET_RZA1H) #define UART_NUM 8 +#else +#define UART_NUM 5 +#endif #define IRQ_NUM 4 static void uart0_tx_irq(void); -static void uart1_tx_irq(void); -static void uart2_tx_irq(void); -static void uart3_tx_irq(void); -static void uart4_tx_irq(void); -static void uart5_tx_irq(void); -static void uart6_tx_irq(void); -static void uart7_tx_irq(void); static void uart0_rx_irq(void); -static void uart1_rx_irq(void); -static void uart2_rx_irq(void); -static void uart3_rx_irq(void); -static void uart4_rx_irq(void); -static void uart5_rx_irq(void); -static void uart6_rx_irq(void); -static void uart7_rx_irq(void); static void uart0_er_irq(void); +static void uart1_tx_irq(void); +static void uart1_rx_irq(void); static void uart1_er_irq(void); +static void uart2_tx_irq(void); +static void uart2_rx_irq(void); static void uart2_er_irq(void); +static void uart3_tx_irq(void); +static void uart3_rx_irq(void); static void uart3_er_irq(void); +static void uart4_tx_irq(void); +static void uart4_rx_irq(void); static void uart4_er_irq(void); +#if defined(TARGET_RZA1H) +static void uart5_tx_irq(void); +static void uart5_rx_irq(void); static void uart5_er_irq(void); +static void uart6_tx_irq(void); +static void uart6_rx_irq(void); static void uart6_er_irq(void); +static void uart7_tx_irq(void); +static void uart7_rx_irq(void); static void uart7_er_irq(void); +#endif static void serial_put_done(serial_t *obj); static uint8_t serial_available_buffer(serial_t *obj); static void serial_irq_err_set(serial_t *obj, uint32_t enable); -static const PinMap PinMap_UART_TX[] = { - {P2_14 , UART0, 6}, - {P2_5 , UART1, 6}, - {P4_12 , UART1, 7}, - {P6_3 , UART2, 7}, - {P4_14 , UART2, 7}, - {P5_3 , UART3, 5}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P8_14 , UART4, 7}, - {P8_13 , UART5, 5}, - {P11_10, UART5, 3}, - {P6_6 , UART5, 5}, - {P5_6 , UART6, 5}, - {P11_1 , UART6, 4}, - {P7_4 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {P2_15 , UART0, 6}, - {P2_6 , UART1, 6}, - {P4_13 , UART1, 7}, - {P6_2 , UART2, 7}, - {P4_15 , UART2, 7}, - {P5_4 , UART3, 5}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P8_15 , UART4, 7}, - {P8_11 , UART5, 5}, - {P11_11, UART5, 3}, - {P6_7 , UART5, 5}, - {P5_7 , UART6, 5}, - {P11_2 , UART6, 4}, - {P7_5 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {P2_3 , UART1, 6}, - {P11_7 , UART5, 3}, - {P7_6 , UART7, 4}, - {NC , NC , 0} -}; -static const PinMap PinMap_UART_RTS[] = { - {P2_7 , UART1, 6}, - {P11_8 , UART5, 3}, - {P7_7 , UART7, 4}, - {NC , NC , 0} -}; - - - static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; static uart_irq_handler irq_handler; @@ -126,7 +79,6 @@ serial_t stdio_uart; struct serial_global_data_s { uint32_t serial_irq_id; gpio_t sw_rts, sw_cts; - uint8_t rx_irq_set_flow, rx_irq_set_api; serial_t *tranferring_obj, *receiving_obj; uint32_t async_tx_callback, async_rx_callback; int event, wanted_rx_events; @@ -140,9 +92,11 @@ static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn}, {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn}, {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn}, +#if defined(TARGET_RZA1H) {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn}, {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn}, - {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn} + {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn}, +#endif }; static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { @@ -151,9 +105,11 @@ static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq}, {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq}, {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq}, +#if defined(TARGET_RZA1H) {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq}, {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq}, - {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq} + {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq}, +#endif }; static __IO uint16_t *SCSCR_MATCH[] = { @@ -162,9 +118,11 @@ static __IO uint16_t *SCSCR_MATCH[] = { &SCSCR_2, &SCSCR_3, &SCSCR_4, +#if defined(TARGET_RZA1H) &SCSCR_5, &SCSCR_6, &SCSCR_7, +#endif }; static __IO uint16_t *SCFSR_MATCH[] = { @@ -173,9 +131,11 @@ static __IO uint16_t *SCFSR_MATCH[] = { &SCFSR_2, &SCFSR_3, &SCFSR_4, +#if defined(TARGET_RZA1H) &SCFSR_5, &SCFSR_6, &SCFSR_7, +#endif }; @@ -191,32 +151,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->serial.uart = (struct st_scif *)SCIF[uart]; // enable power - switch (uart) { - case UART0: - CPG.STBCR4 &= ~(1 << 7); - break; - case UART1: - CPG.STBCR4 &= ~(1 << 6); - break; - case UART2: - CPG.STBCR4 &= ~(1 << 5); - break; - case UART3: - CPG.STBCR4 &= ~(1 << 4); - break; - case UART4: - CPG.STBCR4 &= ~(1 << 3); - break; - case UART5: - CPG.STBCR4 &= ~(1 << 2); - break; - case UART6: - CPG.STBCR4 &= ~(1 << 1); - break; - case UART7: - CPG.STBCR4 &= ~(1 << 0); - break; - } + CPG.STBCR4 &= ~(1 << (7 - uart)); dummy = CPG.STBCR4; /* ==== SCIF initial setting ==== */ @@ -226,7 +161,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ---- FIFO control register (SCFCR) setting ---- */ /* Transmit FIFO reset & Receive FIFO data register reset */ - obj->serial.uart->SCFCR = 0x0006; + obj->serial.uart->SCFCR = 0x0006u; /* ---- Serial status register (SCFSR) setting ---- */ dummy = obj->serial.uart->SCFSR; @@ -264,32 +199,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); - switch (uart) { - case UART0: - obj->serial.index = 0; - break; - case UART1: - obj->serial.index = 1; - break; - case UART2: - obj->serial.index = 2; - break; - case UART3: - obj->serial.index = 3; - break; - case UART4: - obj->serial.index = 4; - break; - case UART5: - obj->serial.index = 5; - break; - case UART6: - obj->serial.index = 6; - break; - case UART7: - obj->serial.index = 7; - break; - } + obj->serial.index = uart; + uart_data[obj->serial.index].sw_rts.pin = NC; uart_data[obj->serial.index].sw_cts.pin = NC; @@ -312,51 +223,43 @@ void serial_free(serial_t *obj) { // serial_baud // set the baud rate, taking in to account the current SystemFrequency void serial_baud(serial_t *obj, int baudrate) { - uint16_t DL; + uint32_t pclk_base; + uint32_t bgdm = 1; + uint32_t cks = 0; + uint32_t DL; - obj->serial.uart->SCSMR &= ~0x0003; + if (RZ_A1_IsClockMode0() == false) { + pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; + } else { + pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; + } - if (baudrate > 32552) { - obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 - DL = PCLK / (8 * baudrate); + if (baudrate > (int)(pclk_base / 0x800)) { + obj->serial.uart->SCSMR &= ~0x0003; + obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + DL = (pclk_base + (4 * baudrate)) / (8 * baudrate); // Rounding if (DL > 0) { DL--; } obj->serial.uart->SCBRR = (uint8_t)DL; - } else if (baudrate > 16276) { - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1; - } else if (baudrate > 8138) { - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1; - } else if (baudrate > 4169) { - obj->serial.uart->SCSMR |= 0x0001; - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1; - } else if (baudrate > 2034) { - obj->serial.uart->SCSMR |= 0x0001; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1; - } else if (baudrate > 1017) { - obj->serial.uart->SCSMR |= 0x0002; - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1; - } else if (baudrate > 508) { - obj->serial.uart->SCSMR |= 0x0002; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1; - } else if (baudrate > 254) { - obj->serial.uart->SCSMR |= 0x0003; - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1; - } else if (baudrate > 127) { + } else if (baudrate < (int)(pclk_base / 0x80000)) { obj->serial.uart->SCSMR |= 0x0003; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = 0xFFu; } else { - obj->serial.uart->SCSMR |= 0x0003; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = 0xFFu; + DL = (pclk_base + (8 * baudrate)) / (16 * baudrate); // Rounding + while (DL > 256) { + DL >>= 1; + if (bgdm == 1) { + bgdm = 0; + } else { + bgdm = 1; + cks++; + } + } + obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks; + obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7); + obj->serial.uart->SCBRR = (uint8_t)(DL - 1); } } @@ -398,11 +301,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b break; } - obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078) - | (data_bits << 6) - | (parity_enable << 5) - | (parity_select << 4) - | (stop_bits << 3); + obj->serial.uart->SCSMR = data_bits << 6 + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; } /****************************************************************************** @@ -510,7 +412,7 @@ static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { serial_t *obj = uart_data[index].receiving_obj; - int was_masked, err_read; + int err_read; if (obj) { serial_irq_err_set(obj, 0); @@ -525,11 +427,7 @@ static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { } serial_rx_abort_asynch(obj); -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); if (obj->serial.uart->SCFSR & 0x93) { err_read = obj->serial.uart->SCFSR; obj->serial.uart->SCFSR = (err_read & ~0x93); @@ -537,95 +435,91 @@ static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { if (obj->serial.uart->SCLSR & 1) { obj->serial.uart->SCLSR = 0; } - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); } } -/* TX handler */ -static void uart0_tx_irq(void) { +static void uart0_tx_irq(void) { uart_tx_irq(SCIFTXI0_IRQn, 0); } -static void uart1_tx_irq(void) { - uart_tx_irq(SCIFTXI1_IRQn, 1); -} -static void uart2_tx_irq(void) { - uart_tx_irq(SCIFTXI2_IRQn, 2); +static void uart0_rx_irq(void) { + uart_rx_irq(SCIFRXI0_IRQn, 0); } -static void uart3_tx_irq(void) { - uart_tx_irq(SCIFTXI3_IRQn, 3); +static void uart0_er_irq(void) { + uart_err_irq(SCIFERI0_IRQn, 0); } -static void uart4_tx_irq(void) { - uart_tx_irq(SCIFTXI4_IRQn, 4); + +static void uart1_tx_irq(void) { + uart_tx_irq(SCIFTXI1_IRQn, 1); } -static void uart5_tx_irq(void) { - uart_tx_irq(SCIFTXI5_IRQn, 5); +static void uart1_rx_irq(void) { + uart_rx_irq(SCIFRXI1_IRQn, 1); } -static void uart6_tx_irq(void) { - uart_tx_irq(SCIFTXI6_IRQn, 6); +static void uart1_er_irq(void) { + uart_err_irq(SCIFERI1_IRQn, 1); } -static void uart7_tx_irq(void) { - uart_tx_irq(SCIFTXI7_IRQn, 7); + +static void uart2_tx_irq(void) { + uart_tx_irq(SCIFTXI2_IRQn, 2); } -/* RX handler */ -static void uart0_rx_irq(void) { - uart_rx_irq(SCIFRXI0_IRQn, 0); +static void uart2_rx_irq(void) { + uart_rx_irq(SCIFRXI2_IRQn, 2); } -static void uart1_rx_irq(void) { - uart_rx_irq(SCIFRXI1_IRQn, 1); +static void uart2_er_irq(void) { + uart_err_irq(SCIFERI2_IRQn, 2); } -static void uart2_rx_irq(void) { - uart_rx_irq(SCIFRXI2_IRQn, 2); + +static void uart3_tx_irq(void) { + uart_tx_irq(SCIFTXI3_IRQn, 3); } -static void uart3_rx_irq(void) { +static void uart3_rx_irq(void) { uart_rx_irq(SCIFRXI3_IRQn, 3); } -static void uart4_rx_irq(void) { - uart_rx_irq(SCIFRXI4_IRQn, 4); +static void uart3_er_irq(void) { + uart_err_irq(SCIFERI3_IRQn, 3); } -static void uart5_rx_irq(void) { - uart_rx_irq(SCIFRXI5_IRQn, 5); + +static void uart4_tx_irq(void) { + uart_tx_irq(SCIFTXI4_IRQn, 4); } -static void uart6_rx_irq(void) { - uart_rx_irq(SCIFRXI6_IRQn, 6); +static void uart4_rx_irq(void) { + uart_rx_irq(SCIFRXI4_IRQn, 4); } -static void uart7_rx_irq(void) { - uart_rx_irq(SCIFRXI7_IRQn, 7); +static void uart4_er_irq(void) { + uart_err_irq(SCIFERI4_IRQn, 4); } -/* Error handler */ -static void uart0_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 0); + +#if defined(TARGET_RZA1H) +static void uart5_tx_irq(void) { + uart_tx_irq(SCIFTXI5_IRQn, 5); } -static void uart1_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 1); +static void uart5_rx_irq(void) { + uart_rx_irq(SCIFRXI5_IRQn, 5); } -static void uart2_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 2); +static void uart5_er_irq(void) { + uart_err_irq(SCIFERI5_IRQn, 5); } -static void uart3_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 3); + +static void uart6_tx_irq(void) { + uart_tx_irq(SCIFTXI6_IRQn, 6); } -static void uart4_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 4); +static void uart6_rx_irq(void) { + uart_rx_irq(SCIFRXI6_IRQn, 6); } -static void uart5_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 5); +static void uart6_er_irq(void) { + uart_err_irq(SCIFERI6_IRQn, 6); } -static void uart6_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 6); + +static void uart7_tx_irq(void) { + uart_tx_irq(SCIFTXI7_IRQn, 7); } -static void uart7_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 7); +static void uart7_rx_irq(void) { + uart_rx_irq(SCIFRXI7_IRQn, 7); } +static void uart7_er_irq(void) { + uart_err_irq(SCIFERI7_IRQn, 7); +} +#endif void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -643,7 +537,13 @@ static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enab } } -static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { +static void serial_irq_err_set(serial_t *obj, uint32_t enable) +{ + serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable); + serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable); +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type IRQn; IRQHandler handler; @@ -655,45 +555,20 @@ static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enabl } } -static void serial_irq_err_set(serial_t *obj, uint32_t enable) -{ - serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable); - serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable); -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (RxIrq == irq) { - uart_data[obj->serial.index].rx_irq_set_api = enable; - } - serial_irq_set_internal(obj, irq, enable); -} - -static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { - uart_data[obj->serial.index].rx_irq_set_flow = enable; - serial_irq_set_internal(obj, RxIrq, enable); -} - /****************************************************************************** * READ/WRITE ******************************************************************************/ int serial_getc(serial_t *obj) { uint16_t err_read; int data; - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); if (obj->serial.uart->SCFSR & 0x93) { err_read = obj->serial.uart->SCFSR; obj->serial.uart->SCFSR = (err_read & ~0x93); } obj->serial.uart->SCSCR |= 0x0040; // Set RIE - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); if (obj->serial.uart->SCLSR & 0x0001) { obj->serial.uart->SCLSR = 0u; // ORER clear @@ -702,16 +577,10 @@ int serial_getc(serial_t *obj) { while (!serial_readable(obj)); data = obj->serial.uart->SCFRDR & 0xff; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); err_read = obj->serial.uart->SCFSR; obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); if (err_read & 0x80) { data = -1; //err @@ -727,20 +596,13 @@ void serial_putc(serial_t *obj, int c) { static void serial_put_done(serial_t *obj) { - int was_masked; volatile uint16_t dummy_read; - -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + + core_util_critical_section_enter(); dummy_read = obj->serial.uart->SCFSR; obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE obj->serial.uart->SCSCR |= 0x0080; // Set TIE - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); } int serial_readable(serial_t *obj) { @@ -752,20 +614,13 @@ int serial_writable(serial_t *obj) { } void serial_clear(serial_t *obj) { - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); - obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 - obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->serial.uart->SCFCR |= 0x0006u; // TFRST = 1, RFRST = 1 + obj->serial.uart->SCFCR &= ~0x0006u; // TFRST = 0, RFRST = 0 obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); } void serial_pinout_tx(PinName tx) { @@ -773,64 +628,37 @@ void serial_pinout_tx(PinName tx) { } void serial_break_set(serial_t *obj) { - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); // TxD Output(L) obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); } void serial_break_clear(serial_t *obj) { - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1 - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); } +#if DEVICE_SERIAL_FC void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { // determine the UART to use - int was_masked; - - serial_flow_irq_set(obj, 0); if (type == FlowControlRTSCTS) { -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_enter(); + obj->serial.uart->SCFCR |= 0x0008u; // CTS/RTS enable + core_util_critical_section_exit(); pinmap_pinout(rxflow, PinMap_UART_RTS); pinmap_pinout(txflow, PinMap_UART_CTS); } else { -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable - if (!was_masked) { - __enable_irq(); - } + core_util_critical_section_enter(); + obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable + core_util_critical_section_exit(); } } +#endif static uint8_t serial_available_buffer(serial_t *obj) { diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c similarity index 89% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c index a62d8b38dbe..fd3db3716f3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c @@ -18,49 +18,10 @@ #include "spi_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "mbed_error.h" #include "RZ_A1_Init.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {P10_12, SPI_0, 4}, - {P4_4 , SPI_1, 2}, - {P6_4 , SPI_1, 7}, - {P11_12, SPI_1, 2}, - {P8_3 , SPI_2, 3}, - {P5_0 , SPI_3, 8}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P10_13, SPI_0, 4}, - {P4_5 , SPI_1, 2}, - {P6_5 , SPI_1, 7}, - {P11_13, SPI_1, 2}, - {P8_4 , SPI_2, 3}, - {P5_1 , SPI_3, 8}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P10_14, SPI_0, 4}, - {P4_6 , SPI_1, 2}, - {P6_6 , SPI_1, 7}, - {P11_14, SPI_1, 2}, - {P8_5 , SPI_2, 3}, - {P5_2 , SPI_3, 8}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P10_15, SPI_0, 4}, - {P4_7 , SPI_1, 2}, - {P6_7 , SPI_1, 7}, - {P11_15, SPI_1, 2}, - {P8_6 , SPI_2, 3}, - {P5_3 , SPI_3, 8}, - {NC , NC , 0} -}; +#include "mbed_drv_cfg.h" static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; @@ -87,13 +48,9 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->spi.index = spi; // enable power and clocking - switch (spi) { - case SPI_0: CPGSTBCR10 &= ~(0x80); break; - case SPI_1: CPGSTBCR10 &= ~(0x40); break; - case SPI_2: CPGSTBCR10 &= ~(0x20); break; - case SPI_3: CPGSTBCR10 &= ~(0x10); break; - } + CPGSTBCR10 &= ~(0x80 >> spi); dummy = CPGSTBCR10; + (void)dummy; obj->spi.spi->SPCR = 0x00; // CTRL to 0 obj->spi.spi->SPSCR = 0x00; // no sequential operation @@ -192,7 +149,7 @@ void spi_frequency(spi_t *obj, int hz) { hz_min = pclk_base / 2 / 256 / 8; hz_max = pclk_base / 2; - if ((hz < hz_min) || (hz > hz_max)) { + if (((uint32_t)hz < hz_min) || ((uint32_t)hz > hz_max)) { error("Couldn't setup requested SPI frequency"); return; } @@ -293,37 +250,38 @@ int spi_busy(spi_t *obj) { #if DEVICE_SPI_ASYNCH -#define IRQ_NUM 2 +#define SPI_NUM 5 +#define IRQ_NUM 2 static void spi_irqs_set(spi_t *obj, uint32_t enable); static void spi_async_write(spi_t *obj); static void spi_async_read(spi_t *obj); static void spi0_rx_irq(void); -static void spi1_rx_irq(void); -static void spi2_rx_irq(void); -static void spi3_rx_irq(void); -static void spi4_rx_irq(void); static void spi0_er_irq(void); +static void spi1_rx_irq(void); static void spi1_er_irq(void); +static void spi2_rx_irq(void); static void spi2_er_irq(void); +static void spi3_rx_irq(void); static void spi3_er_irq(void); +static void spi4_rx_irq(void); static void spi4_er_irq(void); -static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = { +static const IRQn_Type irq_set_tbl[SPI_NUM][IRQ_NUM] = { {RSPISPRI0_IRQn, RSPISPEI0_IRQn}, {RSPISPRI1_IRQn, RSPISPEI1_IRQn}, {RSPISPRI2_IRQn, RSPISPEI2_IRQn}, {RSPISPRI3_IRQn, RSPISPEI3_IRQn}, - {RSPISPRI4_IRQn, RSPISPEI4_IRQn} + {RSPISPRI4_IRQn, RSPISPEI4_IRQn}, }; -static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = { +static const IRQHandler hander_set_tbl[SPI_NUM][IRQ_NUM] = { {spi0_rx_irq, spi0_er_irq}, {spi1_rx_irq, spi1_er_irq}, {spi2_rx_irq, spi2_er_irq}, {spi3_rx_irq, spi3_er_irq}, - {spi4_rx_irq, spi4_er_irq} + {spi4_rx_irq, spi4_er_irq}, }; struct spi_global_data_s { @@ -331,7 +289,7 @@ struct spi_global_data_s { uint32_t async_callback, event, wanted_events; }; -static struct spi_global_data_s spi_data[RSPI_COUNT]; +static struct spi_global_data_s spi_data[SPI_NUM]; static void spi_rx_irq(IRQn_Type irq_num, uint32_t index) { @@ -388,53 +346,34 @@ static void spi_err_irq(IRQn_Type irq_num, uint32_t index) } } -static void spi0_rx_irq(void) -{ +static void spi0_rx_irq(void) { spi_rx_irq(RSPISPRI0_IRQn, 0); } - -static void spi1_rx_irq(void) -{ - spi_rx_irq(RSPISPRI1_IRQn, 1); -} - -static void spi2_rx_irq(void) -{ - spi_rx_irq(RSPISPRI2_IRQn, 2); -} - -static void spi3_rx_irq(void) -{ - spi_rx_irq(RSPISPRI3_IRQn, 3); -} - -static void spi4_rx_irq(void) -{ - spi_rx_irq(RSPISPRI4_IRQn, 4); -} - -static void spi0_er_irq(void) -{ +static void spi0_er_irq(void) { spi_err_irq(RSPISPEI0_IRQn, 0); } - -static void spi1_er_irq(void) -{ +static void spi1_rx_irq(void) { + spi_rx_irq(RSPISPRI1_IRQn, 1); +} +static void spi1_er_irq(void) { spi_err_irq(RSPISPEI1_IRQn, 1); } - -static void spi2_er_irq(void) -{ +static void spi2_rx_irq(void) { + spi_rx_irq(RSPISPRI2_IRQn, 2); +} +static void spi2_er_irq(void) { spi_err_irq(RSPISPEI2_IRQn, 2); } - -static void spi3_er_irq(void) -{ +static void spi3_rx_irq(void) { + spi_rx_irq(RSPISPRI3_IRQn, 3); +} +static void spi3_er_irq(void) { spi_err_irq(RSPISPEI3_IRQn, 3); } - -static void spi4_er_irq(void) -{ +static void spi4_rx_irq(void) { + spi_rx_irq(RSPISPRI4_IRQn, 4); +} +static void spi4_er_irq(void) { spi_err_irq(RSPISPEI4_IRQn, 4); } @@ -447,6 +386,7 @@ static void spi_irqs_set(spi_t *obj, uint32_t enable) if (enable) { InterruptHandlerRegister(irqTable[i], handlerTable[i]); GIC_SetPriority(irqTable[i], 5); + GIC_SetConfiguration(irqTable[i], 1); GIC_EnableIRQ(irqTable[i]); } else { GIC_DisableIRQ(irqTable[i]); @@ -561,7 +501,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, obj->rx_buff.length = rx_length * bit_width / 8; obj->rx_buff.pos = 0; obj->rx_buff.width = bit_width; - for (i = 0; i < obj->rx_buff.length; i++) { + for (i = 0; i < (int)obj->rx_buff.length; i++) { ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD; } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c similarity index 93% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c index 7bd1ab24cc4..e6951fb7c9e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c @@ -16,11 +16,12 @@ #include #include "us_ticker_api.h" #include "PeripheralNames.h" -#include "ostm_iodefine.h" +#include "iodefine.h" +#include "cmsis.h" #include "RZ_A1_Init.h" -#include "MBRZA1H.h" #include "vfp_neon_push_pop.h" +#include "mbed_critical.h" #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ @@ -62,6 +63,7 @@ void us_ticker_init(void) { // INTC settings InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); + GIC_SetConfiguration(US_TICKER_TIMER_IRQn, 3); GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } @@ -92,21 +94,13 @@ static void us_ticker_read_last(void) { } uint32_t us_ticker_read() { - int check_irq_masked; - -#if defined ( __ICCARM__) - check_irq_masked = __disable_irq_iar(); -#else - check_irq_masked = __disable_irq(); -#endif /* __ICCARM__ */ + core_util_critical_section_enter(); __vfp_neon_push(); us_ticker_read_last(); __vfp_neon_pop(); - if (!check_irq_masked) { - __enable_irq(); - } + core_util_critical_section_exit(); /* clock to us */ return (uint32_t)ticker_us_last64; diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h deleted file mode 100644 index e7db5806262..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h +++ /dev/null @@ -1,182 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART0, - UART1, - UART2, - UART3, - UART4, - UART5, - UART6, - UART7, -} UARTName; - -// PWMType & 1 == 1 then have to use PWDTR[12] == 1 -typedef enum { - PWM1A = 0, - PWM1B, - PWM1C, - PWM1D, - PWM1E, - PWM1F, - PWM1G, - PWM1H, - PWM2A = 0x10, - PWM2B, - PWM2C, - PWM2D, - PWM2E, - PWM2F, - PWM2G, - PWM2H, -} PWMType; - -typedef enum { - TIOC0A = 0, - TIOC0B, - TIOC0C, - TIOC0D, - TIOC1A = 0x10, - TIOC1B, - TIOC2A = 0x20, - TIOC2B, - TIOC3A = 0x30, - TIOC3B, - TIOC3C, - TIOC3D, - TIOC4A = 0x40, - TIOC4B, - TIOC4C, - TIOC4D, -} MTU2_PWMType; - -typedef enum { - PWM0_PIN = 0, - PWM1_PIN, - PWM2_PIN, - PWM3_PIN, - PWM4_PIN, - PWM5_PIN, - PWM6_PIN, - PWM7_PIN, - PWM8_PIN, - PWM9_PIN, - PWM10_PIN, - PWM11_PIN, - PWM12_PIN, -#ifdef MAX_PERI - PWM13_PIN, - PWM14_PIN, - PWM15_PIN, - MTU2_PWM0_PIN = 0x20, - MTU2_PWM1_PIN, - MTU2_PWM2_PIN, - MTU2_PWM3_PIN, - MTU2_PWM4_PIN, - MTU2_PWM5_PIN, - MTU2_PWM6_PIN, - MTU2_PWM7_PIN, - MTU2_PWM8_PIN, - MTU2_PWM9_PIN, - MTU2_PWM10_PIN, - MTU2_PWM11_PIN, - MTU2_PWM12_PIN, - MTU2_PWM13_PIN, - MTU2_PWM14_PIN, - MTU2_PWM15_PIN, - MTU2_PWM16_PIN, - MTU2_PWM17_PIN, - MTU2_PWM18_PIN, - MTU2_PWM19_PIN, - MTU2_PWM20_PIN, - MTU2_PWM21_PIN, - MTU2_PWM22_PIN, - MTU2_PWM23_PIN, - MTU2_PWM23_PIN, - MTU2_PWM24_PIN, - MTU2_PWM25_PIN, - MTU2_PWM26_PIN, -#else - MTU2_PWM0_PIN = 0x20, - MTU2_PWM1_PIN, - MTU2_PWM2_PIN, - MTU2_PWM3_PIN, - MTU2_PWM4_PIN, - MTU2_PWM5_PIN, - MTU2_PWM6_PIN, - MTU2_PWM7_PIN, - MTU2_PWM8_PIN, - MTU2_PWM9_PIN, - MTU2_PWM10_PIN, - MTU2_PWM11_PIN, -#endif -} PWMName; - -typedef enum { - AN0= 0, - AN1= 1, - AN2= 2, - AN3= 3, - AN4= 4, - AN5= 5, - AN6= 6, - AN7= 7, -} ADCName; - -typedef enum { - SPI_1 = 1, - SPI_2, - SPI_3, - SPI_4, -} SPIName; - -typedef enum { - I2C_0 = 0, - I2C_1, - I2C_2, - I2C_3 -} I2CName; - -typedef enum { - CAN_0 = 0, - CAN_1, - CAN_2, - CAN_3, - CAN_4 -} CANName; - - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART3 - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c deleted file mode 100644 index caada57bf30..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c +++ /dev/null @@ -1,133 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#include "cmsis.h" -#include "pinmap.h" - -#include "adc_iodefine.h" -#include "cpg_iodefine.h" - -#define ANALOGIN_MEDIAN_FILTER 0 - -#ifdef MAX_PERI -static const PinMap PinMap_ADC[] = { - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_14, AN6, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -}; -#else -static const PinMap PinMap_ADC[] = { - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -}; -#endif - -static volatile uint16_t *ADCDR[] = { - &ADCADDRA, - &ADCADDRB, - &ADCADDRC, - &ADCADDRD, - &ADCADDRE, - &ADCADDRF, - &ADCADDRG, - &ADCADDRH, -}; - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - CPGSTBCR3 &= ~(1 << 1); - CPGSTBCR6 &= ~(1 << 7); - - // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 - // [8:6] CKS 010 :: 340tclk - // [5:3] MDS 000 :: single mode - // [2:0] CH 000 :: AN0 - ADCADCSR = 0x0080; - - pinmap_pinout(pin, PinMap_ADC); -} - -static inline uint32_t adc_read(analogin_t *obj) { - volatile uint16_t data; - - // Select the appropriate channel and start conversion - ADCADCSR &= 0xfff8; - ADCADCSR |= (1 << 13 | (obj->adc & 0x7)); - - // Wait end of conversion - do { - data = ADCADCSR; - } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0)); - - // clear flag - ADCADCSR &= ~(1 << 15); - - return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range -} - -#if ANALOGIN_MEDIAN_FILTER -static inline void order(uint32_t *a, uint32_t *b) { - if (*a > *b) { - uint32_t t = *a; - *a = *b; - *b = t; - } -} -#endif - -static inline uint32_t adc_read_u32(analogin_t *obj) { - uint32_t value; -#if ANALOGIN_MEDIAN_FILTER - uint32_t v1 = adc_read(obj); - uint32_t v2 = adc_read(obj); - uint32_t v3 = adc_read(obj); - order(&v1, &v2); - order(&v2, &v3); - order(&v1, &v2); - value = v2; -#else - value = adc_read(obj); -#endif - return value; -} - -uint16_t analogin_read_u16(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion -} - -float analogin_read(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (float)value * (1.0f / (float)0x0FFF); // 12 bits range -} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c deleted file mode 100644 index ea826157ca8..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c +++ /dev/null @@ -1,1042 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_assert.h" -#include "can_api.h" -#include "RZ_A1_Init.h" -#include "cmsis.h" -#include "pinmap.h" -#include "rscan0_iodefine.h" -#include "r_typedefs.h" -#include "VKRZA1H.h" - -#define CAN_NUM 5 -#define CAN_SND_RCV 2 -#define IRQ_NUM 8 - -static void can_rec_irq(uint32_t ch); -static void can_trx_irq(uint32_t ch); -static void can_err_irq(uint32_t ch, CanIrqType type); -static void can0_rec_irq(void); -static void can1_rec_irq(void); -static void can2_rec_irq(void); -static void can3_rec_irq(void); -static void can4_rec_irq(void); -static void can0_trx_irq(void); -static void can1_trx_irq(void); -static void can2_trx_irq(void); -static void can3_trx_irq(void); -static void can4_trx_irq(void); -static void can0_err_warning_irq(void); -static void can1_err_warning_irq(void); -static void can2_err_warning_irq(void); -static void can3_err_warning_irq(void); -static void can4_err_warning_irq(void); -static void can0_overrun_irq(void); -static void can1_overrun_irq(void); -static void can2_overrun_irq(void); -static void can3_overrun_irq(void); -static void can4_overrun_irq(void); -static void can0_passive_irq(void); -static void can1_passive_irq(void); -static void can2_passive_irq(void); -static void can3_passive_irq(void); -static void can4_passive_irq(void); -static void can0_arb_lost_irq(void); -static void can1_arb_lost_irq(void); -static void can2_arb_lost_irq(void); -static void can3_arb_lost_irq(void); -static void can4_arb_lost_irq(void); -static void can0_bus_err_irq(void); -static void can1_bus_err_irq(void); -static void can2_bus_err_irq(void); -static void can3_bus_err_irq(void); -static void can4_bus_err_irq(void); -static void can_reset_reg(can_t *obj); -static void can_reset_recv_rule(can_t *obj); -static void can_reset_buffer(can_t *obj); -static void can_reconfigure_channel(void); -static void can_set_frequency(can_t *obj, int f); -static void can_set_global_mode(int mode); -static void can_set_channel_mode(uint32_t ch, int mode); - -typedef enum { - CAN_SEND = 0, - CAN_RECV -} CANfunc; - -typedef enum { - GL_OPE = 0, - GL_RESET, - GL_TEST -} Globalmode; - -typedef enum { - CH_COMM = 0, - CH_RESET, - CH_HOLD -} Channelmode; - -typedef struct { - IRQn_Type int_num; /* Interrupt number */ - IRQHandler handler; /* Interrupt handler */ -} can_info_int_t; - -static can_irq_handler irq_handler; -static uint32_t can_irq_id[CAN_NUM]; -static int can_initialized[CAN_NUM] = {0}; - -#ifdef MAX_PERI -static const PinMap PinMap_CAN_RD[] = { - {P7_8 , CAN_0, 4}, - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P7_11 , CAN_1, 4}, - {P4_9 , CAN_2, 6}, - {P6_4 , CAN_2, 3}, - {P7_2 , CAN_2, 5}, - {P2_12 , CAN_3, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {P2_14 , CAN_4, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_CAN_TD[] = { - {P7_9 , CAN_0, 4}, - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P7_10 , CAN_1, 4}, - {P4_8 , CAN_2, 6}, - {P6_5 , CAN_2, 3}, - {P7_3 , CAN_2, 5}, - {P2_13 , CAN_3, 5}, - {P4_3 , CAN_3, 4}, - {P4_11 , CAN_4, 6}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -}; -#else -static const PinMap PinMap_CAN_RD[] = { - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {NC , NC , 0} -}; - -static const PinMap PinMap_CAN_TD[] = { - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P4_3 , CAN_3, 4}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -}; -#endif - -static __IO uint32_t *CTR_MATCH[] = { - &RSCAN0C0CTR, - &RSCAN0C1CTR, - &RSCAN0C2CTR, - &RSCAN0C3CTR, - &RSCAN0C4CTR, -}; - -static __IO uint32_t *CFG_MATCH[] = { - &RSCAN0C0CFG, - &RSCAN0C1CFG, - &RSCAN0C2CFG, - &RSCAN0C3CFG, - &RSCAN0C4CFG, -}; - -static __IO uint32_t *RFCC_MATCH[] = { - &RSCAN0RFCC0, - &RSCAN0RFCC1, - &RSCAN0RFCC2, - &RSCAN0RFCC3, - &RSCAN0RFCC4, - &RSCAN0RFCC5, - &RSCAN0RFCC6, - &RSCAN0RFCC7 -}; - -static __IO uint32_t *TXQCC_MATCH[] = { - &RSCAN0TXQCC0, - &RSCAN0TXQCC1, - &RSCAN0TXQCC2, - &RSCAN0TXQCC3, - &RSCAN0TXQCC4, -}; - -static __IO uint32_t *THLCC_MATCH[] = { - &RSCAN0THLCC0, - &RSCAN0THLCC1, - &RSCAN0THLCC2, - &RSCAN0THLCC3, - &RSCAN0THLCC4, -}; - -static __IO uint32_t *STS_MATCH[] = { - &RSCAN0C0STS, - &RSCAN0C1STS, - &RSCAN0C2STS, - &RSCAN0C3STS, - &RSCAN0C4STS, -}; - -static __IO uint32_t *ERFL_MATCH[] = { - &RSCAN0C0ERFL, - &RSCAN0C1ERFL, - &RSCAN0C2ERFL, - &RSCAN0C3ERFL, - &RSCAN0C4ERFL, -}; - -static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFCC0 , &RSCAN0CFCC1 }, - { &RSCAN0CFCC3 , &RSCAN0CFCC4 }, - { &RSCAN0CFCC6 , &RSCAN0CFCC7 }, - { &RSCAN0CFCC9 , &RSCAN0CFCC10 }, - { &RSCAN0CFCC12, &RSCAN0CFCC13 } -}; - -static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 }, - { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 }, - { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 }, - { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 }, - { &RSCAN0CFSTS12, &RSCAN0CFSTS13 } -}; - -static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 }, - { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 }, - { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 }, - { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 }, - { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 } -}; - -static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFID0 , &RSCAN0CFID1 }, - { &RSCAN0CFID3 , &RSCAN0CFID4 }, - { &RSCAN0CFID6 , &RSCAN0CFID7 }, - { &RSCAN0CFID9 , &RSCAN0CFID10 }, - { &RSCAN0CFID12, &RSCAN0CFID13 } -}; - -static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 }, - { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 }, - { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 }, - { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 }, - { &RSCAN0CFPTR12, &RSCAN0CFPTR13 } -}; - -static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFDF00 , &RSCAN0CFDF01 }, - { &RSCAN0CFDF03 , &RSCAN0CFDF04 }, - { &RSCAN0CFDF06 , &RSCAN0CFDF07 }, - { &RSCAN0CFDF09 , &RSCAN0CFDF010 }, - { &RSCAN0CFDF012, &RSCAN0CFDF013 } -}; - -static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFDF10 , &RSCAN0CFDF11 }, - { &RSCAN0CFDF13 , &RSCAN0CFDF14 }, - { &RSCAN0CFDF16 , &RSCAN0CFDF17 }, - { &RSCAN0CFDF19 , &RSCAN0CFDF110 }, - { &RSCAN0CFDF112, &RSCAN0CFDF113 } -}; - -static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = -{ - { /* ch0 */ - { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */ - { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */ - { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */ - { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */ - { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */ - { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */ - { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */ - }, - { /* ch1 */ - { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */ - { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */ - { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */ - { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */ - { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */ - { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */ - { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */ - }, - { /* ch2 */ - { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */ - { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */ - { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */ - { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */ - { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */ - { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */ - { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */ - }, - { /* ch3 */ - { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */ - { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */ - { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */ - { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */ - { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */ - { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */ - { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */ - }, - { /* ch4 */ - { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */ - { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */ - { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */ - { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */ - { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */ - { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */ - { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */ - } -}; - -static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0; -static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0; -static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00; -static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10; - -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { - irq_handler = handler; - can_irq_id[obj->ch] = id; -} - -void can_irq_free(can_t *obj) { - can_irq_id[obj->ch] = 0; -} - -void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { - __IO uint32_t *dmy_ctr; - - /* Wake-up Irq is not supported */ - if (type != IRQ_WAKEUP) { - if (enable) { - dmy_ctr = CTR_MATCH[obj->ch]; - if (type == IRQ_ERROR) { - /* EWIE interrupts is enable */ - *dmy_ctr |= 0x00000200; - } else if (type == IRQ_OVERRUN) { - /* OLIE interrupts is enable */ - *dmy_ctr |= 0x00002000; - } else if (type == IRQ_PASSIVE) { - /* EPIE interrupts is enable */ - *dmy_ctr |= 0x00000400; - } else if (type == IRQ_ARB) { - /* ALIE interrupts is enable */ - *dmy_ctr |= 0x00008000; - } else if (type == IRQ_BUS) { - /* BEIE interrupts is enable */ - *dmy_ctr |= 0x00000100; - } - InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler); - GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5); - GIC_EnableIRQ(can_int_info[obj->ch][type].int_num); - } else { - GIC_DisableIRQ(can_int_info[obj->ch][type].int_num); - } - } -} - -static void can_rec_irq(uint32_t ch) { - __IO uint32_t *dmy_cfsts; - - dmy_cfsts = CFSTS_TBL[ch][CAN_RECV]; - *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF - - irq_handler(can_irq_id[ch], IRQ_RX); -} - -static void can_trx_irq(uint32_t ch) { - __IO uint32_t *dmy_cfsts; - - dmy_cfsts = CFSTS_TBL[ch][CAN_SEND]; - *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF - - irq_handler(can_irq_id[ch], IRQ_TX); -} - -static void can_err_irq(uint32_t ch, CanIrqType type) { - __IO uint32_t *dmy_erfl; - int val = 1; - - dmy_erfl = ERFL_MATCH[ch]; - switch (type) { - case IRQ_ERROR: - *dmy_erfl &= 0xFFFFFFFD; // Clear EWF - break; - case IRQ_OVERRUN: - *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF - break; - case IRQ_PASSIVE: - *dmy_erfl &= 0xFFFFFFFB; // Clear EPF - break; - case IRQ_ARB: - *dmy_erfl &= 0xFFFFFF7F; // Clear ALF - break; - case IRQ_BUS: - *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR - *dmy_erfl &= 0xFFFFFFFE; // Clear BEF - break; - case IRQ_WAKEUP: - /* not supported */ - /* fall through */ - default: - val = 0; - break; - } - if (val == 1) { - irq_handler(can_irq_id[ch], type); - } -} - -static void can0_rec_irq(void) { - can_rec_irq(CAN_0); -} - -static void can1_rec_irq(void) { - can_rec_irq(CAN_1); -} - -static void can2_rec_irq(void) { - can_rec_irq(CAN_2); -} - -static void can3_rec_irq(void) { - can_rec_irq(CAN_3); -} - -static void can4_rec_irq(void) { - can_rec_irq(CAN_4); -} - -static void can0_trx_irq(void) { - can_trx_irq(CAN_0); -} - -static void can1_trx_irq(void) { - can_trx_irq(CAN_1); -} - -static void can2_trx_irq(void) { - can_trx_irq(CAN_2); -} - -static void can3_trx_irq(void) { - can_trx_irq(CAN_3); -} - -static void can4_trx_irq(void) { - can_trx_irq(CAN_4); -} - -static void can0_err_warning_irq(void) { - can_err_irq(CAN_0, IRQ_ERROR); -} - -static void can1_err_warning_irq(void) { - can_err_irq(CAN_1, IRQ_ERROR); -} - -static void can2_err_warning_irq(void) { - can_err_irq(CAN_2, IRQ_ERROR); -} - -static void can3_err_warning_irq(void) { - can_err_irq(CAN_3, IRQ_ERROR); -} - -static void can4_err_warning_irq(void) { - can_err_irq(CAN_4, IRQ_ERROR); -} - -static void can0_overrun_irq(void) { - can_err_irq(CAN_0, IRQ_OVERRUN); -} - -static void can1_overrun_irq(void) { - can_err_irq(CAN_1, IRQ_OVERRUN); -} - -static void can2_overrun_irq(void) { - can_err_irq(CAN_2, IRQ_OVERRUN); -} - -static void can3_overrun_irq(void) { - can_err_irq(CAN_3, IRQ_OVERRUN); -} - -static void can4_overrun_irq(void) { - can_err_irq(CAN_4, IRQ_OVERRUN); -} - -static void can0_passive_irq(void) { - can_err_irq(CAN_0, IRQ_PASSIVE); -} - -static void can1_passive_irq(void) { - can_err_irq(CAN_1, IRQ_PASSIVE); -} - -static void can2_passive_irq(void) { - can_err_irq(CAN_2, IRQ_PASSIVE); -} - -static void can3_passive_irq(void) { - can_err_irq(CAN_3, IRQ_PASSIVE); -} - -static void can4_passive_irq(void) { - can_err_irq(CAN_4, IRQ_PASSIVE); -} - -static void can0_arb_lost_irq(void) { - can_err_irq(CAN_0, IRQ_ARB); -} - -static void can1_arb_lost_irq(void) { - can_err_irq(CAN_1, IRQ_ARB); -} - -static void can2_arb_lost_irq(void) { - can_err_irq(CAN_2, IRQ_ARB); -} - -static void can3_arb_lost_irq(void) { - can_err_irq(CAN_3, IRQ_ARB); -} - -static void can4_arb_lost_irq(void) { - can_err_irq(CAN_4, IRQ_ARB); -} - -static void can0_bus_err_irq(void) { - can_err_irq(CAN_0, IRQ_BUS); -} - -static void can1_bus_err_irq(void) { - can_err_irq(CAN_1, IRQ_BUS); -} - -static void can2_bus_err_irq(void) { - can_err_irq(CAN_2, IRQ_BUS); -} - -static void can3_bus_err_irq(void) { - can_err_irq(CAN_3, IRQ_BUS); -} - -static void can4_bus_err_irq(void) { - can_err_irq(CAN_4, IRQ_BUS); -} - -void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) { - __IO uint32_t *dmy_ctr; - - /* determine the CAN to use */ - uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD); - uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD); - obj->ch = pinmap_merge(can_tx, can_rx); - MBED_ASSERT((int)obj->ch != NC); - - /* enable CAN clock */ - CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32); - /* Has CAN RAM initialisation completed ? */ - while ((RSCAN0GSTS & 0x08) == 0x08) { - __NOP(); - } - /* clear Global Stop mode bit */ - RSCAN0GCTR &= 0xFFFFFFFB; - /* clear Channel Stop mode bit */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr &= 0xFFFFFFFB; - /* Enter global reset mode */ - can_set_global_mode(GL_RESET); - /* Enter channel reset mode */ - can_set_channel_mode(obj->ch, CH_RESET); - /* reset register */ - can_reset_reg(obj); - - can_initialized[obj->ch] = 1; - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); - - /* pin out the can pins */ - pinmap_pinout(rd, PinMap_CAN_RD); - pinmap_pinout(td, PinMap_CAN_TD); - - /* set can frequency */ - can_frequency(obj, hz); -} - -void can_init(can_t *obj, PinName rd, PinName td) { - can_init_freq(obj, rd, td, 100000); -} - -void can_free(can_t *obj) { - /* disable CAN clock */ - CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32; -} - -int can_frequency(can_t *obj, int f) { - __IO uint32_t *dmy_cfcc; - int retval = 0; - - if (f <= 1000000) { - /* less than 1Mhz */ - /* set Channel Reset mode */ - can_set_channel_mode(obj->ch, CH_RESET); - can_set_frequency(obj, f); - /* set Channel Communication mode */ - can_set_channel_mode(obj->ch, CH_COMM); - /* restore CFE bit since it is cleared */ - /* Use send/receive FIFO buffer */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; - *dmy_cfcc |= 0x01; - dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; - *dmy_cfcc |= 0x01; - retval = 1; - } - - return retval; -} - -void can_reset(can_t *obj) { - /* Enter global reset mode */ - can_set_global_mode(GL_RESET); - /* Enter channel reset mode */ - can_set_channel_mode(obj->ch, CH_RESET); - /* reset register */ - can_reset_reg(obj); - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); -} - -int can_write(can_t *obj, CAN_Message msg, int cc) { - __IO uint32_t *dmy_sts; - __IO uint32_t *dmy_cfsts; - __IO uint32_t *dmy_cfid; - __IO uint32_t *dmy_cfptr; - __IO uint32_t *dmy_cfdf0; - __IO uint32_t *dmy_cfdf1; - __IO uint32_t *dmy_cfpctr; - int retval = 0; - - /* Wait to become channel communication mode */ - dmy_sts = STS_MATCH[obj->ch]; - while ((*dmy_sts & 0x07) != 0) { - __NOP(); - } - - if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) { - /* send/receive FIFO buffer isn't full */ - dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND]; - if ((*dmy_cfsts & 0x02) != 0x02) { - /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */ - dmy_cfid = CFID_TBL[obj->ch][CAN_SEND]; - *dmy_cfid = ((msg.format << 31) | (msg.type << 30)); - if (msg.format == CANStandard) { - *dmy_cfid |= (msg.id & 0x07FF); - } else { - *dmy_cfid |= (msg.id & 0x1FFFFFFF); - } - /* set length */ - dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND]; - *dmy_cfptr = msg.len << 28; - /* set data */ - dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND]; - memcpy((void *)dmy_cfdf0, &msg.data[0], 4); - dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND]; - memcpy((void *)dmy_cfdf1, &msg.data[4], 4); - /* send request */ - dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND]; - *dmy_cfpctr = 0xFF; - retval = 1; - } - } - - return retval; -} - -int can_read(can_t *obj, CAN_Message *msg, int handle) { - __IO uint32_t *dmy_sts; - __IO uint32_t *dmy_cfsts; - __IO uint32_t *dmy_cfid; - __IO uint32_t *dmy_cfptr; - __IO uint32_t *dmy_cfdf0; - __IO uint32_t *dmy_cfdf1; - __IO uint32_t *dmy_cfpctr; - int retval = 0; - - /* Wait to become channel communication mode */ - dmy_sts = STS_MATCH[obj->ch]; - while ((*dmy_sts & 0x07) != 0) { - __NOP(); - } - - /* send/receive FIFO buffer isn't empty */ - dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV]; - while ((*dmy_cfsts & 0x01) != 0x01) { - /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */ - dmy_cfid = CFID_TBL[obj->ch][CAN_RECV]; - msg->format = (CANFormat)(*dmy_cfid >> 31); - msg->type = (CANType)((*dmy_cfid >> 30) & 0x1); - if (msg->format == CANStandard) { - msg->id = (*dmy_cfid & 0x07FF); - } else { - msg->id = (*dmy_cfid & 0x1FFFFFFF); - } - /* get length */ - dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV]; - msg->len = (unsigned char)(*dmy_cfptr >> 28); - /* get data */ - dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV]; - memcpy(&msg->data[0], (void *)dmy_cfdf0, 4); - dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV]; - memcpy(&msg->data[4], (void *)dmy_cfdf1, 4); - /* receive(next data) request */ - dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV]; - *dmy_cfpctr = 0xFF; - retval = 1; - } - - return retval; -} - -unsigned char can_rderror(can_t *obj) { - __IO uint32_t *dmy_sts; - - dmy_sts = STS_MATCH[obj->ch]; - return (unsigned char)((*dmy_sts >> 16) & 0xFF); -} - -unsigned char can_tderror(can_t *obj) { - __IO uint32_t *dmy_sts; - - dmy_sts = STS_MATCH[obj->ch]; - return (unsigned char)((*dmy_sts >> 24) & 0xFF); -} - -int can_mode(can_t *obj, CanMode mode) { - __IO uint32_t *dmy_ctr; - __IO uint32_t *dmy_sts; - __IO uint32_t *dmy_cfcc; - int ch_cnt; - can_t *tmp_obj; - tmp_obj = obj; - int retval = 1; - - switch (mode) { - case MODE_RESET: - can_set_global_mode(GL_RESET); - can_set_channel_mode(obj->ch, CH_RESET); - for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) { - can_initialized[ch_cnt] = 0; - } - break; - case MODE_NORMAL: - can_set_global_mode(GL_OPE); - can_set_channel_mode(obj->ch, CH_COMM); - break; - case MODE_SILENT: - can_set_channel_mode(obj->ch, CH_HOLD); - /* set listen only mode, enable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000); - can_set_channel_mode(obj->ch, CH_COMM); - break; - case MODE_TEST_LOCAL: - can_set_channel_mode(obj->ch, CH_HOLD); - /* set self test mode 0, enable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000); - can_set_channel_mode(obj->ch, CH_COMM); - break; - case MODE_TEST_GLOBAL: - /* set the channel between the communication test on channel 1 and channel 2 */ - /* set Channel Hold mode */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { - dmy_sts = STS_MATCH[tmp_obj->ch]; - if ((*dmy_sts & 0x04) == 0x04) { - /* Channel Stop mode */ - /* clear Channel Stop mode bit */ - dmy_ctr = CTR_MATCH[tmp_obj->ch]; - *dmy_ctr &= 0xFFFFFFFB; - can_set_channel_mode(tmp_obj->ch, CH_RESET); - } - can_set_channel_mode(tmp_obj->ch, CH_HOLD); - } - can_set_global_mode(GL_TEST); - /* enable communication test between channel1 and channel2 */ - RSCAN0GTSTCFG = 0x06; - RSCAN0GTSTCTR = 0x01; - /* send and receive setting of channel1 and channel2 */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { - can_reset_buffer(tmp_obj); - /* set global interrrupt */ - /* THLEIE, MEIE and DEIE interrupts are disable */ - RSCAN0GCTR &= 0xFFFFF8FF; - /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */ - /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */ - dmy_ctr = CTR_MATCH[tmp_obj->ch]; - *dmy_ctr &= 0x00018700; - can_set_global_mode(GL_OPE); - can_set_channel_mode(tmp_obj->ch, CH_COMM); - /* Use send/receive FIFO buffer */ - dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND]; - *dmy_cfcc |= 0x01; - dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV]; - *dmy_cfcc |= 0x01; - } - break; - case MODE_TEST_SILENT: - /* not supported */ - /* fall through */ - default: - retval = 0; - break; - } - - return retval; -} - -int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { - int retval = 0; - - if ((format == CANStandard) || (format == CANExtended)) { - if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) { - /* set Global Reset mode and Channel Reset mode */ - can_set_global_mode(GL_RESET); - can_set_channel_mode(obj->ch, CH_RESET); - /* enable receive rule table writing */ - RSCAN0GAFLECTR = 0x00000100; - /* set the page number of receive rule table(page number = 0) */ - RSCAN0GAFLECTR |= (obj->ch * 4); - /* set IDE format */ - *dmy_gaflid = (format << 31); - if (format == CANExtended) { - /* set receive rule ID for bit28-0 */ - *dmy_gaflid |= (id & 0x1FFFFFFF); - } else { - /* set receive rule ID for bit10-0 */ - *dmy_gaflid |= (id & 0x07FF); - } - /* set ID mask bit */ - *dmy_gaflm = (0xC0000000 | mask); - /* disable receive rule table writing */ - RSCAN0GAFLECTR &= 0xFFFFFEFF; - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); - retval = 1; - } - } - - return retval; -} - -void can_monitor(can_t *obj, int silent) { - __IO uint32_t *dmy_ctr; - - /* set Channel Hold mode */ - can_set_channel_mode(obj->ch, CH_HOLD); - if (silent) { - /* set listen only mode, enable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000); - can_set_channel_mode(obj->ch, CH_COMM); - } else { - /* set normal test mode, disable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr &= 0x00FFFFFF; - /* reset register */ - can_reset_reg(obj); - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); - } -} - -static void can_reset_reg(can_t *obj) { - __IO uint32_t *dmy_ctr; - - /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */ - /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */ - RSCAN0GCFG = 0x00000003; - /* set default frequency at 100k */ - can_set_frequency(obj, 100000); - /* set receive rule */ - can_reset_recv_rule(obj); - /* set buffer */ - can_reset_buffer(obj); - /* set global interrrupt */ - /* THLEIE, MEIE and DEIE interrupts are disable */ - RSCAN0GCTR &= 0xFFFFF8FF; - /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr &= 0xFFFF00FF; -} - -static void can_reset_recv_rule(can_t *obj) { - /* number of receive rules of each chanel = 64 */ - RSCAN0GAFLCFG0 = 0x40404040; - RSCAN0GAFLCFG1 = 0x40000000; - /* enable receive rule table writing */ - RSCAN0GAFLECTR = 0x00000100; - /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */ - RSCAN0GAFLECTR |= (obj->ch * 4); - /* set standard ID, data frame and receive rule ID */ - *dmy_gaflid = 0x07FF; - /* IDE bit, RTR bit and ID bit(28-0) are not compared */ - *dmy_gaflm = 0; - /* DLC check is 1 bytes, not use a receive buffer */ - *dmy_gaflp0 = 0x10000000; - /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */ - *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3)); - /* disable receive rule table writing */ - RSCAN0GAFLECTR &= 0xFFFFFEFF; -} - -static void can_reset_buffer(can_t *obj) { - __IO uint32_t *dmy_rfcc; - __IO uint32_t *dmy_cfcc; - __IO uint32_t *dmy_txqcc; - __IO uint32_t *dmy_thlcc; - int cnt; - - /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */ - /* number of rows of send/receive FIFO buffer = 4 */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; - *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; - *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */ - /* receive buffer is not used */ - RSCAN0RMNB = 0; - /* receive FIFO buffer is not used */ - for (cnt = 0; cnt < 8; cnt++) { - dmy_rfcc = RFCC_MATCH[cnt]; - *dmy_rfcc = 0; - } - /* send queue is not used */ - dmy_txqcc = TXQCC_MATCH[obj->ch]; - *dmy_txqcc = 0; - /* send history is not used */ - dmy_thlcc = THLCC_MATCH[obj->ch]; - *dmy_thlcc = 0; - - /* CFTXIE and CFRXIE interrupts are enable */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; - *dmy_cfcc |= 0x04; - dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; - *dmy_cfcc |= 0x02; - /* TMIEp interrupt is disable */ - RSCAN0TMIEC0 = 0x00000000; - RSCAN0TMIEC1 = 0x00000000; - RSCAN0TMIEC2 = 0x00000000; -} - -static void can_reconfigure_channel(void) { - __IO uint32_t *dmy_cfcc; - int ch_cnt; - - for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) { - if (can_initialized[ch_cnt] == 1) { - /* set Global Operation mode and Channel Communication mode */ - can_set_global_mode(GL_OPE); - can_set_channel_mode(ch_cnt, CH_COMM); - /* Use send/receive FIFO buffer */ - dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND]; - *dmy_cfcc |= 0x01; - dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV]; - *dmy_cfcc |= 0x01; - } - } -} - -static void can_set_frequency(can_t *obj, int f) { - __IO uint32_t *dmy_cfg; - int oldfreq = 0; - int newfreq = 0; - uint32_t clkc_val; - uint8_t tmp_tq; - uint8_t tq = 0; - uint8_t tmp_brp; - uint8_t brp = 0; - uint8_t tseg1 = 0; - uint8_t tseg2 = 0; - uint8_t sjw = 0; - - /* set clkc */ - if (RZ_A1_IsClockMode0() == false) { - clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2; - } else { - clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2; - } - /* calculate BRP bit and Choose max value of calculated frequency */ - for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) { - /* f = fCAN / ((BRP+1) * Tq) */ - /* BRP = (fCAN / (f * Tq)) - 1 */ - tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry) - newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq); - if (newfreq >= oldfreq) { - oldfreq = newfreq; - tq = tmp_tq; - brp = tmp_brp; - } - } - /* calculate TSEG1 bit and TSEG2 bit */ - tseg1 = (tq - 1) * 0.666666667; - tseg2 = (tq - 1) - tseg1; - sjw = (tseg2 > 4)? 4 : tseg2; - /* set RSCAN0CmCFG register */ - dmy_cfg = CFG_MATCH[obj->ch]; - *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp; -} - -static void can_set_global_mode(int mode) { - /* set Global mode */ - RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode); - /* Wait to cahnge into Global XXXX mode */ - while ((RSCAN0GSTS & 0x07) != mode) { - __NOP(); - } -} - -static void can_set_channel_mode(uint32_t ch, int mode) { - __IO uint32_t *dmy_ctr; - __IO uint32_t *dmy_sts; - - /* set Channel mode */ - dmy_ctr = CTR_MATCH[ch]; - *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode); - /* Wait to cahnge into Channel XXXX mode */ - dmy_sts = STS_MATCH[ch]; - while ((*dmy_sts & 0x07) != mode) { - __NOP(); - } -} - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h deleted file mode 100644 index 323884e05eb..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** -* @file RZ_A1_Init.h -* $Rev: 531 $ -* $Date:: 2013-04-16 13:07:35 +0900#$ -* @brief RZ_A1 Initialize -******************************************************************************/ - -#ifndef RZ_A1_INIT_H -#define RZ_A1_INIT_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include -#include -#include "iodefine.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ - -/****************************************************************************** -Variable Externs -******************************************************************************/ - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -void RZ_A1_SetSramWriteEnable(void); -void RZ_A1_InitClock(void); -int RZ_A1_IsClockMode0(void); -void RZ_A1_InitBus(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* RZ_A1_INIT_H */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h deleted file mode 100644 index deb2ebbc131..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h +++ /dev/null @@ -1,85 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/****************************************************************************** -* File Name : dev_drv.h -* $Rev: 809 $ -* $Date:: 2014-04-09 15:06:36 +0900#$ -* Description : Device driver header -******************************************************************************/ -#ifndef DEV_DRV_H -#define DEV_DRV_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ - - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - - -/****************************************************************************** -Macro definitions -******************************************************************************/ -/* ==== Arguments, Return values ==== */ -#define DEVDRV_SUCCESS (0) /* Success */ -#define DEVDRV_ERROR (-1) /* Failure */ - -/* ==== Flags ==== */ -#define DEVDRV_FLAG_OFF (0) /* Flag OFF */ -#define DEVDRV_FLAG_ON (1) /* Flag ON */ - -/* ==== Channels ==== */ -typedef enum devdrv_ch -{ - DEVDRV_CH_0, /* Channel 0 */ - DEVDRV_CH_1, /* Channel 1 */ - DEVDRV_CH_2, /* Channel 2 */ - DEVDRV_CH_3, /* Channel 3 */ - DEVDRV_CH_4, /* Channel 4 */ - DEVDRV_CH_5, /* Channel 5 */ - DEVDRV_CH_6, /* Channel 6 */ - DEVDRV_CH_7, /* Channel 7 */ - DEVDRV_CH_8, /* Channel 8 */ - DEVDRV_CH_9, /* Channel 9 */ - DEVDRV_CH_10, /* Channel 10 */ - DEVDRV_CH_11, /* Channel 11 */ - DEVDRV_CH_12, /* Channel 12 */ - DEVDRV_CH_13, /* Channel 13 */ - DEVDRV_CH_14, /* Channel 14 */ - DEVDRV_CH_15 /* Channel 15 */ -} devdrv_ch_t; - -/****************************************************************************** -Variable Externs -******************************************************************************/ - - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -#endif /* DEV_DRV_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.h deleted file mode 100644 index d4cbfd81ab4..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.h +++ /dev/null @@ -1,316 +0,0 @@ -/**************************************************************************//** - * @file gic.h - * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 29 August 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef GIC_H_ -#define GIC_H_ - -/* IO definitions (access restrictions to peripheral registers) */ -/** -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) - */ -typedef struct -{ - __IO uint32_t ICDDCR; - __I uint32_t ICDICTR; - __I uint32_t ICDIIDR; - uint32_t RESERVED0[29]; - __IO uint32_t ICDISR[32]; - __IO uint32_t ICDISER[32]; - __IO uint32_t ICDICER[32]; - __IO uint32_t ICDISPR[32]; - __IO uint32_t ICDICPR[32]; - __I uint32_t ICDABR[32]; - uint32_t RESERVED1[32]; - __IO uint32_t ICDIPR[256]; - __IO uint32_t ICDIPTR[256]; - __IO uint32_t ICDICFR[64]; - uint32_t RESERVED2[128]; - __IO uint32_t ICDSGIR; -} GICDistributor_Type; - -/** \brief Structure type to access the Controller Interface (GICC) - */ -typedef struct -{ - __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register - __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register - __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register - __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register - __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register - __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register - __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register - __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register - - uint32_t RESERVED[55]; - - __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register -} GICInterface_Type; - -/*@} end of GICD */ - -/* ########################## GIC functions #################################### */ -/** \brief Functions that manage interrupts via the GIC. - @{ - */ - -/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface - - Enables the forwarding of pending interrupts to the CPU interfaces. - - */ -void GIC_EnableDistributor(void); - -/** \brief Disable Distributor - - Disables the forwarding of pending interrupts to the CPU interfaces. - - */ -void GIC_DisableDistributor(void); - -/** \brief Provides information about the configuration of the GIC. - Provides information about the configuration of the GIC. - - whether the GIC implements the Security Extensions - - the maximum number of interrupt IDs that the GIC supports - - the number of CPU interfaces implemented - - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). - - \return Distributor Information. - */ -uint32_t GIC_DistributorInfo(void); - -/** \brief Distributor Implementer Identification Register. - - Distributor Implementer Identification Register - - \return Implementer Information. - */ -uint32_t GIC_DistributorImplementer(void); - -/** \brief Set list of processors that the interrupt is sent to if it is asserted. - - The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. - This field stores the list of processors that the interrupt is sent to if it is asserted. - - \param [in] IRQn Interrupt number. - \param [in] target CPU target - */ -void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); - -/** \brief Get list of processors that the interrupt is sent to if it is asserted. - - The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. - This field stores the list of processors that the interrupt is sent to if it is asserted. - - \param [in] IRQn Interrupt number. - \param [in] target CPU target -*/ -uint32_t GIC_GetTarget(IRQn_Type IRQn); - -/** \brief Enable Interface - - Enables the signalling of interrupts to the target processors. - - */ -void GIC_EnableInterface(void); - -/** \brief Disable Interface - - Disables the signalling of interrupts to the target processors. - - */ -void GIC_DisableInterface(void); - -/** \brief Acknowledge Interrupt - - The function acknowledges the highest priority pending interrupt and returns its IRQ number. - - \return Interrupt number - */ -IRQn_Type GIC_AcknowledgePending(void); - -/** \brief End Interrupt - - The function writes the end of interrupt register, indicating that handling of the interrupt is complete. - - \param [in] IRQn Interrupt number. - */ -void GIC_EndInterrupt(IRQn_Type IRQn); - - -/** \brief Enable Interrupt - - Set-enable bit for each interrupt supported by the GIC. - - \param [in] IRQn External interrupt number. - */ -void GIC_EnableIRQ(IRQn_Type IRQn); - -/** \brief Disable Interrupt - - Clear-enable bit for each interrupt supported by the GIC. - - \param [in] IRQn Number of the external interrupt to disable - */ -void GIC_DisableIRQ(IRQn_Type IRQn); - -/** \brief Set Pending Interrupt - - Set-pending bit for each interrupt supported by the GIC. - - \param [in] IRQn Interrupt number. - */ -void GIC_SetPendingIRQ(IRQn_Type IRQn); - -/** \brief Clear Pending Interrupt - - Clear-pending bit for each interrupt supported by the GIC - - \param [in] IRQn Number of the interrupt for clear pending - */ -void GIC_ClearPendingIRQ(IRQn_Type IRQn); - -/** \brief Int_config field for each interrupt supported by the GIC. - - This field identifies whether the corresponding interrupt is: - (1) edge-triggered or (0) level-sensitive - (1) 1-N model or (0) N-N model - - \param [in] IRQn Interrupt number. - \param [in] edge_level (1) edge-triggered or (0) level-sensitive - \param [in] model (1) 1-N model or (0) N-N model - */ -void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - */ -uint32_t GIC_GetPriority(IRQn_Type IRQn); - -/** \brief CPU Interface Priority Mask Register - - The priority mask level for the CPU interface. If the priority of an interrupt is higher than the - value indicated by this field, the interface signals the interrupt to the processor. - - \param [in] Mask. - */ -void GIC_InterfacePriorityMask(uint32_t priority); - -/** \brief Set the binary point. - - Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. - - \param [in] Mask. - */ -void GIC_SetBinaryPoint(uint32_t binary_point); - -/** \brief Get the binary point. - - Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. - - \return Binary point. - */ -uint32_t GIC_GetBinaryPoint(uint32_t binary_point); - -/** \brief Get Interrupt state. - - Get the interrupt state, whether pending and/or active - - \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active - */ -uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); - -/** \brief Send Software Generated interrupt - - Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. -GIC_InterfacePriorityMask - \param [in] IRQn The Interrupt ID of the SGI. - \param [in] target_list CPUTargetList - \param [in] filter_list TargetListFilter - */ -void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); - -/** \brief API call to initialise the interrupt distributor - - API call to initialise the interrupt distributor - - */ -void GIC_DistInit(void); - -/** \brief API call to initialise the CPU interface - - API call to initialise the CPU interface - - */ -void GIC_CPUInterfaceInit(void); - -/** \brief API call to set the Interrupt Configuration Registers - - API call to initialise the Interrupt Configuration Registers - - */ -void GIC_SetICDICFR (const uint32_t *ICDICFRn); - -/** \brief API call to Enable the GIC - - API call to Enable the GIC - - */ -void GIC_Enable(void); - -#endif /* GIC_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefine.h deleted file mode 100644 index 2d185599826..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefine.h +++ /dev/null @@ -1,136 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register (V1.00a) -******************************************************************************/ -#ifndef R7S72100_IODEFINE_H -#define R7S72100_IODEFINE_H -#define IODEFINE_H_VERSION 100 - -enum iodefine_byte_select_t -{ - L = 0, H = 1, - LL= 0, LH = 1, HL = 2, HH = 3 -}; - -/*********************************************************************** - <<< [iodefine_reg32_t] >>> -- Padding : sizeof(iodefine_reg32_t) == 4 -- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg32_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ - volatile uint8_t UINT8[4]; /* 8-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - -/*********************************************************************** - <<< [iodefine_reg32_16_t] >>> -- Padding : sizeof(iodefine_reg32_16_t) == 4 -- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg32_16_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - -/*********************************************************************** - <<< [iodefine_reg16_8_t] >>> -- Padding : sizeof(iodefine_reg16_8_t) == 2 -- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - - - - - - -#include "adc_iodefine.h" /* (V1.00a) */ -#include "bsc_iodefine.h" /* (V1.00a) */ -#include "ceu_iodefine.h" /* (V1.00a) */ -#include "cpg_iodefine.h" /* (V1.00a) */ -#include "disc_iodefine.h" /* (V1.00a) */ -#include "dmac_iodefine.h" /* (V1.00a) */ -#include "dvdec_iodefine.h" /* (V1.00a) */ -#include "ether_iodefine.h" /* (V1.00a) */ -#include "flctl_iodefine.h" /* (V1.00a) */ -#include "gpio_iodefine.h" /* (V1.00a) */ -#include "ieb_iodefine.h" /* (V1.00a) */ -#include "inb_iodefine.h" /* (V1.00a) */ -#include "intc_iodefine.h" /* (V1.00a) */ -#include "irda_iodefine.h" /* (V1.00a) */ -#include "jcu_iodefine.h" /* (V1.00a) */ -#include "l2c_iodefine.h" /* (V1.00a) */ -#include "lin_iodefine.h" /* (V1.00a) */ -#include "lvds_iodefine.h" /* (V1.00a) */ -#include "mlb_iodefine.h" /* (V1.00a) */ -#include "mmc_iodefine.h" /* (V1.00a) */ -#include "mtu2_iodefine.h" /* (V1.00a) */ -#include "ostm_iodefine.h" /* (V1.00a) */ -#include "pfv_iodefine.h" /* (V1.00a) */ -#include "pwm_iodefine.h" /* (V1.00a) */ -#include "riic_iodefine.h" /* (V1.00a) */ -#include "romdec_iodefine.h" /* (V1.00a) */ -#include "rscan0_iodefine.h" /* (V1.00a) */ -#include "rspi_iodefine.h" /* (V1.00a) */ -#include "rtc_iodefine.h" /* (V1.00a) */ -#include "scif_iodefine.h" /* (V1.00a) */ -#include "scim_iodefine.h" /* (V1.00a) */ -#include "scux_iodefine.h" /* (V1.00a) */ -#include "sdg_iodefine.h" /* (V1.00a) */ -#include "spdif_iodefine.h" /* (V1.00a) */ -#include "spibsc_iodefine.h" /* (V1.00a) */ -#include "ssif_iodefine.h" /* (V1.00a) */ -#include "usb20_iodefine.h" /* (V1.00a) */ -#include "vdc5_iodefine.h" /* (V1.00a) */ -#include "wdt_iodefine.h" /* (V1.00a) */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h deleted file mode 100644 index 9daefe447a1..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h +++ /dev/null @@ -1,556 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : riic_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register (V1.00a) -******************************************************************************/ -#ifndef RIIC_IODEFINE_H -#define RIIC_IODEFINE_H - -#include "reg32_t.h" - -struct st_riic -{ /* RIIC */ -#define RIICnCRm_COUNT 2 - union reg32_t RIICnCR1; /* RIICnCR1 */ - union reg32_t RIICnCR2; /* RIICnCR2 */ -#define RIICnMRm_COUNT 3 - union reg32_t RIICnMR1; /* RIICnMR1 */ - union reg32_t RIICnMR2; /* RIICnMR2 */ - union reg32_t RIICnMR3; /* RIICnMR3 */ - union reg32_t RIICnFER; /* RIICnFER */ - union reg32_t RIICnSER; /* RIICnSER */ - union reg32_t RIICnIER; /* RIICnIER */ -#define RIICnSRm_COUNT 2 - union reg32_t RIICnSR1; /* RIICnSR1 */ - union reg32_t RIICnSR2; /* RIICnSR2 */ -#define RIICnSARm_COUNT 3 - union reg32_t RIICnSAR0; /* RIICnSAR0 */ - union reg32_t RIICnSAR1; /* RIICnSAR1 */ - union reg32_t RIICnSAR2; /* RIICnSAR2 */ - union reg32_t RIICnBRL; /* RIICnBRL */ - union reg32_t RIICnBRH; /* RIICnBRH */ - union reg32_t RIICnDRT; /* RIICnDRT */ - union reg32_t RIICnDRR; /* RIICnDRR */ - -}; - - -#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ -#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ -#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */ -#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ - - -/* Start of channnel array defines of RIIC */ - -/* Channnel array defines of RIIC */ -/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ -#define RIIC_COUNT 4 -#define RIIC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of RIIC */ - - -#define RIIC0CR1 RIIC0.RIICnCR1.UINT32 -#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L] -#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL] -#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH] -#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H] -#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL] -#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH] -#define RIIC0CR2 RIIC0.RIICnCR2.UINT32 -#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L] -#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL] -#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH] -#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H] -#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL] -#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH] -#define RIIC0MR1 RIIC0.RIICnMR1.UINT32 -#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L] -#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL] -#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH] -#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H] -#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL] -#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH] -#define RIIC0MR2 RIIC0.RIICnMR2.UINT32 -#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L] -#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL] -#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH] -#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H] -#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL] -#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH] -#define RIIC0MR3 RIIC0.RIICnMR3.UINT32 -#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L] -#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL] -#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH] -#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H] -#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL] -#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH] -#define RIIC0FER RIIC0.RIICnFER.UINT32 -#define RIIC0FERL RIIC0.RIICnFER.UINT16[L] -#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL] -#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH] -#define RIIC0FERH RIIC0.RIICnFER.UINT16[H] -#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL] -#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH] -#define RIIC0SER RIIC0.RIICnSER.UINT32 -#define RIIC0SERL RIIC0.RIICnSER.UINT16[L] -#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL] -#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH] -#define RIIC0SERH RIIC0.RIICnSER.UINT16[H] -#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL] -#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH] -#define RIIC0IER RIIC0.RIICnIER.UINT32 -#define RIIC0IERL RIIC0.RIICnIER.UINT16[L] -#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL] -#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH] -#define RIIC0IERH RIIC0.RIICnIER.UINT16[H] -#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL] -#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH] -#define RIIC0SR1 RIIC0.RIICnSR1.UINT32 -#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L] -#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL] -#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH] -#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H] -#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL] -#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH] -#define RIIC0SR2 RIIC0.RIICnSR2.UINT32 -#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L] -#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL] -#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH] -#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H] -#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL] -#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH] -#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32 -#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L] -#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL] -#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH] -#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H] -#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL] -#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH] -#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32 -#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L] -#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL] -#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH] -#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H] -#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL] -#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH] -#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32 -#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L] -#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL] -#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH] -#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H] -#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL] -#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH] -#define RIIC0BRL RIIC0.RIICnBRL.UINT32 -#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L] -#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL] -#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH] -#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H] -#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL] -#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH] -#define RIIC0BRH RIIC0.RIICnBRH.UINT32 -#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L] -#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL] -#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH] -#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H] -#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL] -#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH] -#define RIIC0DRT RIIC0.RIICnDRT.UINT32 -#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L] -#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL] -#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH] -#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H] -#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL] -#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH] -#define RIIC0DRR RIIC0.RIICnDRR.UINT32 -#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L] -#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL] -#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH] -#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H] -#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL] -#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH] -#define RIIC1CR1 RIIC1.RIICnCR1.UINT32 -#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L] -#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL] -#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH] -#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H] -#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL] -#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH] -#define RIIC1CR2 RIIC1.RIICnCR2.UINT32 -#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L] -#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL] -#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH] -#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H] -#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL] -#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH] -#define RIIC1MR1 RIIC1.RIICnMR1.UINT32 -#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L] -#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL] -#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH] -#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H] -#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL] -#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH] -#define RIIC1MR2 RIIC1.RIICnMR2.UINT32 -#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L] -#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL] -#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH] -#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H] -#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL] -#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH] -#define RIIC1MR3 RIIC1.RIICnMR3.UINT32 -#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L] -#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL] -#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH] -#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H] -#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL] -#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH] -#define RIIC1FER RIIC1.RIICnFER.UINT32 -#define RIIC1FERL RIIC1.RIICnFER.UINT16[L] -#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL] -#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH] -#define RIIC1FERH RIIC1.RIICnFER.UINT16[H] -#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL] -#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH] -#define RIIC1SER RIIC1.RIICnSER.UINT32 -#define RIIC1SERL RIIC1.RIICnSER.UINT16[L] -#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL] -#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH] -#define RIIC1SERH RIIC1.RIICnSER.UINT16[H] -#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL] -#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH] -#define RIIC1IER RIIC1.RIICnIER.UINT32 -#define RIIC1IERL RIIC1.RIICnIER.UINT16[L] -#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL] -#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH] -#define RIIC1IERH RIIC1.RIICnIER.UINT16[H] -#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL] -#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH] -#define RIIC1SR1 RIIC1.RIICnSR1.UINT32 -#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L] -#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL] -#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH] -#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H] -#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL] -#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH] -#define RIIC1SR2 RIIC1.RIICnSR2.UINT32 -#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L] -#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL] -#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH] -#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H] -#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL] -#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH] -#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32 -#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L] -#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL] -#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH] -#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H] -#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL] -#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH] -#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32 -#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L] -#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL] -#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH] -#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H] -#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL] -#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH] -#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32 -#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L] -#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL] -#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH] -#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H] -#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL] -#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH] -#define RIIC1BRL RIIC1.RIICnBRL.UINT32 -#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L] -#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL] -#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH] -#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H] -#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL] -#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH] -#define RIIC1BRH RIIC1.RIICnBRH.UINT32 -#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L] -#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL] -#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH] -#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H] -#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL] -#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH] -#define RIIC1DRT RIIC1.RIICnDRT.UINT32 -#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L] -#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL] -#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH] -#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H] -#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL] -#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH] -#define RIIC1DRR RIIC1.RIICnDRR.UINT32 -#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L] -#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL] -#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH] -#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H] -#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL] -#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH] -#define RIIC2CR1 RIIC2.RIICnCR1.UINT32 -#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L] -#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL] -#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH] -#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H] -#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL] -#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH] -#define RIIC2CR2 RIIC2.RIICnCR2.UINT32 -#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L] -#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL] -#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH] -#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H] -#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL] -#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH] -#define RIIC2MR1 RIIC2.RIICnMR1.UINT32 -#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L] -#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL] -#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH] -#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H] -#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL] -#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH] -#define RIIC2MR2 RIIC2.RIICnMR2.UINT32 -#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L] -#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL] -#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH] -#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H] -#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL] -#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH] -#define RIIC2MR3 RIIC2.RIICnMR3.UINT32 -#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L] -#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL] -#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH] -#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H] -#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL] -#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH] -#define RIIC2FER RIIC2.RIICnFER.UINT32 -#define RIIC2FERL RIIC2.RIICnFER.UINT16[L] -#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL] -#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH] -#define RIIC2FERH RIIC2.RIICnFER.UINT16[H] -#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL] -#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH] -#define RIIC2SER RIIC2.RIICnSER.UINT32 -#define RIIC2SERL RIIC2.RIICnSER.UINT16[L] -#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL] -#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH] -#define RIIC2SERH RIIC2.RIICnSER.UINT16[H] -#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL] -#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH] -#define RIIC2IER RIIC2.RIICnIER.UINT32 -#define RIIC2IERL RIIC2.RIICnIER.UINT16[L] -#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL] -#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH] -#define RIIC2IERH RIIC2.RIICnIER.UINT16[H] -#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL] -#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH] -#define RIIC2SR1 RIIC2.RIICnSR1.UINT32 -#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L] -#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL] -#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH] -#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H] -#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL] -#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH] -#define RIIC2SR2 RIIC2.RIICnSR2.UINT32 -#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L] -#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL] -#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH] -#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H] -#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL] -#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH] -#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32 -#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L] -#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL] -#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH] -#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H] -#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL] -#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH] -#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32 -#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L] -#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL] -#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH] -#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H] -#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL] -#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH] -#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32 -#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L] -#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL] -#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH] -#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H] -#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL] -#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH] -#define RIIC2BRL RIIC2.RIICnBRL.UINT32 -#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L] -#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL] -#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH] -#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H] -#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL] -#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH] -#define RIIC2BRH RIIC2.RIICnBRH.UINT32 -#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L] -#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL] -#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH] -#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H] -#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL] -#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH] -#define RIIC2DRT RIIC2.RIICnDRT.UINT32 -#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L] -#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL] -#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH] -#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H] -#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL] -#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH] -#define RIIC2DRR RIIC2.RIICnDRR.UINT32 -#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L] -#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL] -#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH] -#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H] -#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL] -#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH] -#define RIIC3CR1 RIIC3.RIICnCR1.UINT32 -#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L] -#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL] -#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH] -#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H] -#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL] -#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH] -#define RIIC3CR2 RIIC3.RIICnCR2.UINT32 -#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L] -#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL] -#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH] -#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H] -#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL] -#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH] -#define RIIC3MR1 RIIC3.RIICnMR1.UINT32 -#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L] -#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL] -#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH] -#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H] -#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL] -#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH] -#define RIIC3MR2 RIIC3.RIICnMR2.UINT32 -#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L] -#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL] -#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH] -#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H] -#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL] -#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH] -#define RIIC3MR3 RIIC3.RIICnMR3.UINT32 -#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L] -#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL] -#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH] -#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H] -#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL] -#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH] -#define RIIC3FER RIIC3.RIICnFER.UINT32 -#define RIIC3FERL RIIC3.RIICnFER.UINT16[L] -#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL] -#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH] -#define RIIC3FERH RIIC3.RIICnFER.UINT16[H] -#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL] -#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH] -#define RIIC3SER RIIC3.RIICnSER.UINT32 -#define RIIC3SERL RIIC3.RIICnSER.UINT16[L] -#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL] -#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH] -#define RIIC3SERH RIIC3.RIICnSER.UINT16[H] -#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL] -#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH] -#define RIIC3IER RIIC3.RIICnIER.UINT32 -#define RIIC3IERL RIIC3.RIICnIER.UINT16[L] -#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL] -#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH] -#define RIIC3IERH RIIC3.RIICnIER.UINT16[H] -#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL] -#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH] -#define RIIC3SR1 RIIC3.RIICnSR1.UINT32 -#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L] -#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL] -#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH] -#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H] -#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL] -#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH] -#define RIIC3SR2 RIIC3.RIICnSR2.UINT32 -#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L] -#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL] -#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH] -#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H] -#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL] -#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH] -#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32 -#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L] -#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL] -#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH] -#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H] -#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL] -#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH] -#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32 -#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L] -#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL] -#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH] -#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H] -#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL] -#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH] -#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32 -#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L] -#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL] -#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH] -#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H] -#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL] -#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH] -#define RIIC3BRL RIIC3.RIICnBRL.UINT32 -#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L] -#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL] -#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH] -#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H] -#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL] -#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH] -#define RIIC3BRH RIIC3.RIICnBRH.UINT32 -#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L] -#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL] -#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH] -#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H] -#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL] -#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH] -#define RIIC3DRT RIIC3.RIICnDRT.UINT32 -#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L] -#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL] -#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH] -#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H] -#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL] -#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH] -#define RIIC3DRR RIIC3.RIICnDRR.UINT32 -#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L] -#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL] -#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH] -#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H] -#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL] -#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH] -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h deleted file mode 100644 index 1698f027ccf..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h +++ /dev/null @@ -1,9038 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rscan0_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register (V1.00a) -******************************************************************************/ -#ifndef RSCAN0_IODEFINE_H -#define RSCAN0_IODEFINE_H -/* ->QAC 0639 : Over 127 members (C90) */ -/* ->QAC 0857 : Over 1024 #define (C90) */ -/* ->SEC M1.10.1 : Not magic number */ - -struct st_rscan0 -{ /* RSCAN0 */ -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C0CFG; /* C0CFG */ - union iodefine_reg32_t C0CTR; /* C0CTR */ - union iodefine_reg32_t C0STS; /* C0STS */ - union iodefine_reg32_t C0ERFL; /* C0ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C1CFG; /* C1CFG */ - union iodefine_reg32_t C1CTR; /* C1CTR */ - union iodefine_reg32_t C1STS; /* C1STS */ - union iodefine_reg32_t C1ERFL; /* C1ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C2CFG; /* C2CFG */ - union iodefine_reg32_t C2CTR; /* C2CTR */ - union iodefine_reg32_t C2STS; /* C2STS */ - union iodefine_reg32_t C2ERFL; /* C2ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C3CFG; /* C3CFG */ - union iodefine_reg32_t C3CTR; /* C3CTR */ - union iodefine_reg32_t C3STS; /* C3STS */ - union iodefine_reg32_t C3ERFL; /* C3ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C4CFG; /* C4CFG */ - union iodefine_reg32_t C4CTR; /* C4CTR */ - union iodefine_reg32_t C4STS; /* C4STS */ - union iodefine_reg32_t C4ERFL; /* C4ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - - volatile uint8_t dummy159[52]; /* */ - union iodefine_reg32_t GCFG; /* GCFG */ - union iodefine_reg32_t GCTR; /* GCTR */ - union iodefine_reg32_t GSTS; /* GSTS */ - union iodefine_reg32_t GERFL; /* GERFL */ - union iodefine_reg32_16_t GTSC; /* GTSC */ - union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ -#define RSCAN0_GAFLCFG0_COUNT 2 - union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ - union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ - union iodefine_reg32_t RMNB; /* RMNB */ -#define RSCAN0_RMND0_COUNT 3 - union iodefine_reg32_t RMND0; /* RMND0 */ - union iodefine_reg32_t RMND1; /* RMND1 */ - union iodefine_reg32_t RMND2; /* RMND2 */ - - volatile uint8_t dummy160[4]; /* */ -#define RSCAN0_RFCC0_COUNT 8 - union iodefine_reg32_t RFCC0; /* RFCC0 */ - union iodefine_reg32_t RFCC1; /* RFCC1 */ - union iodefine_reg32_t RFCC2; /* RFCC2 */ - union iodefine_reg32_t RFCC3; /* RFCC3 */ - union iodefine_reg32_t RFCC4; /* RFCC4 */ - union iodefine_reg32_t RFCC5; /* RFCC5 */ - union iodefine_reg32_t RFCC6; /* RFCC6 */ - union iodefine_reg32_t RFCC7; /* RFCC7 */ -#define RSCAN0_RFSTS0_COUNT 8 - union iodefine_reg32_t RFSTS0; /* RFSTS0 */ - union iodefine_reg32_t RFSTS1; /* RFSTS1 */ - union iodefine_reg32_t RFSTS2; /* RFSTS2 */ - union iodefine_reg32_t RFSTS3; /* RFSTS3 */ - union iodefine_reg32_t RFSTS4; /* RFSTS4 */ - union iodefine_reg32_t RFSTS5; /* RFSTS5 */ - union iodefine_reg32_t RFSTS6; /* RFSTS6 */ - union iodefine_reg32_t RFSTS7; /* RFSTS7 */ -#define RSCAN0_RFPCTR0_COUNT 8 - union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ - union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ - union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ - union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ - union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ - union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ - union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ - union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ -#define RSCAN0_CFCC0_COUNT 15 - union iodefine_reg32_t CFCC0; /* CFCC0 */ - union iodefine_reg32_t CFCC1; /* CFCC1 */ - union iodefine_reg32_t CFCC2; /* CFCC2 */ - union iodefine_reg32_t CFCC3; /* CFCC3 */ - union iodefine_reg32_t CFCC4; /* CFCC4 */ - union iodefine_reg32_t CFCC5; /* CFCC5 */ - union iodefine_reg32_t CFCC6; /* CFCC6 */ - union iodefine_reg32_t CFCC7; /* CFCC7 */ - union iodefine_reg32_t CFCC8; /* CFCC8 */ - union iodefine_reg32_t CFCC9; /* CFCC9 */ - union iodefine_reg32_t CFCC10; /* CFCC10 */ - union iodefine_reg32_t CFCC11; /* CFCC11 */ - union iodefine_reg32_t CFCC12; /* CFCC12 */ - union iodefine_reg32_t CFCC13; /* CFCC13 */ - union iodefine_reg32_t CFCC14; /* CFCC14 */ - - volatile uint8_t dummy161[36]; /* */ -#define RSCAN0_CFSTS0_COUNT 15 - union iodefine_reg32_t CFSTS0; /* CFSTS0 */ - union iodefine_reg32_t CFSTS1; /* CFSTS1 */ - union iodefine_reg32_t CFSTS2; /* CFSTS2 */ - union iodefine_reg32_t CFSTS3; /* CFSTS3 */ - union iodefine_reg32_t CFSTS4; /* CFSTS4 */ - union iodefine_reg32_t CFSTS5; /* CFSTS5 */ - union iodefine_reg32_t CFSTS6; /* CFSTS6 */ - union iodefine_reg32_t CFSTS7; /* CFSTS7 */ - union iodefine_reg32_t CFSTS8; /* CFSTS8 */ - union iodefine_reg32_t CFSTS9; /* CFSTS9 */ - union iodefine_reg32_t CFSTS10; /* CFSTS10 */ - union iodefine_reg32_t CFSTS11; /* CFSTS11 */ - union iodefine_reg32_t CFSTS12; /* CFSTS12 */ - union iodefine_reg32_t CFSTS13; /* CFSTS13 */ - union iodefine_reg32_t CFSTS14; /* CFSTS14 */ - - volatile uint8_t dummy162[36]; /* */ -#define RSCAN0_CFPCTR0_COUNT 15 - union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ - union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ - union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ - union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ - union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ - union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ - union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ - union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ - union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ - union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ - union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ - union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ - union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ - union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ - union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ - - volatile uint8_t dummy163[36]; /* */ - union iodefine_reg32_t FESTS; /* FESTS */ - union iodefine_reg32_t FFSTS; /* FFSTS */ - union iodefine_reg32_t FMSTS; /* FMSTS */ - union iodefine_reg32_t RFISTS; /* RFISTS */ - union iodefine_reg32_t CFRISTS; /* CFRISTS */ - union iodefine_reg32_t CFTISTS; /* CFTISTS */ - -#define RSCAN0_TMC0_COUNT 80 - volatile uint8_t TMC0; /* TMC0 */ - volatile uint8_t TMC1; /* TMC1 */ - volatile uint8_t TMC2; /* TMC2 */ - volatile uint8_t TMC3; /* TMC3 */ - volatile uint8_t TMC4; /* TMC4 */ - volatile uint8_t TMC5; /* TMC5 */ - volatile uint8_t TMC6; /* TMC6 */ - volatile uint8_t TMC7; /* TMC7 */ - volatile uint8_t TMC8; /* TMC8 */ - volatile uint8_t TMC9; /* TMC9 */ - volatile uint8_t TMC10; /* TMC10 */ - volatile uint8_t TMC11; /* TMC11 */ - volatile uint8_t TMC12; /* TMC12 */ - volatile uint8_t TMC13; /* TMC13 */ - volatile uint8_t TMC14; /* TMC14 */ - volatile uint8_t TMC15; /* TMC15 */ - volatile uint8_t TMC16; /* TMC16 */ - volatile uint8_t TMC17; /* TMC17 */ - volatile uint8_t TMC18; /* TMC18 */ - volatile uint8_t TMC19; /* TMC19 */ - volatile uint8_t TMC20; /* TMC20 */ - volatile uint8_t TMC21; /* TMC21 */ - volatile uint8_t TMC22; /* TMC22 */ - volatile uint8_t TMC23; /* TMC23 */ - volatile uint8_t TMC24; /* TMC24 */ - volatile uint8_t TMC25; /* TMC25 */ - volatile uint8_t TMC26; /* TMC26 */ - volatile uint8_t TMC27; /* TMC27 */ - volatile uint8_t TMC28; /* TMC28 */ - volatile uint8_t TMC29; /* TMC29 */ - volatile uint8_t TMC30; /* TMC30 */ - volatile uint8_t TMC31; /* TMC31 */ - volatile uint8_t TMC32; /* TMC32 */ - volatile uint8_t TMC33; /* TMC33 */ - volatile uint8_t TMC34; /* TMC34 */ - volatile uint8_t TMC35; /* TMC35 */ - volatile uint8_t TMC36; /* TMC36 */ - volatile uint8_t TMC37; /* TMC37 */ - volatile uint8_t TMC38; /* TMC38 */ - volatile uint8_t TMC39; /* TMC39 */ - volatile uint8_t TMC40; /* TMC40 */ - volatile uint8_t TMC41; /* TMC41 */ - volatile uint8_t TMC42; /* TMC42 */ - volatile uint8_t TMC43; /* TMC43 */ - volatile uint8_t TMC44; /* TMC44 */ - volatile uint8_t TMC45; /* TMC45 */ - volatile uint8_t TMC46; /* TMC46 */ - volatile uint8_t TMC47; /* TMC47 */ - volatile uint8_t TMC48; /* TMC48 */ - volatile uint8_t TMC49; /* TMC49 */ - volatile uint8_t TMC50; /* TMC50 */ - volatile uint8_t TMC51; /* TMC51 */ - volatile uint8_t TMC52; /* TMC52 */ - volatile uint8_t TMC53; /* TMC53 */ - volatile uint8_t TMC54; /* TMC54 */ - volatile uint8_t TMC55; /* TMC55 */ - volatile uint8_t TMC56; /* TMC56 */ - volatile uint8_t TMC57; /* TMC57 */ - volatile uint8_t TMC58; /* TMC58 */ - volatile uint8_t TMC59; /* TMC59 */ - volatile uint8_t TMC60; /* TMC60 */ - volatile uint8_t TMC61; /* TMC61 */ - volatile uint8_t TMC62; /* TMC62 */ - volatile uint8_t TMC63; /* TMC63 */ - volatile uint8_t TMC64; /* TMC64 */ - volatile uint8_t TMC65; /* TMC65 */ - volatile uint8_t TMC66; /* TMC66 */ - volatile uint8_t TMC67; /* TMC67 */ - volatile uint8_t TMC68; /* TMC68 */ - volatile uint8_t TMC69; /* TMC69 */ - volatile uint8_t TMC70; /* TMC70 */ - volatile uint8_t TMC71; /* TMC71 */ - volatile uint8_t TMC72; /* TMC72 */ - volatile uint8_t TMC73; /* TMC73 */ - volatile uint8_t TMC74; /* TMC74 */ - volatile uint8_t TMC75; /* TMC75 */ - volatile uint8_t TMC76; /* TMC76 */ - volatile uint8_t TMC77; /* TMC77 */ - volatile uint8_t TMC78; /* TMC78 */ - volatile uint8_t TMC79; /* TMC79 */ - volatile uint8_t dummy164[48]; /* */ -#define RSCAN0_TMSTS0_COUNT 80 - volatile uint8_t TMSTS0; /* TMSTS0 */ - volatile uint8_t TMSTS1; /* TMSTS1 */ - volatile uint8_t TMSTS2; /* TMSTS2 */ - volatile uint8_t TMSTS3; /* TMSTS3 */ - volatile uint8_t TMSTS4; /* TMSTS4 */ - volatile uint8_t TMSTS5; /* TMSTS5 */ - volatile uint8_t TMSTS6; /* TMSTS6 */ - volatile uint8_t TMSTS7; /* TMSTS7 */ - volatile uint8_t TMSTS8; /* TMSTS8 */ - volatile uint8_t TMSTS9; /* TMSTS9 */ - volatile uint8_t TMSTS10; /* TMSTS10 */ - volatile uint8_t TMSTS11; /* TMSTS11 */ - volatile uint8_t TMSTS12; /* TMSTS12 */ - volatile uint8_t TMSTS13; /* TMSTS13 */ - volatile uint8_t TMSTS14; /* TMSTS14 */ - volatile uint8_t TMSTS15; /* TMSTS15 */ - volatile uint8_t TMSTS16; /* TMSTS16 */ - volatile uint8_t TMSTS17; /* TMSTS17 */ - volatile uint8_t TMSTS18; /* TMSTS18 */ - volatile uint8_t TMSTS19; /* TMSTS19 */ - volatile uint8_t TMSTS20; /* TMSTS20 */ - volatile uint8_t TMSTS21; /* TMSTS21 */ - volatile uint8_t TMSTS22; /* TMSTS22 */ - volatile uint8_t TMSTS23; /* TMSTS23 */ - volatile uint8_t TMSTS24; /* TMSTS24 */ - volatile uint8_t TMSTS25; /* TMSTS25 */ - volatile uint8_t TMSTS26; /* TMSTS26 */ - volatile uint8_t TMSTS27; /* TMSTS27 */ - volatile uint8_t TMSTS28; /* TMSTS28 */ - volatile uint8_t TMSTS29; /* TMSTS29 */ - volatile uint8_t TMSTS30; /* TMSTS30 */ - volatile uint8_t TMSTS31; /* TMSTS31 */ - volatile uint8_t TMSTS32; /* TMSTS32 */ - volatile uint8_t TMSTS33; /* TMSTS33 */ - volatile uint8_t TMSTS34; /* TMSTS34 */ - volatile uint8_t TMSTS35; /* TMSTS35 */ - volatile uint8_t TMSTS36; /* TMSTS36 */ - volatile uint8_t TMSTS37; /* TMSTS37 */ - volatile uint8_t TMSTS38; /* TMSTS38 */ - volatile uint8_t TMSTS39; /* TMSTS39 */ - volatile uint8_t TMSTS40; /* TMSTS40 */ - volatile uint8_t TMSTS41; /* TMSTS41 */ - volatile uint8_t TMSTS42; /* TMSTS42 */ - volatile uint8_t TMSTS43; /* TMSTS43 */ - volatile uint8_t TMSTS44; /* TMSTS44 */ - volatile uint8_t TMSTS45; /* TMSTS45 */ - volatile uint8_t TMSTS46; /* TMSTS46 */ - volatile uint8_t TMSTS47; /* TMSTS47 */ - volatile uint8_t TMSTS48; /* TMSTS48 */ - volatile uint8_t TMSTS49; /* TMSTS49 */ - volatile uint8_t TMSTS50; /* TMSTS50 */ - volatile uint8_t TMSTS51; /* TMSTS51 */ - volatile uint8_t TMSTS52; /* TMSTS52 */ - volatile uint8_t TMSTS53; /* TMSTS53 */ - volatile uint8_t TMSTS54; /* TMSTS54 */ - volatile uint8_t TMSTS55; /* TMSTS55 */ - volatile uint8_t TMSTS56; /* TMSTS56 */ - volatile uint8_t TMSTS57; /* TMSTS57 */ - volatile uint8_t TMSTS58; /* TMSTS58 */ - volatile uint8_t TMSTS59; /* TMSTS59 */ - volatile uint8_t TMSTS60; /* TMSTS60 */ - volatile uint8_t TMSTS61; /* TMSTS61 */ - volatile uint8_t TMSTS62; /* TMSTS62 */ - volatile uint8_t TMSTS63; /* TMSTS63 */ - volatile uint8_t TMSTS64; /* TMSTS64 */ - volatile uint8_t TMSTS65; /* TMSTS65 */ - volatile uint8_t TMSTS66; /* TMSTS66 */ - volatile uint8_t TMSTS67; /* TMSTS67 */ - volatile uint8_t TMSTS68; /* TMSTS68 */ - volatile uint8_t TMSTS69; /* TMSTS69 */ - volatile uint8_t TMSTS70; /* TMSTS70 */ - volatile uint8_t TMSTS71; /* TMSTS71 */ - volatile uint8_t TMSTS72; /* TMSTS72 */ - volatile uint8_t TMSTS73; /* TMSTS73 */ - volatile uint8_t TMSTS74; /* TMSTS74 */ - volatile uint8_t TMSTS75; /* TMSTS75 */ - volatile uint8_t TMSTS76; /* TMSTS76 */ - volatile uint8_t TMSTS77; /* TMSTS77 */ - volatile uint8_t TMSTS78; /* TMSTS78 */ - volatile uint8_t TMSTS79; /* TMSTS79 */ - volatile uint8_t dummy165[48]; /* */ -#define RSCAN0_TMTRSTS0_COUNT 3 - union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ - union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ - union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ - - volatile uint8_t dummy166[4]; /* */ -#define RSCAN0_TMTARSTS0_COUNT 3 - union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ - union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ - union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ - - volatile uint8_t dummy167[4]; /* */ -#define RSCAN0_TMTCSTS0_COUNT 3 - union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ - union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ - union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ - - volatile uint8_t dummy168[4]; /* */ -#define RSCAN0_TMTASTS0_COUNT 3 - union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ - union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ - union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ - - volatile uint8_t dummy169[4]; /* */ -#define RSCAN0_TMIEC0_COUNT 3 - union iodefine_reg32_t TMIEC0; /* TMIEC0 */ - union iodefine_reg32_t TMIEC1; /* TMIEC1 */ - union iodefine_reg32_t TMIEC2; /* TMIEC2 */ - - volatile uint8_t dummy170[4]; /* */ -#define RSCAN0_TXQCC0_COUNT 5 - union iodefine_reg32_t TXQCC0; /* TXQCC0 */ - union iodefine_reg32_t TXQCC1; /* TXQCC1 */ - union iodefine_reg32_t TXQCC2; /* TXQCC2 */ - union iodefine_reg32_t TXQCC3; /* TXQCC3 */ - union iodefine_reg32_t TXQCC4; /* TXQCC4 */ - - volatile uint8_t dummy171[12]; /* */ -#define RSCAN0_TXQSTS0_COUNT 5 - union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ - union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ - union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ - union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ - union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ - - volatile uint8_t dummy172[12]; /* */ -#define RSCAN0_TXQPCTR0_COUNT 5 - union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ - union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ - union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ - union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ - union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ - - volatile uint8_t dummy173[12]; /* */ -#define RSCAN0_THLCC0_COUNT 5 - union iodefine_reg32_t THLCC0; /* THLCC0 */ - union iodefine_reg32_t THLCC1; /* THLCC1 */ - union iodefine_reg32_t THLCC2; /* THLCC2 */ - union iodefine_reg32_t THLCC3; /* THLCC3 */ - union iodefine_reg32_t THLCC4; /* THLCC4 */ - - volatile uint8_t dummy174[12]; /* */ -#define RSCAN0_THLSTS0_COUNT 5 - union iodefine_reg32_t THLSTS0; /* THLSTS0 */ - union iodefine_reg32_t THLSTS1; /* THLSTS1 */ - union iodefine_reg32_t THLSTS2; /* THLSTS2 */ - union iodefine_reg32_t THLSTS3; /* THLSTS3 */ - union iodefine_reg32_t THLSTS4; /* THLSTS4 */ - - volatile uint8_t dummy175[12]; /* */ -#define RSCAN0_THLPCTR0_COUNT 5 - union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ - union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ - union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ - union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ - union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ - - volatile uint8_t dummy176[12]; /* */ -#define RSCAN0_GTINTSTS0_COUNT 2 - union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ - union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ - union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ - union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ - - volatile uint8_t dummy177[12]; /* */ - union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ - - volatile uint8_t dummy178[128]; /* */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID0; /* GAFLID0 */ - union iodefine_reg32_t GAFLM0; /* GAFLM0 */ - union iodefine_reg32_t GAFLP00; /* GAFLP00 */ - union iodefine_reg32_t GAFLP10; /* GAFLP10 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID1; /* GAFLID1 */ - union iodefine_reg32_t GAFLM1; /* GAFLM1 */ - union iodefine_reg32_t GAFLP01; /* GAFLP01 */ - union iodefine_reg32_t GAFLP11; /* GAFLP11 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID2; /* GAFLID2 */ - union iodefine_reg32_t GAFLM2; /* GAFLM2 */ - union iodefine_reg32_t GAFLP02; /* GAFLP02 */ - union iodefine_reg32_t GAFLP12; /* GAFLP12 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID3; /* GAFLID3 */ - union iodefine_reg32_t GAFLM3; /* GAFLM3 */ - union iodefine_reg32_t GAFLP03; /* GAFLP03 */ - union iodefine_reg32_t GAFLP13; /* GAFLP13 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID4; /* GAFLID4 */ - union iodefine_reg32_t GAFLM4; /* GAFLM4 */ - union iodefine_reg32_t GAFLP04; /* GAFLP04 */ - union iodefine_reg32_t GAFLP14; /* GAFLP14 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID5; /* GAFLID5 */ - union iodefine_reg32_t GAFLM5; /* GAFLM5 */ - union iodefine_reg32_t GAFLP05; /* GAFLP05 */ - union iodefine_reg32_t GAFLP15; /* GAFLP15 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID6; /* GAFLID6 */ - union iodefine_reg32_t GAFLM6; /* GAFLM6 */ - union iodefine_reg32_t GAFLP06; /* GAFLP06 */ - union iodefine_reg32_t GAFLP16; /* GAFLP16 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID7; /* GAFLID7 */ - union iodefine_reg32_t GAFLM7; /* GAFLM7 */ - union iodefine_reg32_t GAFLP07; /* GAFLP07 */ - union iodefine_reg32_t GAFLP17; /* GAFLP17 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID8; /* GAFLID8 */ - union iodefine_reg32_t GAFLM8; /* GAFLM8 */ - union iodefine_reg32_t GAFLP08; /* GAFLP08 */ - union iodefine_reg32_t GAFLP18; /* GAFLP18 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID9; /* GAFLID9 */ - union iodefine_reg32_t GAFLM9; /* GAFLM9 */ - union iodefine_reg32_t GAFLP09; /* GAFLP09 */ - union iodefine_reg32_t GAFLP19; /* GAFLP19 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID10; /* GAFLID10 */ - union iodefine_reg32_t GAFLM10; /* GAFLM10 */ - union iodefine_reg32_t GAFLP010; /* GAFLP010 */ - union iodefine_reg32_t GAFLP110; /* GAFLP110 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID11; /* GAFLID11 */ - union iodefine_reg32_t GAFLM11; /* GAFLM11 */ - union iodefine_reg32_t GAFLP011; /* GAFLP011 */ - union iodefine_reg32_t GAFLP111; /* GAFLP111 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID12; /* GAFLID12 */ - union iodefine_reg32_t GAFLM12; /* GAFLM12 */ - union iodefine_reg32_t GAFLP012; /* GAFLP012 */ - union iodefine_reg32_t GAFLP112; /* GAFLP112 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID13; /* GAFLID13 */ - union iodefine_reg32_t GAFLM13; /* GAFLM13 */ - union iodefine_reg32_t GAFLP013; /* GAFLP013 */ - union iodefine_reg32_t GAFLP113; /* GAFLP113 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID14; /* GAFLID14 */ - union iodefine_reg32_t GAFLM14; /* GAFLM14 */ - union iodefine_reg32_t GAFLP014; /* GAFLP014 */ - union iodefine_reg32_t GAFLP114; /* GAFLP114 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID15; /* GAFLID15 */ - union iodefine_reg32_t GAFLM15; /* GAFLM15 */ - union iodefine_reg32_t GAFLP015; /* GAFLP015 */ - union iodefine_reg32_t GAFLP115; /* GAFLP115 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID0; /* RMID0 */ - union iodefine_reg32_t RMPTR0; /* RMPTR0 */ - union iodefine_reg32_t RMDF00; /* RMDF00 */ - union iodefine_reg32_t RMDF10; /* RMDF10 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID1; /* RMID1 */ - union iodefine_reg32_t RMPTR1; /* RMPTR1 */ - union iodefine_reg32_t RMDF01; /* RMDF01 */ - union iodefine_reg32_t RMDF11; /* RMDF11 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID2; /* RMID2 */ - union iodefine_reg32_t RMPTR2; /* RMPTR2 */ - union iodefine_reg32_t RMDF02; /* RMDF02 */ - union iodefine_reg32_t RMDF12; /* RMDF12 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID3; /* RMID3 */ - union iodefine_reg32_t RMPTR3; /* RMPTR3 */ - union iodefine_reg32_t RMDF03; /* RMDF03 */ - union iodefine_reg32_t RMDF13; /* RMDF13 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID4; /* RMID4 */ - union iodefine_reg32_t RMPTR4; /* RMPTR4 */ - union iodefine_reg32_t RMDF04; /* RMDF04 */ - union iodefine_reg32_t RMDF14; /* RMDF14 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID5; /* RMID5 */ - union iodefine_reg32_t RMPTR5; /* RMPTR5 */ - union iodefine_reg32_t RMDF05; /* RMDF05 */ - union iodefine_reg32_t RMDF15; /* RMDF15 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID6; /* RMID6 */ - union iodefine_reg32_t RMPTR6; /* RMPTR6 */ - union iodefine_reg32_t RMDF06; /* RMDF06 */ - union iodefine_reg32_t RMDF16; /* RMDF16 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID7; /* RMID7 */ - union iodefine_reg32_t RMPTR7; /* RMPTR7 */ - union iodefine_reg32_t RMDF07; /* RMDF07 */ - union iodefine_reg32_t RMDF17; /* RMDF17 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID8; /* RMID8 */ - union iodefine_reg32_t RMPTR8; /* RMPTR8 */ - union iodefine_reg32_t RMDF08; /* RMDF08 */ - union iodefine_reg32_t RMDF18; /* RMDF18 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID9; /* RMID9 */ - union iodefine_reg32_t RMPTR9; /* RMPTR9 */ - union iodefine_reg32_t RMDF09; /* RMDF09 */ - union iodefine_reg32_t RMDF19; /* RMDF19 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID10; /* RMID10 */ - union iodefine_reg32_t RMPTR10; /* RMPTR10 */ - union iodefine_reg32_t RMDF010; /* RMDF010 */ - union iodefine_reg32_t RMDF110; /* RMDF110 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID11; /* RMID11 */ - union iodefine_reg32_t RMPTR11; /* RMPTR11 */ - union iodefine_reg32_t RMDF011; /* RMDF011 */ - union iodefine_reg32_t RMDF111; /* RMDF111 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID12; /* RMID12 */ - union iodefine_reg32_t RMPTR12; /* RMPTR12 */ - union iodefine_reg32_t RMDF012; /* RMDF012 */ - union iodefine_reg32_t RMDF112; /* RMDF112 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID13; /* RMID13 */ - union iodefine_reg32_t RMPTR13; /* RMPTR13 */ - union iodefine_reg32_t RMDF013; /* RMDF013 */ - union iodefine_reg32_t RMDF113; /* RMDF113 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID14; /* RMID14 */ - union iodefine_reg32_t RMPTR14; /* RMPTR14 */ - union iodefine_reg32_t RMDF014; /* RMDF014 */ - union iodefine_reg32_t RMDF114; /* RMDF114 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID15; /* RMID15 */ - union iodefine_reg32_t RMPTR15; /* RMPTR15 */ - union iodefine_reg32_t RMDF015; /* RMDF015 */ - union iodefine_reg32_t RMDF115; /* RMDF115 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID16; /* RMID16 */ - union iodefine_reg32_t RMPTR16; /* RMPTR16 */ - union iodefine_reg32_t RMDF016; /* RMDF016 */ - union iodefine_reg32_t RMDF116; /* RMDF116 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID17; /* RMID17 */ - union iodefine_reg32_t RMPTR17; /* RMPTR17 */ - union iodefine_reg32_t RMDF017; /* RMDF017 */ - union iodefine_reg32_t RMDF117; /* RMDF117 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID18; /* RMID18 */ - union iodefine_reg32_t RMPTR18; /* RMPTR18 */ - union iodefine_reg32_t RMDF018; /* RMDF018 */ - union iodefine_reg32_t RMDF118; /* RMDF118 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID19; /* RMID19 */ - union iodefine_reg32_t RMPTR19; /* RMPTR19 */ - union iodefine_reg32_t RMDF019; /* RMDF019 */ - union iodefine_reg32_t RMDF119; /* RMDF119 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID20; /* RMID20 */ - union iodefine_reg32_t RMPTR20; /* RMPTR20 */ - union iodefine_reg32_t RMDF020; /* RMDF020 */ - union iodefine_reg32_t RMDF120; /* RMDF120 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID21; /* RMID21 */ - union iodefine_reg32_t RMPTR21; /* RMPTR21 */ - union iodefine_reg32_t RMDF021; /* RMDF021 */ - union iodefine_reg32_t RMDF121; /* RMDF121 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID22; /* RMID22 */ - union iodefine_reg32_t RMPTR22; /* RMPTR22 */ - union iodefine_reg32_t RMDF022; /* RMDF022 */ - union iodefine_reg32_t RMDF122; /* RMDF122 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID23; /* RMID23 */ - union iodefine_reg32_t RMPTR23; /* RMPTR23 */ - union iodefine_reg32_t RMDF023; /* RMDF023 */ - union iodefine_reg32_t RMDF123; /* RMDF123 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID24; /* RMID24 */ - union iodefine_reg32_t RMPTR24; /* RMPTR24 */ - union iodefine_reg32_t RMDF024; /* RMDF024 */ - union iodefine_reg32_t RMDF124; /* RMDF124 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID25; /* RMID25 */ - union iodefine_reg32_t RMPTR25; /* RMPTR25 */ - union iodefine_reg32_t RMDF025; /* RMDF025 */ - union iodefine_reg32_t RMDF125; /* RMDF125 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID26; /* RMID26 */ - union iodefine_reg32_t RMPTR26; /* RMPTR26 */ - union iodefine_reg32_t RMDF026; /* RMDF026 */ - union iodefine_reg32_t RMDF126; /* RMDF126 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID27; /* RMID27 */ - union iodefine_reg32_t RMPTR27; /* RMPTR27 */ - union iodefine_reg32_t RMDF027; /* RMDF027 */ - union iodefine_reg32_t RMDF127; /* RMDF127 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID28; /* RMID28 */ - union iodefine_reg32_t RMPTR28; /* RMPTR28 */ - union iodefine_reg32_t RMDF028; /* RMDF028 */ - union iodefine_reg32_t RMDF128; /* RMDF128 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID29; /* RMID29 */ - union iodefine_reg32_t RMPTR29; /* RMPTR29 */ - union iodefine_reg32_t RMDF029; /* RMDF029 */ - union iodefine_reg32_t RMDF129; /* RMDF129 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID30; /* RMID30 */ - union iodefine_reg32_t RMPTR30; /* RMPTR30 */ - union iodefine_reg32_t RMDF030; /* RMDF030 */ - union iodefine_reg32_t RMDF130; /* RMDF130 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID31; /* RMID31 */ - union iodefine_reg32_t RMPTR31; /* RMPTR31 */ - union iodefine_reg32_t RMDF031; /* RMDF031 */ - union iodefine_reg32_t RMDF131; /* RMDF131 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID32; /* RMID32 */ - union iodefine_reg32_t RMPTR32; /* RMPTR32 */ - union iodefine_reg32_t RMDF032; /* RMDF032 */ - union iodefine_reg32_t RMDF132; /* RMDF132 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID33; /* RMID33 */ - union iodefine_reg32_t RMPTR33; /* RMPTR33 */ - union iodefine_reg32_t RMDF033; /* RMDF033 */ - union iodefine_reg32_t RMDF133; /* RMDF133 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID34; /* RMID34 */ - union iodefine_reg32_t RMPTR34; /* RMPTR34 */ - union iodefine_reg32_t RMDF034; /* RMDF034 */ - union iodefine_reg32_t RMDF134; /* RMDF134 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID35; /* RMID35 */ - union iodefine_reg32_t RMPTR35; /* RMPTR35 */ - union iodefine_reg32_t RMDF035; /* RMDF035 */ - union iodefine_reg32_t RMDF135; /* RMDF135 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID36; /* RMID36 */ - union iodefine_reg32_t RMPTR36; /* RMPTR36 */ - union iodefine_reg32_t RMDF036; /* RMDF036 */ - union iodefine_reg32_t RMDF136; /* RMDF136 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID37; /* RMID37 */ - union iodefine_reg32_t RMPTR37; /* RMPTR37 */ - union iodefine_reg32_t RMDF037; /* RMDF037 */ - union iodefine_reg32_t RMDF137; /* RMDF137 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID38; /* RMID38 */ - union iodefine_reg32_t RMPTR38; /* RMPTR38 */ - union iodefine_reg32_t RMDF038; /* RMDF038 */ - union iodefine_reg32_t RMDF138; /* RMDF138 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID39; /* RMID39 */ - union iodefine_reg32_t RMPTR39; /* RMPTR39 */ - union iodefine_reg32_t RMDF039; /* RMDF039 */ - union iodefine_reg32_t RMDF139; /* RMDF139 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID40; /* RMID40 */ - union iodefine_reg32_t RMPTR40; /* RMPTR40 */ - union iodefine_reg32_t RMDF040; /* RMDF040 */ - union iodefine_reg32_t RMDF140; /* RMDF140 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID41; /* RMID41 */ - union iodefine_reg32_t RMPTR41; /* RMPTR41 */ - union iodefine_reg32_t RMDF041; /* RMDF041 */ - union iodefine_reg32_t RMDF141; /* RMDF141 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID42; /* RMID42 */ - union iodefine_reg32_t RMPTR42; /* RMPTR42 */ - union iodefine_reg32_t RMDF042; /* RMDF042 */ - union iodefine_reg32_t RMDF142; /* RMDF142 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID43; /* RMID43 */ - union iodefine_reg32_t RMPTR43; /* RMPTR43 */ - union iodefine_reg32_t RMDF043; /* RMDF043 */ - union iodefine_reg32_t RMDF143; /* RMDF143 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID44; /* RMID44 */ - union iodefine_reg32_t RMPTR44; /* RMPTR44 */ - union iodefine_reg32_t RMDF044; /* RMDF044 */ - union iodefine_reg32_t RMDF144; /* RMDF144 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID45; /* RMID45 */ - union iodefine_reg32_t RMPTR45; /* RMPTR45 */ - union iodefine_reg32_t RMDF045; /* RMDF045 */ - union iodefine_reg32_t RMDF145; /* RMDF145 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID46; /* RMID46 */ - union iodefine_reg32_t RMPTR46; /* RMPTR46 */ - union iodefine_reg32_t RMDF046; /* RMDF046 */ - union iodefine_reg32_t RMDF146; /* RMDF146 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID47; /* RMID47 */ - union iodefine_reg32_t RMPTR47; /* RMPTR47 */ - union iodefine_reg32_t RMDF047; /* RMDF047 */ - union iodefine_reg32_t RMDF147; /* RMDF147 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID48; /* RMID48 */ - union iodefine_reg32_t RMPTR48; /* RMPTR48 */ - union iodefine_reg32_t RMDF048; /* RMDF048 */ - union iodefine_reg32_t RMDF148; /* RMDF148 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID49; /* RMID49 */ - union iodefine_reg32_t RMPTR49; /* RMPTR49 */ - union iodefine_reg32_t RMDF049; /* RMDF049 */ - union iodefine_reg32_t RMDF149; /* RMDF149 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID50; /* RMID50 */ - union iodefine_reg32_t RMPTR50; /* RMPTR50 */ - union iodefine_reg32_t RMDF050; /* RMDF050 */ - union iodefine_reg32_t RMDF150; /* RMDF150 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID51; /* RMID51 */ - union iodefine_reg32_t RMPTR51; /* RMPTR51 */ - union iodefine_reg32_t RMDF051; /* RMDF051 */ - union iodefine_reg32_t RMDF151; /* RMDF151 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID52; /* RMID52 */ - union iodefine_reg32_t RMPTR52; /* RMPTR52 */ - union iodefine_reg32_t RMDF052; /* RMDF052 */ - union iodefine_reg32_t RMDF152; /* RMDF152 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID53; /* RMID53 */ - union iodefine_reg32_t RMPTR53; /* RMPTR53 */ - union iodefine_reg32_t RMDF053; /* RMDF053 */ - union iodefine_reg32_t RMDF153; /* RMDF153 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID54; /* RMID54 */ - union iodefine_reg32_t RMPTR54; /* RMPTR54 */ - union iodefine_reg32_t RMDF054; /* RMDF054 */ - union iodefine_reg32_t RMDF154; /* RMDF154 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID55; /* RMID55 */ - union iodefine_reg32_t RMPTR55; /* RMPTR55 */ - union iodefine_reg32_t RMDF055; /* RMDF055 */ - union iodefine_reg32_t RMDF155; /* RMDF155 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID56; /* RMID56 */ - union iodefine_reg32_t RMPTR56; /* RMPTR56 */ - union iodefine_reg32_t RMDF056; /* RMDF056 */ - union iodefine_reg32_t RMDF156; /* RMDF156 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID57; /* RMID57 */ - union iodefine_reg32_t RMPTR57; /* RMPTR57 */ - union iodefine_reg32_t RMDF057; /* RMDF057 */ - union iodefine_reg32_t RMDF157; /* RMDF157 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID58; /* RMID58 */ - union iodefine_reg32_t RMPTR58; /* RMPTR58 */ - union iodefine_reg32_t RMDF058; /* RMDF058 */ - union iodefine_reg32_t RMDF158; /* RMDF158 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID59; /* RMID59 */ - union iodefine_reg32_t RMPTR59; /* RMPTR59 */ - union iodefine_reg32_t RMDF059; /* RMDF059 */ - union iodefine_reg32_t RMDF159; /* RMDF159 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID60; /* RMID60 */ - union iodefine_reg32_t RMPTR60; /* RMPTR60 */ - union iodefine_reg32_t RMDF060; /* RMDF060 */ - union iodefine_reg32_t RMDF160; /* RMDF160 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID61; /* RMID61 */ - union iodefine_reg32_t RMPTR61; /* RMPTR61 */ - union iodefine_reg32_t RMDF061; /* RMDF061 */ - union iodefine_reg32_t RMDF161; /* RMDF161 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID62; /* RMID62 */ - union iodefine_reg32_t RMPTR62; /* RMPTR62 */ - union iodefine_reg32_t RMDF062; /* RMDF062 */ - union iodefine_reg32_t RMDF162; /* RMDF162 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID63; /* RMID63 */ - union iodefine_reg32_t RMPTR63; /* RMPTR63 */ - union iodefine_reg32_t RMDF063; /* RMDF063 */ - union iodefine_reg32_t RMDF163; /* RMDF163 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID64; /* RMID64 */ - union iodefine_reg32_t RMPTR64; /* RMPTR64 */ - union iodefine_reg32_t RMDF064; /* RMDF064 */ - union iodefine_reg32_t RMDF164; /* RMDF164 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID65; /* RMID65 */ - union iodefine_reg32_t RMPTR65; /* RMPTR65 */ - union iodefine_reg32_t RMDF065; /* RMDF065 */ - union iodefine_reg32_t RMDF165; /* RMDF165 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID66; /* RMID66 */ - union iodefine_reg32_t RMPTR66; /* RMPTR66 */ - union iodefine_reg32_t RMDF066; /* RMDF066 */ - union iodefine_reg32_t RMDF166; /* RMDF166 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID67; /* RMID67 */ - union iodefine_reg32_t RMPTR67; /* RMPTR67 */ - union iodefine_reg32_t RMDF067; /* RMDF067 */ - union iodefine_reg32_t RMDF167; /* RMDF167 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID68; /* RMID68 */ - union iodefine_reg32_t RMPTR68; /* RMPTR68 */ - union iodefine_reg32_t RMDF068; /* RMDF068 */ - union iodefine_reg32_t RMDF168; /* RMDF168 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID69; /* RMID69 */ - union iodefine_reg32_t RMPTR69; /* RMPTR69 */ - union iodefine_reg32_t RMDF069; /* RMDF069 */ - union iodefine_reg32_t RMDF169; /* RMDF169 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID70; /* RMID70 */ - union iodefine_reg32_t RMPTR70; /* RMPTR70 */ - union iodefine_reg32_t RMDF070; /* RMDF070 */ - union iodefine_reg32_t RMDF170; /* RMDF170 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID71; /* RMID71 */ - union iodefine_reg32_t RMPTR71; /* RMPTR71 */ - union iodefine_reg32_t RMDF071; /* RMDF071 */ - union iodefine_reg32_t RMDF171; /* RMDF171 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID72; /* RMID72 */ - union iodefine_reg32_t RMPTR72; /* RMPTR72 */ - union iodefine_reg32_t RMDF072; /* RMDF072 */ - union iodefine_reg32_t RMDF172; /* RMDF172 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID73; /* RMID73 */ - union iodefine_reg32_t RMPTR73; /* RMPTR73 */ - union iodefine_reg32_t RMDF073; /* RMDF073 */ - union iodefine_reg32_t RMDF173; /* RMDF173 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID74; /* RMID74 */ - union iodefine_reg32_t RMPTR74; /* RMPTR74 */ - union iodefine_reg32_t RMDF074; /* RMDF074 */ - union iodefine_reg32_t RMDF174; /* RMDF174 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID75; /* RMID75 */ - union iodefine_reg32_t RMPTR75; /* RMPTR75 */ - union iodefine_reg32_t RMDF075; /* RMDF075 */ - union iodefine_reg32_t RMDF175; /* RMDF175 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID76; /* RMID76 */ - union iodefine_reg32_t RMPTR76; /* RMPTR76 */ - union iodefine_reg32_t RMDF076; /* RMDF076 */ - union iodefine_reg32_t RMDF176; /* RMDF176 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID77; /* RMID77 */ - union iodefine_reg32_t RMPTR77; /* RMPTR77 */ - union iodefine_reg32_t RMDF077; /* RMDF077 */ - union iodefine_reg32_t RMDF177; /* RMDF177 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID78; /* RMID78 */ - union iodefine_reg32_t RMPTR78; /* RMPTR78 */ - union iodefine_reg32_t RMDF078; /* RMDF078 */ - union iodefine_reg32_t RMDF178; /* RMDF178 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID79; /* RMID79 */ - union iodefine_reg32_t RMPTR79; /* RMPTR79 */ - union iodefine_reg32_t RMDF079; /* RMDF079 */ - union iodefine_reg32_t RMDF179; /* RMDF179 */ -/* end of struct st_rscan_from_rscan0rmidp */ - - volatile uint8_t dummy179[768]; /* */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID0; /* RFID0 */ - union iodefine_reg32_t RFPTR0; /* RFPTR0 */ - union iodefine_reg32_t RFDF00; /* RFDF00 */ - union iodefine_reg32_t RFDF10; /* RFDF10 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID1; /* RFID1 */ - union iodefine_reg32_t RFPTR1; /* RFPTR1 */ - union iodefine_reg32_t RFDF01; /* RFDF01 */ - union iodefine_reg32_t RFDF11; /* RFDF11 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID2; /* RFID2 */ - union iodefine_reg32_t RFPTR2; /* RFPTR2 */ - union iodefine_reg32_t RFDF02; /* RFDF02 */ - union iodefine_reg32_t RFDF12; /* RFDF12 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID3; /* RFID3 */ - union iodefine_reg32_t RFPTR3; /* RFPTR3 */ - union iodefine_reg32_t RFDF03; /* RFDF03 */ - union iodefine_reg32_t RFDF13; /* RFDF13 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID4; /* RFID4 */ - union iodefine_reg32_t RFPTR4; /* RFPTR4 */ - union iodefine_reg32_t RFDF04; /* RFDF04 */ - union iodefine_reg32_t RFDF14; /* RFDF14 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID5; /* RFID5 */ - union iodefine_reg32_t RFPTR5; /* RFPTR5 */ - union iodefine_reg32_t RFDF05; /* RFDF05 */ - union iodefine_reg32_t RFDF15; /* RFDF15 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID6; /* RFID6 */ - union iodefine_reg32_t RFPTR6; /* RFPTR6 */ - union iodefine_reg32_t RFDF06; /* RFDF06 */ - union iodefine_reg32_t RFDF16; /* RFDF16 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID7; /* RFID7 */ - union iodefine_reg32_t RFPTR7; /* RFPTR7 */ - union iodefine_reg32_t RFDF07; /* RFDF07 */ - union iodefine_reg32_t RFDF17; /* RFDF17 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID0; /* CFID0 */ - union iodefine_reg32_t CFPTR0; /* CFPTR0 */ - union iodefine_reg32_t CFDF00; /* CFDF00 */ - union iodefine_reg32_t CFDF10; /* CFDF10 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID1; /* CFID1 */ - union iodefine_reg32_t CFPTR1; /* CFPTR1 */ - union iodefine_reg32_t CFDF01; /* CFDF01 */ - union iodefine_reg32_t CFDF11; /* CFDF11 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID2; /* CFID2 */ - union iodefine_reg32_t CFPTR2; /* CFPTR2 */ - union iodefine_reg32_t CFDF02; /* CFDF02 */ - union iodefine_reg32_t CFDF12; /* CFDF12 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID3; /* CFID3 */ - union iodefine_reg32_t CFPTR3; /* CFPTR3 */ - union iodefine_reg32_t CFDF03; /* CFDF03 */ - union iodefine_reg32_t CFDF13; /* CFDF13 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID4; /* CFID4 */ - union iodefine_reg32_t CFPTR4; /* CFPTR4 */ - union iodefine_reg32_t CFDF04; /* CFDF04 */ - union iodefine_reg32_t CFDF14; /* CFDF14 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID5; /* CFID5 */ - union iodefine_reg32_t CFPTR5; /* CFPTR5 */ - union iodefine_reg32_t CFDF05; /* CFDF05 */ - union iodefine_reg32_t CFDF15; /* CFDF15 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID6; /* CFID6 */ - union iodefine_reg32_t CFPTR6; /* CFPTR6 */ - union iodefine_reg32_t CFDF06; /* CFDF06 */ - union iodefine_reg32_t CFDF16; /* CFDF16 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID7; /* CFID7 */ - union iodefine_reg32_t CFPTR7; /* CFPTR7 */ - union iodefine_reg32_t CFDF07; /* CFDF07 */ - union iodefine_reg32_t CFDF17; /* CFDF17 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID8; /* CFID8 */ - union iodefine_reg32_t CFPTR8; /* CFPTR8 */ - union iodefine_reg32_t CFDF08; /* CFDF08 */ - union iodefine_reg32_t CFDF18; /* CFDF18 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID9; /* CFID9 */ - union iodefine_reg32_t CFPTR9; /* CFPTR9 */ - union iodefine_reg32_t CFDF09; /* CFDF09 */ - union iodefine_reg32_t CFDF19; /* CFDF19 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID10; /* CFID10 */ - union iodefine_reg32_t CFPTR10; /* CFPTR10 */ - union iodefine_reg32_t CFDF010; /* CFDF010 */ - union iodefine_reg32_t CFDF110; /* CFDF110 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID11; /* CFID11 */ - union iodefine_reg32_t CFPTR11; /* CFPTR11 */ - union iodefine_reg32_t CFDF011; /* CFDF011 */ - union iodefine_reg32_t CFDF111; /* CFDF111 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID12; /* CFID12 */ - union iodefine_reg32_t CFPTR12; /* CFPTR12 */ - union iodefine_reg32_t CFDF012; /* CFDF012 */ - union iodefine_reg32_t CFDF112; /* CFDF112 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID13; /* CFID13 */ - union iodefine_reg32_t CFPTR13; /* CFPTR13 */ - union iodefine_reg32_t CFDF013; /* CFDF013 */ - union iodefine_reg32_t CFDF113; /* CFDF113 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID14; /* CFID14 */ - union iodefine_reg32_t CFPTR14; /* CFPTR14 */ - union iodefine_reg32_t CFDF014; /* CFDF014 */ - union iodefine_reg32_t CFDF114; /* CFDF114 */ -/* end of struct st_rscan_from_rscan0cfidm */ - - volatile uint8_t dummy180[144]; /* */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID0; /* TMID0 */ - union iodefine_reg32_t TMPTR0; /* TMPTR0 */ - union iodefine_reg32_t TMDF00; /* TMDF00 */ - union iodefine_reg32_t TMDF10; /* TMDF10 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID1; /* TMID1 */ - union iodefine_reg32_t TMPTR1; /* TMPTR1 */ - union iodefine_reg32_t TMDF01; /* TMDF01 */ - union iodefine_reg32_t TMDF11; /* TMDF11 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID2; /* TMID2 */ - union iodefine_reg32_t TMPTR2; /* TMPTR2 */ - union iodefine_reg32_t TMDF02; /* TMDF02 */ - union iodefine_reg32_t TMDF12; /* TMDF12 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID3; /* TMID3 */ - union iodefine_reg32_t TMPTR3; /* TMPTR3 */ - union iodefine_reg32_t TMDF03; /* TMDF03 */ - union iodefine_reg32_t TMDF13; /* TMDF13 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID4; /* TMID4 */ - union iodefine_reg32_t TMPTR4; /* TMPTR4 */ - union iodefine_reg32_t TMDF04; /* TMDF04 */ - union iodefine_reg32_t TMDF14; /* TMDF14 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID5; /* TMID5 */ - union iodefine_reg32_t TMPTR5; /* TMPTR5 */ - union iodefine_reg32_t TMDF05; /* TMDF05 */ - union iodefine_reg32_t TMDF15; /* TMDF15 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID6; /* TMID6 */ - union iodefine_reg32_t TMPTR6; /* TMPTR6 */ - union iodefine_reg32_t TMDF06; /* TMDF06 */ - union iodefine_reg32_t TMDF16; /* TMDF16 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID7; /* TMID7 */ - union iodefine_reg32_t TMPTR7; /* TMPTR7 */ - union iodefine_reg32_t TMDF07; /* TMDF07 */ - union iodefine_reg32_t TMDF17; /* TMDF17 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID8; /* TMID8 */ - union iodefine_reg32_t TMPTR8; /* TMPTR8 */ - union iodefine_reg32_t TMDF08; /* TMDF08 */ - union iodefine_reg32_t TMDF18; /* TMDF18 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID9; /* TMID9 */ - union iodefine_reg32_t TMPTR9; /* TMPTR9 */ - union iodefine_reg32_t TMDF09; /* TMDF09 */ - union iodefine_reg32_t TMDF19; /* TMDF19 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID10; /* TMID10 */ - union iodefine_reg32_t TMPTR10; /* TMPTR10 */ - union iodefine_reg32_t TMDF010; /* TMDF010 */ - union iodefine_reg32_t TMDF110; /* TMDF110 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID11; /* TMID11 */ - union iodefine_reg32_t TMPTR11; /* TMPTR11 */ - union iodefine_reg32_t TMDF011; /* TMDF011 */ - union iodefine_reg32_t TMDF111; /* TMDF111 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID12; /* TMID12 */ - union iodefine_reg32_t TMPTR12; /* TMPTR12 */ - union iodefine_reg32_t TMDF012; /* TMDF012 */ - union iodefine_reg32_t TMDF112; /* TMDF112 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID13; /* TMID13 */ - union iodefine_reg32_t TMPTR13; /* TMPTR13 */ - union iodefine_reg32_t TMDF013; /* TMDF013 */ - union iodefine_reg32_t TMDF113; /* TMDF113 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID14; /* TMID14 */ - union iodefine_reg32_t TMPTR14; /* TMPTR14 */ - union iodefine_reg32_t TMDF014; /* TMDF014 */ - union iodefine_reg32_t TMDF114; /* TMDF114 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID15; /* TMID15 */ - union iodefine_reg32_t TMPTR15; /* TMPTR15 */ - union iodefine_reg32_t TMDF015; /* TMDF015 */ - union iodefine_reg32_t TMDF115; /* TMDF115 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID16; /* TMID16 */ - union iodefine_reg32_t TMPTR16; /* TMPTR16 */ - union iodefine_reg32_t TMDF016; /* TMDF016 */ - union iodefine_reg32_t TMDF116; /* TMDF116 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID17; /* TMID17 */ - union iodefine_reg32_t TMPTR17; /* TMPTR17 */ - union iodefine_reg32_t TMDF017; /* TMDF017 */ - union iodefine_reg32_t TMDF117; /* TMDF117 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID18; /* TMID18 */ - union iodefine_reg32_t TMPTR18; /* TMPTR18 */ - union iodefine_reg32_t TMDF018; /* TMDF018 */ - union iodefine_reg32_t TMDF118; /* TMDF118 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID19; /* TMID19 */ - union iodefine_reg32_t TMPTR19; /* TMPTR19 */ - union iodefine_reg32_t TMDF019; /* TMDF019 */ - union iodefine_reg32_t TMDF119; /* TMDF119 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID20; /* TMID20 */ - union iodefine_reg32_t TMPTR20; /* TMPTR20 */ - union iodefine_reg32_t TMDF020; /* TMDF020 */ - union iodefine_reg32_t TMDF120; /* TMDF120 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID21; /* TMID21 */ - union iodefine_reg32_t TMPTR21; /* TMPTR21 */ - union iodefine_reg32_t TMDF021; /* TMDF021 */ - union iodefine_reg32_t TMDF121; /* TMDF121 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID22; /* TMID22 */ - union iodefine_reg32_t TMPTR22; /* TMPTR22 */ - union iodefine_reg32_t TMDF022; /* TMDF022 */ - union iodefine_reg32_t TMDF122; /* TMDF122 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID23; /* TMID23 */ - union iodefine_reg32_t TMPTR23; /* TMPTR23 */ - union iodefine_reg32_t TMDF023; /* TMDF023 */ - union iodefine_reg32_t TMDF123; /* TMDF123 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID24; /* TMID24 */ - union iodefine_reg32_t TMPTR24; /* TMPTR24 */ - union iodefine_reg32_t TMDF024; /* TMDF024 */ - union iodefine_reg32_t TMDF124; /* TMDF124 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID25; /* TMID25 */ - union iodefine_reg32_t TMPTR25; /* TMPTR25 */ - union iodefine_reg32_t TMDF025; /* TMDF025 */ - union iodefine_reg32_t TMDF125; /* TMDF125 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID26; /* TMID26 */ - union iodefine_reg32_t TMPTR26; /* TMPTR26 */ - union iodefine_reg32_t TMDF026; /* TMDF026 */ - union iodefine_reg32_t TMDF126; /* TMDF126 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID27; /* TMID27 */ - union iodefine_reg32_t TMPTR27; /* TMPTR27 */ - union iodefine_reg32_t TMDF027; /* TMDF027 */ - union iodefine_reg32_t TMDF127; /* TMDF127 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID28; /* TMID28 */ - union iodefine_reg32_t TMPTR28; /* TMPTR28 */ - union iodefine_reg32_t TMDF028; /* TMDF028 */ - union iodefine_reg32_t TMDF128; /* TMDF128 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID29; /* TMID29 */ - union iodefine_reg32_t TMPTR29; /* TMPTR29 */ - union iodefine_reg32_t TMDF029; /* TMDF029 */ - union iodefine_reg32_t TMDF129; /* TMDF129 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID30; /* TMID30 */ - union iodefine_reg32_t TMPTR30; /* TMPTR30 */ - union iodefine_reg32_t TMDF030; /* TMDF030 */ - union iodefine_reg32_t TMDF130; /* TMDF130 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID31; /* TMID31 */ - union iodefine_reg32_t TMPTR31; /* TMPTR31 */ - union iodefine_reg32_t TMDF031; /* TMDF031 */ - union iodefine_reg32_t TMDF131; /* TMDF131 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID32; /* TMID32 */ - union iodefine_reg32_t TMPTR32; /* TMPTR32 */ - union iodefine_reg32_t TMDF032; /* TMDF032 */ - union iodefine_reg32_t TMDF132; /* TMDF132 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID33; /* TMID33 */ - union iodefine_reg32_t TMPTR33; /* TMPTR33 */ - union iodefine_reg32_t TMDF033; /* TMDF033 */ - union iodefine_reg32_t TMDF133; /* TMDF133 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID34; /* TMID34 */ - union iodefine_reg32_t TMPTR34; /* TMPTR34 */ - union iodefine_reg32_t TMDF034; /* TMDF034 */ - union iodefine_reg32_t TMDF134; /* TMDF134 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID35; /* TMID35 */ - union iodefine_reg32_t TMPTR35; /* TMPTR35 */ - union iodefine_reg32_t TMDF035; /* TMDF035 */ - union iodefine_reg32_t TMDF135; /* TMDF135 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID36; /* TMID36 */ - union iodefine_reg32_t TMPTR36; /* TMPTR36 */ - union iodefine_reg32_t TMDF036; /* TMDF036 */ - union iodefine_reg32_t TMDF136; /* TMDF136 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID37; /* TMID37 */ - union iodefine_reg32_t TMPTR37; /* TMPTR37 */ - union iodefine_reg32_t TMDF037; /* TMDF037 */ - union iodefine_reg32_t TMDF137; /* TMDF137 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID38; /* TMID38 */ - union iodefine_reg32_t TMPTR38; /* TMPTR38 */ - union iodefine_reg32_t TMDF038; /* TMDF038 */ - union iodefine_reg32_t TMDF138; /* TMDF138 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID39; /* TMID39 */ - union iodefine_reg32_t TMPTR39; /* TMPTR39 */ - union iodefine_reg32_t TMDF039; /* TMDF039 */ - union iodefine_reg32_t TMDF139; /* TMDF139 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID40; /* TMID40 */ - union iodefine_reg32_t TMPTR40; /* TMPTR40 */ - union iodefine_reg32_t TMDF040; /* TMDF040 */ - union iodefine_reg32_t TMDF140; /* TMDF140 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID41; /* TMID41 */ - union iodefine_reg32_t TMPTR41; /* TMPTR41 */ - union iodefine_reg32_t TMDF041; /* TMDF041 */ - union iodefine_reg32_t TMDF141; /* TMDF141 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID42; /* TMID42 */ - union iodefine_reg32_t TMPTR42; /* TMPTR42 */ - union iodefine_reg32_t TMDF042; /* TMDF042 */ - union iodefine_reg32_t TMDF142; /* TMDF142 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID43; /* TMID43 */ - union iodefine_reg32_t TMPTR43; /* TMPTR43 */ - union iodefine_reg32_t TMDF043; /* TMDF043 */ - union iodefine_reg32_t TMDF143; /* TMDF143 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID44; /* TMID44 */ - union iodefine_reg32_t TMPTR44; /* TMPTR44 */ - union iodefine_reg32_t TMDF044; /* TMDF044 */ - union iodefine_reg32_t TMDF144; /* TMDF144 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID45; /* TMID45 */ - union iodefine_reg32_t TMPTR45; /* TMPTR45 */ - union iodefine_reg32_t TMDF045; /* TMDF045 */ - union iodefine_reg32_t TMDF145; /* TMDF145 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID46; /* TMID46 */ - union iodefine_reg32_t TMPTR46; /* TMPTR46 */ - union iodefine_reg32_t TMDF046; /* TMDF046 */ - union iodefine_reg32_t TMDF146; /* TMDF146 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID47; /* TMID47 */ - union iodefine_reg32_t TMPTR47; /* TMPTR47 */ - union iodefine_reg32_t TMDF047; /* TMDF047 */ - union iodefine_reg32_t TMDF147; /* TMDF147 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID48; /* TMID48 */ - union iodefine_reg32_t TMPTR48; /* TMPTR48 */ - union iodefine_reg32_t TMDF048; /* TMDF048 */ - union iodefine_reg32_t TMDF148; /* TMDF148 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID49; /* TMID49 */ - union iodefine_reg32_t TMPTR49; /* TMPTR49 */ - union iodefine_reg32_t TMDF049; /* TMDF049 */ - union iodefine_reg32_t TMDF149; /* TMDF149 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID50; /* TMID50 */ - union iodefine_reg32_t TMPTR50; /* TMPTR50 */ - union iodefine_reg32_t TMDF050; /* TMDF050 */ - union iodefine_reg32_t TMDF150; /* TMDF150 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID51; /* TMID51 */ - union iodefine_reg32_t TMPTR51; /* TMPTR51 */ - union iodefine_reg32_t TMDF051; /* TMDF051 */ - union iodefine_reg32_t TMDF151; /* TMDF151 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID52; /* TMID52 */ - union iodefine_reg32_t TMPTR52; /* TMPTR52 */ - union iodefine_reg32_t TMDF052; /* TMDF052 */ - union iodefine_reg32_t TMDF152; /* TMDF152 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID53; /* TMID53 */ - union iodefine_reg32_t TMPTR53; /* TMPTR53 */ - union iodefine_reg32_t TMDF053; /* TMDF053 */ - union iodefine_reg32_t TMDF153; /* TMDF153 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID54; /* TMID54 */ - union iodefine_reg32_t TMPTR54; /* TMPTR54 */ - union iodefine_reg32_t TMDF054; /* TMDF054 */ - union iodefine_reg32_t TMDF154; /* TMDF154 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID55; /* TMID55 */ - union iodefine_reg32_t TMPTR55; /* TMPTR55 */ - union iodefine_reg32_t TMDF055; /* TMDF055 */ - union iodefine_reg32_t TMDF155; /* TMDF155 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID56; /* TMID56 */ - union iodefine_reg32_t TMPTR56; /* TMPTR56 */ - union iodefine_reg32_t TMDF056; /* TMDF056 */ - union iodefine_reg32_t TMDF156; /* TMDF156 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID57; /* TMID57 */ - union iodefine_reg32_t TMPTR57; /* TMPTR57 */ - union iodefine_reg32_t TMDF057; /* TMDF057 */ - union iodefine_reg32_t TMDF157; /* TMDF157 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID58; /* TMID58 */ - union iodefine_reg32_t TMPTR58; /* TMPTR58 */ - union iodefine_reg32_t TMDF058; /* TMDF058 */ - union iodefine_reg32_t TMDF158; /* TMDF158 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID59; /* TMID59 */ - union iodefine_reg32_t TMPTR59; /* TMPTR59 */ - union iodefine_reg32_t TMDF059; /* TMDF059 */ - union iodefine_reg32_t TMDF159; /* TMDF159 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID60; /* TMID60 */ - union iodefine_reg32_t TMPTR60; /* TMPTR60 */ - union iodefine_reg32_t TMDF060; /* TMDF060 */ - union iodefine_reg32_t TMDF160; /* TMDF160 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID61; /* TMID61 */ - union iodefine_reg32_t TMPTR61; /* TMPTR61 */ - union iodefine_reg32_t TMDF061; /* TMDF061 */ - union iodefine_reg32_t TMDF161; /* TMDF161 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID62; /* TMID62 */ - union iodefine_reg32_t TMPTR62; /* TMPTR62 */ - union iodefine_reg32_t TMDF062; /* TMDF062 */ - union iodefine_reg32_t TMDF162; /* TMDF162 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID63; /* TMID63 */ - union iodefine_reg32_t TMPTR63; /* TMPTR63 */ - union iodefine_reg32_t TMDF063; /* TMDF063 */ - union iodefine_reg32_t TMDF163; /* TMDF163 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID64; /* TMID64 */ - union iodefine_reg32_t TMPTR64; /* TMPTR64 */ - union iodefine_reg32_t TMDF064; /* TMDF064 */ - union iodefine_reg32_t TMDF164; /* TMDF164 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID65; /* TMID65 */ - union iodefine_reg32_t TMPTR65; /* TMPTR65 */ - union iodefine_reg32_t TMDF065; /* TMDF065 */ - union iodefine_reg32_t TMDF165; /* TMDF165 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID66; /* TMID66 */ - union iodefine_reg32_t TMPTR66; /* TMPTR66 */ - union iodefine_reg32_t TMDF066; /* TMDF066 */ - union iodefine_reg32_t TMDF166; /* TMDF166 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID67; /* TMID67 */ - union iodefine_reg32_t TMPTR67; /* TMPTR67 */ - union iodefine_reg32_t TMDF067; /* TMDF067 */ - union iodefine_reg32_t TMDF167; /* TMDF167 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID68; /* TMID68 */ - union iodefine_reg32_t TMPTR68; /* TMPTR68 */ - union iodefine_reg32_t TMDF068; /* TMDF068 */ - union iodefine_reg32_t TMDF168; /* TMDF168 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID69; /* TMID69 */ - union iodefine_reg32_t TMPTR69; /* TMPTR69 */ - union iodefine_reg32_t TMDF069; /* TMDF069 */ - union iodefine_reg32_t TMDF169; /* TMDF169 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID70; /* TMID70 */ - union iodefine_reg32_t TMPTR70; /* TMPTR70 */ - union iodefine_reg32_t TMDF070; /* TMDF070 */ - union iodefine_reg32_t TMDF170; /* TMDF170 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID71; /* TMID71 */ - union iodefine_reg32_t TMPTR71; /* TMPTR71 */ - union iodefine_reg32_t TMDF071; /* TMDF071 */ - union iodefine_reg32_t TMDF171; /* TMDF171 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID72; /* TMID72 */ - union iodefine_reg32_t TMPTR72; /* TMPTR72 */ - union iodefine_reg32_t TMDF072; /* TMDF072 */ - union iodefine_reg32_t TMDF172; /* TMDF172 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID73; /* TMID73 */ - union iodefine_reg32_t TMPTR73; /* TMPTR73 */ - union iodefine_reg32_t TMDF073; /* TMDF073 */ - union iodefine_reg32_t TMDF173; /* TMDF173 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID74; /* TMID74 */ - union iodefine_reg32_t TMPTR74; /* TMPTR74 */ - union iodefine_reg32_t TMDF074; /* TMDF074 */ - union iodefine_reg32_t TMDF174; /* TMDF174 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID75; /* TMID75 */ - union iodefine_reg32_t TMPTR75; /* TMPTR75 */ - union iodefine_reg32_t TMDF075; /* TMDF075 */ - union iodefine_reg32_t TMDF175; /* TMDF175 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID76; /* TMID76 */ - union iodefine_reg32_t TMPTR76; /* TMPTR76 */ - union iodefine_reg32_t TMDF076; /* TMDF076 */ - union iodefine_reg32_t TMDF176; /* TMDF176 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID77; /* TMID77 */ - union iodefine_reg32_t TMPTR77; /* TMPTR77 */ - union iodefine_reg32_t TMDF077; /* TMDF077 */ - union iodefine_reg32_t TMDF177; /* TMDF177 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID78; /* TMID78 */ - union iodefine_reg32_t TMPTR78; /* TMPTR78 */ - union iodefine_reg32_t TMDF078; /* TMDF078 */ - union iodefine_reg32_t TMDF178; /* TMDF178 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID79; /* TMID79 */ - union iodefine_reg32_t TMPTR79; /* TMPTR79 */ - union iodefine_reg32_t TMDF079; /* TMDF079 */ - union iodefine_reg32_t TMDF179; /* TMDF179 */ -/* end of struct st_rscan_from_rscan0tmidp */ - - volatile uint8_t dummy181[768]; /* */ -#define RSCAN0_THLACC0_COUNT 5 - union iodefine_reg32_t THLACC0; /* THLACC0 */ - union iodefine_reg32_t THLACC1; /* THLACC1 */ - union iodefine_reg32_t THLACC2; /* THLACC2 */ - union iodefine_reg32_t THLACC3; /* THLACC3 */ - union iodefine_reg32_t THLACC4; /* THLACC4 */ - -}; - - -struct st_rscan_from_rscan0cncfg -{ - union iodefine_reg32_t CnCFG; /* CnCFG */ - union iodefine_reg32_t CnCTR; /* CnCTR */ - union iodefine_reg32_t CnSTS; /* CnSTS */ - union iodefine_reg32_t CnERFL; /* CnERFL */ -}; - - -struct st_rscan_from_rscan0gaflidj -{ - union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ - union iodefine_reg32_t GAFLMj; /* GAFLMj */ - union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ - union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ -}; - - -struct st_rscan_from_rscan0rmidp -{ - union iodefine_reg32_t RMIDp; /* RMIDp */ - union iodefine_reg32_t RMPTRp; /* RMPTRp */ - union iodefine_reg32_t RMDF0p; /* RMDF0p */ - union iodefine_reg32_t RMDF1p; /* RMDF1p */ -}; - - -struct st_rscan_from_rscan0rfidm -{ - union iodefine_reg32_t RFIDm; /* RFIDm */ - union iodefine_reg32_t RFPTRm; /* RFPTRm */ - union iodefine_reg32_t RFDF0m; /* RFDF0m */ - union iodefine_reg32_t RFDF1m; /* RFDF1m */ -}; - - -struct st_rscan_from_rscan0tmidp -{ - union iodefine_reg32_t TMIDp; /* TMIDp */ - union iodefine_reg32_t TMPTRp; /* TMPTRp */ - union iodefine_reg32_t TMDF0p; /* TMDF0p */ - union iodefine_reg32_t TMDF1p; /* TMDF1p */ -}; - - -struct st_rscan_from_rscan0cfidm -{ - union iodefine_reg32_t CFIDm; /* CFIDm */ - union iodefine_reg32_t CFPTRm; /* CFPTRm */ - union iodefine_reg32_t CFDF0m; /* CFDF0m */ - union iodefine_reg32_t CFDF1m; /* CFDF1m */ -}; - - -#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ - - -/* Start of channnel array defines of RSCAN0 */ - -/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15 -#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ - &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */ -#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */ -#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */ -#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */ -#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */ -#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */ -#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */ -#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */ -#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */ -#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */ -#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */ -#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */ -#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */ -#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */ -#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ - - -/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80 -#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ - &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ - &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \ - &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \ - &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \ - &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \ - &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \ - &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \ - &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \ - &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */ -#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */ -#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */ -#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */ -#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */ -#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */ -#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */ -#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */ -#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */ -#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */ -#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */ -#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */ -#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */ -#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */ -#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */ -#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */ -#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */ -#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */ -#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */ -#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */ -#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */ -#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */ -#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */ -#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */ -#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */ -#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */ -#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */ -#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */ -#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */ -#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */ -#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */ -#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */ -#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */ -#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */ -#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */ -#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */ -#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */ -#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */ -#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */ -#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */ -#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */ -#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */ -#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */ -#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */ -#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */ -#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */ -#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */ -#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */ -#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */ -#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */ -#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */ -#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */ -#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */ -#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */ -#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */ -#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */ -#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */ -#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */ -#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */ -#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */ -#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */ -#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */ -#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */ -#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */ -#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */ -#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */ -#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */ -#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */ -#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */ -#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */ -#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */ -#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */ -#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */ -#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */ -#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */ -#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */ -#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */ -#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */ -#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */ -#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ - - -/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8 -#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */ -#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */ -#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */ -#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */ -#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */ -#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */ -#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */ -#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ - - -/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80 -#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ - &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ - &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \ - &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \ - &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \ - &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \ - &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \ - &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \ - &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \ - &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */ -#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */ -#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */ -#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */ -#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */ -#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */ -#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */ -#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */ -#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */ -#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */ -#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */ -#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */ -#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */ -#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */ -#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */ -#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */ -#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */ -#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */ -#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */ -#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */ -#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */ -#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */ -#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */ -#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */ -#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */ -#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */ -#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */ -#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */ -#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */ -#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */ -#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */ -#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */ -#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */ -#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */ -#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */ -#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */ -#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */ -#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */ -#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */ -#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */ -#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */ -#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */ -#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */ -#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */ -#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */ -#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */ -#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */ -#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */ -#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */ -#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */ -#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */ -#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */ -#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */ -#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */ -#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */ -#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */ -#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */ -#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */ -#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */ -#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */ -#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */ -#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */ -#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */ -#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */ -#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */ -#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */ -#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */ -#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */ -#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */ -#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */ -#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */ -#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */ -#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */ -#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */ -#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */ -#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */ -#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */ -#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */ -#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */ -#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ - - -/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */ -/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */ -#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16 -#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ - &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */ -#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */ -#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */ -#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */ -#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */ -#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */ -#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */ -#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */ -#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */ -#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */ -#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */ -#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */ -#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */ -#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */ -#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */ -#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ - - -/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */ -/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */ -#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5 -#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */ -#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */ -#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */ -#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ -#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ - -/* End of channnel array defines of RSCAN0 */ - - -#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32 -#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L] -#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL] -#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH] -#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H] -#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL] -#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH] -#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32 -#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L] -#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL] -#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH] -#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H] -#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL] -#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH] -#define RSCAN0C0STS RSCAN0.C0STS.UINT32 -#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L] -#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL] -#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH] -#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H] -#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL] -#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH] -#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32 -#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L] -#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL] -#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH] -#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H] -#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL] -#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH] -#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32 -#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L] -#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL] -#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH] -#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H] -#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL] -#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH] -#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32 -#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L] -#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL] -#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH] -#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H] -#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL] -#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH] -#define RSCAN0C1STS RSCAN0.C1STS.UINT32 -#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L] -#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL] -#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH] -#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H] -#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL] -#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH] -#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32 -#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L] -#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL] -#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH] -#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H] -#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL] -#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH] -#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32 -#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L] -#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL] -#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH] -#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H] -#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL] -#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH] -#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32 -#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L] -#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL] -#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH] -#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H] -#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL] -#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH] -#define RSCAN0C2STS RSCAN0.C2STS.UINT32 -#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L] -#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL] -#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH] -#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H] -#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL] -#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH] -#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32 -#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L] -#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL] -#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH] -#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H] -#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL] -#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH] -#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32 -#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L] -#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL] -#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH] -#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H] -#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL] -#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH] -#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32 -#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L] -#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL] -#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH] -#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H] -#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL] -#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH] -#define RSCAN0C3STS RSCAN0.C3STS.UINT32 -#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L] -#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL] -#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH] -#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H] -#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL] -#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH] -#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32 -#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L] -#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL] -#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH] -#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H] -#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL] -#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH] -#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32 -#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L] -#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL] -#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH] -#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H] -#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL] -#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH] -#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32 -#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L] -#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL] -#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH] -#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H] -#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL] -#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH] -#define RSCAN0C4STS RSCAN0.C4STS.UINT32 -#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L] -#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL] -#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH] -#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H] -#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL] -#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH] -#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32 -#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L] -#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL] -#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH] -#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H] -#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL] -#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH] -#define RSCAN0GCFG RSCAN0.GCFG.UINT32 -#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L] -#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL] -#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH] -#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H] -#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL] -#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH] -#define RSCAN0GCTR RSCAN0.GCTR.UINT32 -#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L] -#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL] -#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH] -#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H] -#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL] -#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH] -#define RSCAN0GSTS RSCAN0.GSTS.UINT32 -#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L] -#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL] -#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH] -#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H] -#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL] -#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH] -#define RSCAN0GERFL RSCAN0.GERFL.UINT32 -#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L] -#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL] -#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH] -#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H] -#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL] -#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH] -#define RSCAN0GTSC RSCAN0.GTSC.UINT32 -#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L] -#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H] -#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32 -#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L] -#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL] -#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH] -#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H] -#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL] -#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH] -#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32 -#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L] -#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL] -#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH] -#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H] -#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL] -#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH] -#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32 -#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L] -#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL] -#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH] -#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H] -#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL] -#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH] -#define RSCAN0RMNB RSCAN0.RMNB.UINT32 -#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L] -#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL] -#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH] -#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H] -#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL] -#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH] -#define RSCAN0RMND0 RSCAN0.RMND0.UINT32 -#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L] -#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL] -#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH] -#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H] -#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL] -#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH] -#define RSCAN0RMND1 RSCAN0.RMND1.UINT32 -#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L] -#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL] -#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH] -#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H] -#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL] -#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH] -#define RSCAN0RMND2 RSCAN0.RMND2.UINT32 -#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L] -#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL] -#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH] -#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H] -#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL] -#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH] -#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32 -#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L] -#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL] -#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH] -#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H] -#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL] -#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH] -#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32 -#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L] -#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL] -#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH] -#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H] -#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL] -#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH] -#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32 -#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L] -#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL] -#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH] -#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H] -#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL] -#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH] -#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32 -#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L] -#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL] -#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH] -#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H] -#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL] -#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH] -#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32 -#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L] -#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL] -#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH] -#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H] -#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL] -#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH] -#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32 -#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L] -#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL] -#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH] -#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H] -#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL] -#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH] -#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32 -#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L] -#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL] -#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH] -#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H] -#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL] -#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH] -#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32 -#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L] -#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL] -#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH] -#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H] -#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL] -#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH] -#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32 -#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L] -#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL] -#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH] -#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H] -#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL] -#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH] -#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32 -#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L] -#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL] -#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH] -#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H] -#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL] -#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH] -#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32 -#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L] -#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL] -#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH] -#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H] -#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL] -#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH] -#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32 -#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L] -#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL] -#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH] -#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H] -#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL] -#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH] -#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32 -#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L] -#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL] -#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH] -#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H] -#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL] -#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH] -#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32 -#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L] -#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL] -#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH] -#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H] -#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL] -#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH] -#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32 -#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L] -#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL] -#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH] -#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H] -#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL] -#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH] -#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32 -#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L] -#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL] -#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH] -#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H] -#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL] -#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH] -#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32 -#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L] -#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL] -#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH] -#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H] -#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL] -#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH] -#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32 -#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L] -#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL] -#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH] -#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H] -#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL] -#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH] -#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32 -#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L] -#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL] -#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH] -#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H] -#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL] -#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH] -#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32 -#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L] -#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL] -#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH] -#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H] -#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL] -#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH] -#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32 -#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L] -#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL] -#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH] -#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H] -#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL] -#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH] -#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32 -#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L] -#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL] -#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH] -#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H] -#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL] -#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH] -#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32 -#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L] -#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL] -#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH] -#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H] -#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL] -#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH] -#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32 -#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L] -#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL] -#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH] -#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H] -#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL] -#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH] -#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32 -#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L] -#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL] -#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH] -#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H] -#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL] -#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH] -#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32 -#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L] -#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL] -#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH] -#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H] -#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL] -#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH] -#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32 -#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L] -#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL] -#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH] -#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H] -#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL] -#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH] -#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32 -#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L] -#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL] -#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH] -#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H] -#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL] -#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH] -#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32 -#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L] -#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL] -#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH] -#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H] -#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL] -#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH] -#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32 -#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L] -#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL] -#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH] -#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H] -#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL] -#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH] -#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32 -#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L] -#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL] -#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH] -#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H] -#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL] -#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH] -#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32 -#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L] -#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL] -#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH] -#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H] -#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL] -#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH] -#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32 -#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L] -#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL] -#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH] -#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H] -#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL] -#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH] -#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32 -#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L] -#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL] -#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH] -#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H] -#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL] -#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH] -#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32 -#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L] -#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL] -#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH] -#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H] -#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL] -#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH] -#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32 -#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L] -#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL] -#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH] -#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H] -#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL] -#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH] -#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32 -#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L] -#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL] -#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH] -#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H] -#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL] -#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH] -#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32 -#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L] -#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL] -#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH] -#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H] -#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL] -#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH] -#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32 -#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L] -#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL] -#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH] -#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H] -#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL] -#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH] -#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32 -#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L] -#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL] -#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH] -#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H] -#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL] -#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH] -#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32 -#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L] -#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL] -#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH] -#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H] -#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL] -#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH] -#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32 -#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L] -#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL] -#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH] -#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H] -#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL] -#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH] -#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32 -#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L] -#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL] -#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH] -#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H] -#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL] -#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH] -#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32 -#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L] -#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL] -#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH] -#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H] -#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL] -#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH] -#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32 -#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L] -#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL] -#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH] -#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H] -#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL] -#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH] -#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32 -#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L] -#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL] -#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH] -#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H] -#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL] -#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH] -#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32 -#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L] -#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL] -#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH] -#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H] -#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL] -#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH] -#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32 -#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L] -#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL] -#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH] -#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H] -#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL] -#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH] -#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32 -#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L] -#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL] -#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH] -#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H] -#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL] -#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH] -#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32 -#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L] -#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL] -#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH] -#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H] -#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL] -#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH] -#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32 -#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L] -#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL] -#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH] -#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H] -#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL] -#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH] -#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32 -#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L] -#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL] -#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH] -#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H] -#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL] -#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH] -#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32 -#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L] -#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL] -#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH] -#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H] -#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL] -#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH] -#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32 -#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L] -#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL] -#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH] -#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H] -#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL] -#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH] -#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32 -#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L] -#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL] -#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH] -#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H] -#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL] -#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH] -#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32 -#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L] -#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL] -#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH] -#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H] -#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL] -#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH] -#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32 -#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L] -#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL] -#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH] -#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H] -#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL] -#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH] -#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32 -#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L] -#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL] -#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH] -#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H] -#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL] -#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH] -#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32 -#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L] -#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL] -#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH] -#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H] -#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL] -#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH] -#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32 -#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L] -#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL] -#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH] -#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H] -#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL] -#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH] -#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32 -#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L] -#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL] -#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH] -#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H] -#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL] -#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH] -#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32 -#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L] -#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL] -#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH] -#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H] -#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL] -#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH] -#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32 -#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L] -#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL] -#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH] -#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H] -#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL] -#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH] -#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32 -#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L] -#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL] -#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH] -#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H] -#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL] -#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH] -#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32 -#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L] -#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL] -#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH] -#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H] -#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL] -#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH] -#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32 -#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L] -#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL] -#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH] -#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H] -#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL] -#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH] -#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32 -#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L] -#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL] -#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH] -#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H] -#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL] -#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH] -#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32 -#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L] -#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL] -#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH] -#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H] -#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL] -#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH] -#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32 -#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L] -#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL] -#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH] -#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H] -#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL] -#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH] -#define RSCAN0FESTS RSCAN0.FESTS.UINT32 -#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L] -#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL] -#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH] -#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H] -#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL] -#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH] -#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32 -#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L] -#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL] -#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH] -#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H] -#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL] -#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH] -#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32 -#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L] -#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL] -#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH] -#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H] -#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL] -#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH] -#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32 -#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L] -#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL] -#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH] -#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H] -#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL] -#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH] -#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32 -#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L] -#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL] -#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH] -#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H] -#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL] -#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH] -#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32 -#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L] -#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL] -#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH] -#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H] -#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL] -#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH] -#define RSCAN0TMC0 RSCAN0.TMC0 -#define RSCAN0TMC1 RSCAN0.TMC1 -#define RSCAN0TMC2 RSCAN0.TMC2 -#define RSCAN0TMC3 RSCAN0.TMC3 -#define RSCAN0TMC4 RSCAN0.TMC4 -#define RSCAN0TMC5 RSCAN0.TMC5 -#define RSCAN0TMC6 RSCAN0.TMC6 -#define RSCAN0TMC7 RSCAN0.TMC7 -#define RSCAN0TMC8 RSCAN0.TMC8 -#define RSCAN0TMC9 RSCAN0.TMC9 -#define RSCAN0TMC10 RSCAN0.TMC10 -#define RSCAN0TMC11 RSCAN0.TMC11 -#define RSCAN0TMC12 RSCAN0.TMC12 -#define RSCAN0TMC13 RSCAN0.TMC13 -#define RSCAN0TMC14 RSCAN0.TMC14 -#define RSCAN0TMC15 RSCAN0.TMC15 -#define RSCAN0TMC16 RSCAN0.TMC16 -#define RSCAN0TMC17 RSCAN0.TMC17 -#define RSCAN0TMC18 RSCAN0.TMC18 -#define RSCAN0TMC19 RSCAN0.TMC19 -#define RSCAN0TMC20 RSCAN0.TMC20 -#define RSCAN0TMC21 RSCAN0.TMC21 -#define RSCAN0TMC22 RSCAN0.TMC22 -#define RSCAN0TMC23 RSCAN0.TMC23 -#define RSCAN0TMC24 RSCAN0.TMC24 -#define RSCAN0TMC25 RSCAN0.TMC25 -#define RSCAN0TMC26 RSCAN0.TMC26 -#define RSCAN0TMC27 RSCAN0.TMC27 -#define RSCAN0TMC28 RSCAN0.TMC28 -#define RSCAN0TMC29 RSCAN0.TMC29 -#define RSCAN0TMC30 RSCAN0.TMC30 -#define RSCAN0TMC31 RSCAN0.TMC31 -#define RSCAN0TMC32 RSCAN0.TMC32 -#define RSCAN0TMC33 RSCAN0.TMC33 -#define RSCAN0TMC34 RSCAN0.TMC34 -#define RSCAN0TMC35 RSCAN0.TMC35 -#define RSCAN0TMC36 RSCAN0.TMC36 -#define RSCAN0TMC37 RSCAN0.TMC37 -#define RSCAN0TMC38 RSCAN0.TMC38 -#define RSCAN0TMC39 RSCAN0.TMC39 -#define RSCAN0TMC40 RSCAN0.TMC40 -#define RSCAN0TMC41 RSCAN0.TMC41 -#define RSCAN0TMC42 RSCAN0.TMC42 -#define RSCAN0TMC43 RSCAN0.TMC43 -#define RSCAN0TMC44 RSCAN0.TMC44 -#define RSCAN0TMC45 RSCAN0.TMC45 -#define RSCAN0TMC46 RSCAN0.TMC46 -#define RSCAN0TMC47 RSCAN0.TMC47 -#define RSCAN0TMC48 RSCAN0.TMC48 -#define RSCAN0TMC49 RSCAN0.TMC49 -#define RSCAN0TMC50 RSCAN0.TMC50 -#define RSCAN0TMC51 RSCAN0.TMC51 -#define RSCAN0TMC52 RSCAN0.TMC52 -#define RSCAN0TMC53 RSCAN0.TMC53 -#define RSCAN0TMC54 RSCAN0.TMC54 -#define RSCAN0TMC55 RSCAN0.TMC55 -#define RSCAN0TMC56 RSCAN0.TMC56 -#define RSCAN0TMC57 RSCAN0.TMC57 -#define RSCAN0TMC58 RSCAN0.TMC58 -#define RSCAN0TMC59 RSCAN0.TMC59 -#define RSCAN0TMC60 RSCAN0.TMC60 -#define RSCAN0TMC61 RSCAN0.TMC61 -#define RSCAN0TMC62 RSCAN0.TMC62 -#define RSCAN0TMC63 RSCAN0.TMC63 -#define RSCAN0TMC64 RSCAN0.TMC64 -#define RSCAN0TMC65 RSCAN0.TMC65 -#define RSCAN0TMC66 RSCAN0.TMC66 -#define RSCAN0TMC67 RSCAN0.TMC67 -#define RSCAN0TMC68 RSCAN0.TMC68 -#define RSCAN0TMC69 RSCAN0.TMC69 -#define RSCAN0TMC70 RSCAN0.TMC70 -#define RSCAN0TMC71 RSCAN0.TMC71 -#define RSCAN0TMC72 RSCAN0.TMC72 -#define RSCAN0TMC73 RSCAN0.TMC73 -#define RSCAN0TMC74 RSCAN0.TMC74 -#define RSCAN0TMC75 RSCAN0.TMC75 -#define RSCAN0TMC76 RSCAN0.TMC76 -#define RSCAN0TMC77 RSCAN0.TMC77 -#define RSCAN0TMC78 RSCAN0.TMC78 -#define RSCAN0TMC79 RSCAN0.TMC79 -#define RSCAN0TMSTS0 RSCAN0.TMSTS0 -#define RSCAN0TMSTS1 RSCAN0.TMSTS1 -#define RSCAN0TMSTS2 RSCAN0.TMSTS2 -#define RSCAN0TMSTS3 RSCAN0.TMSTS3 -#define RSCAN0TMSTS4 RSCAN0.TMSTS4 -#define RSCAN0TMSTS5 RSCAN0.TMSTS5 -#define RSCAN0TMSTS6 RSCAN0.TMSTS6 -#define RSCAN0TMSTS7 RSCAN0.TMSTS7 -#define RSCAN0TMSTS8 RSCAN0.TMSTS8 -#define RSCAN0TMSTS9 RSCAN0.TMSTS9 -#define RSCAN0TMSTS10 RSCAN0.TMSTS10 -#define RSCAN0TMSTS11 RSCAN0.TMSTS11 -#define RSCAN0TMSTS12 RSCAN0.TMSTS12 -#define RSCAN0TMSTS13 RSCAN0.TMSTS13 -#define RSCAN0TMSTS14 RSCAN0.TMSTS14 -#define RSCAN0TMSTS15 RSCAN0.TMSTS15 -#define RSCAN0TMSTS16 RSCAN0.TMSTS16 -#define RSCAN0TMSTS17 RSCAN0.TMSTS17 -#define RSCAN0TMSTS18 RSCAN0.TMSTS18 -#define RSCAN0TMSTS19 RSCAN0.TMSTS19 -#define RSCAN0TMSTS20 RSCAN0.TMSTS20 -#define RSCAN0TMSTS21 RSCAN0.TMSTS21 -#define RSCAN0TMSTS22 RSCAN0.TMSTS22 -#define RSCAN0TMSTS23 RSCAN0.TMSTS23 -#define RSCAN0TMSTS24 RSCAN0.TMSTS24 -#define RSCAN0TMSTS25 RSCAN0.TMSTS25 -#define RSCAN0TMSTS26 RSCAN0.TMSTS26 -#define RSCAN0TMSTS27 RSCAN0.TMSTS27 -#define RSCAN0TMSTS28 RSCAN0.TMSTS28 -#define RSCAN0TMSTS29 RSCAN0.TMSTS29 -#define RSCAN0TMSTS30 RSCAN0.TMSTS30 -#define RSCAN0TMSTS31 RSCAN0.TMSTS31 -#define RSCAN0TMSTS32 RSCAN0.TMSTS32 -#define RSCAN0TMSTS33 RSCAN0.TMSTS33 -#define RSCAN0TMSTS34 RSCAN0.TMSTS34 -#define RSCAN0TMSTS35 RSCAN0.TMSTS35 -#define RSCAN0TMSTS36 RSCAN0.TMSTS36 -#define RSCAN0TMSTS37 RSCAN0.TMSTS37 -#define RSCAN0TMSTS38 RSCAN0.TMSTS38 -#define RSCAN0TMSTS39 RSCAN0.TMSTS39 -#define RSCAN0TMSTS40 RSCAN0.TMSTS40 -#define RSCAN0TMSTS41 RSCAN0.TMSTS41 -#define RSCAN0TMSTS42 RSCAN0.TMSTS42 -#define RSCAN0TMSTS43 RSCAN0.TMSTS43 -#define RSCAN0TMSTS44 RSCAN0.TMSTS44 -#define RSCAN0TMSTS45 RSCAN0.TMSTS45 -#define RSCAN0TMSTS46 RSCAN0.TMSTS46 -#define RSCAN0TMSTS47 RSCAN0.TMSTS47 -#define RSCAN0TMSTS48 RSCAN0.TMSTS48 -#define RSCAN0TMSTS49 RSCAN0.TMSTS49 -#define RSCAN0TMSTS50 RSCAN0.TMSTS50 -#define RSCAN0TMSTS51 RSCAN0.TMSTS51 -#define RSCAN0TMSTS52 RSCAN0.TMSTS52 -#define RSCAN0TMSTS53 RSCAN0.TMSTS53 -#define RSCAN0TMSTS54 RSCAN0.TMSTS54 -#define RSCAN0TMSTS55 RSCAN0.TMSTS55 -#define RSCAN0TMSTS56 RSCAN0.TMSTS56 -#define RSCAN0TMSTS57 RSCAN0.TMSTS57 -#define RSCAN0TMSTS58 RSCAN0.TMSTS58 -#define RSCAN0TMSTS59 RSCAN0.TMSTS59 -#define RSCAN0TMSTS60 RSCAN0.TMSTS60 -#define RSCAN0TMSTS61 RSCAN0.TMSTS61 -#define RSCAN0TMSTS62 RSCAN0.TMSTS62 -#define RSCAN0TMSTS63 RSCAN0.TMSTS63 -#define RSCAN0TMSTS64 RSCAN0.TMSTS64 -#define RSCAN0TMSTS65 RSCAN0.TMSTS65 -#define RSCAN0TMSTS66 RSCAN0.TMSTS66 -#define RSCAN0TMSTS67 RSCAN0.TMSTS67 -#define RSCAN0TMSTS68 RSCAN0.TMSTS68 -#define RSCAN0TMSTS69 RSCAN0.TMSTS69 -#define RSCAN0TMSTS70 RSCAN0.TMSTS70 -#define RSCAN0TMSTS71 RSCAN0.TMSTS71 -#define RSCAN0TMSTS72 RSCAN0.TMSTS72 -#define RSCAN0TMSTS73 RSCAN0.TMSTS73 -#define RSCAN0TMSTS74 RSCAN0.TMSTS74 -#define RSCAN0TMSTS75 RSCAN0.TMSTS75 -#define RSCAN0TMSTS76 RSCAN0.TMSTS76 -#define RSCAN0TMSTS77 RSCAN0.TMSTS77 -#define RSCAN0TMSTS78 RSCAN0.TMSTS78 -#define RSCAN0TMSTS79 RSCAN0.TMSTS79 -#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32 -#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L] -#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL] -#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH] -#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H] -#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL] -#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH] -#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32 -#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L] -#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL] -#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH] -#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H] -#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL] -#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH] -#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32 -#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L] -#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL] -#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH] -#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H] -#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL] -#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH] -#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32 -#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L] -#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL] -#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH] -#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H] -#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL] -#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH] -#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32 -#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L] -#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL] -#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH] -#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H] -#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL] -#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH] -#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32 -#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L] -#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL] -#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH] -#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H] -#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL] -#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH] -#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32 -#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L] -#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL] -#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH] -#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H] -#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL] -#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH] -#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32 -#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L] -#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL] -#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH] -#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H] -#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL] -#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH] -#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32 -#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L] -#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL] -#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH] -#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H] -#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL] -#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH] -#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32 -#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L] -#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL] -#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH] -#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H] -#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL] -#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH] -#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32 -#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L] -#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL] -#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH] -#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H] -#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL] -#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH] -#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32 -#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L] -#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL] -#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH] -#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H] -#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL] -#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH] -#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32 -#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L] -#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL] -#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH] -#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H] -#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL] -#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH] -#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32 -#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L] -#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL] -#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH] -#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H] -#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL] -#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH] -#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32 -#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L] -#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL] -#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH] -#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H] -#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL] -#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH] -#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32 -#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L] -#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL] -#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH] -#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H] -#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL] -#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH] -#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32 -#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L] -#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL] -#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH] -#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H] -#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL] -#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH] -#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32 -#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L] -#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL] -#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH] -#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H] -#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL] -#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH] -#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32 -#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L] -#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL] -#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH] -#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H] -#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL] -#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH] -#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32 -#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L] -#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL] -#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH] -#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H] -#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL] -#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH] -#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32 -#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L] -#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL] -#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH] -#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H] -#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL] -#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH] -#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32 -#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L] -#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL] -#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH] -#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H] -#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL] -#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH] -#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32 -#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L] -#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL] -#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH] -#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H] -#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL] -#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH] -#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32 -#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L] -#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL] -#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH] -#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H] -#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL] -#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH] -#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32 -#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L] -#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL] -#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH] -#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H] -#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL] -#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH] -#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32 -#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L] -#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL] -#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH] -#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H] -#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL] -#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH] -#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32 -#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L] -#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL] -#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH] -#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H] -#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL] -#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH] -#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32 -#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L] -#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL] -#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH] -#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H] -#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL] -#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH] -#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32 -#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L] -#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL] -#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH] -#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H] -#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL] -#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH] -#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32 -#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L] -#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL] -#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH] -#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H] -#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL] -#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH] -#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32 -#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L] -#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL] -#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH] -#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H] -#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL] -#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH] -#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32 -#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L] -#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL] -#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH] -#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H] -#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL] -#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH] -#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32 -#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L] -#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL] -#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH] -#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H] -#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL] -#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH] -#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32 -#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L] -#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL] -#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH] -#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H] -#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL] -#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH] -#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32 -#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L] -#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL] -#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH] -#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H] -#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL] -#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH] -#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32 -#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L] -#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL] -#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH] -#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H] -#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL] -#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH] -#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32 -#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L] -#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL] -#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH] -#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H] -#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL] -#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH] -#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32 -#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L] -#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL] -#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH] -#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H] -#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL] -#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH] -#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32 -#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L] -#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL] -#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH] -#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H] -#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL] -#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH] -#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32 -#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L] -#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL] -#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH] -#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H] -#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL] -#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH] -#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32 -#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L] -#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL] -#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH] -#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H] -#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL] -#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH] -#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32 -#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L] -#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL] -#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH] -#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H] -#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL] -#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH] -#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32 -#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L] -#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL] -#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH] -#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H] -#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL] -#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH] -#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32 -#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L] -#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL] -#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH] -#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H] -#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL] -#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH] -#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32 -#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L] -#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL] -#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH] -#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H] -#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL] -#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH] -#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32 -#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L] -#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL] -#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH] -#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H] -#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL] -#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH] -#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32 -#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L] -#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL] -#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH] -#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H] -#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL] -#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH] -#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32 -#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L] -#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL] -#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH] -#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H] -#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL] -#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH] -#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32 -#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L] -#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL] -#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH] -#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H] -#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL] -#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH] -#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32 -#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L] -#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H] -#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32 -#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L] -#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL] -#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH] -#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H] -#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL] -#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH] -#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32 -#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L] -#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL] -#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH] -#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H] -#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL] -#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH] -#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32 -#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L] -#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL] -#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH] -#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H] -#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL] -#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH] -#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32 -#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L] -#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL] -#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH] -#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H] -#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL] -#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH] -#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32 -#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L] -#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL] -#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH] -#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H] -#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL] -#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH] -#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32 -#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L] -#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL] -#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH] -#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H] -#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL] -#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH] -#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32 -#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L] -#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL] -#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH] -#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H] -#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL] -#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH] -#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32 -#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L] -#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL] -#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH] -#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H] -#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL] -#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH] -#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32 -#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L] -#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL] -#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH] -#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H] -#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL] -#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH] -#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32 -#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L] -#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL] -#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH] -#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H] -#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL] -#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH] -#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32 -#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L] -#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL] -#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH] -#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H] -#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL] -#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH] -#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32 -#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L] -#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL] -#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH] -#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H] -#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL] -#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH] -#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32 -#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L] -#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL] -#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH] -#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H] -#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL] -#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH] -#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32 -#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L] -#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL] -#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH] -#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H] -#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL] -#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH] -#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32 -#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L] -#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL] -#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH] -#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H] -#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL] -#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH] -#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32 -#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L] -#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL] -#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH] -#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H] -#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL] -#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH] -#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32 -#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L] -#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL] -#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH] -#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H] -#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL] -#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH] -#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32 -#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L] -#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL] -#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH] -#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H] -#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL] -#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH] -#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32 -#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L] -#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL] -#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH] -#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H] -#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL] -#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH] -#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32 -#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L] -#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL] -#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH] -#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H] -#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL] -#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH] -#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32 -#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L] -#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL] -#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH] -#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H] -#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL] -#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH] -#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32 -#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L] -#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL] -#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH] -#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H] -#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL] -#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH] -#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32 -#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L] -#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL] -#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH] -#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H] -#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL] -#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH] -#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32 -#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L] -#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL] -#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH] -#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H] -#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL] -#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH] -#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32 -#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L] -#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL] -#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH] -#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H] -#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL] -#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH] -#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32 -#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L] -#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL] -#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH] -#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H] -#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL] -#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH] -#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32 -#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L] -#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL] -#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH] -#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H] -#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL] -#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH] -#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32 -#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L] -#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL] -#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH] -#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H] -#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL] -#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH] -#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32 -#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L] -#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL] -#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH] -#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H] -#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL] -#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH] -#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32 -#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L] -#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL] -#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH] -#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H] -#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL] -#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH] -#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32 -#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L] -#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL] -#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH] -#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H] -#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL] -#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH] -#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32 -#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L] -#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL] -#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH] -#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H] -#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL] -#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH] -#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32 -#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L] -#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL] -#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH] -#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H] -#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL] -#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH] -#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32 -#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L] -#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL] -#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH] -#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H] -#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL] -#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH] -#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32 -#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L] -#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL] -#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH] -#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H] -#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL] -#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH] -#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32 -#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L] -#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL] -#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH] -#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H] -#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL] -#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH] -#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32 -#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L] -#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL] -#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH] -#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H] -#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL] -#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH] -#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32 -#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L] -#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL] -#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH] -#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H] -#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL] -#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH] -#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32 -#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L] -#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL] -#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH] -#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H] -#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL] -#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH] -#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32 -#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L] -#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL] -#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH] -#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H] -#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL] -#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH] -#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32 -#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L] -#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL] -#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH] -#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H] -#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL] -#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH] -#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32 -#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L] -#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL] -#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH] -#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H] -#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL] -#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH] -#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32 -#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L] -#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL] -#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH] -#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H] -#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL] -#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH] -#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32 -#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L] -#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL] -#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH] -#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H] -#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL] -#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH] -#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32 -#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L] -#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL] -#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH] -#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H] -#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL] -#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH] -#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32 -#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L] -#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL] -#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH] -#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H] -#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL] -#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH] -#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32 -#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L] -#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL] -#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH] -#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H] -#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL] -#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH] -#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32 -#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L] -#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL] -#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH] -#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H] -#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL] -#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH] -#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32 -#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L] -#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL] -#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH] -#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H] -#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL] -#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH] -#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32 -#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L] -#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL] -#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH] -#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H] -#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL] -#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH] -#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32 -#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L] -#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL] -#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH] -#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H] -#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL] -#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH] -#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32 -#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L] -#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL] -#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH] -#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H] -#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL] -#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH] -#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32 -#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L] -#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL] -#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH] -#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H] -#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL] -#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH] -#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32 -#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L] -#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL] -#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH] -#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H] -#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL] -#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH] -#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32 -#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L] -#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL] -#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH] -#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H] -#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL] -#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH] -#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32 -#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L] -#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL] -#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH] -#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H] -#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL] -#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH] -#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32 -#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L] -#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL] -#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH] -#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H] -#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL] -#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH] -#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32 -#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L] -#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL] -#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH] -#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H] -#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL] -#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH] -#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32 -#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L] -#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL] -#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH] -#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H] -#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL] -#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH] -#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32 -#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L] -#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL] -#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH] -#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H] -#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL] -#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH] -#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32 -#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L] -#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL] -#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH] -#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H] -#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL] -#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH] -#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32 -#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L] -#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL] -#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH] -#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H] -#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL] -#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH] -#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32 -#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L] -#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL] -#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH] -#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H] -#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL] -#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH] -#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32 -#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L] -#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL] -#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH] -#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H] -#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL] -#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH] -#define RSCAN0RMID0 RSCAN0.RMID0.UINT32 -#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L] -#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL] -#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH] -#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H] -#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL] -#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH] -#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32 -#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L] -#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL] -#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH] -#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H] -#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL] -#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH] -#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32 -#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L] -#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL] -#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH] -#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H] -#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL] -#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH] -#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32 -#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L] -#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL] -#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH] -#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H] -#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL] -#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH] -#define RSCAN0RMID1 RSCAN0.RMID1.UINT32 -#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L] -#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL] -#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH] -#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H] -#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL] -#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH] -#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32 -#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L] -#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL] -#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH] -#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H] -#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL] -#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH] -#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32 -#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L] -#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL] -#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH] -#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H] -#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL] -#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH] -#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32 -#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L] -#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL] -#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH] -#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H] -#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL] -#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH] -#define RSCAN0RMID2 RSCAN0.RMID2.UINT32 -#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L] -#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL] -#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH] -#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H] -#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL] -#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH] -#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32 -#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L] -#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL] -#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH] -#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H] -#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL] -#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH] -#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32 -#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L] -#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL] -#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH] -#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H] -#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL] -#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH] -#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32 -#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L] -#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL] -#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH] -#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H] -#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL] -#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH] -#define RSCAN0RMID3 RSCAN0.RMID3.UINT32 -#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L] -#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL] -#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH] -#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H] -#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL] -#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH] -#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32 -#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L] -#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL] -#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH] -#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H] -#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL] -#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH] -#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32 -#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L] -#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL] -#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH] -#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H] -#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL] -#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH] -#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32 -#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L] -#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL] -#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH] -#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H] -#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL] -#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH] -#define RSCAN0RMID4 RSCAN0.RMID4.UINT32 -#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L] -#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL] -#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH] -#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H] -#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL] -#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH] -#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32 -#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L] -#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL] -#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH] -#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H] -#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL] -#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH] -#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32 -#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L] -#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL] -#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH] -#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H] -#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL] -#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH] -#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32 -#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L] -#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL] -#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH] -#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H] -#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL] -#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH] -#define RSCAN0RMID5 RSCAN0.RMID5.UINT32 -#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L] -#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL] -#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH] -#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H] -#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL] -#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH] -#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32 -#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L] -#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL] -#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH] -#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H] -#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL] -#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH] -#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32 -#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L] -#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL] -#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH] -#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H] -#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL] -#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH] -#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32 -#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L] -#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL] -#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH] -#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H] -#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL] -#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH] -#define RSCAN0RMID6 RSCAN0.RMID6.UINT32 -#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L] -#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL] -#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH] -#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H] -#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL] -#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH] -#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32 -#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L] -#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL] -#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH] -#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H] -#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL] -#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH] -#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32 -#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L] -#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL] -#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH] -#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H] -#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL] -#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH] -#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32 -#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L] -#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL] -#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH] -#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H] -#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL] -#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH] -#define RSCAN0RMID7 RSCAN0.RMID7.UINT32 -#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L] -#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL] -#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH] -#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H] -#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL] -#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH] -#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32 -#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L] -#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL] -#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH] -#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H] -#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL] -#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH] -#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32 -#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L] -#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL] -#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH] -#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H] -#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL] -#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH] -#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32 -#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L] -#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL] -#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH] -#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H] -#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL] -#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH] -#define RSCAN0RMID8 RSCAN0.RMID8.UINT32 -#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L] -#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL] -#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH] -#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H] -#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL] -#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH] -#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32 -#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L] -#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL] -#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH] -#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H] -#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL] -#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH] -#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32 -#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L] -#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL] -#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH] -#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H] -#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL] -#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH] -#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32 -#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L] -#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL] -#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH] -#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H] -#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL] -#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH] -#define RSCAN0RMID9 RSCAN0.RMID9.UINT32 -#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L] -#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL] -#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH] -#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H] -#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL] -#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH] -#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32 -#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L] -#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL] -#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH] -#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H] -#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL] -#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH] -#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32 -#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L] -#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL] -#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH] -#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H] -#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL] -#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH] -#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32 -#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L] -#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL] -#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH] -#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H] -#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL] -#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH] -#define RSCAN0RMID10 RSCAN0.RMID10.UINT32 -#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L] -#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL] -#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH] -#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H] -#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL] -#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH] -#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32 -#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L] -#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL] -#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH] -#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H] -#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL] -#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH] -#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32 -#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L] -#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL] -#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH] -#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H] -#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL] -#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH] -#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32 -#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L] -#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL] -#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH] -#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H] -#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL] -#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH] -#define RSCAN0RMID11 RSCAN0.RMID11.UINT32 -#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L] -#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL] -#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH] -#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H] -#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL] -#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH] -#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32 -#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L] -#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL] -#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH] -#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H] -#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL] -#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH] -#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32 -#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L] -#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL] -#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH] -#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H] -#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL] -#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH] -#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32 -#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L] -#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL] -#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH] -#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H] -#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL] -#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH] -#define RSCAN0RMID12 RSCAN0.RMID12.UINT32 -#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L] -#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL] -#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH] -#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H] -#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL] -#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH] -#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32 -#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L] -#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL] -#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH] -#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H] -#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL] -#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH] -#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32 -#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L] -#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL] -#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH] -#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H] -#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL] -#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH] -#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32 -#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L] -#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL] -#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH] -#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H] -#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL] -#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH] -#define RSCAN0RMID13 RSCAN0.RMID13.UINT32 -#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L] -#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL] -#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH] -#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H] -#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL] -#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH] -#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32 -#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L] -#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL] -#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH] -#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H] -#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL] -#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH] -#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32 -#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L] -#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL] -#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH] -#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H] -#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL] -#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH] -#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32 -#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L] -#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL] -#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH] -#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H] -#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL] -#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH] -#define RSCAN0RMID14 RSCAN0.RMID14.UINT32 -#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L] -#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL] -#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH] -#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H] -#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL] -#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH] -#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32 -#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L] -#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL] -#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH] -#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H] -#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL] -#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH] -#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32 -#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L] -#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL] -#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH] -#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H] -#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL] -#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH] -#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32 -#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L] -#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL] -#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH] -#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H] -#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL] -#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH] -#define RSCAN0RMID15 RSCAN0.RMID15.UINT32 -#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L] -#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL] -#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH] -#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H] -#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL] -#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH] -#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32 -#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L] -#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL] -#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH] -#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H] -#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL] -#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH] -#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32 -#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L] -#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL] -#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH] -#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H] -#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL] -#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH] -#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32 -#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L] -#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL] -#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH] -#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H] -#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL] -#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH] -#define RSCAN0RMID16 RSCAN0.RMID16.UINT32 -#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L] -#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL] -#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH] -#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H] -#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL] -#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH] -#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32 -#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L] -#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL] -#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH] -#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H] -#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL] -#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH] -#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32 -#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L] -#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL] -#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH] -#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H] -#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL] -#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH] -#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32 -#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L] -#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL] -#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH] -#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H] -#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL] -#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH] -#define RSCAN0RMID17 RSCAN0.RMID17.UINT32 -#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L] -#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL] -#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH] -#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H] -#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL] -#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH] -#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32 -#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L] -#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL] -#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH] -#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H] -#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL] -#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH] -#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32 -#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L] -#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL] -#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH] -#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H] -#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL] -#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH] -#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32 -#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L] -#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL] -#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH] -#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H] -#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL] -#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH] -#define RSCAN0RMID18 RSCAN0.RMID18.UINT32 -#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L] -#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL] -#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH] -#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H] -#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL] -#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH] -#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32 -#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L] -#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL] -#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH] -#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H] -#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL] -#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH] -#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32 -#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L] -#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL] -#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH] -#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H] -#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL] -#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH] -#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32 -#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L] -#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL] -#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH] -#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H] -#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL] -#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH] -#define RSCAN0RMID19 RSCAN0.RMID19.UINT32 -#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L] -#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL] -#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH] -#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H] -#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL] -#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH] -#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32 -#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L] -#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL] -#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH] -#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H] -#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL] -#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH] -#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32 -#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L] -#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL] -#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH] -#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H] -#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL] -#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH] -#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32 -#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L] -#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL] -#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH] -#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H] -#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL] -#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH] -#define RSCAN0RMID20 RSCAN0.RMID20.UINT32 -#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L] -#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL] -#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH] -#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H] -#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL] -#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH] -#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32 -#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L] -#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL] -#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH] -#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H] -#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL] -#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH] -#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32 -#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L] -#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL] -#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH] -#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H] -#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL] -#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH] -#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32 -#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L] -#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL] -#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH] -#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H] -#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL] -#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH] -#define RSCAN0RMID21 RSCAN0.RMID21.UINT32 -#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L] -#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL] -#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH] -#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H] -#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL] -#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH] -#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32 -#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L] -#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL] -#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH] -#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H] -#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL] -#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH] -#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32 -#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L] -#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL] -#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH] -#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H] -#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL] -#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH] -#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32 -#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L] -#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL] -#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH] -#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H] -#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL] -#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH] -#define RSCAN0RMID22 RSCAN0.RMID22.UINT32 -#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L] -#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL] -#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH] -#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H] -#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL] -#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH] -#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32 -#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L] -#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL] -#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH] -#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H] -#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL] -#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH] -#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32 -#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L] -#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL] -#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH] -#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H] -#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL] -#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH] -#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32 -#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L] -#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL] -#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH] -#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H] -#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL] -#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH] -#define RSCAN0RMID23 RSCAN0.RMID23.UINT32 -#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L] -#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL] -#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH] -#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H] -#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL] -#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH] -#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32 -#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L] -#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL] -#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH] -#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H] -#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL] -#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH] -#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32 -#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L] -#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL] -#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH] -#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H] -#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL] -#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH] -#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32 -#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L] -#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL] -#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH] -#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H] -#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL] -#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH] -#define RSCAN0RMID24 RSCAN0.RMID24.UINT32 -#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L] -#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL] -#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH] -#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H] -#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL] -#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH] -#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32 -#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L] -#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL] -#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH] -#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H] -#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL] -#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH] -#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32 -#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L] -#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL] -#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH] -#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H] -#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL] -#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH] -#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32 -#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L] -#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL] -#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH] -#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H] -#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL] -#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH] -#define RSCAN0RMID25 RSCAN0.RMID25.UINT32 -#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L] -#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL] -#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH] -#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H] -#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL] -#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH] -#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32 -#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L] -#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL] -#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH] -#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H] -#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL] -#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH] -#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32 -#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L] -#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL] -#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH] -#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H] -#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL] -#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH] -#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32 -#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L] -#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL] -#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH] -#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H] -#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL] -#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH] -#define RSCAN0RMID26 RSCAN0.RMID26.UINT32 -#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L] -#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL] -#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH] -#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H] -#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL] -#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH] -#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32 -#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L] -#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL] -#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH] -#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H] -#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL] -#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH] -#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32 -#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L] -#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL] -#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH] -#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H] -#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL] -#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH] -#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32 -#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L] -#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL] -#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH] -#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H] -#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL] -#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH] -#define RSCAN0RMID27 RSCAN0.RMID27.UINT32 -#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L] -#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL] -#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH] -#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H] -#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL] -#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH] -#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32 -#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L] -#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL] -#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH] -#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H] -#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL] -#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH] -#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32 -#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L] -#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL] -#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH] -#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H] -#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL] -#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH] -#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32 -#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L] -#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL] -#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH] -#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H] -#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL] -#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH] -#define RSCAN0RMID28 RSCAN0.RMID28.UINT32 -#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L] -#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL] -#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH] -#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H] -#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL] -#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH] -#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32 -#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L] -#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL] -#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH] -#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H] -#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL] -#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH] -#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32 -#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L] -#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL] -#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH] -#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H] -#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL] -#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH] -#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32 -#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L] -#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL] -#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH] -#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H] -#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL] -#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH] -#define RSCAN0RMID29 RSCAN0.RMID29.UINT32 -#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L] -#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL] -#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH] -#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H] -#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL] -#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH] -#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32 -#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L] -#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL] -#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH] -#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H] -#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL] -#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH] -#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32 -#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L] -#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL] -#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH] -#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H] -#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL] -#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH] -#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32 -#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L] -#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL] -#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH] -#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H] -#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL] -#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH] -#define RSCAN0RMID30 RSCAN0.RMID30.UINT32 -#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L] -#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL] -#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH] -#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H] -#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL] -#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH] -#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32 -#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L] -#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL] -#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH] -#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H] -#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL] -#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH] -#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32 -#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L] -#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL] -#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH] -#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H] -#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL] -#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH] -#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32 -#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L] -#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL] -#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH] -#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H] -#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL] -#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH] -#define RSCAN0RMID31 RSCAN0.RMID31.UINT32 -#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L] -#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL] -#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH] -#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H] -#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL] -#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH] -#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32 -#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L] -#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL] -#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH] -#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H] -#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL] -#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH] -#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32 -#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L] -#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL] -#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH] -#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H] -#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL] -#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH] -#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32 -#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L] -#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL] -#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH] -#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H] -#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL] -#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH] -#define RSCAN0RMID32 RSCAN0.RMID32.UINT32 -#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L] -#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL] -#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH] -#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H] -#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL] -#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH] -#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32 -#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L] -#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL] -#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH] -#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H] -#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL] -#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH] -#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32 -#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L] -#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL] -#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH] -#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H] -#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL] -#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH] -#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32 -#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L] -#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL] -#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH] -#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H] -#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL] -#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH] -#define RSCAN0RMID33 RSCAN0.RMID33.UINT32 -#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L] -#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL] -#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH] -#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H] -#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL] -#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH] -#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32 -#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L] -#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL] -#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH] -#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H] -#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL] -#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH] -#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32 -#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L] -#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL] -#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH] -#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H] -#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL] -#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH] -#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32 -#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L] -#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL] -#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH] -#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H] -#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL] -#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH] -#define RSCAN0RMID34 RSCAN0.RMID34.UINT32 -#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L] -#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL] -#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH] -#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H] -#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL] -#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH] -#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32 -#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L] -#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL] -#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH] -#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H] -#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL] -#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH] -#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32 -#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L] -#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL] -#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH] -#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H] -#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL] -#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH] -#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32 -#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L] -#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL] -#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH] -#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H] -#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL] -#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH] -#define RSCAN0RMID35 RSCAN0.RMID35.UINT32 -#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L] -#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL] -#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH] -#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H] -#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL] -#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH] -#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32 -#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L] -#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL] -#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH] -#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H] -#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL] -#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH] -#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32 -#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L] -#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL] -#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH] -#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H] -#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL] -#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH] -#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32 -#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L] -#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL] -#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH] -#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H] -#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL] -#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH] -#define RSCAN0RMID36 RSCAN0.RMID36.UINT32 -#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L] -#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL] -#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH] -#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H] -#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL] -#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH] -#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32 -#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L] -#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL] -#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH] -#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H] -#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL] -#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH] -#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32 -#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L] -#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL] -#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH] -#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H] -#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL] -#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH] -#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32 -#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L] -#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL] -#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH] -#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H] -#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL] -#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH] -#define RSCAN0RMID37 RSCAN0.RMID37.UINT32 -#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L] -#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL] -#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH] -#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H] -#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL] -#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH] -#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32 -#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L] -#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL] -#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH] -#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H] -#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL] -#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH] -#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32 -#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L] -#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL] -#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH] -#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H] -#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL] -#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH] -#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32 -#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L] -#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL] -#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH] -#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H] -#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL] -#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH] -#define RSCAN0RMID38 RSCAN0.RMID38.UINT32 -#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L] -#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL] -#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH] -#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H] -#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL] -#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH] -#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32 -#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L] -#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL] -#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH] -#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H] -#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL] -#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH] -#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32 -#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L] -#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL] -#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH] -#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H] -#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL] -#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH] -#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32 -#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L] -#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL] -#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH] -#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H] -#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL] -#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH] -#define RSCAN0RMID39 RSCAN0.RMID39.UINT32 -#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L] -#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL] -#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH] -#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H] -#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL] -#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH] -#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32 -#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L] -#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL] -#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH] -#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H] -#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL] -#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH] -#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32 -#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L] -#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL] -#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH] -#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H] -#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL] -#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH] -#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32 -#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L] -#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL] -#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH] -#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H] -#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL] -#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH] -#define RSCAN0RMID40 RSCAN0.RMID40.UINT32 -#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L] -#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL] -#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH] -#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H] -#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL] -#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH] -#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32 -#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L] -#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL] -#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH] -#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H] -#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL] -#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH] -#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32 -#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L] -#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL] -#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH] -#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H] -#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL] -#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH] -#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32 -#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L] -#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL] -#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH] -#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H] -#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL] -#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH] -#define RSCAN0RMID41 RSCAN0.RMID41.UINT32 -#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L] -#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL] -#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH] -#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H] -#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL] -#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH] -#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32 -#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L] -#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL] -#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH] -#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H] -#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL] -#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH] -#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32 -#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L] -#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL] -#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH] -#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H] -#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL] -#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH] -#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32 -#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L] -#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL] -#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH] -#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H] -#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL] -#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH] -#define RSCAN0RMID42 RSCAN0.RMID42.UINT32 -#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L] -#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL] -#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH] -#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H] -#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL] -#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH] -#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32 -#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L] -#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL] -#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH] -#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H] -#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL] -#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH] -#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32 -#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L] -#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL] -#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH] -#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H] -#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL] -#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH] -#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32 -#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L] -#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL] -#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH] -#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H] -#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL] -#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH] -#define RSCAN0RMID43 RSCAN0.RMID43.UINT32 -#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L] -#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL] -#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH] -#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H] -#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL] -#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH] -#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32 -#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L] -#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL] -#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH] -#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H] -#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL] -#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH] -#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32 -#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L] -#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL] -#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH] -#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H] -#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL] -#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH] -#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32 -#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L] -#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL] -#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH] -#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H] -#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL] -#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH] -#define RSCAN0RMID44 RSCAN0.RMID44.UINT32 -#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L] -#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL] -#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH] -#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H] -#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL] -#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH] -#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32 -#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L] -#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL] -#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH] -#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H] -#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL] -#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH] -#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32 -#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L] -#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL] -#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH] -#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H] -#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL] -#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH] -#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32 -#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L] -#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL] -#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH] -#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H] -#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL] -#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH] -#define RSCAN0RMID45 RSCAN0.RMID45.UINT32 -#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L] -#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL] -#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH] -#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H] -#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL] -#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH] -#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32 -#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L] -#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL] -#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH] -#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H] -#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL] -#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH] -#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32 -#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L] -#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL] -#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH] -#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H] -#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL] -#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH] -#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32 -#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L] -#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL] -#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH] -#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H] -#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL] -#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH] -#define RSCAN0RMID46 RSCAN0.RMID46.UINT32 -#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L] -#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL] -#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH] -#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H] -#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL] -#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH] -#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32 -#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L] -#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL] -#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH] -#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H] -#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL] -#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH] -#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32 -#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L] -#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL] -#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH] -#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H] -#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL] -#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH] -#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32 -#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L] -#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL] -#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH] -#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H] -#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL] -#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH] -#define RSCAN0RMID47 RSCAN0.RMID47.UINT32 -#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L] -#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL] -#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH] -#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H] -#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL] -#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH] -#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32 -#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L] -#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL] -#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH] -#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H] -#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL] -#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH] -#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32 -#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L] -#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL] -#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH] -#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H] -#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL] -#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH] -#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32 -#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L] -#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL] -#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH] -#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H] -#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL] -#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH] -#define RSCAN0RMID48 RSCAN0.RMID48.UINT32 -#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L] -#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL] -#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH] -#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H] -#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL] -#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH] -#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32 -#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L] -#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL] -#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH] -#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H] -#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL] -#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH] -#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32 -#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L] -#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL] -#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH] -#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H] -#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL] -#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH] -#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32 -#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L] -#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL] -#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH] -#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H] -#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL] -#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH] -#define RSCAN0RMID49 RSCAN0.RMID49.UINT32 -#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L] -#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL] -#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH] -#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H] -#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL] -#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH] -#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32 -#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L] -#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL] -#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH] -#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H] -#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL] -#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH] -#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32 -#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L] -#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL] -#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH] -#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H] -#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL] -#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH] -#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32 -#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L] -#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL] -#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH] -#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H] -#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL] -#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH] -#define RSCAN0RMID50 RSCAN0.RMID50.UINT32 -#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L] -#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL] -#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH] -#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H] -#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL] -#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH] -#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32 -#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L] -#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL] -#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH] -#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H] -#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL] -#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH] -#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32 -#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L] -#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL] -#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH] -#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H] -#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL] -#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH] -#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32 -#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L] -#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL] -#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH] -#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H] -#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL] -#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH] -#define RSCAN0RMID51 RSCAN0.RMID51.UINT32 -#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L] -#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL] -#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH] -#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H] -#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL] -#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH] -#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32 -#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L] -#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL] -#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH] -#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H] -#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL] -#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH] -#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32 -#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L] -#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL] -#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH] -#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H] -#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL] -#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH] -#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32 -#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L] -#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL] -#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH] -#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H] -#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL] -#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH] -#define RSCAN0RMID52 RSCAN0.RMID52.UINT32 -#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L] -#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL] -#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH] -#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H] -#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL] -#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH] -#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32 -#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L] -#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL] -#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH] -#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H] -#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL] -#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH] -#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32 -#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L] -#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL] -#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH] -#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H] -#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL] -#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH] -#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32 -#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L] -#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL] -#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH] -#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H] -#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL] -#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH] -#define RSCAN0RMID53 RSCAN0.RMID53.UINT32 -#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L] -#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL] -#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH] -#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H] -#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL] -#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH] -#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32 -#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L] -#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL] -#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH] -#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H] -#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL] -#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH] -#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32 -#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L] -#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL] -#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH] -#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H] -#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL] -#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH] -#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32 -#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L] -#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL] -#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH] -#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H] -#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL] -#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH] -#define RSCAN0RMID54 RSCAN0.RMID54.UINT32 -#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L] -#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL] -#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH] -#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H] -#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL] -#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH] -#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32 -#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L] -#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL] -#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH] -#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H] -#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL] -#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH] -#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32 -#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L] -#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL] -#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH] -#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H] -#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL] -#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH] -#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32 -#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L] -#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL] -#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH] -#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H] -#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL] -#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH] -#define RSCAN0RMID55 RSCAN0.RMID55.UINT32 -#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L] -#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL] -#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH] -#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H] -#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL] -#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH] -#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32 -#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L] -#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL] -#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH] -#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H] -#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL] -#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH] -#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32 -#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L] -#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL] -#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH] -#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H] -#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL] -#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH] -#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32 -#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L] -#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL] -#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH] -#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H] -#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL] -#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH] -#define RSCAN0RMID56 RSCAN0.RMID56.UINT32 -#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L] -#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL] -#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH] -#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H] -#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL] -#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH] -#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32 -#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L] -#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL] -#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH] -#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H] -#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL] -#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH] -#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32 -#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L] -#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL] -#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH] -#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H] -#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL] -#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH] -#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32 -#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L] -#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL] -#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH] -#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H] -#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL] -#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH] -#define RSCAN0RMID57 RSCAN0.RMID57.UINT32 -#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L] -#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL] -#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH] -#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H] -#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL] -#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH] -#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32 -#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L] -#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL] -#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH] -#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H] -#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL] -#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH] -#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32 -#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L] -#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL] -#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH] -#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H] -#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL] -#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH] -#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32 -#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L] -#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL] -#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH] -#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H] -#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL] -#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH] -#define RSCAN0RMID58 RSCAN0.RMID58.UINT32 -#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L] -#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL] -#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH] -#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H] -#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL] -#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH] -#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32 -#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L] -#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL] -#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH] -#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H] -#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL] -#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH] -#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32 -#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L] -#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL] -#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH] -#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H] -#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL] -#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH] -#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32 -#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L] -#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL] -#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH] -#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H] -#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL] -#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH] -#define RSCAN0RMID59 RSCAN0.RMID59.UINT32 -#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L] -#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL] -#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH] -#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H] -#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL] -#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH] -#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32 -#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L] -#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL] -#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH] -#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H] -#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL] -#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH] -#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32 -#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L] -#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL] -#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH] -#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H] -#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL] -#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH] -#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32 -#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L] -#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL] -#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH] -#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H] -#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL] -#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH] -#define RSCAN0RMID60 RSCAN0.RMID60.UINT32 -#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L] -#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL] -#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH] -#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H] -#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL] -#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH] -#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32 -#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L] -#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL] -#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH] -#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H] -#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL] -#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH] -#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32 -#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L] -#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL] -#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH] -#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H] -#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL] -#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH] -#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32 -#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L] -#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL] -#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH] -#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H] -#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL] -#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH] -#define RSCAN0RMID61 RSCAN0.RMID61.UINT32 -#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L] -#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL] -#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH] -#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H] -#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL] -#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH] -#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32 -#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L] -#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL] -#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH] -#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H] -#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL] -#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH] -#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32 -#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L] -#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL] -#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH] -#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H] -#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL] -#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH] -#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32 -#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L] -#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL] -#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH] -#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H] -#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL] -#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH] -#define RSCAN0RMID62 RSCAN0.RMID62.UINT32 -#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L] -#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL] -#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH] -#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H] -#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL] -#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH] -#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32 -#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L] -#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL] -#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH] -#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H] -#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL] -#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH] -#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32 -#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L] -#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL] -#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH] -#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H] -#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL] -#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH] -#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32 -#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L] -#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL] -#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH] -#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H] -#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL] -#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH] -#define RSCAN0RMID63 RSCAN0.RMID63.UINT32 -#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L] -#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL] -#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH] -#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H] -#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL] -#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH] -#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32 -#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L] -#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL] -#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH] -#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H] -#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL] -#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH] -#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32 -#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L] -#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL] -#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH] -#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H] -#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL] -#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH] -#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32 -#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L] -#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL] -#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH] -#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H] -#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL] -#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH] -#define RSCAN0RMID64 RSCAN0.RMID64.UINT32 -#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L] -#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL] -#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH] -#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H] -#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL] -#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH] -#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32 -#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L] -#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL] -#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH] -#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H] -#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL] -#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH] -#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32 -#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L] -#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL] -#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH] -#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H] -#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL] -#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH] -#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32 -#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L] -#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL] -#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH] -#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H] -#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL] -#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH] -#define RSCAN0RMID65 RSCAN0.RMID65.UINT32 -#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L] -#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL] -#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH] -#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H] -#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL] -#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH] -#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32 -#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L] -#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL] -#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH] -#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H] -#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL] -#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH] -#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32 -#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L] -#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL] -#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH] -#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H] -#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL] -#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH] -#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32 -#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L] -#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL] -#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH] -#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H] -#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL] -#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH] -#define RSCAN0RMID66 RSCAN0.RMID66.UINT32 -#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L] -#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL] -#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH] -#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H] -#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL] -#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH] -#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32 -#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L] -#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL] -#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH] -#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H] -#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL] -#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH] -#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32 -#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L] -#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL] -#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH] -#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H] -#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL] -#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH] -#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32 -#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L] -#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL] -#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH] -#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H] -#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL] -#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH] -#define RSCAN0RMID67 RSCAN0.RMID67.UINT32 -#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L] -#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL] -#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH] -#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H] -#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL] -#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH] -#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32 -#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L] -#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL] -#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH] -#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H] -#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL] -#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH] -#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32 -#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L] -#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL] -#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH] -#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H] -#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL] -#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH] -#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32 -#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L] -#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL] -#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH] -#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H] -#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL] -#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH] -#define RSCAN0RMID68 RSCAN0.RMID68.UINT32 -#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L] -#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL] -#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH] -#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H] -#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL] -#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH] -#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32 -#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L] -#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL] -#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH] -#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H] -#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL] -#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH] -#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32 -#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L] -#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL] -#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH] -#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H] -#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL] -#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH] -#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32 -#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L] -#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL] -#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH] -#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H] -#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL] -#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH] -#define RSCAN0RMID69 RSCAN0.RMID69.UINT32 -#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L] -#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL] -#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH] -#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H] -#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL] -#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH] -#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32 -#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L] -#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL] -#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH] -#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H] -#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL] -#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH] -#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32 -#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L] -#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL] -#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH] -#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H] -#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL] -#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH] -#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32 -#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L] -#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL] -#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH] -#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H] -#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL] -#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH] -#define RSCAN0RMID70 RSCAN0.RMID70.UINT32 -#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L] -#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL] -#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH] -#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H] -#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL] -#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH] -#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32 -#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L] -#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL] -#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH] -#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H] -#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL] -#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH] -#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32 -#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L] -#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL] -#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH] -#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H] -#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL] -#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH] -#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32 -#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L] -#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL] -#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH] -#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H] -#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL] -#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH] -#define RSCAN0RMID71 RSCAN0.RMID71.UINT32 -#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L] -#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL] -#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH] -#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H] -#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL] -#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH] -#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32 -#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L] -#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL] -#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH] -#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H] -#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL] -#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH] -#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32 -#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L] -#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL] -#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH] -#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H] -#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL] -#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH] -#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32 -#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L] -#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL] -#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH] -#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H] -#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL] -#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH] -#define RSCAN0RMID72 RSCAN0.RMID72.UINT32 -#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L] -#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL] -#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH] -#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H] -#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL] -#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH] -#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32 -#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L] -#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL] -#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH] -#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H] -#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL] -#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH] -#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32 -#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L] -#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL] -#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH] -#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H] -#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL] -#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH] -#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32 -#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L] -#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL] -#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH] -#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H] -#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL] -#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH] -#define RSCAN0RMID73 RSCAN0.RMID73.UINT32 -#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L] -#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL] -#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH] -#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H] -#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL] -#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH] -#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32 -#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L] -#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL] -#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH] -#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H] -#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL] -#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH] -#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32 -#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L] -#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL] -#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH] -#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H] -#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL] -#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH] -#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32 -#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L] -#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL] -#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH] -#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H] -#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL] -#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH] -#define RSCAN0RMID74 RSCAN0.RMID74.UINT32 -#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L] -#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL] -#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH] -#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H] -#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL] -#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH] -#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32 -#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L] -#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL] -#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH] -#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H] -#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL] -#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH] -#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32 -#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L] -#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL] -#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH] -#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H] -#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL] -#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH] -#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32 -#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L] -#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL] -#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH] -#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H] -#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL] -#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH] -#define RSCAN0RMID75 RSCAN0.RMID75.UINT32 -#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L] -#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL] -#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH] -#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H] -#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL] -#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH] -#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32 -#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L] -#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL] -#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH] -#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H] -#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL] -#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH] -#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32 -#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L] -#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL] -#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH] -#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H] -#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL] -#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH] -#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32 -#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L] -#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL] -#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH] -#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H] -#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL] -#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH] -#define RSCAN0RMID76 RSCAN0.RMID76.UINT32 -#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L] -#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL] -#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH] -#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H] -#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL] -#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH] -#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32 -#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L] -#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL] -#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH] -#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H] -#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL] -#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH] -#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32 -#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L] -#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL] -#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH] -#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H] -#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL] -#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH] -#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32 -#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L] -#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL] -#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH] -#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H] -#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL] -#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH] -#define RSCAN0RMID77 RSCAN0.RMID77.UINT32 -#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L] -#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL] -#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH] -#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H] -#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL] -#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH] -#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32 -#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L] -#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL] -#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH] -#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H] -#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL] -#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH] -#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32 -#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L] -#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL] -#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH] -#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H] -#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL] -#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH] -#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32 -#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L] -#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL] -#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH] -#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H] -#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL] -#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH] -#define RSCAN0RMID78 RSCAN0.RMID78.UINT32 -#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L] -#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL] -#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH] -#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H] -#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL] -#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH] -#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32 -#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L] -#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL] -#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH] -#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H] -#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL] -#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH] -#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32 -#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L] -#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL] -#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH] -#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H] -#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL] -#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH] -#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32 -#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L] -#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL] -#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH] -#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H] -#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL] -#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH] -#define RSCAN0RMID79 RSCAN0.RMID79.UINT32 -#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L] -#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL] -#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH] -#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H] -#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL] -#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH] -#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32 -#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L] -#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL] -#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH] -#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H] -#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL] -#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH] -#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32 -#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L] -#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL] -#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH] -#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H] -#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL] -#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH] -#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32 -#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L] -#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL] -#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH] -#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H] -#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL] -#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH] -#define RSCAN0RFID0 RSCAN0.RFID0.UINT32 -#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L] -#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL] -#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH] -#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H] -#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL] -#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH] -#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32 -#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L] -#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL] -#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH] -#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H] -#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL] -#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH] -#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32 -#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L] -#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL] -#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH] -#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H] -#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL] -#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH] -#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32 -#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L] -#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL] -#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH] -#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H] -#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL] -#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH] -#define RSCAN0RFID1 RSCAN0.RFID1.UINT32 -#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L] -#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL] -#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH] -#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H] -#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL] -#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH] -#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32 -#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L] -#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL] -#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH] -#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H] -#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL] -#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH] -#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32 -#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L] -#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL] -#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH] -#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H] -#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL] -#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH] -#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32 -#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L] -#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL] -#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH] -#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H] -#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL] -#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH] -#define RSCAN0RFID2 RSCAN0.RFID2.UINT32 -#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L] -#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL] -#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH] -#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H] -#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL] -#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH] -#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32 -#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L] -#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL] -#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH] -#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H] -#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL] -#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH] -#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32 -#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L] -#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL] -#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH] -#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H] -#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL] -#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH] -#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32 -#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L] -#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL] -#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH] -#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H] -#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL] -#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH] -#define RSCAN0RFID3 RSCAN0.RFID3.UINT32 -#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L] -#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL] -#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH] -#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H] -#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL] -#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH] -#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32 -#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L] -#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL] -#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH] -#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H] -#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL] -#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH] -#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32 -#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L] -#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL] -#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH] -#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H] -#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL] -#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH] -#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32 -#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L] -#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL] -#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH] -#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H] -#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL] -#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH] -#define RSCAN0RFID4 RSCAN0.RFID4.UINT32 -#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L] -#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL] -#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH] -#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H] -#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL] -#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH] -#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32 -#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L] -#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL] -#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH] -#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H] -#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL] -#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH] -#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32 -#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L] -#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL] -#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH] -#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H] -#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL] -#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH] -#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32 -#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L] -#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL] -#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH] -#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H] -#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL] -#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH] -#define RSCAN0RFID5 RSCAN0.RFID5.UINT32 -#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L] -#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL] -#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH] -#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H] -#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL] -#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH] -#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32 -#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L] -#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL] -#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH] -#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H] -#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL] -#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH] -#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32 -#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L] -#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL] -#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH] -#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H] -#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL] -#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH] -#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32 -#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L] -#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL] -#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH] -#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H] -#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL] -#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH] -#define RSCAN0RFID6 RSCAN0.RFID6.UINT32 -#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L] -#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL] -#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH] -#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H] -#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL] -#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH] -#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32 -#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L] -#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL] -#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH] -#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H] -#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL] -#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH] -#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32 -#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L] -#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL] -#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH] -#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H] -#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL] -#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH] -#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32 -#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L] -#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL] -#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH] -#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H] -#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL] -#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH] -#define RSCAN0RFID7 RSCAN0.RFID7.UINT32 -#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L] -#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL] -#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH] -#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H] -#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL] -#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH] -#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32 -#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L] -#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL] -#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH] -#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H] -#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL] -#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH] -#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32 -#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L] -#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL] -#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH] -#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H] -#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL] -#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH] -#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32 -#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L] -#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL] -#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH] -#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H] -#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL] -#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH] -#define RSCAN0CFID0 RSCAN0.CFID0.UINT32 -#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L] -#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL] -#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH] -#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H] -#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL] -#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH] -#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32 -#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L] -#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL] -#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH] -#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H] -#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL] -#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH] -#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32 -#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L] -#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL] -#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH] -#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H] -#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL] -#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH] -#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32 -#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L] -#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL] -#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH] -#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H] -#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL] -#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH] -#define RSCAN0CFID1 RSCAN0.CFID1.UINT32 -#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L] -#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL] -#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH] -#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H] -#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL] -#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH] -#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32 -#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L] -#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL] -#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH] -#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H] -#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL] -#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH] -#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32 -#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L] -#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL] -#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH] -#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H] -#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL] -#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH] -#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32 -#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L] -#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL] -#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH] -#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H] -#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL] -#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH] -#define RSCAN0CFID2 RSCAN0.CFID2.UINT32 -#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L] -#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL] -#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH] -#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H] -#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL] -#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH] -#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32 -#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L] -#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL] -#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH] -#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H] -#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL] -#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH] -#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32 -#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L] -#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL] -#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH] -#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H] -#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL] -#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH] -#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32 -#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L] -#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL] -#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH] -#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H] -#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL] -#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH] -#define RSCAN0CFID3 RSCAN0.CFID3.UINT32 -#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L] -#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL] -#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH] -#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H] -#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL] -#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH] -#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32 -#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L] -#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL] -#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH] -#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H] -#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL] -#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH] -#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32 -#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L] -#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL] -#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH] -#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H] -#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL] -#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH] -#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32 -#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L] -#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL] -#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH] -#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H] -#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL] -#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH] -#define RSCAN0CFID4 RSCAN0.CFID4.UINT32 -#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L] -#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL] -#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH] -#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H] -#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL] -#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH] -#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32 -#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L] -#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL] -#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH] -#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H] -#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL] -#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH] -#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32 -#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L] -#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL] -#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH] -#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H] -#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL] -#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH] -#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32 -#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L] -#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL] -#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH] -#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H] -#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL] -#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH] -#define RSCAN0CFID5 RSCAN0.CFID5.UINT32 -#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L] -#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL] -#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH] -#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H] -#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL] -#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH] -#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32 -#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L] -#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL] -#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH] -#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H] -#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL] -#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH] -#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32 -#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L] -#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL] -#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH] -#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H] -#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL] -#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH] -#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32 -#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L] -#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL] -#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH] -#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H] -#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL] -#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH] -#define RSCAN0CFID6 RSCAN0.CFID6.UINT32 -#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L] -#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL] -#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH] -#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H] -#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL] -#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH] -#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32 -#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L] -#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL] -#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH] -#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H] -#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL] -#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH] -#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32 -#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L] -#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL] -#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH] -#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H] -#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL] -#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH] -#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32 -#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L] -#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL] -#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH] -#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H] -#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL] -#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH] -#define RSCAN0CFID7 RSCAN0.CFID7.UINT32 -#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L] -#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL] -#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH] -#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H] -#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL] -#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH] -#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32 -#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L] -#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL] -#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH] -#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H] -#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL] -#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH] -#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32 -#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L] -#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL] -#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH] -#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H] -#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL] -#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH] -#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32 -#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L] -#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL] -#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH] -#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H] -#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL] -#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH] -#define RSCAN0CFID8 RSCAN0.CFID8.UINT32 -#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L] -#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL] -#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH] -#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H] -#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL] -#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH] -#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32 -#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L] -#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL] -#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH] -#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H] -#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL] -#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH] -#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32 -#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L] -#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL] -#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH] -#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H] -#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL] -#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH] -#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32 -#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L] -#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL] -#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH] -#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H] -#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL] -#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH] -#define RSCAN0CFID9 RSCAN0.CFID9.UINT32 -#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L] -#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL] -#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH] -#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H] -#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL] -#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH] -#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32 -#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L] -#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL] -#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH] -#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H] -#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL] -#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH] -#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32 -#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L] -#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL] -#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH] -#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H] -#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL] -#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH] -#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32 -#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L] -#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL] -#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH] -#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H] -#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL] -#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH] -#define RSCAN0CFID10 RSCAN0.CFID10.UINT32 -#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L] -#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL] -#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH] -#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H] -#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL] -#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH] -#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32 -#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L] -#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL] -#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH] -#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H] -#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL] -#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH] -#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32 -#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L] -#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL] -#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH] -#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H] -#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL] -#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH] -#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32 -#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L] -#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL] -#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH] -#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H] -#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL] -#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH] -#define RSCAN0CFID11 RSCAN0.CFID11.UINT32 -#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L] -#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL] -#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH] -#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H] -#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL] -#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH] -#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32 -#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L] -#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL] -#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH] -#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H] -#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL] -#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH] -#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32 -#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L] -#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL] -#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH] -#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H] -#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL] -#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH] -#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32 -#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L] -#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL] -#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH] -#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H] -#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL] -#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH] -#define RSCAN0CFID12 RSCAN0.CFID12.UINT32 -#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L] -#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL] -#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH] -#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H] -#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL] -#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH] -#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32 -#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L] -#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL] -#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH] -#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H] -#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL] -#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH] -#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32 -#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L] -#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL] -#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH] -#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H] -#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL] -#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH] -#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32 -#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L] -#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL] -#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH] -#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H] -#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL] -#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH] -#define RSCAN0CFID13 RSCAN0.CFID13.UINT32 -#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L] -#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL] -#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH] -#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H] -#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL] -#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH] -#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32 -#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L] -#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL] -#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH] -#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H] -#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL] -#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH] -#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32 -#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L] -#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL] -#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH] -#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H] -#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL] -#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH] -#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32 -#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L] -#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL] -#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH] -#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H] -#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL] -#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH] -#define RSCAN0CFID14 RSCAN0.CFID14.UINT32 -#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L] -#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL] -#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH] -#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H] -#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL] -#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH] -#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32 -#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L] -#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL] -#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH] -#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H] -#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL] -#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH] -#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32 -#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L] -#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL] -#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH] -#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H] -#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL] -#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH] -#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32 -#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L] -#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL] -#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH] -#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H] -#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL] -#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH] -#define RSCAN0TMID0 RSCAN0.TMID0.UINT32 -#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L] -#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL] -#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH] -#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H] -#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL] -#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH] -#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32 -#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L] -#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL] -#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH] -#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H] -#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL] -#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH] -#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32 -#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L] -#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL] -#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH] -#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H] -#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL] -#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH] -#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32 -#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L] -#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL] -#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH] -#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H] -#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL] -#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH] -#define RSCAN0TMID1 RSCAN0.TMID1.UINT32 -#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L] -#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL] -#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH] -#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H] -#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL] -#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH] -#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32 -#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L] -#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL] -#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH] -#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H] -#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL] -#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH] -#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32 -#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L] -#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL] -#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH] -#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H] -#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL] -#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH] -#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32 -#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L] -#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL] -#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH] -#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H] -#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL] -#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH] -#define RSCAN0TMID2 RSCAN0.TMID2.UINT32 -#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L] -#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL] -#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH] -#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H] -#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL] -#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH] -#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32 -#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L] -#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL] -#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH] -#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H] -#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL] -#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH] -#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32 -#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L] -#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL] -#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH] -#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H] -#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL] -#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH] -#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32 -#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L] -#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL] -#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH] -#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H] -#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL] -#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH] -#define RSCAN0TMID3 RSCAN0.TMID3.UINT32 -#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L] -#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL] -#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH] -#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H] -#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL] -#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH] -#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32 -#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L] -#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL] -#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH] -#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H] -#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL] -#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH] -#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32 -#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L] -#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL] -#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH] -#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H] -#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL] -#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH] -#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32 -#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L] -#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL] -#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH] -#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H] -#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL] -#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH] -#define RSCAN0TMID4 RSCAN0.TMID4.UINT32 -#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L] -#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL] -#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH] -#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H] -#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL] -#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH] -#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32 -#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L] -#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL] -#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH] -#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H] -#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL] -#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH] -#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32 -#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L] -#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL] -#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH] -#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H] -#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL] -#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH] -#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32 -#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L] -#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL] -#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH] -#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H] -#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL] -#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH] -#define RSCAN0TMID5 RSCAN0.TMID5.UINT32 -#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L] -#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL] -#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH] -#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H] -#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL] -#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH] -#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32 -#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L] -#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL] -#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH] -#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H] -#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL] -#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH] -#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32 -#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L] -#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL] -#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH] -#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H] -#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL] -#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH] -#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32 -#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L] -#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL] -#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH] -#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H] -#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL] -#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH] -#define RSCAN0TMID6 RSCAN0.TMID6.UINT32 -#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L] -#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL] -#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH] -#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H] -#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL] -#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH] -#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32 -#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L] -#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL] -#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH] -#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H] -#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL] -#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH] -#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32 -#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L] -#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL] -#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH] -#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H] -#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL] -#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH] -#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32 -#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L] -#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL] -#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH] -#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H] -#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL] -#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH] -#define RSCAN0TMID7 RSCAN0.TMID7.UINT32 -#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L] -#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL] -#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH] -#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H] -#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL] -#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH] -#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32 -#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L] -#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL] -#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH] -#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H] -#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL] -#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH] -#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32 -#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L] -#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL] -#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH] -#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H] -#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL] -#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH] -#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32 -#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L] -#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL] -#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH] -#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H] -#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL] -#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH] -#define RSCAN0TMID8 RSCAN0.TMID8.UINT32 -#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L] -#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL] -#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH] -#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H] -#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL] -#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH] -#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32 -#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L] -#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL] -#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH] -#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H] -#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL] -#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH] -#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32 -#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L] -#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL] -#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH] -#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H] -#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL] -#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH] -#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32 -#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L] -#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL] -#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH] -#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H] -#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL] -#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH] -#define RSCAN0TMID9 RSCAN0.TMID9.UINT32 -#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L] -#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL] -#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH] -#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H] -#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL] -#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH] -#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32 -#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L] -#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL] -#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH] -#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H] -#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL] -#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH] -#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32 -#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L] -#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL] -#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH] -#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H] -#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL] -#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH] -#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32 -#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L] -#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL] -#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH] -#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H] -#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL] -#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH] -#define RSCAN0TMID10 RSCAN0.TMID10.UINT32 -#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L] -#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL] -#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH] -#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H] -#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL] -#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH] -#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32 -#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L] -#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL] -#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH] -#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H] -#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL] -#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH] -#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32 -#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L] -#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL] -#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH] -#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H] -#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL] -#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH] -#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32 -#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L] -#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL] -#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH] -#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H] -#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL] -#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH] -#define RSCAN0TMID11 RSCAN0.TMID11.UINT32 -#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L] -#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL] -#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH] -#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H] -#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL] -#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH] -#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32 -#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L] -#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL] -#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH] -#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H] -#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL] -#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH] -#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32 -#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L] -#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL] -#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH] -#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H] -#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL] -#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH] -#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32 -#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L] -#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL] -#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH] -#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H] -#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL] -#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH] -#define RSCAN0TMID12 RSCAN0.TMID12.UINT32 -#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L] -#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL] -#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH] -#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H] -#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL] -#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH] -#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32 -#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L] -#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL] -#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH] -#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H] -#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL] -#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH] -#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32 -#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L] -#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL] -#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH] -#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H] -#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL] -#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH] -#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32 -#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L] -#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL] -#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH] -#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H] -#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL] -#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH] -#define RSCAN0TMID13 RSCAN0.TMID13.UINT32 -#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L] -#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL] -#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH] -#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H] -#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL] -#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH] -#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32 -#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L] -#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL] -#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH] -#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H] -#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL] -#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH] -#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32 -#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L] -#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL] -#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH] -#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H] -#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL] -#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH] -#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32 -#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L] -#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL] -#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH] -#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H] -#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL] -#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH] -#define RSCAN0TMID14 RSCAN0.TMID14.UINT32 -#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L] -#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL] -#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH] -#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H] -#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL] -#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH] -#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32 -#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L] -#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL] -#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH] -#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H] -#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL] -#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH] -#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32 -#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L] -#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL] -#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH] -#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H] -#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL] -#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH] -#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32 -#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L] -#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL] -#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH] -#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H] -#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL] -#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH] -#define RSCAN0TMID15 RSCAN0.TMID15.UINT32 -#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L] -#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL] -#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH] -#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H] -#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL] -#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH] -#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32 -#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L] -#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL] -#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH] -#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H] -#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL] -#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH] -#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32 -#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L] -#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL] -#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH] -#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H] -#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL] -#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH] -#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32 -#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L] -#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL] -#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH] -#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H] -#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL] -#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH] -#define RSCAN0TMID16 RSCAN0.TMID16.UINT32 -#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L] -#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL] -#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH] -#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H] -#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL] -#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH] -#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32 -#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L] -#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL] -#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH] -#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H] -#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL] -#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH] -#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32 -#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L] -#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL] -#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH] -#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H] -#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL] -#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH] -#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32 -#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L] -#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL] -#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH] -#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H] -#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL] -#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH] -#define RSCAN0TMID17 RSCAN0.TMID17.UINT32 -#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L] -#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL] -#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH] -#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H] -#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL] -#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH] -#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32 -#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L] -#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL] -#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH] -#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H] -#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL] -#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH] -#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32 -#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L] -#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL] -#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH] -#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H] -#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL] -#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH] -#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32 -#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L] -#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL] -#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH] -#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H] -#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL] -#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH] -#define RSCAN0TMID18 RSCAN0.TMID18.UINT32 -#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L] -#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL] -#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH] -#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H] -#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL] -#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH] -#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32 -#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L] -#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL] -#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH] -#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H] -#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL] -#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH] -#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32 -#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L] -#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL] -#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH] -#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H] -#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL] -#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH] -#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32 -#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L] -#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL] -#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH] -#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H] -#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL] -#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH] -#define RSCAN0TMID19 RSCAN0.TMID19.UINT32 -#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L] -#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL] -#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH] -#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H] -#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL] -#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH] -#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32 -#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L] -#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL] -#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH] -#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H] -#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL] -#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH] -#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32 -#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L] -#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL] -#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH] -#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H] -#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL] -#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH] -#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32 -#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L] -#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL] -#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH] -#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H] -#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL] -#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH] -#define RSCAN0TMID20 RSCAN0.TMID20.UINT32 -#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L] -#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL] -#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH] -#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H] -#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL] -#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH] -#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32 -#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L] -#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL] -#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH] -#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H] -#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL] -#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH] -#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32 -#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L] -#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL] -#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH] -#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H] -#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL] -#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH] -#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32 -#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L] -#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL] -#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH] -#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H] -#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL] -#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH] -#define RSCAN0TMID21 RSCAN0.TMID21.UINT32 -#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L] -#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL] -#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH] -#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H] -#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL] -#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH] -#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32 -#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L] -#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL] -#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH] -#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H] -#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL] -#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH] -#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32 -#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L] -#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL] -#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH] -#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H] -#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL] -#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH] -#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32 -#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L] -#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL] -#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH] -#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H] -#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL] -#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH] -#define RSCAN0TMID22 RSCAN0.TMID22.UINT32 -#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L] -#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL] -#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH] -#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H] -#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL] -#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH] -#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32 -#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L] -#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL] -#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH] -#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H] -#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL] -#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH] -#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32 -#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L] -#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL] -#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH] -#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H] -#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL] -#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH] -#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32 -#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L] -#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL] -#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH] -#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H] -#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL] -#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH] -#define RSCAN0TMID23 RSCAN0.TMID23.UINT32 -#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L] -#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL] -#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH] -#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H] -#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL] -#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH] -#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32 -#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L] -#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL] -#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH] -#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H] -#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL] -#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH] -#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32 -#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L] -#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL] -#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH] -#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H] -#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL] -#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH] -#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32 -#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L] -#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL] -#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH] -#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H] -#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL] -#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH] -#define RSCAN0TMID24 RSCAN0.TMID24.UINT32 -#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L] -#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL] -#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH] -#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H] -#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL] -#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH] -#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32 -#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L] -#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL] -#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH] -#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H] -#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL] -#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH] -#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32 -#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L] -#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL] -#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH] -#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H] -#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL] -#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH] -#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32 -#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L] -#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL] -#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH] -#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H] -#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL] -#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH] -#define RSCAN0TMID25 RSCAN0.TMID25.UINT32 -#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L] -#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL] -#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH] -#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H] -#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL] -#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH] -#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32 -#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L] -#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL] -#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH] -#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H] -#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL] -#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH] -#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32 -#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L] -#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL] -#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH] -#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H] -#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL] -#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH] -#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32 -#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L] -#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL] -#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH] -#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H] -#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL] -#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH] -#define RSCAN0TMID26 RSCAN0.TMID26.UINT32 -#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L] -#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL] -#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH] -#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H] -#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL] -#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH] -#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32 -#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L] -#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL] -#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH] -#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H] -#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL] -#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH] -#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32 -#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L] -#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL] -#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH] -#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H] -#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL] -#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH] -#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32 -#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L] -#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL] -#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH] -#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H] -#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL] -#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH] -#define RSCAN0TMID27 RSCAN0.TMID27.UINT32 -#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L] -#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL] -#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH] -#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H] -#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL] -#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH] -#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32 -#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L] -#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL] -#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH] -#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H] -#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL] -#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH] -#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32 -#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L] -#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL] -#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH] -#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H] -#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL] -#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH] -#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32 -#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L] -#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL] -#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH] -#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H] -#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL] -#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH] -#define RSCAN0TMID28 RSCAN0.TMID28.UINT32 -#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L] -#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL] -#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH] -#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H] -#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL] -#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH] -#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32 -#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L] -#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL] -#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH] -#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H] -#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL] -#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH] -#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32 -#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L] -#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL] -#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH] -#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H] -#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL] -#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH] -#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32 -#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L] -#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL] -#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH] -#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H] -#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL] -#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH] -#define RSCAN0TMID29 RSCAN0.TMID29.UINT32 -#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L] -#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL] -#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH] -#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H] -#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL] -#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH] -#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32 -#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L] -#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL] -#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH] -#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H] -#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL] -#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH] -#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32 -#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L] -#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL] -#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH] -#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H] -#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL] -#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH] -#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32 -#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L] -#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL] -#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH] -#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H] -#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL] -#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH] -#define RSCAN0TMID30 RSCAN0.TMID30.UINT32 -#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L] -#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL] -#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH] -#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H] -#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL] -#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH] -#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32 -#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L] -#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL] -#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH] -#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H] -#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL] -#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH] -#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32 -#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L] -#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL] -#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH] -#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H] -#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL] -#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH] -#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32 -#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L] -#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL] -#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH] -#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H] -#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL] -#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH] -#define RSCAN0TMID31 RSCAN0.TMID31.UINT32 -#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L] -#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL] -#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH] -#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H] -#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL] -#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH] -#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32 -#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L] -#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL] -#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH] -#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H] -#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL] -#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH] -#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32 -#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L] -#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL] -#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH] -#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H] -#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL] -#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH] -#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32 -#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L] -#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL] -#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH] -#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H] -#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL] -#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH] -#define RSCAN0TMID32 RSCAN0.TMID32.UINT32 -#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L] -#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL] -#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH] -#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H] -#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL] -#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH] -#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32 -#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L] -#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL] -#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH] -#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H] -#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL] -#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH] -#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32 -#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L] -#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL] -#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH] -#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H] -#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL] -#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH] -#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32 -#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L] -#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL] -#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH] -#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H] -#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL] -#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH] -#define RSCAN0TMID33 RSCAN0.TMID33.UINT32 -#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L] -#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL] -#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH] -#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H] -#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL] -#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH] -#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32 -#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L] -#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL] -#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH] -#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H] -#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL] -#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH] -#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32 -#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L] -#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL] -#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH] -#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H] -#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL] -#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH] -#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32 -#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L] -#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL] -#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH] -#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H] -#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL] -#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH] -#define RSCAN0TMID34 RSCAN0.TMID34.UINT32 -#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L] -#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL] -#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH] -#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H] -#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL] -#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH] -#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32 -#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L] -#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL] -#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH] -#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H] -#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL] -#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH] -#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32 -#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L] -#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL] -#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH] -#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H] -#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL] -#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH] -#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32 -#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L] -#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL] -#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH] -#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H] -#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL] -#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH] -#define RSCAN0TMID35 RSCAN0.TMID35.UINT32 -#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L] -#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL] -#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH] -#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H] -#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL] -#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH] -#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32 -#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L] -#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL] -#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH] -#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H] -#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL] -#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH] -#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32 -#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L] -#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL] -#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH] -#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H] -#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL] -#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH] -#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32 -#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L] -#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL] -#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH] -#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H] -#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL] -#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH] -#define RSCAN0TMID36 RSCAN0.TMID36.UINT32 -#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L] -#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL] -#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH] -#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H] -#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL] -#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH] -#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32 -#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L] -#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL] -#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH] -#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H] -#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL] -#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH] -#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32 -#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L] -#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL] -#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH] -#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H] -#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL] -#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH] -#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32 -#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L] -#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL] -#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH] -#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H] -#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL] -#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH] -#define RSCAN0TMID37 RSCAN0.TMID37.UINT32 -#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L] -#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL] -#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH] -#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H] -#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL] -#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH] -#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32 -#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L] -#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL] -#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH] -#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H] -#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL] -#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH] -#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32 -#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L] -#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL] -#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH] -#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H] -#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL] -#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH] -#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32 -#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L] -#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL] -#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH] -#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H] -#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL] -#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH] -#define RSCAN0TMID38 RSCAN0.TMID38.UINT32 -#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L] -#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL] -#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH] -#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H] -#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL] -#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH] -#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32 -#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L] -#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL] -#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH] -#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H] -#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL] -#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH] -#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32 -#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L] -#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL] -#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH] -#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H] -#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL] -#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH] -#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32 -#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L] -#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL] -#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH] -#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H] -#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL] -#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH] -#define RSCAN0TMID39 RSCAN0.TMID39.UINT32 -#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L] -#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL] -#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH] -#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H] -#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL] -#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH] -#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32 -#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L] -#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL] -#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH] -#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H] -#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL] -#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH] -#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32 -#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L] -#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL] -#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH] -#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H] -#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL] -#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH] -#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32 -#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L] -#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL] -#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH] -#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H] -#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL] -#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH] -#define RSCAN0TMID40 RSCAN0.TMID40.UINT32 -#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L] -#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL] -#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH] -#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H] -#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL] -#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH] -#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32 -#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L] -#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL] -#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH] -#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H] -#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL] -#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH] -#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32 -#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L] -#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL] -#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH] -#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H] -#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL] -#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH] -#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32 -#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L] -#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL] -#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH] -#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H] -#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL] -#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH] -#define RSCAN0TMID41 RSCAN0.TMID41.UINT32 -#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L] -#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL] -#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH] -#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H] -#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL] -#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH] -#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32 -#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L] -#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL] -#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH] -#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H] -#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL] -#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH] -#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32 -#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L] -#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL] -#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH] -#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H] -#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL] -#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH] -#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32 -#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L] -#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL] -#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH] -#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H] -#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL] -#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH] -#define RSCAN0TMID42 RSCAN0.TMID42.UINT32 -#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L] -#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL] -#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH] -#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H] -#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL] -#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH] -#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32 -#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L] -#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL] -#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH] -#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H] -#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL] -#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH] -#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32 -#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L] -#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL] -#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH] -#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H] -#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL] -#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH] -#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32 -#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L] -#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL] -#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH] -#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H] -#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL] -#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH] -#define RSCAN0TMID43 RSCAN0.TMID43.UINT32 -#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L] -#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL] -#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH] -#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H] -#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL] -#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH] -#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32 -#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L] -#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL] -#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH] -#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H] -#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL] -#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH] -#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32 -#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L] -#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL] -#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH] -#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H] -#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL] -#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH] -#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32 -#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L] -#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL] -#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH] -#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H] -#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL] -#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH] -#define RSCAN0TMID44 RSCAN0.TMID44.UINT32 -#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L] -#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL] -#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH] -#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H] -#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL] -#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH] -#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32 -#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L] -#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL] -#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH] -#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H] -#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL] -#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH] -#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32 -#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L] -#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL] -#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH] -#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H] -#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL] -#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH] -#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32 -#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L] -#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL] -#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH] -#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H] -#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL] -#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH] -#define RSCAN0TMID45 RSCAN0.TMID45.UINT32 -#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L] -#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL] -#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH] -#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H] -#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL] -#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH] -#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32 -#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L] -#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL] -#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH] -#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H] -#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL] -#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH] -#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32 -#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L] -#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL] -#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH] -#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H] -#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL] -#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH] -#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32 -#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L] -#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL] -#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH] -#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H] -#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL] -#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH] -#define RSCAN0TMID46 RSCAN0.TMID46.UINT32 -#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L] -#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL] -#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH] -#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H] -#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL] -#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH] -#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32 -#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L] -#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL] -#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH] -#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H] -#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL] -#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH] -#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32 -#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L] -#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL] -#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH] -#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H] -#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL] -#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH] -#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32 -#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L] -#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL] -#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH] -#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H] -#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL] -#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH] -#define RSCAN0TMID47 RSCAN0.TMID47.UINT32 -#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L] -#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL] -#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH] -#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H] -#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL] -#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH] -#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32 -#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L] -#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL] -#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH] -#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H] -#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL] -#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH] -#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32 -#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L] -#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL] -#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH] -#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H] -#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL] -#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH] -#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32 -#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L] -#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL] -#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH] -#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H] -#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL] -#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH] -#define RSCAN0TMID48 RSCAN0.TMID48.UINT32 -#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L] -#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL] -#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH] -#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H] -#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL] -#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH] -#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32 -#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L] -#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL] -#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH] -#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H] -#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL] -#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH] -#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32 -#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L] -#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL] -#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH] -#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H] -#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL] -#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH] -#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32 -#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L] -#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL] -#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH] -#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H] -#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL] -#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH] -#define RSCAN0TMID49 RSCAN0.TMID49.UINT32 -#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L] -#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL] -#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH] -#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H] -#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL] -#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH] -#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32 -#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L] -#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL] -#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH] -#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H] -#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL] -#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH] -#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32 -#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L] -#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL] -#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH] -#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H] -#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL] -#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH] -#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32 -#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L] -#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL] -#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH] -#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H] -#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL] -#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH] -#define RSCAN0TMID50 RSCAN0.TMID50.UINT32 -#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L] -#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL] -#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH] -#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H] -#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL] -#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH] -#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32 -#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L] -#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL] -#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH] -#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H] -#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL] -#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH] -#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32 -#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L] -#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL] -#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH] -#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H] -#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL] -#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH] -#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32 -#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L] -#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL] -#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH] -#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H] -#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL] -#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH] -#define RSCAN0TMID51 RSCAN0.TMID51.UINT32 -#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L] -#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL] -#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH] -#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H] -#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL] -#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH] -#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32 -#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L] -#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL] -#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH] -#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H] -#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL] -#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH] -#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32 -#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L] -#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL] -#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH] -#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H] -#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL] -#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH] -#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32 -#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L] -#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL] -#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH] -#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H] -#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL] -#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH] -#define RSCAN0TMID52 RSCAN0.TMID52.UINT32 -#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L] -#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL] -#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH] -#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H] -#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL] -#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH] -#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32 -#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L] -#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL] -#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH] -#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H] -#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL] -#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH] -#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32 -#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L] -#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL] -#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH] -#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H] -#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL] -#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH] -#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32 -#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L] -#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL] -#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH] -#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H] -#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL] -#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH] -#define RSCAN0TMID53 RSCAN0.TMID53.UINT32 -#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L] -#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL] -#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH] -#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H] -#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL] -#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH] -#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32 -#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L] -#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL] -#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH] -#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H] -#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL] -#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH] -#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32 -#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L] -#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL] -#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH] -#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H] -#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL] -#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH] -#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32 -#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L] -#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL] -#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH] -#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H] -#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL] -#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH] -#define RSCAN0TMID54 RSCAN0.TMID54.UINT32 -#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L] -#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL] -#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH] -#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H] -#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL] -#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH] -#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32 -#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L] -#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL] -#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH] -#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H] -#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL] -#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH] -#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32 -#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L] -#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL] -#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH] -#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H] -#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL] -#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH] -#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32 -#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L] -#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL] -#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH] -#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H] -#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL] -#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH] -#define RSCAN0TMID55 RSCAN0.TMID55.UINT32 -#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L] -#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL] -#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH] -#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H] -#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL] -#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH] -#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32 -#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L] -#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL] -#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH] -#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H] -#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL] -#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH] -#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32 -#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L] -#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL] -#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH] -#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H] -#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL] -#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH] -#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32 -#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L] -#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL] -#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH] -#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H] -#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL] -#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH] -#define RSCAN0TMID56 RSCAN0.TMID56.UINT32 -#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L] -#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL] -#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH] -#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H] -#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL] -#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH] -#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32 -#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L] -#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL] -#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH] -#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H] -#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL] -#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH] -#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32 -#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L] -#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL] -#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH] -#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H] -#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL] -#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH] -#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32 -#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L] -#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL] -#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH] -#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H] -#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL] -#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH] -#define RSCAN0TMID57 RSCAN0.TMID57.UINT32 -#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L] -#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL] -#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH] -#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H] -#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL] -#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH] -#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32 -#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L] -#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL] -#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH] -#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H] -#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL] -#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH] -#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32 -#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L] -#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL] -#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH] -#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H] -#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL] -#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH] -#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32 -#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L] -#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL] -#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH] -#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H] -#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL] -#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH] -#define RSCAN0TMID58 RSCAN0.TMID58.UINT32 -#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L] -#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL] -#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH] -#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H] -#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL] -#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH] -#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32 -#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L] -#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL] -#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH] -#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H] -#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL] -#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH] -#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32 -#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L] -#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL] -#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH] -#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H] -#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL] -#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH] -#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32 -#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L] -#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL] -#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH] -#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H] -#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL] -#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH] -#define RSCAN0TMID59 RSCAN0.TMID59.UINT32 -#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L] -#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL] -#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH] -#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H] -#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL] -#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH] -#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32 -#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L] -#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL] -#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH] -#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H] -#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL] -#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH] -#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32 -#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L] -#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL] -#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH] -#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H] -#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL] -#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH] -#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32 -#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L] -#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL] -#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH] -#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H] -#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL] -#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH] -#define RSCAN0TMID60 RSCAN0.TMID60.UINT32 -#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L] -#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL] -#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH] -#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H] -#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL] -#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH] -#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32 -#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L] -#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL] -#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH] -#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H] -#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL] -#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH] -#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32 -#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L] -#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL] -#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH] -#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H] -#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL] -#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH] -#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32 -#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L] -#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL] -#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH] -#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H] -#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL] -#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH] -#define RSCAN0TMID61 RSCAN0.TMID61.UINT32 -#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L] -#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL] -#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH] -#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H] -#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL] -#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH] -#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32 -#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L] -#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL] -#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH] -#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H] -#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL] -#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH] -#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32 -#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L] -#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL] -#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH] -#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H] -#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL] -#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH] -#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32 -#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L] -#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL] -#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH] -#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H] -#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL] -#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH] -#define RSCAN0TMID62 RSCAN0.TMID62.UINT32 -#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L] -#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL] -#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH] -#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H] -#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL] -#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH] -#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32 -#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L] -#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL] -#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH] -#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H] -#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL] -#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH] -#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32 -#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L] -#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL] -#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH] -#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H] -#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL] -#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH] -#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32 -#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L] -#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL] -#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH] -#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H] -#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL] -#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH] -#define RSCAN0TMID63 RSCAN0.TMID63.UINT32 -#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L] -#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL] -#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH] -#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H] -#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL] -#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH] -#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32 -#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L] -#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL] -#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH] -#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H] -#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL] -#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH] -#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32 -#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L] -#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL] -#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH] -#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H] -#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL] -#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH] -#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32 -#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L] -#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL] -#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH] -#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H] -#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL] -#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH] -#define RSCAN0TMID64 RSCAN0.TMID64.UINT32 -#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L] -#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL] -#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH] -#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H] -#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL] -#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH] -#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32 -#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L] -#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL] -#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH] -#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H] -#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL] -#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH] -#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32 -#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L] -#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL] -#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH] -#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H] -#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL] -#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH] -#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32 -#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L] -#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL] -#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH] -#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H] -#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL] -#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH] -#define RSCAN0TMID65 RSCAN0.TMID65.UINT32 -#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L] -#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL] -#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH] -#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H] -#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL] -#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH] -#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32 -#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L] -#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL] -#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH] -#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H] -#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL] -#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH] -#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32 -#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L] -#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL] -#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH] -#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H] -#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL] -#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH] -#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32 -#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L] -#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL] -#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH] -#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H] -#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL] -#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH] -#define RSCAN0TMID66 RSCAN0.TMID66.UINT32 -#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L] -#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL] -#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH] -#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H] -#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL] -#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH] -#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32 -#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L] -#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL] -#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH] -#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H] -#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL] -#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH] -#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32 -#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L] -#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL] -#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH] -#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H] -#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL] -#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH] -#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32 -#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L] -#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL] -#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH] -#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H] -#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL] -#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH] -#define RSCAN0TMID67 RSCAN0.TMID67.UINT32 -#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L] -#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL] -#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH] -#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H] -#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL] -#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH] -#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32 -#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L] -#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL] -#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH] -#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H] -#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL] -#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH] -#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32 -#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L] -#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL] -#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH] -#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H] -#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL] -#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH] -#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32 -#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L] -#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL] -#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH] -#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H] -#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL] -#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH] -#define RSCAN0TMID68 RSCAN0.TMID68.UINT32 -#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L] -#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL] -#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH] -#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H] -#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL] -#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH] -#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32 -#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L] -#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL] -#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH] -#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H] -#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL] -#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH] -#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32 -#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L] -#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL] -#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH] -#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H] -#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL] -#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH] -#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32 -#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L] -#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL] -#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH] -#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H] -#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL] -#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH] -#define RSCAN0TMID69 RSCAN0.TMID69.UINT32 -#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L] -#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL] -#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH] -#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H] -#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL] -#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH] -#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32 -#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L] -#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL] -#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH] -#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H] -#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL] -#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH] -#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32 -#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L] -#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL] -#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH] -#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H] -#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL] -#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH] -#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32 -#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L] -#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL] -#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH] -#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H] -#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL] -#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH] -#define RSCAN0TMID70 RSCAN0.TMID70.UINT32 -#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L] -#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL] -#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH] -#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H] -#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL] -#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH] -#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32 -#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L] -#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL] -#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH] -#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H] -#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL] -#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH] -#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32 -#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L] -#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL] -#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH] -#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H] -#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL] -#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH] -#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32 -#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L] -#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL] -#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH] -#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H] -#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL] -#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH] -#define RSCAN0TMID71 RSCAN0.TMID71.UINT32 -#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L] -#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL] -#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH] -#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H] -#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL] -#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH] -#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32 -#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L] -#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL] -#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH] -#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H] -#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL] -#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH] -#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32 -#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L] -#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL] -#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH] -#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H] -#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL] -#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH] -#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32 -#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L] -#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL] -#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH] -#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H] -#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL] -#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH] -#define RSCAN0TMID72 RSCAN0.TMID72.UINT32 -#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L] -#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL] -#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH] -#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H] -#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL] -#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH] -#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32 -#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L] -#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL] -#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH] -#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H] -#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL] -#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH] -#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32 -#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L] -#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL] -#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH] -#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H] -#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL] -#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH] -#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32 -#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L] -#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL] -#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH] -#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H] -#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL] -#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH] -#define RSCAN0TMID73 RSCAN0.TMID73.UINT32 -#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L] -#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL] -#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH] -#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H] -#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL] -#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH] -#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32 -#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L] -#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL] -#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH] -#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H] -#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL] -#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH] -#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32 -#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L] -#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL] -#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH] -#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H] -#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL] -#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH] -#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32 -#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L] -#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL] -#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH] -#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H] -#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL] -#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH] -#define RSCAN0TMID74 RSCAN0.TMID74.UINT32 -#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L] -#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL] -#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH] -#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H] -#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL] -#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH] -#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32 -#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L] -#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL] -#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH] -#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H] -#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL] -#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH] -#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32 -#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L] -#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL] -#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH] -#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H] -#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL] -#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH] -#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32 -#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L] -#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL] -#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH] -#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H] -#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL] -#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH] -#define RSCAN0TMID75 RSCAN0.TMID75.UINT32 -#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L] -#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL] -#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH] -#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H] -#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL] -#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH] -#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32 -#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L] -#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL] -#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH] -#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H] -#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL] -#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH] -#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32 -#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L] -#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL] -#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH] -#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H] -#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL] -#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH] -#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32 -#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L] -#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL] -#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH] -#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H] -#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL] -#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH] -#define RSCAN0TMID76 RSCAN0.TMID76.UINT32 -#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L] -#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL] -#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH] -#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H] -#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL] -#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH] -#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32 -#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L] -#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL] -#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH] -#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H] -#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL] -#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH] -#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32 -#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L] -#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL] -#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH] -#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H] -#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL] -#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH] -#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32 -#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L] -#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL] -#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH] -#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H] -#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL] -#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH] -#define RSCAN0TMID77 RSCAN0.TMID77.UINT32 -#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L] -#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL] -#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH] -#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H] -#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL] -#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH] -#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32 -#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L] -#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL] -#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH] -#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H] -#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL] -#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH] -#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32 -#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L] -#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL] -#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH] -#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H] -#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL] -#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH] -#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32 -#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L] -#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL] -#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH] -#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H] -#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL] -#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH] -#define RSCAN0TMID78 RSCAN0.TMID78.UINT32 -#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L] -#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL] -#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH] -#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H] -#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL] -#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH] -#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32 -#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L] -#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL] -#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH] -#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H] -#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL] -#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH] -#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32 -#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L] -#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL] -#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH] -#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H] -#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL] -#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH] -#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32 -#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L] -#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL] -#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH] -#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H] -#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL] -#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH] -#define RSCAN0TMID79 RSCAN0.TMID79.UINT32 -#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L] -#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL] -#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH] -#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H] -#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL] -#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH] -#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32 -#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L] -#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL] -#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH] -#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H] -#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL] -#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH] -#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32 -#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L] -#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL] -#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH] -#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H] -#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL] -#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH] -#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32 -#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L] -#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL] -#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH] -#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H] -#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL] -#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH] -#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32 -#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L] -#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL] -#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH] -#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H] -#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL] -#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH] -#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32 -#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L] -#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL] -#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH] -#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H] -#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL] -#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH] -#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32 -#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L] -#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL] -#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH] -#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H] -#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL] -#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH] -#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32 -#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L] -#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL] -#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH] -#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H] -#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL] -#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH] -#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32 -#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L] -#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL] -#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH] -#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H] -#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL] -#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH] -/* <-SEC M1.10.1 */ -/* <-QAC 0857 */ -/* <-QAC 0639 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h deleted file mode 100644 index 0fbd14e702b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h +++ /dev/null @@ -1,204 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rspi_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register (V1.00a) -******************************************************************************/ -#ifndef RSPI_IODEFINE_H -#define RSPI_IODEFINE_H -/* ->SEC M1.10.1 : Not magic number */ - -#include "reg32_t.h" - -struct st_rspi -{ /* RSPI */ - volatile uint8_t SPCR; /* SPCR */ - volatile uint8_t SSLP; /* SSLP */ - volatile uint8_t SPPCR; /* SPPCR */ - volatile uint8_t SPSR; /* SPSR */ - union reg32_t SPDR; /* SPDR */ - - volatile uint8_t SPSCR; /* SPSCR */ - volatile uint8_t SPSSR; /* SPSSR */ - volatile uint8_t SPBR; /* SPBR */ - volatile uint8_t SPDCR; /* SPDCR */ - volatile uint8_t SPCKD; /* SPCKD */ - volatile uint8_t SSLND; /* SSLND */ - volatile uint8_t SPND; /* SPND */ - volatile uint8_t dummy1[1]; /* */ -#define SPCMD_COUNT 4 - volatile uint16_t SPCMD0; /* SPCMD0 */ - volatile uint16_t SPCMD1; /* SPCMD1 */ - volatile uint16_t SPCMD2; /* SPCMD2 */ - volatile uint16_t SPCMD3; /* SPCMD3 */ - volatile uint8_t dummy2[8]; /* */ - volatile uint8_t SPBFCR; /* SPBFCR */ - volatile uint8_t dummy3[1]; /* */ - volatile uint16_t SPBFDR; /* SPBFDR */ -}; - - -#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ -#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ -#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ -#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ -#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ - - -/* Start of channnel array defines of RSPI */ - -/* Channnel array defines of RSPI */ -/*(Sample) value = RSPI[ channel ]->SPCR; */ -#define RSPI_COUNT 5 -#define RSPI_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of RSPI */ - - -#define SPCR_0 RSPI0.SPCR -#define SSLP_0 RSPI0.SSLP -#define SPPCR_0 RSPI0.SPPCR -#define SPSR_0 RSPI0.SPSR -#define SPDR_0 RSPI0.SPDR.UINT32 -#define SPDR_0L RSPI0.SPDR.UINT16[L] -#define SPDR_0H RSPI0.SPDR.UINT16[H] -#define SPDR_0LL RSPI0.SPDR.UINT8[LL] -#define SPDR_0LH RSPI0.SPDR.UINT8[LH] -#define SPDR_0HL RSPI0.SPDR.UINT8[HL] -#define SPDR_0HH RSPI0.SPDR.UINT8[HH] -#define SPSCR_0 RSPI0.SPSCR -#define SPSSR_0 RSPI0.SPSSR -#define SPBR_0 RSPI0.SPBR -#define SPDCR_0 RSPI0.SPDCR -#define SPCKD_0 RSPI0.SPCKD -#define SSLND_0 RSPI0.SSLND -#define SPND_0 RSPI0.SPND -#define SPCMD0_0 RSPI0.SPCMD0 -#define SPCMD1_0 RSPI0.SPCMD1 -#define SPCMD2_0 RSPI0.SPCMD2 -#define SPCMD3_0 RSPI0.SPCMD3 -#define SPBFCR_0 RSPI0.SPBFCR -#define SPBFDR_0 RSPI0.SPBFDR -#define SPCR_1 RSPI1.SPCR -#define SSLP_1 RSPI1.SSLP -#define SPPCR_1 RSPI1.SPPCR -#define SPSR_1 RSPI1.SPSR -#define SPDR_1 RSPI1.SPDR.UINT32 -#define SPDR_1L RSPI1.SPDR.UINT16[L] -#define SPDR_1H RSPI1.SPDR.UINT16[H] -#define SPDR_1LL RSPI1.SPDR.UINT8[LL] -#define SPDR_1LH RSPI1.SPDR.UINT8[LH] -#define SPDR_1HL RSPI1.SPDR.UINT8[HL] -#define SPDR_1HH RSPI1.SPDR.UINT8[HH] -#define SPSCR_1 RSPI1.SPSCR -#define SPSSR_1 RSPI1.SPSSR -#define SPBR_1 RSPI1.SPBR -#define SPDCR_1 RSPI1.SPDCR -#define SPCKD_1 RSPI1.SPCKD -#define SSLND_1 RSPI1.SSLND -#define SPND_1 RSPI1.SPND -#define SPCMD0_1 RSPI1.SPCMD0 -#define SPCMD1_1 RSPI1.SPCMD1 -#define SPCMD2_1 RSPI1.SPCMD2 -#define SPCMD3_1 RSPI1.SPCMD3 -#define SPBFCR_1 RSPI1.SPBFCR -#define SPBFDR_1 RSPI1.SPBFDR -#define SPCR_2 RSPI2.SPCR -#define SSLP_2 RSPI2.SSLP -#define SPPCR_2 RSPI2.SPPCR -#define SPSR_2 RSPI2.SPSR -#define SPDR_2 RSPI2.SPDR.UINT32 -#define SPDR_2L RSPI2.SPDR.UINT16[L] -#define SPDR_2H RSPI2.SPDR.UINT16[H] -#define SPDR_2LL RSPI2.SPDR.UINT8[LL] -#define SPDR_2LH RSPI2.SPDR.UINT8[LH] -#define SPDR_2HL RSPI2.SPDR.UINT8[HL] -#define SPDR_2HH RSPI2.SPDR.UINT8[HH] -#define SPSCR_2 RSPI2.SPSCR -#define SPSSR_2 RSPI2.SPSSR -#define SPBR_2 RSPI2.SPBR -#define SPDCR_2 RSPI2.SPDCR -#define SPCKD_2 RSPI2.SPCKD -#define SSLND_2 RSPI2.SSLND -#define SPND_2 RSPI2.SPND -#define SPCMD0_2 RSPI2.SPCMD0 -#define SPCMD1_2 RSPI2.SPCMD1 -#define SPCMD2_2 RSPI2.SPCMD2 -#define SPCMD3_2 RSPI2.SPCMD3 -#define SPBFCR_2 RSPI2.SPBFCR -#define SPBFDR_2 RSPI2.SPBFDR -#define SPCR_3 RSPI3.SPCR -#define SSLP_3 RSPI3.SSLP -#define SPPCR_3 RSPI3.SPPCR -#define SPSR_3 RSPI3.SPSR -#define SPDR_3 RSPI3.SPDR.UINT32 -#define SPDR_3L RSPI3.SPDR.UINT16[L] -#define SPDR_3H RSPI3.SPDR.UINT16[H] -#define SPDR_3LL RSPI3.SPDR.UINT8[LL] -#define SPDR_3LH RSPI3.SPDR.UINT8[LH] -#define SPDR_3HL RSPI3.SPDR.UINT8[HL] -#define SPDR_3HH RSPI3.SPDR.UINT8[HH] -#define SPSCR_3 RSPI3.SPSCR -#define SPSSR_3 RSPI3.SPSSR -#define SPBR_3 RSPI3.SPBR -#define SPDCR_3 RSPI3.SPDCR -#define SPCKD_3 RSPI3.SPCKD -#define SSLND_3 RSPI3.SSLND -#define SPND_3 RSPI3.SPND -#define SPCMD0_3 RSPI3.SPCMD0 -#define SPCMD1_3 RSPI3.SPCMD1 -#define SPCMD2_3 RSPI3.SPCMD2 -#define SPCMD3_3 RSPI3.SPCMD3 -#define SPBFCR_3 RSPI3.SPBFCR -#define SPBFDR_3 RSPI3.SPBFDR -#define SPCR_4 RSPI4.SPCR -#define SSLP_4 RSPI4.SSLP -#define SPPCR_4 RSPI4.SPPCR -#define SPSR_4 RSPI4.SPSR -#define SPDR_4 RSPI4.SPDR.UINT32 -#define SPDR_4L RSPI4.SPDR.UINT16[L] -#define SPDR_4H RSPI4.SPDR.UINT16[H] -#define SPDR_4LL RSPI4.SPDR.UINT8[LL] -#define SPDR_4LH RSPI4.SPDR.UINT8[LH] -#define SPDR_4HL RSPI4.SPDR.UINT8[HL] -#define SPDR_4HH RSPI4.SPDR.UINT8[HH] -#define SPSCR_4 RSPI4.SPSCR -#define SPSSR_4 RSPI4.SPSSR -#define SPBR_4 RSPI4.SPBR -#define SPDCR_4 RSPI4.SPDCR -#define SPCKD_4 RSPI4.SPCKD -#define SSLND_4 RSPI4.SSLND -#define SPND_4 RSPI4.SPND -#define SPCMD0_4 RSPI4.SPCMD0 -#define SPCMD1_4 RSPI4.SPCMD1 -#define SPCMD2_4 RSPI4.SPCMD2 -#define SPCMD3_4 RSPI4.SPCMD3 -#define SPBFCR_4 RSPI4.SPBFCR -#define SPBFDR_4 RSPI4.SPBFDR -/* <-SEC M1.10.1 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h deleted file mode 100644 index d25b903b89a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h +++ /dev/null @@ -1,173 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : spibsc_iodefine.h -* $Rev: $ -* $Date:: $ -* Description : Definition of I/O Register (V1.00a) -******************************************************************************/ -#ifndef SPIBSC_IODEFINE_H -#define SPIBSC_IODEFINE_H -/* ->SEC M1.10.1 : Not magic number */ - -struct st_spibsc -{ /* SPIBSC */ - volatile uint32_t CMNCR; /* CMNCR */ - volatile uint32_t SSLDR; /* SSLDR */ - volatile uint32_t SPBCR; /* SPBCR */ - volatile uint32_t DRCR; /* DRCR */ - volatile uint32_t DRCMR; /* DRCMR */ - volatile uint32_t DREAR; /* DREAR */ - volatile uint32_t DROPR; /* DROPR */ - volatile uint32_t DRENR; /* DRENR */ - volatile uint32_t SMCR; /* SMCR */ - volatile uint32_t SMCMR; /* SMCMR */ - volatile uint32_t SMADR; /* SMADR */ - volatile uint32_t SMOPR; /* SMOPR */ - volatile uint32_t SMENR; /* SMENR */ - volatile uint8_t dummy1[4]; /* */ - union iodefine_reg32_t SMRDR0; /* SMRDR0 */ - union iodefine_reg32_t SMRDR1; /* SMRDR1 */ - union iodefine_reg32_t SMWDR0; /* SMWDR0 */ - union iodefine_reg32_t SMWDR1; /* SMWDR1 */ - - volatile uint32_t CMNSR; /* CMNSR */ - volatile uint8_t dummy2[12]; /* */ - volatile uint32_t DRDMCR; /* DRDMCR */ - volatile uint32_t DRDRENR; /* DRDRENR */ - volatile uint32_t SMDMCR; /* SMDMCR */ - volatile uint32_t SMDRENR; /* SMDRENR */ -}; - - -#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ -#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ - - -/* Start of channnel array defines of SPIBSC */ - -/* Channnel array defines of SPIBSC */ -/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ -#define SPIBSC_COUNT 2 -#define SPIBSC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SPIBSC0, &SPIBSC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SPIBSC */ - - -#define CMNCR_0 SPIBSC0.CMNCR -#define SSLDR_0 SPIBSC0.SSLDR -#define SPBCR_0 SPIBSC0.SPBCR -#define DRCR_0 SPIBSC0.DRCR -#define DRCMR_0 SPIBSC0.DRCMR -#define DREAR_0 SPIBSC0.DREAR -#define DROPR_0 SPIBSC0.DROPR -#define DRENR_0 SPIBSC0.DRENR -#define SMCR_0 SPIBSC0.SMCR -#define SMCMR_0 SPIBSC0.SMCMR -#define SMADR_0 SPIBSC0.SMADR -#define SMOPR_0 SPIBSC0.SMOPR -#define SMENR_0 SPIBSC0.SMENR -#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32 -#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L] -#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H] -#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL] -#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH] -#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL] -#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH] -#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32 -#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L] -#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H] -#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL] -#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH] -#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL] -#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH] -#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32 -#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L] -#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H] -#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL] -#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH] -#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL] -#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH] -#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32 -#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L] -#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H] -#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL] -#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH] -#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL] -#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH] -#define CMNSR_0 SPIBSC0.CMNSR -#define DRDMCR_0 SPIBSC0.DRDMCR -#define DRDRENR_0 SPIBSC0.DRDRENR -#define SMDMCR_0 SPIBSC0.SMDMCR -#define SMDRENR_0 SPIBSC0.SMDRENR -#define CMNCR_1 SPIBSC1.CMNCR -#define SSLDR_1 SPIBSC1.SSLDR -#define SPBCR_1 SPIBSC1.SPBCR -#define DRCR_1 SPIBSC1.DRCR -#define DRCMR_1 SPIBSC1.DRCMR -#define DREAR_1 SPIBSC1.DREAR -#define DROPR_1 SPIBSC1.DROPR -#define DRENR_1 SPIBSC1.DRENR -#define SMCR_1 SPIBSC1.SMCR -#define SMCMR_1 SPIBSC1.SMCMR -#define SMADR_1 SPIBSC1.SMADR -#define SMOPR_1 SPIBSC1.SMOPR -#define SMENR_1 SPIBSC1.SMENR -#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32 -#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L] -#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H] -#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL] -#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH] -#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL] -#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH] -#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32 -#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L] -#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H] -#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL] -#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH] -#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL] -#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH] -#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32 -#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L] -#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H] -#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL] -#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH] -#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL] -#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH] -#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32 -#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L] -#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H] -#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL] -#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH] -#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL] -#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH] -#define CMNSR_1 SPIBSC1.CMNSR -#define DRDMCR_1 SPIBSC1.DRDMCR -#define DRDRENR_1 SPIBSC1.DRDRENR -#define SMDMCR_1 SPIBSC1.SMDMCR -#define SMDRENR_1 SPIBSC1.SMDRENR -/* <-SEC M1.10.1 */ -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h deleted file mode 100644 index 5f0fec64ddc..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h +++ /dev/null @@ -1,83 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rza_io_regrw.h -* $Rev: 1135 $ -* $Date:: 2014-08-08 10:11:30 +0900#$ -* Description : Low level register read/write header -*******************************************************************************/ -#ifndef RZA_IO_REGRW_H -#define RZA_IO_REGRW_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -/* ==== includes each bit mask header ==== */ -#include "cpg_iobitmask.h" -#include "intc_iobitmask.h" -#include "bsc_iobitmask.h" -#include "dmac_iobitmask.h" -#include "mtu2_iobitmask.h" -#include "ostm_iobitmask.h" -#include "scif_iobitmask.h" -#include "rspi_iobitmask.h" -#include "riic_iobitmask.h" -#include "usb_iobitmask.h" -#include "gpio_iobitmask.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - - -/****************************************************************************** -Macro definitions -******************************************************************************/ - - -/****************************************************************************** -Variable Externs -******************************************************************************/ - - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ -void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask); -void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask); -void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask); -uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask); -uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask); -uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask); - -#ifdef __cplusplus -} -#endif - -#endif /* RZA_IO_REGRW_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h deleted file mode 100644 index fcdf554bb87..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h +++ /dev/null @@ -1,84 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** -* @file nvic_wrapper.h -* $Rev: $ -* $Date:: $ -* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) -******************************************************************************/ - -#ifndef NVIC_WRAPPER_H -#define NVIC_WRAPPER_H - - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ - -/****************************************************************************** -Variable Externs -******************************************************************************/ - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -/* NVIC functions */ -void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -uint32_t NVIC_GetPriorityGrouping(void); -void NVIC_EnableIRQ(IRQn_Type IRQn); -void NVIC_DisableIRQ(IRQn_Type IRQn); -uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); -void NVIC_SetPendingIRQ(IRQn_Type IRQn); -void NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t NVIC_GetActive(IRQn_Type IRQn); -void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); -uint32_t NVIC_GetPriority(IRQn_Type IRQn); -uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); -void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -void NVIC_SystemReset(void); -/* SysTick function */ -uint32_t SysTick_Config(uint32_t ticks); -/* Debug In/Output function */ -uint32_t ITM_SendChar (uint32_t ch); -int32_t ITM_ReceiveChar (void); -int32_t ITM_CheckChar (void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* NVIC_WRAPPER_H */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.h deleted file mode 100644 index 0960a4d1f3d..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************//** - * @file pl310.h - * @brief Implementation of pl310 functions - * @version - * @date 11 June 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef __PL310 -#define __PL310 - -typedef struct -{ - __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */ - __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */ - uint32_t RESERVED0[0x3e]; - __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */ - __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */ - uint32_t RESERVED1[0x3e]; - __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */ - __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */ - __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */ - uint32_t RESERVED2[0x2]; - __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */ - __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */ - __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */ - __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */ - uint32_t RESERVED3[0x143]; - __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */ - uint32_t RESERVED4[0xf]; - __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */ - uint32_t RESERVED6[2]; - __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */ - uint32_t RESERVED5[0xc]; - __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */ - uint32_t RESERVED7[1]; - __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */ - __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */ - uint32_t RESERVED8[0xc]; - __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */ - uint32_t RESERVED9[1]; - __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ - __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */ - uint32_t RESERVED10[0x40]; - __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */ - __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */ - __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */ - __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */ - __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */ - __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */ - __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */ - __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */ - __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */ - __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */ - __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */ - __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */ - uint32_t RESERVED11[0x4]; - __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */ - __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */ - uint32_t RESERVED12[0xaa]; - __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */ - __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */ - uint32_t RESERVED13[0xce]; - __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */ - -} PL310_TypeDef; - -#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */ - -extern int PL310_GetID (void); -extern int PL310_GetType (void); -extern void PL310_InvAllByWay (void); -extern void PL310_CleanInvAllByWay(void); -extern void PL310_Enable(void); -extern void PL310_Disable(void); -extern void PL310_InvPa (void *); -extern void PL310_CleanPa (void *); -extern void PL310_CleanInvPa (void *); - -#endif - - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h deleted file mode 100644 index 188c22218d7..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : r_typedefs.h -* $Rev: 788 $ -* $Date:: 2014-04-07 18:57:13 +0900#$ -* Description : basic type definition -******************************************************************************/ -#ifndef R_TYPEDEFS_H -#define R_TYPEDEFS_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include -#include -#include - -#if defined(__ARM_NEON__) - -#include - -#else /* __ARM_NEON__ */ - -typedef float float32_t; -typedef double float64_t; - -#endif /* __ARM_NEON__ */ - -/****************************************************************************** -Typedef definitions -******************************************************************************/ -typedef char char_t; -typedef int bool_t; -typedef int int_t; -typedef long double float128_t; -typedef signed long long_t; -typedef unsigned long ulong_t; - -#endif /* R_TYPEDEFS_H */ - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c deleted file mode 100644 index f919fa8c8bd..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c +++ /dev/null @@ -1,200 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rza_io_regrw.c -* $Rev: 1121 $ -* $Date:: 2014-08-06 17:09:53 +0900#$ -* Description : Low level register read/write -*******************************************************************************/ - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include "r_typedefs.h" - -#ifdef __CC_ARM -#pragma arm section code = "CODE_IO_REGRW" -#pragma arm section rodata = "CONST_IO_REGRW" -#pragma arm section rwdata = "DATA_IO_REGRW" -#pragma arm section zidata = "BSS_IO_REGRW" -#endif - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - - -/****************************************************************************** -Macro definitions -******************************************************************************/ - - -/****************************************************************************** -Imported global variables and functions (from other files) -******************************************************************************/ - - -/****************************************************************************** -Exported global variables and functions (to be accessed by other files) -******************************************************************************/ - - -/****************************************************************************** -Private global variables and functions -******************************************************************************/ - - -/****************************************************************************** -* Function Name: RZA_IO_RegWrite_8 -* Description : IO register 8-bit write -* Arguments : volatile uint8_t * ioreg : IO register for writing -* : : Use register definition name of the -* : : iodefine.h -* : uint8_t write_value : Write value for the IO register -* : uint8_t shift : The number of left shifts to the -* : : target bit -* : uint8_t mask : Mask value for the IO register -* : : (Target bit : "1") -* Return Value : None -******************************************************************************/ -void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask) -{ - uint8_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ - *ioreg = reg_value; /* Write to register */ -} - -/****************************************************************************** -* Function Name: RZA_IO_RegWrite_16 -* Description : IO register 16-bit write -* Arguments : volatile uint16_t * ioreg : IO register for writing -* : : Use register definition name of the -* : : iodefine.h -* : uint16_t write_value : Write value for the IO register -* : uint16_t shift : The number of left shifts to the -* : : target bit -* : uint16_t mask : Mask value for the IO register -* : : (Target bit : "1") -* Return Value : None -******************************************************************************/ -void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask) -{ - uint16_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ - *ioreg = reg_value; /* Write to register */ -} - -/****************************************************************************** -* Function Name: RZA_IO_RegWrite_32 -* Description : IO register 32-bit write -* Arguments : volatile uint32_t * ioreg : IO register for writing -* : : Use register definition name of the -* : : iodefine.h -* : uint32_t write_value : Write value for the IO register -* : uint32_t shift : The number of left shifts to the -* : : target bit -* : uint32_t mask : Mask value for the IO register -* : : (Target bit : "1") -* Return Value : None -******************************************************************************/ -void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) -{ - uint32_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ - *ioreg = reg_value; /* Write to register */ -} - -/****************************************************************************** -* Function Name: RZA_IO_RegRead_8 -* Description : IO register 8-bit read -* Arguments : volatile uint8_t * ioreg : IO register for reading -* : : Use register definition name of the -* : : iodefine.h -* : uint8_t shift : The number of right shifts to the -* : : target bit -* : uint8_t mask : Mask bit for the IO register -* : : (Target bit: "1") -* Return Value : uint8_t : Value of the obtained target bit -******************************************************************************/ -uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask) -{ - uint8_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ - - return reg_value; -} - -/****************************************************************************** -* Function Name: RZA_IO_RegRead_16 -* Description : IO register 16-bit read -* Arguments : volatile uint16_t * ioreg : IO register for reading -* : : Use register definition name of the -* : : iodefine.h -* : uint16_t shift : The number of right shifts to the -* : : target bit -* : uint16_t mask : Mask bit for the IO register -* : : (Target bit: "1") -* Return Value : uint16_t : Value of the obtained target bit -******************************************************************************/ -uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask) -{ - uint16_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ - - return reg_value; -} - -/****************************************************************************** -* Function Name: RZA_IO_RegRead_32 -* Description : IO register 32-bit read -* Arguments : volatile uint32_t * ioreg : IO register for reading -* : : Use register definition name of the -* : : iodefine.h -* : uint32_t shift : The number of right shifts to the -* : : target bit -* : uint32_t mask : Mask bit for the IO register -* : : (Target bit: "1") -* Return Value : uint32_t : Value of the obtained target bit -******************************************************************************/ -uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask) -{ - uint32_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ - - return reg_value; -} - - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c deleted file mode 100644 index de43879c168..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c +++ /dev/null @@ -1,695 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "ether_iodefine.h" -#include "ethernetext_api.h" - -/* Descriptor info */ -#define NUM_OF_TX_DESCRIPTOR (16) -#define NUM_OF_RX_DESCRIPTOR (16) -#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ -#define MAX_SEND_SIZE (1514) -/* Ethernet Descriptor Value Define */ -#define TD0_TFP_TOP_BOTTOM (0x30000000) -#define TD0_TACT (0x80000000) -#define TD0_TDLE (0x40000000) -#define RD0_RACT (0x80000000) -#define RD0_RDLE (0x40000000) -#define RD0_RFE (0x08000000) -#define RD0_RCSE (0x04000000) -#define RD0_RFS (0x03FF0000) -#define RD0_RCS (0x0000FFFF) -#define RD0_RFS_RFOF (0x02000000) -#define RD0_RFS_RUAF (0x00400000) -#define RD0_RFS_RRF (0x00100000) -#define RD0_RFS_RTLF (0x00080000) -#define RD0_RFS_RTSF (0x00040000) -#define RD0_RFS_PRE (0x00020000) -#define RD0_RFS_CERF (0x00010000) -#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ - RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) -#define RD1_RDL_MSK (0x0000FFFF) -/* PHY Register */ -#define BASIC_MODE_CONTROL_REG (0) -#define BASIC_MODE_STATUS_REG (1) -#define PHY_IDENTIFIER1_REG (2) -#define PHY_IDENTIFIER2_REG (3) -#define PHY_SP_CTL_STS_REG (31) -/* MII management interface access */ -#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ -#define PHY_ST (1) -#define PHY_WRITE (1) -#define PHY_READ (2) -#define MDC_WAIT (6) /* 400ns/4 */ -#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ -#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */ -#define M_PHY_ID (0xFFFFFFF0) -#define PHY_ID_LAN8710A (0x0007C0F0) -/* ETHERPIR0 */ -#define PIR0_MDI (0x00000008) -#define PIR0_MDO (0x00000004) -#define PIR0_MMD (0x00000002) -#define PIR0_MDC (0x00000001) -#define PIR0_MDC_HIGH (0x00000001) -#define PIR0_MDC_LOW (0x00000000) -/* ETHEREDRRR0 */ -#define EDRRR0_RR (0x00000001) -/* ETHEREDTRR0 */ -#define EDTRR0_TR (0x00000003) -/* software wait */ -#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ - -#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ - /* 0x00040000 : Detect frame reception */ - /* 0x00010000 : Receive FIFO overflow */ - /* 0x00000010 : Residual bit frame reception */ - /* 0x00000008 : Long frame reception */ - /* 0x00000004 : Short frame reception */ - /* 0x00000002 : PHY-LSI reception error */ - /* 0x00000001 : Receive frame CRC error */ -#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ - -/* Send descriptor */ -typedef struct tag_edmac_send_desc { - uint32_t td0; - uint32_t td1; - uint8_t *td2; - uint32_t padding4; -} edmac_send_desc_t; - -/* Receive descriptor */ -typedef struct tag_edmac_recv_desc { - uint32_t rd0; - uint32_t rd1; - uint8_t *rd2; - uint32_t padding4; -} edmac_recv_desc_t; - -/* memory */ -/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ -/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ -#if defined(__ICCARM__) -#pragma data_alignment=16 -static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! - @ ".mirrorram"; -#else -static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] - __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! -#endif -static int32_t rx_read_offset; /* read offset */ -static int32_t tx_wite_offset; /* write offset */ -static uint32_t send_top_index; -static uint32_t recv_top_index; -static int32_t Interrupt_priority; -static edmac_send_desc_t *p_eth_desc_dsend = NULL; -static edmac_recv_desc_t *p_eth_desc_drecv = NULL; -static edmac_recv_desc_t *p_recv_end_desc = NULL; -static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; -static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ -static uint32_t phy_id = 0; -static uint32_t start_stop = 1; /* 0:stop 1:start */ - -/* function */ -static void lan_reg_reset(void); -static void lan_desc_create(void); -static void lan_reg_set(int32_t link); -static uint16_t phy_reg_read(uint16_t reg_addr); -static void phy_reg_write(uint16_t reg_addr, uint16_t data); -static void mii_preamble(void); -static void mii_cmd(uint16_t reg_addr, uint32_t option); -static void mii_reg_read(uint16_t *data); -static void mii_reg_write(uint16_t data); -static void mii_z(void); -static void mii_write_1(void); -static void mii_write_0(void); -static void set_ether_pir(uint32_t set_data); -static void wait_100us(int32_t wait_cnt); - - -int ethernetext_init(ethernet_cfg_t *p_ethcfg) { - int32_t i; - uint16_t val; - - CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ - - /* -->4F<-- P1_14(ET_COL) */ - GPIOPMC1 |= 0x4000; - GPIOPFCAE1 &= ~0x4000; - GPIOPFCE1 |= 0x4000; - GPIOPFC1 |= 0x4000; - GPIOPIPC1 |= 0x4000; - - /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0), - P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */ - GPIOPMC2 |= 0x0FFF; - GPIOPFCAE2 &= ~0x0FFF; - GPIOPFCE2 &= ~0x0FFF; - GPIOPFC2 |= 0x0FFF; - GPIOPIPC2 |= 0x0FFF; - - /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ - GPIOPMC3 |= 0x0078; - GPIOPFCAE3 &= ~0x0078; - GPIOPFCE3 &= ~0x0078; - GPIOPFC3 |= 0x0078; - GPIOPIPC3 |= 0x0078; - - /* -->3F<-- P7_0(ET_MDC) */ - GPIOPMC7 |= 0x0001; - GPIOPFCAE7 &= ~0x0001; - GPIOPFCE7 |= 0x0001; - GPIOPFC7 &= ~0x0001; - GPIOPIPC7 |= 0x0001; - - /* Resets the E-MAC,E-DMAC */ - lan_reg_reset(); - - /* Resets the PHY-LSI */ - phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); - for (i = 10000; i > 0; i--) { - val = phy_reg_read(BASIC_MODE_CONTROL_REG); - if (((uint32_t)val & 0x8000uL) == 0) { - break; /* Reset complete */ - } - } - - phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) - | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); - - Interrupt_priority = p_ethcfg->int_priority; - p_recv_cb_fnc = p_ethcfg->recv_cb; - start_stop = 1; - - if (p_ethcfg->ether_mac != NULL) { - (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); - } else { - ethernet_address(mac_addr); /* Get MAC Address */ - } - - return 0; -} - -void ethernetext_start_stop(int32_t mode) { - if (mode == 1) { - /* start */ - ETHEREDTRR0 |= EDTRR0_TR; - ETHEREDRRR0 |= EDRRR0_RR; - start_stop = 1; - } else { - /* stop */ - ETHEREDTRR0 &= ~EDTRR0_TR; - ETHEREDRRR0 &= ~EDRRR0_RR; - start_stop = 0; - } -} - -int ethernetext_chk_link_mode(void) { - int32_t link; - uint16_t data; - - if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { - data = phy_reg_read(PHY_SP_CTL_STS_REG); - switch (((uint32_t)data >> 2) & 0x00000007) { - case 0x0001: - link = HALF_10M; - break; - case 0x0005: - link = FULL_10M; - break; - case 0x0002: - link = HALF_TX; - break; - case 0x0006: - link = FULL_TX; - break; - default: - link = NEGO_FAIL; - break; - } - } else { - link = NEGO_FAIL; - } - - return link; -} - -void ethernetext_set_link_mode(int32_t link) { - lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ - lan_desc_create(); /* Initialize of buffer memory */ - lan_reg_set(link); /* E-DMAC, E-MAC initialization */ -} - -int ethernet_init() { - ethernet_cfg_t ethcfg; - - ethcfg.int_priority = 5; - ethcfg.recv_cb = NULL; - ethcfg.ether_mac = NULL; - ethernetext_init(ðcfg); - ethernet_set_link(-1, 0); /* Auto-Negotiation */ - - return 0; -} - -void ethernet_free() { - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ -} - -int ethernet_write(const char *data, int slen) { - edmac_send_desc_t *p_send_desc; - int32_t copy_size; - - if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) - || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { - copy_size = 0; - } else { - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - if ((p_send_desc->td0 & TD0_TACT) != 0) { - copy_size = 0; - } else { - copy_size = MAX_SEND_SIZE - tx_wite_offset; - if (copy_size > slen) { - copy_size = slen; - } - (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); - tx_wite_offset += copy_size; - } - } - - return copy_size; -} - -int ethernet_send() { - edmac_send_desc_t *p_send_desc; - int32_t ret; - - if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { - ret = 0; - } else { - /* Transfer 1 frame */ - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - - /* Sets the frame length */ - p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); - tx_wite_offset = 0; - - /* Sets the transmit descriptor to transmit again */ - p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); - p_send_desc->td0 |= TD0_TACT; - if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { - ETHEREDTRR0 |= EDTRR0_TR; - } - - /* Update the current descriptor */ - send_top_index++; - if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { - send_top_index = 0; - } - ret = 1; - } - - return ret; -} - -int ethernet_receive() { - edmac_recv_desc_t *p_recv_desc; - int32_t receive_size = 0; - - if (p_eth_desc_drecv != NULL) { - if (p_recv_end_desc != NULL) { - /* Sets the receive descriptor to receive again */ - p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_end_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - p_recv_end_desc = NULL; - } - - p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ - if ((p_recv_desc->rd0 & RD0_RACT) == 0) { - /* Receives 1 frame */ - if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { - /* Receive frame error */ - /* Sets the receive descriptor to receive again */ - p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - } else { - /* Copies the received frame */ - rx_read_offset = 0; - p_recv_end_desc = p_recv_desc; - receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ - } - - /* Update the current descriptor */ - recv_top_index++; - if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { - recv_top_index = 0; - } - } - } - - return receive_size; -} - -int ethernet_read(char *data, int dlen) { - edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ - int32_t copy_size; - - if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { - copy_size = 0; - } else { - copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; - if (copy_size > dlen) { - copy_size = dlen; - } - (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); - rx_read_offset += copy_size; - } - - return copy_size; -} - -void ethernet_address(char *mac) { - if (mac != NULL) { - mbed_mac_address(mac); /* Get MAC Address */ - } -} - -int ethernet_link(void) { - int32_t ret; - uint16_t data; - - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { - ret = 1; - } else { - ret = 0; - } - - return ret; -} - -void ethernet_set_link(int speed, int duplex) { - uint16_t data; - int32_t i; - int32_t link; - - if ((speed < 0) || (speed > 1)) { - data = 0x1000; /* Auto-Negotiation Enable */ - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - for (i = 0; i < 1000; i++) { - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { - break; - } - wait_100us(10); - } - } else { - data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - wait_100us(1); - } - - link = ethernetext_chk_link_mode(); - ethernetext_set_link_mode(link); -} - -void INT_Ether(void) { - uint32_t stat_edmac; - uint32_t stat_etherc; - - /* Clear the interrupt request flag */ - stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ - ETHEREESR0 = stat_edmac; - /* Reception-related */ - if (stat_edmac & EDMAC_EESIPR_INI_RECV) { - if (p_recv_cb_fnc != NULL) { - p_recv_cb_fnc(); - } - } - /* E-MAC-related */ - if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { - /* Clear the interrupt request flag */ - stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ - ETHERECSR0 = stat_etherc; - } -} - -static void lan_reg_reset(void) { - volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ - - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - while (j--) { - /* Do Nothing */ - } - - ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ - ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ - - /* Check clear software reset */ - while ((ETHEREDMR0 & 0x00000003) != 0) { - /* Do Nothing */ - } -} - -static void lan_desc_create(void) { - int32_t i; - uint8_t *p_memory_top; - - (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory)); - p_memory_top = ethernet_nc_memory; - - /* Descriptor area configuration */ - p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); - p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); - - /* Transmit descriptor */ - for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { - p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ - p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ - } - p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ - - /* Receive descriptor */ - for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { - p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ - p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ - } - p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ - - /* Initialize descriptor management information */ - send_top_index = 0; - recv_top_index = 0; - rx_read_offset = 0; - tx_wite_offset = 0; - p_recv_end_desc = NULL; -} - -static void lan_reg_set(int32_t link) { - /* MAC address setting */ - ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24) - | ((uint32_t)mac_addr[1] << 16) - | ((uint32_t)mac_addr[2] << 8) - | (uint32_t)mac_addr[3]; - ETHERMALR0 = ((uint32_t)mac_addr[4] << 8) - | (uint32_t)mac_addr[5]; - - /* E-DMAC */ - ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; - ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; - ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ - ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ - ETHEREDMR0 |= 0x00000040; /* Little endian */ - ETHERTRSCER0 &= ~0x0003009F; /* All clear */ - ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ - ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ - ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ - ETHERFCFTR0 &= ~0x001F00FF; - ETHERFCFTR0 |= 0x00070007; - ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ - - /* E-MAC */ - ETHERECMR0 &= ~0x04BF2063; /* All clear */ - ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ - ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ - ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ - ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ - ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ - if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { - ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ - } else { - ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ - } - - /* Interrupt-related */ - if (p_recv_cb_fnc != NULL) { - ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ - ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ - ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ - ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ - InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ - GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ - GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ - } - - ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ - - /* Enable transmission/reception */ - if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { - ETHEREDRRR0 |= 0x00000001; /* RR */ - } -} - -static uint16_t phy_reg_read(uint16_t reg_addr) { - uint16_t data; - - mii_preamble(); - mii_cmd(reg_addr, PHY_READ); - mii_z(); - mii_reg_read(&data); - mii_z(); - - return data; -} - -static void phy_reg_write(uint16_t reg_addr, uint16_t data) { - mii_preamble(); - mii_cmd(reg_addr, PHY_WRITE); - mii_write_1(); - mii_write_0(); - mii_reg_write(data); - mii_z(); -} - -static void mii_preamble(void) { - int32_t i = 32; - - for (i = 32; i > 0; i--) { - /* 1 is output via the MII (Media Independent Interface) block. */ - mii_write_1(); - } -} - -static void mii_cmd(uint16_t reg_addr, uint32_t option) { - int32_t i; - uint16_t data = 0; - - data |= (PHY_ST << 14); /* ST code */ - data |= (option << 12); /* OP code */ - data |= (PHY_ADDR << 7); /* PHY Address */ - data |= (uint16_t)(reg_addr << 2); /* Reg Address */ - for (i = 14; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_reg_read(uint16_t *data) { - int32_t i; - uint16_t reg_data = 0; - - /* Data are read in one bit at a time */ - for (i = 16; i > 0; i--) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - reg_data <<= 1; - reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); - } - *data = reg_data; -} - -static void mii_reg_write(uint16_t data) { - int32_t i; - - /* Data are written one bit at a time */ - for (i = 16; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_z(void) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); -} - -static void mii_write_1(void) { - set_ether_pir(PIR0_MDO | PIR0_MMD); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD); -} - -static void mii_write_0(void) { - set_ether_pir(PIR0_MMD); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD); -} - -static void set_ether_pir(uint32_t set_data) { - int32_t i; - - for (i = MDC_WAIT; i > 0; i--) { - ETHERPIR0 = set_data; - } -} - -static void wait_100us(int32_t wait_cnt) { - volatile int32_t j = LOOP_100us * wait_cnt; - - while (--j) { - /* Do Nothing */ - } -} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h deleted file mode 100644 index 18dfa2109e3..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h +++ /dev/null @@ -1,20 +0,0 @@ - -/* PHY link mode */ -#define NEGO_FAIL (0) -#define HALF_10M (1) -#define FULL_10M (2) -#define HALF_TX (3) -#define FULL_TX (4) - -typedef void (ethernetext_cb_fnc)(void); - -typedef struct tag_ethernet_cfg { - int int_priority; - ethernetext_cb_fnc *recv_cb; - char *ether_mac; -} ethernet_cfg_t; - -extern int ethernetext_init(ethernet_cfg_t *p_ethcfg); -extern void ethernetext_start_stop(int32_t mode); -extern int ethernetext_chk_link_mode(void); -extern void ethernetext_set_link_mode(int32_t link); diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h deleted file mode 100644 index 3865c03ec21..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __GPIO_ADDRDEFINE__ -#define __GPIO_ADDRDEFINE__ - -#define GPIO_BASE ((long)0xFCFE3000uL) /* GPIO */ - -#define PORT(n) (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4)) -#define PSR(n) (volatile unsigned long *)(GPIO_BASE + 0x100 + ((n)*4)) -#define PPR(n) (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4)) -#define PM(n) (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4)) -#define PMC(n) (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4)) -#define PFC(n) (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4)) -#define PFCE(n) (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4)) -#define PNOT(n) (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4)) -#define PMSR(n) (volatile unsigned long *)(GPIO_BASE + 0x800 + ((n)*4)) -#define PMCSR(n) (volatile unsigned long *)(GPIO_BASE + 0x900 + ((n)*4)) -#define PFCAE(n) (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4)) -#define PIBC(n) (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4)) -#define PBDC(n) (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4)) -#define PIPC(n) (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4)) - -#endif/*__GPIO_ADDRDEFINE__*/ - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c deleted file mode 100644 index d6be236949b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c +++ /dev/null @@ -1,223 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "gpio_irq_api.h" -#include "intc_iodefine.h" -#include "pinmap.h" -#include "cmsis.h" -#include "gpio_addrdefine.h" - -#define CHANNEL_NUM 8 - -static void gpio_irq0(void); -static void gpio_irq1(void); -static void gpio_irq2(void); -static void gpio_irq3(void); -static void gpio_irq4(void); -static void gpio_irq5(void); -static void gpio_irq6(void); -static void gpio_irq7(void); - -static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL}; -static gpio_irq_handler irq_handler; -static const int nIRQn_h = 32; -extern PinName gpio_multi_guard; - -enum { - IRQ0,IRQ1, - IRQ2,IRQ3, - IRQ4,IRQ5, - IRQ6,IRQ7, - -} IRQNo; - -static const IRQHandler irq_tbl[CHANNEL_NUM] = { - &gpio_irq0, - &gpio_irq1, - &gpio_irq2, - &gpio_irq3, - &gpio_irq4, - &gpio_irq5, - &gpio_irq6, - &gpio_irq7, -}; - -#ifdef MAX_PERI -static const PinMap PinMap_IRQ[] = { - {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, - {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, - {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, - {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, - {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, - {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, - {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, - {NC, NC, 0} -}; -#else -static const PinMap PinMap_IRQ[] = { - {P9_1, IRQ0, 4}, - {P7_8, IRQ1, 8}, - {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, - {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, - {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, - {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, - {NC, NC, 0} -}; -#endif - -static void handle_interrupt_in(int irq_num) { - uint16_t irqs; - uint16_t edge_req; - gpio_irq_t *obj; - gpio_irq_event irq_event; - - irqs = INTCIRQRR; - if (irqs & (1 << irq_num)) { - obj = channel_obj[irq_num]; - if (obj != NULL) { - edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3); - if (edge_req == 1) { - irq_event = IRQ_FALL; - } else if (edge_req == 2) { - irq_event = IRQ_RISE; - } else { - uint32_t mask = (1 << (obj->pin & 0x0F)); - __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin)); - - if ((*reg_in & mask) == 0) { - irq_event = IRQ_FALL; - } else { - irq_event = IRQ_RISE; - } - } - irq_handler(obj->port, irq_event); - } - INTCIRQRR &= ~(1 << irq_num); - } -} - -static void gpio_irq0(void) { - handle_interrupt_in(0); -} - -static void gpio_irq1(void) { - handle_interrupt_in(1); -} - -static void gpio_irq2(void) { - handle_interrupt_in(2); -} - -static void gpio_irq3(void) { - handle_interrupt_in(3); -} - -static void gpio_irq4(void) { - handle_interrupt_in(4); -} - -static void gpio_irq5(void) { - handle_interrupt_in(5); -} - -static void gpio_irq6(void) { - handle_interrupt_in(6); -} - -static void gpio_irq7(void) { - handle_interrupt_in(7); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - int shift; - if (pin == NC) return -1; - - obj->ch = pinmap_peripheral(pin, PinMap_IRQ); - obj->pin = (int)pin ; - obj->port = (int)id ; - - shift = obj->ch*2; - channel_obj[obj->ch] = obj; - irq_handler = handler; - - pinmap_pinout(pin, PinMap_IRQ); - gpio_multi_guard = pin; /* Set multi guard */ - - // INTC settings - InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]); - INTCICR1 &= ~(0x3 << shift); - INTCICR1 |= (0x3 << shift); - GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); - GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); - obj->int_enable = 1; - __enable_irq(); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_obj[obj->ch] = NULL; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - int shift = obj->ch*2; - uint16_t val = event == IRQ_RISE ? 2 : - event == IRQ_FALL ? 1 : 0; - uint16_t work_icr_val; - - /* check edge interrupt setting */ - work_icr_val = INTCICR1; - if (enable == 1) { - /* Set interrupt serect */ - work_icr_val |= (val << shift); - } else { - /* Clear interrupt serect */ - work_icr_val &= ~(val << shift); - } - - if ((work_icr_val & (3 << shift)) == 0) { - /* No edge interrupt setting */ - GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); - /* Clear Interrupt flags */ - INTCIRQRR &= ~(1 << obj->ch); - INTCICR1 = work_icr_val; - } else if (obj->int_enable == 1) { - INTCICR1 = work_icr_val; - GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); - } else { - INTCICR1 = work_icr_val; - } -} - -void gpio_irq_enable(gpio_irq_t *obj) { - int shift = obj->ch*2; - uint16_t work_icr_val = INTCICR1; - - /* check edge interrupt setting */ - if ((work_icr_val & (3 << shift)) != 0) { - GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); - } - obj->int_enable = 1; -} - -void gpio_irq_disable(gpio_irq_t *obj) { - GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); - obj->int_enable = 0; -} - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c deleted file mode 100644 index 4904faa978f..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c +++ /dev/null @@ -1,760 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "r_typedefs.h" - -#include "riic_iodefine.h" -#include "RZ_A1_Init.h" -#include "VKRZA1H.h" - -volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; - -#define REG(N) \ - RIIC[obj->i2c]->RIICn##N - -/* RIICnCR1 */ -#define CR1_RST (1 << 6) -#define CR1_ICE (1 << 7) - -/* RIICnCR2 */ -#define CR2_ST (1 << 1) -#define CR2_RS (1 << 2) -#define CR2_SP (1 << 3) -#define CR2_TRS (1 << 5) -#define CR2_BBSY (1 << 7) - -/* RIICnMR3 */ -#define MR3_ACKBT (1 << 3) -#define MR3_ACKWP (1 << 4) -#define MR3_WAIT (1 << 6) - -/* RIICnSER */ -#define SER_SAR0E (1 << 0) - -/* RIICnSR1 */ -#define SR1_AAS0 (1 << 0) - -/* RIICnSR2 */ -#define SR2_START (1 << 2) -#define SR2_STOP (1 << 3) -#define SR2_NACKF (1 << 4) -#define SR2_RDRF (1 << 5) -#define SR2_TEND (1 << 6) -#define SR2_TDRE (1 << 7) - -#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ - -static const PinMap PinMap_I2C_SDA[] = { - {P1_1 , I2C_0, 1}, - {P1_3 , I2C_1, 1}, - {P1_5 , I2C_2, 1}, - {P1_7 , I2C_3, 1}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {P1_0 , I2C_0, 1}, - {P1_2 , I2C_1, 1}, - {P1_4 , I2C_2, 1}, - {P1_6 , I2C_3, 1}, - {NC , NC, 0} -}; - - -static inline int i2c_status(i2c_t *obj) { - return REG(SR2.UINT8[0]); -} - -static void i2c_reg_reset(i2c_t *obj) { - /* full reset */ - REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off - REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on - REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on - - REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack) - REG(SER.UINT8[0]) = 0x00; // no slave addr enabled - - /* set frequency */ - REG(MR1.UINT8[0]) |= obj->pclk_bit; - REG(BRL.UINT8[0]) = obj->width_low; - REG(BRH.UINT8[0]) = obj->width_hi; - - REG(MR2.UINT8[0]) = 0x07; - REG(MR3.UINT8[0]) = 0x00; - - REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT - REG(IER.UINT8[0]) = 0x00; // no interrupt - - REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset -} - -static inline int i2c_wait_RDRF(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_RDRF) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_wait_TDRE(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_TDRE) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_wait_TEND(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_TEND) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - - -static int i2c_wait_START(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_START) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_wait_STOP(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_STOP) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_set_STOP(i2c_t *obj) { - /* SR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - /* Stop condition */ - REG(CR2.UINT32) |= CR2_SP; - - return 0; -} - -static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { - /* SR2.NACKF = 0 */ - REG(SR2.UINT32) &= ~SR2_NACKF; - /* SR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; -} - -static void i2c_set_MR3_NACK(i2c_t *obj) { - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; -} - -static void i2c_set_MR3_ACK(i2c_t *obj) { - /* send a ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) &= ~MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; -} - -static inline void i2c_power_enable(i2c_t *obj) { - volatile uint8_t dummy; - switch ((int)obj->i2c) { - case I2C_0: - CPGSTBCR9 &= ~(0x80); - break; - case I2C_1: - CPGSTBCR9 &= ~(0x40); - break; - case I2C_2: - CPGSTBCR9 &= ~(0x20); - break; - case I2C_3: - CPGSTBCR9 &= ~(0x10); - break; - } - dummy = CPGSTBCR9; -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - /* determine the I2C to use */ - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); - - /* enable power */ - i2c_power_enable(obj); - - /* set default frequency at 100k */ - i2c_frequency(obj, 100000); - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - obj->last_stop_flag = 1; -} - -inline int i2c_start(i2c_t *obj) { - int timeout = 0; - - while ((REG(CR2.UINT32) & CR2_BBSY) != 0) { - timeout ++; - if (timeout >= obj->bbsy_wait_cnt) { - break; - } - } - /* Start Condition */ - REG(CR2.UINT8[0]) |= CR2_ST; - - return 0; -} - -static inline int i2c_restart(i2c_t *obj) { - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - /* ReStart condition */ - REG(CR2.UINT32) |= CR2_RS; - - return 0; -} - -inline int i2c_stop(i2c_t *obj) { - (void)i2c_set_STOP(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - - return 0; -} - -static void i2c_set_err_noslave(i2c_t *obj) { - (void)i2c_set_STOP(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - obj->last_stop_flag = 1; -} - -static inline int i2c_do_write(i2c_t *obj, int value) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_TDRE) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - /* write the data */ - REG(DRT.UINT32) = value; - - return 0; -} - -static inline int i2c_read_address_write(i2c_t *obj, int value) { - int status; - - status = i2c_wait_TDRE(obj); - if (status == 0) { - /* write the data */ - REG(DRT.UINT32) = value; - } - - return status; - -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - if (last == 2) { - /* this time is befor last byte read */ - /* Set MR3 WAIT bit is 1 */; - REG(MR3.UINT32) |= MR3_WAIT; - } else if (last == 1) { - i2c_set_MR3_NACK(obj); - } else { - i2c_set_MR3_ACK(obj); - } - - /* return the data */ - return (REG(DRR.UINT32) & 0xFF); -} - -void i2c_frequency(i2c_t *obj, int hz) { - float64_t pclk_val; - float64_t wait_utime; - volatile float64_t bps; - volatile float64_t L_time; /* H Width period */ - volatile float64_t H_time; /* L Width period */ - uint32_t tmp_L_width; - uint32_t tmp_H_width; - uint32_t remainder; - uint32_t wk_cks = 0; - - /* set PCLK */ - if (false == RZ_A1_IsClockMode0()) { - pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK; - } else { - pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK; - } - - /* Min 10kHz, Max 400kHz */ - if (hz < 10000) { - bps = 10000; - } else if (hz > 400000) { - bps = 400000; - } else { - bps = (float64_t)hz; - } - - /* Calculation L width time */ - L_time = (1 / (2 * bps)); /* Harf period of frequency */ - H_time = L_time; - - /* Check I2C mode of Speed */ - if (bps > 100000) { - /* Fast-mode */ - L_time -= 102E-9; /* Falling time of SCL clock. */ - H_time -= 138E-9; /* Rising time of SCL clock. */ - /* Check L wideth */ - if (L_time < 1.3E-6) { - /* Wnen L width less than 1.3us */ - /* Subtract Rise up and down time for SCL from H/L width */ - L_time = 1.3E-6; - H_time = (1 / bps) - L_time - 138E-9 - 102E-9; - } - } - - tmp_L_width = (uint32_t)(L_time * pclk_val * 10); - tmp_L_width >>= 1; - wk_cks++; - while (tmp_L_width >= 341) { - tmp_L_width >>= 1; - wk_cks++; - } - remainder = tmp_L_width % 10; - tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */ - - tmp_H_width = (uint32_t)(H_time * pclk_val * 10); - tmp_H_width >>= wk_cks; - if (remainder == 0) { - tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */ - } else { - remainder += tmp_H_width % 10; - tmp_H_width = (tmp_H_width / 10) - 3; - if (remainder > 10) { - tmp_H_width += 1; /* fine adjustment */ - } - } - /* timeout of BBSY bit is minimum low width by frequency */ - /* so timeout calculates "(low width) * 2" by frequency */ - wait_utime = (L_time * 2) * 1000000; - /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ - if (wait_utime <= 0.3) { - obj->bbsy_wait_cnt = 1; - } else { - obj->bbsy_wait_cnt = (int)(wait_utime / 0.3); - } - - - /* I2C Rate */ - obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ - obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0); - obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0); - - /* full reset */ - i2c_reg_reset(obj); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count = 0; - int status; - int value; - volatile uint32_t work_reg = 0; - - i2c_set_MR3_ACK(obj); - /* There is a STOP condition for last processing */ - if (obj->last_stop_flag != 0) { - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; - } - } - obj->last_stop_flag = stop; - /* Send Slave address */ - status = i2c_read_address_write(obj, (address | 0x01)); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* wait RDRF */ - status = i2c_wait_RDRF(obj); - /* check ACK/NACK */ - if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { - /* Slave sends NACK */ - (void)i2c_set_STOP(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - obj->last_stop_flag = 1; - return I2C_ERROR_NO_SLAVE; - } - if (length != 0) { - /* Read in all except last byte */ - if (length > 2) { - /* dummy read */ - value = REG(DRR.UINT32); - for (count = 0; count < (length - 1); count++) { - /* wait for it to arrive */ - status = i2c_wait_RDRF(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* Recieve the data */ - if (count == (length - 2)) { - value = i2c_do_read(obj, 1); - } else if ((length >= 3) && (count == (length - 3))) { - value = i2c_do_read(obj, 2); - } else { - value = i2c_do_read(obj, 0); - } - data[count] = (char)value; - } - } else if (length == 2) { - /* Set MR3 WAIT bit is 1 */ - REG(MR3.UINT32) |= MR3_WAIT; - /* dummy read */ - value = REG(DRR.UINT32); - /* wait for it to arrive */ - status = i2c_wait_RDRF(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - i2c_set_MR3_NACK(obj); - data[count] = (char)REG(DRR.UINT32); - count++; - } else { - /* length == 1 */ - /* Set MR3 WAIT bit is 1 */; - REG(MR3.UINT32) |= MR3_WAIT; - i2c_set_MR3_NACK(obj); - /* dummy read */ - value = REG(DRR.UINT32); - } - /* wait for it to arrive */ - status = i2c_wait_RDRF(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - - /* If not repeated start, send stop. */ - if (stop) { - (void)i2c_set_STOP(obj); - /* RIICnDRR read */ - value = (REG(DRR.UINT32) & 0xFF); - data[count] = (char)value; - /* RIICnMR3.WAIT = 0 */ - REG(MR3.UINT32) &= ~MR3_WAIT; - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - /* RIICnDRR read */ - value = (REG(DRR.UINT32) & 0xFF); - data[count] = (char)value; - /* RIICnMR3.WAIT = 0 */ - REG(MR3.UINT32) &= ~MR3_WAIT; - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } - } else { - /* If not repeated start, send stop. */ - if (stop) { - (void)i2c_set_STOP(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int cnt; - int status; - - /* There is a STOP condition for last processing */ - if (obj->last_stop_flag != 0) { - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; - } - } - obj->last_stop_flag = stop; - /* Send Slave address */ - status = i2c_do_write(obj, address); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* Wait send end */ - status = i2c_wait_TEND(obj); - if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { - /* Slave sends NACK */ - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* Send Write data */ - for (cnt=0; cnt= WAIT_TIMEOUT) { - return ack; - } - } - /* check ACK/NACK */ - if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { - /* NACK */ - i2c_set_SR2_NACKF_STOP(obj); - } else { - ack = 1; - } - } - - return ack; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - if (enable_slave != 0) { - REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled - } else { - REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled - } -} - -int i2c_slave_receive(i2c_t *obj) { - int status; - int retval; - - status = (REG(SR1.UINT8[0]) & SR1_AAS0); - status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4; - - switch(status) { - case 0x01: - /* the master is writing to this slave */ - retval = 3; - break; - case 0x02: - /* the master is writing to all slave */ - retval = 2; - break; - case 0x03: - /* the master has requested a read from this slave */ - retval = 1; - break; - default : - /* no data */ - retval = 0; - break; - } - - return retval; -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) { - int timeout = 0; - int count; - int break_flg = 0; - - if(length <= 0) { - return 0; - } - for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) { - if ((i2c_status(obj) & SR2_STOP) != 0) { - break_flg = 1; - break; - } - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - if (break_flg == 0) { - if (count == 0) { - /* dummy read */ - (void)REG(DRR.UINT32); - } else { - data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); - } - } - } - if (break_flg == 0) { - (void)i2c_wait_STOP(obj); - } else { - if ((i2c_status(obj) & SR2_RDRF) != 0) { - if (count <= 1) { - /* fail safe */ - /* dummy read */ - (void)REG(DRR.UINT32); - } else { - data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); - } - } - } - /* SR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - - return (count - 1); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int count = 0; - int status = 0; - - if(length <= 0) { - return 0; - } - - while ((count < length) && (status == 0)) { - status = i2c_do_write(obj, data[count]); - if(status == 0) { - /* Wait send end */ - status = i2c_wait_TEND(obj); - if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) { - /* NACK */ - break; - } - } - count++; - } - /* dummy read */ - (void)REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - - return count; -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - REG(SAR0.UINT32) = (address & 0xfffffffe); -} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c deleted file mode 100644 index 22bb560902a..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c +++ /dev/null @@ -1,192 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_addrdefine.h" - -PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ - -typedef struct { - PinName pin; - int function; - int pm; -} PinFunc; - -#ifdef MAX_PERI -static const PinFunc PIPC_0_tbl[] = { -// pin func pm - {P4_0 , 2 , -1}, /* TIOC0A */ - {P5_0 , 6 , -1}, /* TIOC0A */ - {P7_0 , 7 , -1}, /* TIOC0A */ - {P4_1 , 2 , -1}, /* TIOC0B */ - {P5_1 , 6 , -1}, /* TIOC0B */ - {P7_1 , 7 , -1}, /* TIOC0B */ - {P4_2 , 2 , -1}, /* TIOC0C */ - {P5_5 , 6 , -1}, /* TIOC0C */ - {P7_2 , 7 , -1}, /* TIOC0C */ - {P4_3 , 2 , -1}, /* TIOC0D */ - {P5_7 , 6 , -1}, /* TIOC0D */ - {P7_3 , 7 , -1}, /* TIOC0D */ - {P2_11 , 5 , -1}, /* TIOC1A */ - {P6_0 , 5 , -1}, /* TIOC1A */ - {P7_4 , 7 , -1}, /* TIOC1A */ - {P8_8 , 5 , -1}, /* TIOC1A */ - {P9_7 , 4 , -1}, /* TIOC1A */ - {P2_12 , 8 , -1}, /* TIOC1B */ - {P5_2 , 6 , -1}, /* TIOC1B */ - {P6_1 , 5 , -1}, /* TIOC1B */ - {P7_5 , 7 , -1}, /* TIOC1B */ - {P8_9 , 5 , -1}, /* TIOC1B */ - {P2_1 , 6 , -1}, /* TIOC2A */ - {P6_2 , 6 , -1}, /* TIOC2A */ - {P7_6 , 7 , -1}, /* TIOC2A */ - {P8_14 , 4 , -1}, /* TIOC2A */ - {P2_2 , 6 , -1}, /* TIOC2B */ - {P6_3 , 6 , -1}, /* TIOC2B */ - {P7_7 , 7 , -1}, /* TIOC2B */ - {P8_15 , 4 , -1}, /* TIOC2B */ - {P3_4 , 6 , -1}, /* TIOC3A */ - {P7_8 , 7 , -1}, /* TIOC3A */ - {P8_10 , 4 , -1}, /* TIOC3A */ - {P3_5 , 6 , -1}, /* TIOC3B */ - {P7_9 , 7 , -1}, /* TIOC3B */ - {P8_11 , 4 , -1}, /* TIOC3B */ - {P3_6 , 6 , -1}, /* TIOC3C */ - {P5_3 , 6 , -1}, /* TIOC3C */ - {P7_10 , 7 , -1}, /* TIOC3C */ - {P8_12 , 4 , -1}, /* TIOC3C */ - {P3_7 , 6 , -1}, /* TIOC3D */ - {P5_4 , 6 , -1}, /* TIOC3D */ - {P7_11 , 7 , -1}, /* TIOC3D */ - {P8_13 , 4 , -1}, /* TIOC3D */ - {P3_8 , 6 , -1}, /* TIOC4A */ - {P4_4 , 3 , -1}, /* TIOC4A */ - {P7_12 , 7 , -1}, /* TIOC4A */ - {P3_9 , 6 , -1}, /* TIOC4B */ - {P4_5 , 3 , -1}, /* TIOC4B */ - {P7_13 , 7 , -1}, /* TIOC4B */ - {P3_10 , 6 , -1}, /* TIOC4C */ - {P4_6 , 3 , -1}, /* TIOC4C */ - {P7_14 , 7 , -1}, /* TIOC4C */ - {P3_11 , 6 , -1}, /* TIOC4D */ - {P4_7 , 3 , -1}, /* TIOC4D */ - {P7_15 , 7 , -1}, /* TIOC4D */ - {P5_7 , 1 , 1 }, /* TXOUT0M */ - {P5_6 , 1 , 1 }, /* TXOUT0P */ - {P5_5 , 1 , 1 }, /* TXOUT1M */ - {P5_4 , 1 , 1 }, /* TXOUT1P */ - {P5_3 , 1 , 1 }, /* TXOUT2M */ - {P5_2 , 1 , 1 }, /* TXOUT2P */ - {P5_1 , 1 , 1 }, /* TXCLKOUTM */ - {P5_0 , 1 , 1 }, /* TXCLKOUTP */ - {P2_11 , 4 , 0 }, /* SSITxD0 */ - {P4_7 , 5 , 0 }, /* SSITxD0 */ - {P7_4 , 6 , 0 }, /* SSITxD1 */ - {P4_15 , 6 , 0 }, /* SSITxD3 */ - {P7_11 , 2 , 0 }, /* SSITxD3 */ - {P2_7 , 4 , 0 }, /* SSITxD5 */ - {P4_11 , 5 , 0 }, /* SSITxD5 */ - {P8_10 , 8 , 0 }, /* SSITxD5 */ - {P3_7 , 8 , 0 }, /* WDTOVF */ - {NC , 0 , -1} -}; -#else -static const PinFunc PIPC_0_tbl[] = { - // pin func pm - {P4_0 , 2 , -1}, // TIOC0A - {P5_0 , 6 , -1}, // TIOC0A - {P4_2 , 2 , -1}, // TIOC0C - {P5_5 , 6 , -1}, // TIOC0C - // - {P8_14 , 4 , -1}, // TIOC2A - // - {P8_10 , 4 , -1}, // TIOC3A - {P5_3 , 6 , -1}, // TIOC3C - {P8_12 , 4 , -1}, // TIOC3C - // - {P3_8 , 6 , -1}, // TIOC4A - {P4_4 , 3 , -1}, // TIOC4A - {P3_10 , 6 , -1}, // TIOC4C - {P4_6 , 3 , -1}, // TIOC4C - // - {P5_7 , 1 , 1 }, // TXOUT0M - {P5_6 , 1 , 1 }, // TXOUT0P - {P5_5 , 1 , 1 }, // TXOUT1M - {P5_4 , 1 , 1 }, // TXOUT1P - {P5_3 , 1 , 1 }, // TXOUT2M - {P5_2 , 1 , 1 }, // TXOUT2P - {P5_1 , 1 , 1 }, // TXCLKOUTM - {P5_0 , 1 , 1 }, // TXCLKOUTP - {P4_7 , 5 , 0 }, // SSITxD0 - {P8_10 , 8 , 0 }, // SSITxD5 - {P3_7 , 8 , 0 }, // WDTOVF - {NC , 0 , -1} -}; -#endif - -void pin_function(PinName pin, int function) { - if (pin == (PinName)NC) return; - - int n = pin >> 4; - int bitmask = 1<<(pin & 0xf); - const PinFunc * Pipc_0_func = PIPC_0_tbl; - int pipc_data = 1; - - if (gpio_multi_guard != pin) { - if (function == 0) { - // means GPIO mode - *PMC(n) &= ~bitmask; - } else { - // alt-function mode - --function; - - if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} - if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} - if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} - - while (Pipc_0_func->pin != NC) { - if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { - pipc_data = 0; - if (Pipc_0_func->pm == 0) { - *PMSR(n) = (bitmask << 16) | 0; - } else if (Pipc_0_func->pm == 1) { - *PMSR(n) = (bitmask << 16) | bitmask; - } else { - // Do Nothing - } - break; - } - Pipc_0_func++; - } - if (pipc_data == 1) { - *PIPC(n) |= bitmask; - } else { - *PIPC(n) &= ~bitmask; - } - - if (P1_0 <= pin && pin <= P1_7 && function == 0) { - *PBDC(n) |= bitmask; - } - *PMC(n) |= bitmask; - } - } else { - gpio_multi_guard = (PinName)NC; - } -} - -void pin_mode(PinName pin, PinMode mode) { -// if (pin == (PinName)NC) { return; } -} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c deleted file mode 100644 index 522290cd876..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c +++ /dev/null @@ -1,700 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "RZ_A1_Init.h" -#include "cpg_iodefine.h" -#include "pwm_iodefine.h" -#include "gpio_addrdefine.h" - -#ifdef MAX_PERI -#define MTU2_PWM_NUM 27 -#define MTU2_PWM_SIGNAL 2 -#define MTU2_PWM_OFFSET 0x20 - -// PORT ID, PWM ID, Pin function -static const PinMap PinMap_PWM[] = { - // TIOC0 A,C - {P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A - {P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A - {P7_0 , MTU2_PWM2_PIN , 7}, //TIOC0A - {P4_2 , MTU2_PWM3_PIN , 2}, //TIOC0C - {P5_5 , MTU2_PWM4_PIN , 6}, //TIOC0C - {P7_2 , MTU2_PWM5_PIN , 7}, //TIOC0C - //TIOC1 A - {P2_11 , MTU2_PWM6_PIN , 5}, //TIOC1A - {P6_0 , MTU2_PWM7_PIN , 5}, //TIOC1A - {P7_4 , MTU2_PWM8_PIN , 7}, //TIOC1A - {P8_8 , MTU2_PWM9_PIN , 5}, //TIOC1A - {P9_7 , MTU2_PWM10_PIN , 4}, //TIOC1A - //TIOC2 A - {P2_1 , MTU2_PWM11_PIN , 6}, //TIOC2A - {P6_2 , MTU2_PWM12_PIN , 6}, //TIOC2A - {P7_6 , MTU2_PWM13_PIN , 7}, //TIOC2A - {P8_14 , MTU2_PWM14_PIN , 4}, //TIOC2A - //TIOC3 A,C - {P3_4 , MTU2_PWM15_PIN , 6}, //TIOC3A - {P7_8 , MTU2_PWM16_PIN , 7}, //TIOC3A - {P8_10 , MTU2_PWM17_PIN , 4}, //TIOC3A - {P3_6 , MTU2_PWM18_PIN , 6}, //TIOC3C - {P7_10 , MTU2_PWM19_PIN , 7}, //TIOC3C - {P8_12 , MTU2_PWM20_PIN , 4}, //TIOC3C - //TIOC4 A,C - {P3_8 , MTU2_PWM21_PIN , 6}, //TIOC4A - {P4_4 , MTU2_PWM22_PIN , 3}, //TIOC4A - {P7_12 , MTU2_PWM23_PIN , 7}, //TIOC4A - {P3_10 , MTU2_PWM24_PIN , 6}, //TIOC4C - {P4_6 , MTU2_PWM25_PIN , 3}, //TIOC4C - {P7_14 , MTU2_PWM26_PIN , 7}, //TIOC4C - //PWM1 - {P8_8 , PWM0_PIN , 6}, //PWM1A - {P8_9 , PWM1_PIN , 6}, //PWM1B - {P8_10 , PWM2_PIN , 6}, //PWM1C - {P8_11 , PWM3_PIN , 6}, //PWM1D - {P8_12 , PWM4_PIN , 6}, //PWM1E - {P8_13 , PWM5_PIN , 6}, //PWM1F - {P8_14 , PWM6_PIN , 6}, //PWM1G - {P8_15 , PWM7_PIN , 6}, //PWM1H - //PWM2 - {P3_0 , PWM8_PIN , 7}, //PWM2A - {P3_1 , PWM9_PIN , 7}, //PWM2B - {P3_2 , PWM10_PIN , 7}, //PWM2C - {P3_3 , PWM11_PIN , 7}, //PWM2D - {P4_4 , PWM12_PIN , 4}, //PWM2E - {P4_5 , PWM13_PIN , 4}, //PWM2F - {P4_6 , PWM14_PIN , 4}, //PWM2G - {P4_7 , PWM15_PIN , 4}, //PWM2H - {NC , NC , 0} -}; - -static const PWMType PORT[] = { - PWM1A, // PWM0_PIN - PWM1B, // PWM1_PIN - PWM1C, // PWM2_PIN - PWM1D, // PWM3_PIN - PWM1E, // PWM4_PIN - PWM1F, // PWM5_PIN - PWM1G, // PWM6_PIN - PWM1H, // PWM7_PIN - PWM2A, // PWM8_PIN - PWM2B, // PWM9_PIN - PWM2C, // PWM10_PIN - PWM2D, // PWM11_PIN - PWM2E, // PWM12_PIN - PWM2F, // PWM13_PIN - PWM2G, // PWM14_PIN - PWM2H, // PWM15_PIN -}; - -static const MTU2_PWMType MTU2_PORT[] = { - TIOC0A, // MTU2_PWM0_PIN - TIOC0A, // MTU2_PWM1_PIN - TIOC0A, // MTU2_PWM2_PIN - TIOC0C, // MTU2_PWM3_PIN - TIOC0C, // MTU2_PWM4_PIN - TIOC0C, // MTU2_PWM5_PIN - TIOC1A, // MTU2_PWM6_PIN - TIOC1A, // MTU2_PWM7_PIN - TIOC1A, // MTU2_PWM8_PIN - TIOC1A, // MTU2_PWM9_PIN - TIOC1A, // MTU2_PWM10_PIN - TIOC2A, // MTU2_PWM11_PIN - TIOC2A, // MTU2_PWM12_PIN - TIOC2A, // MTU2_PWM13_PIN - TIOC2A, // MTU2_PWM14_PIN - TIOC3A, // MTU2_PWM15_PIN - TIOC3A, // MTU2_PWM16_PIN - TIOC3A, // MTU2_PWM17_PIN - TIOC3C, // MTU2_PWM18_PIN - TIOC3C, // MTU2_PWM19_PIN - TIOC3C, // MTU2_PWM20_PIN - TIOC4A, // MTU2_PWM21_PIN - TIOC4A, // MTU2_PWM22_PIN - TIOC4A, // MTU2_PWM23_PIN - TIOC4C, // MTU2_PWM24_PIN - TIOC4C, // MTU2_PWM25_PIN - TIOC4C, // MTU2_PWM26_PIN -}; - -static __IO uint16_t *PWM_MATCH[] = { - &PWMPWBFR_1A, // PWM0_PIN - &PWMPWBFR_1A, // PWM1_PIN - &PWMPWBFR_1C, // PWM2_PIN - &PWMPWBFR_1C, // PWM3_PIN - &PWMPWBFR_1E, // PWM4_PIN - &PWMPWBFR_1E, // PWM5_PIN - &PWMPWBFR_1G, // PWM6_PIN - &PWMPWBFR_1G, // PWM7_PIN - &PWMPWBFR_2A, // PWM8_PIN - &PWMPWBFR_2A, // PWM9_PIN - &PWMPWBFR_2C, // PWM10_PIN - &PWMPWBFR_2C, // PWM11_PIN - &PWMPWBFR_2E, // PWM12_PIN - &PWMPWBFR_2E, // PWM13_PIN - &PWMPWBFR_2G, // PWM14_PIN - &PWMPWBFR_2G, // PWM15_PIN -}; - -static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { - { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM0_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM1_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM2_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM3_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM4_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM5_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM6_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM7_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM8_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM9_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM10_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM11_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM12_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM13_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM14_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM15_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM16_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM17_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM18_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM19_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM20_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM21_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM22_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM23_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM24_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM25_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM26_PIN -}; -#else -#define MTU2_PWM_NUM 12 -#define MTU2_PWM_SIGNAL 2 -#define MTU2_PWM_OFFSET 0x20 - -// PORT ID, PWM ID, Pin function -static const PinMap PinMap_PWM[] = { - //TIOC0 A,C - {P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A - {P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A - {P4_2 , MTU2_PWM2_PIN , 2}, //TIOC0C - {P5_5 , MTU2_PWM3_PIN , 6}, //TIOC0C - //TIOC2 A - {P8_14 , MTU2_PWM4_PIN , 4}, //TIOC2A - //TIOC3 A,C - {P8_10 , MTU2_PWM5_PIN , 4}, //TIOC3A - {P5_3 , MTU2_PWM6_PIN , 6}, //TIOC3C - {P8_12 , MTU2_PWM7_PIN , 4}, //TIOC3C - //TIOC4 A,C - {P3_8 , MTU2_PWM8_PIN , 6}, //TIOC4A - {P4_4 , MTU2_PWM9_PIN , 3}, //TIOC4A - {P3_10 , MTU2_PWM10_PIN , 6}, //TIOC4C - {P4_6 , MTU2_PWM11_PIN , 3}, //TIOC4C - //PWM1 - {P8_10 , PWM0_PIN , 6}, //PWM1C - {P8_11 , PWM1_PIN , 6}, //PWM1D - {P8_12 , PWM2_PIN , 6}, //PWM1E - {P8_13 , PWM3_PIN , 6}, //PWM1F - {P8_14 , PWM4_PIN , 6}, //PWM1G - {P8_15 , PWM5_PIN , 6}, //PWM1H - //PWM2 - {P3_0 , PWM6_PIN , 7}, //PWM2A - {P3_1 , PWM7_PIN , 7}, //PWM2B - {P3_2 , PWM8_PIN , 7}, //PWM2C - {P4_4 , PWM9_PIN , 4}, //PWM2E - {P4_5 , PWM10_PIN , 4}, //PWM2F - {P4_6 , PWM11_PIN , 4}, //PWM2G - {P4_7 , PWM12_PIN , 4}, //PWM2H - {NC , NC , 0} -}; - -static const PWMType PORT[] = { - PWM1C, // PWM0_PIN - PWM1D, // PWM1_PIN - PWM1E, // PWM2_PIN - PWM1F, // PWM3_PIN - PWM1G, // PWM4_PIN - PWM1H, // PWM5_PIN - PWM2A, // PWM6_PIN - PWM2B, // PWM7_PIN - PWM2C, // PWM8_PIN - PWM2E, // PWM9_PIN - PWM2F, // PWM10_PIN - PWM2G, // PWM11_PIN - PWM2H, // PWM12_PIN -}; - -static const MTU2_PWMType MTU2_PORT[] = { - TIOC0A, // MTU2_PWM0_PIN - TIOC0A, // MTU2_PWM1_PIN - TIOC0C, // MTU2_PWM2_PIN - TIOC0C, // MTU2_PWM3_PIN - TIOC2A, // MTU2_PWM4_PIN - TIOC3A, // MTU2_PWM5_PIN - TIOC3C, // MTU2_PWM6_PIN - TIOC3C, // MTU2_PWM7_PIN - TIOC4A, // MTU2_PWM8_PIN - TIOC4A, // MTU2_PWM9_PIN - TIOC4C, // MTU2_PWM10_PIN - TIOC4C, // MTU2_PWM11_PIN -}; - -static __IO uint16_t *PWM_MATCH[] = { - &PWMPWBFR_1C, // PWM0_PIN - &PWMPWBFR_1C, // PWM1_PIN - &PWMPWBFR_1E, // PWM2_PIN - &PWMPWBFR_1E, // PWM3_PIN - &PWMPWBFR_1G, // PWM4_PIN - &PWMPWBFR_1G, // PWM5_PIN - &PWMPWBFR_2A, // PWM6_PIN - &PWMPWBFR_2A, // PWM7_PIN - &PWMPWBFR_2C, // PWM8_PIN - &PWMPWBFR_2E, // PWM9_PIN - &PWMPWBFR_2E, // PWM10_PIN - &PWMPWBFR_2G, // PWM11_PIN - &PWMPWBFR_2G, // PWM12_PIN -}; - -static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM0_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM1_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM2_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM3_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM4_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM5_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM6_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM7_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM8_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM9_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM10_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM11_PIN -}; -#endif - - -static __IO uint8_t *TCR_MATCH[] = { - &MTU2TCR_0, - &MTU2TCR_1, - &MTU2TCR_2, - &MTU2TCR_3, - &MTU2TCR_4, -}; - -static __IO uint8_t *TIORH_MATCH[] = { - &MTU2TIORH_0, - &MTU2TIOR_1, - &MTU2TIOR_2, - &MTU2TIORH_3, - &MTU2TIORH_4, -}; - -static __IO uint8_t *TIORL_MATCH[] = { - &MTU2TIORL_0, - NULL, - NULL, - &MTU2TIORL_3, - &MTU2TIORL_4, -}; - -static __IO uint16_t *TGRA_MATCH[] = { - &MTU2TGRA_0, - &MTU2TGRA_1, - &MTU2TGRA_2, - &MTU2TGRA_3, - &MTU2TGRA_4, -}; - -static __IO uint16_t *TGRC_MATCH[] = { - &MTU2TGRC_0, - NULL, - NULL, - &MTU2TGRC_3, - &MTU2TGRC_4, -}; - -static __IO uint8_t *TMDR_MATCH[] = { - &MTU2TMDR_0, - &MTU2TMDR_1, - &MTU2TMDR_2, - &MTU2TMDR_3, - &MTU2TMDR_4, -}; - -static int MAX_PERIOD[] = { - 125000, - 503000, - 2000000, - 2000000, - 2000000, -}; - -typedef enum { - MODE_PWM = 0, - MODE_MTU2 -} PWMmode; - -typedef enum { - MTU2_PULSE = 0, - MTU2_PERIOD -} MTU2Signal; - -static int pwm_mode = MODE_PWM; -static uint16_t init_period_ch1 = 0; -static uint16_t init_period_ch2 = 0; -static uint16_t init_mtu2_period_ch[5] = {0}; -static int32_t period_ch1 = 1; -static int32_t period_ch2 = 1; -static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; - -void pwmout_init(pwmout_t* obj, PinName pin) { - // determine the channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - if (pwm >= MTU2_PWM_OFFSET) { - /* PWM by MTU2 */ - int tmp_pwm; - - pwm_mode = MODE_MTU2; - // power on - CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33); - - obj->pwm = pwm; - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) { - obj->ch = 4; - MTU2TOER |= 0x36; - } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) { - obj->ch = 3; - MTU2TOER |= 0x09; - } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) { - obj->ch = 2; - } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) { - obj->ch = 1; - } else { - obj->ch = 0; - } - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); - - int bitmask = 1 << (pin & 0xf); - - *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0; - - // default duty 0.0f - pwmout_write(obj, 0); - if (init_mtu2_period_ch[obj->ch] == 0) { - // default period 1ms - pwmout_period_us(obj, 1000); - init_mtu2_period_ch[obj->ch] = 1; - } - } else { - /* PWM */ - pwm_mode = MODE_PWM; - // power on - CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); - - obj->pwm = pwm; - if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) { - obj->ch = 2; - PWMPWPR_2_BYTE_L = 0x00; - } else { - obj->ch = 1; - PWMPWPR_1_BYTE_L = 0x00; - } - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); - - // default to 491us: standard for servos, and fine for e.g. brightness control - pwmout_write(obj, 0); - if ((obj->ch == 2) && (init_period_ch2 == 0)) { - pwmout_period_us(obj, 491); - init_period_ch2 = 1; - } - if ((obj->ch == 1) && (init_period_ch1 == 0)) { - pwmout_period_us(obj, 491); - init_period_ch1 = 1; - } - } -} - -void pwmout_free(pwmout_t* obj) { - pwmout_write(obj, 0); -} - -void pwmout_write(pwmout_t* obj, float value) { - uint32_t wk_cycle; - uint16_t v; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - int tmp_pwm; - - if (value < 0.0f) { - value = 0.0f; - } else if (value > 1.0f) { - value = 1.0f; - } else { - // Do Nothing - } - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; - // set channel match to percentage - *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); - } else { - /* PWM */ - if (value < 0.0f) { - value = 0.0f; - } else if (value > 1.0f) { - value = 1.0f; - } else { - // Do Nothing - } - - if (obj->ch == 2) { - wk_cycle = PWMPWCYR_2 & 0x03ff; - } else { - wk_cycle = PWMPWCYR_1 & 0x03ff; - } - - // set channel match to percentage - v = (uint16_t)((float)wk_cycle * value); - *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); - } -} - -float pwmout_read(pwmout_t* obj) { - uint32_t wk_cycle; - float value; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - uint32_t wk_pulse; - int tmp_pwm; - - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; - wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; - value = ((float)wk_pulse / (float)wk_cycle); - } else { - /* PWM */ - if (obj->ch == 2) { - wk_cycle = PWMPWCYR_2 & 0x03ff; - } else { - wk_cycle = PWMPWCYR_1 & 0x03ff; - } - value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); - } - - return (value > 1.0f) ? (1.0f) : (value); -} - -void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ - uint16_t wk_pwmpbfr; - float value; - uint16_t v; - - wk_pwmpbfr = *p_pwmpbfr; - value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle); - v = (uint16_t)((float)new_cycle * value); - *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); -} - -static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ - uint16_t wk_pwmpbfr; - float value; - - wk_pwmpbfr = *p_pwmpbfr; - value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); - *p_pwmpbfr = (uint16_t)((float)new_cycle * value); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) { - uint64_t wk_cycle_mtu2; - uint32_t pclk_base; - uint32_t wk_cycle; - uint32_t wk_cks = 0; - uint16_t wk_last_cycle; - int max_us = 0; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - int tmp_pwm; - uint8_t tmp_tcr_up; - uint8_t tmp_tstr_sp; - uint8_t tmp_tstr_st; - - max_us = MAX_PERIOD[obj->ch]; - if (us > max_us) { - us = max_us; - } else if (us < 1) { - us = 1; - } else { - // Do Nothing - } - - if (RZ_A1_IsClockMode0() == false) { - pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK; - } else { - pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK; - } - - wk_cycle_mtu2 = (uint64_t)pclk_base * us; - while (wk_cycle_mtu2 >= 65535000000) { - if ((obj->ch == 1) && (wk_cks == 3)) { - wk_cks+=2; - } else if ((obj->ch == 2) && (wk_cks == 3)) { - wk_cycle_mtu2 >>= 2; - wk_cks+=3; - } - wk_cycle_mtu2 >>= 2; - wk_cks++; - } - wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); - - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { - tmp_tcr_up = 0xC0; - } else { - tmp_tcr_up = 0x40; - } - if ((obj->ch == 4) || (obj->ch == 3)) { - tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3))); - tmp_tstr_st = (1 << (obj->ch + 3)); - } else { - tmp_tstr_sp = ~(0x38 | (1 << obj->ch)); - tmp_tstr_st = (1 << obj->ch); - } - // Counter Stop - MTU2TSTR &= tmp_tstr_sp; - wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; - *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks; - *TIORH_MATCH[obj->ch] = 0x21; - if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { - *TIORL_MATCH[obj->ch] = 0x21; - } - *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period - - // Set duty again(TGRA) - set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle); - if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { - // Set duty again(TGRC) - set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle); - } - *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1 - - // Counter Start - MTU2TSTR |= tmp_tstr_st; - // Save for future use - mtu2_period_ch[obj->ch] = us; - } else { - /* PWM */ - if (us > 491) { - us = 491; - } else if (us < 1) { - us = 1; - } else { - // Do Nothing - } - - if (RZ_A1_IsClockMode0() == false) { - pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000; - } else { - pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000; - } - - wk_cycle = pclk_base * us; - while (wk_cycle >= 102350) { - wk_cycle >>= 1; - wk_cks++; - } - wk_cycle = (wk_cycle + 50) / 100; - - if (obj->ch == 2) { - wk_last_cycle = PWMPWCYR_2 & 0x03ff; - PWMPWCR_2_BYTE_L = 0xc0 | wk_cks; - PWMPWCYR_2 = (uint16_t)wk_cycle; - - // Set duty again - set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle); - - // Counter Start - PWMPWCR_2_BYTE_L |= 0x08; - - // Save for future use - period_ch2 = us; - } else { - wk_last_cycle = PWMPWCYR_1 & 0x03ff; - PWMPWCR_1_BYTE_L = 0xc0 | wk_cks; - PWMPWCYR_1 = (uint16_t)wk_cycle; - - // Set duty again - set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle); - - // Counter Start - PWMPWCR_1_BYTE_L |= 0x08; - - // Save for future use - period_ch1 = us; - } - } -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - float value = 0; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - if (mtu2_period_ch[obj->ch] != 0) { - value = (float)us / (float)mtu2_period_ch[obj->ch]; - } - } else { - /* PWM */ - if (obj->ch == 2) { - if (period_ch2 != 0) { - value = (float)us / (float)period_ch2; - } - } else { - if (period_ch1 != 0) { - value = (float)us / (float)period_ch1; - } - } - } - pwmout_write(obj, value); -} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c deleted file mode 100644 index 3982a77a9bb..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c +++ /dev/null @@ -1,732 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include "mbed_assert.h" -#include -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "gpio_api.h" - -#include "scif_iodefine.h" -#include "cpg_iodefine.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define PCLK (66666666) // Define the peripheral clock P1 frequency. - -#define UART_NUM 8 -#define IRQ_NUM 2 - -static void uart0_tx_irq(void); -static void uart1_tx_irq(void); -static void uart2_tx_irq(void); -static void uart3_tx_irq(void); -static void uart4_tx_irq(void); -static void uart5_tx_irq(void); -static void uart6_tx_irq(void); -static void uart7_tx_irq(void); -static void uart0_rx_irq(void); -static void uart1_rx_irq(void); -static void uart2_rx_irq(void); -static void uart3_rx_irq(void); -static void uart4_rx_irq(void); -static void uart5_rx_irq(void); -static void uart6_rx_irq(void); -static void uart7_rx_irq(void); - -#ifdef MAX_PERI -static const PinMap PinMap_UART_TX[] = { - {P2_14 , UART0, 6}, - {P4_9 , UART0, 7}, - {P6_9 , UART0, 5}, - {P2_5 , UART1, 6}, - {P4_12 , UART1, 7}, - {P6_12 , UART1, 5}, - {P9_3 , UART1, 4}, - {P3_0 , UART2, 6}, - {P3_1 , UART2, 4}, - {P4_2 , UART2, 5}, - {P4_14 , UART2, 7}, - {P6_3 , UART2, 7}, - {P8_6 , UART2, 7}, - {P3_5 , UART3, 7}, - {P5_3 , UART3, 5}, - {P6_1 , UART3, 7}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P7_1 , UART4, 4}, - {P8_14 , UART4, 7}, - {P6_6 , UART5, 5}, - {P8_1 , UART5, 4}, - {P8_13 , UART5, 5}, - {P5_6 , UART6, 5}, - {P6_14 , UART6, 4}, - {P7_4 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {P2_15 , UART0, 6}, - {P4_10 , UART0, 7}, - {P6_10 , UART0, 5}, - {P2_6 , UART1, 6}, - {P4_13 , UART1, 7}, - {P6_13 , UART1, 5}, - {P9_4 , UART1, 4}, - {P3_2 , UART2, 4}, - {P4_3 , UART2, 5}, - {P4_15 , UART2, 7}, - {P6_2 , UART2, 7}, - {P8_4 , UART2, 7}, - {P3_6 , UART3, 7}, - {P5_4 , UART3, 5}, - {P6_0 , UART3, 7}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P7_2 , UART4, 4}, - {P8_15 , UART4, 7}, - {P6_7 , UART5, 5}, - {P8_2 , UART5, 4}, - {P8_11 , UART5, 5}, - {P5_7 , UART6, 5}, - {P6_15 , UART6, 4}, - {P7_5 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {P2_3 , UART1, 6}, - {P9_5 , UART1, 4}, - {P6_3 , UART5, 5}, - {P7_15 , UART5, 4}, - {P7_6 , UART7, 4}, - {NC , NC , 0} -}; -static const PinMap PinMap_UART_RTS[] = { - {P2_7 , UART1, 6}, - {P9_6 , UART1, 4}, - {P6_4 , UART5, 5}, - {P8_3 , UART5, 4}, - {P7_7 , UART7, 4}, - {NC , NC , 0} -}; -#else -static const PinMap PinMap_UART_TX[] = { - {P3_0 , UART2, 6}, - {P3_1 , UART2, 4}, - {P4_2 , UART2, 5}, - {P5_3 , UART3, 5}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P8_14 , UART4, 7}, - {P8_13 , UART5, 5}, - {P5_6 , UART6, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {P3_2 , UART2, 4}, - {P4_3 , UART2, 5}, - {P5_4 , UART3, 5}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P8_15 , UART4, 7}, - {P8_11 , UART5, 5}, - {P5_7 , UART6, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {NC , NC , 0} -}; -static const PinMap PinMap_UART_RTS[] = { - {NC , NC , 0} -}; -#endif - -static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -struct serial_global_data_s { - uint32_t serial_irq_id; - gpio_t sw_rts, sw_cts; - uint8_t count, rx_irq_set_flow, rx_irq_set_api; -}; - -static struct serial_global_data_s uart_data[UART_NUM]; - -static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { - {SCIFRXI0_IRQn, SCIFTXI0_IRQn}, - {SCIFRXI1_IRQn, SCIFTXI1_IRQn}, - {SCIFRXI2_IRQn, SCIFTXI2_IRQn}, - {SCIFRXI3_IRQn, SCIFTXI3_IRQn}, - {SCIFRXI4_IRQn, SCIFTXI4_IRQn}, - {SCIFRXI5_IRQn, SCIFTXI5_IRQn}, - {SCIFRXI6_IRQn, SCIFTXI6_IRQn}, - {SCIFRXI7_IRQn, SCIFTXI7_IRQn} -}; - -static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { - {uart0_rx_irq, uart0_tx_irq}, - {uart1_rx_irq, uart1_tx_irq}, - {uart2_rx_irq, uart2_tx_irq}, - {uart3_rx_irq, uart3_tx_irq}, - {uart4_rx_irq, uart4_tx_irq}, - {uart5_rx_irq, uart5_tx_irq}, - {uart6_rx_irq, uart6_tx_irq}, - {uart7_rx_irq, uart7_tx_irq} -}; - -static __IO uint16_t *SCSCR_MATCH[] = { - &SCSCR_0, - &SCSCR_1, - &SCSCR_2, - &SCSCR_3, - &SCSCR_4, - &SCSCR_5, - &SCSCR_6, - &SCSCR_7, -}; - -static __IO uint16_t *SCFSR_MATCH[] = { - &SCFSR_0, - &SCFSR_1, - &SCFSR_2, - &SCFSR_3, - &SCFSR_4, - &SCFSR_5, - &SCFSR_6, - &SCFSR_7, -}; - - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - volatile uint8_t dummy ; - int is_stdio_uart = 0; - // determine the UART to use - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - uint32_t uart = pinmap_merge(uart_tx, uart_rx); - - MBED_ASSERT((int)uart != NC); - - obj->uart = (struct st_scif *)SCIF[uart]; - // enable power - switch (uart) { - case UART0: - CPG.STBCR4 &= ~(1 << 7); - break; - case UART1: - CPG.STBCR4 &= ~(1 << 6); - break; - case UART2: - CPG.STBCR4 &= ~(1 << 5); - break; - case UART3: - CPG.STBCR4 &= ~(1 << 4); - break; - case UART4: - CPG.STBCR4 &= ~(1 << 3); - break; - case UART5: - CPG.STBCR4 &= ~(1 << 2); - break; - case UART6: - CPG.STBCR4 &= ~(1 << 1); - break; - case UART7: - CPG.STBCR4 &= ~(1 << 0); - break; - } - dummy = CPG.STBCR4; - - /* if this uart has been previously configured to tx, wait tx completion befor loading new configuration */ - if(obj->uart->SCSCR & 0xA0) - while(!(obj->uart->SCFSR & 0x0040)); - - /* ==== SCIF initial setting ==== */ - /* ---- Serial control register (SCSCR) setting ---- */ - /* B'00 : Internal CLK */ - obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ - - /* ---- FIFO control register (SCFCR) setting ---- */ - /* Transmit FIFO reset & Receive FIFO data register reset */ - obj->uart->SCFCR = 0x0006; - - /* ---- Serial status register (SCFSR) setting ---- */ - dummy = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */ - - /* ---- Line status register (SCLSR) setting ---- */ - /* ORER bit clear */ - obj->uart->SCLSR = 0; - - /* ---- Serial extension mode register (SCEMR) setting ---- - b7 BGDM - Baud rate generator double-speed mode : Normal mode - b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ - obj->uart->SCEMR = 0x0000u; - - /* ---- Bit rate register (SCBRR) setting ---- */ - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - /* ---- FIFO control register (SCFCR) setting ---- */ - obj->uart->SCFCR = 0x0030u; - - /* ---- Serial port register (SCSPTR) setting ---- - b1 SPB2IO - Serial port break output : disabled - b0 SPB2DT - Serial port break data : High-level */ - obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 - - /* ---- Line status register (SCLSR) setting ---- - b0 ORER - Overrun error detect : clear */ - - if (obj->uart->SCLSR & 0x0001) { - obj->uart->SCLSR = 0u; // ORER clear - } - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - switch (uart) { - case UART0: - obj->index = 0; - break; - case UART1: - obj->index = 1; - break; - case UART2: - obj->index = 2; - break; - case UART3: - obj->index = 3; - break; - case UART4: - obj->index = 4; - break; - case UART5: - obj->index = 5; - break; - case UART6: - obj->index = 6; - break; - case UART7: - obj->index = 7; - break; - } - uart_data[obj->index].sw_rts.pin = NC; - uart_data[obj->index].sw_cts.pin = NC; - - /* ---- Serial control register (SCSCR) setting ---- */ - /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */ - obj->uart->SCSCR = (((uart_tx != (uint32_t)NC)? 0xA0 : 0) | ((uart_rx != (uint32_t)NC)? 0x50 : 0 )); //0x00F0; - - is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - uint16_t DL; - - obj->uart->SCSMR &= ~0x0003; - - if (baudrate > 32552) { - obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 - DL = PCLK / (8 * baudrate); - if (DL > 0) { - DL--; - } - obj->uart->SCBRR = (uint8_t)DL; - } else if (baudrate > 16276) { - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; - } else if (baudrate > 8138) { - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; - } else if (baudrate > 4169) { - obj->uart->SCSMR |= 0x0001; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; - } else if (baudrate > 2034) { - obj->uart->SCSMR |= 0x0001; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; - } else if (baudrate > 1017) { - obj->uart->SCSMR |= 0x0002; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; - } else if (baudrate > 508) { - obj->uart->SCSMR |= 0x0002; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; - } else if (baudrate > 254) { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; - } else if (baudrate > 127) { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; - } else { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = 0xFFu; - } -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - int parity_enable; - int parity_select; - - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); - - stop_bits = (stop_bits == 1)? 0: - (stop_bits == 2)? 1: - 0; // must not to be - - data_bits = (data_bits == 8)? 0: - (data_bits == 7)? 1: - 0; // must not to be - - switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd: - parity_enable = 1; - parity_select = 1; - break; - case ParityEven: - parity_enable = 1; - parity_select = 0; - break; - case ParityForced1: - case ParityForced0: - default: - parity_enable = 0; - parity_select = 0; - break; - } - - obj->uart->SCSMR = data_bits << 6 - | parity_enable << 5 - | parity_select << 4 - | stop_bits << 3; -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { - __IO uint16_t *dmy_rd_scscr; - __IO uint16_t *dmy_rd_scfsr; - - dmy_rd_scscr = SCSCR_MATCH[index]; - *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0 - dmy_rd_scfsr = SCFSR_MATCH[index]; - *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE - - irq_handler(uart_data[index].serial_irq_id, TxIrq); -} - -static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { - __IO uint16_t *dmy_rd_scscr; - __IO uint16_t *dmy_rd_scfsr; - - dmy_rd_scscr = SCSCR_MATCH[index]; - *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0 - dmy_rd_scfsr = SCFSR_MATCH[index]; - *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR - - irq_handler(uart_data[index].serial_irq_id, RxIrq); -} - -/* TX handler */ -static void uart0_tx_irq(void) { - uart_tx_irq(SCIFTXI0_IRQn, 0); -} -static void uart1_tx_irq(void) { - uart_tx_irq(SCIFTXI1_IRQn, 1); -} -static void uart2_tx_irq(void) { - uart_tx_irq(SCIFTXI2_IRQn, 2); -} -static void uart3_tx_irq(void) { - uart_tx_irq(SCIFTXI3_IRQn, 3); -} -static void uart4_tx_irq(void) { - uart_tx_irq(SCIFTXI4_IRQn, 4); -} -static void uart5_tx_irq(void) { - uart_tx_irq(SCIFTXI5_IRQn, 5); -} -static void uart6_tx_irq(void) { - uart_tx_irq(SCIFTXI6_IRQn, 6); -} -static void uart7_tx_irq(void) { - uart_tx_irq(SCIFTXI7_IRQn, 7); -} -/* RX handler */ -static void uart0_rx_irq(void) { - uart_rx_irq(SCIFRXI0_IRQn, 0); -} -static void uart1_rx_irq(void) { - uart_rx_irq(SCIFRXI1_IRQn, 1); -} -static void uart2_rx_irq(void) { - uart_rx_irq(SCIFRXI2_IRQn, 2); -} -static void uart3_rx_irq(void) { - uart_rx_irq(SCIFRXI3_IRQn, 3); -} -static void uart4_rx_irq(void) { - uart_rx_irq(SCIFRXI4_IRQn, 4); -} -static void uart5_rx_irq(void) { - uart_rx_irq(SCIFRXI5_IRQn, 5); -} -static void uart6_rx_irq(void) { - uart_rx_irq(SCIFRXI6_IRQn, 6); -} -static void uart7_rx_irq(void) { - uart_rx_irq(SCIFRXI7_IRQn, 7); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; -} - -static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type IRQn; - IRQHandler handler; - - IRQn = irq_set_tbl[obj->index][irq]; - handler = hander_set_tbl[obj->index][irq]; - - if ((obj->index >= 0) && (obj->index <= 7)) { - if (enable) { - InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); - GIC_SetPriority(IRQn, 5); - GIC_EnableIRQ(IRQn); - } else { - GIC_DisableIRQ(IRQn); - } - } -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (RxIrq == irq) { - uart_data[obj->index].rx_irq_set_api = enable; - } - serial_irq_set_internal(obj, irq, enable); -} - -static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { - uart_data[obj->index].rx_irq_set_flow = enable; - serial_irq_set_internal(obj, RxIrq, enable); -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - uint16_t err_read; - int data; - int was_masked; - -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - if (obj->uart->SCFSR & 0x93) { - err_read = obj->uart->SCFSR; - obj->uart->SCFSR = (err_read & ~0x93); - } - obj->uart->SCSCR |= 0x0040; // Set RIE - if (!was_masked) { - __enable_irq(); - } - - if (obj->uart->SCLSR & 0x0001) { - obj->uart->SCLSR = 0u; // ORER clear - } - - while (!serial_readable(obj)); - data = obj->uart->SCFRDR & 0xff; - -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - err_read = obj->uart->SCFSR; - obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF - if (!was_masked) { - __enable_irq(); - } - - if (err_read & 0x80) { - data = -1; //err - } - return data; -} - -void serial_putc(serial_t *obj, int c) { - uint16_t dummy_read; - int was_masked; - -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - obj->uart->SCSCR |= 0x0080; // Set TIE - if (!was_masked) { - __enable_irq(); - } - while (!serial_writable(obj)); - obj->uart->SCFTDR = c; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - dummy_read = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE - if (!was_masked) { - __enable_irq(); - } - uart_data[obj->index].count++; -} - -int serial_readable(serial_t *obj) { - return ((obj->uart->SCFSR & 0x02) != 0); // RDF -} - -int serial_writable(serial_t *obj) { - return ((obj->uart->SCFSR & 0x20) != 0); // TDFE -} - -void serial_clear(serial_t *obj) { - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - - obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 - obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 - obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 - - if (!was_masked) { - __enable_irq(); - } -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - // TxD Output(L) - obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 - obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) - if (!was_masked) { - __enable_irq(); - } -} - -void serial_break_clear(serial_t *obj) { - int was_masked; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) - obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 - if (!was_masked) { - __enable_irq(); - } -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { - // determine the UART to use - int was_masked; - - serial_flow_irq_set(obj, 0); - - if (type == FlowControlRTSCTS) { -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - obj->uart->SCFCR = 0x0008u; // CTS/RTS enable - if (!was_masked) { - __enable_irq(); - } - pinmap_pinout(rxflow, PinMap_UART_RTS); - pinmap_pinout(txflow, PinMap_UART_CTS); - } else { -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - obj->uart->SCFCR = 0x0000u; // CTS/RTS diable - if (!was_masked) { - __enable_irq(); - } - } -} - - - - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c deleted file mode 100644 index 1464aaacd31..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c +++ /dev/null @@ -1,343 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include - -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "RZ_A1_Init.h" - - -#ifdef MAX_PERI -static const PinMap PinMap_SPI_SCLK[] = { - {P2_12 , SPI_0, 2}, - {P7_15 , SPI_0, 2}, - {P4_4 , SPI_1, 2}, - {P6_4 , SPI_1, 7}, - {P8_3 , SPI_2, 3}, - {P8_14 , SPI_2, 5}, - {P3_0 , SPI_3, 8}, - {P5_0 , SPI_3, 8}, - {P2_8 , SPI_4, 8}, - {P4_0 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P2_13 , SPI_0, 2}, - {P8_0 , SPI_0, 2}, - {P4_5 , SPI_1, 2}, - {P6_5 , SPI_1, 7}, - {P8_4 , SPI_2, 3}, - {P8_15 , SPI_2, 5}, - {P3_1 , SPI_3, 8}, - {P5_1 , SPI_3, 8}, - {P2_9 , SPI_4, 8}, - {P4_1 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P2_14 , SPI_0, 2}, - {P8_1 , SPI_0, 2}, - {P4_6 , SPI_1, 2}, - {P6_6 , SPI_1, 7}, - {P8_5 , SPI_2, 3}, - {P9_0 , SPI_2, 5}, - {P3_2 , SPI_3, 8}, - {P5_2 , SPI_3, 8}, - {P2_10 , SPI_4, 8}, - {P4_2 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P2_15 , SPI_0, 2}, - {P8_2 , SPI_0, 2}, - {P4_7 , SPI_1, 2}, - {P6_7 , SPI_1, 7}, - {P8_6 , SPI_2, 3}, - {P9_1 , SPI_2, 5}, - {P3_3 , SPI_3, 8}, - {P5_3 , SPI_3, 8}, - {P2_11 , SPI_4, 8}, - {P4_3 , SPI_4, 7}, - {NC , NC , 0} -}; -#else -static const PinMap PinMap_SPI_SCLK[] = { - {P4_4 , SPI_1, 2}, - {P8_14 , SPI_2, 5}, - {P5_0 , SPI_3, 8}, - {P4_0 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P4_5 , SPI_1, 2}, - {P8_15 , SPI_2, 5}, - {P5_1 , SPI_3, 8}, - {P4_1 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P4_6 , SPI_1, 2}, - {P9_0 , SPI_2, 5}, - {P5_2 , SPI_3, 8}, - {P4_2 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P4_7 , SPI_1, 2}, - {P9_1 , SPI_2, 5}, - {P5_3 , SPI_3, 8}, - {P4_3 , SPI_4, 7}, - {NC , NC , 0} -}; -#endif - - -static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; - -static inline void spi_disable(spi_t *obj); -static inline void spi_enable(spi_t *obj); -static inline int spi_readable(spi_t *obj); -static inline void spi_write(spi_t *obj, int value); -static inline int spi_read(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - volatile uint8_t dummy; - uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); - uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); - uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); - uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); - uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); - uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); - uint32_t spi = pinmap_merge(spi_data, spi_cntl); - - MBED_ASSERT((int)spi != NC); - - obj->spi = (struct st_rspi *)RSPI[spi]; - - // enable power and clocking - switch (spi) { - case SPI_1: CPGSTBCR10 &= ~(0x40); break; - case SPI_2: CPGSTBCR10 &= ~(0x20); break; - case SPI_3: CPGSTBCR10 &= ~(0x10); break; - case SPI_4: CPGSTBCR10 &= ~(0x08); break; - } - dummy = CPGSTBCR10; - - obj->spi->SPCR = 0x00; // CTRL to 0 - obj->spi->SPSCR = 0x00; // no sequential operation - obj->spi->SSLP = 0x00; // SSL 'L' active - obj->spi->SPDCR = 0x20; // byte access - obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK - obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK - obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK - obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0 - obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 - obj->spi->SPBFCR = 0x30; // and reset buffer - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if ((int)ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - int DSS; // DSS (data select size) - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - uint16_t tmp = 0; - uint16_t mask = 0xf03; - uint16_t wk_spcmd0; - uint8_t splw; - - switch (mode) { - case 0: - case 1: - case 2: - case 3: - // Do Nothing - break; - default: - error("SPI format error"); - return; - } - - switch (bits) { - case 8: - DSS = 0x7; - splw = 0x20; - break; - case 16: - DSS = 0xf; - splw = 0x40; - break; - case 32: - DSS = 0x2; - splw = 0x60; - break; - default: - error("SPI module don't support other than 8/16/32bits"); - return; - } - tmp |= phase; - tmp |= (polarity << 1); - tmp |= (DSS << 8); - obj->bits = bits; - - spi_disable(obj); - wk_spcmd0 = obj->spi->SPCMD0; - wk_spcmd0 &= ~mask; - wk_spcmd0 |= (mask & tmp); - obj->spi->SPCMD0 = wk_spcmd0; - obj->spi->SPDCR = splw; - if (slave) { - obj->spi->SPCR &=~(1 << 3); // MSTR to 0 - } else { - obj->spi->SPCR |= (1 << 3); // MSTR to 1 - } - spi_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - uint32_t pclk_base; - uint32_t div; - uint32_t brdv = 0; - uint32_t hz_max; - uint32_t hz_min; - uint16_t mask = 0x000c; - uint16_t wk_spcmd0; - - /* set PCLK */ - if (RZ_A1_IsClockMode0() == false) { - pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; - } else { - pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; - } - - hz_min = pclk_base / 2 / 256 / 8; - hz_max = pclk_base / 2; - if ((hz < hz_min) || (hz > hz_max)) { - error("Couldn't setup requested SPI frequency"); - return; - } - - div = (pclk_base / hz / 2); - while (div > 256) { - div >>= 1; - brdv++; - } - div -= 1; - brdv = (brdv << 2); - - spi_disable(obj); - obj->spi->SPBR = div; - wk_spcmd0 = obj->spi->SPCMD0; - wk_spcmd0 &= ~mask; - wk_spcmd0 |= (mask & brdv); - obj->spi->SPCMD0 = wk_spcmd0; - spi_enable(obj); -} - -static inline void spi_disable(spi_t *obj) { - obj->spi->SPCR &= ~(1 << 6); // SPE to 0 -} - -static inline void spi_enable(spi_t *obj) { - obj->spi->SPCR |= (1 << 6); // SPE to 1 -} - -static inline int spi_readable(spi_t *obj) { - return obj->spi->SPSR & (1 << 7); // SPRF -} - -static inline int spi_tend(spi_t *obj) { - return obj->spi->SPSR & (1 << 6); // TEND -} - -static inline void spi_write(spi_t *obj, int value) { - if (obj->bits == 8) { - obj->spi->SPDR.UINT8[0] = (uint8_t)value; - } else if (obj->bits == 16) { - obj->spi->SPDR.UINT16[0] = (uint16_t)value; - } else { - obj->spi->SPDR.UINT32 = (uint32_t)value; - } -} - -static inline int spi_read(spi_t *obj) { - int read_data; - - if (obj->bits == 8) { - read_data = obj->spi->SPDR.UINT8[0]; - } else if (obj->bits == 16) { - read_data = obj->spi->SPDR.UINT16[0]; - } else { - read_data = obj->spi->SPDR.UINT32; - } - - return read_data; -} - -int spi_master_write(spi_t *obj, int value) { - spi_write(obj, value); - while(!spi_tend(obj)); - return spi_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) { - return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); -} - -int spi_slave_read(spi_t *obj) { - return spi_read(obj); -} - -void spi_slave_write(spi_t *obj, int value) { - spi_write(obj, value); -} - -int spi_busy(spi_t *obj) { - return 0; -} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c deleted file mode 100644 index 6bcaea41d6c..00000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c +++ /dev/null @@ -1,143 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "ostm_iodefine.h" - -#include "RZ_A1_Init.h" -#include "VKRZA1H.h" - -#define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) -#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ - -#define US_TICKER_CLOCK_US_DEV (1000000) - -int us_ticker_inited = 0; -static double count_clock = 0; -static uint32_t last_read = 0; -static uint32_t wrap_arround = 0; -static uint64_t ticker_us_last64 = 0; - -void us_ticker_interrupt(void) { - us_ticker_irq_handler(); -} - -void us_ticker_init(void) { - if (us_ticker_inited) return; - us_ticker_inited = 1; - - /* set Counter Clock(us) */ - if (false == RZ_A1_IsClockMode0()) { - count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); - } else { - count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); - } - - /* Power Control for Peripherals */ - CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ - - // timer settings - OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ - OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ - - OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ - - // INTC settings - InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); - GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); - GIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -static uint64_t ticker_read_counter64(void) { - uint32_t cnt_val; - uint64_t cnt_val64; - - if (!us_ticker_inited) - us_ticker_init(); - - /* read counter */ - cnt_val = OSTM1CNT; - if (last_read > cnt_val) { - wrap_arround++; - } - last_read = cnt_val; - cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val; - - return cnt_val64; -} - -uint32_t us_ticker_read() { - uint64_t cnt_val64; - uint64_t us_val64; - int check_irq_masked; - -#if defined ( __ICCARM__) - check_irq_masked = __disable_irq_iar(); -#else - check_irq_masked = __disable_irq(); -#endif /* __ICCARM__ */ - - cnt_val64 = ticker_read_counter64(); - us_val64 = (cnt_val64 / count_clock); - ticker_us_last64 = us_val64; - - if (!check_irq_masked) { - __enable_irq(); - } - - /* clock to us */ - return (uint32_t)us_val64; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - // set match value - uint64_t timestamp64; - uint64_t set_cmp_val64; - volatile uint32_t set_cmp_val; - uint64_t count_val_64; - - /* calc compare mach timestamp */ - timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp; - if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) { - /* This event is wrap arround */ - timestamp64 += 0x100000000; - } - - /* calc compare mach timestamp */ - set_cmp_val64 = timestamp64 * count_clock; - set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF); - count_val_64 = ticker_read_counter64(); - if (set_cmp_val64 <= (count_val_64 + 500)) { - GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); - GIC_EnableIRQ(US_TICKER_TIMER_IRQn); - return; - } - OSTM1CMP = set_cmp_val; - GIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_fire_interrupt(void) { - GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_disable_interrupt(void) { - GIC_DisableIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_clear_interrupt(void) { - GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn); -} diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h index 75193d4863c..651c10b9976 100644 --- a/targets/TARGET_RENESAS/mbed_rtx.h +++ b/targets/TARGET_RENESAS/mbed_rtx.h @@ -16,4 +16,32 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H -#endif // MBED_MBED_RTX_H \ No newline at end of file +#include + +#define OS_IDLE_THREAD_STACK_SIZE 512 + +#if defined(__CC_ARM) + extern char Image$$ARM_LIB_STACK$$Base[]; + extern char Image$$ARM_LIB_STACK$$ZI$$Limit[]; + extern char Image$$ARM_LIB_HEAP$$Base[]; + #define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$Base) + #define ISR_STACK_SIZE ((uint32_t)((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - (uint32_t)Image$$ARM_LIB_STACK$$Base)) + #define INITIAL_SP (Image$$ARM_LIB_STACK$$ZI$$Limit) + #define HEAP_START ((unsigned char*)Image$$ARM_LIB_HEAP$$Base) + #define HEAP_SIZE ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START)) +#elif defined(__GNUC__) + extern uint32_t __StackTop; + extern uint32_t __StackLimit; + extern uint32_t __end__; + #define ISR_STACK_START ((unsigned char*)&__StackLimit) + #define ISR_STACK_SIZE ((uint32_t)((uint32_t)&__StackTop - (uint32_t)&__StackLimit)) + #define INITIAL_SP (&__StackTop) + #define HEAP_START ((unsigned char*)&__end__) + #define HEAP_SIZE ((uint32_t)((uint32_t)ISR_STACK_START - (uint32_t)HEAP_START)) +#elif defined(__ICCARM__) + /* No region declarations needed */ +#else + #error "no toolchain defined" +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp index 4410b92f8d6..92b3a91b568 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp +++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp @@ -36,14 +36,16 @@ typedef struct _wifi_scan_hdl { #define MAX_SCAN_TIMEOUT (15000) +static bool _inited = false; + static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) { wifi_scan_hdl *scan_handler = (wifi_scan_hdl *)malloced_scan_result->user_data; if (malloced_scan_result->scan_complete != RTW_TRUE) { if(scan_handler->ap_details && scan_handler->scan_num > scan_handler->ap_num){ - nsapi_wifi_ap_t ap; + nsapi_wifi_ap_t ap; rtw_scan_result_t* record = &malloced_scan_result->ap_details; - record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ + record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t)); memcpy(ap.ssid, record->SSID.val, record->SSID.len); memcpy(ap.bssid, record->BSSID.octet, 6); @@ -88,7 +90,7 @@ RTWInterface::RTWInterface(bool debug) { emac_interface_t *emac; int ret; - extern u32 GlobalDebugEnable; + extern u32 GlobalDebugEnable; GlobalDebugEnable = debug?1:0; emac = wlan_emac_init_interface(); @@ -97,10 +99,13 @@ RTWInterface::RTWInterface(bool debug) return; } emac->ops.power_up(emac); - ret = mbed_lwip_init(emac); - if (ret != 0) { - printf("Error init RTWInterface!(%d)\r\n", ret); - return; + if (_inited == false) { + ret = mbed_lwip_init(emac); + if (ret != 0) { + printf("Error init RTWInterface!(%d)\r\n", ret); + return; + } + _inited = true; } } @@ -130,6 +135,25 @@ nsapi_error_t RTWInterface::set_dhcp(bool dhcp) */ nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) { + if(!ssid) { + return NSAPI_ERROR_PARAMETER; + } + + switch (security) { + case NSAPI_SECURITY_WPA: + case NSAPI_SECURITY_WPA2: + case NSAPI_SECURITY_WPA_WPA2: + case NSAPI_SECURITY_WEP: + if((strlen(pass) < 8) || (strlen(pass) > 63)) { // 802.11 password 8-63 characters + return NSAPI_ERROR_PARAMETER; + } + break; + case NSAPI_SECURITY_NONE: + break; + default: + return NSAPI_ERROR_PARAMETER; + } + strncpy(_ssid, ssid, 255); strncpy(_pass, pass, 255); _security = security; @@ -158,7 +182,7 @@ nsapi_error_t RTWInterface::connect() break; case NSAPI_SECURITY_NONE: sec = RTW_SECURITY_OPEN; - break; + break; default: return NSAPI_ERROR_PARAMETER; } @@ -167,7 +191,7 @@ nsapi_error_t RTWInterface::connect() uint8_t pscan_config = PSCAN_ENABLE; wifi_set_pscan_chan(&_channel, &pscan_config, 1); } - + ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL); if (ret != RTW_SUCCESS) { printf("failed: %d\r\n", ret); @@ -218,7 +242,7 @@ int8_t RTWInterface::get_rssi() } nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass, - nsapi_security_t security, uint8_t channel) + nsapi_security_t security, uint8_t channel) { set_credentials(ssid, pass, security); set_channel(channel); @@ -230,9 +254,10 @@ nsapi_error_t RTWInterface::disconnect() char essid[33]; wlan_emac_link_change(false); + mbed_lwip_bringdown(); if(wifi_is_connected_to_ap() != RTW_SUCCESS) return NSAPI_ERROR_NO_CONNECTION; - if(wifi_disconnect()<0){ + if(wifi_disconnect()<0){ return NSAPI_ERROR_DEVICE_ERROR; } while(1){ @@ -281,4 +306,4 @@ const char *RTWInterface::get_gateway() NetworkStack *RTWInterface::get_stack() { return nsapi_create_stack(&lwip_stack); -} \ No newline at end of file +} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index 4cf7eea1a8d..03f74e0f690 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -13,26 +13,26 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { IMAGE2_TABLE 0x10007000 FIXED { - *rtl8195a_init.o(.image2.ram.data*, +FIRST) - *rtl8195a_init.o(.image2.validate.rodata*) + *rtl8195a_init*.o(.image2.ram.data*, +FIRST) + *rtl8195a_init*.o(.image2.validate.rodata*) } ER_IRAM +0 FIXED { - *rtl8195a_crypto.o (+RO) + *rtl8195a_crypto*.o (+RO) *(i.mbedtls*) *libc.a (+RO) *rtx_*.o (+RO) } RW_IRAM1 +0 UNINIT FIXED { - *rtl8195a_crypto.o(+RW) + *rtl8195a_crypto*.o(+RW) *libc.a (+RW) *(.sdram.data*) *lib_peripheral_mbed_arm.ar (+RW) } RW_IRAM2 +0 UNINIT FIXED { - *rtl8195a_crypto.o(+ZI, COMMON) + *rtl8195a_crypto*.o(+ZI, COMMON) *libc.a (+ZI, COMMON) *(.bss.thread_stack_main) *lib_peripheral_mbed_arm.ar (+ZI, COMMON) @@ -44,8 +44,8 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { LR_TCM 0x1FFF0000 0x10000 { TCM_OVERLAY 0x1FFF0000 0x10000 { - *lwip_mem.o(.bss*) - *lwip_memp.o(.bss*) + *lwip_mem*.o(.bss*) + *lwip_memp*.o(.bss*) *.o(.tcm.heap*) } } diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c index 565b149a978..58127d457ec 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c @@ -23,24 +23,24 @@ static flash_t flash_obj; -void OTA_ReadHeader(uint32_t base, imginfo_t *img) +void OTA_ReadHeader(uint32_t addr, imginfo_t *img) { uint32_t epoch_hi, epoch_lo; - if (base != OTA_REGION1_BASE || base != OTA_REGION2_BASE) { + if (addr != OTA_REGION1_HEADER || addr != OTA_REGION2_HEADER) { return; } - flash_ext_read_word(&flash_obj, base + OTA_TAG_OFS, &img->tag); - flash_ext_read_word(&flash_obj, base + OTA_VER_OFS, &img->ver); - flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS, &epoch_hi); - flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS + 4, &epoch_lo); + flash_ext_read_word(&flash_obj, addr + OTA_TAG_OFS, &img->tag); + flash_ext_read_word(&flash_obj, addr + OTA_VER_OFS, &img->ver); + flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS, &epoch_hi); + flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS + 4, &epoch_lo); img->timestamp = ((uint64_t)epoch_hi << 32) | (uint64_t) epoch_lo; - flash_ext_read_word(&flash_obj, base + OTA_SIZE_OFS, &img->size); - flash_ext_stream_read(&flash_obj, base + OTA_HASH_OFS, 32, img->hash); - flash_ext_stream_read(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign); - flash_ext_read_word(&flash_obj, base + OTA_CRC32_OFS, &img->crc32); + flash_ext_read_word(&flash_obj, addr + OTA_SIZE_OFS, &img->size); + flash_ext_stream_read(&flash_obj, addr + OTA_HASH_OFS, 32, img->hash); + flash_ext_stream_read(&flash_obj, addr + OTA_CAMPAIGN_OFS, 16, img->campaign); + flash_ext_read_word(&flash_obj, addr + OTA_CRC32_OFS, &img->crc32); } bool OTA_CheckHeader(imginfo_t *img) @@ -61,9 +61,9 @@ bool OTA_CheckHeader(imginfo_t *img) return true; } -void OTA_GetImageInfo(uint32_t base, imginfo_t *img) +void OTA_GetImageInfo(uint32_t header, imginfo_t *img) { - OTA_ReadHeader(base, img); + OTA_ReadHeader(header, img); if (!OTA_CheckHeader(img)) { img->timestamp = 0; @@ -77,8 +77,8 @@ uint32_t OTA_GetUpdateBase(void) { imginfo_t img1, img2; - OTA_GetImageInfo(OTA_REGION1_BASE, &img1); - OTA_GetImageInfo(OTA_REGION2_BASE, &img2); + OTA_GetImageInfo(OTA_REGION1_HEADER, &img1); + OTA_GetImageInfo(OTA_REGION2_HEADER, &img2); if (img1.valid && img2.valid) { if (img1.timestamp < img2.timestamp) { diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h index bea950e13ed..81d89ad6d65 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h @@ -22,17 +22,19 @@ #define FLASH_SECTOR_SIZE 0x1000 #define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1) +#define OTA_REGION1_HEADER 0x0b000 +#define OTA_REGION2_HEADER 0x0c000 #define OTA_REGION1_BASE 0x40000 #define OTA_REGION2_BASE 0x120000 #define OTA_REGION1_SIZE 0xe0000 #define OTA_REGION2_SIZE 0xe0000 #define OTA_REGION_SIZE 0xe0000 -#define OTA_MBED_FS_BASE 0xb000 +#define OTA_MBED_FS_BASE 0x10000 +#define OTA_MBED_FS_SIZE 0x30000 #define OTA_CRC32_LEN 0x44 #define OTA_HEADER_LEN 0x48 -#define OTA_HEADER_OFS 0x0 #define OTA_TAG_OFS 0x0 #define OTA_VER_OFS 0x4 #define OTA_EPOCH_OFS 0x8 @@ -57,6 +59,8 @@ typedef struct imginfo_s { uint8_t campaign[16]; uint32_t crc32; bool valid; + uint32_t header_addr; + uint32_t image_addr; } imginfo_t; #ifdef __cplusplus @@ -64,7 +68,7 @@ extern "C" { #endif extern void OTA_GetImageInfo(uint32_t base, imginfo_t *info); -extern uint32_t OTA_GetUpdateBase(void); +extern uint32_t OTA_GetUpdateRegion(void); extern uint32_t OTA_UpdateHeader(uint32_t base, imginfo_t *img); extern uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data); diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h index cd7c25c8c09..f200e31f119 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { UART_2 = (int)USART2_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h index c7b5fd67543..d3093d1ae9e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h @@ -127,6 +127,18 @@ typedef enum { // D14 = PB_9, // D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // STM32F0-Discovery(STM32F051R8) connector namings PA0 = PA_0, PA1 = PA_1, @@ -188,10 +200,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S index 6630f3629b6..fedb462f5f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f051x8.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S index 71932f44e97..e8f7595f38c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f051x8.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S index 5ae8717ba31..70959f3f8d7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f051x8.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h index 3f0c4e35f60..7e2cf35a023 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h @@ -46,11 +46,11 @@ #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() -#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h index 1be4bcc070d..0149d3d7416 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f051x8.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2805,56 +2803,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -3524,72 +3574,72 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3775,25 +3825,25 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3986,9 +4036,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -4020,6 +4070,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -6636,6 +6691,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h index b7cf48712fb..9836a7e3d9a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c index ccb1e96f4d1..72fa4b7e7d4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c @@ -212,7 +212,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h index cd46695e137..26f11f6d451 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_2 = (int)USART2_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h index 68256c2a4dd..53a0430cefe 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h @@ -127,6 +127,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -135,10 +147,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S index c82949c838b..f83bb9d4535 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S @@ -101,7 +101,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD 0 ; Reserved DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 DCD 0 ; Reserved DCD TIM14_IRQHandler ; TIM14 DCD TIM15_IRQHandler ; TIM15 @@ -120,7 +120,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -171,6 +171,7 @@ Default_Handler PROC EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK] EXPORT TIM15_IRQHandler [WEAK] EXPORT TIM16_IRQHandler [WEAK] @@ -197,6 +198,7 @@ ADC1_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM3_IRQHandler +TIM6_IRQHandler TIM14_IRQHandler TIM15_IRQHandler TIM16_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S index 8d3a08bac10..f616165ec94 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S @@ -74,7 +74,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD 0 ; Reserved DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 DCD 0 ; Reserved DCD TIM14_IRQHandler ; TIM14 DCD TIM15_IRQHandler ; TIM15 @@ -93,7 +93,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -144,6 +144,7 @@ Default_Handler PROC EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM14_IRQHandler [WEAK] EXPORT TIM15_IRQHandler [WEAK] EXPORT TIM16_IRQHandler [WEAK] @@ -170,6 +171,7 @@ ADC1_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler TIM1_CC_IRQHandler TIM3_IRQHandler +TIM6_IRQHandler TIM14_IRQHandler TIM15_IRQHandler TIM16_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S index 45267362742..97a36cb81e6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f030x8.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F030x8 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F030x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S index 8c13b3d3303..f609cd8be2f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_IAR/startup_stm32f030x8.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f030x8.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F030x8 devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h index 3f0c4e35f60..7e2cf35a023 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h @@ -46,11 +46,11 @@ #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() -#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h index 0339d8a0da6..c10d677ce3c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f030x8.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2301,56 +2299,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -2990,63 +3040,63 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3220,19 +3270,19 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3414,9 +3464,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -3448,6 +3498,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -5322,7 +5377,10 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) - + +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h index 4a5b4d432ef..0af10c21f38 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c index 0e8886ed76f..fe5ebfe73bf 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c @@ -213,7 +213,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h index 2b4906c1d2a..78b420b9924 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h @@ -44,10 +44,6 @@ typedef enum { UART_1 = (int)USART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h index a5f7d1c6d36..5c43458fdca 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h @@ -97,15 +97,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PA_9, I2C_SDA = PA_10, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S index a6eea51afda..c46d4079c5a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f031x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S index 757a90de992..ac23206062d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f031x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S index 2d505708c31..6659250a3a4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f031x6.s * @author MCD Application Team - * @version V2.2.2 - * @date 26-June-2015 - * @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S index c02773e1acd..c7a11a44e33 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f031x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2015 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h index e8d74550477..0b0e2f60353 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h @@ -45,11 +45,11 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h index f281ed9cb3d..c4d15c3faa7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f031x6.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2359,56 +2357,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -3094,51 +3144,51 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3297,16 +3347,16 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3489,9 +3539,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -3523,6 +3573,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -5564,6 +5619,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /*********************** UART Instances : IRDA mode ***************************/ #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h index 3c267512945..ada004259c4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c index 2e18b9cc29a..6b57adbc6e7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c @@ -213,7 +213,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h index 40a30114c17..4ebdb238834 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_2 = (int)USART2_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE // for compilation diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h index a148910e590..24b39a36b62 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h @@ -110,15 +110,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PA_9, I2C_SDA = PA_10, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S index 25c8f935300..588b14a2b1b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f042x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S index 01448774865..af9dc49cf5d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f042x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S index a751fe57843..f4fc3ae1ff7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f042x6.s * @author MCD Application Team - * @version V2.2.2 - * @date 26-June-2015 - * @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /** * @brief This is the code that gets called when the processor first @@ -78,8 +80,6 @@ Reset_Handler: LDR R1, [R0] LSRS R1, R1, #24 LDR R2,=0x1F - MOVS R1, #0 - MOVS R2, #1 CMP R1, R2 BNE ApplicationStart @@ -96,21 +96,35 @@ Reset_Handler: ApplicationStart: /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S index 8cde7360b88..7772212e7ca 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f042x6.s ;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 ;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2015 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h index 0caa0508c08..8fc6dd3afe9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h @@ -45,11 +45,11 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h index ffd0022e42e..9530b33c1c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f042x6.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -6496,56 +6494,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -7264,69 +7314,69 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ #define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ +#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ #define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -7506,22 +7556,22 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -7733,9 +7783,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -7767,6 +7817,11 @@ typedef struct #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -10528,6 +10583,9 @@ typedef struct (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM14)) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h index 6f844a2fad3..b579f75dfb9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h index 08f32ca2628..7cdddd7a860 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h @@ -47,10 +47,6 @@ typedef enum { UART_4 = (int)USART4_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h index 400c744a361..1e9cff29d2d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S index 0814fae074c..4c5c3ddb3d8 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f070xb.s ;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 05-December-2014 ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S index 29a68407e0b..20704321405 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f070xb.s ;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 05-December-2014 ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S index 16ce3d8edbb..72094b591ab 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f070xb.s * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 - * @brief STM32F070xb/STM32F070x8 devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F070xb/STM32F070x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,7 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata - +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -65,21 +66,6 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - // Load from _sidata -> _sdata through _edata - // _sidata has a vma = lma in flash at the end of .text - // _sdata has a lma in flash but a vma of ram, so here we move it from where - // it was loaded (lma) into where it will be accessed (vma). - // Register Schema: - // r0 = _sdata, r1 = _edata, r2 = _sidata - // r3 = index (goes from 0 -> _sdata - _edata) - // r4 = temp var for *(_sidata + r3) or (_sdata + r3) - // This is all equivalent to this C: - // int index = 0; - // extern uint32_t *_sdata, *_sidata; - // while (_sdata + index < _edata) { - // *_sdata[index] = *_sidata[index]; - // index += 1; - // } ldr r0, =_sdata ldr r1, =_edata ldr r2, =_sidata @@ -92,16 +78,28 @@ CopyDataInit: adds r3, r3, #4 LoopCopyDataInit: - // while (_sdata + r3 < _edata) adds r4, r0, r3 - // if (r4 < r1) branch to CopyDataInit cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit - +/* Call static constructors */ + // bl __libc_init_array /* Call the application's entry point.*/ // bl main bl _start diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S index 7fcd91c9e45..144e3ecb013 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/startup_stm32f070xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f070xb.s ;* Author : MCD Application Team -;* Version : V2.2.0 -;* Date : 05-December-2014 ;* Description : STM32F070xB devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h index 3f0c4e35f60..7e2cf35a023 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h @@ -46,11 +46,11 @@ #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM1_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() -#define TIM_MST_RESET_ON __TIM1_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM1_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM1_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h index 25770e09f55..c5ccb917760 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f070xb.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -2396,56 +2394,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -3120,75 +3170,75 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -3373,19 +3423,19 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -3577,9 +3627,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -3623,6 +3673,11 @@ typedef struct #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -5669,6 +5724,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h index 1e936ed8697..f85e5fcaf11 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c index b870c189d7b..0cc1885a6f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c @@ -216,7 +216,6 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h index 52b2b82eb23..9f37e1a64b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h @@ -51,10 +51,6 @@ typedef enum { UART_4 = (int)USART4_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h index 400c744a361..1e9cff29d2d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S index 23b894eaa07..d1a1f2fac67 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f072xb.s ;* Author : MCD Application Team -;* Version : V2.0.0 -;* Date : 20-May-2014 ;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S index 33050eb33d2..82ea5cdc5b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f072xb.s ;* Author : MCD Application Team -;* Version : V2.0.0 -;* Date : 20-May-2014 ;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S index 525d175a139..8c4a2e4b38d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f072xb.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F072x8/STM32F072xB devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F072x8/STM32F072xB devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,28 +66,42 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ - bl SystemInit + bl SystemInit /* Call static constructors */ - //bl __libc_init_array + //bl __libc_init_array /* Call the application's entry point.*/ - //bl main + //bl main /** * Calling the crt0 'cold-start' entry point. There __libc_init_array is called * and when existing hardware_init_hook() and software_init_hook() before diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S index 82a403f68b7..b334e01ded5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/startup_stm32f072xb.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f072xb.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h index 42c96c85c60..c6c8f2729ff 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h @@ -45,11 +45,11 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h index 18c8c9958ce..5960276be28 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f072xb.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -6934,56 +6932,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -7711,90 +7761,90 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ -#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ #define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ +#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ #define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -8001,28 +8051,28 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOERST_Pos (21U) #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ -#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */ +#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -8248,9 +8298,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -8294,6 +8344,11 @@ typedef struct #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -11132,6 +11187,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h index 58c50fb30f1..3aba5160ddd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h index 5acb24b75f9..f2616871d51 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_8 = (int)USART8_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h index 3c33d81d857..b09d4914821 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h @@ -124,6 +124,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -132,10 +144,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S rename to targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S index d338b6ae5d8..2df33929713 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f091xc.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f091xc.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S rename to targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S index d6f00552e83..dd63a9aca9e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_ARM_STD/startup_stm32f091xc.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f091xc.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S index cc06a7ff626..ba5808009cc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f091xc.s * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 - * @brief STM32F091xC devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F091xC devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -55,6 +53,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .section .text.Reset_Handler .weak Reset_Handler @@ -64,21 +66,35 @@ Reset_Handler: mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S index 682f12bc3d1..4658aa996b1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_IAR/startup_stm32f091xc.S @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** ;* File Name : startup_stm32f091xc.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 03-Oct-2014 ;* Description : STM32F091xc/STM32F098xc devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,8 +13,6 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* ;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h index 42c96c85c60..c6c8f2729ff 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h @@ -45,11 +45,11 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() -#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() #define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h index afbadedaac0..8b96be761a0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f091xc.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -7405,56 +7403,108 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0_Pos (0U) -#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk -#define GPIO_AFRL_AFRL1_Pos (4U) -#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk -#define GPIO_AFRL_AFRL2_Pos (8U) -#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk -#define GPIO_AFRL_AFRL3_Pos (12U) -#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk -#define GPIO_AFRL_AFRL4_Pos (16U) -#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk -#define GPIO_AFRL_AFRL5_Pos (20U) -#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk -#define GPIO_AFRL_AFRL6_Pos (24U) -#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk -#define GPIO_AFRL_AFRL7_Pos (28U) -#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk - +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk + +/* Legacy aliases */ +#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos +#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos +#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos +#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos +#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos +#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos +#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos +#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos +#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0_Pos (0U) -#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk -#define GPIO_AFRH_AFRH1_Pos (4U) -#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk -#define GPIO_AFRH_AFRH2_Pos (8U) -#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk -#define GPIO_AFRH_AFRH3_Pos (12U) -#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk -#define GPIO_AFRH_AFRH4_Pos (16U) -#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk -#define GPIO_AFRH_AFRH5_Pos (20U) -#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk -#define GPIO_AFRH_AFRH6_Pos (24U) -#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk -#define GPIO_AFRH_AFRH7_Pos (28U) -#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk + +/* Legacy aliases */ +#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos +#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos +#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos +#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos +#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos +#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos +#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos +#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos +#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 (0x00000001U) @@ -8169,99 +8219,99 @@ typedef struct /***************** Bit definition for RCC_APB2RSTR register ****************/ #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ -#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ #define RCC_APB2RSTR_USART6RST_Pos (5U) #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ -#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 clock reset */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ #define RCC_APB2RSTR_USART7RST_Pos (6U) #define RCC_APB2RSTR_USART7RST_Msk (0x1U << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */ -#define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 clock reset */ +#define RCC_APB2RSTR_USART7RST RCC_APB2RSTR_USART7RST_Msk /*!< USART7 reset */ #define RCC_APB2RSTR_USART8RST_Pos (7U) #define RCC_APB2RSTR_USART8RST_Msk (0x1U << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */ -#define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 clock reset */ +#define RCC_APB2RSTR_USART8RST RCC_APB2RSTR_USART8RST_Msk /*!< USART8 reset */ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ -#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ -#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ -#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ -#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_TIM15RST_Pos (16U) #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ -#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ -#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ -#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ #define RCC_APB2RSTR_DBGMCURST_Pos (22U) #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ -#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */ +#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ -/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */ +/*!< Old ADC1 reset bit definition maintained for legacy purpose */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /***************** Bit definition for RCC_APB1RSTR register ****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ -#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ -#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ -#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ -#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ -#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */ +#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ -#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ -#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ -#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ -#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 clock reset */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART4RST_Pos (19U) #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ -#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 clock reset */ +#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ #define RCC_APB1RSTR_USART5RST_Pos (20U) #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ -#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 clock reset */ +#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ -#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ -#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_CANRST_Pos (25U) #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ -#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN clock reset */ +#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ #define RCC_APB1RSTR_CRSRST_Pos (27U) #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */ -#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */ +#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ -#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */ #define RCC_APB1RSTR_CECRST_Pos (30U) #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ -#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */ +#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC reset */ /****************** Bit definition for RCC_AHBENR register *****************/ #define RCC_AHBENR_DMAEN_Pos (0U) @@ -8480,28 +8530,28 @@ typedef struct /******************* Bit definition for RCC_AHBRSTR register ***************/ #define RCC_AHBRSTR_GPIOARST_Pos (17U) #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ -#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */ +#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ #define RCC_AHBRSTR_GPIOBRST_Pos (18U) #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ -#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */ +#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ #define RCC_AHBRSTR_GPIOCRST_Pos (19U) #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ -#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */ +#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ #define RCC_AHBRSTR_GPIODRST_Pos (20U) #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ -#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */ +#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ #define RCC_AHBRSTR_GPIOERST_Pos (21U) #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */ -#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE clock reset */ +#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */ #define RCC_AHBRSTR_GPIOFRST_Pos (22U) #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ -#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */ +#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ #define RCC_AHBRSTR_TSCRST_Pos (24U) #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ -#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */ +#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS reset */ /* Old Bit definition maintained for legacy purpose */ -#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ +#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS reset */ /******************* Bit definition for RCC_CFGR2 register *****************/ /*!< PREDIV configuration */ @@ -8729,9 +8779,9 @@ typedef struct #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -8775,6 +8825,11 @@ typedef struct #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +/* Legacy defines */ +#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos +#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk +#define RTC_CR_BCK RTC_CR_BKP + /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ @@ -11673,6 +11728,9 @@ typedef struct #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM14) +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h index c222d694eff..e07f12b04f5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -112,11 +110,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.3 */ #define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h index 0e1378cd325..f654061771c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c index f60f6bc02c0..007513ecea0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c @@ -73,7 +73,7 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.Resolution = ADC_RESOLUTION_12B; obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; - obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; + obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; obj->handle.Init.LowPowerAutoWait = DISABLE; obj->handle.Init.LowPowerAutoPowerOff = DISABLE; obj->handle.Init.ContinuousConvMode = DISABLE; @@ -81,7 +81,7 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; + obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; __HAL_RCC_ADC1_CLK_ENABLE(); diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h index c6ebc7bd02c..fee640796f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h @@ -136,6 +136,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html b/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html deleted file mode 100644 index d64f3ec73f6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F0/device/Release_Notes_stm32f0xx_hal.html +++ /dev/null @@ -1,916 +0,0 @@ - -Release Notes for STM32F0xx HAL Drivers - -
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Release -Notes for STM32F0xx HAL Drivers

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Copyright -2016 STMicroelectronics

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Update History

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V1.5.0 -/ 04-November-2016

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation

HAL Drivers changes

  • - -Enhance HAL delay and time base implementation:
    • Add -new templates -stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c -and stm32f0xx_hal_timebase_tim_template.c which can be used to override -the native -HAL time base functions (defined as weak) to use either RTC or -Timer as time -base tick source. For more details about the usage of these drivers, -please refer to HAL\HAL_TimeBase examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0
    • HAL IWDG driver: Overall driver rework for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: Overall driver rework for better implementation
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • HAL TIM driver : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure

  • HAL Generic
    • Update HAL Driver compliancy with:
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)
      • MISRA -C 2004 rule 14.8 (the statement forming the body of a 'switch', -'while', 'do ... while', or 'for' statement shall be a compound -statement)
  • HAL IWDG
    • New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() -and HAL_IWDG_GetState() APIs
      • API functions are: 
        • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG -counter
        • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
    • Refer to the following example to identify the changes : IWDG_Reset, IWDG_WidowMode
  • HAL WWDG
    • New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() -and HAL_WWDG_GetState() APIs
      • Update HAL_WWDG_Refresh() API to remove counter parameter
      • New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt
      • API -functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), -HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()
    • Refer to the following example to identify the changes: WWDG_Example
  • HAL CEC
    • Overall driver rework with break of compatibility with HAL V1.4.0
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
      • Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC state information related to global Handle management and Tx Operations
      • Update CEC process to manage the new CEC states.
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
  • HAL UART/USART/IRDA/SMARTCARD
    • IRQ Handler global optimization 
    • New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT()
    • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
    • Polling management update:
      • The user Timeout value must be estimated for the overall process -duration
  • HAL SPI
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
      • Polling mode:
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data
      •  Interrupt mode:
        • Minimize access on SPI registers
      • All modes:
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
        • Update timeout management to check on global processes
        • Update error code management in all processes
    • Fix regression in polling mode:
      • Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()
    • Fix regression in interrupt mode:
      • Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()
      • Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()
    • Prevent data -packing mode in reception for STM32F030x6, STM32F030x8, -STM32F031x6, STM32F038xx, STM32F051x8 and STM32F058xx
  • HAL DMA
    • Global - driver code optimization to reduce memory footprint 
    • Add - new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to - register/unregister the different callbacks identified by the enum - typedef HAL_DMA_CallbackIDTypeDef
    • Add - new Error Code HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove - DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in - HAL_DMA_StateTypeDef
  • HAL RTC
    • Interrupt flag cleared before enabling the interrupt in HAL_RTCEx_SetWakeUpTimer_IT()
  • HAL I2C
    • Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()
    • Move I2C_NO_OPTION_FRAME in private section
    • Use CMSIS bit for compilation switch instead of product switch
    • Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)
    • Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer
    • On slave, reset LISTEN_TX state in case of direction change
    • Remove GCC warnings
  • HAL TIM
    • API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE -bit from TIMx_CR1 register
    • New -API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and  -__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit -from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers
    • Update TIM_SET_CAPTUREPOLARITY and TIM_RESET_CAPTUREPOLARITY definition to take into account CC4NP bit
    • Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()
  • HAL SMBUS
    • Update SMBUS_Master_ISR() and SMBUS_Slave_ISR() to ensure storage of last receive data
  • HAL - PCD 
    • Update - HAL_PCD_ActivateRemoteWakeup() and HAL_PCD_DeActivateRemoteWakeup() APIs - to add condition if LPM activated.
-

LL Drivers changes

  • LL GPIO
    • Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx serie)
  • LL_TIM
    • Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx serie)
  • LL_CRS
    • Update CRS_POSITION_XXX  definitions to use CMSIS definition instead of hardcoded values

V1.4.0 -/ 27-May-2016

  • First official release supporting the Low Level drivers for the STM32F0xx family:
    • Low Layer drivers APIs provide register level programming:
      they require deep knowledge of peripherals described in STM32F0xx Reference Manual.
    • Low Layer drivers are available for ADC, COMP, Cortex, CRC, CRS, DAC, DMA, EXTI, -GPIO, I2C, IWDG, PWR,
      RCC, RTC, SPI, TIM, USART and WWDG peripherals       and additional Low Level Bus, System and Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f0xx_ll_ppp.h files for PPP peripherals,
      there is no configuration file and each stm32f0xx_ll_ppp.h file must be included in user code.
  • Maintenance release to fix known defects and enhancements implementation.
  • HAL generic
    • Updated HAL Driver compliancy with MISRA C 2004 rules:
      • MISRA C 2004 rule 5.2 (tmpreg" variable shall not be used inside MACRO)
      • MISRA C 2004 rule 10.3 (illegal explicit conversion from type "unsigned int" to "uint16_t *).
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).
      • MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).
      • MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
      • MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself).
      • MISRA C 2004 rule 14.9 ('if {expression}' / 'else' construct shall be followed by a compound statement).
      • MISRA C 2004 rule 15.3 (all switch statements shall contain a final default clause).
      • MISRA C 2004 rule 16.3 (identifiers shall be given for all of the parameters in a function prototype declaration).
      • MISRA C 2004 rule 16.4 (identifiers used in the declaration and definition shall be identical).
      • MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis).
  • HAL
    • Changed uwTick to global to allow overwrite of HAL_IncTick().
  • HAL COMP
    • Added delay in COMP startup time required to reach propagation delay specification.
  • HAL CRC
    • Updated devices supporting Programmable Polynomial features: defines and functions prototypes are available only for
      STM32F071xB, STM32F072xB, STM32F078xx, STM32F091xC, STM32F098x devices.
    • Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).
  • HAL DMA
    • Added __HAL_DMA_GET_COUNTER() macro returning the number of remaining data units in the current DMA Channel transfer.
    • Provided -new function HAL_DMA_Abort_IT() to abort current DMA transfer -under interrupt mode without polling for DMA enable bit.
  • HAL GPIO
    • Updated IS_GPIO_PIN() macro to cover full u32 bits.
  • HAL I2C
    • Used macro definition for I2C instances supporting Wakeup from Stop mode.
    • Updated polling flags management within I2C slave DMA drivers.
    • Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).
    • Updated WaitOnFlag management (timeout measurement should be always cumulative).
    • Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).
    • Reworked DMA end process and I2C error management during DMA transfer.
  • HAL PWR
    • Aligned EWUPx pins and PWR functions with CMSIS definitions.
  • HAL IRDA
    • Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).
    • Updated IRDA_SetConfig() function following UART Baudrate calculation update.
    • Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ.
    • Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.
  • HAL RCC
    • Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.
    • Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).
    • Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.
    • Corrected CRS interrupt sources.
    • Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.
    • Added missing HAL IRQHandler and callbacks API for CRS management.
    • Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.
    • Removed HSI48State from structure RCC_OscInitTypeDef when device does not support HSI48.
    • Removed RCC_HSI48_OFF.
    • Removed flag RCC_FLAG_RMV which is write only.
    • Modified AHBPrescTable and APBPrescTable in HAL.
    • Renamed RCC_CRS_SYNCWARM to RCC_CRS_SYNCWARN.
    • Renamed RCC_CRS_TRIMOV to RCC_CRS_TRIMOVF.
  • HAL SPI
    • Updated HAL_SPI_TransmitReceive() function in slave mode to receive correctly the CRC when NSS pulse activated.
    • Added missing __IO in SPI_HandleTypeDef definition.
    • Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.
    • Updated -SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added -return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC() -function is called from HAL_SPI_TransmitReceive_IT() when CRC is -activated.
  • HAL TIM
    • Used IS_TIM_HALL_INTERFACE_INSTANCE macro instead of IS_TIM_XOR_INSTANCE macro in
      HAL_TIMEx_HallSensor_xxx() functions.
    • Updated HAL_TIM_ConfigOCrefClear() function to allow TIM_CLEARINPUTSOURCE_OCREFCLR as new ClearInputSource.
  • HAL UART-USART
    • Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).
    • Updated USART_SetConfig() function following UART Baudrate calculation update.
    • Aligned UART-USART Stop Bits with others STM32 series.
    • Renamed IS_UART_WAKEUP_INSTANCE to IS_UART_WAKEUP_FROMSTOP_INSTANCE.
    • Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ.
    • Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.
  • HAL USB
    • Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.
    • Added missing USB_CNTR_SOFM when setting wInterrupt_Mask global variable used in HAL_PCD_Init.
  • HAL SMARTCARD
    • Aligned SMARTCARD Stop Bits with others STM32 series.
    • Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.
    • Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ.

V1.3.1 -/ 29-January-2016

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation
  • HAL Generic
    • Updated HAL Driver compliancy with:
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
    • Updated HAL weak empty callbacks to prevent unused argument compilation warnings.
    • Updated stm32f3xx_hal_msp.c files:
      • Removed reference to MicroXplorer.
    • Updated stm32f3xx_hal_conf.h files:
      • Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms
  • HAL ADC
    • Corrected ADC_CHANNEL_VREFINT enabling in the CCR register.
    • Corrected assert param of nb of discontinuous conversions when discontinuous mode is enabled.
    • Removed Flag EOS in HAL_ADC_GetValue().
  • HAL CAN
    • Corrected missing __HAL_UNLOCK when all Mailboxes are busy.
    • Added ERRI bit clear besides to clearing LEC bits in CAN_ESR register, in case of Error interrupt.
  • HAL CORTEX
    • Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.
  • HAL CRC
    • Updated CRC HAL_CRC_Calculate() and HAL_CRC_Accumulate() comments, handling input data pointers that are not * uint32_t.
  • HAL FLASH
    • Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.
    • Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.
  • HAL GPIO
    • Updated GPIO Output Speed literals naming to ensure HAL full compatibility.
    • Added GPIOD support for STM32070x6 devices.
    • Modified ADC poll for event to return timeout instead of error.
  • HAL I2C
    • Corrected wrong management of AF after NACK.
    • Aligned I2C driver with new state machine definition.
    • Corrected interrupt disabling in I2C_SlaveReceive_ISR() function.
    • Modified HAL_I2C_Master_Transmit to handle sending data of size 0.
    • Renamed I2C_CR1_DFN to I2C_CR1_DNF.
  • HAL PCD
    • Updated call to Double Buffering Counter Function.
  • HAL PWR
    • Added do { } while(0) in __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() multi statement macro.
  • HAL RCC
    • Performed optimizations for HAL_RCC_ClockConfig() function.
    • Corrected invertion in LSE drive capability Bit definition.
    • Performed optimizations for internal oscillators and PLL startup time.
    • Added GPIOD support for STM32070x6 devices.
    • Removed GPIOE support for STM32F030xC devices.
    • Add RCC_USBCLKSOURCE_NONE when HSI48 is not present.
    • Corrected definition for flag RCC_FLAG_V18PWRRST.
    • Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.
    • Aligned naming of macros related to CRS_CFGR register.
    • Corrected __HAL_RCC_CRS_CLEAR_IT()/__HAL_RCC_CRS_CLEAR_FLAG() macros.
    • Removed Bit PLLNODIV for STM32F030x6 devices.
    • Review implementation to automatically enable backup domain.
    • Added RCC_IT_HSI48RDY definition.
    • Renamed __HAL_RCC_MCO_CONFIG() to __HAL_RCC_MCO1_CONFIG().
  • HAL RTC
    • Aligned different HAL_RTC_XXIRQHandler() implementations.
    • Check the behavior of flag WUTWF and corrected update of wakeup counter registers.
    • Added subsecond fration formula in HAL_RTC_GetTime() function.
    • Updated Bits mask literals used in macros definition.
  • HAL TIM
    • Corrected __HAL_TIM_SET_PRESCALER timer prescaler definition.
    • Protected SMCR register of possible overwrite in HAL_TIM_ConfigOCrefClear().
    • Corrected assert checks in HAL_TIM_ConfigClockSource().
  • HAL TSC
    • Updated IO default state management.
  • HAL UART-USART
    • Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).
    • Corrected UART_FLAG_SBKF definition.
    • Corrected values used for max allowed baudrates constant definitions.
    • Removed -USART_CR2_LINEN/USART_CR3_IREN/USART_CR3_SCEN/USART_CR1_UESM bits -definitions for STM32F030x6, STM32F030x8, STM32F070xB, STM32F070x6, -STM32F030xC.
  • HAL WWDG
    • Aligned WWDG registers Bits naming between all families.

V1.3.0 -/ 26-June-2015

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation
  • Complete HAL API alignment (macro/function renaming)
  • HAL Generic
    • Update HAL drivers to be MISRA/C++ compliant.
    • Initialized handle lock in HAL_PPP_Init().
    • Add SYSCFG define macros to manage FM+ on GPIOs.
    • Use uint32_t instead of uint8_t/uint_16.
  • HAL ADC
    • Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().
    • Align ADC_SOFTWARE_START literal on STM32L0xx.
    • HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.
    • HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.
    • ADC_ConversionStop(): correct wrong timeout value.
    • HAL_ADC_AnalogWDGConfig(): Add missing assert param.
    • Remove channel for monitoring VBAT power supply pin on F0 Value line devices.
    • Move -sampling time setting into ADC init stucture (keep setting into ADC -channel init stucture with comments of obsolete setting).
    • Move -__HAL_UNLOCK() before peripheral activation because if an interruption -occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be -executed while HAL still locked.
    • ADC_DMAConvCplt(): Add call to ADC error callback in case of error.
    • Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).
    • Simplify __HAL_ADC_GET_IT_SOURCE().
    • Add use of POSITION_VAL.
    • Add optimization of ADC stabilization delays.
  • HAL CAN 
    • Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().
    • Unlock the CAN process when communication error occurred.
    • Replace “uint32_t Data[8]” by “uint8_t Data[8]” in structures  CanTxMsgTypeDef and CanRxMsgTypeDef.
  • HAL CEC 
    • Add new API HAL_CEC_GetReceivedFrameSize() to get size of received frame
  • HAL CORTEX 
    • Add new macro IS_NVIC_DEVICE_IRQ() to -check on negative values of IRQn parameter
  • HAL CRC 
    • Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().
    • Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).
  • HAL DAC 
    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and -DAC_FLAG_DMAUDR2.
  • HAL DMA
    • Correct __HAL_DMA_GET_IT_SOURCE brief comments.
  • HAL FLASH
    • FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • Add missing macro __HAL_FLASH_GET_LATENCY.
    • Disable WRP not compliant with other family.
    • Add FLASH_BANK1_END defines.
    • Remove WRP defines for few defines under devices swicthes.
    • Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.
  • HAL GPIO 
    • stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.
  • HAL I2C
    • HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.
  • HAL I2S
    • HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.
  • HAL IRDA
    • HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL PWR
    • Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.
    • Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.
  • HAL RCC
    • Implement workaround to cover RCC limitation regarding Peripheral enable delay.
    • HAL_RCC_OscConfig(): correct test on LSEState.
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.
    • Add defines for RCC_System_Clock_Source_Status.
    • Follow specific procedure to enable HSE.
    • Add macros to get the enable or disable status of peripheral clock.
    • HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.
    • Add interface HAL_RCCEx_GetPeriphCLKFreq.
  • HAL RTC
    • Add missing RTC_FLAG_INIT in flag list.
    • HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).
    • Remove RTC_FLAG_INIT as currently unused.
  • HAL SMARTCARD
    • Add missing IDLE flag management.
    • Align SMARTCARD_Last_Bit defines.
  • HAL SPI 
    • Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().
      In -that case only RX callback are used and the call of TX callback can -close the communication before the end of the RX processing.
    • SPI_2linesRxISR_8BIT(): -correct issue on RX 2lines with DataSize8bit, even buffer size and CRC -8bit (SPI_RXFIFO_THRESHOLD is not set).
    • Fit bit update add BSY flag check for all the process.
    • Add -__IO (volatile) to the "State" member of the SPI_HandleTypeDef -struct. to missing reset of the Dma Tx callback inside the -function -HAL_SPI_TransmitReceive_DMA().
  • HAL TIM
    • Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.
  • HAL UART
    • Add macro to control CTS and RTS from the customer applications.
    • UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.
    • Change DMA TX management to remove WaitOnFlag in ISR.
    • Add DMA circular mode support for the communication peripherals.
    • Add UART NVIC configuration in the HAL_UART_MspInit().
    • Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.
    • Modify UART DMA implementation issue (missed clear the TC bit in the SR).
    • Add a OVR flag clear prior resuming DMA RX transfer.
    • HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).
    • HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.
    • HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL USART
    • HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().
    • Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.
    • HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).
    • HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.
    • HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).
    • HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.

V1.2.1 -/ 09-January-2015

  • HAL 
    • stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only
  • HAL GPIO
    • stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB
  • HAL RCC
    • stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for STM32F070x6
  • HAL RTC -
    • stm32f0xx_hal_rtc_ex.h/.c: -Enable RTC periodic Wakeup timer feature on STM32F070xB -& STM32F030xC -
    • stm32f0xx_hal_rtc_ex.c: -remove HAL_RTCEx_Tamper3EventCallback() -API for STM32F070xB -& STM32F030xC, since -there is no TAMPER3 on those products.
    -
  • HAL UART -
    • stm32f0xx_hal_uart_ex.c/.h: -add HAL_RS485Ex_Init() API for STM32F0xx Value -Line devices

V1.2.0 -/ 05-December-2014

Main -Changes

-
  • HAL generic 
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • HandleTypeDef.ErrorCode must be typed uint32_t
    • Update HAL drivers to ensure compliancy w/ C++
    • Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h
    • Case mismatch between #include typo and effective file name generating compiler errors under Linux
    • Correct various issues for documentation generation (group name, doxygen tags, etc..)
    • Missing support of I2C_PAx_FMP of F04xx devices

  • HAL ADC 

    • Improve HAL ADC comments
    • Correct issue observed with ADC start simultaneous commands
    • Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices.
  • HAL CAN 
    • ErrorCode field is now declared as __IO uint32 instead of enum HAL_CAN_ErrorTypeDef to fix C++ compilation issue

  • HAL CEC 

    • change ErrorCode field declaration from uint32_t  to __IO uint32_t

    • correct CEC state: Ready to Receive state lost upon Transmission end

  • HAL COMP 
    • State field is now declared as uint32_t instead of enum HAL_COMP_StateTypeDef to fix C++ compilation issue
    • change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue

  • HAL CRC 

    • Wrong @ref in CRCLength field description for documentation generation 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.

  • HAL DAC 

    • HAL_DAC_Stop_DMA() code clean up

    • Use of internal macro MODIFY_REG() to update CR register

  • HAL DMA 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • DMA channel remap register renamed for compatibility with other STM32 devices.
    • Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description
  • HAL FLASH 
    • Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected
    • ErrorCode field is now declared as uint32 instead of enum FLASH_ErrorTypeDef to fix C++ compilation issue
    • change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue
    • Clean the error context to FLASH_ERROR_NONE before starting new Flash operation
    • Put all the clear flags in the FLASH_SetSerrorCode()
    • Stop the programming procedure in case of error detected in HAL_FLASH_Program()
    • Check error before doing new procedure in HAL_FLASH_IRQhandler()

  • HAL GPIO 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • correct Typo in 'How to use this driver' section & update comments
    • Add assert on GPIO PIN in HAL_GPIO_DeInit()
    • Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration
    • Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()
    • Reset Interrupt mode registers only in HAL_GPIO_DeInit()
  • HAL I2C
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • ErrorCode field is now declared as uint32 instead of enum HAL_I2C_ErrorTypeDef to fix C++ compilation issue

  • HAL I2S 

    • ErrorCode field is now declared as uint32 instead of enum HAL_I2S_ErrorTypeDef to fix C++ compilation issue.
    • Change HAL_I2S_GetError() type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue.
    • Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable" warning w/ TrueSTUDIO.
    • Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c
    • Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)

  • HAL IRDA 

    • ErrorCode field is now declared as uint32 instead of enum HAL_IRDA_ErrorTypeDef to fix C++ compilation issue
    • Missing doxygen tags for IRDA_HandleTypeDef fields description

  • HAL PWR 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register:
  • HAL_PWR_DisableSleepOnExit()
  • HAL_PWR_EnableSleepOnExit()
  • HAL_PWR_EnableSEVOnPend()
  • HAL_PWR_DisableSEVOnPend()
    • Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()

  • HAL RCC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay
    • Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_rcc_ex.h since this feature is not supported on all F0 devices
    • Change HAL_RCCEx_CRSWaitSynchronization() type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue

  • HAL RTC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Enhance @note describing the use of HAL RTC APIs 
  • HAL SMARTCARD
    • ErrorCode field is now declared as uint32 instead of enum HAL_SMARTCARD_ErrorTypeDef to fix C++ compilation issue
  • HAL SMBUS
    • ErrorCode & PreviousState fields are now declared as uint32 instead of enum HAL_SMBUS_ErrorTypeDef & HAL_SMBUS_StateTypeDef to fix C++ compilation issue
    • Change HAL_SMBUS_GetState() type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue

  • HAL SPI 

    • ErrorCode field is now declared as uint32 instead of enum HAL_SPI_ErrorTypeDef to fix C++ compilation issue
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning w/ TrueSTUDIO.
    • Add DMA circular mode support on SPI HAL driver.
    • Internal -fucntion renaming: HAL_SPI_DMATransmitCplt(), -HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & -HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().
    • Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype
    • uint32_t driver alignment for compatibility with other STM32 devices
    • Add new API HAL_SPI_GetError(), which was missing on STM32F0xx family

  • HAL UART/USART 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.
    • ErrorCode field is now declared as uint32 instead of enum HAL_U(S)ART_ErrorTypeDef to fix C++ compilation issue
    • unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h
    • Add missing API HAL_StatusTypeDef HAL_LIN_SendBreak()
    • correct wrong USART_IT_CM value
    • correct issue with Lin mode data length
    • Add new value for Stop bit definition: UART_STOPBITS_1_5

  • HAL USB 

    • Add support of new STM32F0 value line devices STM32F070xB/x6.
    • Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description
    • Correct _HAL_PCD_CLEAR_FLAG() macros definition

  • HAL WWDG 

    • Add new macro to manage WWDG IT & correction:

      • __HAL_WWDG_DISABLE_IT()
      • __HAL_WWDG_GET_IT()
      • __HAL_WWDG_GET_IT_SOURCE()

V1.1.0 -/ 03-October-2014

Main -Changes

-
  • HAL generic 
    • general improvement of Doxygen Tags for CHM UM generation
    • Add support of new devices STM32F091xC, STM32F098xx in STM32F0xx HAL drivers
    • minor corrections for Pdf/Chm UM generation
    • Correction for MISRA 
    • [F098xx] Remove PVD IT line wrapper
    • FLAG&IT assert macros to be removed
    • Bad macro name in stm32F0xx_hal.c/.h files
    • uint32_t Alignement in HAL driver
  • HAL update (for STM32F091xC/STM32F098xx)
    • Add new define for HAL IRDA Enveloppe source Selection
    • Add new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()
    • Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)
    • Add new macro __HAL_GET_PENDING_IT()
    • Add new macro __HAL_SYSCFG_IRDA_ENV_SELECTION()
    • Add new macro __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()

  • HAL COMP 

    • Missing assert param IS_COMP_TRIGGERMODE

  • HAL Cortex 

    • remove Macro not supported by cortex-M0 in stm32f0xx.h

  • HAL DMA 

    • Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)
    • Add new defines for DMAx channels remap bit field definition
    • Add new macros: IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()
    • Add new macro: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index
    • Add new macro: __HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index
    • Add new macro: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index
    • Add new macro: __HAL_DMA_GET_FLAG()
    • Add new macro: __HAL_DMA_CLEAR_FLAG()
    • Add new macro: __HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()
    • Bit definition name error for HAL_DMA1_CH2 remap on STM32F091xC
    • HAL_DMA_PollForTransfer updated

  • HAL GPIO 

    • BSRR regsiter should not be split in BSRRH/BSRRL
    • rework GPIO_GET_SOURCE
    • Add new defines for AF functions selection

  • HAL I2S 

    • Supp ClockSource in Init

  • HAL IRDA 

    • Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro

  • HAL IWDG 

    • Use WRITE_REG instead of SET_BIT

  • HAL PWR 

    • Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx

    • PVD feature need falling/rising Event modes
      • Update defines name PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING to PWR_PVD_MODE_NORMAL/PWR_PVD_MODE_IT_RISING/PWR_PVD_MODE_IT_FALLING/PWR_PVD_MODE_IT_RISING_FALLING
      • Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING
      • Update macro IS_PWR_PVD_MODE()
      • change macro name: __HAL_PWR_PVD_EXTI_ENABLE_IT(), __HAL_PWR_PVD_EXTI_DISABLE_IT(), __HAL_PWR_PVD_EXTI_GENERATE_SWIT(), __HAL_PWR_PVD_EXTI_GET_FLAG(),  __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
      • Add -new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(), -__HAL_PWR_PVD_EXTI_DISABLE_EVENT(), -__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(), -__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()
  • HAL RCC 
    • Defect correction:
      • HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode
      • STM32F091xC/STM32F098xx
        • New structure RCC_PeriphCLKInitTypeDef
        • Add -defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1, -RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC, -RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3
        • Add macro IS_RCC_PERIPHCLK()
        • Add -defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1, -RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE, -CC_USART3CLKSOURCE_HSI
        • Add macro IS_RCC_USART3CLKSOURCE()
        • Add macro __HAL_RCC_GET_USART3_SOURCE()
        • Add macro __HAL_RCC_USART3_CONFIG()
        • add clock enable macros for new UART: __USART5_CLK_ENABLE,  __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE
        • add clock disable macros for new UART: __USART5_CLK_DISABLE,  __USART6_CLK_DISABLE, __USART7_CLK_DISABLE, __USART8_CLK_DISABLE
        • add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET
        • add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_RELEASE_RESET, __USART7_RELEASE_RESET, __USART8_RELEASE_RESET 

  • HAL SMARTCARD 

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR

  • HAL SMBUS  

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function

  • HAL SPI 

    • Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC

    • Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready

  • HAL TIM 

    • Missed/Unused assert param to be added/removed
    • Trigger interrupt should be activated when working with a slave mode
    • Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT
    • Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4
    • missing assert in HAL_TIMEx_ConfigBreakDeadTime
    • Add URS_ENABLE/ URS_DISABLE macros

  • HAL UART/USART 

    • Change UART TX-IT implementation to remove WaitOnFlag in ISR
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4
      • Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4

  • HAL USB 

    • Bad IN/OUT EndPoint parameter array size

  • HAL WWDG 

    • improvements from other families

Defect Correction

 - - - - - - - - - - - - - - - - - - - - - - - - -
-

STM32F0xx_HAL_Driver

- 		-

Defect

- 		-

PWR

- 		-

PVD feature need falling/rising Event modes

-
-

STM32F0xx_HAL_Driver

- 		-

Defect

- 		-

COMP

- 		-

Missing assert param IS_COMP_TRIGGERMODE 

-
-

STM32F0xx_HAL_Driver

- 		-

Defect

- 		-

RCC

- 		-

HAL_RCC_OscConfig: HSERDY has to be checked also in by - pass mode

-
-

V1.0.1 -/ 18-June-2014

Main -Changes

-
  • - - - - - - - -

    HAL generic update

    • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
    • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait.
    • Add -new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.

  • HAL CEC update

    • Process no more locked during the transmission in interrupt mode. 

  • HAL COMP update

    • Add NonInvertingInput field in the COMP_InitTypeDef structure.
    • Add new defines COMP_NONINVERTINGINPUT_IO1 and COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED

  • HAL DMA update

    • Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status
  • - - - - - - - -

    HAL I2C update

    • Add -management of NACK event in Master transmitter mode and Slave -transmitter/receiver modes (only in polling mode), in that case the -current transfer is stopped.

  • HAL I2S update

    • I2S clock source change: new define I2S_CLOCK_SYSCLK, remove I2S_CLOCK_PLL
    • Improvement done in I2S transfer/receive processes

  • HAL IRDA update

    • Add new enum typedef IRDA_ClockSourceTypeDef
    • Add new macro __HAL_IRDA_GETCLOCKSOURCE
    • Change in HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • -

    HAL PCD update

    -
    • -

      Add new macro __HAL_USB_EXTI_GENERATE_SWIT

      -

  • HAL PWR update

    • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function

  • HAL RCC update

    • Add USB peripheral and clocking macros for STM32F078xx device.
    • Fix HSI Calibration issue when selected as SYSCLK
  • - - - - - - - -

    HAL SMARTCARD update

    • Change in HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.
    • Process no more locked during the transmission in interrupt mode.

  • HAL SMBUS update

    • Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack

  • HAL TIM update

    • Fix macro __HAL_TIM_PRESCALER

  • HAL TSC update

    • Fix define TSC_ACQ_MODE_SYNCHRO
  • - - - - - - - -

    HAL UART update

    • Change in HAL_LIN_Init() parameter BreakDetectLength to uint32_t
    • Change in HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.

  • HAL USART update

    • Change USART_InitTypeDef fields to uint32_t type
    • Rename __USART_ENABLE and __USART_DISABLE macros to respectively __HAL_USART_ENABLE and __HAL_USART_DISABLE
    • Change in HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
    • Change in HAL_USART_TransmitReceive_DMA() to manage DMA half transfer mode

V1.0.0 -/ 20-May-2014

-

Main -Changes

-
  • First official -release of STM32F0xx HAL drivers for STM32F030x4/x6, STM32F030x8, STM32F031x4/x6,  STM32F051x4/x6/x8,  STM32F071x8/xB,  STM32F042x4/x6, -STM32F072x8/xB,  STM32F038xx, - STM32F048xx, STM32F058xx and STM32F078xx -devices.

License

-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- -
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h index 647f238bbf8..5c80466c633 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 + * @version V1.8.1 + * @date 14-April-2017 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -138,7 +138,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -265,7 +267,6 @@ #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 @@ -457,6 +458,78 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE + + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + + +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -670,7 +743,6 @@ #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE @@ -678,9 +750,6 @@ #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT @@ -1312,7 +1381,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1785,20 +1853,20 @@ #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1815,7 +1883,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2410,7 +2478,6 @@ #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE @@ -2443,8 +2510,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2466,8 +2531,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2692,7 +2755,10 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32WB) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2788,7 +2854,6 @@ #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c index 2060122aca9..bb588b4aa74 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -70,10 +68,10 @@ * @{ */ /** - * @brief STM32F0xx HAL Driver version number V1.5.0 + * @brief STM32F0xx HAL Driver version number V1.7.0 */ #define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ #define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ @@ -232,7 +230,7 @@ __weak void HAL_MspDeInit(void) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __Weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) @@ -307,14 +305,21 @@ __weak uint32_t HAL_GetTick(void) * is incremented. * @note ThiS function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(__IO uint32_t Delay) { - uint32_t tickstart = 0U; - tickstart = HAL_GetTick(); - while((HAL_GetTick() - tickstart) < Delay) + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait++; + } + + while((HAL_GetTick() - tickstart) < wait) { } } @@ -379,6 +384,33 @@ uint32_t HAL_GetDEVID(void) return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @brief Enable the Debug Module during STOP mode * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h index 7f02a7db9a9..e9747eeadb0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -378,7 +376,7 @@ #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) /** @defgroup HAL_Pin_remap HAL Pin remap * @brief Pin remapping enable/disable macros - * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping + * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping * @{ */ #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ @@ -393,7 +391,7 @@ #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ /** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. * That you can find above these macros. */ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ @@ -482,7 +480,7 @@ /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register * @note This feature is applicable on STM32F09x - * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL + * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL * @{ */ #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ @@ -532,6 +530,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c index 445e48e966c..a94fe6d8011 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_adc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -355,7 +353,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma); * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) @@ -581,7 +579,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) * bypassed without error reporting: it can be the intended behaviour in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) @@ -697,7 +695,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initializes the ADC MSP. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) @@ -712,7 +710,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitializes the ADC MSP. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) @@ -754,7 +752,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) @@ -819,7 +817,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /** * @brief Stop ADC conversion of regular group, disable ADC peripheral. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) @@ -872,8 +870,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -988,12 +986,12 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /** * @brief Poll for conversion event. - * @param hadc: ADC handle - * @param EventType: the ADC event type. + * @param hadc ADC handle + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog event * @arg ADC_OVR_EVENT: ADC Overrun event - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -1069,7 +1067,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * parameter "EOCSelection" * - overrun (if available) * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) @@ -1150,7 +1148,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /** * @brief Stop ADC conversion of regular group, disable interruption of * end-of-conversion, disable ADC peripheral. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) @@ -1201,9 +1199,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * - DMA half transfer * - overrun * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param hadc ADC handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1292,7 +1290,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable * ADC peripheral. * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) @@ -1374,7 +1372,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) @@ -1391,7 +1389,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Handles ADC interrupt request. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) @@ -1507,7 +1505,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Conversion complete callback in non blocking mode - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) @@ -1522,7 +1520,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Conversion DMA half-transfer callback in non blocking mode - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) @@ -1537,7 +1535,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog callback in non blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) @@ -1553,7 +1551,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief ADC error callback in non blocking mode * (ADC conversion with interruption or transfer by DMA) - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) @@ -1606,8 +1604,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel for regular group. + * @param hadc ADC handle + * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1739,8 +1737,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @param hadc: ADC handle - * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) @@ -1862,7 +1860,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * For example: * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL state */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) @@ -1876,7 +1874,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC Error Code */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) @@ -1906,7 +1904,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * flag ADC_FLAG_RDY is not usable. * Therefore, this function must be called under condition of * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) @@ -1971,7 +1969,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) @@ -2028,7 +2026,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) * @brief Stop ADC conversion. * @note Prerequisite condition to use this function: ADC conversions must be * stopped to disable the ADC. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) @@ -2079,7 +2077,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) @@ -2140,7 +2138,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2154,7 +2152,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h index abb05a25dfc..9addcb7696d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_adc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -332,7 +330,6 @@ typedef struct */ #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ /** * @} */ @@ -463,7 +460,7 @@ typedef struct /** * @brief Enable the ADC peripheral - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) \ @@ -471,7 +468,7 @@ typedef struct /** * @brief Disable the ADC peripheral - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) \ @@ -482,8 +479,8 @@ typedef struct /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source @@ -498,8 +495,8 @@ typedef struct /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source @@ -513,8 +510,8 @@ typedef struct (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC interrupt source to check + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source @@ -529,8 +526,8 @@ typedef struct /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag @@ -545,8 +542,8 @@ typedef struct /** * @brief Clear the ADC's pending flags - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag @@ -561,7 +558,7 @@ typedef struct (((__HANDLE__)->Instance->ISR) = (__FLAG__)) /** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ @@ -583,7 +580,7 @@ typedef struct /** * @brief Verification of hardware constraints before ADC can be enabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) */ #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ @@ -594,7 +591,7 @@ typedef struct /** * @brief Verification of hardware constraints before ADC can be disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) */ #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ @@ -604,7 +601,7 @@ typedef struct /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ @@ -619,7 +616,7 @@ typedef struct /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -627,7 +624,7 @@ typedef struct /** * @brief Check if no conversion on going on regular group - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ @@ -637,7 +634,7 @@ typedef struct /** * @brief Returns resolution bits in CFGR1 register: RES[1:0]. * Returned value is among parameters to @ref ADC_Resolution. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) \ @@ -646,7 +643,7 @@ typedef struct /** * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. * Returned value is among parameters to @ref ADC_Resolution. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_SAMPLINGTIME(__HANDLE__) \ @@ -663,7 +660,7 @@ typedef struct /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -672,7 +669,7 @@ typedef struct /** * @brief Configure the channel number into channel selection register - * @param _CHANNEL_: ADC Channel + * @param _CHANNEL_ ADC Channel * @retval None */ /* This function converts ADC channels from numbers (see defgroup ADC_channels) @@ -702,7 +699,7 @@ typedef struct /** * @brief Set the ADC's sample time - * @param _SAMPLETIME_: Sample time parameter. + * @param _SAMPLETIME_ Sample time parameter. * @retval None */ /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ @@ -715,7 +712,7 @@ typedef struct /** * @brief Set the Analog Watchdog 1 channel. - * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. + * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. * @retval None */ #define ADC_CFGR_AWDCH(_CHANNEL_) \ @@ -723,7 +720,7 @@ typedef struct /** * @brief Enable ADC discontinuous conversion mode for regular group - * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. + * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. * @retval None */ #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ @@ -731,7 +728,7 @@ typedef struct /** * @brief Enable the ADC auto off mode. - * @param _AUTOOFF_: Auto off bit enable or disable. + * @param _AUTOOFF_ Auto off bit enable or disable. * @retval None */ #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ @@ -739,7 +736,7 @@ typedef struct /** * @brief Enable the ADC auto delay mode. - * @param _AUTOWAIT_: Auto delay bit enable or disable. + * @param _AUTOWAIT_ Auto delay bit enable or disable. * @retval None */ #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ @@ -747,7 +744,7 @@ typedef struct /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ @@ -755,7 +752,7 @@ typedef struct /** * @brief Enable ADC overrun mode. - * @param _OVERRUN_MODE_: Overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. * @retval Overun bit setting to be programmed into CFGR register */ /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ @@ -768,7 +765,7 @@ typedef struct /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. - * @param _SCAN_MODE_: Scan conversion mode. + * @param _SCAN_MODE_ Scan conversion mode. * @retval None */ /* Note: Scan mode set using this macro (instead of parameter direct set) */ @@ -782,7 +779,7 @@ typedef struct /** * @brief Enable the ADC DMA continuous request. - * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @param _DMACONTREQ_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ @@ -790,7 +787,7 @@ typedef struct /** * @brief Configure the analog watchdog high threshold into register TR. - * @param _Threshold_: Threshold value + * @param _Threshold_ Threshold value * @retval None */ #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ @@ -804,8 +801,8 @@ typedef struct * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) - * @param __HANDLE__: ADC handle - * @param _Threshold_: Value to be shifted + * @param __HANDLE__ ADC handle + * @param _Threshold_ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ @@ -833,8 +830,7 @@ typedef struct ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ - ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) ) + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c index d3061241fb4..a3408d9d4f5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.c @@ -2,15 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Calibration (ADC automatic self-calibration) * Other functions (generic functions) are available in file - * "stm32l1xx_hal_adc.c". + * "stm32f0xx_hal_adc.c". * @verbatim [..] @@ -109,13 +107,14 @@ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @note Calibration factor can be read after calibration, using function * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tickstart=0U; + uint32_t tickstart = 0U; + uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -131,6 +130,15 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); + /* Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 serie: Calibration factor is */ + /* available in data register and also transfered by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + /* Start ADC calibration */ hadc->Instance->CR |= ADC_CR_ADCAL; @@ -153,6 +161,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) } } + /* Restore ADC DMA transfer request after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h index c7dec724ce5..04d2438359e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of ADC HAL Extension module. ****************************************************************************** * @attention @@ -153,7 +151,7 @@ * VrefInt/TempSensor/Vbat * Note: On STM32F0, availability of internal channel Vbat depends on * devices lines. - * @param __CHANNEL__: ADC channel + * @param __CHANNEL__ ADC channel * @retval None */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) @@ -175,7 +173,7 @@ * VrefInt/TempSensor/Vbat. * Note: On STM32F0, availability of internal channel Vbat depends on * devices lines. - * @param __CHANNEL__: ADC channel + * @param __CHANNEL__ ADC channel * @retval Bit of register ADC_CCR */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c index 715f4fbb649..17dede7d5e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_can.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -28,9 +26,13 @@ (#) Initialise and configure the CAN using HAL_CAN_Init() function. (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. - + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + *** Polling mode IO operation *** ================================= [..] @@ -157,10 +159,10 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); */ /** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) @@ -200,18 +202,18 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) hcan->State = HAL_CAN_STATE_BUSY; /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -221,95 +223,97 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) } /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) { /* Set the time triggered communication mode */ if (hcan->Init.TTCM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_TTCM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } /* Set the automatic bus-off management */ if (hcan->Init.ABOM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_ABOM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } /* Set the automatic wake-up mode */ if (hcan->Init.AWUM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_AWUM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } /* Set the no automatic retransmission */ if (hcan->Init.NART == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_NART; + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } /* Set the receive FIFO locked mode */ if (hcan->Init.RFLM == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_RFLM; + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } /* Set the transmit FIFO priority */ if (hcan->Init.TXFP == ENABLE) { - hcan->Instance->MCR |= CAN_MCR_TXFP; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } else { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1U); + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SJW | + hcan->Init.BS1 | + hcan->Init.BS2 | + (hcan->Init.Prescaler - 1U) )); /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State= HAL_CAN_STATE_TIMEOUT; + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + + return HAL_TIMEOUT; } } /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) { status = CAN_INITSTATUS_SUCCESS; } @@ -339,15 +343,15 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /** * @brief Configures the CAN reception filter according to the specified * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that + * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { - uint32_t filternbrbitpos = 0; + uint32_t filternbrbitpos = 0U; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); @@ -360,81 +364,80 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy filternbrbitpos = (1U) << sFilterConfig->FilterNumber; /* Initialisation mode for the filter */ - hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT; - /* Select the start slave bank */ - hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - hcan->Instance->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); - - /* Filter Deactivation */ - hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos; + MODIFY_REG(hcan->Instance->FMR , + CAN_FMR_CAN2SB , + CAN_FMR_FINIT | + (uint32_t)(sFilterConfig->BankNumber << 8U) ); /* Filter Deactivation */ + CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos); /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { /* 16-bit scale for the filter */ - hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos); /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { /* 32-bit scale for the filter */ - hcan->Instance->FS1R |= filternbrbitpos; + SET_BIT(hcan->Instance->FS1R, filternbrbitpos); + /* 32-bit identifier or First 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { /*Id/Mask mode for the filter*/ - hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos); } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ - hcan->Instance->FM1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->FM1R, filternbrbitpos); } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) { /* FIFO 0 assignation for the filter */ - hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos); } - - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + else { /* FIFO 1 assignation for the filter */ - hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->FFA1R, filternbrbitpos); } /* Filter activation */ if (sFilterConfig->FilterActivation == ENABLE) { - hcan->Instance->FA1R |= filternbrbitpos; + SET_BIT(hcan->Instance->FA1R, filternbrbitpos); } /* Leave the initialisation mode for the filter */ - hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT); + CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT)); /* Return function status */ return HAL_OK; @@ -442,7 +445,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /** * @brief Deinitializes the CANx peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ @@ -475,7 +478,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) /** * @brief Initializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -491,7 +494,7 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) /** * @brief DeInitializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -528,9 +531,9 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) /** * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) @@ -542,37 +545,43 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { + { /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } - + /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) { - transmitmailbox = 0U; + transmitmailbox = CAN_TXMAILBOX_0; } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) { - transmitmailbox = 1U; + transmitmailbox = CAN_TXMAILBOX_1; } - else + else { - transmitmailbox = 2U; + transmitmailbox = CAN_TXMAILBOX_2; } /* Set up the Id */ @@ -580,15 +589,15 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) if (hcan->pTxMsg->IDE == CAN_ID_STD) { assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ + hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); } /* Set up the DLC */ @@ -597,16 +606,17 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4])); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); + /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); /* Get tick */ tickstart = HAL_GetTick(); @@ -617,26 +627,37 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + + /* Cancel transmission */ + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -647,7 +668,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - + /* Return function status */ return HAL_ERROR; } @@ -655,7 +676,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /** * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ @@ -667,7 +688,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) @@ -676,92 +697,94 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) __HAL_LOCK(hcan); /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) { - transmitmailbox = 0U; + transmitmailbox = CAN_TXMAILBOX_0; } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) { - transmitmailbox = 1U; + transmitmailbox = CAN_TXMAILBOX_1; } else { - transmitmailbox = 2U; + transmitmailbox = CAN_TXMAILBOX_2; } /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if(hcan->pTxMsg->IDE == CAN_ID_STD) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ + hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); } - + /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } - + /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hcan); - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); - - /* Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME); - + /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); } else { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; @@ -772,34 +795,85 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /** * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. - * @param Timeout: Timeout duration. + * @param FIFONumber FIFO number. + * @param Timeout Timeout duration. * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - + /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; } - else + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; } - + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + /* Get tick */ tickstart = HAL_GetTick(); @@ -809,41 +883,54 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; } } } - + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) { - hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; } else { - hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; } - - hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; + pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; + pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; + pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; + pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; + pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; + pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; + pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; /* Release the FIFO */ if(FIFONumber == CAN_FIFO0) @@ -856,16 +943,43 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Release FIFO1 */ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } /* Process unlocked */ @@ -877,69 +991,108 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /** * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. + * @param FIFONumber FIFO number. * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { /* Process unlocked */ __HAL_UNLOCK(hcan); - if(FIFONumber == CAN_FIFO0) + return HAL_BUSY; + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; } - else + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; } - + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } else { - return HAL_BUSY; + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } /* Return function status */ @@ -948,7 +1101,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber /** * @brief Enters the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status. */ @@ -963,10 +1116,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) hcan->State = HAL_CAN_STATE_BUSY; /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + MODIFY_REG(hcan->Instance->MCR, + CAN_MCR_INRQ , + CAN_MCR_SLEEP ); /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) { /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -979,7 +1135,8 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) { if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -1003,7 +1160,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) /** * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral * is in the normal mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status. */ @@ -1018,23 +1175,26 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) hcan->State = HAL_CAN_STATE_BUSY; /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) { if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; } } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + + if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) { /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -1055,27 +1215,67 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) /** * @brief Handles CAN interrupt request - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + /* Check End of transmission flag */ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) { + /* Check Transmit request completion status */ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + /* Check Transmit success */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) || + (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) || + (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); } } /* Check End of reception flag for FIFO0 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U)) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO0); @@ -1083,12 +1283,15 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Check End of reception flag for FIFO1 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U)) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO1); } + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + /* Check Error Warning Flag */ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && @@ -1106,7 +1309,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { /* Set CAN error code to EPV error */ hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ + /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-Off Flag */ @@ -1155,16 +1358,40 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) } /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); } /* Call the Error call Back in case of Errors */ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) { /* Clear ERRI Flag */ - hcan->Instance->MSR |= CAN_MSR_ERRI; + SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); + /* Set the CAN state ready to be able to start again the process */ hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + /* Call Error callback function */ HAL_CAN_ErrorCallback(hcan); } @@ -1172,7 +1399,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /** * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1188,7 +1415,7 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) /** * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1204,7 +1431,7 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1240,7 +1467,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) /** * @brief return the CAN state - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ @@ -1252,7 +1479,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) /** * @brief Return the CAN error code - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ @@ -1274,9 +1501,10 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) * * @{ */ + /** * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ @@ -1287,33 +1515,36 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_BUSY_TX) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - + /* Transmission complete callback */ HAL_CAN_TxCpltCallback(hcan); @@ -1322,84 +1553,122 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /** * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number + * @param FIFONumber Specify the FIFO number * @retval HAL status * @retval None */ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) { - hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; } else { - hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; } - - hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; + pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; + pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; + pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; + pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; + pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; + pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; + pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; + /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1)) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } /* Receive complete callback */ @@ -1408,6 +1677,7 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum /* Return function status */ return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h index 456cf5f885a..95a0476d348 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_can.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -59,20 +57,24 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ - */ + */ /** * @brief HAL State structures definition */ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ }HAL_CAN_StateTypeDef; @@ -140,7 +142,7 @@ typedef struct second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. @@ -180,7 +182,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. + uint8_t Data[8]; /*!< Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ }CanTxMsgTypeDef; @@ -205,7 +207,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be received. + uint8_t Data[8]; /*!< Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. @@ -227,8 +229,10 @@ typedef struct CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ - + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + HAL_LockTypeDef Lock; /*!< CAN locking object */ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ @@ -250,16 +254,19 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ -#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ -#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */ /** * @} */ @@ -273,10 +280,10 @@ typedef struct * @} */ -/** @defgroup CAN_operating_mode CAN operating mode +/** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -285,10 +292,10 @@ typedef struct */ -/** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -296,10 +303,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1 +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -315,15 +322,14 @@ typedef struct #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ - /** * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -331,72 +337,65 @@ typedef struct #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ - /** * @} */ -/** @defgroup CAN_filter_mode CAN filter mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ - /** * @} */ -/** @defgroup CAN_filter_scale CAN filter scale +/** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ - /** * @} */ -/** @defgroup CAN_filter_FIFO CAN filter FIFO +/** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ - /** * @} */ -/** @defgroup CAN_identifier_type CAN identifier type +/** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ #define CAN_ID_STD (0x00000000U) /*!< Standard Id */ #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ - /** * @} */ -/** @defgroup CAN_remote_transmission_request CAN remote transmission request +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ - /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number * @{ */ #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ - /** * @} */ -/** @defgroup CAN_flags CAN flags +/** @defgroup CAN_flags CAN Flags * @{ */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() @@ -423,22 +422,25 @@ typedef struct #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ -#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ + /** * @} */ -/** @defgroup CAN_interrupts CAN interrupts +/** @defgroup CAN_interrupts CAN Interrupts * @{ */ #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ @@ -465,7 +467,7 @@ typedef struct /** * @} */ - + /** @defgroup CAN_Mailboxes CAN Mailboxes * @{ */ @@ -476,7 +478,7 @@ typedef struct /** * @} */ - + /** * @} */ @@ -485,42 +487,42 @@ typedef struct /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ - + /** @brief Reset CAN handle state - * @param __HANDLE__: CAN handle. + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param __HANDLE__ CAN handle. + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @retval The number of pending message. */ #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: * @arg CAN_TSR_RQCP0: Request MailBox0 Flag * @arg CAN_TSR_RQCP1: Request MailBox1 Flag * @arg CAN_TSR_RQCP2: Request MailBox2 Flag @@ -552,9 +554,9 @@ typedef struct ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: * @arg CAN_TSR_RQCP0: Request MailBox0 Flag * @arg CAN_TSR_RQCP1: Request MailBox1 Flag * @arg CAN_TSR_RQCP2: Request MailBox2 Flag @@ -578,16 +580,16 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the CAN Handle. - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be one of the following values: * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable @@ -597,21 +599,19 @@ typedef struct /** * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: CAN handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @param __HANDLE__ CAN handle. + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. * @retval The new status of transmission (TRUE or FALSE). */ #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) - - +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) -/** + /** * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param __HANDLE__ CAN handle. + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @retval None */ #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ @@ -619,8 +619,8 @@ typedef struct /** * @brief Cancel a transmit request. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @param __HANDLE__ specifies the CAN Handle. + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. * @retval None */ #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ @@ -630,8 +630,8 @@ typedef struct /** * @brief Enable or disables the DBG Freeze for CAN. - * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. + * @param __HANDLE__ specifies the CAN Handle. + * @param __NEWSTATE__ new state of the CAN peripheral. * This parameter can be: ENABLE (CAN reception/transmission is frozen * during debug. Reception FIFOs can still be accessed/controlled normally) * or DISABLE (CAN is working during debug). @@ -641,14 +641,14 @@ typedef struct ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) /** - * @} - */ - + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ - + /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @{ @@ -661,14 +661,13 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); /** - * @} - */ - + * @} + */ + /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + * @brief I/O operation functions * @{ */ - /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); @@ -676,31 +675,28 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, u HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); - void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); - void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); /** - * @} - */ - + * @} + */ + /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions * @brief CAN Peripheral State functions * @{ - */ + */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); - /** - * @} - */ - + * @} + */ + /** - * @} - */ + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -730,27 +726,37 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ + #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) + #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) + #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) + #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) + +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) + #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) + #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) + #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) + +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) @@ -759,29 +765,38 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) + #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) /** * @} */ +/* End of private macros -----------------------------------------------------*/ /** * @} */ - + /** * @} - */ + */ #endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F078xx || STM32F091xC || STM32F098xx */ @@ -793,4 +808,3 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c index 5c22bb0b405..3c93dc5a6bd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cec.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -78,6 +76,13 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" +#ifdef HAL_CEC_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) ||\ + defined(STM32F051x8) || defined(STM32F058xx) ||\ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ + defined(STM32F091xC) || defined (STM32F098xx) + /** @addtogroup STM32F0xx_HAL_Driver * @{ */ @@ -86,12 +91,7 @@ * @brief HAL CEC module driver * @{ */ -#ifdef HAL_CEC_MODULE_ENABLED -#if defined(STM32F042x6) || defined(STM32F048xx) ||\ - defined(STM32F051x8) || defined(STM32F058xx) ||\ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ - defined(STM32F091xC) || defined (STM32F098xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CEC_Private_Constants CEC Private Constants @@ -144,7 +144,7 @@ /** * @brief Initializes the CEC mode according to the specified * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) @@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /** * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -267,8 +267,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /** * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP Init - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) @@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP DeInit - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) @@ -380,11 +380,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). + * @param hcec CEC handle + * @param InitiatorAddress Initiator address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status @@ -440,7 +440,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator /** * @brief Get size of the received frame. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval Frame size */ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) @@ -450,8 +450,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) /** * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ @@ -462,7 +462,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) @@ -567,7 +567,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Tx Transfer completed callback - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) @@ -581,8 +581,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame + * @param hcec CEC handle + * @param RxFrameSize Size of frame * @retval None */ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) @@ -597,7 +597,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize /** * @brief CEC error callbacks - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) @@ -628,7 +628,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize */ /** * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC module. * @retval HAL state */ @@ -643,7 +643,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) /** * @brief Return the CEC error code - * @param hcec : pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. * @retval CEC Error Code */ @@ -659,18 +659,18 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) /** * @} */ - -#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */ - /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ - /* defined(STM32F091xC) || defined (STM32F098xx) */ -#endif /* HAL_CEC_MODULE_ENABLED */ /** * @} */ /** * @} - */ + */ +#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */ + /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ + /* defined(STM32F091xC) || defined (STM32F098xx) */ + +#endif /* HAL_CEC_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h index 24acad6179a..d3b001ef80e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cec.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention @@ -431,7 +429,7 @@ typedef struct */ /** @brief Reset CEC handle gstate & RxState - * @param __HANDLE__: CEC handle. + * @param __HANDLE__ CEC handle. * @retval None */ #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -440,8 +438,8 @@ typedef struct } while(0) /** @brief Checks whether or not the specified CEC interrupt flag is set. - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the flag to check. * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. @@ -460,8 +458,8 @@ typedef struct #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** @brief Clears the interrupt or status flag when raised (write at 1) - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the interrupt/status flag to clear. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the interrupt/status flag to clear. * This parameter can be one of the following values: * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. @@ -481,8 +479,8 @@ typedef struct #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) /** @brief Enables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to enable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to enable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -502,8 +500,8 @@ typedef struct #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** @brief Disables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to disable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to disable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -523,8 +521,8 @@ typedef struct #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) /** @brief Checks whether or not the specified CEC interrupt is enabled. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to check. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -544,52 +542,52 @@ typedef struct #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) /** @brief Enables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) /** @brief Disables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) /** @brief Set Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) /** @brief Set Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. */ #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) /** @brief Get Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) /** @brief Get Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) /** @brief Clear OAR register - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand - * @param __HANDLE__: specifies the CEC Handle. - * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) + * @param __HANDLE__ specifies the CEC Handle. + * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) @@ -704,21 +702,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); * The message size is the payload size: without counting the header, * it varies from 0 byte (ping operation, one header only, no payload) to * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. + * @param __SIZE__ CEC message size. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. - * @param __ADDRESS__: CEC own address. + * @param __ADDRESS__ CEC own address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) /** @brief Check CEC initiator or destination logical address setting. * Initiator and destination addresses are coded over 4 bits. - * @param __ADDRESS__: CEC initiator or logical address. + * @param __ADDRESS__ CEC initiator or logical address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c index 61760a35636..a2d9c2d1f2a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: @@ -188,7 +186,7 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */ /* CSR register reset value */ #define COMP_CSR_RESET_VALUE (0x00000000U) @@ -230,7 +228,7 @@ * parameters in the COMP_InitTypeDef and create the associated handle. * @note If the selected comparator is locked, initialization can't be performed. * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) @@ -316,7 +314,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) * @brief DeInitializes the COMP peripheral * @note Deinitialization can't be performed if the COMP configuration is locked. * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) @@ -357,7 +355,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) /** * @brief Initializes the COMP MSP. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) @@ -372,7 +370,7 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) /** * @brief DeInitializes COMP MSP. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) @@ -406,7 +404,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) /** * @brief Start the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) @@ -438,7 +436,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) hcomp->State = HAL_COMP_STATE_BUSY; /* Delay for COMP startup time */ - wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U)); + wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; @@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /** * @brief Stop the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) @@ -495,7 +493,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /** * @brief Enables the interrupt and starts the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status. */ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) @@ -542,7 +540,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) /** * @brief Disable the interrupt and Stop the comparator - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) @@ -559,7 +557,7 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) /** * @brief Comparator IRQ Handler - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) @@ -598,7 +596,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /** * @brief Lock the selected comparator configuration. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) @@ -643,7 +641,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * voltage than the inverting input * - Comparator output is low when the non-inverting input is at a higher * voltage than the inverting input - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. * */ @@ -670,7 +668,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) /** * @brief Comparator callback. - * @param hcomp: COMP handle + * @param hcomp COMP handle * @retval None */ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) @@ -705,7 +703,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) /** * @brief Return the COMP state - * @param hcomp : COMP handle + * @param hcomp COMP handle * @retval HAL state */ uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h index 30c9a981906..ae0df5004f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention @@ -262,14 +260,14 @@ typedef struct */ /** @brief Reset COMP handle state - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) /** * @brief Enable the specified comparator. - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ @@ -278,7 +276,7 @@ typedef struct /** * @brief Disable the specified comparator. - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ @@ -287,7 +285,7 @@ typedef struct /** * @brief Lock the specified comparator configuration. - * @param __HANDLE__: COMP handle. + * @param __HANDLE__ COMP handle. * @retval None */ #define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ @@ -463,8 +461,8 @@ typedef struct #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) /** @brief Check whether the specified COMP flag is set or not. - * @param __HANDLE__: specifies the COMP Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the COMP Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg COMP_FLAG_LOCK: lock flag * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -564,7 +562,7 @@ uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); */ /** * @brief Get the specified EXTI line for a comparator instance. - * @param __INSTANCE__: specifies the COMP instance. + * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h index 3c256a33856..6baa4090c0b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_conf.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -85,7 +83,7 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** @@ -93,7 +91,7 @@ * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -102,7 +100,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -110,14 +108,14 @@ * Timeout value */ #if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */ + #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ #endif /* HSI_STARTUP_TIMEOUT */ /** * @brief Internal High Speed oscillator for ADC (HSI14) value. */ #if !defined (HSI14_VALUE) -#define HSI14_VALUE (14000000U) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + #define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz. The real value may vary depending on the variations in voltage and temperature. */ #endif /* HSI14_VALUE */ @@ -126,7 +124,7 @@ * @brief Internal High Speed oscillator for USB (HSI48) value. */ #if !defined (HSI48_VALUE) -#define HSI48_VALUE (48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz. The real value may vary depending on the variations in voltage and temperature. */ #endif /* HSI48_VALUE */ @@ -135,22 +133,22 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE (40000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + #define LSI_VALUE 40000U +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ /** * @brief Time out for LSE start up value in ms. */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ @@ -161,14 +159,15 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ /* Warning: Must be set to higher priority for HAL_Delay() */ /* and HAL_GetTick() usage under interrupt context */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 0 -#define DATA_CACHE_ENABLE 0 +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 0U +#define DATA_CACHE_ENABLE 0U +#define USE_SPI_CRC 1U /* ########################## Assert Selection ############################## */ /** @@ -177,15 +176,6 @@ */ /*#define USE_FULL_ASSERT 1*/ -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c index 8d189d100fc..fba72d339d9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -140,13 +138,13 @@ /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number . + * @param IRQn External interrupt number . * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 3. * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None @@ -205,7 +203,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -236,7 +234,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None @@ -299,7 +297,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h index 284ac753744..ebea4eab572 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c index 79daa5342df..cd94ee26f43 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -13,19 +11,19 @@ * @verbatim =============================================================================== - ##### How to use this driver ##### + ##### How to use this driver ##### =============================================================================== [..] - (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); - (#) Initialize CRC calculator + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator (++)specify generating polynomial (IP default or non-default one) (++)specify initialization value (IP default or non-default one) (++)specify input data format (++)specify input or output data inversion mode if any - (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the input data buffer starting with the previously computed CRC as initialization value - (#) Use HAL_CRC_Calculate() function to compute the CRC value of the + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the input data buffer starting with the defined initialization value (default or non-default) to initiate CRC calculation @@ -57,7 +55,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -67,7 +65,7 @@ * @{ */ -/** @defgroup CRC CRC +/** @defgroup CRC CRC * @brief CRC HAL module driver. * @{ */ @@ -87,34 +85,35 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @} */ - -/* Exported functions ---------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + /** @defgroup CRC_Exported_Functions CRC Exported Functions * @{ */ -/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions +/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions. * @verbatim =============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle (+) DeInitialize the CRC peripheral - (+) Initialize the CRC MSP - (+) DeInitialize CRC MSP + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP @endverbatim * @{ */ /** - * @brief Initializes the CRC according to the specified - * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: CRC handle + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and initialize the associated handle. + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) @@ -132,6 +131,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -181,8 +181,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) } /** - * @brief DeInitializes the CRC peripheral. - * @param hcrc: CRC handle + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) @@ -205,6 +205,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + /* Reset IDR register content */ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; @@ -223,7 +226,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -237,8 +240,8 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) } /** - * @brief DeInitializes the CRC MSP. - * @param hcrc: CRC handle + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -263,12 +266,12 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - using combination of the previous CRC value and the new one. + (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer + using the combination of the previous CRC value and the new one - or + [..] or - (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer independently of the previous CRC value. @endverbatim @@ -278,16 +281,16 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) @@ -319,9 +322,9 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ case CRC_INPUTDATA_FORMAT_HALFWORDS: temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } /* Change CRC peripheral state */ @@ -338,15 +341,15 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the + * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ @@ -385,9 +388,9 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } /* Change CRC peripheral state */ @@ -399,6 +402,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /* Return the CRC computed value */ return temp; } + /** * @} */ @@ -411,20 +415,20 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. + This subsection permits to get in run-time the status of the peripheral. @endverbatim * @{ */ /** - * @brief Returns the CRC state. - * @param hcrc: CRC handle + * @brief Return the CRC handle state. + * @param hcrc CRC handle * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) { + /* Return CRC handle state */ return hcrc->State; } @@ -436,15 +440,16 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @} */ -/** @addtogroup CRC_Private_Functions CRC Private Functions +/** @defgroup CRC_Private_Functions CRC Private Functions * @{ */ + /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) @@ -456,23 +461,23 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ * handling by the IP */ for(i = 0U; i < (BufferLength/4U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24U) | ((uint32_t)pBuffer[4*i+1]<<16U) | ((uint32_t)pBuffer[4*i+2]<<8U) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3]; } /* last bytes specific handling */ - if ((BufferLength%4) != 0U) + if ((BufferLength%4U) != 0U) { - if (BufferLength%4 == 1U) + if (BufferLength%4U == 1U) { - *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; } - if (BufferLength%4 == 2U) + if (BufferLength%4U == 2U) { - *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; } - if (BufferLength%4 == 3U) + if (BufferLength%4U == 3U) { - *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8U) | (uint16_t)pBuffer[4*i+1]; - *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; + *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; } } @@ -485,38 +490,35 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ /** * @brief Enter 16-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i = 0U; /* input data buffer index */ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) + for(i = 0U; i < (BufferLength/2U); i++) { - hcrc->Instance->DR = (pBuffer[2*i]<<16U) | pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1]; } - if ((BufferLength%2) != 0U) + if ((BufferLength%2U) != 0U) { - *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; + *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; } /* Return the CRC computed value */ return hcrc->Instance->DR; } -/** - * @} - */ /** * @} */ - + #endif /* HAL_CRC_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h index 29dc65bc59d..620ba76a11b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -224,37 +222,37 @@ typedef struct */ /** @brief Reset CRC handle state - * @param __HANDLE__: CRC handle. + * @param __HANDLE__ CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Reset CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Set CRC INIT non-default value - * @param __HANDLE__ : CRC handle - * @param __INIT__ : 32-bit initial value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value * @retval None. */ #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ 8-bit value to be stored in the ID register * @retval None */ #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval 8-bit value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c index 40ff26f60e0..02591701f97 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: @@ -96,7 +94,7 @@ /** * @brief Extended initialization to set generating polynomial - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc) @@ -126,8 +124,8 @@ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc) /** * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode * This parameter can be one of the following values: * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value) * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal @@ -154,8 +152,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t /** * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode * This parameter can be one of the following values: * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) @@ -182,12 +180,12 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) /** * @brief Initializes the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long) * This parameter is written in normal representation, e.g. * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length + * @param PolyLength CRC polynomial length * This parameter can be one of the following values: * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h index 6f37f054e5f..06a518786ed 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_crc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention @@ -133,14 +131,14 @@ /** * @brief Set CRC output reversal - * @param __HANDLE__ : CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) /** * @brief Unset CRC output reversal - * @param __HANDLE__ : CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) @@ -148,8 +146,8 @@ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Set CRC non-default polynomial - * @param __HANDLE__ : CRC handle - * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial * @retval None. */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c index fe166f4c613..f3b658d4b38 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -257,7 +255,7 @@ /** * @brief Initialize the DAC peripheral according to the specified parameters * in the DAC_InitStruct and initialize the associated handle. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -295,7 +293,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) /** * @brief Deinitialize the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -331,7 +329,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /** * @brief Initialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -347,7 +345,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /** * @brief DeInitialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -385,9 +383,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -408,9 +406,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -433,15 +431,15 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -466,9 +464,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Cha /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -531,7 +529,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -546,18 +544,18 @@ __weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -588,7 +586,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /** * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -604,7 +602,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -620,7 +618,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -636,7 +634,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -671,9 +669,9 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -694,10 +692,10 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -739,7 +737,7 @@ __weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_Chan /** * @brief return the DAC handle state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ @@ -752,7 +750,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h index f249ed12065..3d3263cad78 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -180,30 +178,30 @@ typedef struct */ /** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC handle. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) /** @brief Enable the DAC channel - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_Channel__: specifies the DAC channel + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) /** @brief Disable the DAC channel - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_Channel__: specifies the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) /** @brief Enable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -212,8 +210,8 @@ typedef struct #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @retval None @@ -221,8 +219,8 @@ typedef struct #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified DAC interrupt source is enabled or not - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -231,8 +229,8 @@ typedef struct #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to get. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @retval None @@ -240,8 +238,8 @@ typedef struct #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @retval None @@ -284,19 +282,19 @@ typedef struct #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) /** @brief Set DHR12R1 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__)) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c index b21cb61cadf..7ff936db63e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. @@ -116,10 +114,10 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -171,10 +169,10 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval HAL status @@ -226,9 +224,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -259,9 +257,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval The selected DAC channel data output value. @@ -292,9 +290,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -345,15 +343,15 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -512,14 +510,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -602,7 +600,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -660,7 +658,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -709,7 +707,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -724,7 +722,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -737,7 +735,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -768,7 +766,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -783,7 +781,7 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -796,7 +794,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -870,7 +868,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -894,7 +892,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -915,12 +913,12 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -963,12 +961,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -1035,15 +1033,15 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status @@ -1103,7 +1101,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /** * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1119,7 +1117,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1135,7 +1133,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1151,7 +1149,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h index 9823515d96c..57240ee0c51 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h index be1eabc4878..3e2007617b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_def.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_def.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -46,7 +44,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx.h" +#if defined(USE_HAL_LEGACY) #include "stm32_hal_legacy.h" +#endif #include /* Exported types ------------------------------------------------------------*/ @@ -87,7 +87,7 @@ typedef enum #define UNUSED(x) ((void)(x)) /** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. + * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro @@ -124,7 +124,7 @@ typedef enum }while (0) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) && !defined ( __CC_ARM ) +#if defined ( __GNUC__ ) #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c index 29191551fa8..9bd69a01fdf 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -149,7 +147,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -217,7 +215,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitialize the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -290,11 +288,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Start the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -337,11 +335,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -396,8 +394,8 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Abort the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) @@ -422,8 +420,8 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /** * @brief Abort the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) @@ -466,10 +464,10 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) @@ -569,7 +567,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /** * @brief Handle DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ @@ -657,11 +655,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callback function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -710,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -788,7 +786,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ @@ -799,7 +797,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) /** * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ @@ -822,11 +820,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Set the DMA Transfer parameters. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -837,7 +835,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ @@ -846,7 +844,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ @@ -859,7 +857,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief set the DMA base address and channel index depending on DMA instance - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h index 1aeabd9009a..6a9fb70f44a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -365,21 +363,21 @@ typedef struct __DMA_HandleTypeDef */ /** @brief Reset DMA handle state - * @param __HANDLE__: DMA handle. + * @param __HANDLE__ DMA handle. * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) @@ -389,8 +387,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -401,8 +399,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -413,8 +411,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -425,7 +423,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * * @retval The number of remaining data units in the current DMA Channel transfer. */ @@ -433,7 +431,7 @@ typedef struct __DMA_HandleTypeDef #if defined(SYSCFG_CFGR1_DMA_RMP) /** @brief DMA remapping enable/disable macros - * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping + * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping */ #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ SYSCFG->CFGR1 |= (__DMA_REMAP__); \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h index 31538188114..03217b1ca4c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of DMA HAL Extension module. ****************************************************************************** * @attention @@ -523,7 +521,7 @@ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) /** * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -537,7 +535,7 @@ /** * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -551,7 +549,7 @@ /** * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -565,7 +563,7 @@ /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -579,8 +577,8 @@ /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -593,8 +591,8 @@ /** * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -607,7 +605,7 @@ #elif defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -626,7 +624,7 @@ /** * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -645,7 +643,7 @@ /** * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -664,7 +662,7 @@ /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -683,8 +681,8 @@ /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -699,8 +697,8 @@ /** * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -715,7 +713,7 @@ #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ /** * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -727,7 +725,7 @@ /** * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -739,7 +737,7 @@ /** * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -751,7 +749,7 @@ /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -763,8 +761,8 @@ /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -777,8 +775,8 @@ /** * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c index 72ece2dfa82..167bb4bb666 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -436,7 +434,7 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) @@ -455,7 +453,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which returned an error * - Program: Address which was selected for data program diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h index f3497a2bd0c..f2ee2488de7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c index 1999e2c3f36..3c2041cf15e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following @@ -921,26 +919,23 @@ static uint32_t FLASH_OB_GetWRP(void) */ static uint32_t FLASH_OB_GetRDP(void) { - uint32_t readstatus = OB_RDP_LEVEL_0; - uint32_t tmp_reg = 0; + uint32_t tmp_reg = 0U; /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); if (tmp_reg == FLASH_OBR_RDPRT1) { - readstatus = OB_RDP_LEVEL_1; + return OB_RDP_LEVEL_1; } else if (tmp_reg == FLASH_OBR_RDPRT2) { - readstatus = OB_RDP_LEVEL_2; + return OB_RDP_LEVEL_2; } else { - readstatus = OB_RDP_LEVEL_0; + return OB_RDP_LEVEL_0; } - - return readstatus; } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h index 73c96e83aa7..0d127e36855 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c index 7e9a8e27f13..2890fccaeb1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -180,8 +178,8 @@ /** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -305,8 +303,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /** * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -386,8 +384,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /** * @brief Read the specified input port pin. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -415,10 +413,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -442,8 +440,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggle the specified GPIO pin. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the pin to be toggled. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -460,8 +458,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin: specifies the port bits to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ @@ -496,7 +494,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -511,7 +509,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) /** * @brief EXTI line detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h index 31eb6d8d0fe..21157f853c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -181,7 +179,7 @@ typedef enum /** * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -189,7 +187,7 @@ typedef enum /** * @brief Clear the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -197,7 +195,7 @@ typedef enum /** * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -205,7 +203,7 @@ typedef enum /** * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -213,7 +211,7 @@ typedef enum /** * @brief Generate a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h index a6209ad3d01..82169b437f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -76,6 +74,7 @@ #define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ #define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ /* AF 1 */ #define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ @@ -123,6 +122,7 @@ #define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ #define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ /* AF 1 */ #define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c index 9547c6b6f59..225b519bdb8 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -238,7 +236,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -366,7 +364,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -406,7 +404,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - if(hi2c->State == HAL_I2C_STATE_RESET) + if (hi2c->State == HAL_I2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; @@ -444,7 +442,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); } @@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { hi2c->Instance->CR2 = (I2C_CR2_ADD10); } @@ -493,7 +491,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -557,7 +555,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * @verbatim =============================================================================== @@ -569,7 +567,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function + The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. @@ -630,7 +628,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -638,7 +636,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -646,7 +644,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -654,7 +652,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -665,12 +663,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -684,15 +682,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -707,9 +705,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -754,15 +752,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) - { + if (hi2c->State == HAL_I2C_STATE_READY) + { /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -789,12 +787,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -809,15 +807,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -832,9 +830,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -843,7 +841,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -865,7 +863,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /** - * @brief Transmits in slave mode an amount of data in blocking mode. + * @brief Transmits in slave mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -877,15 +875,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -902,7 +900,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -910,13 +908,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -924,26 +922,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -959,16 +957,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } else { @@ -977,10 +975,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1017,9 +1015,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1042,7 +1040,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1050,33 +1048,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferCount--; } - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; } @@ -1092,12 +1090,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1108,10 +1106,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1149,9 +1147,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1168,8 +1166,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1185,7 +1183,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current @@ -1218,9 +1216,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1237,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1252,7 +1250,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1283,7 +1281,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1323,7 +1321,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -1332,7 +1330,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1385,9 +1383,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1404,8 +1402,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1416,7 +1414,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; @@ -1454,7 +1452,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); @@ -1493,9 +1491,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1512,8 +1510,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1524,7 +1522,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; @@ -1541,7 +1539,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1562,7 +1560,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); @@ -1596,12 +1594,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1642,7 +1640,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; return HAL_OK; } @@ -1662,12 +1660,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1737,9 +1735,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1750,7 +1748,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1765,9 +1763,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1782,7 +1780,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1796,9 +1794,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1813,15 +1811,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1833,13 +1831,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1889,9 +1888,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1902,7 +1901,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1917,9 +1916,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1935,7 +1934,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -1949,7 +1948,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, do { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1959,15 +1958,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1978,13 +1977,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -2033,14 +2033,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2060,8 +2060,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2073,9 +2073,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2090,12 +2090,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -2132,14 +2132,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2159,8 +2159,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2172,9 +2172,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2230,14 +2230,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2257,8 +2257,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2270,9 +2270,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2346,14 +2346,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2374,7 +2374,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2386,9 +2386,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2416,7 +2416,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2458,9 +2458,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2474,16 +2474,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2491,14 +2491,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } - } + } } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2517,7 +2517,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2535,8 +2535,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - }while(I2C_Trials < Trials); + } + while (I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; @@ -2579,7 +2580,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2595,7 +2596,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2645,7 +2646,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2661,7 +2662,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2673,7 +2674,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, } /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2706,9 +2707,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2718,10 +2719,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); @@ -2741,11 +2742,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2780,9 +2781,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2792,15 +2793,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); } - + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2815,11 +2816,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2847,7 +2848,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -2875,7 +2876,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); @@ -2904,7 +2905,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if(hi2c->Mode == HAL_I2C_MODE_MASTER) + if (hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2923,7 +2924,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -2944,7 +2945,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief This function handles I2C event interrupt request. @@ -2959,7 +2960,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) + if (hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } @@ -2977,7 +2978,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -2986,7 +2987,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -2995,7 +2996,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -3004,7 +3005,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -3077,8 +3078,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -3228,7 +3229,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @} - */ + */ /** * @} @@ -3246,14 +3247,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3266,27 +3267,27 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -3294,7 +3295,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { hi2c->XferSize = hi2c->XferCount; - if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } @@ -3307,7 +3308,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call TxCpltCallback() if no stop mode is set */ - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSequentialCplt(hi2c); @@ -3320,14 +3321,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ - if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -3347,7 +3348,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3367,26 +3368,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3414,9 +3415,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; @@ -3424,24 +3425,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->XferCount--; } - if((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); - } + } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3450,7 +3451,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } else { - if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ @@ -3460,7 +3461,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3480,7 +3481,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; uint32_t xfermode = 0U; @@ -3488,14 +3489,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3504,18 +3505,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if(hi2c->XferCount != 0U) + + if (hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -3533,7 +3534,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui hi2c->XferCount -= hi2c->XferSize; /* Enable DMA Request */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } @@ -3549,7 +3550,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3569,18 +3570,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3590,17 +3591,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3626,12 +3627,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3642,7 +3643,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3654,9 +3655,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3665,18 +3666,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } -return HAL_OK; + return HAL_OK; } /** @@ -3693,12 +3694,12 @@ return HAL_OK; */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3709,7 +3710,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3721,9 +3722,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3732,17 +3733,17 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -3763,7 +3764,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -3771,19 +3772,19 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2U) + if (hi2c->AddrEventCount == 2U) { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3885,7 +3886,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3901,7 +3902,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) HAL_I2C_SlaveTxCpltCallback(hi2c); } - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3937,7 +3938,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if((ITFlags & I2C_FLAG_AF) != RESET) + if ((ITFlags & I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3950,16 +3951,16 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Call the corresponding callback to inform upper layer of End of Transfer */ - if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; @@ -3985,7 +3986,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4022,7 +4023,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); @@ -4037,26 +4038,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); } /* All data are not transferred, so set error code accordingly */ - if(hi2c->XferCount != 0U) + if (hi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4070,19 +4071,19 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } } - else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; @@ -4094,7 +4095,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) HAL_I2C_ListenCpltCallback(hi2c); } /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4132,12 +4133,12 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4177,9 +4178,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -4193,10 +4194,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ - if(hi2c->State != HAL_I2C_STATE_ABORT) + if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; @@ -4206,7 +4207,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } /* Abort DMA TX transfer if any */ - if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4218,14 +4219,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } /* Abort DMA RX transfer if any */ - else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -4237,16 +4238,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } - else if(hi2c->State == HAL_I2C_STATE_ABORT) + else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4272,13 +4273,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { - hi2c->Instance->TXDR = 0x00U; + hi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); } @@ -4291,13 +4292,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4309,7 +4310,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4348,13 +4349,13 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4366,7 +4367,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4405,7 +4406,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4417,12 +4418,12 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4432,10 +4433,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ - if(hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); } @@ -4458,14 +4459,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4487,21 +4488,21 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4524,19 +4525,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4558,16 +4559,16 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -4576,7 +4577,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4586,10 +4587,10 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4610,18 +4611,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4644,7 +4645,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4690,8 +4691,8 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); /* update CR2 register */ hi2c->Instance->CR2 = tmpreg; @@ -4708,28 +4709,28 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr { uint32_t tmpisr = 0U; - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -4737,31 +4738,31 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr } else { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } } - + /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ @@ -4781,49 +4782,49 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter { uint32_t tmpisr = 0U; - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h index a3aa63142d3..dfdbdec4b60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32F0xx_HAL_I2C_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" +#include "stm32f0xx_hal_def.h" /** @addtogroup STM32F0xx_HAL_Driver * @{ @@ -52,7 +50,7 @@ /** @addtogroup I2C * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types @@ -60,13 +58,13 @@ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition + * @brief I2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization + This parameter calculated by referring to I2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. @@ -90,9 +88,9 @@ typedef struct uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ -}I2C_InitTypeDef; +} I2C_InitTypeDef; -/** +/** * @} */ @@ -122,7 +120,7 @@ typedef struct * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ - */ + */ typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ @@ -139,7 +137,7 @@ typedef enum HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -}HAL_I2C_StateTypeDef; +} HAL_I2C_StateTypeDef; /** * @} @@ -170,9 +168,9 @@ typedef enum HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -}HAL_I2C_ModeTypeDef; +} HAL_I2C_ModeTypeDef; -/** +/** * @} */ @@ -213,7 +211,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -228,7 +226,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -}I2C_HandleTypeDef; +} I2C_HandleTypeDef; /** * @} */ @@ -313,7 +311,7 @@ typedef struct __I2C_HandleTypeDef /** * @} */ - + /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ @@ -431,7 +429,7 @@ typedef struct __I2C_HandleTypeDef * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified I2C interrupt source is enabled or not. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the I2C interrupt source to check. @@ -506,7 +504,7 @@ typedef struct __I2C_HandleTypeDef #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) @@ -527,7 +525,7 @@ typedef struct __I2C_HandleTypeDef */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** @@ -538,7 +536,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); * @{ */ /* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -547,7 +545,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - /******* Non-Blocking mode: Interrupt */ +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -563,7 +561,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - /******* Non-Blocking mode: DMA */ +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -604,11 +602,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants @@ -617,7 +615,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros @@ -681,7 +679,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions @@ -690,15 +688,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /* Private functions are defined in stm32f0xx_hal_i2c.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c index d8c8e4a8f0a..6c24c54b2ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.c @@ -2,10 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions * @@ -96,7 +94,7 @@ ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters + (+) Configure Noise Filters (+) Configure Wake Up Feature @endverbatim @@ -116,7 +114,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -162,7 +160,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -206,12 +204,12 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -245,12 +243,12 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -263,7 +261,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) /* Enable wakeup from stop mode */ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - __HAL_I2C_ENABLE(hi2c); + __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h index cd3ce9d68e8..69bc8fb2922 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #define __STM32F0xx_HAL_I2C_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,7 +50,7 @@ /** @addtogroup I2CEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -64,7 +62,7 @@ /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE (0x00000000U) +#define I2C_ANALOGFILTER_ENABLE 0x00000000U #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} @@ -73,7 +71,7 @@ /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ -#define I2C_FMP_NOT_SUPPORTED (0xAAAA0000U) /*!< Fast Mode Plus not supported */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ #if defined(SYSCFG_CFGR1_I2C_FMP_PA9) #define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ #define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ @@ -101,7 +99,7 @@ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -154,7 +152,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c index 93e0bdb27a3..d0fe3dada49 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -212,7 +210,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -331,7 +329,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /** * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -365,7 +363,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -381,7 +379,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -443,15 +441,15 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -531,15 +529,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /** * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate @@ -612,10 +610,10 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -677,10 +675,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -744,10 +742,10 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u /** * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -825,10 +823,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -915,7 +913,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -943,7 +941,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -978,7 +976,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1019,7 +1017,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1073,7 +1071,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1089,7 +1087,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1105,7 +1103,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1121,7 +1119,7 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1137,7 +1135,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1172,7 +1170,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL state */ @@ -1183,7 +1181,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval I2S Error Code */ @@ -1204,7 +1202,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) */ /** * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1225,7 +1223,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1238,7 +1236,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1258,7 +1256,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1271,7 +1269,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1293,7 +1291,7 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1315,7 +1313,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) /** * @brief Receive an amount of data in non-blocking mode with Interrupt -* @param hi2s: I2S handle +* @param hi2s I2S handle * @retval None */ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) @@ -1337,11 +1335,11 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h index fcf0bf67d9b..1cf51f2487c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -293,21 +291,21 @@ typedef struct */ /** @brief Reset I2S handle state - * @param __HANDLE__: I2S handle. + * @param __HANDLE__ I2S handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) /** @brief Enable or disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE)) /** @brief Enable or disable the specified I2S interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -318,9 +316,9 @@ typedef struct #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -330,8 +328,8 @@ typedef struct #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_TXE: Transmit buffer empty flag @@ -345,7 +343,7 @@ typedef struct #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ @@ -355,7 +353,7 @@ typedef struct UNUSED(tmpreg); \ }while(0) /** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c index 17871e7b519..606972ce221 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -266,7 +264,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @brief Initialize the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -319,7 +317,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /** * @brief DeInitialize the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -353,7 +351,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief Initialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -369,7 +367,7 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) /** * @brief DeInitialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1653,7 +1651,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -2025,7 +2023,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2055,7 +2053,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h index 06e25afe6ce..6df14dd57c3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** @@ -361,22 +359,10 @@ typedef enum #define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */ #define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */ #define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */ - -/** Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - */ -#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */ - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ -#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */ -#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */ -#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */ +#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */ +#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */ +#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */ +#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */ /** * @} */ @@ -413,7 +399,7 @@ typedef enum */ /** @brief Reset IRDA handle state. - * @param __HANDLE__: IRDA handle. + * @param __HANDLE__ IRDA handle. * @retval None */ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -422,7 +408,7 @@ typedef enum } while(0) /** @brief Flush the IRDA DR register. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ @@ -432,8 +418,8 @@ typedef enum } while(0) /** @brief Clear the specified IRDA pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref IRDA_CLEAR_PEF * @arg @ref IRDA_CLEAR_FEF @@ -446,39 +432,39 @@ typedef enum #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) /** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) /** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) /** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) /** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) /** @brief Check whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag @@ -498,8 +484,8 @@ typedef enum /** @brief Enable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -514,8 +500,8 @@ typedef enum ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -531,8 +517,8 @@ typedef enum /** @brief Check whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -547,8 +533,8 @@ typedef enum #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified IRDA interrupt source is enabled or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -563,8 +549,8 @@ typedef enum /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag @@ -578,8 +564,8 @@ typedef enum /** @brief Set a specific IRDA request flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request @@ -590,25 +576,25 @@ typedef enum #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -623,20 +609,20 @@ typedef enum */ /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. - * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) /** * @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__: IRDA frame parity. + * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ @@ -645,14 +631,14 @@ typedef enum /** * @brief Ensure that IRDA communication mode is valid. - * @param __MODE__: IRDA communication mode. + * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that IRDA power mode is valid. - * @param __MODE__: IRDA power mode. + * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ @@ -660,7 +646,7 @@ typedef enum /** * @brief Ensure that IRDA state is valid. - * @param __STATE__: IRDA state mode. + * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ @@ -668,7 +654,7 @@ typedef enum /** * @brief Ensure that IRDA associated UART/USART mode is valid. - * @param __MODE__: IRDA associated UART/USART mode. + * @param __MODE__ IRDA associated UART/USART mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ @@ -676,7 +662,7 @@ typedef enum /** * @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__: IRDA sampling rate. + * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ @@ -684,7 +670,7 @@ typedef enum /** * @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__: IRDA DMA TX mode. + * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ @@ -692,7 +678,7 @@ typedef enum /** * @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__: IRDA DMA RX mode. + * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ @@ -700,7 +686,7 @@ typedef enum /** * @brief Ensure that IRDA request is valid. - * @param __PARAM__: IRDA request. + * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h index 969406fc53a..52df110414d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of IRDA HAL Extended module. ****************************************************************************** * @attention @@ -95,8 +93,8 @@ */ /** @brief Report the IRDA clock source. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ @@ -315,7 +313,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || \ @@ -389,7 +387,7 @@ /** * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__: IRDA frame length. + * @param __LENGTH__ IRDA frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c index 9f3e96c6150..1899f1f862d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h index 45914d09530..b3f3cd29933 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c index 5b858c44576..a802483a14c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -132,7 +130,7 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and create the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) @@ -213,7 +211,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes the PCD peripheral - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) @@ -239,7 +237,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -254,7 +252,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -288,7 +286,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /** * @brief Start the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) @@ -301,7 +299,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) /** * @brief Stop the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) @@ -323,7 +321,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) /** * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @@ -401,8 +399,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data out stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -418,8 +416,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data IN stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -434,7 +432,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -449,7 +447,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Start Of Frame callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -464,7 +462,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Reset callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -479,7 +477,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Suspend event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -494,7 +492,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Resume event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -509,8 +507,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO OUT callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -526,8 +524,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO IN callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -543,7 +541,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connection event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -558,7 +556,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callbacks - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -591,7 +589,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connect the USB device - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) @@ -607,7 +605,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) /** * @brief Disconnect the USB device - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) @@ -623,8 +621,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) /** * @brief Set the USB Device address - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) @@ -646,10 +644,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) } /** * @brief Open and configure an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packert size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packert size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) @@ -754,8 +752,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /** * @brief Deactivate an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -825,10 +823,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Receive an amount of data - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -845,8 +843,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & 0x7FU; - __HAL_LOCK(hpcd); - /* Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { @@ -873,15 +869,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) - __HAL_UNLOCK(hpcd); - return HAL_OK; } /** * @brief Get Received Data Size - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -890,10 +884,10 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** * @brief Send an amount of data - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -910,8 +904,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->is_in = 1U; ep->num = ep_addr & 0x7FU; - __HAL_LOCK(hpcd); - /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { @@ -951,16 +943,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) - - __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Set a STALL condition over an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1005,8 +995,8 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Clear a STALL condition over in an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1045,8 +1035,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Flush an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1056,7 +1046,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling -* @param hpcd: PCD handle +* @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1077,7 +1067,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling -* @param hpcd: PCD handle +* @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1116,7 +1106,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD state - * @param hpcd : PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) @@ -1136,10 +1126,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) */ /** * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx: USB peripheral instance register address. - * @param pbUsrBuf: pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. * @retval None */ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) @@ -1162,28 +1152,37 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u /** * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx: USB peripheral instance register address. + * @param USBx USB peripheral instance register address. * @param pbUsrBuf = pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. * @retval None */ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; + uint32_t n = (uint32_t)wNBytes >> 1U; uint32_t i; uint16_t *pdwVal; + uint32_t temp; pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + for (i = n; i != 0U; i--) { - *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++; - pbUsrBuf++; + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); + *pbUsrBuf++ = ((temp >> 8) & 0xFF); + } + + if (wNBytes % 2) + { + temp = *pdwVal++; + *pbUsrBuf++ = ((temp >> 0) & 0xFF); } } /** * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) @@ -1241,7 +1240,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); /* SETUP bit kept frozen while CTR_RX = 1*/ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h index a55517f0a3e..9f1b753289e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -386,9 +384,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. * @retval None */ #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ @@ -396,8 +394,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Endpoint Type */ #define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) @@ -406,9 +404,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir Direction * @retval None */ #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ @@ -425,8 +423,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval EP_DBUF_OUT, EP_DBUF_IN, * EP_DBUF_ERR if the endpoint counter not yet programmed. */ @@ -442,9 +440,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ @@ -465,9 +463,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ @@ -489,10 +487,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. * @retval None */ #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ @@ -525,8 +523,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval status */ #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) @@ -534,8 +532,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) @@ -543,8 +541,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval TRUE = endpoint in stall condition. */ #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ @@ -554,8 +552,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ @@ -565,8 +563,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -574,8 +572,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -583,8 +581,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ @@ -594,8 +592,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ @@ -605,8 +603,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ @@ -620,9 +618,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. * @retval None */ #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ @@ -630,8 +628,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) @@ -644,9 +642,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). * @retval None */ #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) @@ -654,8 +652,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval address of the buffer. */ #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -663,9 +661,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. + * @param dwReg Register + * @param wCount Counter. + * @param wNBlocks no. of Blocks. * @retval None */ #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ @@ -708,9 +706,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. * @retval None */ #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) @@ -721,8 +719,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Counter value */ #define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) @@ -730,9 +728,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. * @retval Counter value */ #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) @@ -740,10 +738,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @param wBuf1Addr buffer 1 address. * @retval None */ #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ @@ -753,8 +751,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -762,11 +760,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT * EP_DBUF_IN = IN - * @param wCount: Counter value + * @param wCount Counter value * @retval None */ #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ @@ -797,8 +795,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c index 959e7dd1a0e..b00d2f8547a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -81,12 +79,12 @@ /** * @brief Configure PMA for EP - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind * @arg USB_SNG_BUF: Single Buffer used * @arg USB_DBL_BUF: Double Buffer used - * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * @param pmaadress EP address in The PMA: In case of single buffer endpoint * this parameter is 16-bit value providing the address * in PMA allocated to endpoint. * In case of double buffer endpoint this parameter diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h index 035e8bba839..35a70b64816 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pcd_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention @@ -36,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L0xx_HAL_PCD_EX_H -#define __STM32L0xx_HAL_PCD_EX_H +#ifndef __STM32F0xx_HAL_PCD_EX_H +#define __STM32F0xx_HAL_PCD_EX_H #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c index 8959920a3fa..4eef3d0f4e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -241,7 +239,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. * This parameter can be value of : * @ref PWREx_WakeUp_Pins * @retval None @@ -256,7 +254,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. * This parameter can be values of : * @ref PWREx_WakeUp_Pins * @retval None @@ -272,11 +270,11 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Enters Sleep mode. * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Specifies the regulator state in SLEEP mode. + * @param Regulator Specifies the regulator state in SLEEP mode. * On STM32F0 devices, this parameter is a dummy value and it is ignored * as regulator can't be modified in this mode. Parameter is kept for platform * compatibility. - * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: @@ -317,11 +315,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in STOP mode. + * @param Regulator Specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h index 302e410fd66..ce9b7dd5177 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -104,7 +102,7 @@ */ /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A), @@ -126,7 +124,7 @@ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c index 4ce4ace5b1f..d83817ddef2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -116,7 +114,7 @@ defined (STM32F042x6) || defined (STM32F072xB) /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h index 384cf459ce1..ef74a81d77f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c index fd2730f76d7..619a481a17d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -986,7 +984,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef gpio = {0U}; + GPIO_InitTypeDef gpio; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); @@ -1068,7 +1066,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, - 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U}; + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; uint32_t sysclockfreq = 0U; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h index 56a62eea436..c9cf5a657cf 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -68,12 +66,12 @@ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ #if defined(RCC_HSI48_SUPPORT) -#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -83,11 +81,11 @@ * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00U -#define RCC_CFGR_OFFSET 0x04U -#define RCC_CIR_OFFSET 0x08U -#define RCC_BDCR_OFFSET 0x20U -#define RCC_CSR_OFFSET 0x24U +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 /** * @} @@ -114,30 +112,30 @@ #define RCC_CFGR_HPRE_BITNUMBER 4U #define RCC_CFGR_PPRE_BITNUMBER 8U /* Flags in the CFGR2 register */ -#define RCC_CFGR2_PREDIV_BITNUMBER 0U +#define RCC_CFGR2_PREDIV_BITNUMBER 0 /* Flags in the CR register */ -#define RCC_CR_HSIRDY_BitNumber 1U -#define RCC_CR_HSERDY_BitNumber 17U -#define RCC_CR_PLLRDY_BitNumber 25U +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 /* Flags in the CR2 register */ -#define RCC_CR2_HSI14RDY_BitNumber 1U -#define RCC_CR2_HSI48RDY_BitNumber 16U +#define RCC_CR2_HSI14RDY_BitNumber 1 +#define RCC_CR2_HSI48RDY_BitNumber 16 /* Flags in the BDCR register */ -#define RCC_BDCR_LSERDY_BitNumber 1U +#define RCC_BDCR_LSERDY_BitNumber 1 /* Flags in the CSR register */ -#define RCC_CSR_LSIRDY_BitNumber 1U -#define RCC_CSR_V18PWRRSTF_BitNumber 23U -#define RCC_CSR_RMVF_BitNumber 24U -#define RCC_CSR_OBLRSTF_BitNumber 25U -#define RCC_CSR_PINRSTF_BitNumber 26U -#define RCC_CSR_PORRSTF_BitNumber 27U -#define RCC_CSR_SFTRSTF_BitNumber 28U -#define RCC_CSR_IWDGRSTF_BitNumber 29U -#define RCC_CSR_WWDGRSTF_BitNumber 30U -#define RCC_CSR_LPWRRSTF_BitNumber 31U +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 /* Flags in the HSITRIM register */ -#define RCC_CR_HSITRIM_BitNumber 3U -#define RCC_HSI14TRIM_BIT_NUMBER 3U +#define RCC_CR_HSITRIM_BitNumber 3 +#define RCC_HSI14TRIM_BIT_NUMBER 3 #define RCC_FLAG_MASK ((uint8_t)0x1FU) /** @@ -244,20 +242,22 @@ typedef struct This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ uint32_t HSI14State; /*!< The new state of the HSI14. This parameter can be a value of @ref RCC_HSI14_Config */ uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ +#if defined(RCC_HSI48_SUPPORT) uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ +#endif /* RCC_HSI48_SUPPORT */ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ } RCC_OscInitTypeDef; @@ -352,7 +352,7 @@ typedef struct /** @defgroup RCC_HSI14_Config RCC HSI14 Config * @{ */ -#define RCC_HSI14_OFF ((uint32_t)0x00000000U) +#define RCC_HSI14_OFF (0x00000000U) #define RCC_HSI14_ON RCC_CR2_HSI14ON #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) @@ -641,56 +641,56 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) @@ -744,35 +744,35 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) @@ -818,56 +818,56 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) @@ -1074,7 +1074,7 @@ typedef struct CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ - }while(0) + }while(0U) /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. @@ -1133,7 +1133,7 @@ typedef struct CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ - }while(0) + }while(0U) /** * @} @@ -1267,7 +1267,7 @@ typedef struct do { \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ - } while(0) + } while(0U) /** @brief Get oscillator clock selected as PLL input clock diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c index c4b7ca86fa2..a5699bfed8a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -61,9 +59,9 @@ * @{ */ /* Bit position in register */ -#define CRS_CFGR_FELIM_BITNUMBER 16U -#define CRS_CR_TRIM_BITNUMBER 8U -#define CRS_ISR_FECAP_BITNUMBER 16U +#define CRS_CFGR_FELIM_BITNUMBER 16 +#define CRS_CR_TRIM_BITNUMBER 8 +#define CRS_ISR_FECAP_BITNUMBER 16 /** * @} */ @@ -387,7 +385,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { + /* frequency == 0 : means that no available frequency for the peripheral */ uint32_t frequency = 0U; + uint32_t srcclk = 0U; #if defined(USB) uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; @@ -418,11 +418,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = HSE_VALUE / 32U; } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; - } break; } case RCC_PERIPHCLK_USART1: @@ -450,11 +445,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for USART1*/ - else - { - frequency = 0U; - } break; } #if defined(RCC_CFGR3_USART2SW) @@ -483,11 +473,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for USART2*/ - else - { - frequency = 0U; - } break; } #endif /* RCC_CFGR3_USART2SW */ @@ -517,11 +502,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for USART3*/ - else - { - frequency = 0U; - } break; } #endif /* RCC_CFGR3_USART3SW */ @@ -540,11 +520,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = HAL_RCC_GetSysClockFreq(); } - /* Clock not enabled for I2C1*/ - else - { - frequency = 0U; - } break; } #if defined(USB) @@ -580,7 +555,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ frequency = (HSI_VALUE / predivfactor) * pllmull; #else - /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */ + /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ frequency = (HSI_VALUE >> 1U) * pllmull; #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ } @@ -592,11 +567,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = HSI48_VALUE; } #endif /* RCC_CR2_HSI48ON */ - /* Clock not enabled for USB*/ - else - { - frequency = 0U; - } break; } #endif /* USB */ @@ -616,11 +586,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = LSE_VALUE; } - /* Clock not enabled for CEC */ - else - { - frequency = 0U; - } break; } #endif /* CEC */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h index c8499b1c155..e86d95010cd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -600,14 +598,14 @@ typedef struct typedef struct { uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF */ + This parameter must be a number between 0 and 0xFFFFU */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ + This parameter must be a number between 0 and 0x3FU */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFF */ + This parameter must be a number between 0 and 0xFFFFU */ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. @@ -839,7 +837,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -849,7 +847,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -864,7 +862,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} @@ -873,7 +871,7 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds +#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} @@ -882,7 +880,7 @@ typedef struct /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ /** * @} */ @@ -890,7 +888,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** @@ -900,7 +898,7 @@ typedef struct /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ /** * @} @@ -962,7 +960,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) @@ -976,7 +974,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) @@ -993,7 +991,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) @@ -1010,7 +1008,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) @@ -1033,7 +1031,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) @@ -1054,7 +1052,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) @@ -1075,7 +1073,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) @@ -1096,14 +1094,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) @@ -1123,7 +1121,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) @@ -1142,7 +1140,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) @@ -1160,21 +1158,21 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) @@ -1192,7 +1190,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) @@ -1208,7 +1206,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ @@ -1222,7 +1220,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) @@ -1236,7 +1234,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) @@ -1258,7 +1256,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) @@ -1275,7 +1273,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) @@ -1289,14 +1287,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) @@ -1942,7 +1940,7 @@ typedef struct { \ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ } \ - } while(0) + } while(0U) /** * @brief Check whether the specified CRS flag is set or not. @@ -1982,7 +1980,7 @@ typedef struct { \ WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ - } while(0) + } while(0U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c index 6f8fba5e47c..c884b7cabd4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -146,7 +144,7 @@ /** * @brief Initialize the RTC according to the specified parameters * in the RTC_InitTypeDef structure and initialize the associated handle. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) @@ -205,7 +203,21 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); @@ -221,7 +233,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /** * @brief DeInitialize the RTC peripheral. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status */ @@ -339,7 +351,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /** * @brief Initialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) @@ -354,7 +366,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) @@ -387,9 +399,9 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Set RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -473,7 +485,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); @@ -511,12 +523,12 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Get RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned * with input format (BIN or BCD), also SubSeconds field returning the * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -566,9 +578,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Set RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -674,9 +686,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Get RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN : Binary data format * @arg RTC_FORMAT_BCD : BCD data format @@ -731,9 +743,9 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Set the specified RTC Alarm. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -876,9 +888,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1028,8 +1040,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactivate the specified RTC Alarm. - * @param hrtc: RTC handle - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @retval HAL status @@ -1085,12 +1097,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /** * @brief Get the RTC Alarm value and masks. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1132,7 +1144,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Handle Alarm interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) @@ -1160,7 +1172,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) @@ -1175,8 +1187,8 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle AlarmA Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1235,7 +1247,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) @@ -1279,7 +1291,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Return the RTC handle state. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL state */ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) @@ -1303,7 +1315,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @brief Enter the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) @@ -1334,7 +1346,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /** * @brief Convert a 2 digit decimal to BCD format. - * @param Value: Byte to be converted + * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) @@ -1352,7 +1364,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) /** * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted + * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h index aaf32fe7767..dd1c54f6327 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -202,8 +200,8 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 (0x00000000U) -#define RTC_HOURFORMAT_12 (0x00000040U) +#define RTC_HOURFORMAT_24 0x00000000U +#define RTC_HOURFORMAT_12 0x00000040U /** * @} @@ -212,8 +210,8 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U) -#define RTC_OUTPUT_POLARITY_LOW (0x00100000U) +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U +#define RTC_OUTPUT_POLARITY_LOW 0x00100000U /** * @} */ @@ -221,8 +219,8 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U) -#define RTC_OUTPUT_TYPE_PUSHPULL (0x00040000U) +#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U +#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U /** * @} */ @@ -230,8 +228,8 @@ typedef struct /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) /** * @} */ @@ -239,9 +237,9 @@ typedef struct /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H (0x00020000U) -#define RTC_DAYLIGHTSAVING_ADD1H (0x00010000U) -#define RTC_DAYLIGHTSAVING_NONE (0x00000000U) +#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U +#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U +#define RTC_DAYLIGHTSAVING_NONE 0x00000000U /** * @} */ @@ -249,8 +247,8 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET (0x00000000U) -#define RTC_STOREOPERATION_SET (0x00040000U) +#define RTC_STOREOPERATION_RESET 0x00000000U +#define RTC_STOREOPERATION_SET 0x00040000U /** * @} */ @@ -258,8 +256,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions * @{ */ -#define RTC_FORMAT_BIN (0x000000000U) -#define RTC_FORMAT_BCD (0x000000001U) +#define RTC_FORMAT_BIN 0x000000000U +#define RTC_FORMAT_BCD 0x000000001U /** * @} */ @@ -268,18 +266,18 @@ typedef struct * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01U) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) -#define RTC_MONTH_MARCH ((uint8_t)0x03U) -#define RTC_MONTH_APRIL ((uint8_t)0x04U) -#define RTC_MONTH_MAY ((uint8_t)0x05U) -#define RTC_MONTH_JUNE ((uint8_t)0x06U) -#define RTC_MONTH_JULY ((uint8_t)0x07U) -#define RTC_MONTH_AUGUST ((uint8_t)0x08U) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) /** * @} */ @@ -287,13 +285,13 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) /** * @} */ @@ -301,8 +299,8 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY (0x40000000U) +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U /** * @} */ @@ -310,12 +308,12 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions * @{ */ -#define RTC_ALARMMASK_NONE (0x00000000U) +#define RTC_ALARMMASK_NONE 0x00000000U #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL (0x80808080U) +#define RTC_ALARMMASK_ALL 0x80808080U /** * @} */ @@ -332,38 +330,38 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL (0x00000000U) /*!< All Alarm SS fields are masked. +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 (0x01000000U) /*!< SS[14:1] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 (0x02000000U) /*!< SS[14:2] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 (0x03000000U) /*!< SS[14:3] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 (0x04000000U) /*!< SS[14:4] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 (0x05000000U) /*!< SS[14:5] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 (0x06000000U) /*!< SS[14:6] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 (0x07000000U) /*!< SS[14:7] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 (0x08000000U) /*!< SS[14:8] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 (0x09000000U) /*!< SS[14:9] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 (0x0A000000U) /*!< SS[14:10] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 (0x0B000000U) /*!< SS[14:11] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 (0x0C000000U) /*!< SS[14:12] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 (0x0D000000U) /*!< SS[14:13] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 (0x0E000000U) /*!< SS[14] is don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE (0x0F000000U) /*!< SS[14:0] are compared and must match +#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match to activate alarm. */ /** * @} @@ -372,13 +370,13 @@ typedef struct /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS (0x00008000U) -#define RTC_IT_WUT (0x00004000U) -#define RTC_IT_ALRA (0x00001000U) -#define RTC_IT_TAMP (0x00000004U) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 (0x00020000U) /*only for RTC_ISR flag check*/ -#define RTC_IT_TAMP2 (0x00040000U) /*only for RTC_ISR flag check*/ -#define RTC_IT_TAMP3 (0x00080000U) /*only for RTC_ISR flag check*/ +#define RTC_IT_TS 0x00008000U +#define RTC_IT_WUT 0x00004000U +#define RTC_IT_ALRA 0x00001000U +#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/ /** * @} */ @@ -386,20 +384,20 @@ typedef struct /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF (0x00010000U) -#define RTC_FLAG_TAMP3F (0x00008000U) -#define RTC_FLAG_TAMP2F (0x00004000U) -#define RTC_FLAG_TAMP1F (0x00002000U) -#define RTC_FLAG_TSOVF (0x00001000U) -#define RTC_FLAG_TSF (0x00000800U) -#define RTC_FLAG_WUTF (0x00000400U) -#define RTC_FLAG_ALRAF (0x00000100U) -#define RTC_FLAG_INITF (0x00000040U) -#define RTC_FLAG_RSF (0x00000020U) -#define RTC_FLAG_INITS (0x00000010U) -#define RTC_FLAG_SHPF (0x00000008U) -#define RTC_FLAG_WUTWF (0x00000004U) -#define RTC_FLAG_ALRAWF (0x00000001U) +#define RTC_FLAG_RECALPF 0x00010000U +#define RTC_FLAG_TAMP3F 0x00008000U +#define RTC_FLAG_TAMP2F 0x00004000U +#define RTC_FLAG_TAMP1F 0x00002000U +#define RTC_FLAG_TSOVF 0x00001000U +#define RTC_FLAG_TSF 0x00000800U +#define RTC_FLAG_WUTF 0x00000400U +#define RTC_FLAG_ALRAF 0x00000100U +#define RTC_FLAG_INITF 0x00000040U +#define RTC_FLAG_RSF 0x00000020U +#define RTC_FLAG_INITS 0x00000010U +#define RTC_FLAG_SHPF 0x00000008U +#define RTC_FLAG_WUTWF 0x00000004U +#define RTC_FLAG_ALRAWF 0x00000001U /** * @} */ @@ -414,14 +412,14 @@ typedef struct */ /** @brief Reset RTC handle state - * @param __HANDLE__: RTC handle. + * @param __HANDLE__ RTC handle. * @retval None */ #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ @@ -432,7 +430,7 @@ typedef struct /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ @@ -442,22 +440,22 @@ typedef struct /** * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -466,8 +464,8 @@ typedef struct /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -476,8 +474,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -486,8 +484,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None @@ -496,8 +494,8 @@ typedef struct /** * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRAWF @@ -507,8 +505,8 @@ typedef struct /** * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_ALRAF * @retval None @@ -674,10 +672,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK (0x007F7F7FU) -#define RTC_DR_RESERVED_MASK (0x00FFFF3FU) -#define RTC_INIT_MASK (0xFFFFFFFFU) -#define RTC_RSF_MASK (0xFFFFFF5FU) +#define RTC_TR_RESERVED_MASK 0x007F7F7FU +#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU #define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \ RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \ RTC_FLAG_WUTF | RTC_FLAG_ALRAF | \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c index fec90ca4714..de88f3ade49 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: @@ -136,15 +134,15 @@ /** * @brief Set TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @retval HAL status @@ -189,16 +187,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Set TimeStamp with Interrupt. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @retval HAL status @@ -250,7 +248,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivate TimeStamp. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) @@ -287,11 +285,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Get the RTC TimeStamp value. - * @param hrtc: RTC handle + * @param hrtc RTC handle - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -344,8 +342,8 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe /** * @brief Set Tamper * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to Tamper Structure. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -392,9 +390,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. + * @param sTamper Pointer to RTC Tamper. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -449,8 +447,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivate Tamper. - * @param hrtc: RTC handle - * @param Tamper: Selected tamper pin. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. * @retval HAL status */ @@ -476,7 +474,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief Handle TimeStamp interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) @@ -548,7 +546,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief TimeStamp callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) @@ -563,7 +561,7 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 1 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) @@ -578,7 +576,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 2 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) @@ -594,7 +592,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Tamper 3 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) @@ -610,8 +608,8 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle TimeStamp polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -649,8 +647,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** * @brief Handle Tamper 1 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -681,8 +679,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Handle Tamper 2 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -714,8 +712,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Handle Tamper 3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -766,9 +764,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Set wake up timer. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -855,9 +853,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /** * @brief Set wake up timer with interrupt. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -956,7 +954,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /** * @brief Deactivate wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -1008,7 +1006,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Get wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval Counter value */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -1019,7 +1017,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Handle Wake Up Timer interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) @@ -1047,7 +1045,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief Wake Up Timer callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) @@ -1063,8 +1061,8 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle Wake Up Timer Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1127,11 +1125,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Write a data in a specified RTC Backup data register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. + * @param Data Data to be written in the specified RTC Backup data register. * @retval None */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) @@ -1150,8 +1148,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /** * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to * specify the register. * @retval Read value @@ -1173,17 +1171,17 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /** * @brief Set the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field @@ -1249,12 +1247,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /** * @brief Configure the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. * This parameter can be one of the following values : * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * @param ShiftSubFS Select the number of Second Fractions to substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ @@ -1344,8 +1342,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /** * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. @@ -1386,7 +1384,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /** * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) @@ -1415,7 +1413,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) /** * @brief Enable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) @@ -1464,7 +1462,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) @@ -1513,7 +1511,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Enable the Bypass Shadow feature. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status @@ -1545,7 +1543,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Disable the Bypass Shadow feature. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h index 38920de9b93..999844d2d79 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention @@ -98,10 +96,10 @@ typedef struct /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition * @{ */ -#define RTC_OUTPUT_DISABLE (0x00000000U) -#define RTC_OUTPUT_ALARMA (0x00200000U) +#define RTC_OUTPUT_DISABLE 0x00000000U +#define RTC_OUTPUT_ALARMA 0x00200000U #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -#define RTC_OUTPUT_WAKEUP (0x00600000U) +#define RTC_OUTPUT_WAKEUP 0x00600000U #endif /** @@ -112,11 +110,11 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition * @{ */ -#define RTC_BKP_DR0 (0x00000000U) -#define RTC_BKP_DR1 (0x00000001U) -#define RTC_BKP_DR2 (0x00000002U) -#define RTC_BKP_DR3 (0x00000003U) -#define RTC_BKP_DR4 (0x00000004U) +#define RTC_BKP_DR0 0x00000000U +#define RTC_BKP_DR1 0x00000001U +#define RTC_BKP_DR2 0x00000002U +#define RTC_BKP_DR3 0x00000003U +#define RTC_BKP_DR4 0x00000004U /** * @} */ @@ -125,8 +123,8 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING (0x00000000U) -#define RTC_TIMESTAMPEDGE_FALLING (0x00000008U) +#define RTC_TIMESTAMPEDGE_RISING 0x00000000U +#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U /** * @} @@ -135,7 +133,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT (0x00000000U) +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U /** * @} @@ -160,8 +158,8 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE (0x00000000U) -#define RTC_TAMPERTRIGGER_FALLINGEDGE (0x00000002U) +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE @@ -173,13 +171,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definition * @{ */ -#define RTC_TAMPERFILTER_DISABLE (0x00000000U) /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE (0x00000800U) /*!< Tamper is activated after 2 +#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE (0x00001000U) /*!< Tamper is activated after 4 +#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE (0x00001800U) /*!< Tamper is activated after 8 +#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8 consecutive samples at the active level. */ /** @@ -189,21 +187,21 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 (0x00000000U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 (0x00000100U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 (0x00000200U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (0x00000300U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 (0x00000400U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (0x00000500U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (0x00000600U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (0x00000700U) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ /** @@ -213,13 +211,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definition * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK (0x00002000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK (0x00004000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (0x00006000U) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ /** @@ -230,7 +228,7 @@ typedef struct * @{ */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} @@ -239,7 +237,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE (0x00000000U) /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */ /** @@ -250,12 +248,12 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 (0x00000001U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 (0x00000002U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (0x00000003U) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (0x00000004U) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (0x00000006U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U /** @@ -266,11 +264,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC (0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC (0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC (0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds */ /** @@ -280,10 +278,10 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definition * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET (0x00008000U) /*!< The number of RTCCLK pulses added +#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET (0x00000000U) /*!< The number of RTCCLK pulses subbstited +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ /** @@ -292,8 +290,8 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ (0x00000000U) -#define RTC_CALIBOUTPUT_1HZ (0x00080000U) +#define RTC_CALIBOUTPUT_512HZ 0x00000000U +#define RTC_CALIBOUTPUT_1HZ 0x00080000U /** * @} @@ -302,8 +300,8 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definition * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U) +#define RTC_SHIFTADD1S_RESET 0x00000000U +#define RTC_SHIFTADD1S_SET 0x80000000U /** * @} @@ -325,22 +323,22 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -349,8 +347,8 @@ typedef struct /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -359,8 +357,8 @@ typedef struct /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -369,8 +367,8 @@ typedef struct /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -379,8 +377,8 @@ typedef struct /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_WUTF * @arg RTC_FLAG_WUTWF @@ -390,8 +388,8 @@ typedef struct /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: * @arg RTC_FLAG_WUTF * @retval None @@ -489,22 +487,22 @@ typedef struct */ /** * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -513,8 +511,8 @@ typedef struct /** * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -523,8 +521,8 @@ typedef struct /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -533,8 +531,8 @@ typedef struct /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -543,8 +541,8 @@ typedef struct /** * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -554,8 +552,8 @@ typedef struct /** * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag to clear. * This parameter can be: * @arg RTC_FLAG_TSF * @retval None @@ -573,28 +571,28 @@ typedef struct /** * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E)) /** * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E)) /** * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E)) /** * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E)) @@ -602,14 +600,14 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E)) /** * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E)) @@ -617,8 +615,8 @@ typedef struct #endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ /** * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -627,8 +625,8 @@ typedef struct /** * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -638,8 +636,8 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt @@ -651,8 +649,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt @@ -664,8 +662,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -675,8 +673,8 @@ typedef struct #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -688,8 +686,8 @@ typedef struct /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -702,8 +700,8 @@ typedef struct /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -714,8 +712,8 @@ typedef struct /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -824,36 +822,36 @@ typedef struct /** * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_SHPF * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c index 441db9a41c2..e111236f300 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -1300,7 +1298,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /** * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1664,7 +1662,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -1759,7 +1757,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1821,7 +1819,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -2169,7 +2167,7 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() @@ -2242,7 +2240,7 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /** * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h index 188b5739651..f8c229ce6fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -581,27 +579,27 @@ typedef struct */ /** @brief Reset SMARTCARD handle states. - * @param __HANDLE__: SMARTCARD handle. + * @param __HANDLE__ SMARTCARD handle. * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - } while(0) + } while(0U) /** @brief Flush the Smartcard Data registers. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag @@ -616,39 +614,39 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) /** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) /** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) /** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) /** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) /** @brief Check whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag @@ -669,8 +667,8 @@ typedef struct /** @brief Enable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -682,13 +680,13 @@ typedef struct * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -700,14 +698,14 @@ typedef struct * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT__ specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -724,8 +722,8 @@ typedef struct #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt source to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt @@ -737,14 +735,14 @@ typedef struct * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__IT__)) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \ + (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag @@ -760,8 +758,8 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request @@ -771,25 +769,25 @@ typedef struct #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -806,42 +804,42 @@ typedef struct /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on F0 (48 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). - * @param __BAUDRATE__: Baud rate set by the configuration function. + * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 3000001U) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. - * @param __LENGTH__: block length. + * @param __LENGTH__ block length. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) /** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__: receiver timeout value. + * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. - * @param __COUNT__: number of retransmissions. + * @param __COUNT__ number of retransmissions. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) /** * @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__: SMARTCARD frame length. + * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) /** * @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__: SMARTCARD frame number of stop bits. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ @@ -849,7 +847,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__: SMARTCARD frame parity. + * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ @@ -857,28 +855,28 @@ typedef struct /** * @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__: SMARTCARD communication mode. + * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U)) /** * @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__: SMARTCARD frame polarity. + * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** * @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__: SMARTCARD frame phase. + * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) /** * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ @@ -886,7 +884,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__: SMARTCARD frame sampling. + * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ @@ -894,7 +892,7 @@ typedef struct /** * @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__: SMARTCARD NACK transmission setting. + * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ @@ -902,7 +900,7 @@ typedef struct /** * @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__: SMARTCARD receiver timeout setting. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ @@ -910,7 +908,7 @@ typedef struct /** * @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__: SMARTCARD advanced features initialization. + * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ @@ -924,7 +922,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__: SMARTCARD frame TX inversion setting. + * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ @@ -932,7 +930,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__: SMARTCARD frame RX inversion setting. + * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ @@ -940,7 +938,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__: SMARTCARD frame data inversion setting. + * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ @@ -948,7 +946,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ @@ -956,7 +954,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__: SMARTCARD frame overrun setting. + * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -964,7 +962,7 @@ typedef struct /** * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -972,7 +970,7 @@ typedef struct /** * @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__: SMARTCARD frame MSB first setting. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -980,7 +978,7 @@ typedef struct /** * @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__: SMARTCARD request parameter. + * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c index 8dd02134bf6..3f764d30f0c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SMARTCARD HAL module driver. * This file provides extended firmware functions to manage the following * functionalities of the SmartCard. @@ -101,9 +99,9 @@ /** * @brief Update on the fly the SMARTCARD block length in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @param BlockLength SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) @@ -113,9 +111,9 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uin /** * @brief Update on the fly the receiver timeout value in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout * value must be less or equal to 0x0FFFFFFFF. * @retval None */ @@ -127,7 +125,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ /** * @brief Enable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -159,7 +157,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @brief Disable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h index 8d9e8b248cd..ce806d4c557 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smartcard_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention @@ -65,8 +63,8 @@ */ /** @brief Report the SMARTCARD clock source. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F031x6) || defined(STM32F038xx) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c index 2ecc371baba..c693b6e8b48 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.c @@ -2,25 +2,23 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SMBUS HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, * based on I2C principles of operation : * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The SMBUS HAL driver can be used as follows: - + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: - SMBUS_HandleTypeDef hsmbus; + SMBUS_HandleTypeDef hsmbus; (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock @@ -28,7 +26,7 @@ (+++) Enable the clock for the SMBUS GPIOs (+++) Configure SMBUS pins as alternate function open-drain (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SMBUSx interrupt priority + (+++) Configure the SMBUSx interrupt priority (+++) Enable the NVIC SMBUS IRQ Channel (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, @@ -92,7 +90,7 @@ [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention @@ -121,8 +119,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -156,7 +154,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -170,6 +168,10 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); + +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -182,19 +184,19 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and + [..] This subsection provides a set of functions allowing to initialize and deinitialize the SMBUSx peripheral: - (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, IT and NVIC ). - (+) Call the function HAL_SMBUS_Init() to configure the selected device with + (+) Call the function HAL_SMBUS_Init() to configure the selected device with the selected configuration: (++) Clock Timing (++) Bus Timeout @@ -210,28 +212,31 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre (++) Peripheral mode - (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration - of the selected SMBUSx peripheral. + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. + + (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and + HAL_SMBUS_ConfigDigitalFilter(). @endverbatim * @{ */ /** - * @brief Initialize the SMBUS according to the specified parameters + * @brief Initialize the SMBUS according to the specified parameters * in the SMBUS_InitTypeDef and initialize the associated handle. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) -{ +{ /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); @@ -245,7 +250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); - if(hsmbus->State == HAL_SMBUS_STATE_RESET) + if (hsmbus->State == HAL_SMBUS_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; @@ -253,17 +258,17 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); } - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); - - /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ /* Configure SMBUSx: Frequency range */ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ /* Configure SMBUSx: Bus Timeout */ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; @@ -272,10 +277,10 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - if(hsmbus->Init.OwnAddress1 != 0U) + + if (hsmbus->Init.OwnAddress1 != 0U) { - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); } @@ -287,41 +292,41 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ /* Configure SMBUSx: Addressing Master mode */ - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) { hsmbus->Instance->CR2 = (I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ /* AUTOEND and NACK bit will be manage during Transfer process */ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); - + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) + && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } /* Enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitialize the SMBUS peripheral. + * @brief DeInitialize the SMBUS peripheral. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -329,29 +334,29 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the SMBUS Peripheral Clock */ __HAL_SMBUS_DISABLE(hsmbus); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_SMBUS_MspDeInit(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; hsmbus->State = HAL_SMBUS_STATE_RESET; - - /* Release Lock */ + + /* Release Lock */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } @@ -361,14 +366,14 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspInit could be implemented in the user file - */ + */ } /** @@ -377,14 +382,112 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspDeInit could be implemented in the user file - */ + */ +} + +/** + * @brief Configure Analog noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref SMBUS_ANALOGFILTER_ENABLE + * @arg @ref SMBUS_ANALOGFILTER_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Reset ANOFF bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hsmbus->Instance->CR1 |= AnalogFilter; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure Digital noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Get the old register value */ + tmpreg = hsmbus->Instance->CR1; + + /* Reset I2C DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos; + + /* Store the new register value */ + hsmbus->Instance->CR1 = tmpreg; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } } /** @@ -392,14 +495,14 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the SMBUS data + This subsection provides a set of functions allowing to manage the SMBUS data transfers. (#) Blocking mode function to check if device is ready for usage is : @@ -408,7 +511,7 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) (#) There is only one mode of transfer: (++) Non-Blocking mode : The communication is performed using Interrupts. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the + The end of the data processing will be indicated through the dedicated SMBUS IRQ when using Interrupt mode. (#) Non-Blocking mode functions with Interrupt are : @@ -446,15 +549,15 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ +{ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Prepare transfer parameters */ @@ -464,12 +567,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -477,50 +580,54 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint { hsmbus->XferSize = Size; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); - + return HAL_OK; } else { return HAL_BUSY; - } + } } /** @@ -539,27 +646,27 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - + /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - - if(Size > MAX_NBYTE_SIZE) + + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -567,42 +674,46 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 { hsmbus->XferSize = Size; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -616,18 +727,18 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) { - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + /* Keep the same state as previous */ /* to perform as well the call of the corresponding end of transfer callback */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; } - else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; } @@ -638,32 +749,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ return HAL_ERROR; } hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -680,11 +791,11 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -692,10 +803,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -704,11 +815,13 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; - hsmbus->XferSize = Size; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - if(Size > MAX_NBYTE_SIZE) + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -718,32 +831,32 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - + /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -753,8 +866,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } else { - return HAL_ERROR; - } + return HAL_ERROR; + } } /** @@ -771,22 +884,22 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -798,13 +911,16 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ hsmbus->XferSize = Size; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + /* Set NBYTE to receive */ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -815,12 +931,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -830,7 +946,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } else { - return HAL_ERROR; + return HAL_ERROR; } } @@ -843,10 +959,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) { hsmbus->State = HAL_SMBUS_STATE_LISTEN; - + /* Enable the Address Match interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } @@ -859,13 +975,13 @@ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) { /* Disable Address listen mode only if a transfer is not ongoing */ - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Disable the Address Match interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } else @@ -883,7 +999,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; /* Clear ALERT flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); @@ -891,7 +1007,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) /* Enable Alert Interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** * @brief Disable the SMBUS alert mode with Interrupt. @@ -902,16 +1018,16 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; - + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + /* Disable Alert Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** - * @brief Check if target device is ready for communication. + * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value @@ -921,72 +1037,72 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ +{ uint32_t tickstart = 0U; - + __IO uint32_t SMBUS_Trials = 0U; - - if(hsmbus->State == HAL_SMBUS_STATE_READY) + + if (hsmbus->State == HAL_SMBUS_STATE_READY) { - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + do { /* Generate Start */ - hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); - + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); return HAL_TIMEOUT; } - } + } } - + /* Check if the NACKF flag has not been set */ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } else { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -997,31 +1113,32 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Clear STOP Flag, auto generated with autoend*/ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - + /* Check if the maximum allowed number of trials has been reached */ if (SMBUS_Trials++ == Trials) { /* Generate Stop */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - }while(SMBUS_Trials < Trials); + } + } + while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; - } + } else { return HAL_BUSY; @@ -1044,28 +1161,28 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t tmpisrvalue = 0U; - + /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); - + /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) - { + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Master_ISR(hsmbus); } } - + /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1073,15 +1190,15 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Master_ISR(hsmbus); } - } - - /* SMBUS in mode Listener Only --------------------------------------------------*/ + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { @@ -1098,79 +1215,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) */ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); - } - - /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); - } - - /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); - } - - /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; - - /* Clear TIMEOUT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); - } - - /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - } - - /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; - - /* Clear PEC error flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); - } - - /* Call the Error Callback in case of Error detected */ - if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) - { - /* Do not Reset the HAL state in case of ALERT error */ - if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) - { - if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) - { - /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ - /* keep HAL_SMBUS_STATE_LISTEN if set */ - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - } - } - - /* Call the Error callback to prevent upper layer */ - HAL_SMBUS_ErrorCallback(hsmbus); - } + SMBUS_ITErrorHandler(hsmbus); } /** @@ -1179,14 +1224,14 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1210,14 +1255,14 @@ __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1240,8 +1285,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @brief Slave Address Match callback. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param TransferDirection: Master request Transfer Direction (Write/Read) - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -1267,7 +1312,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file */ } @@ -1278,29 +1323,29 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ErrorCallback() could be implemented in the user file - */ + */ } /** * @} - */ + */ -/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1332,14 +1377,14 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) /** * @} - */ + */ /** * @} - */ + */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1349,42 +1394,45 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) { uint16_t DevAddress; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - + /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); @@ -1394,21 +1442,21 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + /* REenable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1420,64 +1468,64 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) - { + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferSize--; - hsmbus->XferCount--; + hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); - - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) + else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ - if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1486,10 +1534,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1497,30 +1545,30 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } /* Call TxCpltCallback() if no stop mode is set */ - else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ - + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1529,10 +1577,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1540,39 +1588,39 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { uint8_t TransferDirection = 0U; uint16_t SlaveAddrCode = 0U; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1594,58 +1642,58 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { TransferDirection = SMBUS_GET_DIR(hsmbus); SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); - + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); } - else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { - if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1U) + if (hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0U) + else if (hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ hsmbus->PreviousState = hsmbus->State; hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1660,13 +1708,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; } - } - else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + } + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -1676,7 +1724,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1685,21 +1733,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0U) + if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferCount--; hsmbus->XferSize--; } - - if(hsmbus->XferCount == 0U) + + if (hsmbus->XferCount == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1716,17 +1764,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } /* Check if STOPF is set */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1744,30 +1792,30 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Clear ADDR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_SMBUS_ListenCpltCallback(hsmbus); } } /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + + return HAL_OK; +} /** * @brief Manage the enabling of Interrupts. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1775,40 +1823,40 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { /* Enable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Enable ERR, TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Enable ERR, TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; } - + /* Enable interrupts only at the end */ /* to avoid the risk of SMBUS interrupt handle execution before */ /* all interrupts requested done */ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); - return HAL_OK; + return HAL_OK; } /** * @brief Manage the disabling of Interrupts. @@ -1817,60 +1865,60 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Disable TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1881,9 +1929,95 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); - + return HAL_OK; } + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + /** * @brief Handle SMBUS Communication Timeout. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1893,26 +2027,26 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + if (Status == RESET) + { + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } @@ -1920,25 +2054,25 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu } else { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; } /** @@ -1964,25 +2098,64 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { uint32_t tmpreg = 0U; - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - + /* Get the CR2 register value */ tmpreg = hsmbus->Instance->CR2; - + /* clear tmpreg specific bits */ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); - + /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + /* update CR2 register */ - hsmbus->Instance->CR2 = tmpreg; -} + hsmbus->Instance->CR2 = tmpreg; +} + +/** + * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +{ + /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME */ + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } +} /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h index 8c71042223e..4a499bcef6f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_smbus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32F0xx_HAL_SMBUS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" +#include "stm32f0xx_hal_def.h" /** @addtogroup STM32F0xx_HAL_Driver * @{ @@ -52,25 +50,25 @@ /** @addtogroup SMBUS * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Types SMBUS Exported Types * @{ - */ - + */ + /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition - * @brief SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization + This parameter calculated by referring to SMBUS initialization section in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. This parameter can be a value of @ref SMBUS_Analog_Filter */ - + uint32_t OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ @@ -99,51 +97,51 @@ typedef struct This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; -/** +/** * @} */ /** @defgroup HAL_state_definition HAL state definition - * @brief HAL State definition + * @brief HAL State definition * @{ - */ + */ #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ -/** +/** * @} */ /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition - * @brief SMBUS Error Code definition + * @brief SMBUS Error Code definition * @{ - */ + */ #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ -/** +/** * @} */ -/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition - * @brief SMBUS handle Structure definition +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition * @{ */ typedef struct @@ -168,11 +166,11 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ -}SMBUS_HandleTypeDef; +} SMBUS_HandleTypeDef; /** * @} */ - + /** * @} */ @@ -292,12 +290,24 @@ typedef struct * @{ */ +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) -#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) /** * @} */ @@ -328,7 +338,7 @@ typedef struct * Elements values convention: 0xXXXXYYYY * - XXXXXXXX : Flag mask * @{ - */ + */ #define SMBUS_FLAG_TXE I2C_ISR_TXE #define SMBUS_FLAG_TXIS I2C_ISR_TXIS @@ -357,8 +367,8 @@ typedef struct /* Exported macros ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros * @{ - */ - + */ + /** @brief Reset SMBUS handle state. * @param __HANDLE__ specifies the SMBUS Handle. * @retval None @@ -376,7 +386,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) @@ -392,11 +402,11 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified SMBUS interrupt source is enabled or not. * @param __HANDLE__ specifies the SMBUS Handle. * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. @@ -408,7 +418,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -417,69 +427,69 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) - * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert * @arg @ref SMBUS_FLAG_BUSY Bus busy * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) - * + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) - + /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert - * + * * @retval None */ #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - + /** @brief Enable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} - */ - - + */ + + /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -490,6 +500,8 @@ typedef struct #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) +#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) @@ -503,7 +515,7 @@ typedef struct ((MASK) == SMBUS_OA2_MASK04) || \ ((MASK) == SMBUS_OA2_MASK05) || \ ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) + ((MASK) == SMBUS_OA2_MASK07)) #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ ((CALL) == SMBUS_GENERALCALL_ENABLE)) @@ -521,12 +533,13 @@ typedef struct #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ ((MODE) == SMBUS_AUTOEND_MODE) || \ ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) - - + + #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ ((REQUEST) == SMBUS_GENERATE_START_READ) || \ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ @@ -538,7 +551,13 @@ typedef struct ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ + IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) @@ -560,16 +579,7 @@ typedef struct /** * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Functions SMBUS Private Functions - * @{ */ -/* Private functions are defined in stm32f0xx_hal_smbus.c file */ -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions @@ -579,12 +589,14 @@ typedef struct /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - + /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); /** * @} @@ -593,7 +605,7 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions * @{ */ - + /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling * @{ @@ -640,7 +652,7 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions * @{ */ @@ -654,7 +666,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup SMBUS_Private_Functions SMBUS Private Functions @@ -663,23 +675,19 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /* Private functions are defined in stm32f0xx_hal_smbus.c file */ /** * @} - */ - -/** - * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c index d7a4f6b96fb..1fc6912ecb7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -60,9 +58,24 @@ (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() [..] - Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, - the following table resume the max SPI frequency reached with data size 8bits/16bits, - according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI + modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the + maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on + the APBx peripheral clock frequency (fPCLK) used by the SPI instance. + + [..] + Data buffer address alignment restriction: + (#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer. + But there is no support for unaligned accesses on the Cortex-M0 processor. + So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for: + (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT() + (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT() + (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA() + and HAL_SPI_TransmitReceive_DMA(). + + @endverbatim + + Additional table : DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ @@ -120,7 +133,6 @@ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - @endverbatim ****************************************************************************** * @attention * @@ -262,7 +274,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -349,7 +361,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit, CRC calculation state */ + Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); @@ -361,7 +373,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif /* USE_SPI_CRC */ - /* Configure : NSS management, TI Mode and Rx Fifo Threshold */ + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); @@ -387,7 +399,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -421,7 +433,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -437,7 +449,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -490,11 +502,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -502,6 +514,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -561,7 +580,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) { hspi->Instance->DR = *((uint16_t *)pData); pData += sizeof(uint16_t); @@ -591,7 +610,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ else { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) { if (hspi->TxXferCount > 1U) { @@ -669,11 +688,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -684,6 +703,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -733,7 +759,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ - /* Set the Rx Fido threshold */ + /* Set the Rx FiFo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* set fiforxthresold according the reception data length: 16bit */ @@ -899,12 +925,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, @@ -919,6 +945,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD uint32_t txallowed = 1U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -971,8 +1005,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } #endif /* USE_SPI_CRC */ - /* Set the Rx Fido threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) { /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1191,16 +1225,23 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1274,16 +1315,23 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData)); + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1319,16 +1367,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->TxXferCount = 0U; hspi->TxISR = NULL; - /* check the data size to adapt Rx threshold and the set the function for IT treatment */ + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* Set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* Set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } @@ -1378,11 +1426,11 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1390,6 +1438,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U)) + { + /* in this case, 16-bit access is performed on Data + So, check Data is 16-bit aligned address */ + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData)); + assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData)); + } + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1456,15 +1512,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } #endif /* USE_SPI_CRC */ - /* check if packing mode is enabled and if there is more than 2 data to receive */ + /* Check if packing mode is enabled and if there is more than 2 data to receive */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* Set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* Set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1486,16 +1542,19 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + /* check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1555,7 +1614,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->hdmatx->XferAbortCallback = NULL; CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - /* packing mode is enabled only if the DMA setting is HALWORD */ + /* Packing mode is enabled only if the DMA setting is HALWORD */ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Check the even/odd of the data size + crc if enabled */ @@ -1595,20 +1654,28 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + /* check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } @@ -1656,7 +1723,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u #endif /* USE_SPI_CRC */ #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx) - /* packing mode management is enabled by the DMA settings */ + /* Packing mode management is enabled by the DMA settings */ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Restriction the DMA data received is not allowed in this mode */ @@ -1668,14 +1735,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { /* set fiforxthresold according the reception data length: 16bit */ @@ -1730,12 +1797,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, @@ -1744,6 +1811,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + /* check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1802,18 +1873,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } #endif + /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - /* the packing mode management is enabled by the DMA settings according the spi data size */ + /* The packing mode management is enabled by the DMA settings according the spi data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthreshold according the reception data length: 16bit */ + /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) @@ -1832,7 +1904,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -1918,25 +1990,46 @@ error : HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; + __IO uint32_t count, resetcount; /* Initialized local variable */ errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { hspi->TxISR = SPI_AbortTx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) { hspi->RxISR = SPI_AbortRx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } /* Clear ERRIE interrupts in case of DMA Mode */ @@ -2052,26 +2145,47 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; uint32_t abortcplt ; + __IO uint32_t count, resetcount; /* Initialized local variable */ errorcode = HAL_OK; abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { hspi->TxISR = SPI_AbortTx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) { hspi->RxISR = SPI_AbortRx_ISR; - while (hspi->State != HAL_SPI_STATE_ABORT) + /* Wait HAL_SPI_STATE_ABORT state */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; } /* Clear ERRIE interrupts in case of DMA Mode */ @@ -2213,7 +2327,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2233,7 +2347,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2253,7 +2367,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) /** * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2284,7 +2398,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2380,7 +2494,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2396,7 +2510,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2412,7 +2526,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2428,7 +2542,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2444,7 +2558,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2460,7 +2574,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2476,7 +2590,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2529,7 +2643,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2541,7 +2655,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2566,7 +2680,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2613,7 +2727,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2704,7 +2818,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2789,7 +2903,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2802,7 +2916,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2815,7 +2929,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2828,7 +2942,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2986,7 +3100,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3036,7 +3150,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3068,7 +3182,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3114,7 +3228,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3148,7 +3262,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3172,7 +3286,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3210,7 +3324,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3235,7 +3349,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3268,7 +3382,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3291,7 +3405,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3324,7 +3438,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3348,7 +3462,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3374,12 +3488,12 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, @@ -3426,12 +3540,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Fifo: Fifo to check - * @param State: Fifo state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, @@ -3487,10 +3601,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3524,9 +3638,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /** * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3537,18 +3651,26 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } return HAL_OK; } /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3605,7 +3727,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3647,7 +3769,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3686,21 +3808,32 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { + __IO uint32_t count; + /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + /* Check RXNEIE is disabled */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) @@ -3719,18 +3852,29 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + /* Check TXEIE is disabled */ + do { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h index 109a19e2ee8..4c62440bad0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -99,7 +97,7 @@ typedef struct This parameter can be a value of @ref SPI_CRC_Calculation */ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size @@ -253,7 +251,7 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_NSS_SOFT SPI_CR1_SSM #define SPI_NSS_HARD_INPUT (0x00000000U) -#define SPI_NSS_HARD_OUTPUT (0x00040000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) /** * @} */ @@ -271,13 +269,13 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) -#define SPI_BAUDRATEPRESCALER_4 (0x00000008U) -#define SPI_BAUDRATEPRESCALER_8 (0x00000010U) -#define SPI_BAUDRATEPRESCALER_16 (0x00000018U) -#define SPI_BAUDRATEPRESCALER_32 (0x00000020U) -#define SPI_BAUDRATEPRESCALER_64 (0x00000028U) -#define SPI_BAUDRATEPRESCALER_128 (0x00000030U) -#define SPI_BAUDRATEPRESCALER_256 (0x00000038U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /** * @} */ @@ -368,10 +366,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level * @{ */ -#define SPI_FTLVL_EMPTY (0x00000000U) -#define SPI_FTLVL_QUARTER_FULL (0x00000800U) -#define SPI_FTLVL_HALF_FULL (0x00001000U) -#define SPI_FTLVL_FULL (0x00001800U) +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) /** * @} @@ -380,10 +378,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ */ -#define SPI_FRLVL_EMPTY (0x00000000U) -#define SPI_FRLVL_QUARTER_FULL (0x00000200U) -#define SPI_FRLVL_HALF_FULL (0x00000400U) -#define SPI_FRLVL_FULL (0x00000600U) +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) /** * @} */ @@ -391,36 +389,47 @@ typedef struct __SPI_HandleTypeDef /** * @} */ - + /* Exported macros -----------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros * @{ */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -/** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -430,9 +439,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -448,27 +457,27 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_modf = 0x00U; \ - tmpreg_modf = (__HANDLE__)->Instance->SR; \ - (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ - UNUSED(tmpreg_modf); \ - } while(0) +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -478,10 +487,10 @@ typedef struct __SPI_HandleTypeDef tmpreg_ovr = (__HANDLE__)->Instance->DR; \ tmpreg_ovr = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_ovr); \ - } while(0) + } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -490,21 +499,21 @@ typedef struct __SPI_HandleTypeDef __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0) + }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** * @} @@ -516,26 +525,26 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ - (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) @@ -600,6 +609,10 @@ typedef struct __SPI_HandleTypeDef #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) +#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) + +#define IS_SPI_16BIT_ALIGNED_ADDRESS(DATA) (((uint32_t)(DATA) % 2U) == 0U) + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c index 52fe0e22877..2ae2a39ed68 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : @@ -57,7 +55,7 @@ /** @defgroup SPIEx_Private_Constants SPIEx Private Constants * @{ */ -#define SPI_FIFO_SIZE 4U +#define SPI_FIFO_SIZE 4 /** * @} */ @@ -72,8 +70,8 @@ */ /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -91,7 +89,7 @@ /** * @brief Flush the RX fifo. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h index 58632d95381..776447667dc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi_ex.h @@ -1,39 +1,37 @@ /** - ****************************************************************************** - * @file stm32f0xx_hal_spi_ex.h - * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 - * @brief Header file of SPI HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32f0xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_SPI_EX_H @@ -56,7 +54,7 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SPIEx_Exported_Functions * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c index 7f8980566a0..459f3624e46 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -199,7 +197,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) @@ -239,7 +237,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM Base peripheral - * @param htim : TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) @@ -266,7 +264,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -281,7 +279,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Base MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -297,7 +295,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) @@ -320,7 +318,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) @@ -343,7 +341,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) @@ -363,7 +361,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) @@ -382,9 +380,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to peripheral. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -428,7 +426,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) @@ -477,7 +475,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) @@ -517,7 +515,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitializes the TIM peripheral - * @param htim : TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) @@ -544,7 +542,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -559,7 +557,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -574,8 +572,8 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -606,8 +604,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -638,8 +636,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -704,8 +702,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -770,15 +768,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -889,8 +887,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -984,7 +982,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) @@ -1024,7 +1022,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1051,7 +1049,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1066,7 +1064,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM PWM MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1081,8 +1079,8 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1113,8 +1111,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1148,8 +1146,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1214,8 +1212,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1280,15 +1278,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1399,8 +1397,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1494,7 +1492,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) @@ -1534,7 +1532,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim : TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) @@ -1561,7 +1559,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Input Capture MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1576,7 +1574,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) @@ -1591,8 +1589,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1617,8 +1615,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1643,8 +1641,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1702,8 +1700,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1762,15 +1760,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The destination Buffer address. - * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1877,8 +1875,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1966,8 +1964,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim : TIM OnePulse handle - * @param OnePulseMode : Select the One pulse mode. + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. @@ -2017,7 +2015,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitializes the TIM One Pulse - * @param htim : TIM One Pulse handle + * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) @@ -2044,7 +2042,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2059,7 +2057,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2074,8 +2072,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2107,8 +2105,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2140,8 +2138,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2179,8 +2177,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2242,8 +2240,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim : TIM Encoder Interface handle - * @param sConfig : TIM Encoder Interface configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2336,7 +2334,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitializes the TIM Encoder interface - * @param htim : TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2363,7 +2361,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2378,7 +2376,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2393,8 +2391,8 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2435,8 +2433,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2479,8 +2477,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2527,8 +2525,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2578,15 +2576,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 : The destination Buffer address for IC1. - * @param pData2 : The destination Buffer address for IC2. - * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2698,8 +2696,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2765,7 +2763,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) @@ -2921,9 +2919,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim : TIM Output Compare handle - * @param sConfig : TIM Output Compare configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2990,9 +2988,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim : TIM IC handle - * @param sConfig : TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3086,9 +3084,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim : TIM handle - * @param sConfig : TIM PWM configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3184,13 +3182,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim : TIM One Pulse handle - * @param sConfig : TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled + * @param InputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3296,8 +3294,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim : TIM handle - * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3318,7 +3316,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc : TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3327,19 +3325,66 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer : The Buffer address. - * @param BurstLength : DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) + uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -3367,7 +3412,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC1: @@ -3379,7 +3424,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC2: @@ -3391,7 +3436,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC3: @@ -3403,7 +3448,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_CC4: @@ -3415,7 +3460,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_COM: @@ -3427,7 +3472,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; case TIM_DMA_TRIGGER: @@ -3439,7 +3484,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); } break; default: @@ -3459,8 +3504,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim : TIM handle - * @param BurstRequestSrc : TIM DMA Request sources to disable + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3519,8 +3564,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim : TIM handle - * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3541,7 +3586,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc : TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3550,19 +3595,66 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer : The Buffer address. - * @param BurstLength : DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ +return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -3590,7 +3682,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC1: @@ -3602,7 +3694,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC2: @@ -3614,7 +3706,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC3: @@ -3626,7 +3718,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_CC4: @@ -3638,7 +3730,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_COM: @@ -3650,7 +3742,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; case TIM_DMA_TRIGGER: @@ -3662,7 +3754,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); } break; default: @@ -3683,8 +3775,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim : TIM handle - * @param BurstRequestSrc : TIM DMA Request sources to disable. + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3743,8 +3835,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim : TIM handle - * @param EventSource : specifies the event source. + * @param htim TIM handle + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3785,10 +3877,10 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim : TIM handle - * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel : specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 @@ -3919,8 +4011,8 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C /** * @brief Configures the clock source to be used - * @param htim : TIM handle - * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4089,8 +4181,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim : TIM handle. - * @param TI1_Selection : Indicate whether or not channel 1 is connected to the + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4123,8 +4215,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim : TIM handle. - * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4158,8 +4250,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4194,8 +4286,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, /** * @brief Read the captured value from Capture Compare unit - * @param htim : TIM handle. - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1 : TIM Channel 1 selected * @arg TIM_CHANNEL_2 : TIM Channel 2 selected @@ -4287,7 +4379,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -4302,7 +4394,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non blocking mode - * @param htim : TIM OC handle + * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -4316,7 +4408,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non blocking mode - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) @@ -4331,7 +4423,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -4346,7 +4438,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -4361,7 +4453,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) @@ -4395,7 +4487,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base state - * @param htim : TIM Base handle + * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) @@ -4405,7 +4497,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC state - * @param htim : TIM Ouput Compare handle + * @param htim TIM Ouput Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4415,7 +4507,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM state - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) @@ -4425,7 +4517,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture state - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) @@ -4435,7 +4527,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode state - * @param htim : TIM OPM handle + * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) @@ -4445,7 +4537,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode state - * @param htim : TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4467,7 +4559,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) @@ -4481,7 +4573,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) @@ -4513,7 +4605,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) } /** * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) @@ -4546,7 +4638,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4560,7 +4652,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) @@ -4574,8 +4666,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Base configuration - * @param TIMx : TIM periheral - * @param Structure : TIM Base configuration structure + * @param TIMx TIM periheral + * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4623,7 +4715,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Time Ouput Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4697,7 +4789,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4773,7 +4865,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4847,7 +4939,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config : The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5029,17 +5121,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 @@ -5084,12 +5176,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5119,17 +5211,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 @@ -5167,12 +5259,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5202,17 +5294,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 @@ -5250,17 +5342,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection : specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter : Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be @@ -5298,7 +5390,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param InputTriggerSource : The Input Trigger source. + * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0 : Internal Trigger 0 * @arg TIM_TS_ITR1 : Internal Trigger 1 @@ -5326,17 +5418,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity : The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter : External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ @@ -5360,13 +5452,13 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel : specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1 : TIM Channel 1 * @arg TIM_CHANNEL_2 : TIM Channel 2 * @arg TIM_CHANNEL_3 : TIM Channel 3 * @arg TIM_CHANNEL_4 : TIM Channel 4 - * @param ChannelState : specifies the TIM Channel CCxE bit new state. + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h index 88f1edfcb32..410138aee6c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -1094,12 +1092,14 @@ typedef struct ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) /** @brief Set TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __ICPSC__: specifies the prescaler value. + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __ICPSC__ specifies the prescaler value. * @retval None */ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ @@ -1109,8 +1109,8 @@ typedef struct ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) /** @brief Reset TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel * @retval None */ #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ @@ -1121,9 +1121,9 @@ typedef struct /** @brief Set TIM IC polarity - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __POLARITY__: specifies TIM Channel Polarity + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel + * @param __POLARITY__ specifies TIM Channel Polarity * @retval None */ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ @@ -1133,8 +1133,8 @@ typedef struct ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) /** @brief Reset TIM IC polarity - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel + * @param __HANDLE__ TIM handle + * @param __CHANNEL__ specifies TIM Channel * @retval None */ #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ @@ -1168,28 +1168,28 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat */ /** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -1206,7 +1206,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat channels have been disabled */ /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ @@ -1221,10 +1221,19 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat } \ } while(0) +/* The Main Output Enable of a timer instance is disabled unconditionally */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled uncondiotionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + /** * @brief Enables the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1240,8 +1249,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Disables the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1257,8 +1266,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Enables the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1273,8 +1282,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Disables the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1289,8 +1298,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Checks whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1310,8 +1319,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Clears the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1331,23 +1340,23 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief Checks whether the specified TIM interrupt has occurred or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Clear the TIM interrupt pending bits - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1356,8 +1365,8 @@ mode. /** * @brief Sets the TIM active prescaler register value on update event. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the active prescaler register new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the active prescaler register new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) @@ -1365,14 +1374,14 @@ mode. /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1380,30 +1389,30 @@ mode. /** * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval None + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) /** * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) @@ -1411,8 +1420,8 @@ mode. /** * @brief Sets the TIM Autoreload Register value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1423,8 +1432,8 @@ mode. /** * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) @@ -1432,12 +1441,12 @@ mode. /** * @brief Sets the TIM Clock Division value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ @@ -1449,16 +1458,19 @@ mode. /** * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Sets the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1474,8 +1486,8 @@ mode. /** * @brief Resets the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1493,14 +1505,14 @@ mode. /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1516,14 +1528,18 @@ mode. /** * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ @@ -1533,7 +1549,7 @@ mode. /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) @@ -1544,7 +1560,7 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): @@ -1558,14 +1574,14 @@ mode. /** * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge @@ -1739,9 +1755,13 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c index 12ce47214c8..9bf2c75d28f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -153,8 +151,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim : TIM Encoder Interface handle - * @param sConfig : TIM Hall Sensor configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -233,7 +231,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -260,7 +258,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -275,7 +273,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -290,7 +288,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) @@ -311,7 +309,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) @@ -332,7 +330,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) @@ -356,7 +354,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) @@ -380,9 +378,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM Hall Sensor handle - * @param pData : The destination Buffer address. - * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -429,7 +427,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) @@ -479,8 +477,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -509,8 +507,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -539,8 +537,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -606,8 +604,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -679,15 +677,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -796,8 +794,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -896,8 +894,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -925,8 +923,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -955,8 +953,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1022,8 +1020,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1095,15 +1093,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData : The source Buffer address. - * @param Length : The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1212,8 +1210,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1301,8 +1299,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complemetary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1326,8 +1324,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1355,8 +1353,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1386,8 +1384,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1445,15 +1443,15 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim : TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1494,15 +1492,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim : TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1547,15 +1545,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim : TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1599,8 +1597,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim : TIM handle. - * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1636,8 +1634,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim : TIM handle - * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1686,8 +1684,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM14 Remapping input capabilities. - * @param htim : TIM handle. - * @param Remap : specifies the TIM remapping source. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. * This parameter can be one of the following values: * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock @@ -1725,10 +1723,10 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) defined(STM32F091xC) || defined (STM32F098xx) /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 @@ -1890,7 +1888,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /** * @brief Hall commutation changed callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) @@ -1905,7 +1903,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) @@ -1920,7 +1918,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) @@ -1953,7 +1951,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Return the TIM Hall Sensor interface state - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) @@ -1976,12 +1974,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel : specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState : specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h index 3e614681aec..a504794e8c7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c index 493b963f3dc..eaf1697a913 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and DeInitialization @@ -153,7 +151,7 @@ static uint32_t TSC_extract_groups(uint32_t iomask); /** * @brief Initializes the TSC peripheral according to the specified parameters * in the TSC_InitTypeDef structure. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) @@ -241,7 +239,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) /** * @brief Deinitializes the TSC peripheral registers to their default reset values. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) @@ -273,7 +271,7 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) /** * @brief Initializes the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -289,7 +287,7 @@ __weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc) /** * @brief DeInitializes the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -327,7 +325,7 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) /** * @brief Starts the acquisition. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ @@ -370,7 +368,7 @@ HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) /** * @brief Enables the interrupt and starts the acquisition - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status. */ @@ -424,7 +422,7 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) /** * @brief Stops the acquisition previously launched in polling mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ @@ -457,7 +455,7 @@ HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc) /** * @brief Stops the acquisition previously launched in interrupt mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ @@ -493,9 +491,9 @@ HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) /** * @brief Gets the acquisition status for a group - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Group status */ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index) @@ -510,9 +508,9 @@ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t /** * @brief Gets the acquisition measure for a group - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Acquisition measure */ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) @@ -545,9 +543,9 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) /** * @brief Configures TSC IOs - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param config: pointer to the configuration structure. + * @param config pointer to the configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config) @@ -582,9 +580,9 @@ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* /** * @brief Discharge TSC IOs - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param choice: enable or disable + * @param choice enable or disable * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) @@ -634,7 +632,7 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) /** * @brief Return the TSC state - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ @@ -670,7 +668,7 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) * @brief Start acquisition and wait until completion * @note There is no need of a timeout parameter as the max count error is already * managed by the TSC peripheral. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ @@ -696,7 +694,7 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) /** * @brief Handles TSC interrupt request - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -742,7 +740,7 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /** * @brief Acquisition completed callback in non blocking mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -758,7 +756,7 @@ __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) /** * @brief Error callback in non blocking mode - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ @@ -786,7 +784,7 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) /** * @brief Utility function used to set the acquired groups mask - * @param iomask: Channels IOs mask + * @param iomask Channels IOs mask * @retval Acquired groups mask */ static uint32_t TSC_extract_groups(uint32_t iomask) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h index 677d1bd721e..8972469eb5e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief This file contains all the functions prototypes for the TSC firmware * library. ****************************************************************************** @@ -439,189 +437,189 @@ typedef struct */ /** @brief Reset TSC handle state - * @param __HANDLE__: TSC handle. + * @param __HANDLE__ TSC handle. * @retval None */ #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) /** * @brief Enable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) /** * @brief Disable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) /** * @brief Start acquisition - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) /** * @brief Stop acquisition - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) /** * @brief Set IO default mode to output push-pull low - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) /** * @brief Set IO default mode to input floating - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) /** * @brief Set synchronization polarity to falling edge - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) /** * @brief Set synchronization polarity to rising edge and high level - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) /** * @brief Enable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** * @brief Disable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) /** @brief Check if the specified TSC interrupt source is enabled or disabled. - * @param __HANDLE__: TSC Handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC Handle + * @param __INTERRUPT__ TSC interrupt * @retval SET or RESET */ #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Get the selected TSC's flag status. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval SET or RESET */ #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @brief Clear the TSC's pending flag. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval None */ #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable schmitt trigger hysteresis on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) /** * @brief Disable schmitt trigger hysteresis on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Open analog switch on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Close analog switch on a group of IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) /** * @brief Enable a group of IOs in channel mode - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of channel IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Enable a group of IOs in sampling mode - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of sampling IOs - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) /** * @brief Enable acquisition groups - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) /** * @brief Disable acquisition groups - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) /** @brief Gets acquisition group status - * @param __HANDLE__: TSC Handle - * @param __GX_INDEX__: Group index + * @param __HANDLE__ TSC Handle + * @param __GX_INDEX__ Group index * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c index b9bed699827..564e2a67d14 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -287,7 +285,7 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /** * @brief Initialize the UART mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -366,7 +364,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -439,9 +437,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the multiprocessor mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod specifies the UART wakeup method. * This parameter can be one of the following values: * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark @@ -531,7 +529,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitialize the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -569,7 +567,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief Initialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) @@ -584,7 +582,7 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) /** * @brief DeInitialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) @@ -680,10 +678,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, @@ -764,10 +762,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, @@ -851,9 +849,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, @@ -907,9 +905,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled using u16 pointer cast). Depending on compilation chain, @@ -969,9 +967,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, @@ -1044,9 +1042,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, @@ -1121,7 +1119,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pause the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) @@ -1154,7 +1152,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /** * @brief Resume the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) @@ -1188,7 +1186,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /** * @brief Stop the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) @@ -1652,7 +1650,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /** * @brief Handle UART interrupt request. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) @@ -1806,7 +1804,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1821,7 +1819,7 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1836,7 +1834,7 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) @@ -1851,7 +1849,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1866,7 +1864,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1949,7 +1947,7 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) @@ -1970,7 +1968,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) /** * @brief Disable UART mute mode (does not mean the UART actually exits mute mode * as it may not have been in mute mode at this very moment). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) @@ -1991,7 +1989,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) /** * @brief Enter UART mute mode (means UART actually enters mute mode). * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -2001,7 +1999,7 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) @@ -2025,7 +2023,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -2105,7 +2103,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) @@ -2210,7 +2208,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral advanced features. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h index 4731c435de1..b6ac309cce5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -408,19 +406,16 @@ typedef struct */ /** @defgroup UART_IT UART IT - * Elements values convention: 000000000XXYYYYYb + * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) * - 01: CR1 register * - 10: CR2 register * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ #define UART_IT_ERR (0x0060U) /*!< UART error interruption */ - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ #define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */ #define UART_IT_NE (0x0200U) /*!< UART noise error interruption */ #define UART_IT_FE (0x0100U) /*!< UART frame error interruption */ @@ -585,7 +580,7 @@ typedef struct */ /** @brief Reset UART handle states. - * @param __HANDLE__: UART handle. + * @param __HANDLE__ UART handle. * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -594,8 +589,8 @@ typedef struct } while(0) /** @brief Clear the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag @@ -635,38 +630,38 @@ typedef struct #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) /** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -722,8 +717,8 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -757,8 +752,8 @@ typedef struct /** @brief Disable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -791,8 +786,8 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT__ specifies the UART interrupt to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -825,8 +820,8 @@ typedef struct #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt source to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -858,8 +853,8 @@ typedef struct (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK))) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag @@ -900,8 +895,8 @@ typedef struct #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref UART_SENDBREAK_REQUEST Send Break Request @@ -920,25 +915,25 @@ typedef struct #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) /** @brief Enable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -952,7 +947,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ @@ -970,7 +965,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ @@ -988,7 +983,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ @@ -1006,7 +1001,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ @@ -1025,21 +1020,21 @@ typedef struct */ /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check UART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. + * @param __BAUDRATE__ Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) @@ -1047,20 +1042,20 @@ typedef struct #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U) /** @brief Check UART assertion time. - * @param __TIME__: 5-bit value assertion time. + * @param __TIME__ 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ #define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) /** @brief Check UART deassertion time. - * @param __TIME__: 5-bit value deassertion time. + * @param __TIME__ 5-bit value deassertion time. * @retval Test result (TRUE or FALSE). */ #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) /** * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__: UART frame number of stop bits. + * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #ifdef USART_SMARTCARD_SUPPORT @@ -1075,7 +1070,7 @@ typedef struct /** * @brief Ensure that UART frame parity is valid. - * @param __PARITY__: UART frame parity. + * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ @@ -1084,7 +1079,7 @@ typedef struct /** * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__: UART hardware flow control. + * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ @@ -1095,14 +1090,14 @@ typedef struct /** * @brief Ensure that UART communication mode is valid. - * @param __MODE__: UART communication mode. + * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. - * @param __STATE__: UART state. + * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ @@ -1110,7 +1105,7 @@ typedef struct /** * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__: UART oversampling. + * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ @@ -1118,7 +1113,7 @@ typedef struct /** * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__: UART frame sampling. + * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ @@ -1126,7 +1121,7 @@ typedef struct /** * @brief Ensure that Address Length detection parameter is valid. - * @param __ADDRESS__: UART Adress length value. + * @param __ADDRESS__ UART Adress length value. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ @@ -1134,7 +1129,7 @@ typedef struct /** * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__: UART receiver timeout setting. + * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ @@ -1142,7 +1137,7 @@ typedef struct /** * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__: UART DMA TX state. + * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ @@ -1150,7 +1145,7 @@ typedef struct /** * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__: UART DMA RX state. + * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ @@ -1158,7 +1153,7 @@ typedef struct /** * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__: UART half-duplex state. + * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ @@ -1166,7 +1161,7 @@ typedef struct /** * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__: UART wake-up method . + * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ @@ -1174,7 +1169,7 @@ typedef struct /** * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__: UART advanced features initialization. + * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ @@ -1189,7 +1184,7 @@ typedef struct /** * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__: UART frame TX inversion setting. + * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ @@ -1197,7 +1192,7 @@ typedef struct /** * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__: UART frame RX inversion setting. + * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ @@ -1205,7 +1200,7 @@ typedef struct /** * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__: UART frame data inversion setting. + * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ @@ -1213,7 +1208,7 @@ typedef struct /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__: UART frame RX/TX pins swap setting. + * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ @@ -1221,7 +1216,7 @@ typedef struct /** * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__: UART frame overrun setting. + * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -1229,7 +1224,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__: UART auto Baud rate state. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ @@ -1237,7 +1232,7 @@ typedef struct /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__: UART DMA enabling or disabling on error setting. + * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -1245,7 +1240,7 @@ typedef struct /** * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__: UART frame MSB first setting. + * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1253,7 +1248,7 @@ typedef struct /** * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__: UART mute mode state. + * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ @@ -1261,7 +1256,7 @@ typedef struct /** * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__: UART driver enable polarity. + * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c index 448174330d4..d9fcb1f8772 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -165,16 +163,16 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. + * @param huart UART handle. + * @param Polarity select the driver enable polarity. * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: + * @param AssertionTime Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: + * @param DeassertionTime Driver Enable deassertion time: * 5-bit value defining the time between the end of the last stop bit, in a * transmitted message, and the de-activation of the DE (Driver Enable) signal. * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the @@ -249,8 +247,8 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /** * @brief Initialize the LIN mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. + * @param huart UART handle. + * @param BreakDetectLength specifies the LIN break detection length. * This parameter can be one of the following values: * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection @@ -349,7 +347,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief UART wakeup from Stop mode callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) @@ -393,8 +391,8 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief Set Wakeup from Stop mode interrupt flag selection. - * @param huart: UART handle. - * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. + * @param huart UART handle. + * @param WakeUpSelection address match, Start Bit detection or RXNE bit status. * This parameter can be one of the following values: * @arg @ref UART_WAKEUP_ON_ADDRESS * @arg @ref UART_WAKEUP_ON_STARTBIT @@ -454,7 +452,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /** * @brief Enable UART Stop Mode. * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) @@ -480,7 +478,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) /** * @brief Disable UART Stop Mode. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) @@ -512,8 +510,8 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: + * @param huart UART handle. + * @param AddressLength this parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status @@ -548,7 +546,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief Transmit break characters. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) @@ -588,8 +586,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart: UART handle. - * @param WakeUpSelection: UART wake up from stop mode parameters. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. * @retval None */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h index 68ef6fdea70..916a98e96a7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of UART HAL Extended module. ****************************************************************************** * @attention @@ -283,7 +281,7 @@ typedef struct */ /** @brief Flush the UART Data registers. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #if !defined(STM32F030x6) && !defined(STM32F030x8) @@ -309,8 +307,8 @@ typedef struct */ /** @brief Report the UART clock source. - * @param __HANDLE__: specifies the UART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) @@ -619,7 +617,7 @@ typedef struct * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -693,7 +691,7 @@ typedef struct /** * @brief Ensure that UART frame length is valid. - * @param __LENGTH__: UART frame length. + * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -711,7 +709,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__: UART auto Baud rate detection mode. + * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -732,7 +730,7 @@ typedef struct #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Ensure that UART LIN state is valid. - * @param __LIN__: UART LIN state. + * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ @@ -740,7 +738,7 @@ typedef struct /** * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__: UART LIN break detection length. + * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ @@ -749,7 +747,7 @@ typedef struct /** * @brief Ensure that UART request parameter is valid. - * @param __PARAM__: UART request parameter. + * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) @@ -768,7 +766,7 @@ typedef struct #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__: UART stop mode state. + * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ @@ -776,7 +774,7 @@ typedef struct /** * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__: UART wake-up selection. + * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c index 456ebd97e42..ad262a931cc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter @@ -369,7 +367,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Initialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) @@ -384,7 +382,7 @@ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) /** * @brief DeInitialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) @@ -1108,7 +1106,6 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Enable the USART transmit DMA channel: the transmit channel is used in order to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive mode */ - tmp = (uint32_t*)&pRxData; /* Set the USART DMA Tx Complete and Error callback to Null */ husart->hdmatx->XferErrorCallback = NULL; husart->hdmatx->XferHalfCpltCallback = NULL; @@ -1720,7 +1717,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) @@ -1735,7 +1732,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1750,7 +1747,7 @@ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) @@ -1765,7 +1762,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1780,7 +1777,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) @@ -1795,7 +1792,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) @@ -1846,7 +1843,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) /** * @brief Return the USART handle state. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle state */ @@ -1857,7 +1854,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) /** * @brief Return the USART error code. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle Error Code */ @@ -2014,7 +2011,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMAError(DMA_HandleTypeDef *hdma) @@ -2166,7 +2163,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Configure the USART peripheral. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) @@ -2244,7 +2241,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /** * @brief Check the USART Idle State. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) @@ -2430,7 +2427,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_TransmitReceive_IT(). - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h index c996457c127..30a6e59d246 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -308,14 +306,14 @@ typedef struct */ /** @brief Reset USART handle state. - * @param __HANDLE__: USART handle. + * @param __HANDLE__ USART handle. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Check whether the specified USART flag is set or not. - * @param __HANDLE__: specifies the USART Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: @if STM32F030x6 @elseif STM32F030x8 @@ -341,8 +339,8 @@ typedef struct #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified USART pending flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref USART_CLEAR_PEF * @arg @ref USART_CLEAR_FEF @@ -356,38 +354,38 @@ typedef struct #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the USART PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) /** @brief Clear the USART FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) /** @brief Clear the USART NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) /** @brief Clear the USART ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) /** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) /** @brief Enable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to enable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -397,13 +395,13 @@ typedef struct * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -413,14 +411,14 @@ typedef struct * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -435,8 +433,8 @@ typedef struct #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified USART interrupt source is enabled or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt * @arg @ref USART_IT_TC Transmission complete interrupt @@ -454,8 +452,8 @@ typedef struct /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag @@ -470,8 +468,8 @@ typedef struct #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific USART request flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __REQ__: specifies the request flag to set. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. * This parameter can be one of the following values: * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request @if STM32F030x6 @@ -488,25 +486,25 @@ typedef struct #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -521,7 +519,7 @@ typedef struct */ /** @brief Check USART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. + * @param __BAUDRATE__ Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval Test result (TRUE or FALSE). @@ -530,7 +528,7 @@ typedef struct /** * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__: USART frame number of stop bits. + * @param __STOPBITS__ USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #ifdef USART_SMARTCARD_SUPPORT @@ -545,7 +543,7 @@ typedef struct /** * @brief Ensure that USART frame parity is valid. - * @param __PARITY__: USART frame parity. + * @param __PARITY__ USART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ @@ -554,14 +552,14 @@ typedef struct /** * @brief Ensure that USART communication mode is valid. - * @param __MODE__: USART communication mode. + * @param __MODE__ USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that USART clock state is valid. - * @param __CLOCK__: USART clock state. + * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) */ #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ @@ -569,21 +567,21 @@ typedef struct /** * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__: USART frame polarity. + * @param __CPOL__ USART frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) /** * @brief Ensure that USART frame phase is valid. - * @param __CPHA__: USART frame phase. + * @param __CPHA__ USART frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) /** * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__: USART frame last bit clock pulse setting. + * @param __LASTBIT__ USART frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h index f21d16a29ea..942fe1ed4ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of USART HAL Extended module. ****************************************************************************** * @attention @@ -125,7 +123,7 @@ */ /** @brief Flush the USART Data registers. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) @@ -151,8 +149,8 @@ */ /** @brief Report the USART clock source. - * @param __HANDLE__: specifies the USART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) @@ -460,7 +458,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -535,7 +533,7 @@ /** * @brief Ensure that USART frame length is valid. - * @param __LENGTH__: USART frame length. + * @param __LENGTH__ USART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ @@ -553,7 +551,7 @@ /** * @brief Ensure that USART request parameter is valid. - * @param __PARAM__: USART request parameter. + * @param __PARAM__ USART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c index 167dc6e2d1e..ae48b997b8e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.c * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h index 3ceddb8fcf3..a164d853901 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.5.0 - * @date 04-November-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -176,7 +174,7 @@ typedef struct /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c index 298efd58dc1..7db18a6a213 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_adc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief ADC LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h index 29c9afd5fd6..2a7f5195875 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_adc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -87,8 +85,8 @@ extern "C" { ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */ @@ -100,18 +98,18 @@ extern "C" { /* GPIO pins) and internal channels (connected to internal paths) */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ /* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U) +#define ADC_CHANNEL_0_NUMBER (0x00000000U) #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0) #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 ) #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) @@ -161,7 +159,7 @@ extern "C" { /* selection of ADC group (ADC group regular). */ /* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) +#define ADC_AWD_CR1_REGOFFSET (0x00000000U) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) @@ -174,28 +172,28 @@ extern "C" { /* ADC registers bits positions */ -#define ADC_CFGR1_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */ -#define ADC_CFGR1_AWDSGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */ -#define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ -#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */ -#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */ -#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */ -#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */ -#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */ -#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */ -#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */ -#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */ -#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */ -#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */ -#define ADC_CHSELR_CHSEL10_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */ -#define ADC_CHSELR_CHSEL11_BITOFFSET_POS ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */ -#define ADC_CHSELR_CHSEL12_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */ -#define ADC_CHSELR_CHSEL13_BITOFFSET_POS ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */ -#define ADC_CHSELR_CHSEL14_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */ -#define ADC_CHSELR_CHSEL15_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */ -#define ADC_CHSELR_CHSEL16_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */ -#define ADC_CHSELR_CHSEL17_BITOFFSET_POS ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */ -#define ADC_CHSELR_CHSEL18_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */ +#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */ /* ADC registers bits groups */ @@ -204,14 +202,14 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ /** @@ -219,19 +217,6 @@ extern "C" { */ -#if defined(USE_FULL_LL_DRIVER) -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Macros ADC Private Macros - * @{ - */ - - -/** - * @} - */ - -#endif - /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure @@ -384,7 +369,7 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ /** * @} */ @@ -397,7 +382,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #if defined(ADC_CCR_VBATEN) @@ -412,7 +397,7 @@ typedef struct */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ -#define LL_ADC_CLOCK_ASYNC ((uint32_t)0x00000000U) /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */ +#define LL_ADC_CLOCK_ASYNC (0x00000000U) /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */ /** * @} */ @@ -420,7 +405,7 @@ typedef struct /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ @@ -431,7 +416,7 @@ typedef struct /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ -#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ /** * @} @@ -440,7 +425,7 @@ typedef struct /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. */ #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ @@ -451,7 +436,7 @@ typedef struct /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ -#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ /** * @} */ @@ -490,7 +475,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ -#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ @@ -513,7 +498,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} @@ -522,7 +507,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** @@ -532,7 +517,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} @@ -541,7 +526,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD ((uint32_t)0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ /** * @} @@ -550,7 +535,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} @@ -559,7 +544,7 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 28.5 ADC clock cycles */ @@ -582,7 +567,7 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ @@ -654,13 +639,13 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ @@ -669,7 +654,7 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2U) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} @@ -821,7 +806,7 @@ typedef struct * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1190,7 +1175,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) + (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) /** * @brief Helper macro to convert the ADC conversion data from @@ -1255,7 +1240,7 @@ typedef struct * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -2701,7 +2686,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) @@ -2712,7 +2697,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* data is not shifted. */ MODIFY_REG(ADCx->TR, AWDThresholdsHighLow, - AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U))); + AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U)); } /** @@ -2747,7 +2732,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /* both thresholds), data is not shifted. */ return (uint32_t)(READ_BIT(ADCx->TR, (AWDThresholdsHighLow | ADC_TR_LT)) - >> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U)) + >> ((~AWDThresholdsHighLow) & 0x00000010U) ); } @@ -2896,7 +2881,8 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular. + * without conversion stop command on going on group regular, + * without ADC disable command on going. * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h index fe6afd83901..405915981ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_bus.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of BUS LL module. @verbatim diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c index 2e153104d55..0a4f6f9cbc6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_comp.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief COMP LL module driver ****************************************************************************** * @attention @@ -295,7 +293,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /** * @brief Set each @ref LL_COMP_InitTypeDef field to default value. - * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure + * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h index fd0025a443d..ceb1a5d82cd 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_comp.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of COMP LL module. ****************************************************************************** * @attention @@ -716,7 +714,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) * to reach reach propagation delay specification. * Refer to device datasheet, parameter "tSTART". * @rmtoll CSR COMP1EN LL_COMP_Enable\n - * COMP2EN LL_COMP_Enable + * CSR COMP2EN LL_COMP_Enable * @param COMPx Comparator instance * @retval None */ @@ -728,7 +726,7 @@ __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx) /** * @brief Disable comparator instance. * @rmtoll CSR COMP1EN LL_COMP_Disable\n - * COMP2EN LL_COMP_Disable + * CSR COMP2EN LL_COMP_Disable * @param COMPx Comparator instance * @retval None */ @@ -741,7 +739,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @brief Get comparator enable state * (0: COMP is disabled, 1: COMP is enabled) * @rmtoll CSR COMP1EN LL_COMP_IsEnabled\n - * COMP2EN LL_COMP_IsEnabled + * CSR COMP2EN LL_COMP_IsEnabled * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ @@ -755,7 +753,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) * @note Once locked, comparator configuration can be accessed in read-only. * @note The only way to unlock the comparator is a device hardware reset. * @rmtoll CSR COMP1LOCK LL_COMP_Lock\n - * COMP2LOCK LL_COMP_Lock + * CSR COMP2LOCK LL_COMP_Lock * @param COMPx Comparator instance * @retval None */ @@ -770,7 +768,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @note Once locked, comparator configuration can be accessed in read-only. * @note The only way to unlock the comparator is a device hardware reset. * @rmtoll CSR COMP1LOCK LL_COMP_IsLocked\n - * COMP2LOCK LL_COMP_IsLocked + * CSR COMP2LOCK LL_COMP_IsLocked * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ @@ -794,7 +792,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * - Comparator output is low when the input plus * is at a higher voltage than the input minus * @rmtoll CSR COMP1OUT LL_COMP_ReadOutputLevel\n - * COMP2OUT LL_COMP_ReadOutputLevel + * CSR COMP2OUT LL_COMP_ReadOutputLevel * @param COMPx Comparator instance * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h index 2d7818c0341..4044db1d1e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_cortex.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of CORTEX LL module. @verbatim ============================================================================== @@ -83,8 +81,8 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c index 43eddd6a237..c634603c65d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief CRC LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h index f32740975f3..949201e135a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of CRC LL module. ****************************************************************************** * @attention @@ -71,7 +69,7 @@ extern "C" { /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length * @{ */ -#define LL_CRC_POLYLENGTH_32B (uint32_t)0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ #define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ #define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ #define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ @@ -83,7 +81,7 @@ extern "C" { /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse * @{ */ -#define LL_CRC_INDATA_REVERSE_NONE (uint32_t)0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ #define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ #define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ #define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ @@ -94,7 +92,7 @@ extern "C" { /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse * @{ */ -#define LL_CRC_OUTDATA_REVERSE_NONE (uint32_t)0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ #define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ /** * @} @@ -106,7 +104,7 @@ extern "C" { * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . * @{ */ -#define LL_CRC_DEFAULT_CRC32_POLY (uint32_t)0x04C11DB7U /*!< Default CRC generating polynomial value */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ /** * @} */ @@ -115,7 +113,7 @@ extern "C" { /** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value * @{ */ -#define LL_CRC_DEFAULT_CRC_INITVALUE (uint32_t)0xFFFFFFFFU /*!< Default CRC computation initialization value */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c index ed454370c33..845f94e4dde 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crs.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief CRS LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h index a5ee1bdc71b..4f154c142b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_crs.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of CRS LL module. ****************************************************************************** * @attention @@ -58,23 +56,7 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ -/** @defgroup CRS_LL_Private_Constants CRS Private Constants - * @{ - */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define CRS_POSITION_TRIM (uint32_t)8U /* bit position in CR reg */ -#define CRS_POSITION_FECAP (uint32_t)16U /* bit position in ISR reg */ -#define CRS_POSITION_RELOAD (uint32_t)0U /* bit position in CFGR reg */ -#define CRS_POSITION_FELIM (uint32_t)16U /* bit position in CFGR reg */ - - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ @@ -317,7 +299,7 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) */ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) { - MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); } /** @@ -327,7 +309,7 @@ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) */ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) { - return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM); + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); } /** @@ -362,7 +344,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) */ __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) { - MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); } /** @@ -372,7 +354,7 @@ __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) */ __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) { - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); } /** @@ -484,10 +466,10 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) */ __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) { - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, - ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings); + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); } /** @@ -528,7 +510,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) */ __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) { - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP); + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c index c3636ff3450..b4596d1c19d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dac.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief DAC LL module driver ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #include "stm32f0xx_ll_dac.h" #include "stm32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h index 67b02d20016..9e060fb71c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dac.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -70,8 +68,8 @@ extern "C" { /* - channel bits position into register SWTRIG */ /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ -#define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ @@ -82,43 +80,43 @@ extern "C" { #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U) -#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U) -#define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U) +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) -#define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */ +#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #else #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_REGOFFSET_MASK_POSBIT0 ((uint32_t)0x0000000FU) /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */ +#define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */ -#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS ((uint32_t)16U) /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS ((uint32_t)20U) /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS ((uint32_t)24U) /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS ((uint32_t)28U) /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ #endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -238,7 +236,7 @@ typedef struct #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ @@ -249,7 +247,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ /** @@ -259,7 +257,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits * @{ */ -#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ @@ -278,7 +276,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude * @{ */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ @@ -297,7 +295,7 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer * @{ */ -#define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ /** * @} @@ -307,8 +305,8 @@ typedef struct /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ -#define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */ -#define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */ +#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ /** * @} */ @@ -346,7 +344,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ @@ -359,7 +357,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ /** * @} */ @@ -479,7 +477,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U)) + ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) /** * @brief Helper macro to calculate the DAC conversion data (unit: digital diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c index 376e8240291..ac2a89c3a3b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dma.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief DMA LL module driver. ****************************************************************************** * @attention @@ -83,7 +81,7 @@ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ @@ -359,7 +357,7 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) /*--------------------------- DMAx CSELR Configuration ----------------------- - * Configure the peripheral base address with parameter : + * Configure the DMA request for DMA instance on Channel x with parameter : * - PeriphRequest: DMA_CSELR[31:0] bits */ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); @@ -376,15 +374,15 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) { /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = (uint32_t)0x00000000U; + DMA_InitStruct->NbData = 0x00000000U; #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h index 09a2851d5ed..9d9eb976a69 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_dma.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of DMA LL module. ****************************************************************************** * @attention @@ -280,19 +278,19 @@ typedef struct /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ #if defined(DMA1_Channel6) -#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ #endif #if defined(DMA1_Channel7) -#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #endif #if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} @@ -301,7 +299,7 @@ typedef struct /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction * @{ */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** @@ -311,7 +309,7 @@ typedef struct /** @defgroup DMA_LL_EC_MODE Transfer mode * @{ */ -#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ /** * @} @@ -321,7 +319,7 @@ typedef struct * @{ */ #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -330,7 +328,7 @@ typedef struct * @{ */ #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -338,7 +336,7 @@ typedef struct /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment * @{ */ -#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** @@ -348,7 +346,7 @@ typedef struct /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment * @{ */ -#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** @@ -358,7 +356,7 @@ typedef struct /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level * @{ */ -#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ @@ -370,22 +368,22 @@ typedef struct /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request * @{ */ -#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */ -#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */ -#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */ -#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */ -#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */ -#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */ -#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */ -#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */ -#define LL_DMA_REQUEST_8 ((uint32_t)0x00000008U) /*!< DMA peripheral request 8 */ -#define LL_DMA_REQUEST_9 ((uint32_t)0x00000009U) /*!< DMA peripheral request 9 */ -#define LL_DMA_REQUEST_10 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */ -#define LL_DMA_REQUEST_11 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */ -#define LL_DMA_REQUEST_12 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */ -#define LL_DMA_REQUEST_13 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */ -#define LL_DMA_REQUEST_14 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */ -#define LL_DMA_REQUEST_15 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ +#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ +#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ +#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ +#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ +#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ +#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ +#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ /** * @} */ @@ -1054,7 +1052,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe /** * @brief Configure the Source and Destination addresses. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr) + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance @@ -1080,24 +1079,21 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - SrcAddress); - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - SrcAddress); - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); } } /** * @brief Set the Memory address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetMemoryAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1113,13 +1109,13 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** * @brief Set the Peripheral address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetPeriphAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1135,8 +1131,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - PeriphAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); } /** @@ -1156,8 +1151,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, - DMA_CMAR_MA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } /** @@ -1177,13 +1171,13 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, - DMA_CPAR_PA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** * @brief Set the Memory to Memory Source address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1199,13 +1193,13 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); } /** * @brief Set the Memory to Memory Destination address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1221,8 +1215,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** @@ -1242,8 +1235,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, - DMA_CPAR_PA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** @@ -1263,8 +1255,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, - DMA_CMAR_MA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) @@ -1695,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } /** @@ -1706,7 +1697,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } /** @@ -1717,7 +1708,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } /** @@ -1728,7 +1719,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } /** @@ -1739,7 +1730,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } #if defined(DMA1_Channel6) @@ -1751,7 +1742,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } #endif @@ -1764,7 +1755,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } #endif @@ -1776,7 +1767,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } /** @@ -1787,7 +1778,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } /** @@ -1798,7 +1789,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } /** @@ -1809,7 +1800,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } /** @@ -1820,7 +1811,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } #if defined(DMA1_Channel6) @@ -1832,7 +1823,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } #endif @@ -1845,7 +1836,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } #endif @@ -1857,7 +1848,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } /** @@ -1868,7 +1859,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } /** @@ -1879,7 +1870,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } /** @@ -1890,7 +1881,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } /** @@ -1901,7 +1892,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } #if defined(DMA1_Channel6) @@ -1913,7 +1904,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } #endif @@ -1926,7 +1917,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } #endif @@ -1938,7 +1929,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } /** @@ -1949,7 +1940,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } /** @@ -1960,7 +1951,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } /** @@ -1971,7 +1962,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } /** @@ -1982,7 +1973,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } #if defined(DMA1_Channel6) @@ -1994,7 +1985,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } #endif @@ -2007,7 +1998,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c index 39cc36eaf0f..d9e42531efc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_exti.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief EXTI LL module driver. ****************************************************************************** * @attention @@ -115,7 +113,7 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR, 0x00000000U); /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register set to default reset values */ + /* Pending register clear */ LL_EXTI_WriteReg(PR, 0x007BFFFFU); return SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h index a80702ae601..647409c6737 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_exti.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_exti.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention @@ -122,7 +120,9 @@ typedef struct #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ #endif #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ #if defined(EXTI_IMR_IM20) #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ @@ -161,10 +161,10 @@ typedef struct #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ -#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ #if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ #endif /*USE_FULL_LL_DRIVER*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c index 6f2f937b666..3fae50cc9a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_gpio.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief GPIO LL module driver. ****************************************************************************** * @attention @@ -62,7 +60,7 @@ /** @addtogroup GPIO_LL_Private_Macros * @{ */ -#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ @@ -74,8 +72,7 @@ #define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) #define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ ((__VALUE__) == LL_GPIO_PULL_UP) ||\ @@ -166,7 +163,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -243,7 +240,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -280,4 +277,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h index 0930221fe3a..2782b069a92 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_gpio.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention @@ -152,7 +150,7 @@ typedef struct /** @defgroup GPIO_LL_EC_MODE Mode * @{ */ -#define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ @@ -163,7 +161,7 @@ typedef struct /** @defgroup GPIO_LL_EC_OUTPUT Output Type * @{ */ -#define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ /** * @} @@ -172,23 +170,20 @@ typedef struct /** @defgroup GPIO_LL_EC_SPEED Output Speed * @{ */ -#define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0_1 /*!< Select I/O fast output speed */ -#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ /** * @} */ #define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW #define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM -#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH -#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH - +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down * @{ */ -#define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ /** @@ -198,14 +193,14 @@ typedef struct /** @defgroup GPIO_LL_EC_AF Alternate Function * @{ */ -#define LL_GPIO_AF_0 ((uint32_t)0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 ((uint32_t)0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 ((uint32_t)0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 ((uint32_t)0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 ((uint32_t)0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 ((uint32_t)0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 ((uint32_t)0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 ((uint32_t)0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ /** * @} */ @@ -422,7 +417,6 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) @@ -459,7 +453,6 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) { @@ -559,7 +552,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0), + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), ((((Pin * Pin) * Pin) * Pin) * Alternate)); } @@ -589,7 +582,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], - ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0)) / (((Pin * Pin) * Pin) * Pin)); + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); } /** @@ -620,7 +613,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0), + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); } @@ -651,7 +644,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0)) / ((((Pin >> 8U) * + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c index 754d8e72c29..5d886404a09 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_i2c.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief I2C LL module driver. ****************************************************************************** * @attention @@ -73,7 +71,7 @@ #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) -#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU) +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ ((__VALUE__) == LL_I2C_NACK)) @@ -184,7 +182,12 @@ uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) */ LL_I2C_DisableOwnAddress1(I2Cx); LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); - LL_I2C_EnableOwnAddress1(I2Cx); + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (I2C_InitStruct->OwnAddress1 != 0U) + { + LL_I2C_EnableOwnAddress1(I2Cx); + } /*---------------------------- I2Cx MODE Configuration ----------------------- * Configure I2Cx peripheral mode with parameter : diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h index c1b5cb8aaed..fbe9e01fc16 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_i2c.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of I2C LL module. ****************************************************************************** * @attention @@ -63,16 +61,6 @@ extern "C" { /** @defgroup I2C_LL_Private_Constants I2C Private Constants * @{ */ -/* Defines used for the bit position in the register and perform offsets */ -#define I2C_POSITION_CR1_DNF (uint32_t)8U -#define I2C_POSITION_CR2_NBYTES (uint32_t)16U -#define I2C_POSITION_TIMINGR_PRESC (uint32_t)28U -#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)20U -#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)16U -#define I2C_POSITION_TIMINGR_SCLH (uint32_t)8U -#define I2C_POSITION_TIMINGR_SCLL (uint32_t)0U -#define I2C_POSITION_ISR_ADDCODE (uint32_t)17U -#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)16U /** * @} */ @@ -198,9 +186,9 @@ typedef struct /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} @@ -209,7 +197,7 @@ typedef struct /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection * @{ */ -#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ /** * @} @@ -218,7 +206,7 @@ typedef struct /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode * @{ */ -#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ /** * @} @@ -227,7 +215,7 @@ typedef struct /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length * @{ */ -#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ /** * @} @@ -251,7 +239,7 @@ typedef struct /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation * @{ */ -#define LL_I2C_ACK ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ /** * @} @@ -260,7 +248,7 @@ typedef struct /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length * @{ */ -#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ /** * @} @@ -269,7 +257,7 @@ typedef struct /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction * @{ */ -#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ /** * @} @@ -280,7 +268,7 @@ typedef struct */ #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /*!< Enable I2C Software end mode with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ @@ -293,7 +281,7 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ #define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ #define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ #define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ @@ -308,7 +296,7 @@ typedef struct /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /*!< Write transfer request by master, slave enters receiver mode. */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ /** * @} @@ -317,8 +305,8 @@ typedef struct /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /*!< Get address of data register used for transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /*!< Get address of data register used for reception */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -326,7 +314,7 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ /** * @} @@ -388,11 +376,11 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL)) + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -463,7 +451,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) { - MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF)); + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); } /** @@ -479,7 +467,7 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt */ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) { - MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF); + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); } /** @@ -490,7 +478,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital */ __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF); + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } /** @@ -922,7 +910,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) */ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } /** @@ -933,7 +921,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } /** @@ -944,7 +932,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } /** @@ -955,7 +943,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } /** @@ -966,7 +954,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } /** @@ -1114,7 +1102,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, - TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB)); + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); } /** @@ -1189,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) { - WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB); + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); } /** @@ -1202,7 +1190,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB); + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } /** @@ -1938,7 +1926,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES); + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); } /** @@ -1949,7 +1937,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer */ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES); + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } /** @@ -2122,7 +2110,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr { MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request); + SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } /** @@ -2148,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1); + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h index 21a111bd58a..7a2086e76d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_iwdg.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention @@ -64,10 +62,10 @@ extern "C" { * @{ */ -#define LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU) /*!< IWDG Reload Counter Enable */ -#define LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU) /*!< IWDG Peripheral Enable */ -#define LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U) /*!< IWDG KR Write Access Enable */ -#define LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U) /*!< IWDG KR Write Access Disable */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ /** * @} @@ -96,7 +94,7 @@ extern "C" { /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider * @{ */ -#define LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U) /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c index 14df679af9e..b4bf66509ac 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_pwr.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h index 64b314504ff..3a6449d8cb1 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_pwr.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of PWR LL module. ****************************************************************************** * @attention @@ -58,11 +56,8 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ - /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants @@ -85,30 +80,30 @@ extern "C" { */ #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#endif -#if defined (PWR_CSR_VREFINTRDYF) +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ -#endif +#endif /* PWR_CSR_VREFINTRDYF */ #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ -#if defined (PWR_CSR_EWUP3) +#if defined(PWR_CSR_EWUP3) #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ #endif /* PWR_CSR_EWUP3 */ -#if defined (PWR_CSR_EWUP4) +#if defined(PWR_CSR_EWUP4) #define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ #endif /* PWR_CSR_EWUP4 */ -#if defined (PWR_CSR_EWUP5) +#if defined(PWR_CSR_EWUP5) #define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ #endif /* PWR_CSR_EWUP5 */ -#if defined (PWR_CSR_EWUP6) +#if defined(PWR_CSR_EWUP6) #define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ #endif /* PWR_CSR_EWUP6 */ -#if defined (PWR_CSR_EWUP7) +#if defined(PWR_CSR_EWUP7) #define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ #endif /* PWR_CSR_EWUP7 */ -#if defined (PWR_CSR_EWUP8) +#if defined(PWR_CSR_EWUP8) #define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ #endif /* PWR_CSR_EWUP8 */ /** @@ -119,9 +114,9 @@ extern "C" { /** @defgroup PWR_LL_EC_MODE_PWR Mode Power * @{ */ -#define LL_PWR_MODE_STOP_MAINREGU ((uint32_t)0x00000000U) /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ /** * @} */ @@ -130,14 +125,14 @@ extern "C" { /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode * @{ */ -#define LL_PWR_REGU_DSMODE_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ /** - * @} - */ + * @} + */ #endif /* PWR_CR_LPDS */ -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level * @{ */ @@ -152,29 +147,28 @@ extern "C" { /** * @} */ -#endif - +#endif /* PWR_PVD_SUPPORT */ /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins -* @{ -*/ + * @{ + */ #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ -#if defined (PWR_CSR_EWUP3) +#if defined(PWR_CSR_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ #endif /* PWR_CSR_EWUP3 */ -#if defined (PWR_CSR_EWUP4) +#if defined(PWR_CSR_EWUP4) #define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ #endif /* PWR_CSR_EWUP4 */ -#if defined (PWR_CSR_EWUP5) +#if defined(PWR_CSR_EWUP5) #define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ #endif /* PWR_CSR_EWUP5 */ -#if defined (PWR_CSR_EWUP6) +#if defined(PWR_CSR_EWUP6) #define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ #endif /* PWR_CSR_EWUP6 */ -#if defined (PWR_CSR_EWUP7) +#if defined(PWR_CSR_EWUP7) #define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ #endif /* PWR_CSR_EWUP7 */ -#if defined (PWR_CSR_EWUP8) +#if defined(PWR_CSR_EWUP8) #define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ #endif /* PWR_CSR_EWUP8 */ /** @@ -217,7 +211,6 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions * @{ @@ -227,7 +220,6 @@ extern "C" { * @{ */ - /** * @brief Enable access to the backup domain * @rmtoll CR DBP LL_PWR_EnableBkUpAccess @@ -260,7 +252,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) #if defined(PWR_CR_LPDS) /** - * @brief Set voltage regulator mode during deep sleep mode + * @brief Set voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_SetRegulModeDS * @param RegulMode This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN @@ -273,7 +265,7 @@ __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) } /** - * @brief Get voltage regulator mode during deep sleep mode + * @brief Get voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_GetRegulModeDS * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN @@ -286,9 +278,9 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) #endif /* PWR_CR_LPDS */ /** - * @brief Set power down mode when CPU enters deepsleep + * @brief Set Power Down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * CR LPDS LL_PWR_SetPowerMode + * @rmtoll CR LPDS LL_PWR_SetPowerMode * @param PDMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU @@ -301,9 +293,9 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) } /** - * @brief Get power down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode - * CR LPDS LL_PWR_SetPowerMode + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU @@ -314,7 +306,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); } -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector * @rmtoll CR PLS LL_PWR_SetPVDLevel @@ -381,13 +373,18 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); } -#endif +#endif /* PWR_PVD_SUPPORT */ /** * @brief Enable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n - * CSR EWUP2 LL_PWR_EnableWakeUpPin\n - * CSR EWUP3 LL_PWR_EnableWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -409,8 +406,13 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) /** * @brief Disable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n - * CSR EWUP2 LL_PWR_DisableWakeUpPin\n - * CSR EWUP3 LL_PWR_DisableWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -432,8 +434,13 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) /** * @brief Check if the WakeUp PINx functionality is enabled * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -452,6 +459,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); } + /** * @} */ @@ -480,7 +488,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); } -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** * @brief Indicate whether VDD voltage is below the selected PVD threshold * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO @@ -490,9 +498,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); } -#endif +#endif /* PWR_PVD_SUPPORT */ -#if defined (PWR_CSR_VREFINTRDYF) +#if defined(PWR_CSR_VREFINTRDYF) /** * @brief Get Internal Reference VrefInt Flag * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY @@ -502,10 +510,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) { return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); } -#endif - - - +#endif /* PWR_CSR_VREFINTRDYF */ /** * @brief Clear Standby Flag * @rmtoll CR CSBF LL_PWR_ClearFlag_SB @@ -526,6 +531,9 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) SET_BIT(PWR->CR, PWR_CR_CWUF); } +/** + * @} + */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function @@ -545,10 +553,6 @@ ErrorStatus LL_PWR_DeInit(void); * @} */ -/** - * @} - */ - #endif /* defined(PWR) */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c index 83058763f39..6a244fdd502 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rcc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -148,7 +146,7 @@ ErrorStatus LL_RCC_DeInit(void) /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); - + /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); @@ -499,6 +497,12 @@ uint32_t RCC_GetSystemClockFreq(void) frequency = RCC_PLL_GetFreqDomain_SYS(); break; +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ + frequency = HSI48_VALUE; + break; +#endif /* RCC_HSI48_SUPPORT */ + default: frequency = HSI_VALUE; break; @@ -548,15 +552,15 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) pllinputfreq = HSI_VALUE; #else case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE / 2; + pllinputfreq = HSI_VALUE / 2U; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; -#if defined(RCC_CFGR_SW_HSI48) +#if defined(RCC_HSI48_SUPPORT) case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ pllinputfreq = HSI48_VALUE; break; -#endif /* RCC_CFGR_SW_HSI48 */ +#endif /* RCC_HSI48_SUPPORT */ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; @@ -566,7 +570,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) pllinputfreq = HSI_VALUE; #else - pllinputfreq = HSI_VALUE / 2; + pllinputfreq = HSI_VALUE / 2U; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; } diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h index 974329afb5f..50bba6b2b6d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rcc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -58,14 +56,6 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_LL_Private_Constants RCC Private Constants * @{ @@ -139,24 +129,24 @@ typedef struct * @{ */ #if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */ +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ #endif /* HSI_VALUE */ #if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ #if defined(RCC_HSI48_SUPPORT) #if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */ +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ #endif /* RCC_HSI48_SUPPORT */ /** @@ -333,8 +323,8 @@ typedef struct /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency * @{ */ -#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ /** * @} */ @@ -445,7 +435,7 @@ typedef struct /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ -#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ @@ -571,7 +561,7 @@ typedef struct * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() * , @ref LL_RCC_PLL_GetPrediv()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) - * @param __PLLMUL__: This parameter can be one of the following values: + * @param __PLLMUL__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 @@ -587,7 +577,7 @@ typedef struct * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 - * @param __PLLPREDIV__: This parameter can be one of the following values: + * @param __PLLPREDIV__ This parameter can be one of the following values: * @arg @ref LL_RCC_PREDIV_DIV_1 * @arg @ref LL_RCC_PREDIV_DIV_2 * @arg @ref LL_RCC_PREDIV_DIV_3 @@ -614,7 +604,7 @@ typedef struct * @brief Helper macro to calculate the PLLCLK frequency * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) - * @param __PLLMUL__: This parameter can be one of the following values: + * @param __PLLMUL__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 @@ -640,7 +630,7 @@ typedef struct * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__: This parameter can be one of the following values: + * @param __AHBPRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 @@ -652,14 +642,14 @@ typedef struct * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval HCLK clock frequency (in Hz) */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) /** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__: This parameter can be one of the following values: + * @param __APB1PRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 @@ -667,7 +657,7 @@ typedef struct * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) /** * @} @@ -804,7 +794,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) { - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL); + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); } /** @@ -818,7 +808,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM); + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); } /** @@ -828,7 +818,7 @@ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) { - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM); + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c index e3feddb32de..6c1ba8e075f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rtc.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief RTC LL module driver. ****************************************************************************** * @attention @@ -62,12 +60,12 @@ * @{ */ /* Default values used for prescaler */ -#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU) -#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU) +#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU +#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU /* Values used for timeout */ -#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ -#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */ /** * @} */ @@ -80,9 +78,9 @@ #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) -#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU) +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) -#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU) +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ || ((__VALUE__) == LL_RTC_FORMAT_BCD)) @@ -103,7 +101,7 @@ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) -#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U)) +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ @@ -369,7 +367,7 @@ void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) * @param RTC_Format This parameter can be one of the following values: * @arg @ref LL_RTC_FORMAT_BIN * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Day register is configured diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h index 710e92af16f..b7cfbe6f497 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_rtc.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -63,49 +61,20 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) -/* Defines used for the bit position in the register and perform offsets */ -#define RTC_POSITION_TR_HT (uint32_t)20U -#define RTC_POSITION_TR_HU (uint32_t)16U -#define RTC_POSITION_TR_MT (uint32_t)12U -#define RTC_POSITION_TR_MU (uint32_t)8U -#define RTC_POSITION_TR_ST (uint32_t)4U -#define RTC_POSITION_TR_SU (uint32_t)0U -#define RTC_POSITION_DR_YT (uint32_t)20U -#define RTC_POSITION_DR_YU (uint32_t)16U -#define RTC_POSITION_DR_MT (uint32_t)12U -#define RTC_POSITION_DR_MU (uint32_t)8U -#define RTC_POSITION_DR_DT (uint32_t)4U -#define RTC_POSITION_DR_DU (uint32_t)0U -#define RTC_POSITION_DR_WDU (uint32_t)13U -#define RTC_POSITION_ALMA_DT (uint32_t)28U -#define RTC_POSITION_ALMA_DU (uint32_t)24U -#define RTC_POSITION_ALMA_HT (uint32_t)20U -#define RTC_POSITION_ALMA_HU (uint32_t)16U -#define RTC_POSITION_ALMA_MT (uint32_t)12U -#define RTC_POSITION_ALMA_MU (uint32_t)8U -#define RTC_POSITION_ALMA_SU (uint32_t)0U -#define RTC_POSITION_ALMA_ST (uint32_t)4U -#define RTC_POSITION_PRER_PREDIV_A (uint32_t)16U -#define RTC_POSITION_ALMA_MASKSS (uint32_t)24U -#define RTC_POSITION_TS_HU (uint32_t)16U -#define RTC_POSITION_TS_MNU (uint32_t)8U -#define RTC_POSITION_TS_WDU (uint32_t)13U -#define RTC_POSITION_TS_MU (uint32_t)8U - /* Defines used to combine date & time */ -#define RTC_OFFSET_WEEKDAY (uint32_t)24U -#define RTC_OFFSET_DAY (uint32_t)16U -#define RTC_OFFSET_MONTH (uint32_t)8U -#define RTC_OFFSET_HOUR (uint32_t)16U -#define RTC_OFFSET_MINUTE (uint32_t)8U +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U /** * @} @@ -248,8 +217,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U) /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U) /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ /** * @} */ @@ -257,7 +226,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay * @{ */ -#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ /** * @} @@ -335,7 +304,7 @@ typedef struct /** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT * @{ */ -#define LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ #define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ /** * @} @@ -344,7 +313,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT * @{ */ -#define LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U) /*!< Output disabled */ +#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ #define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ #define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ #define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ @@ -355,7 +324,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ /** * @} @@ -374,7 +343,7 @@ typedef struct /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN * @{ */ -#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ #define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ /** * @} @@ -383,7 +352,7 @@ typedef struct /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT * @{ */ -#define LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ #define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ /** * @} @@ -392,7 +361,7 @@ typedef struct /** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND * @{ */ -#define LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ #define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ /** * @} @@ -401,7 +370,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK * @{ */ -#define LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ #define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ #define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ #define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ @@ -414,7 +383,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT * @{ */ -#define LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ #define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ /** * @} @@ -423,7 +392,7 @@ typedef struct /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE * @{ */ -#define LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ #define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ /** * @} @@ -432,7 +401,7 @@ typedef struct /** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT * @{ */ -#define LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ #define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ /** * @} @@ -490,7 +459,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ -#define LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ @@ -503,7 +472,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ -#define LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ #define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ #define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ #define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ @@ -516,7 +485,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ @@ -548,7 +517,7 @@ typedef struct /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV * @{ */ -#define LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U) /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ @@ -562,11 +531,11 @@ typedef struct /** @defgroup RTC_LL_EC_BKP BACKUP * @{ */ -#define LL_RTC_BKP_DR0 ((uint32_t)0x00000000U) -#define LL_RTC_BKP_DR1 ((uint32_t)0x00000001U) -#define LL_RTC_BKP_DR2 ((uint32_t)0x00000002U) -#define LL_RTC_BKP_DR3 ((uint32_t)0x00000003U) -#define LL_RTC_BKP_DR4 ((uint32_t)0x00000004U) +#define LL_RTC_BKP_DR0 0x00000000U +#define LL_RTC_BKP_DR1 0x00000001U +#define LL_RTC_BKP_DR2 0x00000002U +#define LL_RTC_BKP_DR3 0x00000003U +#define LL_RTC_BKP_DR4 0x00000004U /** * @} */ @@ -575,9 +544,9 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output * @{ */ -#define LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ /** * @} */ @@ -585,7 +554,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion * @{ */ -#define LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ #define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ /** * @} @@ -594,7 +563,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period * @{ */ -#define LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ #define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ #define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ /** @@ -1041,7 +1010,7 @@ __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) { - MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A); + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); } /** @@ -1064,7 +1033,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP */ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A); + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } /** @@ -1156,7 +1125,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) { MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), - (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU))); + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); } /** @@ -1177,7 +1146,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); - return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU)); + return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); } /** @@ -1194,7 +1163,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) { MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), - (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU))); + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); } /** @@ -1215,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); - return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU)); + return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); } /** @@ -1232,7 +1201,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) { MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), - (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU))); + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); } /** @@ -1253,7 +1222,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU)); + return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); } /** @@ -1282,9 +1251,9 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, register uint32_t temp = 0U; temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) | \ - (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \ - (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)); + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); } @@ -1307,42 +1276,47 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); } /** * @brief Memorize whether the daylight saving time change has been performed * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BCK LL_RTC_TIME_EnableDayLightStore + * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->CR, RTC_CR_BCK); + SET_BIT(RTCx->CR, RTC_CR_BKP); } /** * @brief Disable memorization whether the daylight saving time change has been performed. * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BCK LL_RTC_TIME_DisableDayLightStore + * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) { - CLEAR_BIT(RTCx->CR, RTC_CR_BCK); + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); } /** * @brief Check if RTC Day Light Saving stored operation has been enabled or not - * @rmtoll CR BCK LL_RTC_TIME_IsDayLightStoreEnabled + * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK)); + return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)); } /** @@ -1426,7 +1400,7 @@ __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSe __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) { MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), - (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU))); + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); } /** @@ -1444,7 +1418,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU)); + return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); } /** @@ -1463,7 +1437,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) { - MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU); + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); } /** @@ -1483,7 +1457,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU); + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } /** @@ -1510,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) { MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), - (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU))); + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); } /** @@ -1540,7 +1514,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); - return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU)); + return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); } /** @@ -1555,7 +1529,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) { MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), - (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU))); + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); } /** @@ -1573,7 +1547,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); - return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU)); + return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); } /** @@ -1615,10 +1589,10 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin { register uint32_t temp = 0U; - temp = (WeekDay << RTC_POSITION_DR_WDU) | \ - (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) | \ - (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \ - (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)); + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); } @@ -1641,7 +1615,13 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); } /** @@ -1751,7 +1731,7 @@ __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), - (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU))); + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); } /** @@ -1767,7 +1747,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); - return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU)); + return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); } /** @@ -1786,7 +1766,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) { - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU); + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); } /** @@ -1804,7 +1784,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU); + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } /** @@ -1846,7 +1826,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), - (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU))); + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); } /** @@ -1862,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); - return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU)); + return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); } /** @@ -1877,7 +1857,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), - (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU))); + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); } /** @@ -1893,7 +1873,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); - return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU)); + return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); } /** @@ -1908,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) { MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), - (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU))); + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); } /** @@ -1924,7 +1904,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) register uint32_t temp = 0U; temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU)); + return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); } /** @@ -1949,9 +1929,9 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 { register uint32_t temp = 0U; - temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)) | \ - (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \ - (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)); + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); } @@ -1985,7 +1965,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) { - MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS); + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); } /** @@ -1996,7 +1976,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS); + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } /** @@ -2107,7 +2087,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU); + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } /** @@ -2120,7 +2100,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU); + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } /** @@ -2170,7 +2150,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU); + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } /** @@ -2195,7 +2175,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU); + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c index 07cd385fdd1..30054902858 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_spi.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief SPI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h index 6a8581e1f2a..d3a638158fb 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_spi.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of SPI LL module. ****************************************************************************** * @attention @@ -141,7 +139,6 @@ typedef struct #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ -#define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */ #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ @@ -165,7 +162,7 @@ typedef struct * @{ */ #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ -#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ /** * @} */ @@ -173,7 +170,7 @@ typedef struct /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol * @{ */ -#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ /** * @} @@ -182,7 +179,7 @@ typedef struct /** @defgroup SPI_LL_EC_PHASE Clock Phase * @{ */ -#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ /** * @} @@ -191,7 +188,7 @@ typedef struct /** @defgroup SPI_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ /** * @} @@ -200,7 +197,7 @@ typedef struct /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler * @{ */ -#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ @@ -216,7 +213,7 @@ typedef struct * @{ */ #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ -#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ /** * @} */ @@ -224,7 +221,7 @@ typedef struct /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode * @{ */ -#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ @@ -236,7 +233,7 @@ typedef struct * @{ */ #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ -#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ /** * @} @@ -266,7 +263,7 @@ typedef struct /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation * @{ */ -#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ /** * @} @@ -276,7 +273,7 @@ typedef struct /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length * @{ */ -#define LL_SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< 8-bit CRC length */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ /** * @} @@ -285,7 +282,7 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ /** * @} @@ -294,7 +291,7 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level * @{ */ -#define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ @@ -305,7 +302,7 @@ typedef struct /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level * @{ */ -#define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ @@ -316,8 +313,8 @@ typedef struct /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity * @{ */ -#define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Select DMA parity Even */ -#define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U) /*!< Select DMA parity Odd */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ /** * @} @@ -1283,7 +1280,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) { - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << 13U)); + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); } /** @@ -1296,7 +1293,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) */ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) { - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> 13U); + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } /** @@ -1310,7 +1307,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) { - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << 14U)); + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); } /** @@ -1323,7 +1320,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) */ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) { - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> 14U); + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } /** @@ -1490,7 +1487,7 @@ typedef struct #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ -#define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ /** @@ -1511,7 +1508,7 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ @@ -1522,7 +1519,7 @@ typedef struct /** @defgroup I2S_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ /** * @} @@ -1531,7 +1528,7 @@ typedef struct /** @defgroup I2S_LL_EC_STANDARD I2s Standard * @{ */ -#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /*!< I2S standard philips */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ @@ -1543,7 +1540,7 @@ typedef struct /** @defgroup I2S_LL_EC_MODE Operation Mode * @{ */ -#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ @@ -1554,7 +1551,7 @@ typedef struct /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor * @{ */ -#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ /** * @} @@ -1565,7 +1562,7 @@ typedef struct /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output * @{ */ -#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ /** * @} @@ -1575,16 +1572,16 @@ typedef struct * @{ */ -#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configuration 192000 Hz */ -#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configuration 96000 Hz */ -#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configuration 48000 Hz */ -#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configuration 44100 Hz */ -#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configuration 32000 Hz */ -#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configuration 22050 Hz */ -#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configuration 16000 Hz */ -#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configuration 11025 Hz */ -#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configuration 8000 Hz */ -#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. Register I2SDIV = 2 */ +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h index 870497991c0..65af161464e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_system.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -76,9 +74,6 @@ extern "C" { * @{ */ -/* Defines used for position in the register */ -#define DBGMCU_REVID_POSITION (uint32_t)16U - /** * @} */ @@ -337,7 +332,7 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY * @{ */ -#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ /** * @} @@ -1635,7 +1630,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c index 3393d5ec4b6..fa745e11902 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_tim.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief TIM LL module driver. ****************************************************************************** * @attention @@ -127,6 +125,26 @@ #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ @@ -265,7 +283,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /* Set the default configuration */ TIM_InitStruct->Prescaler = (uint16_t)0x0000U; TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; - TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; } @@ -335,7 +353,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U; + TIM_OC_InitStruct->CompareValue = 0x00000000U; TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; @@ -528,7 +546,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U; + TIM_HallSensorInitStruct->CommutationDelay = 0U; } /** @@ -623,6 +641,68 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType return SUCCESS; } +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked + * depending on the LOCK configuration, it can be necessary to configure all of + * them during the first write access to the TIMx_BDTR register. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h index 7c4974ecbf7..85ebdf1b6a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_tim.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of TIM LL module. ****************************************************************************** * @attention @@ -126,9 +124,9 @@ static const uint8_t SHIFT_TAB_OISx[] = */ -#define TIMx_OR_RMP_SHIFT ((uint32_t)16U) -#define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU) -#define TIM14_OR_RMP_MASK ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)) +#define TIMx_OR_RMP_SHIFT 16U +#define TIMx_OR_RMP_MASK 0x0000FFFFU +#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ #define DT_DELAY_1 ((uint8_t)0x7FU) @@ -147,7 +145,6 @@ static const uint8_t SHIFT_TAB_OISx[] = * @} */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Macros TIM Private Macros * @{ @@ -209,7 +206,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ - uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. @@ -267,6 +264,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. @@ -390,6 +388,61 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +} LL_TIM_BDTR_InitTypeDef; + /** * @} */ @@ -420,6 +473,26 @@ typedef struct * @} */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + /** @defgroup TIM_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. * @{ @@ -439,8 +512,8 @@ typedef struct /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source * @{ */ -#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ -#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ /** * @} */ @@ -448,8 +521,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ /** * @} */ @@ -457,11 +530,11 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!TIMx_CCRy else active.*/ #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ @@ -557,7 +630,7 @@ typedef struct /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity * @{ */ -#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ /** * @} @@ -566,7 +639,7 @@ typedef struct /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State * @{ */ -#define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U) /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) /** @@ -1005,7 +1077,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) { - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** @@ -1016,18 +1088,18 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance - * @retval State of bit (1 or 0). + * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); } /** @@ -2709,7 +2781,13 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) { + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); } /** @@ -2722,7 +2800,13 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) { + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); } /** @@ -2738,7 +2822,13 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) { + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); + + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); } /** @@ -2932,15 +3022,14 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) * @} */ -#if defined(TIM_SMCR_OCCS) /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management * @{ */ /** - * @brief Set the OCREF clear source + * @brief Set the OCREF clear input source * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT * @note This function can only be used in Output compare and PWM modes. - * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource * @param TIMx Timer instance * @param OCRefClearInputSource This parameter can be one of the following values: * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR @@ -2955,7 +3044,6 @@ __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t * @} */ -#endif /* TIM_SMCR_OCCS */ /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management * @{ */ @@ -3847,6 +3935,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ @@ -3871,5 +3961,4 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType #endif #endif /* __STM32F0xx_LL_TIM_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c index d6de97daae4..d671b293b29 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_usart.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief USART LL module driver. ****************************************************************************** * @attention @@ -77,6 +75,12 @@ * divided by the smallest oversampling used on the USART (i.e. 8) */ #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U) +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -247,7 +251,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance - * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * that contains the configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are initialized according to USART_InitStruct content @@ -275,7 +279,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR1 Configuration ----------------------- + /*---------------------------- USART CR1 Configuration --------------------- * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value @@ -288,20 +292,20 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini (USART_InitStruct->DataWidth | USART_InitStruct->Parity | USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); - /*---------------------------- USART CR2 Configuration ----------------------- + /*---------------------------- USART CR2 Configuration --------------------- * Configure USARTx CR2 (Stop bits) with parameters: * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). */ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); - /*---------------------------- USART CR3 Configuration ----------------------- + /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); - /*---------------------------- USART BRR Configuration ----------------------- + /*---------------------------- USART BRR Configuration --------------------- * Retrieve Clock frequency used for USART Peripheral */ if (USARTx == USART1) @@ -389,6 +393,12 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini periphclk, USART_InitStruct->OverSampling, USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -398,7 +408,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /** * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -421,7 +431,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content @@ -482,7 +492,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef /** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h index b3f2911d12f..e8f00fb8de7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_usart.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of USART LL module. ****************************************************************************** * @attention @@ -63,16 +61,6 @@ extern "C" { /** @defgroup USART_LL_Private_Constants USART Private Constants * @{ */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define USART_POSITION_CR1_DEDT (uint32_t)16 -#define USART_POSITION_CR1_DEAT (uint32_t)21 -#define USART_POSITION_CR2_ADD (uint32_t)24 -#if defined(USART_SMARTCARD_SUPPORT) -#define USART_POSITION_CR3_SCARCNT (uint32_t)17 -#define USART_POSITION_RTOR_BLEN (uint32_t)24 -#define USART_POSITION_GTPR_GT (uint32_t)8 -#endif /** * @} */ @@ -268,7 +256,7 @@ typedef struct /** @defgroup USART_LL_EC_DIRECTION Communication Direction * @{ */ -#define LL_USART_DIRECTION_NONE (uint32_t)0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ @@ -279,7 +267,7 @@ typedef struct /** @defgroup USART_LL_EC_PARITY Parity Control * @{ */ -#define LL_USART_PARITY_NONE (uint32_t)0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** @@ -289,7 +277,7 @@ typedef struct /** @defgroup USART_LL_EC_WAKEUP Wakeup * @{ */ -#define LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ /** * @} @@ -300,10 +288,10 @@ typedef struct */ #if defined(USART_7BITS_SUPPORT) #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ #else -#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ #define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ #endif /** @@ -313,7 +301,7 @@ typedef struct /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling * @{ */ -#define LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} @@ -324,7 +312,7 @@ typedef struct * @{ */ -#define LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ /** * @} @@ -334,7 +322,7 @@ typedef struct /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse * @{ */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ /** * @} @@ -343,7 +331,7 @@ typedef struct /** @defgroup USART_LL_EC_PHASE Clock Phase * @{ */ -#define LL_USART_PHASE_1EDGE (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ /** * @} @@ -352,7 +340,7 @@ typedef struct /** @defgroup USART_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_USART_POLARITY_LOW (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ /** * @} @@ -364,7 +352,7 @@ typedef struct #if defined(USART_SMARTCARD_SUPPORT) #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ #endif -#define LL_USART_STOPBITS_1 (uint32_t)0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ #if defined(USART_SMARTCARD_SUPPORT) #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ #endif @@ -376,7 +364,7 @@ typedef struct /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap * @{ */ -#define LL_USART_TXRX_STANDARD (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} @@ -385,7 +373,7 @@ typedef struct /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ -#define LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} @@ -394,7 +382,7 @@ typedef struct /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ -#define LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} @@ -403,7 +391,7 @@ typedef struct /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ -#define LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ /** * @} @@ -412,7 +400,7 @@ typedef struct /** @defgroup USART_LL_EC_BITORDER Bit Order * @{ */ -#define LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ /** * @} @@ -421,7 +409,7 @@ typedef struct /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection * @{ */ -#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ #if defined(USART_FABR_SUPPORT) #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ @@ -434,7 +422,7 @@ typedef struct /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ -#define LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} @@ -443,7 +431,7 @@ typedef struct /** @defgroup USART_LL_EC_HWCONTROL Hardware Control * @{ */ -#define LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ @@ -455,7 +443,7 @@ typedef struct /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ -#define LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** @@ -467,7 +455,7 @@ typedef struct /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power * @{ */ -#define LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ /** * @} @@ -478,7 +466,7 @@ typedef struct /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length * @{ */ -#define LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ /** * @} @@ -488,7 +476,7 @@ typedef struct /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ -#define LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} @@ -497,8 +485,8 @@ typedef struct /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /*!< Get address of data register used for transmission */ -#define LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U /*!< Get address of data register used for reception */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -1400,7 +1388,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) { MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD))); + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); } /** @@ -1415,7 +1403,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD); + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } /** @@ -1627,6 +1615,7 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values * @note Peripheral clock and Baud rate values provided as function parameters should be valid * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. * @rmtoll BRR BRR LL_USART_SetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock @@ -1659,6 +1648,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @brief Return current Baud Rate value, according to USARTDIV present in BRR register * (full BRR content), and to used Peripheral Clock and Oversampling mode values * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. * @rmtoll BRR BRR LL_USART_GetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock @@ -1725,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) { - MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_POSITION_RTOR_BLEN); + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); } /** @@ -1736,7 +1726,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo */ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_POSITION_RTOR_BLEN); + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } #endif @@ -1952,7 +1942,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) { - MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_POSITION_CR3_SCARCNT); + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); } /** @@ -1965,7 +1955,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, */ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_POSITION_CR3_SCARCNT); + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } /** @@ -2009,7 +1999,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); } /** @@ -2023,7 +2013,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 */ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } /** @@ -2173,7 +2163,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) { - MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_POSITION_CR1_DEDT); + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); } /** @@ -2186,7 +2176,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 */ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_POSITION_CR1_DEDT); + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } /** @@ -2200,7 +2190,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) { - MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_POSITION_CR1_DEAT); + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); } /** @@ -2213,7 +2203,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_POSITION_CR1_DEAT); + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c index 49942c5f02b..836204a08c2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_utils.c * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief UTILS LL module driver. ****************************************************************************** * @attention @@ -60,15 +58,15 @@ */ /* Defines used for PLL range */ -#define UTILS_PLL_OUTPUT_MIN ((uint32_t)16000000U) /*!< Frequency min for PLL output, in Hz */ -#define UTILS_PLL_OUTPUT_MAX ((uint32_t)48000000U) /*!< Frequency max for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ +#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ /* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000U) /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX ((uint32_t)32000000U) /*!< Frequency max for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to SYSCLK Frequency */ -#define UTILS_LATENCY1_FREQ ((uint32_t)24000000U) /*!< SYSCLK frequency to set FLASH latency 1 */ +#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ /** * @} */ @@ -133,7 +131,9 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +#if defined(FLASH_ACR_LATENCY) static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -268,7 +268,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS /* Force PREDIV value to 2 */ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - /* Calculate the new PLL output frequency */ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); @@ -426,7 +425,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); #else - LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ /* Enable PLL and switch system clock to PLL */ @@ -460,6 +459,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa * - SUCCESS: Latency has been modified * - ERROR: Latency cannot be modified */ +#if defined(FLASH_ACR_LATENCY) static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) { ErrorStatus status = SUCCESS; @@ -491,6 +491,7 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) } return status; } +#endif /* FLASH_ACR_LATENCY */ /** * @brief Function to check that PLL can be modified @@ -536,7 +537,6 @@ static ErrorStatus UTILS_PLL_IsBusy(void) status = ERROR; } - return status; } @@ -558,7 +558,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); /* Calculate current SYSCLK frequency */ - sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]); + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); /* Increasing the number of wait states because of higher CPU frequency */ if (sysclk_frequency_current < SYSCLK_Frequency) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h index 0eeaeda6fd4..ca5ed3eba65 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_utils.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of UTILS LL module. @verbatim ============================================================================== @@ -75,7 +73,7 @@ extern "C" { */ /* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY (uint32_t)0xFFFFFFFFU +#define LL_MAX_DELAY 0xFFFFFFFFU /** * @brief Unique device ID register base address @@ -158,8 +156,8 @@ typedef struct /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation * @{ */ -#define LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U /*!< HSE Bypass is enabled */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ /** * @} */ @@ -217,6 +215,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h index 5fb27831ee9..3a6d707e707 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f0xx_ll_wwdg.h * @author MCD Application Team - * @version V1.4.0 - * @date 27-May-2016 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention @@ -82,7 +80,7 @@ extern "C" { /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER * @{ */ -#define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c b/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c index 688f9fe1d1f..9f773160907 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from diff --git a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c new file mode 100644 index 00000000000..9a2d7c4c8ef --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c @@ -0,0 +1,175 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "mbed_assert.h" +#include "cmsis.h" + +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#endif + +// Minimum number of bytes to be programmed at a time +#define MIN_PROG_SIZE (4U) + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Flash */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t PAGEError = 0; + FLASH_EraseInitTypeDef EraseInitStruct; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + // Clear Flash status register's flags + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* MBED HAL erases 1 sector at a time */ + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.PageAddress = address; + EraseInitStruct.NbPages = 1; + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + uint32_t StartAddress = 0; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if ((size % MIN_PROG_SIZE) != 0) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Program the user Flash area word by word */ + StartAddress = address; + + /* HW needs an aligned address to program flash, which data parameter doesn't ensure */ + if ((uint32_t) data % 4 != 0) { + + volatile uint32_t data32; + while (address < (StartAddress + size) && (status == 0)) { + for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) { + *(((uint8_t *) &data32) + i) = *(data + i); + } + + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } else { /* case where data is aligned, so let's avoid any copy */ + while ((address < (StartAddress + size)) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } + + flash_lock(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return MBED_FLASH_INVALID_SIZE; + } else { + return FLASH_PAGE_SIZE; + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return MIN_PROG_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 36023d28e75..2ea47faeb3d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,234 +27,26 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#if defined (TARGET_STM32F091RC) - #define UART_NUM (8) +#if defined (TARGET_STM32F031K6) + #define UART_NUM (1) #elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6) #define UART_NUM (2) -#elif defined (TARGET_STM32F031K6) - #define UART_NUM (1) -#else +#elif defined (TARGET_STM32F070RB) || defined (TARGET_STM32F072RB) #define UART_NUM (4) +#else + #define UART_NUM (8) // max value (TARGET_STM32F091RC) #endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - -#if defined USART2_BASE - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } -#endif - -#if defined USART3_BASE - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } -#endif - -#if defined USART4_BASE - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif - -#if defined USART5_BASE - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - -#if defined USART6_BASE - if (obj_s->uart == UART_6) { - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - } -#endif - -#if defined USART7_BASE - if (obj_s->uart == UART_7) { - __HAL_RCC_USART7_FORCE_RESET(); - __HAL_RCC_USART7_RELEASE_RESET(); - __HAL_RCC_USART7_CLK_ENABLE(); - obj_s->index = 6; - } -#endif - -#if defined USART8_BASE - if (obj_s->uart == UART_8) { - __HAL_RCC_USART8_FORCE_RESET(); - __HAL_RCC_USART8_RELEASE_RESET(); - __HAL_RCC_USART8_CLK_ENABLE(); - obj_s->index = 7; - } -#endif - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } - -#if defined(USART2_BASE) - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } -#endif - -#if defined USART3_BASE - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - } -#endif - -#if defined USART4_BASE - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_DISABLE(); - } -#endif - -#if defined USART5_BASE - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_DISABLE(); - } -#endif - -#if defined USART6_BASE - if (obj_s->uart == UART_6) { - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_DISABLE(); - } -#endif - -#if defined USART7_BASE - if (obj_s->uart == UART_7) { - __HAL_RCC_USART7_FORCE_RESET(); - __HAL_RCC_USART7_RELEASE_RESET(); - __HAL_RCC_USART7_CLK_DISABLE(); - } -#endif - -#if defined USART8_BASE - if (obj_s->uart == UART_8) { - __HAL_RCC_USART8_FORCE_RESET(); - __HAL_RCC_USART8_RELEASE_RESET(); - __HAL_RCC_USART8_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -884,7 +676,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -943,6 +735,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h index d886153259e..2b92feedda4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h index a5849893dab..cd2e2e9416d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h @@ -132,15 +132,27 @@ typedef enum { C14 = PC_14, C15 = PC_15, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PC_13, LED2 = PC_13, LED3 = PC_13, LED4 = PC_13, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h index 28dba655c0d..803ce057313 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h index a8a684f69c6..fa65262c88f 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h @@ -143,6 +143,17 @@ typedef enum { PB14 = PB_14, PB15 = PB_15, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif // Generic signals namings LED1 = PC_9, @@ -152,8 +163,8 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - USBTX = PA_2, - USBRX = PA_3, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h index d886153259e..2b92feedda4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h index f3c5dd5ee2a..70edef80c31 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h @@ -119,6 +119,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -127,10 +139,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h index 3bd078970cb..d57c6128f95 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h @@ -124,6 +124,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c new file mode 100644 index 00000000000..46c6040ae49 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c @@ -0,0 +1,175 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "mbed_assert.h" +#include "cmsis.h" + +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#endif + +// Minimum number of bytes to be programmed at a time +#define MIN_PROG_SIZE (4U) + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Flash */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t PAGEError = 0; + FLASH_EraseInitTypeDef EraseInitStruct; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + // Clear Flash status register's flags + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_OPTVERR); + + /* MBED HAL erases 1 sector at a time */ + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.PageAddress = address; + EraseInitStruct.NbPages = 1; + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + uint32_t StartAddress = 0; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if ((size % MIN_PROG_SIZE) != 0) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Program the user Flash area word by word */ + StartAddress = address; + + /* HW needs an aligned address to program flash, which data parameter doesn't ensure */ + if ((uint32_t) data % 4 != 0) { + + volatile uint32_t data32; + while (address < (StartAddress + size) && (status == 0)) { + for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) { + *(((uint8_t *) &data32) + i) = *(data + i); + } + + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } else { /* case where data is aligned, so let's avoid any copy */ + while ((address < (StartAddress + size)) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } + + flash_lock(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return MBED_FLASH_INVALID_SIZE; + } else { + return FLASH_PAGE_SIZE; + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return MIN_PROG_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c index 8c9cf38f214..b0747f4d502 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,129 +27,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" +#include "serial_api_hal.h" #define UART_NUM (3) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -687,7 +576,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -746,6 +635,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h index 6e998e8e3dc..b5227168fb0 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h @@ -227,6 +227,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -235,10 +247,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, - SERIAL_RX = PD_9, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = PB_5, // Conflict between D11 and RMII RX Data Valid (PA7) @@ -275,10 +287,6 @@ typedef enum { NC = (int)0xFFFFFFFF } PinName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART UART_3 - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h new file mode 100644 index 00000000000..f39e40d693b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include + +#if DEVICE_FLASH + +#define FLASH_SIZE ((uint32_t)0x100000) + +/* Base address of the Flash sectors */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c new file mode 100644 index 00000000000..321647cf094 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c @@ -0,0 +1,218 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #if DEVICE_FLASH + +#include "flash_api.h" +#include "flash_data.h" +#include "platform/mbed_critical.h" + +static uint32_t GetSector(uint32_t Address); +static uint32_t GetSectorSize(uint32_t Sector); + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Falsh */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + static FLASH_EraseInitTypeDef EraseInitStruct; + uint32_t FirstSector; + uint32_t SectorError = 0; + int32_t status = 0; + + if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Get the 1st sector to erase */ + FirstSector = GetSector(address); + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + EraseInitStruct.Sector = FirstSector; + EraseInitStruct.NbSectors = 1; + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int32_t status = 0; + + if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + + __HAL_FLASH_DATA_CACHE_RESET(); + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + __HAL_FLASH_DATA_CACHE_ENABLE(); + + while ((size > 0) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) { + status = -1; + } else { + size--; + address++; + data++; + } + } + + flash_lock(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + return MBED_FLASH_INVALID_SIZE; + } else { + return (GetSectorSize(GetSector(address))); + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + // Flash of STM32F2 devices can be programed 1 byte at a time + return 1; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +/** + * @brief Gets the sector of a given address + * @param None + * @retval The sector of a given address + */ +static uint32_t GetSector(uint32_t address) +{ + uint32_t sector = 0; + uint32_t tmp = address - ADDR_FLASH_SECTOR_0; + /* This function supports 1Mb and 2Mb flash sizes */ +#if defined(ADDR_FLASH_SECTOR_16) + if (address & 0x100000) { // handle 2nd bank + /* Sector will be at least 12 */ + sector = FLASH_SECTOR_12; + tmp -= 0x100000; + address -= 0x100000; + } +#endif + if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize + sector += tmp >>14; + } +#if defined(ADDR_FLASH_SECTOR_5) + else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size + sector += FLASH_SECTOR_4; + } else { + sector += 4 + (tmp >>17); + } +#else + // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one. + else { //64k sector size + sector += FLASH_SECTOR_4; + } +#endif + return sector; +} + +/** + * @brief Gets sector Size + * @param None + * @retval The size of a given sector + */ +static uint32_t GetSectorSize(uint32_t Sector) +{ + uint32_t sectorsize = 0x00; +#if defined(FLASH_SECTOR_16) + if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ + (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\ + (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { + sectorsize = 16 * 1024; + } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { +#else +if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ + (Sector == FLASH_SECTOR_3)) { + sectorsize = 16 * 1024; + } else if(Sector == FLASH_SECTOR_4) { +#endif + sectorsize = 64 * 1024; + } else { + sectorsize = 128 * 1024; + } + return sectorsize; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h index a961a63a448..7359e18a6c8 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -145,6 +145,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #define GPIO_IP_WITHOUT_BRR #include "gpio_object.h" diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index 7f238971756..cc74ffb45e9 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,216 +27,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#define UART_NUM (8) +#define UART_NUM (6) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - switch (obj_s->uart) { - case UART_1: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - break; - - case UART_2: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - break; - -#if defined(USART3_BASE) - case UART_3: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - break; -#endif -#if defined(USART6_BASE) - case UART_6: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - break; -#endif -#if defined(UART7_BASE) - case UART_7: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_ENABLE(); - obj_s->index = 6; - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_ENABLE(); - obj_s->index = 7; - break; -#endif - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - switch (obj_s->index) { - case 0: - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - break; - - case 1: - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - break; - -#if defined(USART3_BASE) - case 2: - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - break; -#endif -#if defined(UART4_BASE) - case 3: - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - break; -#endif -#if defined(UART5_BASE) - case 4: - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - break; -#endif -#if defined(USART6_BASE) - case 5: - __USART6_FORCE_RESET(); - __USART6_RELEASE_RESET(); - __USART6_CLK_DISABLE(); - break; -#endif -#if defined(UART7_BASE) - case 6: - __UART7_FORCE_RESET(); - __UART7_RELEASE_RESET(); - __UART7_CLK_DISABLE(); - break; -#endif -#if defined(UART8_BASE) - case 7: - __UART8_FORCE_RESET(); - __UART8_RELEASE_RESET(); - __UART8_CLK_DISABLE(); - break; -#endif - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -865,7 +667,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -924,6 +726,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h index 4c9aa7c4a17..84dc52f0190 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_2 = (int)SPI2_BASE, SPI_3 = (int)SPI3_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h index d5aebd0b64c..cd4bab1df26 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PB_13, LED2 = PB_13, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h index e6702378135..a7c5821bf78 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h @@ -49,13 +49,9 @@ typedef enum { typedef enum { UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE // defined for compilation issue. UART3 is not present on STM32F303K8 + UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h index 65b8674ddf7..c27ed38491f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h @@ -115,6 +115,18 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, @@ -123,10 +135,10 @@ typedef enum { USER_BUTTON = 0x20, // no user button on the board // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h index 834ab70364b..271640d391e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h index c24d17702ba..ed39a9e7703 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h @@ -177,6 +177,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PE_9, LED2 = PE_8, @@ -191,10 +203,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h index ff95fc7be8f..b711ad93024 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h index 456c8b11b8a..8fbd953fb12 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h @@ -131,6 +131,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -139,10 +151,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h index 6b86154e45a..02772cf5546 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h @@ -55,11 +55,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART UART_3 - - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h index fb36d0c13ef..e7ce2730b43 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h @@ -198,6 +198,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -206,10 +218,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = SERIAL_TX, // Virtual Com Port - USBRX = SERIAL_RX, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h index c646d1d65dc..924634dbbf0 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PB_3 -#define STDIO_UART_RX PB_4 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h index ea7db7d7507..f5466954c1f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h @@ -113,6 +113,18 @@ typedef enum { // D14 = PB_9, // D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PB_3, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_4, +#endif + // Generic signals namings LED1 = PB_6, LED2 = PB_7, @@ -121,10 +133,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PB_3, - SERIAL_RX = PB_4, - USBTX = PB_3, - USBRX = PB_4, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h index efde3b38292..ea97b1188fa 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h index fce0ab472e9..65022e77ea5 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h @@ -126,6 +126,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -134,10 +146,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h index ba731890ce5..590b60d94c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h @@ -132,6 +132,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h index 2a8d5d35096..855b76fc0c7 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h @@ -442,16 +442,6 @@ * @{ */ #define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ -#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) - is connected to the non inverting input of comparator X-1U */ -/** - * @} - */ -#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) -/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices) - * @{ - */ -#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ #define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) is connected to the non inverting input of comparator X-1U */ /** @@ -2395,8 +2385,7 @@ || \ (((INPUT) == COMP_NONINVERTINGINPUT_IO1))) -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE)) +#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */ #define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c new file mode 100644 index 00000000000..9a2d7c4c8ef --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -0,0 +1,175 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "mbed_assert.h" +#include "cmsis.h" + +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U) +#endif + +// Minimum number of bytes to be programmed at a time +#define MIN_PROG_SIZE (4U) + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Flash */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t PAGEError = 0; + FLASH_EraseInitTypeDef EraseInitStruct; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + // Clear Flash status register's flags + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* MBED HAL erases 1 sector at a time */ + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.PageAddress = address; + EraseInitStruct.NbPages = 1; + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + uint32_t StartAddress = 0; + int32_t status = 0; + + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return -1; + } + + if ((size % MIN_PROG_SIZE) != 0) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Program the user Flash area word by word */ + StartAddress = address; + + /* HW needs an aligned address to program flash, which data parameter doesn't ensure */ + if ((uint32_t) data % 4 != 0) { + + volatile uint32_t data32; + while (address < (StartAddress + size) && (status == 0)) { + for (uint8_t i = 0; i < MIN_PROG_SIZE; i++) { + *(((uint8_t *) &data32) + i) = *(data + i); + } + + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } else { /* case where data is aligned, so let's avoid any copy */ + while ((address < (StartAddress + size)) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + address = address + MIN_PROG_SIZE; + data = data + MIN_PROG_SIZE; + } else { + status = -1; + } + } + } + + flash_lock(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if (!(IS_FLASH_PROGRAM_ADDRESS(address))) { + return MBED_FLASH_INVALID_SIZE; + } else { + return FLASH_PAGE_SIZE; + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return MIN_PROG_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c index b1f2de8ca06..13ba2eaa7af 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,179 +27,21 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" - -#define UART_NUM (5) - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -UART_HandleTypeDef uart_handlers[UART_NUM]; - -uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock + switch to SystemClock - if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_ENABLE(); -#if defined(RCC_USART1CLKSOURCE_SYSCLK) - __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK); -#endif - obj_s->index = 0; - } -#if defined(USART2_BASE) - if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_ENABLE(); -#if defined(RCC_USART2CLKSOURCE_SYSCLK) - __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK); -#endif - obj_s->index = 1; - } -#endif -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_ENABLE(); -#if defined(RCC_USART3CLKSOURCE_SYSCLK) - __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK); -#endif - obj_s->index = 2; - } -#endif -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_ENABLE(); -#if defined(RCC_UART4CLKSOURCE_SYSCLK) - __HAL_RCC_UART4_CONFIG(RCC_UART4CLKSOURCE_SYSCLK); -#endif - obj_s->index = 3; - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __UART5_CLK_ENABLE(); -#if defined(RCC_UART5CLKSOURCE_SYSCLK) - __HAL_RCC_UART5_CONFIG(RCC_UART5CLKSOURCE_SYSCLK); -#endif - obj_s->index = 4; - } -#endif - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} +#include "serial_api_hal.h" -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } -#endif -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - } +#if defined (TARGET_STM32F302x8) || defined (TARGET_STM32F303x8) || defined (TARGET_STM32F334x8) + #define UART_NUM (3) +#else + #define UART_NUM (5) // max value #endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); +uint32_t serial_irq_ids[UART_NUM] = {0}; +UART_HandleTypeDef uart_handlers[UART_NUM]; - obj_s->baudrate = baudrate; - init_uart(obj); -} +static uart_irq_handler irq_handler; /****************************************************************************** * INTERRUPTS HANDLING @@ -785,7 +627,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -844,6 +686,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h new file mode 100644 index 00000000000..15a5c2bc7a9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PB_6 +#define STDIO_UART_RX PB_7 +#define STDIO_UART UART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c new file mode 100644 index 00000000000..7c2b21786f6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c @@ -0,0 +1,212 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO +// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK +// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h new file mode 100644 index 00000000000..941228cae4d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h @@ -0,0 +1,230 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + // Not connected + NC = -1, + + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Module pins + // Defined based on the external pin (40-pin connector) alternate function mapping (Page 15 of MTQ-H5-B01 device guide) + // Device guide used: S000628,Version1.4 + P_1 = PB_6, + P_2 = PA_14, + P_3 = PA_15, + P_4 = PB_4, + P_5 = NC, + P_6 = NC, + P_7 = NC, + P_8 = NC, + P_9 = PA_2, + P_10 = PA_7, + P_11 = PB_1, + P_12 = PA_1, + P_13 = NC, + P_14 = PB_5, + P_15 = PA_5, + P_16 = PB_8, + P_17 = PB_15, + P_18 = PC_2, + P_19 = PB_0, + P_20 = PC_0, + P_21 = PC_1, + P_22 = PC_4, + P_23 = PB_13, + P_24 = PC_9, + P_25 = PB_9, + P_26 = PA_6, + P_27 = PC_8, + P_28 = NC, + P_29 = PA_0, + P_30 = PA_9, + P_31 = PA_8, + P_32 = PA_3, + P_33 = NC, + P_34 = NC, + P_35 = NC, + P_36 = NC, + P_37 = NC, + P_38 = PB_3, + P_39 = PA_13, + P_40 = PB_7, + + //DAPLink + USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = MBED_CONF_TARGET_USB_RX, + SWDIO = PA_13, + SWCLK = PA_14, + + I2C1_SCL = PB_8, + I2C1_SDA = PB_9, + I2C3_SCL = PA_8, + I2C3_SDA = PC_9, + + I2C_SCL = I2C1_SCL, + I2C_SDA = I2C1_SDA, + + SPI1_MOSI = PB_5, + SPI1_MISO = PA_6, + SPI1_SCK = PA_5, + SPI2_MOSI = PB_15, + SPI2_MISO = PC_2, + SPI2_SCK = PB_13, + + SPI_MOSI = SPI1_MOSI, + SPI_MISO = SPI1_MISO, + SPI_SCK = SPI1_SCK, + SPI_CS1 = PA_3, //LCD CS + SPI_CS2 = PA_15, //SD Card CS + + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + SERIAL_RTS = PA_0, + SERIAL_CTS = PA_1, + SERIAL_DCD = PA_7, + SERIAL_DSR = PA_9, + SERIAL_DTR = PA_8, + SERIAL_RI = PB_1, + + WAKEUP = PA_0, + + // Generic signals namings + LED1 = PA_7, + LED2 = PC_4, + LED3 = PB_13, //MTB mapped to LINK_STATUS pin on module. + SW1 = PB_4, + GPIO1 = PC_8, + GPIO3 = PB_1, + AIN0 = PB_0, + AIN1 = PC_0, + AIN2 = PC_1, + + //Standardized button names + BUTTON1 = SW1, + + RADIO_TX = PC_7, + RADIO_RX = PC_6, + RADIO_RTS = PB_10, + RADIO_CTS = PB_12, + RADIO_DCD = NC, + RADIO_DSR = NC, + RADIO_DTR = NC, + RADIO_RI = NC, + MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16 + MDMTXD = RADIO_TX, // Transmit Data + MDMRXD = RADIO_RX, // Receive Data + MDMRTS = RADIO_RTS, // Request to Send + MDMCTS = RADIO_CTS, // Clear to Send + MDMDCD = RADIO_DCD, // Data Carrier Detect + MDMDSR = RADIO_DSR, // Data Set Ready + MDMDTR = RADIO_DTR, // Data Terminal Ready + MDMRI = RADIO_RI, // Ring Indicator + +} PinName; + +#define ACTIVE_HIGH_POLARITY 1 +#define ACTIVE_LOW_POLARITY 0 + +#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S new file mode 100644 index 00000000000..aa7d51ad148 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S @@ -0,0 +1,373 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct new file mode 100644 index 00000000000..491087ba473 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct @@ -0,0 +1,47 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region + + ER_IROM1 0x08010000 0x70000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM + RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S new file mode 100644 index 00000000000..effaaf1e52e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S @@ -0,0 +1,346 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct new file mode 100644 index 00000000000..491087ba473 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct @@ -0,0 +1,47 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region + + ER_IROM1 0x08010000 0x70000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM + RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld new file mode 100644 index 00000000000..a832fffb7e5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld @@ -0,0 +1,153 @@ +/* Linker script for STM32F411 */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + /* First 64kB of flash reserved for bootloader */ + /* Other 448kB for application */ + FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K +/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */ + RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S new file mode 100644 index 00000000000..b7f10ce5fc5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S @@ -0,0 +1,297 @@ +/* File: startup_STM32F40x.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 09 July 2012 + * + * Copyright (c) 2011, 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WWDG_IRQHandler /* Window WatchDog */ + .long PVD_IRQHandler /* PVD through EXTI Line detection */ + .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .long FLASH_IRQHandler /* FLASH */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line0 */ + .long EXTI1_IRQHandler /* EXTI Line1 */ + .long EXTI2_IRQHandler /* EXTI Line2 */ + .long EXTI3_IRQHandler /* EXTI Line3 */ + .long EXTI4_IRQHandler /* EXTI Line4 */ + .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long EXTI9_5_IRQHandler /* External Line[9:5]s */ + .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long 0 /* Reserved */ + .long EXTI15_10_IRQHandler /* External Line[15:10]s */ + .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .long 0 /* Reserved */ + .long SDIO_IRQHandler /* SDIO */ + .long TIM5_IRQHandler /* TIM5 */ + .long SPI3_IRQHandler /* SPI3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long OTG_FS_IRQHandler /* USB OTG FS */ + .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .long USART6_IRQHandler /* USART6 */ + .long I2C3_EV_IRQHandler /* I2C3 event */ + .long I2C3_ER_IRQHandler /* I2C3 error */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long FPU_IRQHandler /* FPU */ + .long SPI4_IRQHandler /* SPI4 */ + .long SPI5_IRQHandler /* SPI5 */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WWDG_IRQHandler + def_irq_default_handler PVD_IRQHandler + def_irq_default_handler TAMP_STAMP_IRQHandler + def_irq_default_handler RTC_WKUP_IRQHandler + def_irq_default_handler FLASH_IRQHandler + def_irq_default_handler RCC_IRQHandler + def_irq_default_handler EXTI0_IRQHandler + def_irq_default_handler EXTI1_IRQHandler + def_irq_default_handler EXTI2_IRQHandler + def_irq_default_handler EXTI3_IRQHandler + def_irq_default_handler EXTI4_IRQHandler + def_irq_default_handler DMA1_Stream0_IRQHandler + def_irq_default_handler DMA1_Stream1_IRQHandler + def_irq_default_handler DMA1_Stream2_IRQHandler + def_irq_default_handler DMA1_Stream3_IRQHandler + def_irq_default_handler DMA1_Stream4_IRQHandler + def_irq_default_handler DMA1_Stream5_IRQHandler + def_irq_default_handler DMA1_Stream6_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler EXTI9_5_IRQHandler + def_irq_default_handler TIM1_BRK_TIM9_IRQHandler + def_irq_default_handler TIM1_UP_TIM10_IRQHandler + def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler + def_irq_default_handler TIM1_CC_IRQHandler + def_irq_default_handler TIM2_IRQHandler + def_irq_default_handler TIM3_IRQHandler + def_irq_default_handler TIM4_IRQHandler + def_irq_default_handler I2C1_EV_IRQHandler + def_irq_default_handler I2C1_ER_IRQHandler + def_irq_default_handler I2C2_EV_IRQHandler + def_irq_default_handler I2C2_ER_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler USART1_IRQHandler + def_irq_default_handler USART2_IRQHandler + def_irq_default_handler EXTI15_10_IRQHandler + def_irq_default_handler RTC_Alarm_IRQHandler + def_irq_default_handler OTG_FS_WKUP_IRQHandler + def_irq_default_handler DMA1_Stream7_IRQHandler + def_irq_default_handler SDIO_IRQHandler + def_irq_default_handler TIM5_IRQHandler + def_irq_default_handler SPI3_IRQHandler + def_irq_default_handler DMA2_Stream0_IRQHandler + def_irq_default_handler DMA2_Stream1_IRQHandler + def_irq_default_handler DMA2_Stream2_IRQHandler + def_irq_default_handler DMA2_Stream3_IRQHandler + def_irq_default_handler DMA2_Stream4_IRQHandler + def_irq_default_handler OTG_FS_IRQHandler + def_irq_default_handler DMA2_Stream5_IRQHandler + def_irq_default_handler DMA2_Stream6_IRQHandler + def_irq_default_handler DMA2_Stream7_IRQHandler + def_irq_default_handler USART6_IRQHandler + def_irq_default_handler I2C3_EV_IRQHandler + def_irq_default_handler I2C3_ER_IRQHandler + def_irq_default_handler FPU_IRQHandler + def_irq_default_handler SPI4_IRQHandler + def_irq_default_handler SPI5_IRQHandler + def_irq_default_handler DEF_IRQHandler + + .end diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S new file mode 100644 index 00000000000..1b782c36dca --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S @@ -0,0 +1,523 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf new file mode 100644 index 00000000000..87e12d26bb3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf @@ -0,0 +1,32 @@ +/* [ROM = 512kb = 0x80000] */ +define symbol __intvec_start__ = 0x08010000; +define symbol __region_ROM_start__ = 0x08010000; +define symbol __region_ROM_end__ = 0x0807FFFF; + +/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000198; +define symbol __region_RAM_end__ = 0x2001FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +/* Stack: 4kB - 408B for vector table */ +/* Heap: 64kB */ +define symbol __size_cstack__ = 0xe68; +define symbol __size_heap__ = 0x10000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h new file mode 100644 index 00000000000..f0c2b2a9071 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h new file mode 100644 index 00000000000..e44a1ce9f61 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h new file mode 100644 index 00000000000..cedecee5453 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "stm32f4xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() + +#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h new file mode 100644 index 00000000000..c9e8ed9d04b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h @@ -0,0 +1,8683 @@ +/** + ****************************************************************************** + * @file stm32f411xe.h + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - peripherals registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f411xe + * @{ + */ + +#ifndef __STM32F411xE_H +#define __STM32F411xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /* __FPU_PRESENT */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ +#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END 0x0807FFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) +/* Legacy define */ +#define ADC_BASE ADC1_COMMON_BASE +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) + + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +/* Legacy define */ +#define ADC ADC1_COMMON +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ + !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ + !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \ + !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ + /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ + /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ + #define STM32F411xE /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ + /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, + STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ + /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG + and STM32F479NG Devices */ + /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */ + /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */ + /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */ + /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */ + /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, + STM32F413RG, STM32F413VG and STM32F413ZG Devices */ + /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS version number V2.6.1 + */ +#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F410Tx) + #include "stm32f410tx.h" +#elif defined(STM32F410Cx) + #include "stm32f410cx.h" +#elif defined(STM32F410Rx) + #include "stm32f410rx.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#elif defined(STM32F469xx) + #include "stm32f469xx.h" +#elif defined(STM32F479xx) + #include "stm32f479xx.h" +#elif defined(STM32F412Cx) + #include "stm32f412cx.h" +#elif defined(STM32F412Zx) + #include "stm32f412zx.h" +#elif defined(STM32F412Rx) + #include "stm32f412rx.h" +#elif defined(STM32F412Vx) + #include "stm32f412vx.h" +#elif defined(STM32F413xx) + #include "stm32f413xx.h" +#elif defined(STM32F423xx) + #include "stm32f423xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0U, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c new file mode 100644 index 00000000000..eee454211db --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c @@ -0,0 +1,246 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 50 | 50 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "mbed_debug.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif + + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ +#if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) { + while(1) { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/******************************************************************************/ +/* Hard Fault Handler */ +/******************************************************************************/ +void HardFault_Handler(void) +{ + debug("Hard Fault\n"); + NVIC_SystemReset(); +} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h new file mode 100644 index 00000000000..113f67cfe61 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h new file mode 100644 index 00000000000..16467b7c876 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c new file mode 100644 index 00000000000..ea532df442b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if MBED_CONF_NSAPI_PRESENT + +#include "cellular/onboard_modem_api.h" +#include "gpio_api.h" +#include "platform/mbed_wait_api.h" +#include "PinNames.h" + +#if MODEM_ON_BOARD + +static void press_power_button(int time_ms) +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, MDMPWRON, 1); + gpio_write(&gpio, 0); + wait_ms(time_ms); + gpio_write(&gpio, 1); +} + +void onboard_modem_init() +{ + //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed +} + +void onboard_modem_deinit() +{ + //does nothing at the moment, TODO: MultiTech to add hardware de-initialization stuff if needed +} +void onboard_modem_power_up() +{ + /* keep the power line low for 200 milisecond */ + press_power_button(200); + /* give modem a little time to respond */ + wait_ms(100); +} + +void onboard_modem_power_down() +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, MDMPWRON, 0); + /* keep the power line low for more than 10 seconds. + * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes + * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 + * seconds only */ + wait_ms(10*1000); +} +#endif //MODEM_ON_BOARD +#endif //MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h index 23f8aea00e9..bf3ae14ca4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h index 3c967a8aa13..b229bc4d2ba 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h @@ -113,6 +113,18 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PD_12, LED2 = PD_13, @@ -122,10 +134,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h index 23f8aea00e9..bf3ae14ca4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h index df021143930..c89ff31a0f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h index 5d22cf38cbb..10be44289a6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h @@ -56,10 +56,6 @@ typedef enum { UART_6 = (int)USART6_BASE, } UARTName; -#define STDIO_UART_TX PC_6 -#define STDIO_UART_RX PC_7 -#define STDIO_UART UART_6 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h index 0b4d432f6cd..41d2701c46c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h @@ -222,13 +222,25 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PC_6, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PC_7, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PD_8, LED3 = PD_9, LED4 = PD_10, - USBTX = PC_6, /* USART6 */ - USBRX = PC_7, + USBTX = STDIO_UART_TX, /* USART6 */ + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, /* I2C1 */ I2C_SDA = PB_9, SPI_MOSI = PC_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h index e25c70514f2..10be44289a6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h @@ -56,10 +56,6 @@ typedef enum { UART_6 = (int)USART6_BASE, } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h index 1968bebf0f7..d645d3cca84 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h @@ -196,21 +196,33 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings - LED1 = PD_13, - LED2 = PD_12, - LED3 = PD_13, - LED4 = PD_12, - LED5 = PD_14, - LED6 = PD_15, - LED_RED = LED1, + LED1 = PD_13, // LD3 as LD1 is not a user LED + LED2 = PD_12, // LD4 as LD2 is not a user LED + LED3 = PD_13, // orange + LED4 = PD_12, // green + LED5 = PD_14, // red + LED6 = PD_15, // blue + LED_RED = LED5, USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, /* USART2 */ - SERIAL_RX = PA_3, - USBTX = PA_2, /* USART2 */ - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, /* USART2 */ + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, /* USART2 */ + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, /* I2C1 */ I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c index 5610e679500..5a042fb7521 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c @@ -17,25 +17,20 @@ /** * This file configures the system clock as follows: *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 168 | 168 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 168 | 168 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 42 | 42 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 84 | 84 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO + * SYSCLK(MHz) | 168 + * AHBCLK (MHz) | 168 + * APB1CLK (MHz) | 42 + * APB2CLK (MHz) | 84 + * USB capable | YES *----------------------------------------------------------------------------- **/ #include "stm32f4xx.h" - +#include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ @@ -44,16 +39,20 @@ This value must be a multiple of 0x200. */ -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (1) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ +#if ((CLOCK_SOURCE) & USE_PLL_HSI) uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + /** * @brief Setup the microcontroller system @@ -110,20 +109,23 @@ void SystemInit(void) */ void SetSysClock(void) { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 if (SetSysClock_PLL_HSE(1) == 0) #endif { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 if (SetSysClock_PLL_HSE(0) == 0) #endif { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { + if (SetSysClock_PLL_HSI() == 0) +#endif + { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + MBED_ASSERT(1); } } } @@ -133,14 +135,14 @@ void SetSysClock(void) //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz } -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; /* The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency, to update the voltage scaling value @@ -186,15 +188,16 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 1; // OK } -#endif +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ +#if ((CLOCK_SOURCE) & USE_PLL_HSI) /******************************************************************************/ /* PLL (clocked by HSI) used as System clock source */ /******************************************************************************/ uint8_t SetSysClock_PLL_HSI(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; /* The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency, to update the voltage scaling value @@ -232,3 +235,4 @@ uint8_t SetSysClock_PLL_HSI(void) return 1; // OK } +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S new file mode 100644 index 00000000000..57738bbdc32 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S @@ -0,0 +1,636 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf new file mode 100644 index 00000000000..a45f1590555 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000187; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000188; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x7000; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block HEAP, block CSTACK }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h index caa92c00d7d..63cdc8161b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h @@ -51,10 +51,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h index da18af25922..eb975969392 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h index 68f0eff9d2a..c03d011251e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, ELMO_RF_SPI2 = SPI_1, SPI_2 = (int)SPI2_BASE, ELMO_SPI1 = SPI_2, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h index 0b7c41698d3..e81c7b8479e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h @@ -125,6 +125,18 @@ typedef enum { D14 = PC_9, D15 = PA_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_1, @@ -133,10 +145,10 @@ typedef enum { USER_BUTTON = PB_7, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h index 9046d68c2d8..697d107c412 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h index df021143930..c89ff31a0f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h index 78bc359403c..c85180daf46 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h @@ -33,10 +33,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h index bf017176958..8298412355b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h @@ -175,6 +175,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -184,10 +196,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, - SERIAL_RX = PD_9, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c index 2ffdfc51c0b..191ecaf3eaa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c @@ -176,11 +176,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -241,11 +243,13 @@ uint8_t SetSysClock_PLL_HSI(void) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h index 26bfcfccedc..a271aefdb51 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h @@ -43,10 +43,6 @@ typedef enum { UART_10 = (int)UART10_BASE } UARTName; -#define STDIO_UART_TX PG_14 -#define STDIO_UART_RX PG_9 -#define STDIO_UART UART_6 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h index 4b75ed608a0..7b7f67f32f1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h @@ -222,6 +222,18 @@ typedef enum { D14 = PB_11, D15 = PB_10, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PG_14, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PG_9, +#endif + // Generic signals namings LED1 = PC_5, // Green = LD3 on the board LED2 = PE_3, // Red = LD4 on the board @@ -230,10 +242,10 @@ typedef enum { LED_RED = LED2, USER_BUTTON = PA_0, BUTTON1 = USER_BUTTON, - SERIAL_TX = PG_14, - SERIAL_RX = PG_9, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c index 34aa1733138..66575fd3f62 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c @@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -242,11 +244,13 @@ uint8_t SetSysClock_PLL_HSI(void) } /* Select PLLI2S output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h new file mode 100644 index 00000000000..5a74e14367d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE, + UART_9 = (int)UART9_BASE, + UART_10 = (int)UART10_BASE +} UARTName; + +#define STDIO_UART_TX PD_8 +#define STDIO_UART_RX PD_9 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + FMPI2C_1 = (int)FMPI2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE, + CAN_3 = (int)CAN3_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c new file mode 100644 index 00000000000..01e5ded312d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c @@ -0,0 +1,396 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // Connected to LED1 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_3_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LED2 + {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, // Connected to LED3 + {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT0, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)}, + {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// Pins using PWM_5 (TIM5) cannot be used as TIM5 is already used by ticker. +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, + {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, + {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, + {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, + {PA_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, + {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, + {PA_7_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, + {PA_7_ALT1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, + {PA_7_ALT2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // Connected to LED1 + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // Connected to LED1 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // Connected to LED1 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // Connected to LED2 + {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, + {PB_8_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, + {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, + {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, + {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // Connected to LED3 + {PB_14_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // Connected to LED3 + {PB_14_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // Connected to LED3 + {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, + {PB_15_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, + {PB_15_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, +// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, +// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, +// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, +// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PA_15_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX + {PD_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_1, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_12, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PB_3_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED2 + {PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX + {PD_14, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PG_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_11, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART10)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED3 + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_10_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_6_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED3 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_5_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, // Connected to LED1 + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_2_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12_ALT0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_4_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11_ALT0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h new file mode 100644 index 00000000000..2060e5cb239 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h @@ -0,0 +1,261 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, + PA_3 = 0x03, + PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, + PA_5 = 0x05, + PA_5_ALT0 = PA_5|ALT0, + PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT1 = PA_7|ALT1, + PA_7_ALT2 = PA_7|ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_10_ALT0 = PA_10|ALT0, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_12_ALT0 = PA_12|ALT0, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT1 = PB_0|ALT1, + PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT1 = PB_1|ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PA_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_6_ALT0 = PB_6|ALT0, + PB_7 = 0x17, + PB_8 = 0x18, + PB_8_ALT0 = PB_8|ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9|ALT0, + PB_10 = 0x1A, + PB_10_ALT0 = PB_10|ALT0, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_12_ALT0 = PB_12|ALT0, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13|ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT1 = PB_14|ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15|ALT0, + PB_15_ALT1 = PB_15|ALT1, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_6_ALT0 = PC_6|ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7|ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8|ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9|ALT0, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11|ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_2_ALT0 = PE_2|ALT0, + PE_3 = 0x43, + PE_4 = 0x44, + PE_4_ALT0 = PE_4|ALT0, + PE_5 = 0x45, + PE_5_ALT0 = PE_5|ALT0, + PE_6 = 0x46, + PE_6_ALT0 = PE_6|ALT0, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_11_ALT0 = PE_11|ALT0, + PE_12 = 0x4C, + PE_12_ALT0 = PE_12|ALT0, + PE_13 = 0x4D, + PE_13_ALT0 = PE_13|ALT0, + PE_14 = 0x4E, + PE_14_ALT0 = PE_14|ALT0, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_3, + A1 = PC_0, + A2 = PC_3, + A3 = PC_1, + A4 = PC_4, + A5 = PC_5, + D0 = PG_9, + D1 = PG_14, + D2 = PF_15, + D3 = PE_13, + D4 = PF_14, + D5 = PE_11, + D6 = PE_9, + D7 = PF_13, + D8 = PF_12, + D9 = PD_15, + D10 = PD_14, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PB_0, // Green + LED2 = PB_7, // Blue + LED3 = PB_14, // Red + LED4 = LED1, + LED_RED = LED3, + USER_BUTTON = PC_13, + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = PD_8, + SERIAL_RX = PD_9, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + //USB pins + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c new file mode 100644 index 00000000000..34aa1733138 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c @@ -0,0 +1,269 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 + * AHBCLK (MHz) | 100 + * APB1CLK (MHz) | 50 + * APB2CLK (MHz) | 100 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "mbed_assert.h" + + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLI2S output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h index fb1cdab06b6..3a7aa557b6d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h index 00be7f8dac6..24cc2238677 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h @@ -211,6 +211,18 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PG_13, // Corresponds to LD3 on MB1075B LED2 = PG_14, // Corresponds to LD4 on MB1075B @@ -220,10 +232,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, SPI_MOSI = PA_7, SPI_MISO = PA_6, SPI_SCK = PA_5, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h index 1690d9e13f0..d2c2320ba5b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h index f4f612d1e2e..25c07fa7379 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h @@ -235,6 +235,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -244,10 +256,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h index e818a08f300..0f0b59fcefb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h @@ -54,10 +54,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h index 2b0656381b7..aa912fba41a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h @@ -145,9 +145,21 @@ typedef enum { SPI_CLK = D13, SPI_NSS = D10, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // ST-Link - USBRX = PA_10, - USBTX = PA_9, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_13, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.cpp new file mode 100644 index 00000000000..1dcc8af956b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.cpp @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "battery_charger_i2c.h" + +BatteryChargerI2c::BatteryChargerI2c(PinName sda, PinName scl):_i2c(), _hz(100000) +{ + i2c_init(&_i2c, sda, scl); +} + +bool BatteryChargerI2c::read_from_i2c(int i2c_address, char* data_read, int length) +{ + int bytes_read = i2c_read(&_i2c, i2c_address, data_read, length, 1); + return (length == bytes_read); +} + +bool BatteryChargerI2c::write_to_i2c(int i2c_address, const char* data_write, int length) +{ + int bytes_written = i2c_write(&_i2c, i2c_address, data_write, length, 1); + return (length == bytes_written); +} diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.h similarity index 50% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.h index 211a4c870df..c15d4b1d486 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2017 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,39 +13,31 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H -#include "mbed_assert.h" +#ifndef BATTERY_CHARGER_I2C +#define BATTERY_CHARGER_I2C + +#include "hal/i2c_api.h" #ifdef __cplusplus -extern "C" { +extern"C"{ #endif -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __I uint32_t *reg_in; - __IO uint32_t *reg_buf; -} gpio_t; +class BatteryChargerI2c{ -static inline void gpio_write(gpio_t *obj, int value) { - *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0); -} +public: + BatteryChargerI2c(PinName sda, PinName scl); + bool read_from_i2c(int i2c_address, char *data_read, int length); + bool write_to_i2c(int i2c_address, const char *data_write, int length); + virtual ~BatteryChargerI2c() {} -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} +private: + i2c_t _i2c; + int _hz; +}; #ifdef __cplusplus } #endif -#endif +#endif //BATTERY_CHARGER_I2C diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.cpp new file mode 100644 index 00000000000..fbcd250477e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.cpp @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "min_battery_voltage.h" +#include "battery_charger_i2c.h" + +/** Defining HAL_MspInit strong function + * in user defined file as described in documentation + */ + +void HAL_MspInit(void) +{ + set_minimum_battery_voltage(); +} + +void set_minimum_battery_voltage() +{ + char data_write[2] = {0}; + char data_read; + BatteryChargerI2c i2c_object(I2C_SDA_B, I2C_SCL_B); + + if (i2c_object.write_to_i2c(BQ24295_I2C_ADDRESS,&data_write[0] , 1)){ + i2c_object.read_from_i2c(BQ24295_I2C_ADDRESS, &data_read, 1); + data_read = data_read & MIN_BATTERY_VOLTAGE_MASK; + data_write[0] = 0x0; + data_write[1] = data_read; + if (i2c_object.write_to_i2c(BQ24295_I2C_ADDRESS,&data_write[0] , 2)){ + //Battery Voltage is set to 3880mV + } + } + else{ + // Minimum battery voltage could not be set. This is not a critical error, no need to stop execution + // It simply means that longer cabling or USB ports with lower output voltages may cause problems. + } +} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h similarity index 53% rename from features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h index 9b7613e782a..8897843c33a 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2017 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,9 +14,24 @@ * limitations under the License. */ -#ifndef _BTLE_DISCOVERY_H_ -#define _BTLE_DISCOVERY_H_ +#ifndef MIN_BATTERY_VOLTAGE_H +#define MIN_BATTERY_VOLTAGE_H -void bleGattcEventHandler(const ble_evt_t *p_ble_evt); +#ifdef __cplusplus +extern"C"{ +#endif -#endif /*_BTLE_DISCOVERY_H_*/ +#define BQ24295_I2C_ADDRESS (0x6B << 1) +#define MIN_BATTERY_VOLTAGE_MASK (0x87) + +/** Initializes an instance of class BatteryChargerI2c which is using the STM HAL I2C APIs + * This allows longer USB cables or USB ports with lower output voltages to power the board correctly. + */ + +void set_minimum_battery_voltage(void); + +#ifdef __cplusplus +} +#endif + +#endif // MIN_BATTERY_VOLTAGE_H diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h index fcd76d01523..3a7aa557b6d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h @@ -57,9 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h index ea26b948073..26e1426dfe2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h @@ -155,9 +155,26 @@ typedef enum { SPI_SCK = SPI0_SCK, SPI_CS = SPI0_CS, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PA_9, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // DAPLink - USBRX = MBED_CONF_TARGET_USB_RX, - USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_15, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h new file mode 100644 index 00000000000..788bb04f728 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h @@ -0,0 +1,254 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Not connected + NC = (int)0xFFFFFFFF, + + // Module Pins + // PortA + P_A1 = NC, + P_A2 = NC, + P_A3 = NC, + P_A4 = NC, + P_A5 = PC_2, // UART-DTR + P_A6 = PF_2, // Switch-0 + P_A7 = PE_0, // Red, Mode + P_A8 = PB_6, // Green, Switch-1 + P_A9 = PB_8, // Blue + P_A10 = PA_11, // UART-CTS + P_A11 = PA_9, // UART-TXD + P_A12 = PA_12, // UART-RTS + P_A13 = PA_10, // UART-RXD + P_A14 = PD_9, // GPIO-0 + P_A15 = PD_8, // GPIO-1 + P_A16 = PD_11, // GPIO-2 + P_A17 = PD_12, // GPIO-3 + P_A18 = PA_3, // UART-DSR + // PortB + P_B1 = NC, + P_B2 = NC, + P_B3 = NC, + P_B4 = NC, + P_B5 = NC, + P_B6 = NC, + P_B7 = NC, + P_B8 = NC, + // PortC + P_C1 = NC, + P_C2 = NC, + P_C3 = NC, + P_C4 = NC, + P_C5 = PG_4, // SPI-IRQ + P_C6 = PE_13, // SPI-MISO + P_C7 = NC, + P_C8 = PE_12, // Res + P_C9 = NC, + P_C10 = PE_14, // SPI-MOSI + P_C11 = PE_11, // SPI-CS0 + P_C12 = PE_9, // Res + P_C13 = PF_6, // GPIO-4 + P_C14 = PC_1, // RMII-MDC + P_C15 = PA_2, // RMII-MDIO + P_C16 = PF_7, // GPIO-7 + P_C17 = PF_1, // I2C-SCL + P_C18 = PF_0, // I2C-SDA + // PortD + P_D1 = PB_12, // RMII-TXD0 + P_D2 = PB_13, // RMII-TXD1 + P_D3 = PB_11, // RMII-TXEN + P_D4 = PA_7, // RMII-CRSDV + P_D5 = PC_4, // RMII-RXD0 + P_D6 = PC_5, // RMII-RXD1 + P_D7 = NC, + P_D8 = PA_1, // RMII-REFCLK + // TestPads + P_TP5 = PB_4, // NTRST + P_TP7 = PA_13, // TMS SWDIO + P_TP8 = PA_15, // TDI + P_TP9 = PA_14, // TCK SWCLK + P_TP10 = PB_3, // TDO + //P_TP11, // BOOT0 + + // Internal + LED1 = PD_9, + LED2 = PA_12, + LED3 = PD_8, + LED4 = PA_11, + LED5 = PC_2, + LED6 = PA_3, + LED7 = PF_6, + LED_RED = PE_0, + LED_GREEN = PB_6, + LED_BLUE = PB_8, + SW1 = PF_2, + SW2 = PG_4, + + // Standardized button names + BUTTON1 = SW1, + BUTTON2 = SW2, + + I2C_SDA = PF_0, + I2C_SCL = PF_1, + + SPI0_MOSI = PE_14, + SPI0_MISO = PE_13, + SPI0_SCK = PE_12, + SPI0_CS = PE_11, + SPI1_CS = PE_9, + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PA_11, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PA_13, +#endif + + // DAPLink + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + SWDIO = PA_15, + SWCLK = PA_14, + NTRST = PB_4, + + // MTB Aliases + // Left side (top view) + TGT_SWDIO = SWDIO, + TGT_SWCLK = SWCLK, + TGT_RESET = NTRST, + TG_TX = USBTX, + TG_RX = USBRX, + TX1 = P_A15, + RX1 = P_A14, + SDA1 = P_C18, + SCL1 = P_C17, + MOSI1 = P_C10, + MISO1 = P_C6, + SCK1 = SPI_SCK, + GP0 = BUTTON1, + GP1 = SPI_CS, + AIN0 = P_C13, + AIN1 = P_A18, + AIN2 = P_A5, + + //Right side (top view) + GND = NC, + GP10 = NC, + RTS = NC, + CTS = NC, + GP7 = P_C12, + GP6 = P_A12, + GP5 = P_A10, + GP4 = P_A17, + TX2 = NC, + RX2 = NC, + SDA2 = NC, + SCL2 = NC, + MOSI2 = NC, + MISO2 = NC, + SCK2 = NC, + GP3 = P_A16, + GP2 = P_C5, + PWM2 = LED_GREEN, + PWM1 = LED_BLUE, + PWM0 = LED_RED, + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h index e6b09b75023..f9c86382634 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h @@ -178,9 +178,26 @@ typedef enum { BUTTON1 = SW0, BUTTON2 = SW1, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = D8, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = D2, +#endif + // ST-Link - USBRX = MBED_CONF_TARGET_USB_RX, - USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_15, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c new file mode 100644 index 00000000000..718dc230d9e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c @@ -0,0 +1,45 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2017, u-blox Malmö, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Component : HAL + * File : hal_overrides.c + * + * Description : Placeholder for HAL overrides. + *-------------------------------------------------------------------------*/ + +#include "stm32f4xx_hal.h" +#include "stm32f4xx_hal_rcc.h" +#include "stm32f4xx_hal_gpio.h" + +void HAL_MspInit(void) +{ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + + GPIO_InitTypeDef GPIO_InitDef; + + GPIO_InitDef.Pin = GPIO_PIN_6 | GPIO_PIN_8; + GPIO_InitDef.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitDef.Pull = GPIO_NOPULL; + GPIO_InitDef.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitDef); + + GPIO_InitDef.Pin = GPIO_PIN_0; + HAL_GPIO_Init(GPIOE, &GPIO_InitDef); + + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, GPIO_PIN_SET); +} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h index 1690d9e13f0..d2c2320ba5b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h index 72c046868c3..fdf2904ada3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -198,10 +210,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h index d018a67cea8..a1a4d9c699d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h @@ -60,10 +60,6 @@ typedef enum { DMA_2 = (int)DMA2_BASE } DMAName; -#define STDIO_UART_TX PC_10 -#define STDIO_UART_RX PC_11 -#define STDIO_UART UART_4 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h index c311a7b2bec..0435b5d8752 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h @@ -154,6 +154,18 @@ typedef enum { D14 = PC_12, D15 = PB_10, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PC_10, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PC_11, +#endif + // Generic signals namings LED1 = PD_10, LED2 = LED1, @@ -163,10 +175,10 @@ typedef enum { USER_BUTTON = PD_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PC_10, - SERIAL_RX = PC_11, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h index 46e9b94e288..0382c324eaa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h index b1a0b6ca2fe..c496f8b2100 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h index 52458601020..0382c324eaa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h index 0bb0d934330..2a107f9c0ff 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h @@ -190,6 +190,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -199,10 +211,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = SERIAL_TX, // Virtual Com Port - USBRX = SERIAL_RX, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h index 614256717e8..210319584fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PB_10 -#define STDIO_UART_RX PB_11 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h index 5d9786a21b7..1a73dbc2e2a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h @@ -237,6 +237,17 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PB_10, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_11, +#endif // Generic signals namings LED1 = PG_6, @@ -248,10 +259,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PB_10, - SERIAL_RX = PB_11, - USBTX = PB_10, - USBRX = PB_11, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F4/can_device.h b/targets/TARGET_STM/TARGET_STM32F4/can_device.h index 16377c24c9f..81485b0ef72 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/can_device.h @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#if defined(CAN3_BASE) && defined(CAN_3) +#if defined(CAN3_BASE) #define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index 02a3811ccd4..09e326fac7c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,241 +28,26 @@ ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" - #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" - -#define UART_NUM (10) -static uint32_t serial_irq_ids[UART_NUM] = {0}; -UART_HandleTypeDef uart_handlers[UART_NUM]; - -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - switch (obj_s->uart) { - case UART_1: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - break; - - case UART_2: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - break; -#if defined(USART3_BASE) - case UART_3: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - break; -#endif -#if defined(USART6_BASE) - case UART_6: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - break; -#endif -#if defined(UART7_BASE) - case UART_7: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_ENABLE(); - obj_s->index = 6; - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_ENABLE(); - obj_s->index = 7; - break; -#endif -#if defined(UART9_BASE) - case UART_9: - __HAL_RCC_UART9_FORCE_RESET(); - __HAL_RCC_UART9_RELEASE_RESET(); - __HAL_RCC_UART9_CLK_ENABLE(); - obj_s->index = 8; - break; -#endif -#if defined(UART10_BASE) - case UART_10: - __HAL_RCC_UART10_FORCE_RESET(); - __HAL_RCC_UART10_RELEASE_RESET(); - __HAL_RCC_UART10_CLK_ENABLE(); - obj_s->index = 9; - break; -#endif - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} +#include "serial_api_hal.h" -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - switch (obj_s->index) { - case 0: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - break; - case 1: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - break; -#if defined(USART3_BASE) - case 2: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - break; +#if defined (TARGET_STM32F401xC) || defined (TARGET_STM32F401xE) || defined (TARGET_STM32F410xB) || defined (TARGET_STM32F411xE) + #define UART_NUM (3) +#elif defined (TARGET_STM32F412xG) + #define UART_NUM (4) +#elif defined (TARGET_STM32F407xG) || defined (TARGET_STM32F446xE) + #define UART_NUM (6) +#elif defined (TARGET_STM32F429xI) || defined (TARGET_STM32F439xI) || defined (TARGET_STM32F437xG) || defined (TARGET_STM32F469xI) + #define UART_NUM (8) +#else + #define UART_NUM (10) // max value // TARGET_STM32F413xH #endif -#if defined(UART4_BASE) - case 3: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_DISABLE(); - break; -#endif -#if defined(UART5_BASE) - case 4: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_DISABLE(); - break; -#endif -#if defined(USART6_BASE) - case 5: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_DISABLE(); - break; -#endif -#if defined(UART7_BASE) - case 6: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_DISABLE(); - break; -#endif -#if defined(UART8_BASE) - case 7: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_DISABLE(); - break; -#endif -#if defined(UART9_BASE) - case 8: - __HAL_RCC_UART9_FORCE_RESET(); - __HAL_RCC_UART9_RELEASE_RESET(); - __HAL_RCC_UART9_CLK_DISABLE(); - break; -#endif -#if defined(UART10_BASE) - case 9: - __HAL_RCC_UART10_FORCE_RESET(); - __HAL_RCC_UART10_RELEASE_RESET(); - __HAL_RCC_UART10_CLK_DISABLE(); - break; -#endif - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - serial_irq_ids[obj_s->index] = 0; -} +uint32_t serial_irq_ids[UART_NUM] = {0}; +UART_HandleTypeDef uart_handlers[UART_NUM]; -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} +static uart_irq_handler irq_handler; /****************************************************************************** * INTERRUPTS HANDLING @@ -927,7 +712,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -986,6 +771,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h index 9b1a41f133b..0c00d43bf56 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PB_7 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h index 8209a21c191..b096114d9df 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h @@ -246,6 +246,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_7, +#endif + // Generic signals namings LED1 = PI_1, // LD1 = GREEN LED2 = PI_1, @@ -254,10 +266,10 @@ typedef enum { USER_BUTTON = PI_11, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, // Virtual Com Port - SERIAL_RX = PB_7, // Virtual Com Port - USBTX = PA_9, // Virtual Com Port - USBRX = PB_7, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h index 6a73f9ce763..66fc3645d5a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h index 9ef300297c2..36aa261a229 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -197,10 +209,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h index 6a73f9ce763..66fc3645d5a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h index 9ef300297c2..36aa261a229 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -197,10 +209,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h index fc1991862df..2383be6c211 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h index 9ef300297c2..36aa261a229 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -197,10 +209,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h index 0dde5d66edf..2383be6c211 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, @@ -94,7 +90,8 @@ typedef enum { typedef enum { CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE + CAN_2 = (int)CAN2_BASE, + CAN_3 = (int)CAN3_BASE } CANName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h index db69e9cdca9..b13a5687dae 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h @@ -246,6 +246,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PJ_13, // LD1 = RED LED2 = PJ_5, // LD2 = GREEN @@ -254,10 +266,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, // Virtual Com Port - SERIAL_RX = PA_10, // Virtual Com Port - USBTX = PA_9, // Virtual Com Port - USBRX = PA_10, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/can_device.h b/targets/TARGET_STM/TARGET_STM32F7/can_device.h index 0581da55843..729b36177a0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F7/can_device.h @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#if defined(CAN3_BASE) && defined(CAN_3) +#if defined(CAN3_BASE) #define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c index b211bf12d79..cef0123d574 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c @@ -717,6 +717,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; /* Set frame size */ heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* Point to next descriptor */ @@ -746,6 +748,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); } + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* point to next descriptor */ @@ -753,6 +757,9 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL } } + /* Ensure all descriptors are written to RAM before checking transmitter status */ + __DMB(); + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c index a4bece18154..9723a8a526f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,208 +27,17 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" #define UART_NUM (8) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - switch (obj_s->uart) { - case UART_1: - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - break; - - case UART_2: - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - break; -#if defined(USART3_BASE) - case UART_3: - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - break; -#endif - case UART_6: - __HAL_RCC_USART6_FORCE_RESET(); - __HAL_RCC_USART6_RELEASE_RESET(); - __HAL_RCC_USART6_CLK_ENABLE(); - obj_s->index = 5; - break; -#if defined(UART7_BASE) - case UART_7: - __HAL_RCC_UART7_FORCE_RESET(); - __HAL_RCC_UART7_RELEASE_RESET(); - __HAL_RCC_UART7_CLK_ENABLE(); - obj_s->index = 6; - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __HAL_RCC_UART8_FORCE_RESET(); - __HAL_RCC_UART8_RELEASE_RESET(); - __HAL_RCC_UART8_CLK_ENABLE(); - obj_s->index = 7; - break; -#endif - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - switch (obj_s->uart) { - case UART_1: - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - break; - case UART_2: - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - break; -#if defined(USART3_BASE) - case UART_3: - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - break; -#endif -#if defined(UART4_BASE) - case UART_4: - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - break; -#endif -#if defined(UART5_BASE) - case UART_5: - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - break; -#endif - case UART_6: - __USART6_FORCE_RESET(); - __USART6_RELEASE_RESET(); - __USART6_CLK_DISABLE(); - break; -#if defined(UART7_BASE) - case UART_7: - __UART7_FORCE_RESET(); - __UART7_RELEASE_RESET(); - __UART7_CLK_DISABLE(); - break; -#endif -#if defined(UART8_BASE) - case UART_8: - __UART8_FORCE_RESET(); - __UART8_RELEASE_RESET(); - __UART8_CLK_DISABLE(); - break; -#endif - } - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -854,7 +663,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -913,6 +722,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h index 087804bb409..79e68013661 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h index b037f504203..8d94482bf20 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h @@ -121,16 +121,28 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PB_5, // Green LED2 = PA_5, // Red LED3 = PB_6, // Blue LED4 = PB_7, // Red USER_BUTTON = PB_2, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h index 4978a8872ea..52829dbb0ed 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h @@ -45,10 +45,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h index ca509321045..4b36ff0e1f6 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h @@ -109,15 +109,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h index b2e9f9f4953..0b6d2595aaf 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h @@ -45,10 +45,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h index 8302724210b..76e1367ad2e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h @@ -105,15 +105,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h index d2038526218..7b21915ecaf 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h index e78f283d6bb..8f1f4cab851 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h index f6add44db2f..c0393f75eec 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h index d72a5b19e33..29a4c0ae3fb 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h @@ -110,6 +110,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PB_4, LED2 = PA_5, @@ -118,10 +130,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h index 0d54dc17618..c0393f75eec 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h index e78f283d6bb..8f1f4cab851 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c index 74107fd42fb..33123140ede 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,171 +27,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" -#include "mbed_error.h" +#include "serial_api_hal.h" -#define UART_NUM (5) +#if defined (TARGET_STM32L011K4) || defined (TARGET_STM32L031K6) + #define UART_NUM (2) +#elif defined (TARGET_STM32L053x8) + #define UART_NUM (3) +#else + #define UART_NUM (5) +#endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable UART clock -#if defined(USART1_BASE) - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } -#endif - - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_ENABLE(); - obj_s->index = 2; - } - -#if defined(USART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif - -#if defined(USART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock -#if defined(USART1_BASE) - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } -#endif - - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } - - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_DISABLE(); - } - -#if defined(USART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_USART4_FORCE_RESET(); - __HAL_RCC_USART4_RELEASE_RESET(); - __HAL_RCC_USART4_CLK_DISABLE(); - } -#endif - -#if defined(USART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_USART5_FORCE_RESET(); - __HAL_RCC_USART5_RELEASE_RESET(); - __HAL_RCC_USART5_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -761,7 +614,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -820,6 +673,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h index cb931d9cfb0..b627a8fc10e 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h index 7949eb0588a..7cf0167b21a 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h @@ -122,16 +122,28 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PB_1, LED2 = PC_3, LED3 = PB_10, LED4 = PB_10, //USER_BUTTON = PC_13, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h index 22f96fb3dd1..116fcec4f54 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h index 3ede104dce8..e03dd6e4c31 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -130,10 +142,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c index bcf53156b05..797979dd894 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,160 +27,18 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" +#include "serial_api_hal.h" #define UART_NUM (5) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __UART4_FORCE_RESET(); - __UART4_RELEASE_RESET(); - __UART4_CLK_DISABLE(); - } -#endif -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __UART5_FORCE_RESET(); - __UART5_RELEASE_RESET(); - __UART5_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -752,7 +610,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -811,6 +669,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h index f5ee2b01aef..4c8d454ccca 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_3 = (int)SPI3_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h index f0f0f79cac6..4f91b2a7f25 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h @@ -109,15 +109,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c index a1ca68c41cc..59bc3ee8e4f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c @@ -110,7 +110,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct index 9da54cc7c7e..53e420abbe4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2015, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + ; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) -LR_IROM1 0x08000000 0x40000 { ; load region size_region +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - ER_IROM1 0x08000000 0x40000 { ; load address = execution address + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct index 9da54cc7c7e..53e420abbe4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2015, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + ; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) -LR_IROM1 0x08000000 0x40000 { ; load region size_region +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - ER_IROM1 0x08000000 0x40000 { ; load address = execution address + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld index 04dcddcecea..6bdf1dfc43c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld @@ -1,7 +1,15 @@ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 256k +#endif + /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE SRAM1 (rwx) : ORIGIN = 0x20000188, LENGTH = 64k - 0x188 } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf index 9c478c51e2e..061e6768451 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf @@ -1,9 +1,12 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; } + /* [ROM = 256kb = 0x40000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0803FFFF; +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -/* [RAM = 48kb + 16kb = 0xC000] */ +/* [RAM = 48kb + 16kb = 0x10000] */ /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h index 984f5abf524..2ed33835948 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h @@ -2,14 +2,12 @@ ****************************************************************************** * @file stm32l432xx.h * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention @@ -321,7 +319,7 @@ typedef struct /** * @brief Clock Recovery System */ -typedef struct +typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ @@ -574,7 +572,7 @@ typedef struct uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ } PWR_TypeDef; @@ -741,12 +739,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; @@ -865,42 +861,42 @@ typedef struct uint16_t RESERVED5; /*!< Reserved, 0x2A */ } USART_TypeDef; -/** +/** * @brief Universal Serial Bus Full Speed Device */ - + typedef struct { - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t RESERVEDC; /*!< Reserved */ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ - __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t RESERVEDD; /*!< Reserved */ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ - __IO uint16_t RESERVEDE; /*!< Reserved */ + __IO uint16_t RESERVEDE; /*!< Reserved */ } USB_TypeDef; @@ -933,7 +929,7 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ @@ -941,7 +937,6 @@ typedef struct #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ @@ -1068,7 +1063,7 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) +//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) @@ -1165,72 +1160,72 @@ typedef struct /* Note: No specific macro feature on this device */ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ @@ -1248,56 +1243,56 @@ typedef struct #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ -#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ -#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ -#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ @@ -1305,53 +1300,53 @@ typedef struct #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ @@ -1360,26 +1355,26 @@ typedef struct #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ -#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ -#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -1387,78 +1382,78 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ @@ -1466,63 +1461,63 @@ typedef struct #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ @@ -1530,7 +1525,7 @@ typedef struct #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ @@ -1546,7 +1541,7 @@ typedef struct #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ @@ -1563,7 +1558,7 @@ typedef struct #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ @@ -1575,7 +1570,7 @@ typedef struct #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ -#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ @@ -1588,7 +1583,7 @@ typedef struct #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ @@ -1600,7 +1595,7 @@ typedef struct #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ -#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ @@ -1613,7 +1608,7 @@ typedef struct #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -1621,7 +1616,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -1630,7 +1625,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -1639,7 +1634,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -1648,7 +1643,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -1658,7 +1653,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -1667,7 +1662,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -1676,7 +1671,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -1685,7 +1680,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -1694,7 +1689,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -1704,7 +1699,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -1713,7 +1708,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -1722,7 +1717,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -1731,7 +1726,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -1740,7 +1735,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -1750,7 +1745,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -1759,7 +1754,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -1769,7 +1764,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ @@ -1790,13 +1785,13 @@ typedef struct #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -1804,13 +1799,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Pos (6U) #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Pos (8U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ @@ -1819,7 +1814,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Pos (14U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ @@ -1828,7 +1823,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Pos (20U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ @@ -1837,7 +1832,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Pos (26U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ @@ -1847,7 +1842,7 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ @@ -1863,7 +1858,7 @@ typedef struct #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ -#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ @@ -1872,12 +1867,12 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ @@ -1893,7 +1888,7 @@ typedef struct #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ -#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ @@ -1902,12 +1897,12 @@ typedef struct #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ @@ -1923,7 +1918,7 @@ typedef struct #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ -#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ @@ -1932,12 +1927,12 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ @@ -1953,7 +1948,7 @@ typedef struct #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ -#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ @@ -1962,12 +1957,12 @@ typedef struct #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -1988,7 +1983,7 @@ typedef struct #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -2009,7 +2004,7 @@ typedef struct #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -2030,7 +2025,7 @@ typedef struct #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -2051,7 +2046,7 @@ typedef struct #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -2075,7 +2070,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -2099,7 +2094,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ @@ -2123,7 +2118,7 @@ typedef struct #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ @@ -2134,7 +2129,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ @@ -2147,13 +2142,13 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -2161,13 +2156,13 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ @@ -2178,3475 +2173,3475 @@ typedef struct /******************************************************************************/ /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI()==0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + } + + HAL_RCCEx_DisableLSECSS(); + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S new file mode 100644 index 00000000000..895d8e662b9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S @@ -0,0 +1,378 @@ +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l432xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x20010000 ; Top of RAM + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x0F800 ; 62KB (64KB, -2*1KB for main thread and scheduler) + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +SDMMC1_IRQHandler +SPI3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +USB_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct new file mode 100644 index 00000000000..53e420abbe4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct @@ -0,0 +1,53 @@ +#! armcc -E +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + +; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188) { + .ANY (+RW +ZI) + } + +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S new file mode 100644 index 00000000000..e8397decd92 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S @@ -0,0 +1,361 @@ +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l432xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + +__initial_sp EQU 0x20010000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +SDMMC1_IRQHandler +SPI3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +USB_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct new file mode 100644 index 00000000000..53e420abbe4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct @@ -0,0 +1,53 @@ +#! armcc -E +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + +; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188) { + .ANY (+RW +ZI) + } + +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld new file mode 100644 index 00000000000..6bdf1dfc43c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld @@ -0,0 +1,161 @@ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 256k +#endif + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + SRAM1 (rwx) : ORIGIN = 0x20000188, LENGTH = 64k - 0x188 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > SRAM1 + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > SRAM1 + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > SRAM1 + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM1 + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S new file mode 100644 index 00000000000..df1beb6f779 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file startup_stm32l432xx.s + * @author MCD Application Team + * @version V1.1.1 + * @date 29-April-2016 + * @brief STM32L432xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SDMMC1_IRQHandler + .word 0 + .word SPI3_IRQHandler + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word USB_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word 0 + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word LCD_IRQHandler + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S new file mode 100644 index 00000000000..8688b7e8a7f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S @@ -0,0 +1,563 @@ +;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l432xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L432xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU interrupt + DCD CRS_IRQHandler ; CRS interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf new file mode 100644 index 00000000000..061e6768451 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf @@ -0,0 +1,33 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; } + +/* [ROM = 256kb = 0x40000] */ +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; + +/* [RAM = 48kb + 16kb = 0x10000] */ +/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __region_SRAM1_start__ = 0x20000188; +define symbol __region_SRAM1_end__ = 0x2000FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; + +define symbol __size_cstack__ = 0x2000; +define symbol __size_heap__ = 0x4000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in SRAM1_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h new file mode 100644 index 00000000000..41a1233f3b7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h similarity index 80% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h index aa874239099..49f64adf45c 100644 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h @@ -1,7 +1,6 @@ /* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2015 ARM Limited. All rights reserved. + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -12,7 +11,7 @@ * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors + * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * @@ -32,17 +31,10 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187 +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#define NVIC_NUM_VECTORS 98 +#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE // Vectors positioned at start of SRAM1 #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h new file mode 100644 index 00000000000..934e8ed9d23 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l4xx.h" +#include "stm32l4xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() + +#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h new file mode 100644 index 00000000000..a26a4b0e50f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h @@ -0,0 +1,15962 @@ +/** + ****************************************************************************** + * @file stm32l433xx.h + * @author MCD Application Team + * @brief CMSIS STM32L433xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l433xx + * @{ + */ + +#ifndef __STM32L433xx_H +#define __STM32L433xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + USB_IRQn = 67, /*!< USB event Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ + SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + LCD_IRQn = 78, /*!< LCD global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + CRS_IRQn = 82 /*!< CRS global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ +} FLASH_TypeDef; + + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ +#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ +#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ +#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */ +#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) + + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) + + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) + + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t)0xE0042000U) + + +#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ +#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC1_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) + + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) + */ +/* Note: No specific macro feature on this device */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx + * @{ + */ + +#ifndef __STM32L4xx_H +#define __STM32L4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L4) +#define STM32L4 +#endif /* STM32L4 */ + +/* Uncomment the line below according to the target STM32L4 device used in your + application + */ + +#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ + !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ + !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ + !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ + !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) + /* #define STM32L431xx */ /*!< STM32L431xx Devices */ + /* #define STM32L432xx */ /*!< STM32L432xx Devices */ +#define STM32L433xx /*!< STM32L433xx Devices */ + /* #define STM32L442xx */ /*!< STM32L442xx Devices */ + /* #define STM32L443xx */ /*!< STM32L443xx Devices */ + /* #define STM32L451xx */ /*!< STM32L451xx Devices */ + /* #define STM32L452xx */ /*!< STM32L452xx Devices */ + /* #define STM32L462xx */ /*!< STM32L462xx Devices */ + /* #define STM32L471xx */ /*!< STM32L471xx Devices */ + /* #define STM32L475xx */ /*!< STM32L475xx Devices */ + /* #define STM32L476xx */ /*!< STM32L476xx Devices */ + /* #define STM32L485xx */ /*!< STM32L485xx Devices */ + /* #define STM32L486xx */ /*!< STM32L486xx Devices */ + /* #define STM32L496xx */ /*!< STM32L496xx Devices */ + /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ + /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ + /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ + /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ + /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ + /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ + /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L4_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L431xx) + #include "stm32l431xx.h" +#elif defined(STM32L432xx) + #include "stm32l432xx.h" +#elif defined(STM32L433xx) + #include "stm32l433xx.h" +#elif defined(STM32L442xx) + #include "stm32l442xx.h" +#elif defined(STM32L443xx) + #include "stm32l443xx.h" +#elif defined(STM32L451xx) + #include "stm32l451xx.h" +#elif defined(STM32L452xx) + #include "stm32l452xx.h" +#elif defined(STM32L462xx) + #include "stm32l462xx.h" +#elif defined(STM32L471xx) + #include "stm32l471xx.h" +#elif defined(STM32L475xx) + #include "stm32l475xx.h" +#elif defined(STM32L476xx) + #include "stm32l476xx.h" +#elif defined(STM32L485xx) + #include "stm32l485xx.h" +#elif defined(STM32L486xx) + #include "stm32l486xx.h" +#elif defined(STM32L496xx) + #include "stm32l496xx.h" +#elif defined(STM32L4A6xx) + #include "stm32l4a6xx.h" +#elif defined(STM32L4R5xx) + #include "stm32l4r5xx.h" +#elif defined(STM32L4R7xx) + #include "stm32l4r7xx.h" +#elif defined(STM32L4R9xx) + #include "stm32l4r9xx.h" +#elif defined(STM32L4S5xx) + #include "stm32l4s5xx.h" +#elif defined(STM32L4S7xx) + #include "stm32l4s7xx.h" +#elif defined(STM32L4S9xx) + #include "stm32l4s9xx.h" +#else + #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h new file mode 100644 index 00000000000..4954d5c5795 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L4XX_H +#define __SYSTEM_STM32L4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L4xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h new file mode 100644 index 00000000000..ece5f1679fa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct trng_s { + RNG_HandleTypeDef handle; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h index 77a1a05d9b4..2a66882a1c0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PB_6 -#define STDIO_UART_RX PB_7 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h index 9c2ea68f506..42a23b39400 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h @@ -205,6 +205,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PB_6, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_7, +#endif + // Generic signals namings LED1 = D13, // Green LED (LD1) LED2 = PB_14, // Green LED (LD2) @@ -216,10 +228,10 @@ typedef enum { BUTTON3 = USER_BUTTON, BUTTON4 = USER_BUTTON, BUTTON5 = USER_BUTTON, - SERIAL_TX = PB_6, - SERIAL_RX = PB_7, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h index 834eb2d53f5..8b3f1dee446 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l475xx.h * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 * @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File. * * This file contains: @@ -502,7 +500,7 @@ typedef struct __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ - uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */ __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ @@ -849,12 +847,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; @@ -1005,7 +1001,7 @@ typedef struct __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; -/** +/** * @brief USB_OTG_Core_register */ typedef struct @@ -1029,7 +1025,7 @@ typedef struct __IO uint32_t GHWCFG1; /* User HW config1 044h*/ __IO uint32_t GHWCFG2; /* User HW config2 048h*/ __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ + uint32_t Reserved6; /* Reserved 050h*/ __IO uint32_t GLPMCFG; /* LPM Register 054h*/ __IO uint32_t GPWRDN; /* Power Down Register 058h*/ __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ @@ -1039,10 +1035,10 @@ typedef struct __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; -/** +/** * @brief USB_OTG_device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /* dev Configuration Register 800h*/ __IO uint32_t DCTL; /* dev Control Register 804h*/ @@ -1059,17 +1055,17 @@ typedef struct __IO uint32_t DTHRCTL; /* dev thr 830h*/ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ uint32_t Reserved40; /* dedicated EP mask 840h*/ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; -/** +/** * @brief USB_OTG_IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ @@ -1081,10 +1077,10 @@ typedef struct uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ } USB_OTG_INEndpointTypeDef; -/** +/** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ @@ -1095,10 +1091,10 @@ typedef struct uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ } USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief USB_OTG_Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /* Host Configuration Register 400h*/ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ @@ -1109,7 +1105,7 @@ typedef struct __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ } USB_OTG_HostTypeDef; -/** +/** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct @@ -1140,7 +1136,6 @@ typedef struct #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ @@ -1472,72 +1467,72 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ @@ -1555,56 +1550,56 @@ typedef struct #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ -#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ -#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ -#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ @@ -1612,53 +1607,53 @@ typedef struct #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ @@ -1667,26 +1662,26 @@ typedef struct #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ -#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ -#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -1694,78 +1689,78 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ @@ -1773,63 +1768,63 @@ typedef struct #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ @@ -1837,7 +1832,7 @@ typedef struct #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ @@ -1853,7 +1848,7 @@ typedef struct #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ @@ -1870,7 +1865,7 @@ typedef struct #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ @@ -1882,7 +1877,7 @@ typedef struct #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ -#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ @@ -1895,7 +1890,7 @@ typedef struct #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ @@ -1907,7 +1902,7 @@ typedef struct #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ -#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ @@ -1920,7 +1915,7 @@ typedef struct #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -1928,7 +1923,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -1937,7 +1932,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -1946,7 +1941,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -1955,7 +1950,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -1965,7 +1960,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -1974,7 +1969,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -1983,7 +1978,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -1992,7 +1987,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -2001,7 +1996,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -2011,7 +2006,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -2020,7 +2015,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -2029,7 +2024,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -2038,7 +2033,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -2047,7 +2042,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -2057,7 +2052,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -2066,7 +2061,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -2076,7 +2071,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ @@ -2097,13 +2092,13 @@ typedef struct #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -2111,13 +2106,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Pos (6U) #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Pos (8U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ @@ -2126,7 +2121,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Pos (14U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ @@ -2135,7 +2130,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Pos (20U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ @@ -2144,7 +2139,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Pos (26U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ @@ -2154,7 +2149,7 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ @@ -2170,7 +2165,7 @@ typedef struct #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ -#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ @@ -2179,12 +2174,12 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ @@ -2200,7 +2195,7 @@ typedef struct #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ -#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ @@ -2209,12 +2204,12 @@ typedef struct #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ @@ -2230,7 +2225,7 @@ typedef struct #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ -#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ @@ -2239,12 +2234,12 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ @@ -2260,7 +2255,7 @@ typedef struct #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ -#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ @@ -2269,12 +2264,12 @@ typedef struct #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -2295,7 +2290,7 @@ typedef struct #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -2316,7 +2311,7 @@ typedef struct #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -2337,7 +2332,7 @@ typedef struct #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -2358,7 +2353,7 @@ typedef struct #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -2382,7 +2377,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -2406,7 +2401,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ @@ -2430,7 +2425,7 @@ typedef struct #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ @@ -2441,7 +2436,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ @@ -2454,76 +2449,76 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Pos (0U) #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Pos (1U) #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Pos (2U) #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Pos (3U) #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Pos (4U) #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Pos (5U) #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Pos (6U) #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Pos (7U) #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Pos (8U) #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Pos (9U) #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Pos (10U) #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Pos (16U) #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Pos (17U) #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Pos (18U) #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Pos (19U) #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Pos (20U) #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Pos (21U) #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Pos (22U) #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Pos (23U) #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Pos (24U) #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Pos (25U) #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Pos (26U) #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ @@ -2532,7 +2527,7 @@ typedef struct #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ -#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ @@ -2540,23 +2535,23 @@ typedef struct #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ -#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Pos (13U) #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ -#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Pos (14U) #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ -#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -2564,18 +2559,18 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Pos (0U) #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ @@ -2595,7 +2590,7 @@ typedef struct #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ -#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Pos (16U) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ @@ -2622,3475 +2617,3475 @@ typedef struct /******************************************************************************/ /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! -Release Notes for STM32L4xx HAL Drivers - -
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Release -Notes for STM32L4xx HAL Drivers

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Copyright -2017 STMicroelectronics

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Update History

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V1.7.1 -/ 21-April-2017

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Main -Changes

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  • Maintenance Release of HAL and Low Layer drivers
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HAL Drivers changes

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  • HAL generic driver
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() APIs
  • HAL DAC driver
    • Fix Sample & Hold configuration in case of multi-channel
  • HAL HASH driver
    • Fix to ensure proper DMA-based HASH processing suspension/resumption
  • HAL PCD driver
    • Fix USB PCD lock/unlock and flush TX fifo during device reset
  • HAL RTC driver
    • Add wait for synchronization in HAL_RTC_Init() to insure RTC time initialization 

LL Drivers changes

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  • LL ADC
    • Fix legacy APIs LL_ADC_REG_SetTrigSource() and LL_ADC_INJ_SetTrigSource()
  • LL DMA 
    • Write only operation on IFCR register

V1.7.0 -/ 17-February-2017

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Main -Changes

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  • Release of HAL and Low Layer drivers to add support of STM32L496xx/STM32L4A6xx devices
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  • New DCMI, DMA2D, HASH peripherals supported in new HAL DCMI, HAL & LL DMA2D and HAL HASH drivers
  • New CAN2 instance supported in HAL CAN
  • Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) 

   

HAL Drivers changes

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  • HAL DCMI driver (NEW): stm32l4xx_hal_dcmi.h/.c files
  • HAL DMA2D driver (NEW): stm32l4xx_hal_dma2d.h/.c files
  • HAL HASH driver (NEW): stm32l4xx_hal_hash.h/.c and extension stm32l4xx_hal_hash_ex.h/.c files
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer -to the following examples in STM32CubeL4 firmware package V1.7.0 to -identify the changes: BSP example and USB_Device/MSC_Standalone -application
  • HAL generic update
    • stm32l4xx_hal_conf_template.h updated for new HAL DCMI, HAL DMA2D and HAL HASH
      • #define HAL_DCMI_MODULE_ENABLED
      • #define HAL_DMA2D_MODULE_ENABLED
      • HAL_HASH_MODULE_ENABLED
    • HAL_Delay() updated to guarantee minimum delay
  • HAL CAN driver
    • Add support of CAN2 instance
  • HAL GPIO driver
    • Add support of GPIOI port and STM32L496xx/STM32L4A6xx alternate functions
  • HAL PWR driver
    • Add support of GPIOI port pull-up/pull-down state in Standby and Shutdown modes
  • HAL QSPI driver
    • Fix QSPI_HandleTypeDef structure to handle data size as uint32_t
  • HAL RCC driver
    • Add new macros for new peripherals clock and reset for CAN2, DCMI, DMA2D, GPIOI and HASH
    • Fix HAL_RCCEx_GetPeriphCLKFreq() to compute peripheral frequencies from MSI frequency
    • Fix HAL_RCCEx_GetPeriphCLKFreq() to compute DFSDM1 frequency from PCLK2 frequency
    • Rename some peripheral clock sources to specify the corresponding APB clock:
      • RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2
      • RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1
      • RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1
  • HAL RTC driver
    • Fix wrong clear of time and date registers in HAL_RTCEx_TamperTimeStampIRQHandler()
  • HAL SPI driver
    • Add internal timeout to exit HAL_SPI_Abort() and HAL_SPI_Abort_IT() 
  • HAL TIM driver
    • Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()
  • HAL SWPMI driver
    • Fix peripheral clock management sequence in HAL_SWPMI_Init()

LL Drivers changes

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  • LL DMA2D driver (NEW)
  • LL BUS 
    • Add management of new peripherals: CAN2, DCMI, DMA2D, GPIOI and HASH
  • LL PWR
    • For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()
  • LL RCC
    • Fix LL_RCC_GetDFSDMClockFreq() to compute frequency from PCLK2 frequency
  • LL SDMMC
    • Add new internal functions after HAL SD rework
  • LL TIM
    • Fix definition of TIM break input polarity (fix values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)

V1.6.0 -/ 28-October-2016

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Main -Changes

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  • Release of HAL and Low Layer drivers to add support of STM32L451xx/STM32L452xx/STM32L462xx devices
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  • Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm) 

   

HAL Drivers changes

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  • HAL CRYP driver
    • HAL CRYP exported macros alignment with other STM32 series to use CRYP handle address as parameter in:
      • __HAL_CRYP_ENABLE(), __HAL_CRYP_DISABLE(), __HAL_CRYP_SET_OPERATINGMODE(), -__HAL_CRYP_SET_CHAININGMODE(), __HAL_CRYP_GET_FLAG(), __HAL_CRYP_CLEAR_FLAG(), -__HAL_CRYP_GET_IT_SOURCE(), __HAL_CRYP_GET_IT(), __HAL_CRYP_CLEAR_IT(), -__HAL_CRYP_ENABLE_IT() and __HAL_CRYP_DISABLE_IT()
  • HAL FLASH driver
    • Temporary data cache deactivation on 
      • Flash programming in HAL_FLASH_Program() and HAL_FLASH_Program_IT()
      • Flash erase in HAL_FLASHEx_Erase() and HAL_FLASHEx_Erase_IT()
    • To insure LSB/MSB address order in C compiler assembly output, split 64-bit programming in 2 double-word write operations
  • HAL I2C driver
    • Fix -to reset HAL I2C handle LISTEN state option in transfer direction -change with HAL_I2C_Slave_Sequential_Transmit_IT() and -HAL_I2C_Slave_Sequential_Receive_IT() 
  • HAL SMBUS driver
    • Add -support of Zone read/write feature thanks to new XferOptions parameter -values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, -SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and -SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC that may be used in -HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Master_Receive_IT(), -HAL_SMBUS_Slave_Transmit_IT() and HAL_SMBUS_Slave_Receive_IT()
  • HAL RTC driver
    • Fix -race conditions on EXTI flags clearing in HAL_RTC_AlarmIRQHandler(), -HAL_RTCEx_TamperTimeStampIRQHandler() and -HAL_RTCEx_WakeUpTimerIRQHandler()
  • Fix CodeSonar warnings in 
    • HAL ADC, HAL CRC, HAL CRYP, HAL I2C, HAL IRDA, HAL SMARTCARD, HAL SMBUS, HAL OPAMP, HAL RTC, HAL UART, HAL USART

   

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LL Drivers changes

  • LL I2C driver
    • Add I2C4 management in LL_I2C_DeInit()
  • LL SYSTEM driver
    • Application -shall be responsible to write the correct key sequence in SYSCFG_SKR -register prior to call LL_SYSCFG_EnableSRAM2Erase()
  • LL TIM driver
    • New APIs to insure BDTR register initialization in a single write operation 
      • LL_TIM_BDTR_StructInit()
      • LL_TIM_BDTR_Init()
  • LL UTILS driver
    • Fix LL_RCC_PLLSOURCE_HSE in LL_PLL_ConfigSystemClock_HSE()  

V1.5.2 -/ 12-September-2016

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HAL Drivers changes

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  • HAL ADC driver
    • No need to configure number of discontinuous conversions if discontinuous mode is not enabled
    • HAL_ADCEx_MultiModeConfigChannel() returns HAL_ERROR if no Slave instance defined
  • HAL DAC driver
    • Fix calibration with correct handling of DAC_SR_CAL_FLAGx bits in HAL_DACEx_SelfCalibrate()
  • HAL FLASH driver
    • Change in HAL_FLASHEx_OBGetConfig() to not return PCROP and/or WRP data if their respective areas are not defined
    • Fix -error management in HAL_FLASH_IRQHandler() to simply call -HAL_FLASH_OperationErrorCallback() instead of calling both -HAL_FLASH_EndOfOperationCallback() and HAL_FLASH_OperationErrorCallback()
  • HAL I2C driver
    • Fix wrong state check in HAL_I2C_Master_Sequential_Transmit_IT()
    • Add -new option I2C_FIRST_AND_NEXT_FRAME to manage a sequencewith start -condition, address and data to transfer without a final stop condition -allowing successive calls to HAL_I2C_Master_Sequential_Transmit_IT()
  • HAL IRDA driver
    • Add transfer abort functions and associated callbacks in interrupt mode
      • HAL_IRDA_Abort(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortReceive()
      • HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_AbortReceive_IT()
      • HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback()
    • IRQ Handler + DMA model optimizations
  • HAL RTC driver
    • Fix missing wakeup flag clear in HAL_RTCEx_SetWakeUpTimer_IT()  
  • HAL SMARTCARD driver
    • Add transfer abort functions and associated callbacks in interrupt mode
      • HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive()
      • HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()
      • HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback()
    • IRQ Handler + DMA model optimizations
  • HAL SMBUS driver
    • Fix issue on last data reception in host or device modes
  • HAL SPI driver
    • USE_SPI_CRC -compilation define added to provide the mean to optimize the HAL SPI -driver when CRC feature is not used (when CRC is used, application must be changed to set USE_SPI_CRC in stm32l4xx_hal_conf.h (see Inc\stm32l4xx_hal_conf_template.h))
    • Add transfer abort functions and associated callbacks in interrupt mode
      • HAL_SPI_Abort()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
  • HAL SWPMI driver
    • Fix SWPMI peripheral errors management in DMA (resort to HAL_DMA_Abort_IT() and DMA XferAbortCallback in HAL_SWPMI_IRQHandler())
  • HAL UART driver
    • New APIs to abort UART tranfer with associated callbacks added 
      • HAL_UART_Abort(), -HAL_UART_AbortTransmit(), HAL_UART_AbortReceive(), HAL_UART_Abort_IT(), -HAL_UART_AbortTransmit_IT(), HAL_UART_AbortReceive_IT(), -HAL_UART_AbortCpltCallback(), HAL_UART_AbortTransmitCpltCallback() and -HAL_UART_AbortReceiveCpltCallback()
  • HAL USART driver
    • New APIs to abort USART tranfer with associated callbacks added
      • HAL_USART_Abort(), HAL_USART_Abort_IT() and HAL_USART_AbortCpltCallback()

LL Drivers -changes

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  • LL COMP driver
    • Fix LL_COMP_INPUT_PLUS_IO3 definition

V1.5.1 -/ 31-May-2016

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HAL Drivers changes

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  • HAL ADC driver
    • Bypass multimode assert_param macro calls depending on configuration
  • HAL CRC driver -
    • HAL_CRC_DeInit() resets CRC_IDR -register to reset value

LL Drivers -changes

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  • LL BUS driver -
    • LL_APB1_GRP1_PERIPH_USBFS -renamed to LL_APB1_GRP1_PERIPH_USB
    -
  • LL SYSTEM driver -
    • Fix typo on -LL_DBGMCU_APB1_xxx and LL_DBGMCU_APB2_xxx
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V1.5.0 -/ 29-April-2016

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Main -Changes

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  • Maintenance Release of HAL and Low Layer drivers
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HAL Drivers changes

- - -
  • Enhance HAL delay and timebase implementation
    • Add -new driver -stm32l4xx_hal_timebase_tim_template.c which overrides the native HAL -time base functions (defined as weak) to use the TIM peripheral as time -base tick source. For more details about the usage of this driver, please refer to -HAL\HAL_TimeBase example and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0
    • HAL RCC driver
      • To -use PLLSAI1 and PLLSAI2 indidependently from main system PLL, PLLSAI1 -& PLLSAI2 initialization enriched to add PLL entry clock source and -divider M
        • RCC_PLLSAI1InitTypeDef includes PLLSAI1Source and PLLSAI1M new fields
        • RCC_PLLSAI2InitTypeDef includes PLLSAI2Source and PLLSAI2M new fields
      • Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK
      • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
        • All macros __HAL_RCC_DFSDM_xxx() renamed to __HAL_RCC_DFSDM1_xxx()
        • DfsdmClockSelection field of RCC_PeriphCLKInitTypeDef renamed to Dfsdm1ClockSelection
        • RCC_PERIPHCLK_DFSDM renamed to RCC_PERIPHCLK_DFSDM1
        • RCC_DFSDMCLKSOURCE_PCLK renamed to RCC_DFSDM1CLKSOURCE_PCLK
        • RCC_DFSDMCLKSOURCE_SYSCLK renamed to RCC_DFSDM1CLKSOURCE_SYSCLK
        • __HAL_RCC_DFSDM_CONFIG() renamed to __HAL_RCC_DFSDM1_CONFIG()
        • __HAL_RCC_GET_DFSDM_SOURCE() renamed to __HAL_RCC_GET_DFSDM1_SOURCE()
      • Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK
    • HAL I2C driver
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using -the PPP end of transfer interrupt in the DMA transfer process. This requires the following -updates on user application:
        • Configure and enable the I2Cx IRQ in HAL_I2C_MspInit() function
        • In stm32l4xx_it.c file, I2Cx_IRQHandler() function: add a -call to HAL_I2C_IRQHandler() function
    • HAL UART/USART drivers
      • IRQ Handler global optimization 
      • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
      • Polling management update:
        • The user Timeout value must be estimated for the overall process -duration
    • HAL IRDA/SMARTCARD drivers
      • Polling management update:
        • The user Timeout value must be estimated for the overall process -duration
    • HAL SPI driver
      • Add SPI error management during DMA process: this requires the following updates in the user - application:
        • Configure and enable the SPIx IRQ in - HAL_SPI_MspInit() function
        • In stm32l4xx_it.c file, SPIx_IRQHandler() - function: add a call to HAL_SPI_IRQHandler() function
        • - -Add and customize the -Error Callback API: HAL_SPI_ErrorCallback()
    • HAL QSPI driver
      • Add QSPI error management during DMA process
      • Improve the DMA transmit process by using QSPI TC interrupt instead of -waiting on TC flag under DMA ISR. 
      • These two improvements require the following updates on user -application:
        • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
        • In stm32l4xx_it.c file, QSPI_IRQHandler() function: add a -call to HAL_QSPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
      • Add the management of non-blocking transfer abort -service: HAL_QSPI_Abort_IT(). In this case the user must:
        • Add new callback HAL_QSPI_AbortCpltCallback() - to inform user at the end of abort process
        • A new value of State in -the HAL_QSPI_StateTypeDef provides the current state during the abort phase
- -
      • Polling management update:
        • The user Timeout value must be estimated for the overall process -duration
      • Fix wrong data size management in HAL_QSPI_Receive_DMA()
        • New API HAL_QSPI_SetFifoThreshold() and HAL_QSPI_GetFifoThreshold()
    • HAL IWDG driver
      • New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() -and HAL_IWDG_GetState() APIs
        • API functions are: 
          • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG -counter
          • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
        • Refer to the following example to identify the changes: IWDG_Example
    • HAL WWDG driver
      • New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() -and HAL_WWDG_GetState() APIs
        • Update HAL_WWDG_Refresh() API to remove counter parameter
        • New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt
        • API -functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), -HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()
  • HAL DMA driver
    • Global driver code optimization to reduce memory footprint 
    • New APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() to register/unregister the different possible callbacks identified by enum typedef HAL_DMA_CallbackIDTypeDef
    • New API HAL_DMA_Abort_IT() to abort DMA transfer in non-blocking mode for interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
    • Add new Error Codes: HAL_DMA_ERROR_NO_XFER and -HAL_DMA_ERROR_NOT_SUPPORTED
    • Add __HAL_DMA_GET_COUNTER() macro
  • HAL COMP driver
    • EXTI -configuration done in HAL_COMP_Init() based on TriggerMode field of -COMP_InitTypeDef structure; HAL_COMP_Start()/HAL_COMP_Stop() APIs are sufficient to start and stop comparators (HAL_COMP_Start_IT() and HAL_COMP_Stop_IT() are preserved for -legacy compatibility)
    • Add comparator startup time and scaler bridge stabilization time in HAL_COMP_Init()
    • Fix to call HAL_COMP_TriggerCallback() only once when the 2 comparators are configured in window mode
    • Inverting & Non-inverting inputs renaming (previous definitions preserved for legacy compatibility)
      • COMP_INVERTING_xxx definitions renamed to COMP_INPUT_MINUS_xxx
      • COMP_NONINVERTING_xxx definitions renamed to COMP_INPUT_PLUS_xxx
    • Blanking sources renaming to highlight Comparator & Timer instances connections (previous definitions preserved for legacy compatibility)
      • COMP_BLANKINGSRCE_TIM1OC5 renamed to COMP_BLANKINGSRC_TIM1_OC5_COMP1
      • COMP_BLANKINGSRCE_TIM2OC3 renamed to COMP_BLANKINGSRC_TIM2_OC3_COMP1
      • COMP_BLANKINGSRCE_TIM3OC3 renamed to COMP_BLANKINGSRC_TIM3_OC3_COMP1
      • COMP_BLANKINGSRCE_TIM3OC4 renamed to COMP_BLANKINGSRC_TIM3_OC4_COMP2
      • COMP_BLANKINGSRCE_TIM8OC5 renamed to COMP_BLANKINGSRC_TIM8_OC5_COMP2
      • COMP_BLANKINGSRCE_TIM15OC1 renamed to COMP_BLANKINGSRC_TIM15_OC1_COMP2
      • COMP_BLANKINGSRCE_NONE renamed to COMP_BLANKINGSRC_NONE
  • HAL CRYP driver
    • Software workaround for AES issue on GCM encryption with payload length not a multiple of 128 bits
    • Add support of payload length not multiple of 32 bits
  • HAL GPIO driver
    • Add missing GPIO_AF6_COMP1 for STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx
    • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • GPIO_AF6_DFSDM renamed to GPIO_AF6_DFSDM1
  • HAL HCD driver
    • Clear NACK flag before re-enabling the channel for new IN request
  • HAL PCD driver
    • Host mode
      • Use HCLK frequency to set TRDT value
    • Device mode
      • Force suspend and low-power mode before going to L1 state
      • Unmask Start Of Frame interrupt
  • HAL TIM driver
    • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • TIM_BREAKINPUTSOURCE_DFSDM renamed to TIM_BREAKINPUTSOURCE_DFSDM1
  • HAL SAI driver
    • Update - HAL_SAI_IRQHandler:
      • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
  • HAL SWPMI driver
    • Update initialization sequence in voltage class B

   

-

LL Drivers changes

  • LL ADC driver
    • Fix injected conversion configuration with SW start in LL_ADC_INJ_ConfigQueueContext()
  • LL BUS driver
    • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • LL_APB2_GRP1_PERIPH_DFSDM renamed to LL_APB2_GRP1_PERIPH_DFSDM1
  • LL COMP driver
    • Window mode renaming to highlight Comparator instances connection (previous definitions preserved for legacy compatibility)
      • LL_COMP_WINDOWMODE_ENABLE renamed to LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
    • Blanking sources renaming to highlight Comparator & Timer instances connections (previous definitions preserved for legacy compatibility)
      • LL_COMP_BLANKINGSRCE_TIM1OC5 renamed to LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
      • LL_COMP_BLANKINGSRCE_TIM2OC3 renamed to LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
      • LL_COMP_BLANKINGSRCE_TIM3OC3 renamed to LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
      • LL_COMP_BLANKINGSRCE_TIM3OC4 renamed to LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2
      • LL_COMP_BLANKINGSRCE_TIM8OC5 renamed to LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
      • LL_COMP_BLANKINGSRCE_TIM15OC1 renamed to LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2
  • LL I2C driver
    •  Add SMBus feature support
      •  LL_I2C_InitTypeDef structure enriched with new PeripheralMode field to indicate I2C or SMBus modes
      • New -APIs LL_I2C_EnableSMBusAlert(), LL_I2C_DisableSMBusAlert(), -LL_I2C_IsEnabledSMBusAlert(), LL_I2C_EnableSMBusPEC(), -LL_I2C_DisableSMBusPEC(), LL_I2C_IsEnabledSMBusPEC(), -LL_I2C_ConfigSMBusTimeout(), LL_I2C_EnableSMBusTimeout(), LL_I2C_DisableSMBusTimeout(), LL_I2C_IsEnabledSMBusTimeout(), LL_I2C_SetSMBusTimeoutA(), LL_I2C_GetSMBusTimeoutA(), LL_I2C_SetSMBusTimeoutAMode(), LL_I2C_GetSMBusTimeoutAMode(), LL_I2C_SetSMBusTimeoutB(), -LL_I2C_GetSMBusTimeoutB(), LL_I2C_SetSMBusTimeoutBMode(), -LL_I2C_GetSMBusTimeoutBMode(), LL_I2C_IsActiveSMBusFlag_PECERR(), LL_I2C_IsActiveSMBusFlag_TIMEOUT(), -LL_I2C_IsActiveSMBusFlag_ALERT(), LL_I2C_ClearSMBusFlag_PECERR(), -LL_I2C_ClearSMBusFlag_TIMEOUT(), LL_I2C_ClearSMBusFlag_ALERT(), -LL_I2C_EnableSMBusPECCompare(), LL_I2C_IsEnabledSMBusPECCompare() and -LL_I2C_GetSMBusPEC()
    • New APIs LL_I2C_SetMode() and LL_I2C_GetMode()
    • New APIs LL_I2C_EnableAutoEndMode(), LL_I2C_DisableAutoEndMode() and LL_I2C_IsEnabledAutoEndMode()
    • New APIs LL_I2C_EnableReloadMode(), LL_I2C_DisableReloadMode() and LL_I2C_IsEnabledReloadMode()
    • New APIs LL_I2C_EnableSlaveByteControl(), LL_I2C_DisableSlaveByteControl() and LL_I2C_IsEnabledSlaveByteControl()
    • New APIs LL_I2C_SetTransferRequest(), LL_I2C_GetTransferRequest(), LL_I2C_SetSlaveAddr() and LL_I2C_GetSlaveAdd()
    • New APIs LL_I2C_SetTransferSize() and LL_I2C_GetTransferSize()
    • New APIs LL_I2C_GenerateStopCondition(), LL_I2C_GenerateStartCondition()
    • New APIs LL_I2C_EnableAuto10BitRead(), LL_I2C_DisableAuto10BitRead() and LL_I2C_IsEnabledAuto10BitRead()
  • LL PWR driver
    •  New APIs LL_PWR_EnterLowPowerRunMode() and LL_PWR_ExitLowPowerRunMode()
  • LL RCC driver
    •  DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • LL_RCC_DFSDM_CLKSOURCE renamed to LL_RCC_DFSDM1_CLKSOURCE
      • LL_RCC_DFSDM_CLKSOURCE_PCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_PCLK
      • LL_RCC_DFSDM_CLKSOURCE_SYSCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
  • LL SYSTEM driver
    •  New API LL_FLASH_IsPrefetchEnabled()
  • LL TIM driver
    •  DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • LL_TIM_BKIN_SOURCE_DFBK renamed to LL_TIM_BKIN_SOURCE_DF1BK
    • New OCRef clear input selection definitions LL_TIM_OCREF_CLR_INT_NC and LL_TIM_OCREF_CLR_INT_ETR
    • New OCRef clear API LL_TIM_SetOCRefClearInputSource()

V1.4.0 -/ 26-February-2016

-

Main -Changes

-
  • Release of HAL and Low Layer drivers to add support of STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/ STM32L443xx devices
-
  • Low Layer driver initialization/de-initialization APIs applicable to all STM32L4xx devices
  • CRS peripheral implemented as an extension of HAL RCC (HAL_RCCEx_CRS_xxxx() APIs)
  • Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) 

   

HAL Drivers changes

-
  • HAL generic update
    • Add default HSI48_VALUE in stm32l4xx_hal_conf_template
  • HAL CRYP update
    • New error code HAL_CRYP_BUSY_ERROR to reject new request while ongoing processing
  • HAL IRDA/SMARTCARD/UART/USART update
    • Improvement of baud rate computation at initialization

   

-

LL Drivers changes

  • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
    • stm32l4xx_ll_crs.c
  • LL BUS update
    •  Add read-back register on clock enable functions to take into account any delay on bus
  • LL ADC update
    •  Trigger sources renaming:
      • LL_ADC_REG_TRIG_SW_START renamed to LL_ADC_REG_TRIG_SOFTWARE
      • LL_ADC_REG_TRIG_EXT_TIMx_CCy renamed to LL_ADC_REG_TRIG_EXT_TIMx_CHy
      • LL_ADC_INJ_TRIG_SW_START renamed to LL_ADC_INJ_TRIG_SOFTWARE
      • LL_ADC_INJ_TRIG_EXT_TIMx_CCy renamed to LL_ADC_INJ_TRIG_EXT_TIMx_CHy
    • Oversamping data shift renaming:
      • LL_ADC_OVS_DATA_SHIFT_NONE renamed to LL_ADC_OVS_SHIFT_NONE
      • LL_ADC_OVS_DATA_SHIFT_xxx renamed to LL_ADC_OVS_SHIFT_xxx
  • LL DAC update
    •  Trigger sources renaming:
      • LL_DAC_TRIGGER_SOFTWARE renamed to LL_DAC_TRIG_SOFTWARE
      • LL_DAC_TRIGGER_TIMx_TRGO renamed to LL_DAC_TRIG_EXT_TIMx_TRGO
      • LL_DAC_TRIGGER_EXT_IT9 renamed to LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL LPUART update
    •  Improvement of LPUARTDIV value in baud rate computation in __LL_LPUART_DIV() macro
  • LL USART update
    •  Improvement of USARTDIV value in baud rate computation in __LL_USART_DIV_SAMPLING8() and __LL_USART_DIV_SAMPLING16() macros

V1.3.0 -/ 29-January-2016

-

Main -Changes

-
  • New Low Layer driver initialization/de-initialization APIs
    • Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() -and more initialization APIs when applicable for peripheral PPP: -ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, -RCC, RNG, RTC, SPI, SWPMI, TIM and USART. 
    • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
      • stm32l4xx_ll_adc.c, stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c, stm32l4xx_ll_exti.c, stm32l4xx_ll_gpio.c, stm32l4xx_ll_i2c.c, stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c, stm32l4xx_ll_opamp.c, stm32l4xx_ll_pwr.c, stm32l4xx_ll_rcc.c, stm32l4xx_ll_rng.c, stm32l4xx_ll_rtc.c, stm32l4xx_ll_spi.c, stm32l4xx_ll_swpmi.c, stm32l4xx_ll_tim.c and stm32l4xx_ll_usart.c
      • stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration. 
  • Fix "parameter unused" GCC compilation warnings on __weak functions

HAL Drivers changes

-
  • HAL generic update
    • Declare uwTick as global variable to allow weak HAL_IncTick() API updates in user application 
    • Add new API HAL_SYSCFG_EnableIOAnalogSwitchBooster() and HAL_SYSCFG_DisableIOAnalogSwitchBooster()
  • HAL COMP update
    • Allow comparator lock from the reset state with HAL_COMP_Lock()
  • HAL CRYP update
    • Fix state issue to resume AES calculations
  • HAL DMA update
    • Fix state issue after DMA transfer error 
  • HAL FLASH update
    • Fix __HAL_FLASH_INSTRUCTION_CACHE_RESET() and __HAL_FLASH_DATA_CACHE_RESET() to allow multiple resets
  • HAL I2C update
    • Add support of repeated start feature with the following new APIs
      • HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Sequential_Receive_IT() and  HAL_I2C_Master_Abort_IT(), 
      • HAL_I2C_Slave_Sequential_Transmit_IT() and HAL_I2C_Slave_Sequential_Receive_IT()
      • HAL_I2C_EnableListen_IT() and HAL_I2C_DisableListen_IT()
      • New user callbacks HAL_I2C_ListenCpltCallback() and HAL_I2C_AddrCallback()
    • Fix acknowledge failure error management (STOP being automatically generated)
    • Review -state machine and provide new API  HAL_I2C_GetMode() to return -HAL_I2C_MODE_MASTER, HAL_I2C_MODE_SLAVE or HAL_I2C_MODE_NONE
  • HAL IRDA update
    • Add missing IRDA_CLEAR_IDLEF definition for IDLE flag clear with __HAL_IRDA_CLEAR_FLAG()
  • HAL SD update
    • Fix SD card capacity calculation for cards with capacity over 4GB in HAL_SD_Get_CardInfo()
  • HAL SMARTCARD update
    • Add missing SMARTCARD_STOPBITS_0_5 definition for frame with 0.5 stop bit
    • HAL SMARTCARD guardtime correction to not expect a minimum  of 12 etu
  • HAL UART update
    • Add missing UART_STOPBITS_0_5 definition for frame with 0.5 stop bit
    • RX Buffer flush request should not be called at each RXNE processing
    • Fix wrong macro used in assert_param in HAL_LIN_SendBreak()
  • HAL USART update
    • Add missing USART_STOPBITS_0_5 definition for frame with 0.5 stop bit

LL Drivers changes

-
  • LL UTILS update (user code impacted !)
    • Move the following functions declaration from stm32l4xx_ll_utils.h to stm32l4xx_ll_utils.c file
      • LL_mDelay(), LL_Init1msTick() and LL_SetSystemCoreClock()
  • LL ADC update
    •  FLAG & IT definition name change
  • LL COMP update
    •  Rename InputInverting and InputNonInverting APIs
      • LL_COMP_Set{/Get}InputNonInverting() renamed to LL_COMP_Set{/Get}InputMinus
      • LL_COMP_Set{/Get}InputInverting() renamed to LL_COMP_Set{/Get}InputPlus
    • Remove LL_COMP_SetWindowMode() and LL_COMP_GetWindowMode()
  • LL DMA update
    •  Add helper macro __LL_DMA_GET_CHANNEL_INSTANCE()
  • LL GPIO update
    • Fix definition LL_GPIO_OUTPUT_OPENDRAIN
    • Add -the explicit possible values in the API description of -LL_GPIO_GetPinMode(), LL_GPIO_GetPinOutputType(), -LL_GPIO_GetPinSpeed(), LL_GPIO_GetPinPull(), LL_GPIO_GetAFPin_0_7() and -LL_GPIO_GetAFPin_8_15()
    • Add -GPIO speed definitions LL_GPIO_SPEED_FREQ_LOW, -LL_GPIO_SPEED_FREQ_MEDIUM, LL_GPIO_SPEED_FREQ_HIGH and -LL_GPIO_SPEED_FREQ_VERY_HIGH to align with HAL GPIO
  • LL I2C update
    •  Add missing function LL_I2C_ConfigFilters() to configure noise filters
  • LL LPTIM update
    • Add missing functions
      • LL_LPTIM_IsEnabled()
      • LL_LPTIM_SetWaveform()
      • LL_LPTIM_SetPolarity()
  • LL OPAMP update
    • Rename power range APIs
      • LL_OPAMP_Get{/Set}PowerRange() renamed to LL_OPAMP_Get{/Set}CommonPowerRange()
  • LL SPI update
    • Fix LL_SPI_IsEnabled(), LL_SPI_IsEnabledCRC() and LL_SPI_IsEnabledNSSPulse()
    • Remove -LL_SPI_Set{/Get}HalfDuplexDirection() functions: this is managed with -TransferDirection parameter in LL_SPI_Set{/Get}TransferDirection()
  • LL SWPMI update
    • Add missing function LL_SWPMI_IsActivated()
  • LL TIM update
    • Add missing functions
      • LL_TIM_CC_IsEnabledChannel()
      • LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload() and LL_TIM_OC_IsEnabledClear()
      • LL_TIM_IsEnabledMasterSlaveMode()
      • LL_TIM_EnableExternalClock(), LL_TIM_DisableExternalClock() and LL_TIM_IsEnabledExternalClock()
  • LL USART update
    • Add LL_USART_STOPBITS_0_5 definition for usage in LL_USART_Set{/Get}StopBitsLength() and LL_USART_ConfigCharacter()

V1.2.0 -/ 25-November-2015

-

Main -Changes

-
  • HAL generic update
    • Reduce default HSE startup timeout value to 100ms in Inc\stm32l4xx_hal_conf_template.h file
  • HAL PWR update (User application code impacted)
    • Stop 1 with main regulator renamed into Stop 0, to be aligned with latest version of Reference Manual
    • Change HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry) into HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
      • Application code using HAL_PWREx_EnterSTOP1Mode(PWR_LOWPOWERREGULATOR_ON, STOPEntry) must be updated to use HAL_PWREx_EnterSTOP1Mode(STOPEntry)
    • Add new API HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
      • Application code using HAL_PWREx_EnterSTOP1Mode(PWR_MAINREGULATOR_ON, STOPEntry) must be updated to use HAL_PWREx_EnterSTOP0Mode(STOPEntry)
      •  
  • HAL OPAMP update
    • Provide capability to run calibration despite PGA mode by switching temporary to standalone mode
  • HAL SAI update
    • Update SAI block synchronization selection (User application code impacted)
      • Replace uncomplete SAI_SYNCHRONOUS_EXT value for with SAI_SYNCHRONOUS_EXT_SAI1 and SAI_SYNCHRONOUS_EXT_SAI2
    • Update external synchronization input selection (User application code impacted)
      • Remove useless SAI_SYNCEXT_IN_ENABLE value for SynchroExt field in SAI_InitTypeDef structure
    • Add support of 24bits configuration in PCM protocol
    • Add codec not ready interrupt management
    • Fix computation of data size, frame length, active frame length, slot size and first bit offset in I2S protocol
    • Fix mute counter setting in HAL_SAI_EnableRxMuteMode()
    • Fix -ambiguous clock strobing values: fix HAL_SAI_Init() to set correct -CKSTR bits in SAI_xCR1 according to ClockStrobing and AudioMode -parameters
    • Fill in the Fifo before enable interrupt in HAL_SAI_Transmit_IT()
    • Fix assert on active slot selection in HAL_SAI_Init()
    • Fix companding mode management in HAL_SAI_Init()
  • HAL TSC update
    • Improve IODefault state management
  • HAL NOR/HAL SRAM/FMC update
    • WriteFifo field of FMC_NORSRAM_InitTypeDef structure is not applicable on STM32L47x/STM32L48x devices
  • LL PWR update (User application code impacted)
    • LL PWR API change to add new Stop 0 mode and update Stop 1 mode definition
    • Change LL_PWR_SetPowerMode(uint32_t LowPowerMode) possible LowPowerMode values update 
      • LL_PWR_MODE_STOP1_LP_REGU renamed into LL_PWR_MODE_STOP1
        • Application code using LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1_LP_REGU) must be updated to use LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1)
      • LL_PWR_MODE_STOP1_MAIN_REGU renamed into LL_PWR_MODE_STOP0
        • Application code using LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1_MAIN_REGU) must be updated to use LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0)

V1.1.1 -/ 16-October-2015

-

Main -Changes

-
  • HAL generic update
    • Fine -tuning of Inc\stm32l4xx_hal_conf_template.h file to keep Flash prefetch -off as default system configuration (PREFETCH_ENABLE set to 0)
  • HAL TIM update
    • Removed -useless assert_param() macro check on input parameters in -HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel() and -HAL_TIM_ConfigClockSource(), 
  • LL ADC update
    • Fix LL_ADC_GetAnalogWDMonitChannels() for AWD2 and AWD3
  • LL RCC update
    • Add new API LL_RCC_LSE_DisableCSS()
  • LL UTILS update
    • Fix LL_GetPackageType()

V1.1.0 -/ 16-September-2015

-

Main -Changes

-
  • Add Low Layer drivers allowing performance and footprint optimization 
    • Low -Layer drivers APIs provide register level programming: they require -deep knowledge of peripherals described in STM32L4x6 Reference Manual
    • Low -Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, -EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, -SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, -System and Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.
  • HAL ADC update
    • Channel 5 is not usable for ADC3
  • HAL CAN update
    • Update HAL_CAN_IRQHandler() to clear ERRI bit prior to call HAL_CAN_ErrorCallback()
  • HAL COMP update
    • Update HAL_COMP_Init() for low power optimization in case of COMP_INVERTINGINPUT_VREFINT
  • HAL CRC update
    • Add new API HAL_CRYPEx_ProcessSuspend()
  • HAL DMA update
    • Update HAL_DMA_IRQHandler() to set HAL_DMA_ERROR_TE error bit in handle ErrorCode field
  • HAL FLASH update
    • Add option byte OB_USER_nRST_SHDW to be used with HAL_FLASHEx_OBProgram()
  • HAL GPIO update
    • Rename -GPIO speed definitions to GPIO_SPEED_FREQ_LOW, -GPIO_SPEED_FREQ_MEDIUM, GPIO_SPEED_FREQ_HIGH and -GPIO_SPEED_FREQ_VERY_HIGH
    • Fix macro __HAL_GPIO_EXTI_GENERATE_SWIT()
  • HAL PWR update
    • Fix HAL_PWR_DisableWakeUpPin() to clear only appropriate bits in PWR CR3 register
    • Combination -of GPIO pins possible in HAL_PWREx_EnableGPIOPullUp(), -HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown() and -HAL_PWREx_DisableGPIOPullDown()
  • HAL RCC update
    • Add -LSE Clock Security System (CSS) management with new APIs: -HAL_RCCEx_EnableLSECSS_IT(), HAL_RCCEx_LSECSS_IRQHandler() and -HAL_RCCEx_LSECSS_Callback()
    • Add RCC_MCO1SOURCE_NOCLOCK to provide capability to disable MCO output in HAL_RCC_MCOConfig()
    • Update -HAL_RCC_OscConfig() and HAL_RCCEx_PeriphCLKConfig() to keep backup -domain enabled when configuring respectively LSE and RTC clock -source
    • Update HAL_RCCEx_DisablePLLSAI1() and HAL_RCCEx_DisablePLLSAI2() to disable respectively PLLSAI1 and PLLSAI2 clock outputs
    • Update HAL_RCCEx_GetPeriphCLKFreq() to return the frequency in Hz applied to peripherals via HAL_RCCEx_PeriphCLKConfig()
    • Update HAL_RCC_DeInit() to set default MSI range
    • Remove old workaround on LSE drive medium configuration values
  • HAL SPI update
    • Fix issue to receive CRC in RX 2 lines mode 8-bit dataSize and even buffer size.
  • HAL TIM update
    • Fix macro __HAL_TIM_SET_COMPARE()
  • HAL UART update
    • Remove enable of Error interrupt in HAL_UART_Transmit_IT()

V1.0.0 -/ 26-June-2015

-

Main -Changes

-
  • First official release of STM32L4xx HAL Drivers for STM32L471xx/STM32L475xx/ STM32L476xx/ STM32L485xx and STM32L486xx devices.
-

License

-
-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
    -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
    2. -
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
    3. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
    -
    4. -
-       -from this software without specific prior written permission.
-
-THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
-
- -
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h index 901e9a1c154..0ae9d0b2487 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h @@ -2,9 +2,7 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -60,7 +58,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -92,10 +90,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -111,21 +109,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -138,7 +136,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -154,7 +154,7 @@ #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -226,7 +226,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -255,28 +255,27 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -284,7 +283,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -360,11 +359,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -377,12 +376,12 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -400,7 +399,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -432,18 +431,18 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -457,6 +456,78 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE + + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + + +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -469,7 +540,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -542,7 +613,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -572,7 +643,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -596,11 +667,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -609,14 +680,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -625,7 +696,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -637,18 +708,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -661,31 +732,27 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -693,15 +760,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -722,7 +789,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -740,7 +807,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -756,13 +823,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -863,7 +930,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -903,7 +970,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -928,7 +995,7 @@ #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U - + #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ @@ -963,7 +1030,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -978,39 +1045,39 @@ /** * @} - */ - + */ + #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1023,11 +1090,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1037,12 +1104,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1050,7 +1117,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1131,6 +1198,8 @@ #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER @@ -1144,17 +1213,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1165,7 +1234,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1177,28 +1246,31 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1213,8 +1285,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1223,7 +1295,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1231,7 +1303,7 @@ #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 @@ -1243,7 +1315,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1313,7 +1385,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1340,7 +1411,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1413,7 +1484,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1600,7 +1671,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1619,14 +1690,18 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST @@ -1642,11 +1717,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1657,7 +1732,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1666,7 +1741,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1695,8 +1770,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1761,7 +1836,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1769,37 +1844,37 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1816,7 +1891,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2044,6 +2119,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2235,13 +2325,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE @@ -2294,111 +2384,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2406,29 +2496,28 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2444,8 +2533,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2467,8 +2554,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2632,7 +2717,7 @@ #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) @@ -2640,6 +2725,30 @@ #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG @@ -2693,7 +2802,12 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2793,6 +2907,15 @@ #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + /** * @} */ @@ -2800,17 +2923,19 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - +#if defined (STM32G0) +#else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2846,7 +2971,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2871,26 +2996,26 @@ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if defined(STM32F4) +#if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2899,8 +3024,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2922,6 +3047,24 @@ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#endif /** * @} */ @@ -2940,7 +3083,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2972,7 +3115,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -2984,8 +3127,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3090,7 +3233,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3099,7 +3242,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3110,6 +3253,7 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ @@ -3135,11 +3279,22 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c index 285da086c57..5e6dae988a4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -67,11 +65,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32L4xx HAL Driver version number V1.7.1 + * @brief STM32L4xx HAL Driver version number */ #define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ +#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ @@ -253,7 +251,7 @@ __weak void HAL_MspDeInit(void) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) @@ -325,7 +323,7 @@ __weak uint32_t HAL_GetTick(void) * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) @@ -575,11 +573,11 @@ void HAL_SYSCFG_DisableMemorySwappingBank(void) #if defined(VREFBUF) /** * @brief Configure the internal voltage reference buffer voltage scale. - * @param VoltageScaling: specifies the output voltage to achieve + * @param VoltageScaling specifies the output voltage to achieve * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. * @retval None */ @@ -593,7 +591,7 @@ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) /** * @brief Configure the internal voltage reference buffer high impedance mode. - * @param Mode: specifies the high impedance mode + * @param Mode specifies the high impedance mode * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h index 7e98496f8f6..aafa7c351c2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -68,14 +66,21 @@ #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) +#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) +#else #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -374,19 +379,32 @@ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +/** @brief OCTOSPI mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) +#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) + +#else /** @brief QUADSPI mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @brief Return the boot mode as configured by user. * @retval The boot mode as configured by user. The returned value can be one @@ -406,8 +424,8 @@ * @note Write protection can only be disabled by a system reset */ #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ - }while(0) + SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ + }while(0) #if defined(SYSCFG_SWPR2_PAGE63) /** @brief SRAM2 page 32 to 63 write protection enable macro @@ -432,7 +450,7 @@ #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) /** @brief Floating Point Unit interrupt enable/disable macros - * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts + * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts */ #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ @@ -467,7 +485,7 @@ #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) /** @brief Check SYSCFG flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing @@ -480,7 +498,7 @@ #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) /** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__: This parameter can be a value of : + * @param __FASTMODEPLUS__ This parameter can be a value of : * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c index 56177964319..c9c033cbc68 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -47,8 +45,7 @@ (+) ADC channels selectable single/differential input. - (+) ADC offset on regular groups. - + (+) ADC offset shared on 4 offset instances. (+) ADC calibration (+) ADC conversion of regular group. @@ -83,10 +80,10 @@ other device clock parameters configuration: (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) - RCC_ADCCLKSOURCE_PLLSAI2 enable: (optional: if asynchronous clock selected) + RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI2; + (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (++) ADC clock source and clock prescaler are configured at ADC level with @@ -113,7 +110,7 @@ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). - + *** Configuration of ADC, group regular, channels parameters *** ================================================================ [..] @@ -271,20 +268,6 @@ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - -#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\ - ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\ - ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ - -#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \ - ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no - conversion (neither regular nor injected) is on-going */ - -#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ - - /* Delay to wait before setting ADEN once ADCAL has been reset must be at least 4 ADC clock cycles. @@ -297,23 +280,18 @@ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ - - -/* Delay for ADC voltage regulator startup time */ -/* Maximum delay is 10 microseconds */ -/* (refer device RM, parameter Tadcvreg_stup). */ -#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */ - /* Timeout to wait for current conversion on going to be completed. */ -/* Timeout fixed to worst case, for 1 channel. */ +/* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - ADC clock with prescaler 256 */ -/* 653 * 256 = 167168 clock cycles max */ +/* (from asynchronous clock, assuming clock frequency same as CPU for */ +/* this calculation) */ +/* - ADC oversampling ratio 256 */ +/* Calculation: 653 * 256 * 256 = 42795008 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ -#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168) /*!< ADC conversion completion time-out value */ - +#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 42795008) /*!< ADC conversion completion time-out value */ @@ -348,8 +326,8 @@ * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level - * depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks - * or AHB clock. + * (refer to description of RCC configuration for ADC + * in header of this file). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can @@ -369,15 +347,13 @@ * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - ADC_Common_TypeDef *tmpADC_Common; - uint32_t tmpCFGR = 0; + uint32_t tmpCFGR = 0U; __IO uint32_t wait_loop_index = 0; /* Check ADC handle */ @@ -391,11 +367,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_ADC_DFSDMCFG_MODE(hadc)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); @@ -407,20 +383,18 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - if (hadc->Init.DiscontinuousConvMode == ENABLE) + if(hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } - /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) + if(hadc->State == HAL_ADC_STATE_RESET) { /* Init the low level hardware */ HAL_ADC_MspInit(hadc); @@ -432,29 +406,27 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) hadc->Lock = HAL_UNLOCKED; } - /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - /* Exit deep power down mode if still in that state */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD)) + if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0U) { - /* Exit deep power down mode */ - CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); + /* Disable ADC deep power down mode */ + LL_ADC_DisableDeepPowerDown(hadc->Instance); /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } - if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) - { + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + { /* Enable ADC internal voltage regulator */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN); + LL_ADC_EnableInternalRegulator(hadc->Instance); /* Delay for ADC stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2))); + wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); while(wait_loop_index != 0) { wait_loop_index--; @@ -464,7 +436,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -479,19 +451,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + if( (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + ) { - - /* Initialize the ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); /* Configuration of common ADC parameters */ - /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - - /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ @@ -515,8 +485,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ - - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler); + LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); } /* Configuration of ADC: */ @@ -541,19 +510,19 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Enable external trigger if trigger selection is different of software */ /* start. */ - /* - external trigger to start conversion Init.ExternalTrigConv */ - /* - external trigger polarity Init.ExternalTrigConvEdge */ - /* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */ - /* equivalent to software start. */ - if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - && (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE)) + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR |= ( hadc->Init.ExternalTrigConv | hadc->Init.ExternalTrigConvEdge); + tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + | hadc->Init.ExternalTrigConvEdge + ); } - /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); - + /* Update Configuration Register CFGR */ + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -565,10 +534,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); - + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); - - + if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); @@ -576,36 +544,31 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); - if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) - || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)) - { - /* Multi trigger is not applicable to software-triggered conversions */ - assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER)); - } - - - /* Configuration of Oversampler: */ - /* - Oversampling Ratio */ - /* - Right bit shift */ - /* - Triggered mode */ - /* - Oversampling mode (continued/resumed) */ - MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, - ADC_CFGR2_ROVSE | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode | - hadc->Init.Oversampling.OversamplingStopReset); + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + /* - Oversampling mode (continued/resumed) */ + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TROVS | + ADC_CFGR2_ROVSM, + ADC_CFGR2_ROVSE | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode | + hadc->Init.Oversampling.OversamplingStopReset + ); } else { - /* Disable Regular OverSampling */ - CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); + /* Disable ADC oversampling scope on ADC group regular */ + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ - - /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ @@ -613,12 +576,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion" */ + /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) { - /* Set number of ranks in regular group sequencer */ - MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); + /* Set number of ranks in regular group sequencer */ + MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); } else { @@ -635,7 +598,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; - } /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */ + } /* Return function status */ return tmp_hal_status; @@ -643,13 +606,20 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitialize the ADC peripheral registers to their default reset - * values, with deinitialization of the ADC MSP. - * @note Keep in mind that all ADCs use the same clock: disabling - * the clock will reset all ADCs. - * @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by - * reducing the leakage currents and is particularly interesting before - * entering STOP 1 or STOP 2 modes. - * @param hadc: ADC handle + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: + * all ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behavior in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: + * this saves more power by reducing leakage currents + * and is particularly interesting before entering MCU low-power modes. + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) @@ -828,7 +798,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initialize the ADC MSP. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) @@ -843,8 +813,9 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitialize the ADC MSP. - * @param hadc: ADC handle - * @note All ADCs use the same clock: disabling the clock will reset all ADCs. + * @param hadc ADC handle + * @note All ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) @@ -889,13 +860,14 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * @note Case of multimode enabled (when multimode feature is available): * if ADC is Slave, ADC is enabled but conversion is not started, * if ADC is master, ADC is enabled and multimode conversion is started. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_TypeDef *tmpADC_Master; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -907,36 +879,47 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* State machine update: Check if an injected conversion is ongoing */ + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + + /* Set ADC error code */ + /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { - /* Set ADC error code to none */ + /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - - /* Clear regular group conversion flag and overrun flag */ + + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -954,10 +937,9 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - /* Process unlocked */ - __HAL_UNLOCK(hadc); - /* Start ADC */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { @@ -968,11 +950,9 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - - } /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */ + } + + } } else { @@ -995,7 +975,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) @@ -1021,8 +1001,9 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) if (tmp_hal_status == HAL_OK) { /* Set ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } @@ -1035,25 +1016,27 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) /** * @brief Wait for regular group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @note Depending on hadc->Init.EOCSelection, EOS or EOC is - * checked and cleared depending on AUTDLY bit status. - * @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a - * DMA-managed conversions configuration: indeed, EOC is immediately - * reset by the DMA reading the DR register when the converted data is - * available. Therefore, EOC is set for a too short period to be - * reliably polled. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart = 0; - uint32_t tmp_Flag_EOC = 0x00; - uint32_t tmp_cfgr = 0x00; - uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set, - tmp_eos_raised will be corrected - accordingly during API execution */ + uint32_t tickstart = 0U; + uint32_t tmp_Flag_End = 0U; + uint32_t tmp_cfgr = 0U; ADC_TypeDef *tmpADC_Master; /* Check the parameters */ @@ -1062,43 +1045,50 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { - tmp_Flag_EOC = ADC_FLAG_EOS; + tmp_Flag_End = ADC_FLAG_EOS; } /* If end of conversion selected to end of unitary conversion */ else /* ADC_EOC_SINGLE_CONV */ { - /* Check that the ADC is not in a DMA-based configuration. Otherwise, - returns an error. */ - - /* Check whether dual regular conversions are disabled or unavailable. */ - if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if(ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) { - /* Check DMAEN bit in handle ADC CFGR register */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) + /* Check ADC DMA mode in independant mode */ + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; - } + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } } else { - /* Else need to check Common register CCR MDMA bit field. */ - if (ADC_MULTIMODE_DMA_ENABLED()) + /* Check ADC DMA mode in multimode */ + if(ADC_MULTIMODE_DMA_ENABLED(hadc)) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } } - - /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */ - tmp_Flag_EOC = ADC_FLAG_EOC; } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) + while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) @@ -1116,16 +1106,31 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti } } - /* Next, to clear the polled flag as well as to update the handle State, - EOS is checked and the relevant configuration register is retrieved. */ - /* 1. Check whether or not EOS is set */ - if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS)) + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) { - tmp_eos_raised = 0; + /* Check whether end of sequence is reached */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } } - /* 2. Check whether or not hadc is the handle of a Slave ADC with dual - regular conversions enabled. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) + + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) { /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); @@ -1136,57 +1141,31 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tmpADC_Master = ADC_MASTER_REGISTER(hadc); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - + /* Clear polled flag */ - if (tmp_Flag_EOC == ADC_FLAG_EOS) + if (tmp_Flag_End == ADC_FLAG_EOS) { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { - /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ - /* For regular groups, no new conversion will start before EOC is cleared.*/ - /* Note that 1. reading DR clears EOC. */ - /* 2. in multimode with dual regular conversions enabled (when */ - /* multimode feature is available), Master AUTDLY bit is */ - /* checked. */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - /* If 1. EOS is set - 2. conversions are software-triggered - 3. CONT bit is reset (that of handle ADC or Master ADC if applicable) - Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset. - 4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY - can be set */ - if ((tmp_eos_raised) - && (ADC_IS_SOFTWARE_START_REGULAR(hadc)) - && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - /* Return function status */ return HAL_OK; } /** * @brief Poll for ADC event. - * @param hadc: ADC handle - * @param EventType: the ADC event type. + * @param hadc ADC handle + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) @@ -1194,7 +1173,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. * Indeed, the latter is reset only if hadc->Init.Overrun field is set * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten @@ -1212,7 +1191,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Check selected event flag */ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) @@ -1220,7 +1199,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1245,13 +1224,15 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy break; - /* Analog watchdog (level out of window) event */ + /* Analog watchdog (level out of window) event */ /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */ - /* flags HAL_ADC_STATE_AWD/2/3 function. */ - /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */ - /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */ - /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ + /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ + /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */ + /* Check analog watchdog 1 flag */ case ADC_AWD_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -1336,13 +1317,13 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * @note To guarantee a proper reset of all interruptions once all the needed * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) @@ -1361,11 +1342,27 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* State machine update: Check if an injected conversion is ongoing */ + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + + /* Set ADC error code */ + /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ @@ -1373,56 +1370,52 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) } else { - /* Set ADC error code to none */ + /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); - } - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - /* Clear regular group conversion flag and overrun flag */ + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* By default, disable all interruptions before enabling the desired ones */ + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - /* Enable required interruptions */ + /* Enable ADC end of conversion interrupt */ switch(hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); - break; + break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - break; + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; } - + + /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - } + } /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion starts at next */ + /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) + if(ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) { /* Multimode feature is not available or ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. @@ -1446,12 +1439,11 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; - } - } /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); - /* Start ADC */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { @@ -1469,21 +1461,19 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Next, set Slave injected interruptions */ switch(hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; - } - } /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */ - } /* if (tmp_hal_status == HAL_OK) */ + } + } + } + } else { /* Process unlocked */ @@ -1504,7 +1494,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) @@ -1535,7 +1525,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY), + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } @@ -1555,9 +1545,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() * is designed for single-ADC mode only. For multimode, the dedicated * HAL_ADCEx_MultiModeStart_DMA() function must be used. - * @param hadc: ADC handle - * @param pData: Destination Buffer address. - * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes) + * @param hadc ADC handle + * @param pData Destination Buffer address. + * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1583,30 +1573,33 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - } - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + + /* Check if a conversion is on going on ADC group injected */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -1625,46 +1618,47 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, - ADC_IT_OVR is enabled. */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + ADC_IT_OVR is enabled. */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); - + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (tmp_hal_status == HAL_OK) */ + __HAL_UNLOCK(hadc); + } } else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */ - + __HAL_UNLOCK(hadc); + } } else { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } @@ -1673,13 +1667,13 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on injected group. If injected group is under use, it + * @note: ADC peripheral disable is forcing stop of potential + * conversion on ADC group injected. If ADC group injected is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) @@ -1698,7 +1692,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { - /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ + /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -1709,7 +1703,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ @@ -1732,7 +1726,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY), + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } @@ -1757,11 +1751,11 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. - * To clear this flag, either use function: + * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADC_PollForConversion() + * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) @@ -1778,24 +1772,23 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Handle ADC interrupt request. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */ - ADC_TypeDef *tmpADC_Master; - uint32_t tmp_isr = hadc->Instance->ISR; - uint32_t tmp_ier = hadc->Instance->IER; - uint32_t tmp_cfgr = 0x0; - uint32_t tmp_cfgr_jqm = 0x0; + uint32_t tmp_isr = hadc->Instance->ISR; + uint32_t tmp_ier = hadc->Instance->IER; + uint32_t tmp_cfgr = 0x0; + ADC_TypeDef *tmpADC_Master; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - /* ====== Check End of Sampling flag for regular group ===== */ - if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + /* ========== Check End of Sampling flag for ADC group regular ========== */ + if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1803,30 +1796,33 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } - + /* End Of Sampling callback */ HAL_ADCEx_EndOfSamplingCallback(hadc); /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); - } + } - /* ====== Check End of Conversion or Sequence flags for regular group ===== */ - if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ + if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - /* Disable interruption if no further conversion upcoming by regular */ - /* external trigger or by continuous mode, */ - /* and if scan sequence if completed. */ + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) { + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) { /* check CONT bit directly in handle ADC CFGR register */ @@ -1845,22 +1841,23 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Disable ADC end of sequence conversion interrupt */ - /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */ - /* in HAL_Start_IT(), it isn't disabled here because it can be used */ - /* by overrun IRQ process below. */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } else { @@ -1871,24 +1868,25 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } - } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */ - } /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */ + } + } /* Conversion complete callback */ - /* Note: HAL_ADC_ConvCpltCallback can resort to - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether - interruption has been triggered by end of conversion or end of - sequence. */ - HAL_ADC_ConvCpltCallback(hadc); - + /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ + /* to determine if conversion has been triggered from EOC or EOS, */ + /* possibility to use: */ + /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ + HAL_ADC_ConvCpltCallback(hadc); /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); } - - /* ========== Check End of Conversion flag for injected group ========== */ + /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) { @@ -1899,75 +1897,66 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - - /* Check whether interruptions can be disabled only if - - injected conversions are software-triggered when injected queue management is disabled - OR - - auto-injection is enabled, continuous mode is disabled (CONT = 0) - and regular conversions are software-triggered */ - /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) { - - /* First, retrieve proper registers to check */ - /* 1a. Are injected conversions that of a dual Slave ? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) - { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - check JQM bit directly in ADC CFGR register */ - tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); - } - else - { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - need to check JQM bit of Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR); - } - /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) - { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits directly in ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits of Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } - - /* Secondly, check whether JEOC and JEOS interruptions can be disabled */ - if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM)) - && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc)))) ) + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + tmpADC_Master = ADC_MASTER_REGISTER(hadc); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } + + /* Disable interruption if no further conversion upcoming by injected */ + /* external trigger or by automatic injected conversion with regular */ + /* group having no further conversion upcoming (same conditions as */ + /* regular group interruption disabling above), */ + /* and if injected scan sequence is completed. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || + ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + { + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } - } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */ + } /* Injected Conversion complete callback */ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to @@ -1980,8 +1969,6 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } - - /* ========== Check Analog watchdog flags =================================================== */ /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) @@ -2005,7 +1992,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) HAL_ADCEx_LevelOutOfWindow2Callback(hadc); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - } + } /* ========== Check analog watchdog 3 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) @@ -2035,23 +2022,22 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) } else { - /* check DMA configuration, depending on multimode set or not, - or whether or not multimode feature is available */ + /* Check DMA configuration */ if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET) { /* Multimode not set or feature not available or ADC independent */ if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) { - overrun_error = 1; - } + overrun_error = 1; + } } else { /* Multimode (when feature is available) is enabled, Common Control Register MDMA bits must be checked. */ - if (ADC_MULTIMODE_DMA_ENABLED()) + if (ADC_MULTIMODE_DMA_ENABLED(hadc)) { - overrun_error = 1; + overrun_error = 1; } } } @@ -2064,17 +2050,18 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - /* Error callback */ + /* Error callback */ + /* Note: In case of overrun, ADC conversion data is preserved until */ + /* flag OVR is reset. */ + /* Therefore, old ADC conversion data can be retrieved in */ + /* function "HAL_ADC_ErrorCallback()". */ HAL_ADC_ErrorCallback(hadc); } - - /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since - old data is preserved until OVR is reset */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - /* ========== Check Injected context queue overflow flag ========== */ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { @@ -2095,7 +2082,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Conversion complete callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) @@ -2110,7 +2097,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Conversion DMA half-transfer callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) @@ -2125,7 +2112,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog 1 callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) @@ -2147,7 +2134,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) @@ -2192,14 +2179,13 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel assigned to ADC group regular. + * @param hadc ADC handle + * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_Common_TypeDef *tmpADC_Common; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0; @@ -2235,121 +2221,93 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* - Channel rank */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { - - /* Regular sequence configuration */ - /* Clear the old SQx bits then set the new ones for the selected rank */ - /* For Rank 1 to 4 */ - if (sConfig->Rank < 5) - { - MODIFY_REG(hadc->Instance->SQR1, - ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank), - ADC_SQR1_RK(sConfig->Channel, sConfig->Rank)); - } - /* For Rank 5 to 9 */ - else if (sConfig->Rank < 10) + #if !defined (USE_FULL_ASSERT) + /* Correspondance for compatibility with legacy definition of */ + /* sequencer ranks in direct number format. This correspondance can */ + /* be done only on ranks 1 to 5 due to literal values. */ + /* Note: Sequencer ranks in direct number format are no more used */ + /* and are detected by activating USE_FULL_ASSERT feature. */ + if (sConfig->Rank <= 5U) + { + switch (sConfig->Rank) { - MODIFY_REG(hadc->Instance->SQR2, - ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank), - ADC_SQR2_RK(sConfig->Channel, sConfig->Rank)); + case 2U: sConfig->Rank = ADC_REGULAR_RANK_2; break; + case 3U: sConfig->Rank = ADC_REGULAR_RANK_3; break; + case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break; + case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break; + /* case 1U */ + default: sConfig->Rank = ADC_REGULAR_RANK_1; } - /* For Rank 10 to 14 */ - else if (sConfig->Rank < 15) + } + #endif + + /* Set ADC group regular sequence: channel on the selected scan sequence rank */ + LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel sampling time */ + /* - Channel offset */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + { +#if defined(ADC_SMPR1_SMPPLUS) + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if(sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) { - MODIFY_REG(hadc->Instance->SQR3, - ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank), - ADC_SQR3_RK(sConfig->Channel, sConfig->Rank)); + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } - /* For Rank 15 to 16 */ else - { - MODIFY_REG(hadc->Instance->SQR4, - ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank), - ADC_SQR4_RK(sConfig->Channel, sConfig->Rank)); + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } +#else + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); +#endif - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Channel sampling time */ - /* - Channel offset */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + /* Configure the offset: offset enable/disable, channel, offset value */ + + /* Shift the offset with respect to the selected ADC resolution. */ + /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); + + if(sConfig->OffsetNumber != ADC_OFFSET_NONE) { - - /* Channel sampling time configuration */ - /* Clear the old sample time then set the new one for the selected channel */ - /* For channels 10 to 18 */ - if (sConfig->Channel >= ADC_CHANNEL_10) + /* Set ADC selected offset number */ + LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); + + } + else + { + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is disabled. */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { - ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - else /* For channels 0 to 9 */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { - ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - - - /* Configure the offset: offset enable/disable, channel, offset value */ - - /* Shift the offset with respect to the selected ADC resolution. */ - /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); - - switch (sConfig->OffsetNumber) - { - /* Configure offset register i when applicable: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - case ADC_OFFSET_1: - MODIFY_REG(hadc->Instance->OFR1, - ADC_OFR_FIELDS, - ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_2: - MODIFY_REG(hadc->Instance->OFR2, - ADC_OFR_FIELDS, - ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_3: - MODIFY_REG(hadc->Instance->OFR3, - ADC_OFR_FIELDS, - ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_4: - MODIFY_REG(hadc->Instance->OFR4, - ADC_OFR_FIELDS, - ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - /* Case ADC_OFFSET_NONE */ - default : - /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. - If this is the case, offset OFRx is disabled since - sConfig->OffsetNumber = ADC_OFFSET_NONE. */ - if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); - } - if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); - } - if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); - } - if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); - } - break; - } /* switch (sConfig->OffsetNumber) */ - - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); + } + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); + } + } + } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ @@ -2357,51 +2315,31 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { + /* Set mode single-ended or differential input of the selected ADC channel */ + LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); + /* Configuration of differential mode */ - if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) + if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Disable differential mode (default mode: single-ended) */ - CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); } - else - { - /* Enable differential mode */ - SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); - - /* Sampling time configuration of channel ADC_IN+1 (negative input) */ - /* Clear the old sample time then set the new one for the selected */ - /* channel. */ - /* Starting from channel 9, SMPR2 register must be configured */ - if (sConfig->Channel >= ADC_CHANNEL_9) - { - ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1); - } - else /* For channels 0 to 8, SMPR1 must be configured */ - { - ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1); - } - } - - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ - /* paths. */ + /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ /* Configuration of common ADC parameters */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - - /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) ) { /* Configuration of common ADC parameters (continuation) */ @@ -2415,13 +2353,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); - + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2))); + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); while(wait_loop_index != 0) { wait_loop_index--; @@ -2432,15 +2370,15 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - { + { if (ADC_VREFINT_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); - } + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } } } /* If the requested internal measurement path has already been */ @@ -2454,10 +2392,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf tmp_hal_status = HAL_ERROR; } } - - } /* if (ADC_IS_ENABLE(hadc) == RESET) */ - - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */ + } + } /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ @@ -2487,27 +2423,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @note Analog watchdog thresholds can be modified while ADC conversion - * is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc: ADC handle - * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @note On this STM32 serie, analog watchdog thresholds cannot be modified + * while ADC conversion is on going. + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; - - uint32_t tmpADCFlagAWD2orAWD3; - uint32_t tmpADCITAWD2orAWD3; + uint32_t tmpAWDHighThresholdShifted = 0U; + uint32_t tmpAWDLowThresholdShifted = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2531,136 +2457,162 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular and injected groups: */ + /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { - - /* Analog watchdogs configuration */ + /* Analog watchdog configuration */ if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: regular and/or injected */ - /* groups, one or overall group of channels. */ - /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS, - AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) ); - - /* Shift the offset with respect to the selected ADC resolution: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels, on groups regular and-or injected. */ + switch(AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + break; + + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); + break; + + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + case ADC_ANALOGWATCHDOG_ALL_INJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); + break; + + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); + break; + } + + /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->TR1, - ADC_TR1_HT1 | ADC_TR1_LT1, - ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); + + /* Update state, clear previous result related to AWD1 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); - /* Clear the ADC Analog watchdog flag (in case of left enabled by */ - /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ - /* or HAL_ADC_PollForEvent(). */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1); + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD1(hadc->Instance); - /* Configure ADC Analog watchdog interrupt */ + /* Configure ADC analog watchdog interrupt */ if(AnalogWDGConfig->ITMode == ENABLE) { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1); + LL_ADC_EnableIT_AWD1(hadc->Instance); } else { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1); + LL_ADC_DisableIT_AWD1(hadc->Instance); } - - /* Update state, clear previous result related to AWD1 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); } - /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ + /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - /* Shift the threshold with respect to the selected ADC resolution */ - /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ + switch(AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: + /* Update AWD by bitfield to keep the possibility to monitor */ + /* several channels by successive calls of this function. */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + SET_BIT(hadc->Instance->AWD2CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + else + { + SET_BIT(hadc->Instance->AWD3CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + case ADC_ANALOGWATCHDOG_ALL_INJEC: + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + break; + } + + /* Shift the thresholds in function of the selected ADC resolution */ + /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - + + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - /* Set the Analog watchdog channel or group of channels. This also */ - /* enables the watchdog. */ - /* Note: Conditional register reset, because several channels can be */ - /* set by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) + /* Update state, clear previous result related to AWD2 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD2(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) { - SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel)); + LL_ADC_EnableIT_AWD2(hadc->Instance); } else { - CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); + LL_ADC_DisableIT_AWD2(hadc->Instance); } - - /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, - ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); - - /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ - /* settings. */ - tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2; - tmpADCITAWD2orAWD3 = ADC_IT_AWD2; - - /* Update state, clear previous result related to AWD2 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); } /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { - /* Set the Analog watchdog channel or group of channels. This also */ - /* enables the watchdog. */ - /* Note: Conditional register reset, because several channels can be */ - /* set by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) + /* Update state, clear previous result related to AWD3 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD3(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) { - SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel)); + LL_ADC_EnableIT_AWD3(hadc->Instance); } else { - CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); + LL_ADC_DisableIT_AWD3(hadc->Instance); } - - /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, - ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); - - /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ - /* settings. */ - tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3; - tmpADCITAWD2orAWD3 = ADC_IT_AWD3; - - /* Update state, clear previous result related to AWD3 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - } - - /* Clear the ADC Analog watchdog flag (in case left enabled by */ - /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ - /* or HAL_ADC_PollForEvent(). */ - __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3); - - /* Configure ADC Analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) - { - __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3); - } - else - { - __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3); } } } - /* If a conversion is on going on regular or injected groups, no update */ + /* If a conversion is on going on ADC group regular or injected, no update */ /* could be done on neither of the AWD configuration structure parameters. */ else { @@ -2669,7 +2621,6 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -2706,7 +2657,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * For example: * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) @@ -2720,7 +2671,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) @@ -2745,8 +2696,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) /** * @brief Stop ADC conversion. - * @param hadc: ADC handle - * @param ConversionGroup: ADC group regular and/or injected. + * @param hadc ADC handle + * @param ConversionGroup ADC group regular and/or injected. * This parameter can be one of the following values: * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. @@ -2808,7 +2759,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) { /* Stop conversions on regular group */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP); + LL_ADC_REG_StopConversion(hadc->Instance); } } @@ -2858,7 +2809,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio } } - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */ + } /* Return HAL status */ return HAL_OK; @@ -2870,12 +2821,13 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0; + __IO uint32_t wait_loop_index = 0; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -2896,30 +2848,44 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) } /* Enable the ADC peripheral */ - ADC_ENABLE(hadc); - + LL_ADC_Enable(hadc->Instance); + /* Delay for ADC stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles. */ + wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); + while(wait_loop_index != 0) + { + wait_loop_index--; + } + /* Wait for ADC effectively enabled */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) { /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit has been cleared (after a calibration), ADEN bit is reset by the calibration logic. - The workaround is to continue setting ADEN until ADRDY is becomes 1. + The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ - ADC_ENABLE(hadc); - - if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT) - { + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if(LL_ADC_IsEnabled(hadc->Instance) == 0) + { + LL_ADC_Enable(hadc->Instance); + } + + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } @@ -2933,7 +2899,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) @@ -2949,7 +2915,8 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { /* Disable the ADC peripheral */ - ADC_DISABLE(hadc); + LL_ADC_Disable(hadc->Instance); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); } else { @@ -2987,7 +2954,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) @@ -2996,22 +2963,26 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA))) + if(HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))) { - /* Update ADC state machine */ + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ /* Is it the end of the regular sequence ? */ - if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) + if(HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) { /* Are conversions software-triggered ? */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Is CONT bit set ? */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -3022,11 +2993,11 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -3036,20 +3007,24 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* Conversion complete callback */ HAL_ADC_ConvCpltCallback(hadc); } - else /* DMA or internal error occurred (or both) */ + else /* DMA and-or internal error occurred */ { - /* In case of internal error, */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* call Error Callback function */ + /* Call HAL ADC Error Callback function */ HAL_ADC_ErrorCallback(hadc); } + else + { + /* Call ADC DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } } } /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -3063,7 +3038,7 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h index bd11ed33f15..522b91304b7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -46,6 +44,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +/* Include low level driver */ +#include "stm32l4xx_ll_adc.h" + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -65,13 +66,13 @@ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADCEx_Oversampling_Ratio */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADCEx_Right_Bit_Shift */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. - This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected @@ -79,7 +80,8 @@ typedef struct If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). - This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ + }ADC_OversamplingTypeDef; /** @@ -100,23 +102,23 @@ typedef struct */ typedef struct { - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLLSAI1/PLLSAI2 clocks) and clock prescaler. - This parameter can be a value of @ref ADC_ClockPrescaler. - Note: The clock is common for all the ADCs. + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. + This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. + Note: The ADC clock configuration is common to all ADC instances. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. - Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level. - Note: This parameter can be modified only if all ADCs are disabled. */ + Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. + Note: This parameter can be modified only if all ADC instances are disabled. */ uint32_t Resolution; /*!< Configure the ADC resolution. - This parameter can be a value of @ref ADC_Resolution */ + This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. - This parameter can be a value of @ref ADC_Data_align */ + This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. @@ -177,7 +179,7 @@ typedef struct uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. - This parameter can be a value of @ref ADC_Overrun. + This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). @@ -193,11 +195,12 @@ typedef struct ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. - This parameter can be a value of @ref ADCEx_DFSDM_Mode_Configuration. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ + This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + +#endif }ADC_InitTypeDef; /** @@ -208,17 +211,17 @@ typedef struct * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter - * (which fulfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) + * on the fly). */ typedef struct { uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_channels + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Specify the rank in the regular group sequencer. - This parameter can be a value of @ref ADC_regular_rank + This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ @@ -226,7 +229,7 @@ typedef struct Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), @@ -236,7 +239,7 @@ typedef struct uint32_t SingleDiff; /*!< Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADCEx_SingleDifferential + This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. @@ -246,7 +249,7 @@ typedef struct of another parameter update on the fly) */ uint32_t OffsetNumber; /*!< Select the offset number - This parameter can be a value of @ref ADCEx_OffsetNumber + This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. @@ -255,31 +258,31 @@ typedef struct 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ + }ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: - * ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. + * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. */ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) - This parameter can be a value of @ref ADCEx_analog_watchdog_number. */ + This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. - For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected. - For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset - channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored. - This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). - This parameter can be a value of @ref ADC_channels. */ + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ @@ -297,11 +300,24 @@ typedef struct the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ }ADC_AnalogWDGConfTypeDef; +/** + * @brief ADC group injected contexts queue configuration + * @note Structure intended to be used only through structure "ADC_HandleTypeDef" + */ +typedef struct +{ + uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each + HAL_ADCEx_InjectedConfigChannel() call to finally initialize + JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ + + uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ +}ADC_InjectionConfigTypeDef; + /** @defgroup ADC_States ADC States * @{ */ -/** +/** * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. @@ -310,41 +326,60 @@ typedef struct * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ /** * @} */ +/** + * @brief ADC handle Structure definition + */ +typedef struct +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ +}ADC_HandleTypeDef; /** * @} @@ -360,59 +395,59 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error (problem of clocking, - enable/disable, erroneous state, ...) */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ /** * @} */ -/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler +/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ -#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ - -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ - -#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock not divided */ -#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 2 */ -#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock divided by 4 */ -#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 6 */ -#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock divided by 8 */ -#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 10 */ -#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 12 */ -#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16 */ -#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock divided by 32 */ -#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 64 */ -#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 128 */ -#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */ +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ + +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ + +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ /** * @} */ -/** @defgroup ADC_Resolution ADC Resolution +/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */ +#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ /** * @} */ -/** @defgroup ADC_Data_align ADC conversion data alignment +/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) /*!< Data right alignment */ -#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) /*!< Data left alignment */ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ /** * @} */ @@ -420,8 +455,8 @@ typedef struct /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ -#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ +#define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */ /** * @} */ @@ -430,23 +465,23 @@ typedef struct * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) /*!< Event 0 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) /*!< Event 1 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) /*!< Event 2 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 3 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) /*!< Event 4 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 5 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 6 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) /*!< Event 8 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) /*!< Event 9 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) /*!< Event 10 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) /*!< Event 12 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) /*!< Event 15 triggers regular group conversion start */ -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers regular group conversion start */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ +#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -454,10 +489,10 @@ typedef struct /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ @@ -465,126 +500,282 @@ typedef struct /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions * @{ */ -#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of unitary conversion flag */ -#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence conversions flag */ -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< Reserved for future use */ +#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ +#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ /** * @} */ -/** @defgroup ADC_Overrun ADC overrun +/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /*!< Data preserved in case of overrun */ -#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD) /*!< Data overwritten in case of overrun */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} */ -/** @defgroup ADC_regular_rank ADC group regular sequencer rank +/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ +#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ +#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ +#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ +#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ +#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ +#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ +#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ /** * @} */ -/** @defgroup ADC_channels ADC channels +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define ADC_CHANNEL_0 ((uint32_t)(0x00000000)) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0)) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1)) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2)) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3)) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0)) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1)) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2)) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4)) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0)) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1)) /*!< ADC channel 18 */ - -/* Note: VrefInt, TempSensor and Vbat internal channels are not available on all ADC's - (information present in Reference Manual) */ -#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17 /*!< ADC temperature sensor channel */ -#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 /*!< ADC Vbat channel */ -#define ADC_CHANNEL_VREFINT ADC_CHANNEL_0 /*!< ADC Vrefint channel */ +#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ +#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ +#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ +#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ +#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ +#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ +#if defined(ADC_SMPR1_SMPPLUS) +#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ +#endif +/** + * @} + */ +/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ +/* all ADC instances (refer to Reference Manual). */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ #if defined(ADC1) && !defined(ADC2) -#define ADC_CHANNEL_DAC1CH1 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, they cannot be used both simultenaeously. */ -#define ADC_CHANNEL_DAC1CH2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, they cannot be used both simultenaeously. */ +#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ +#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ #elif defined(ADC2) -#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ -#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ +#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ +#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ #if defined(ADC3) -#define ADC_CHANNEL_DAC1CH1_ADC3 (ADC_CHANNEL_14) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ -#define ADC_CHANNEL_DAC1CH2_ADC3 (ADC_CHANNEL_15) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ +#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ +#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ #endif #endif /** * @} */ +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ +#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular + * @{ + */ +#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ +#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ +/** + * @} + */ + + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ +/** + * @} + */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ +#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ +#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ + +#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ + +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ +#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ +#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ + +#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ + +#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ + ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ + ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ + +/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ + ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ + ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ + +/** + * @} + */ /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ -/** @defgroup ADC_Private_Macro ADC Private Macros +/** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) /** * @brief Return resolution bits in CFGR register RES[1:0] field. - * @param __HANDLE__: ADC handle. - * @retval 2-bit field RES of CFGR register. + * @param __HANDLE__ ADC handle + * @retval Value of bitfield RES in CFGR register. */ -#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES) +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (LL_ADC_GetResolution((__HANDLE__)->Instance)) /** * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Verification of ADC state: enabled or disabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -594,53 +785,52 @@ typedef struct /** * @brief Check if conversion is on going on regular group. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ -#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ - ) ? RESET : SET) +#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ + (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) /** * @brief Simultaneously clear and set specific bits of the handle State. * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. + * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Verify that a given value is aligned with the ADC resolution range. - * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). - * @param __ADC_VALUE__: value checked against the resolution. + * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))) ) + ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) ) /** * @brief Verify the length of the scheduled regular conversions group. - * @param __LENGTH__: number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ -#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U))) /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. - * @param NUMBER: number of scheduled regular conversions in discontinuous mode. + * @param NUMBER number of scheduled regular conversions in discontinuous mode. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large) */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) /** * @brief Verify the ADC clock setting. - * @param __ADC_CLOCK__: programmed ADC clock. + * @param __ADC_CLOCK__ programmed ADC clock. * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) */ #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ @@ -658,11 +848,10 @@ typedef struct ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) - /** * @brief Verify the ADC resolution setting. - * @param __RESOLUTION__: programmed ADC resolution. + * @param __RESOLUTION__ programmed ADC resolution. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ @@ -672,7 +861,7 @@ typedef struct /** * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. - * @param __RESOLUTION__: programmed ADC resolution when limited to 6 or 8 bits. + * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ @@ -680,26 +869,25 @@ typedef struct /** * @brief Verify the ADC converted data alignment. - * @param __ALIGN__: programmed ADC converted data alignment. + * @param __ALIGN__ programmed ADC converted data alignment. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) - */ + */ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) - /** * @brief Verify the ADC scan mode. - * @param __SCAN_MODE__: programmed ADC scan mode. + * @param __SCAN_MODE__ programmed ADC scan mode. * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) - */ + */ #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ - ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) - + ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) + /** * @brief Verify the ADC edge trigger setting for regular group. - * @param __EDGE__: programmed ADC edge trigger setting. + * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ + */ #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ @@ -707,51 +895,50 @@ typedef struct /** * @brief Verify the ADC regular conversions external trigger. - * @param __REGTRIG__: programmed ADC regular conversions external trigger. + * @param __HANDLE__ ADC handle + * @param __REGTRIG__ programmed ADC regular conversions external trigger. * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) - */ -#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) + */ +#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) /** * @brief Verify the ADC regular conversions check for converted data availability. - * @param __EOC_SELECTION__: converted data availability check. + * @param __EOC_SELECTION__ converted data availability check. * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) - */ + */ #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ - ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) || \ - ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV) ) - + ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) + /** * @brief Verify the ADC regular conversions overrun handling. - * @param __OVR__: ADC regular conversions overrun handling. + * @param __OVR__ ADC regular conversions overrun handling. * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) - */ + */ #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ - ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) - + ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) + /** * @brief Verify the ADC conversions sampling time. - * @param __TIME__: ADC conversions sampling time. + * @param __TIME__ ADC conversions sampling time. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) */ -#if defined (ADC_SMPR1_SMPPLUS) +#if defined(ADC_SMPR1_SMPPLUS) #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ @@ -774,7 +961,7 @@ typedef struct /** * @brief Verify the ADC regular channel setting. - * @param __CHANNEL__: programmed ADC regular channel. + * @param __CHANNEL__ programmed ADC regular channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ @@ -797,7 +984,7 @@ typedef struct /** * @} */ - + /* Private constants ---------------------------------------------------------*/ @@ -812,132 +999,683 @@ typedef struct /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5) /*!< ADC stop time-out value */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120) +#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) /** * @} */ -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macro ADC Exported Macros +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. * @{ */ /** @brief Reset ADC handle state. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval None */ -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) - - -/** @brief Check whether the specified ADC interrupt source is enabled or not. - * @param __HANDLE__: ADC handle. - * @param __INTERRUPT__: ADC interrupt source to check - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source - * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR, ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. - * @retval State of interruption (SET or RESET) - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \ - )? SET : RESET \ - ) - -/** - * @brief Enable an ADC interrupt. - * @param __HANDLE__: ADC handle. - * @param __INTERRUPT__: ADC Interrupt to enable - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source - * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR, ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) + +/** + * @brief Enable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable an ADC interrupt. - * @param __HANDLE__: ADC handle. - * @param __INTERRUPT__: ADC Interrupt to disable - * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source - * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR, ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + /** * @brief Check whether the specified ADC flag is set or not. - * @param __HANDLE__: ADC handle. - * @param __FLAG__: ADC flag to check + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag - * @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR, ADC overrun flag - * @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag - * @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear a specified ADC flag. - * @param __HANDLE__: ADC handle. - * @param __FLAG__: ADC flag to clear + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @retval State of flag (TRUE or FALSE). + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified ADC flag. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag - * @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR, ADC overrun flag - * @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag - * @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag. - * @note Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR). + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) - +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @} + */ + +/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals ADC_CHANNEL_x. + * @note Example: + * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + +/** + * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n + * (1, 2, 3, 4) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * ADC_CHANNEL_1, ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + */ +#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) +#endif + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ + __LL_ADC_COMMON_INSTANCE((__ADCx__)) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ + __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 serie, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 serie, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32L4, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @} + */ /** * @} @@ -965,7 +1703,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); */ /** @addtogroup ADC_Exported_Functions_Group2 - * @brief IO operation functions + * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c index e43572a990c..249566e9a94 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c @@ -2,22 +2,20 @@ ****************************************************************************** * @file stm32l4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions - * ++ Start, stop, get result of conversions of injected - * group, using 2 possible modes: polling, interruption. + * ++ Start, stop, get result of conversions of ADC group injected, + * using 2 possible modes: polling, interruption. * ++ Calibration * +++ ADC automatic self-calibration * +++ Calibration factors get or set * ++ Multimode feature when available * + Control functions - * ++ Channels configuration on injected group + * ++ Channels configuration on ADC group injected * + State functions - * ++ Injected group queues management + * ++ ADC group injected contexts queue management * Other functions (generic functions) are available in file * "stm32l4xx_hal_adc.c". * @@ -83,10 +81,6 @@ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ -#define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR |\ - ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated - when no conversion is on-going (neither regular nor injected) */ - /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ @@ -95,7 +89,7 @@ /* 112 / 140,000 = 0.8 ms */ /* At maximum CPU speed (80 MHz), this means */ /* 0.8 ms * 80 MHz = 64000 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000) /*!< ADC calibration time-out value */ +#define ADC_CALIBRATION_TIMEOUT (64000U) /*!< ADC calibration time-out value */ /** * @} @@ -122,13 +116,13 @@ (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. - - (+) Start conversion of injected group. - (+) Stop conversion of injected group. - (+) Poll for conversion complete on injected group. - (+) Get result of injected channel conversion. - (+) Start conversion of injected group and enable interruptions. - (+) Stop conversion of injected group and disable interruptions. + + (+) Start conversion of ADC group injected. + (+) Stop conversion of ADC group injected. + (+) Poll for conversion complete on ADC group injected. + (+) Get result of ADC group injected channel conversion. + (+) Start conversion of ADC group injected and enable interruptions. + (+) Stop conversion of ADC group injected and disable interruptions. (+) When multimode feature is available, start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. @@ -144,9 +138,9 @@ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * This parameter can be one of the following values: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) @@ -157,7 +151,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + /* Process locked */ __HAL_LOCK(hadc); @@ -169,10 +163,13 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Select calibration mode single ended or differential ended */ MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff); @@ -186,8 +183,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ - /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -196,8 +194,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t } } - /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); } else { @@ -215,13 +215,12 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t } /** - * @brief Get the calibration factor from automatic conversion result. - * @param hadc: ADC handle. - * @param SingleDiff: Selection of single-ended or differential input - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @retval Converted value + * @brief Get the calibration factor. + * @param hadc ADC handle. + * @param SingleDiff This parameter can be only: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @retval Calibration value. */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) { @@ -229,7 +228,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - /* Return the selected ADC calibration value */ + /* Return the selected ADC calibration value */ if (SingleDiff == ADC_DIFFERENTIAL_ENDED) { return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); @@ -241,13 +240,13 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single } /** - * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going. - * @param hadc: ADC handle. - * @param SingleDiff: Selection of single-ended or differential input. - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum) + * @brief Set the calibration factor to overwrite automatic conversion result. + * ADC must be enabled and no conversion is ongoing. + * @param hadc ADC handle + * @param SingleDiff This parameter can be only: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) @@ -281,6 +280,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + /* Update ADC error code */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; @@ -301,7 +302,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc: ADC handle. + * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) @@ -353,9 +354,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - /* Update ADC state */ - /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY); + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - by default if ADC is Master or Independent or if multimode feature is not available @@ -365,11 +370,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - - /* Clear injected group conversion flag */ + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -388,8 +397,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: set ADSTART only if JAUTO is cleared */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) { SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; @@ -400,19 +407,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* hadc is the handle of a Slave ADC with dual injected conversions enabled: ADSTART is not set */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* Process unlocked */ - __HAL_UNLOCK(hadc); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); - } /* if (tmp_hal_status == HAL_OK) */ + } /* Return function status */ return tmp_hal_status; - } /* if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */ + } } /** @@ -428,7 +433,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). - * @param hadc: ADC handle. + * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -456,16 +461,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } @@ -479,23 +485,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /** * @brief Wait for injected group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is * checked and cleared depending on AUTDLY bit status. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart; - uint32_t tmp_Flag_End = 0x00; - ADC_TypeDef *tmpADC_Master; - uint32_t tmp_cfgr = 0x00; - uint32_t tmp_cfgr_jqm_autdly = 0x00; - uint32_t tmp_jeos_raised = 0x01; /* by default, assume that JEOS is set, - tmp_jeos_raised will be corrected - accordingly during API execution */ - + uint32_t tickstart = 0U; + uint32_t tmp_Flag_End = 0U; + uint32_t tmp_cfgr = 0U; + ADC_TypeDef *tmpADC_Master; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -531,47 +533,51 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } } - /* Next, to clear the polled flag as well as to update the handle State, - JEOS is checked and the relevant configuration registers are retrieved. - JQM, JAUTO and CONT bits will have to be read for the State update, - AUTDLY for JEOS clearing. */ - /* 1. Check whether or not JEOS is set */ - if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS)) - { - tmp_jeos_raised = 0; - } - /* 2. Check whether or not hadc is the handle of a Slave ADC with dual - injected conversions enabled. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET) - { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - check JQM and AUTDLY bits directly in ADC CFGR register */ - tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR); - } - else + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == SET) { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - need to check JQM and AUTDLY bits of Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR); - } - /* 3. Check whether or not hadc is the handle of a Slave ADC with dual - regular conversions enabled. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) - { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits directly in ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits of Master ADC CFGR register */ tmpADC_Master = ADC_MASTER_REGISTER(hadc); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger or by automatic injected conversion */ + /* from group regular. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || + ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + { + /* Check whether end of sequence is reached */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) + { + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + } /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_JEOS) @@ -580,46 +586,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ /* For injected groups, no new conversion will start before JEOS is */ /* cleared. */ - /* Note that 1. reading ADCx_JDRy clears JEOC. */ - /* 2. in multimode with dual injected conversions enabled (when */ - /* multimode feature is available), Master AUTDLY bit is */ - /* checked. */ - if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); } } else { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - } - - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - /* Are injected conversions over ? This is the case if JEOS is set AND - - injected conversions are software-triggered when injected queue management is disabled - OR - - auto-injection is enabled, continuous mode is disabled, - and regular conversions are software-triggered */ - - if (tmp_jeos_raised) - { - if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM)) - && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc))) )) - { - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); } - /* Return API HAL status */ return HAL_OK; } @@ -633,7 +609,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc: ADC handle. + * @param hadc ADC handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) @@ -649,7 +625,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) } else { - /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error @@ -684,8 +659,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY); + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - by default if ADC is Master or Independent or if multimode feature is not available @@ -694,11 +674,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - - /* Clear injected group conversion flag */ + + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) @@ -738,8 +723,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: set ADSTART only if JAUTO is cleared */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) { SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; @@ -750,8 +733,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* hadc is the handle of a Slave ADC with dual injected conversions enabled: ADSTART is not set */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* Process unlocked */ - __HAL_UNLOCK(hadc); } } else @@ -762,7 +743,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Return function status */ return tmp_hal_status; -} + } } /** @@ -781,7 +762,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -805,7 +786,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); @@ -813,17 +794,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } @@ -834,8 +816,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) return tmp_hal_status; } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. * @note Multimode must have been previously configured using @@ -846,9 +827,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * @note State field of Slave ADC handle is not updated in this configuration: * user should not rely on it for information related to Slave regular * conversions. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) - * @param pData: Destination Buffer address. - * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes). + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) + * @param pData Destination Buffer address. + * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -877,7 +858,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t if (tmphadcSlave.Instance == NULL) { - /* Update ADC state machine to error */ + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ @@ -886,7 +867,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t return HAL_ERROR; } - /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); @@ -898,15 +878,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) { - /* Update Master State */ - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - - + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), + HAL_ADC_STATE_REG_BUSY); + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -917,8 +896,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ @@ -927,20 +905,23 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); - + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { @@ -963,7 +944,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) @@ -1053,10 +1034,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) ADC_Disable(hadc); ADC_Disable(&tmphadcSlave); } - /* Change ADC state (ADC master) */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + /* Set ADC state (ADC master) */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } /* Process unlocked */ @@ -1068,7 +1050,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. - * @param hadc: ADC handle of ADC Master (handle of ADC Slave must not be used) + * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) @@ -1079,12 +1061,12 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Get ADC injected group conversion result. @@ -1105,8 +1087,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). - * @param hadc: ADC handle - * @param InjectedRank: the converted ADC injected rank. + * @param hadc ADC handle + * @param InjectedRank the converted ADC injected rank. * This parameter can be one of the following values: * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 @@ -1146,7 +1128,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa /** * @brief Injected conversion complete callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) @@ -1165,7 +1147,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) @@ -1180,7 +1162,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog 2 callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) @@ -1195,7 +1177,7 @@ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog 3 callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) @@ -1211,7 +1193,7 @@ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) /** * @brief End Of Sampling callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) @@ -1224,13 +1206,11 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) */ } - - /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) @@ -1261,9 +1241,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ @@ -1287,7 +1268,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) * disable interrution of end-of-conversion, * disable ADC peripheral if no conversion is on going * on injected group. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) @@ -1320,9 +1301,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) /* if no issue reported */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } else @@ -1346,7 +1328,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. * For multimode (when multimode feature is available), * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) @@ -1403,9 +1385,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } else @@ -1421,8 +1404,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) return tmp_hal_status; } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits @@ -1433,7 +1415,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) * @note In case of DMA configured in circular mode, function * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) @@ -1547,7 +1529,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* Return function status */ return tmp_hal_status; } -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -1600,19 +1582,18 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) * for each context (3 channels x 2 contexts = 6 calls). Conversion can * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. - * @param hadc: ADC handle - * @param sConfigInjected: Structure of ADC injected group and ADC channel for + * @param hadc ADC handle + * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_Common_TypeDef *tmpADC_Common; uint32_t tmpOffsetShifted; - uint32_t wait_loop_index = 0; + uint32_t wait_loop_index = 0U; - uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0; + uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1621,7 +1602,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); @@ -1677,9 +1658,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ - + if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1) ) + (sConfigInjected->InjectedNbrOfConversion == 1U) ) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1695,19 +1676,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) | - sConfigInjected->ExternalTrigInjecConv | - sConfigInjected->ExternalTrigInjecConvEdge ); + tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); + tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); } - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; @@ -1726,7 +1706,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ - if (hadc->InjectionConfig.ChannelCount == 0) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ @@ -1734,7 +1714,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ - hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000; + hadc->InjectionConfig.ContextQueue = 0x00000000U; /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ @@ -1746,21 +1726,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) | - sConfigInjected->ExternalTrigInjecConv | - sConfigInjected->ExternalTrigInjecConvEdge ); + tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) ); } - } /* if (hadc->InjectionConfig.ChannelCount == 0) */ + } - /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ @@ -1768,7 +1747,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Set the JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); - + /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; @@ -1779,7 +1758,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ - if (hadc->InjectionConfig.ChannelCount == 0) + if (hadc->InjectionConfig.ChannelCount == 0U) { MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } @@ -1801,7 +1780,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) | ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) ); } - /* If auto-injected mode is enabled: Injected discontinuous setting is */ + /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { @@ -1864,11 +1843,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - Right bit shift */ /* Enable OverSampling mode */ - - MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS, - ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift ); + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + sConfigInjected->InjecOversampling.Ratio | + sConfigInjected->InjecOversampling.RightBitShift + ); } else { @@ -1876,18 +1858,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } - /* Sampling time configuration of the selected channel */ - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) - { - /* Clear the old sample time and set the new one */ - ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */ - { - /* Clear the old sample time and set the new one */ - ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } +#if defined(ADC_SMPR1_SMPPLUS) + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if(sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); + } + else + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); + } +#else + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); +#endif /* Configure the offset: offset enable/disable, channel, offset value */ @@ -1895,75 +1887,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); - switch (sConfigInjected->InjectedOffsetNumber) + if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { - case ADC_OFFSET_1: - /* Configure offset register 1: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR1, - ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN, - ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_2: - /* Configure offset register 2: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR2, - ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN, - ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_3: - /* Configure offset register 3: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR3, - ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN, - ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_4: - /* Configure offset register 1: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR4, - ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN, - ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - /* Case ADC_OFFSET_NONE */ - default : - /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */ - if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + /* Set ADC selected offset number */ + LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); + + } + else + { + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is disabled. */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR1*/ - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR2*/ - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR3*/ - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } - if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR4*/ - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } - break; } - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ + } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ @@ -1971,32 +1923,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { + /* Set mode single-ended or differential input of the selected ADC channel */ + LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); + /* Configuration of differential mode */ - if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) - { - /* Disable differential mode (default mode: single-ended) */ - CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); - } - else + if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Enable differential mode */ - SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); - - /* Sampling time configuration of channel ADC_IN+1 (negative input). - Starting from channel 9, SMPR2 register must be configured. */ - if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9) - { - /* Clear the old sample time and set the new one */ - ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1); - } - else /* For channels 0 to 8 */ - { - /* Clear the old sample time and set the new one */ - ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1); - } + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); } - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ @@ -2004,18 +1940,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* HAL_ADC_DeInit(). */ /* Configuration of common ADC parameters */ - - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) - ) + if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || + ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || + ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) + ) { /* Configuration of common ADC parameters (continuation) */ /* Software is allowed to change common parameters only when all ADCs */ @@ -2027,11 +1960,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); while(wait_loop_index != 0) { wait_loop_index--; @@ -2042,16 +1975,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) { if (ADC_VREFINT_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); - } - } + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } + } } /* If the requested internal measurement path has already been enabled */ /* and other ADC of the common group are enabled, internal */ @@ -2065,7 +1998,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I } } - } /* if (ADC_IS_ENABLE(hadc) == RESET) */ + } /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -2074,7 +2007,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I return tmp_hal_status; } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: @@ -2087,8 +2020,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I * "ADC_MultiModeTypeDef". * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). - * @param hadc: Master ADC handle - * @param multimode : Structure of ADC multimode configuration + * @param hadc Master ADC handle + * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) @@ -2131,7 +2064,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) ) { /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* If multimode is selected, configure all multimode paramaters. */ /* Otherwise, reset multimode parameters (can be used in case of */ @@ -2155,8 +2088,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) { - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, - multimode->Mode | multimode->TwoSamplingDelay ); + MODIFY_REG(tmpADC_Common->CCR, + ADC_CCR_DUAL | + ADC_CCR_DELAY, + multimode->Mode | + multimode->TwoSamplingDelay + ); } } else /* ADC_MODE_INDEPENDENT */ @@ -2183,14 +2120,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable Injected Queue @@ -2198,7 +2134,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) @@ -2225,7 +2161,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) @@ -2248,7 +2184,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) * be carried out only when ADC is disabled. * @note To enable again the voltage regulator, the user is expected to * resort to HAL_ADC_Init() API. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) @@ -2278,7 +2214,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h index 7dc27f8cdb9..042c3b7548a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of ADC HAL extended module. ****************************************************************************** * @attention @@ -45,7 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -59,48 +57,16 @@ * @{ */ -/** - * @brief ADC group injected contexts queue configuration - */ -typedef struct -{ - uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each - HAL_ADCEx_InjectedConfigChannel() call to finally initialize - JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ - - uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ -}ADC_InjectionConfigTypeDef; - -/** - * @brief ADC handle Structure definition - */ -typedef struct -{ - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO uint32_t State; /*!< ADC communication state (bit-map of ADC states) */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ - - ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ -}ADC_HandleTypeDef; - /** - * @brief ADC Injected Conversion Oversampling structure definition + * @brief ADC Injected Conversion Oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADCEx_Oversampling_Ratio */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADCEx_Right_Bit_Shift */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ }ADC_InjOversamplingTypeDef; /** @@ -122,11 +88,11 @@ typedef struct typedef struct { uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. - This parameter can be a value of @ref ADC_channels + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. - This parameter must be a value of @ref ADCEx_injected_rank. + This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ @@ -134,7 +100,7 @@ typedef struct Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), @@ -144,7 +110,7 @@ typedef struct uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADCEx_SingleDifferential. + This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. @@ -154,7 +120,7 @@ typedef struct of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. - This parameter can be a value of @ref ADCEx_OffsetNumber. + This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. @@ -186,7 +152,7 @@ typedef struct Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. @@ -203,7 +169,7 @@ typedef struct uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_injected_external_trigger_source. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. @@ -211,18 +177,17 @@ typedef struct If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - - uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ - - ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -}ADC_InjectionConfTypeDef; + uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ +}ADC_InjectionConfTypeDef; + +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). @@ -231,19 +196,19 @@ typedef struct typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. - This parameter can be a value of @ref ADCEx_Common_mode. */ + This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) - This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */ + This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases. + This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ }ADC_MultiModeTypeDef; -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -251,7 +216,7 @@ typedef struct /* Exported constants --------------------------------------------------------*/ - /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants +/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants * @{ */ @@ -259,23 +224,23 @@ typedef struct * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /*!< Event 0 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /*!< Event 1 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /*!< Event 2 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 3 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /*!< Event 4 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 5 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 6 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /*!< Event 8 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) /*!< Event 9 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) /*!< Event 10 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) /*!< Event 12 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /*!< Event 15 triggers injected group conversion start */ -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers injected group conversion start */ +#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -283,288 +248,107 @@ typedef struct /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ -/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode +/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ -#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel set in single-ended input mode */ -#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /*!< ADC channel set in differential mode */ +#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ +#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ /** * @} */ -/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number +/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number * @{ */ -#define ADC_OFFSET_NONE ((uint32_t)0x00) /*!< No offset correction */ -#define ADC_OFFSET_1 ((uint32_t)0x01) /*!< Offset correction to apply to a first channel */ -#define ADC_OFFSET_2 ((uint32_t)0x02) /*!< Offset correction to apply to a second channel */ -#define ADC_OFFSET_3 ((uint32_t)0x03) /*!< Offset correction to apply to a third channel */ -#define ADC_OFFSET_4 ((uint32_t)0x04) /*!< Offset correction to apply to a fourth channel */ +#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ +#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ /** * @} */ -/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */ -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */ -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */ -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */ +#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ +#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ +#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ +#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ /** * @} */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */ -#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /*!< Combined regular simultaneous + injected simultaneous mode */ -#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /*!< Combined regular simultaneous + alternate trigger mode */ -#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Combined Interleaved mode + injected simultaneous mode */ -#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)) /*!< Injected simultaneous mode only */ -#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)) /*!< Regular simultaneous mode only */ -#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only */ -#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)) /*!< Alternate trigger mode only */ -/** - * @} - */ +#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ +#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ +#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ +#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ +#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ -/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA mode for multimode +/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ -#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ -#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ -#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ +#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ +#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** * @} */ -/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases +/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /*!< 1 ADC clock cycle delay */ -#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /*!< 2 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /*!< 3 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 4 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /*!< 5 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) /*!< 6 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */ +#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ /** * @} */ -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -/** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode - * @{ - */ -#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */ -/** - * @} - */ - -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ -/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection - * @{ - */ -#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /*!< Analog watchdog 1 selection */ -#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /*!< Analog watchdog 2 selection */ -#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /*!< Analog watchdog 3 selection */ /** * @} */ +#endif /* ADC_MULTIMODE_SUPPORT */ -/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode +/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) /*!< Analog watchdog applied to a regular group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to an injected group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to regular and injected groups all channels */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ +#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ +#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ /** * @} */ -/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group - * @{ - */ -#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) /*!< ADC regular group selection */ -#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC injected group selection */ -#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */ -/** - * @} - */ - -/** @defgroup ADCEx_Event_type ADC Extended Event Type - * @{ - */ -#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ -#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ -#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ -#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ -/** - * @} - */ -#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ - -/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition - * @{ - */ -#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ -#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ -#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ - -#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ - -/** - * @} - */ - -/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition - * @{ - */ -#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */ -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ -#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ -#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ -#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ -#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ -#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ -#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ - -#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ - -#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ - ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ - ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ - -/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ - ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ - ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ - -/** - * @} - */ - - -/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank - * @{ - */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */ -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */ -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */ -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */ -/** - * @} - */ - - - -/** @defgroup ADCEx_Oversampling_Ratio ADC Extended Oversampling Ratio - * @{ - */ - -#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */ -#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /*!< ADC Oversampling ratio 4x */ -#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /*!< ADC Oversampling ratio 8x */ -#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 16x */ -#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /*!< ADC Oversampling ratio 32x */ -#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 64x */ -#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!< ADC Oversampling ratio 128x */ -#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /*!< ADC Oversampling ratio 256x */ -/** - * @} - */ - -/** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift - * @{ - */ -#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ -#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC 1 bit shift for oversampling */ -#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC 2 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 3 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC 4 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)) /*!< ADC 5 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)) /*!< ADC 6 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 7 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC 8 bits shift for oversampling */ -/** - * @} - */ - -/** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling - * @{ - */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< A single trigger for all channel oversampled conversions */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /*!< A trigger for each oversampled conversion */ -/** - * @} - */ - -/** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode - * @{ - */ -#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /*!< Oversampling buffer maintained during injection sequence */ -#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during injection sequence */ -/** - * @} - */ - -/** @defgroup ADC_sampling_times ADC Sampling Times - * @{ - */ -#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000) /*!< Sampling time 2.5 ADC clock cycle */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR1_SMPPLUS) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time - replaces all sampling time 2.5 ADC clock cycles. These 2 sampling - times cannot be used simultaneously. */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ -#define ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles */ -#define ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */ -#define ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles */ -#define ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */ -#define ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 640.5 ADC clock cycles */ -/** - * @} - */ - /** @defgroup ADC_CFGR_fields ADCx CFGR fields * @{ */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ @@ -578,15 +362,15 @@ typedef struct ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /** * @} - */ + */ /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_SMPR1_SMPPLUS) #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ @@ -595,44 +379,44 @@ typedef struct #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ - ADC_SMPR1_SMP0) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ + ADC_SMPR1_SMP0) +#endif /** * @} - */ - + */ + /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) + (neither regular nor injected) is on-going */ +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) +#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) #else -#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) +#endif /** * @} - */ - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/** @defgroup ADCEx_DFSDM_Mode_Configuration ADC Extended DFSDM mode configuration + */ + +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) +/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define ADC_DFSDM_MODE_DISABLE ((uint32_t)0x00000000) /*!< DFSDM mode configuration disabled */ -#define ADC_DFSDM_MODE_ENABLE ((uint32_t)ADC_CFGR_DFSDMCFG) /*!< DFSDM mode configuration enabled */ +#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} - */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ - + */ +#endif + /** * @} */ /* Exported macros -----------------------------------------------------------*/ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros * @{ */ @@ -648,300 +432,179 @@ typedef struct * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases * mentionned above. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ - CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_DUAL) + LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) /** * @} */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ -/* Private macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros * @{ */ - +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (software start) or RESET (external trigger). */ -#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) /** * @brief Check if conversion is on going on regular or injected groups. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (conversion is on going) or RESET (no conversion is on going). */ #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ ) ? RESET : SET) - + /** * @brief Check if conversion is on going on injected group. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (conversion is on going) or RESET (no conversion is on going). */ -#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \ - ) ? RESET : SET) - +#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ + (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) + /** * @brief Check whether or not ADC is independent. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC3) \ )? \ SET \ : \ RESET \ - ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + ) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) #endif - -/** - * @brief Set the sample time for Channels numbers between 0 and 9. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__: Channel number. - * @retval None - */ -#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__))) - -/** - * @brief Set the sample time for Channels numbers between 10 and 18. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__: Channel number. - * @retval None - */ -#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10)))) - -/** - * @brief Write SMPR1 register. - * @param __HANDLE__ : ADC handle. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__ : Channel number. - * @retval None - */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - do { \ - if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \ - { \ - SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \ - { \ - CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - MODIFY_REG((__HANDLE__)->Instance->SMPR1, \ - ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \ - ADC_SMPR1((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \ - } while(0) -#else -#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - MODIFY_REG((__HANDLE__)->Instance->SMPR1, \ - ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \ - ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__))) -#endif - -/** - * @brief Write SMPR2 register. - * @param __HANDLE__ : ADC handle. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__ : Channel number. - * @retval None - */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - do { \ - if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \ - { \ - SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \ - { \ - CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - MODIFY_REG((__HANDLE__)->Instance->SMPR2, \ - ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \ - ADC_SMPR2((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \ - } while(0) -#else -#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - MODIFY_REG((__HANDLE__)->Instance->SMPR2, \ - ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \ - ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__))) -#endif - - -/** - * @brief Set the selected regular Channel rank for rank between 1 and 4. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__))) - -/** - * @brief Set the selected regular Channel rank for rank between 5 and 9. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5))) - -/** - * @brief Set the selected regular Channel rank for rank between 10 and 14. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10))) - -/** - * @brief Set the selected regular Channel rank for rank between 15 and 16. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15))) /** * @brief Set the selected injected Channel rank. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2)) - - -/** - * @brief Set the Analog Watchdog 1 channel. - * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1. - * @retval None - */ -#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH)) - -/** - * @brief Configure the channel number in Analog Watchdog 2 or 3. - * @param __CHANNEL__: ADC Channel + * @param __CHANNELNB__ Channel number. + * @param __RANKNB__ Rank number. * @retval None */ -#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__)) +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue - * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode. + * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. * @retval None - */ -#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM)) + */ +#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) /** * @brief Configure ADC discontinuous conversion mode for injected group - * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode. + * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. * @retval None */ -#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN)) +#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) /** * @brief Configure ADC discontinuous conversion mode for regular group - * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode. + * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. * @retval None - */ -#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN)) + */ +#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) + /** * @brief Configure the number of discontinuous conversions for regular group. - * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions. + * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. * @retval None */ -#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM)) +#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. - * @param __AUTOWAIT__: Auto delay bit enable or disable. + * @param __AUTOWAIT__ Auto delay bit enable or disable. * @retval None */ -#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY)) +#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) /** * @brief Configure ADC continuous conversion mode. - * @param __CONTINUOUS_MODE__: Continuous mode. + * @param __CONTINUOUS_MODE__ Continuous mode. * @retval None */ -#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT)) - +#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) + /** * @brief Configure the ADC DMA continuous request. - * @param __DMACONTREQ_MODE__: DMA continuous request mode. + * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None - */ -#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG)) - + */ +#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) /** * @brief Configure the channel number into offset OFRx register. - * @param __CHANNEL__: ADC Channel. + * @param __CHANNEL__ ADC Channel. * @retval None */ -#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH)) +#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) /** * @brief Configure the channel number into differential mode selection register. - * @param __CHANNEL__: ADC Channel. + * @param __CHANNEL__ ADC Channel. * @retval None */ #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) /** * @brief Configure calibration factor in differential mode to be set into calibration register. - * @param __CALIBRATION_FACTOR__: Calibration factor value. + * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval None */ -#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) +#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) + /** * @brief Calibration factor in differential mode to be retrieved from calibration register. - * @param __CALIBRATION_FACTOR__: Calibration factor value. + * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval None - */ -#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) - + */ +#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) + /** * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. - * @param __THRESHOLD__: Threshold value. + * @param __THRESHOLD__ Threshold value. * @retval None */ #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Configure the ADC DMA continuous request for ADC multimode. - * @param __DMACONTREQ_MODE__: DMA continuous request mode. + * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None - */ -#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG)) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ - + */ +#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) /** * @brief Verification of hardware constraints before ADC can be enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) */ #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ @@ -950,10 +613,10 @@ typedef struct ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ ) == RESET \ ) ? SET : RESET) - + /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_DISABLE(__HANDLE__) \ @@ -961,17 +624,17 @@ typedef struct (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ } while(0) - + /** * @brief Verification of hardware constraints before ADC can be disabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) */ #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ (( ( ((__HANDLE__)->Instance->CR) & \ (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ ) ? SET : RESET) - + /** * @brief Shift the offset with respect to the selected ADC resolution. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. @@ -980,8 +643,8 @@ typedef struct * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). - * @param __HANDLE__: ADC handle - * @param __OFFSET__: Value to be shifted + * @param __HANDLE__ ADC handle + * @param __OFFSET__ Value to be shifted * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ @@ -996,8 +659,8 @@ typedef struct * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). - * @param __HANDLE__: ADC handle - * @param __THRESHOLD__: Value to be shifted + * @param __HANDLE__ ADC handle + * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ @@ -1010,8 +673,8 @@ typedef struct * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). * If resolution 8 bits, no shift. * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). - * @param __HANDLE__: ADC handle - * @param __THRESHOLD__: Value to be shifted + * @param __HANDLE__ ADC handle + * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ @@ -1019,20 +682,9 @@ typedef struct ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ (__THRESHOLD__) << 2 ) -/** - * @brief Report ADC common register. - * @param __HANDLE__: ADC handle. - * @retval Common control register - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define ADC_COMMON_REGISTER(__HANDLE__) (ADC1_COMMON) -#endif - /** * @brief Report Master Instance. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return same instance if ADC of input handle is independent ADC or if * multimode feature is not available. * @retval Master Instance @@ -1045,17 +697,17 @@ typedef struct : \ (ADC1) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance) #endif - + /** * @brief Clear Common Control Register. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \ +#if defined(ADC_MULTIMODE_SUPPORT) +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATEN | \ ADC_CCR_TSEN | \ @@ -1064,22 +716,22 @@ typedef struct ADC_CCR_DMACFG | \ ADC_CCR_DELAY | \ ADC_CCR_DUAL ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \ +#else +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATEN | \ ADC_CCR_TSEN | \ ADC_CCR_VREFEN ) -#endif - - -/** + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** * @brief Check whether or not dual conversions are enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? \ @@ -1087,38 +739,37 @@ typedef struct : \ RESET \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#else #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET) -#endif - +#endif + /** * @brief Check whether or not dual regular conversions are enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? \ - ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ - (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ - (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ + ( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ + (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ + (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ : \ RESET \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#else #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET) #endif - /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return SET if multimode feature is not available. * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -1126,17 +777,17 @@ typedef struct : \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET) -#endif - +#endif + /** * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return SET if multimode feature is not available. * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -1144,18 +795,18 @@ typedef struct : \ ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined( STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET) -#endif +#endif /** * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return SET if multimode feature is not available. * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -1164,26 +815,26 @@ typedef struct ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET) -#endif - +#endif + /** * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter. - * @param __INSTANCE__: ADC instance. + * @param __INSTANCE__ ADC instance. * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \ (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ ) ? SET : RESET) - + /** * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_ANY_OTHER_ENABLED(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) \ )? \ @@ -1195,99 +846,94 @@ typedef struct : \ ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET) -#endif - +#endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. - * @param __HANDLE_MASTER__: ADC master handle. - * @param __HANDLE_SLAVE__: ADC slave handle. - * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL. + * @param __HANDLE_MASTER__ ADC master handle. + * @param __HANDLE_SLAVE__ ADC slave handle. + * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ +#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ - /** * @brief Check whether or not multimode is configured in DMA mode. + * @param __HANDLE__ ADC handle. * @note Return RESET if multimode feature is not available. * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_MULTIMODE_DMA_ENABLED() \ + */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \ ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \ || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS)) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define ADC_MULTIMODE_DMA_ENABLED() (RESET) -#endif - +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET) +#endif /** * @brief Verify the ADC instance connected to the temperature sensor. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -/* The temperature sensor measurement path (channel 17) is available on ADC1 */ + */ +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/* The temperature sensor measurement path (channel 17) is available on ADC1 */ #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ +/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) #endif /** * @brief Verify the ADC instance connected to the battery voltage VBAT. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -/* The battery voltage measurement path (channel 18) is available on ADC1 */ + */ +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/* The battery voltage measurement path (channel 18) is available on ADC1 */ #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ +/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) #endif /** * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -/* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ + */ +/* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) - /** * @brief Verify the length of scheduled injected conversions group. - * @param __LENGTH__: number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) - */ -#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) - - + */ +#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) + /** * @brief Calibration factor size verification (7 bits maximum). - * @param __CALIBRATION_FACTOR__: Calibration factor value. + * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) */ -#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F)) +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) + - /** * @brief Verify the ADC channel setting. - * @param __HANDLE__: ADC handle. - * @param __CHANNEL__: programmed ADC channel. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == ADC_CHANNEL_1) || \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -1305,12 +951,14 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_18) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT))) + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == ADC_CHANNEL_1) || \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -1326,6 +974,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ @@ -1346,7 +995,9 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_15) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_18))) || \ + ((__CHANNEL__) == ADC_CHANNEL_18) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -1363,16 +1014,18 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) ))) + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) #endif - + /** * @brief Verify the ADC channel setting in differential mode. - * @param __HANDLE__: ADC handle. - * @param __CHANNEL__: programmed ADC channel. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + */ +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1390,9 +1043,9 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_15) ) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, - channels 0, 16 to 18 can be only used in single-ended mode. + channels 0, 16 to 18 can be only used in single-ended mode. For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, - channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ + channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ (((__HANDLE__)->Instance) == ADC2)) && \ (((__CHANNEL__) == ADC_CHANNEL_1) || \ @@ -1421,21 +1074,21 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) ))) -#endif - -/** +#endif + +/** * @brief Verify the ADC single-ended input or differential mode setting. - * @param __SING_DIFF__: programmed channel setting. + * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) - */ + */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) - + /** * @brief Verify the ADC offset management setting. - * @param __OFFSET_NUMBER__: ADC offset management. + * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) - */ + */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ @@ -1444,7 +1097,7 @@ typedef struct /** * @brief Verify the ADC injected channel setting. - * @param __CHANNEL__: programmed ADC injected channel. + * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ @@ -1454,31 +1107,31 @@ typedef struct /** * @brief Verify the ADC injected conversions external trigger. - * @param __INJTRIG__: programmed ADC injected conversions external trigger. + * @param __HANDLE__ ADC handle. + * @param __INJTRIG__ programmed ADC injected conversions external trigger. * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) - */ -#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - \ - ((__INJTRIG__) == ADC_SOFTWARE_START) ) + */ +#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) /** * @brief Verify the ADC edge trigger setting for injected group. - * @param __EDGE__: programmed ADC edge trigger setting. + * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) */ #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ @@ -1486,10 +1139,10 @@ typedef struct ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Verify the ADC multimode setting. - * @param __MODE__: programmed ADC multimode setting. + * @param __MODE__ programmed ADC multimode setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ @@ -1499,11 +1152,11 @@ typedef struct ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ ((__MODE__) == ADC_DUALMODE_INTERL) || \ - ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) /** * @brief Verify the ADC multimode DMA access setting. - * @param __MODE__: programmed ADC multimode DMA access setting. + * @param __MODE__ programmed ADC multimode DMA access setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ @@ -1512,7 +1165,7 @@ typedef struct /** * @brief Verify the ADC multimode delay setting. - * @param __DELAY__: programmed ADC multimode delay setting. + * @param __DELAY__ programmed ADC multimode delay setting. * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) */ #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ @@ -1527,11 +1180,11 @@ typedef struct ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Verify the ADC analog watchdog setting. - * @param __WATCHDOG__: programmed ADC analog watchdog setting. + * @param __WATCHDOG__ programmed ADC analog watchdog setting. * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ @@ -1540,7 +1193,7 @@ typedef struct /** * @brief Verify the ADC analog watchdog mode setting. - * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting. + * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ @@ -1553,7 +1206,7 @@ typedef struct /** * @brief Verify the ADC conversion (regular or injected or both). - * @param __CONVERSION__: ADC conversion group. + * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ @@ -1562,7 +1215,7 @@ typedef struct /** * @brief Verify the ADC event type. - * @param __EVENT__: ADC event. + * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ @@ -1574,9 +1227,9 @@ typedef struct /** * @brief Verify the ADC oversampling ratio. - * @param __RATIO__: programmed ADC oversampling ratio. + * @param __RATIO__ programmed ADC oversampling ratio. * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) - */ + */ #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ @@ -1588,9 +1241,9 @@ typedef struct /** * @brief Verify the ADC oversampling shift. - * @param __SHIFT__: programmed ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) - */ + */ #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ @@ -1603,63 +1256,62 @@ typedef struct /** * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__: programmed ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** * @brief Verify the ADC oversampling regular conversion resumed or continued mode. - * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode. + * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) - /** * @brief Verify the DFSDM mode configuration. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) #else #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /** - * @brief Return the DFSDM configuration mode. - * @param __HANDLE__: ADC handle. + * @brief Return the DFSDM configuration mode. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval DFSDM configuration mode */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) #else #define ADC_CFGR_DFSDM(__HANDLE__) (0x0) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ - +#endif + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ - */ - + */ + /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ - */ + */ /* IO operation functions *****************************************************/ /* ADC calibration */ @@ -1675,13 +1327,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* h /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + +#if defined(ADC_MULTIMODE_SUPPORT) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); @@ -1693,26 +1345,26 @@ void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* h void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); -/* ADC Regular conversions stop */ +/* ADC group regular conversions stop */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ - + /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); @@ -1725,10 +1377,10 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* h /** * @} */ - + /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c index 9dfd4d0bec5..a78181d858d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c @@ -2,74 +2,131 @@ ****************************************************************************** * @file stm32l4xx_hal_can.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim - ============================================================================== + ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (++) Connect and configure the involved CAN pins using the - following function HAL_GPIO_Init(); - - (#) Initialize and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or - HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + @endverbatim - ****************************************************************************** * @attention * @@ -107,1099 +164,1679 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10 +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** - * @brief Initialize the CAN peripheral according to the specified parameters - * in the CAN_InitStruct structure and initialize the associated handle. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - if(hcan->State == HAL_CAN_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + return HAL_ERROR; } + } - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - status = CAN_INITSTATUS_SUCCESS; + return HAL_ERROR; } } - - if(status == CAN_INITSTATUS_SUCCESS) + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -} - -/** - * @brief Configure the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; - -#if defined(CAN2) - /* Select the start slave bank */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); -#endif - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filternbrbitpos; - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filternbrbitpos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - CAN1->FA1R |= filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CAN peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } /** - * @brief Initialize the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** - * @brief DeInitialize the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ } + /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + @endverbatim * @{ */ /** - * @brief Initiate and transmit a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Timeout duration. - * @retval HAL status + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0; + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - transmitmailbox = 0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } - else + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiate and transmit a CAN frame message in Interrupt mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0U; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + if (hcan->State == HAL_CAN_STATE_READY) { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME ); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; } else { - return HAL_BUSY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; } - - return HAL_OK; } /** - * @brief Receive a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. - * @param Timeout: Timeout duration. + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + uint32_t tickstart = 0U; + + if (hcan->State == HAL_CAN_STATE_LISTENING) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - } - - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; } else { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Check if timeout is reached */ + if (++count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + status = 1U; + } } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); /* Return function status */ - return HAL_OK; + return status; } /** - * @brief Receive a correct CAN frame in Interrupt mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { + uint32_t transmitmailbox; + /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); } - else + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); } - + + /* Return function status */ + return HAL_OK; } else { - return HAL_BUSY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; } - - /* Return function status */ - return HAL_OK; } /** - * @brief Enter the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @retval Number of free Tx Mailboxes. */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + uint32_t freelevel = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + { + freelevel++; + } - /* Return function status */ - return HAL_ERROR; + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + status = 1U; } } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; + + /* Return status */ + return status; } /** - * @brief Wake up the CAN peripheral from sleep mode (after that the CAN peripheral - * is in the normal mode). - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + uint32_t timestamp = 0U; + uint32_t transmitmailbox; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); } + + /* Return function status */ + return HAL_OK; } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + return HAL_ERROR; } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; } /** - * @brief Handle CAN interrupt request. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) { - if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != RESET) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); } } - - /* Check End of reception flag for FIFO0 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } } - - /* Check End of reception flag for FIFO1 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } } - - /* Check Error Warning Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - /* No need for clear of Error Warning Flag as read-only */ + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } } - - /* Check Error Passive Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } } - - /* Check Bus-Off Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - /* No need for clear of Bus-Off Flag as read-only */ + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } } - - /* Check Last error code Flag */ - if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) { - switch(hcan->Instance->ESR & CAN_ESR_LEC) + if ((msrflags & CAN_MSR_SLAKI) != RESET) { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) + { + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) + { + if ((msrflags & CAN_MSR_ERRI) != RESET) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); } /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + if (errorcode != HAL_CAN_ERROR_NONE) { - /* Clear ERRI bit */ - SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + /* Call Error callback function */ + /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - } + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ } /** - * @brief Transmission complete callback in non-blocking mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file */ } /** - * @brief Reception complete callback in non-blocking mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1208,7 +1845,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } @@ -1217,192 +1854,110 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process. - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief Return the CAN handle state. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { - /* Return CAN handle state */ - return hcan->State; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + + /* Return CAN state */ + return state; } /** * @brief Return the CAN error code. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -/** - * @brief Initiate and transmit a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + HAL_StatusTypeDef status = HAL_OK; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; + + /* Return the status */ + return status; } /** - * @brief Receive a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status + * @} */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - /* Return function status */ - return HAL_OK; -} /** - * @} - */ + * @} + */ #endif /* HAL_CAN_MODULE_ENABLED */ + /** * @} */ +#endif /* CAN1 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h index f71bf09454b..87a0fb0ba8d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_can.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -36,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_CAN_H -#define __STM32L4xx_CAN_H +#ifndef STM32L4xx_HAL_CAN_H +#define STM32L4xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -58,63 +57,60 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -123,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -152,23 +151,27 @@ typedef struct This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ @@ -177,70 +180,67 @@ typedef struct This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ - - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ - - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + CAN_TypeDef *Instance; /*!< Register base address */ - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - HAL_LockTypeDef Lock; /*!< CAN locking object */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - __IO uint32_t ErrorCode; /*!< CAN Error code */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -248,25 +248,39 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ -#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ -#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ -/** @defgroup CAN_InitStatus CAN initialization Status +/** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -274,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -286,7 +300,7 @@ typedef struct /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -297,7 +311,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -320,7 +334,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -335,8 +349,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -344,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -353,8 +367,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -362,8 +376,8 @@ typedef struct /** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -371,332 +385,329 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ /** * @} */ -/** @defgroup CAN_flags CAN Flags +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ +/** @defgroup CAN_flags CAN Flags + * @{ + */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ -/** @defgroup CAN_interrupts CAN Interrupts + +/** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ - +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - /** * @} */ /* Exported macros -----------------------------------------------------------*/ -/** @defgroup CAN_Exported_Macro CAN Exported Macros +/** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state. - * @param __HANDLE__: CAN handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** - * @brief Enable the specified CAN interrupt. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt. + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** - * @brief Disable the specified CAN interrupt. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt. + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) +/** + * @} + */ -/** @brief Check whether the specified CAN interrupt source is enabled or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); /** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + * @} + */ +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); /** - * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + * @} + */ -/** - * @brief Cancel a transmit request. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFO can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management * @{ */ -/* addtogroup and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions * @{ */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + /** * @} - */ + */ /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants +/** @defgroup CAN_Private_Types CAN Private Types * @{ */ -/** @defgroup CAN_transmit_constants CAN Transmit Constants + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ + /** * @} */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) - +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ @@ -705,64 +716,69 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) - +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) - #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) - #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) - -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) - -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) - -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) - -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) - #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) /** * @} */ - -/* Private functions ---------------------------------------------------------*/ +/* End of private macros -----------------------------------------------------*/ /** * @} */ + +#endif /* CAN1 */ /** * @} */ - #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_CAN_H */ +#endif /* STM32L4xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c new file mode 100644 index 00000000000..7e93892d6ae --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c @@ -0,0 +1,1480 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### User NOTE ##### + ============================================================================== + [..] + (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations. + Another HAL CAN driver version has been designed with new API's, to fix these limitations. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (++) Connect and configure the involved CAN pins using the + following function HAL_GPIO_Init(); + + (#) Initialize and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or + HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#ifdef HAL_CAN_MODULE_ENABLED +/* Select HAL CAN module in stm32l4xx_hal_conf.h file: + (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations + (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */ +#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32l4xx_hal_conf.h file' +#endif /* HAL_CAN_MODULE_ENABLED */ + +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10 +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CAN peripheral according to the specified parameters + * in the CAN_InitStruct structure and initialize the associated handle. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ + uint32_t tickstart = 0; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + status = CAN_INITSTATUS_SUCCESS; + } + } + + if(status == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; + +#if defined(CAN2) + /* Select the start slave bank */ + CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); +#endif + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filternbrbitpos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + CAN1->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CAN peripheral registers to their default reset values. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiate and transmit a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiate and transmit a CAN frame message in Interrupt mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + } + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame in Interrupt mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + } + else + { + return HAL_BUSY; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enter the Sleep (low power) mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wake up the CAN peripheral from sleep mode (after that the CAN peripheral + * is in the normal mode). + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle CAN interrupt request. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + } + + /* Check End of reception flag for FIFO0 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + /* Check End of reception flag for FIFO1 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Check Error Warning Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-Off Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + /* No need for clear of Bus-Off Flag as read-only */ + } + + /* Check Last error code Flag */ + if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + switch(hcan->Instance->ESR & CAN_ESR_LEC) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI bit */ + SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); + + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non-blocking mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reception complete callback in non-blocking mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN handle state. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN handle state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +/** + * @brief Initiate and transmit a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame. + * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: Specify the FIFO number + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Disable CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* CAN1 */ + +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h new file mode 100644 index 00000000000..08fd1017dc3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h @@ -0,0 +1,769 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_can_legacy.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_CAN_LEGACY_H +#define __STM32L4xx_CAN_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(CAN1) +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t BankNumber; /*!< Select the start slave bank filter. + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO uint32_t ErrorCode; /*!< CAN Error code */ + +}CAN_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ +#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ +#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN initialization Status + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +/** + * @} + */ + +/** @defgroup CAN_interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ + +/** + * @} + */ + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macro CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state. + * @param __HANDLE__: CAN handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupt. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt. + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupt. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt. + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + + +/** @brief Check whether the specified CAN interrupt source is enabled or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __INTERRUPT__: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + + + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disable the DBG Freeze for CAN. + * @param __HANDLE__: specifies the CAN Handle. + * @param __NEWSTATE__: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFO can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* addtogroup and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +/** @defgroup CAN_transmit_constants CAN Transmit Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +/** + * @} + */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FF) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) + +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) + +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) + +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) + +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) + +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) + +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* CAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CAN_LEGACY_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c index aea11067d41..a6d00340ee3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_comp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: @@ -17,36 +15,34 @@ ================================================================================ ##### COMP Peripheral features ##### ================================================================================ - - [..] - The STM32L4xx device family integrates two analog comparators instances - COMP1 and COMP2: - (#) The COMP input minus (inverting input) and input plus (non inverting input) + + [..] + The STM32L4xx device family integrates two analog comparators instances: + COMP1, COMP2. + (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). - - (#) The COMP output level is available using HAL_COMP_GetOutputLevel() + + (#) Comparators output level is available using HAL_COMP_GetOutputLevel() and can be redirected to other peripherals: GPIO pins (in mode alternate functions for comparator), timers. (refer to GPIO list in reference manual). - + + (#) The comparators have interrupt capability through the EXTI controller + with wake-up from sleep and stop modes. + (#) Pairs of comparators instances can be combined in window mode (2 consecutive instances odd and even COMP and COMP). - - (#) The comparators have interrupt capability through the EXTI controller - with wake-up from sleep and stop modes: - (++) COMP1 is internally connected to EXTI Line 21 - (++) COMP2 is internally connected to EXTI Line 22 - + From the corresponding IRQ handler, the right interrupt source can be retrieved - using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG(). + using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). ##### How to use this driver ##### ================================================================================ [..] This driver provides functions to configure and program the comparator instances of STM32L4xx devices. - + To use the comparator, perform the following steps: (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): @@ -63,7 +59,7 @@ (++) Select the input plus (non-inverting input) (++) Select the hysteresis (++) Select the blanking source - (++) Select the output polarity + (++) Select the output polarity (++) Select the power mode (++) Select the window mode @@ -153,6 +149,10 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" +#ifdef HAL_COMP_MODULE_ENABLED + +#if defined (COMP1) || defined (COMP2) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -162,8 +162,6 @@ * @{ */ -#ifdef HAL_COMP_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup COMP_Private_Constants @@ -175,15 +173,15 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US ((uint32_t) 80U) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (80U) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART_SCALER"). */ /* Unit: us */ -#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200U) /*!< Delay for COMP voltage scaler stabilization time */ -#define COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t) 30U) +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /** * @} @@ -221,10 +219,10 @@ */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { - uint32_t tmp_csr = 0; - uint32_t exti_line = 0; - uint32_t comp_voltage_scaler_not_initialized = 0; - __IO uint32_t wait_loop_index = 0; + uint32_t tmp_csr = 0U; + uint32_t exti_line = 0U; + uint32_t comp_voltage_scaler_not_initialized = 0U; + __IO uint32_t wait_loop_index = 0U; HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ @@ -269,15 +267,16 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) == 0); /* Set COMP parameters */ - tmp_csr = (hcomp->Init.InvertingInput | - hcomp->Init.NonInvertingInput | - hcomp->Init.BlankingSrce | - hcomp->Init.Hysteresis | - hcomp->Init.OutputPol | - hcomp->Init.Mode ); + tmp_csr = ( hcomp->Init.NonInvertingInput + | hcomp->Init.InvertingInput + | hcomp->Init.BlankingSrce + | hcomp->Init.Hysteresis + | hcomp->Init.OutputPol + | hcomp->Init.Mode + ); /* Set parameters in COMP register */ - /* Note: Update all bits except read-only, lock and enable bits */ + /* Note: Update all bits except read-only, lock and enable bits */ #if defined (COMP_CSR_INMESEL) MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | @@ -309,14 +308,14 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ - if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0) && - (comp_voltage_scaler_not_initialized != 0) ) + if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0U) && + (comp_voltage_scaler_not_initialized != 0U) ) { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2U))); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -331,53 +330,53 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET) { - SET_BIT(EXTI->RTSR1, exti_line); + LL_EXTI_EnableRisingTrig_0_31(exti_line); } else { - CLEAR_BIT(EXTI->RTSR1, exti_line); + LL_EXTI_DisableRisingTrig_0_31(exti_line); } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET) { - SET_BIT(EXTI->FTSR1, exti_line); + LL_EXTI_EnableFallingTrig_0_31(exti_line); } else { - CLEAR_BIT(EXTI->FTSR1, exti_line); + LL_EXTI_DisableFallingTrig_0_31(exti_line); } /* Clear COMP EXTI pending bit (if any) */ - WRITE_REG(EXTI->PR1, exti_line); + LL_EXTI_ClearFlag_0_31(exti_line); /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET) { - SET_BIT(EXTI->EMR1, exti_line); + LL_EXTI_EnableEvent_0_31(exti_line); } else { - CLEAR_BIT(EXTI->EMR1, exti_line); + LL_EXTI_DisableEvent_0_31(exti_line); } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET) { - SET_BIT(EXTI->IMR1, exti_line); + LL_EXTI_EnableIT_0_31(exti_line); } else { - CLEAR_BIT(EXTI->IMR1, exti_line); + LL_EXTI_DisableIT_0_31(exti_line); } } else { /* Disable EXTI event mode */ - CLEAR_BIT(EXTI->EMR1, exti_line); + LL_EXTI_DisableEvent_0_31(exti_line); /* Disable EXTI interrupt mode */ - CLEAR_BIT(EXTI->IMR1, exti_line); + LL_EXTI_DisableIT_0_31(exti_line); } /* Set HAL COMP handle state */ @@ -414,7 +413,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set COMP_CSR register to reset value */ - WRITE_REG(hcomp->Instance->CSR, 0x00000000); + WRITE_REG(hcomp->Instance->CSR, 0x00000000U); /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ HAL_COMP_MspDeInit(hcomp); @@ -485,7 +484,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ @@ -510,8 +509,8 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U))); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -573,7 +572,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Check COMP EXTI flag */ - if(READ_BIT(EXTI->PR1, exti_line) != RESET) + if(LL_EXTI_IsActiveFlag_0_31(exti_line) != RESET) { /* Check whether comparator is in independent or window mode */ if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != RESET) @@ -585,12 +584,12 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /* (low or high ) to the other "out of window" area (high or low).*/ /* Both flags must be cleared to call comparator trigger */ /* callback is called once. */ - WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); + LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else { /* Clear COMP EXTI line pending bit */ - WRITE_REG(EXTI->PR1, exti_line); + LL_EXTI_ClearFlag_0_31(exti_line); } /* COMP trigger user callback */ @@ -666,8 +665,8 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * voltage than the input minus * @param hcomp COMP handle * @retval Returns the selected comparator output level: - * @arg @ref COMP_OUTPUT_LEVEL_LOW - * @arg @ref COMP_OUTPUT_LEVEL_HIGH + * @arg COMP_OUTPUT_LEVEL_LOW + * @arg COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) @@ -741,7 +740,6 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @} */ -#endif /* HAL_COMP_MODULE_ENABLED */ /** * @} */ @@ -750,4 +748,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @} */ +#endif /* COMP1 || COMP2 */ + +#endif /* HAL_COMP_MODULE_ENABLED */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h index 2787ba45729..142639e679b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_comp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention @@ -43,8 +41,11 @@ extern "C" { #endif +#if defined (COMP1) || defined (COMP2) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#include "stm32l4xx_ll_exti.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -98,14 +99,14 @@ typedef struct /** * @brief HAL COMP state machine: HAL COMP states definition */ -#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10) +#define COMP_STATE_BITFIELD_LOCK (0x10U) typedef enum { - HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized */ + HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */ HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */ - HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */ HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ - HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ + HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ }HAL_COMP_StateTypeDef; @@ -132,9 +133,8 @@ typedef struct /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ - /** * @} */ @@ -145,7 +145,7 @@ typedef struct /* Note: For the characteritics of comparator power modes */ /* (propagation delay and power consumption), */ /* refer to device datasheet. */ -#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< High Speed */ #define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ #define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */ /** @@ -155,7 +155,7 @@ typedef struct /** @defgroup COMP_InputPlus COMP input plus (non-inverting input) * @{ */ -#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -175,7 +175,7 @@ typedef struct #if defined(DAC_CHANNEL2_SUPPORT) #define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ #endif -#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ +#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ #define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ #if defined(COMP_CSR_INMESEL_1) #define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */ @@ -189,10 +189,10 @@ typedef struct /** @defgroup COMP_Hysteresis COMP hysteresis * @{ */ -#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */ -#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0) /*!< Hysteresis level low */ -#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1) /*!< Hysteresis level medium */ -#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST) /*!< Hysteresis level high */ +#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ /** * @} */ @@ -200,7 +200,7 @@ typedef struct /** @defgroup COMP_OutputPolarity COMP output Polarity * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ #define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ /** * @} @@ -209,35 +209,13 @@ typedef struct /** @defgroup COMP_BlankingSrce COMP blanking source * @{ */ -/* Note: Some blanking sources are not available depending on timer */ -/* availability or devices specificities */ -/* (STM32L43xx, STM32L44xx, STM32L45xx, STM32L46xx) */ -#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */ -/* Blanking sources for COMP instance: COMP1 */ -#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0) /*!< Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator */ -#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1) /*!< Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator */ -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) -#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2) /*!< Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - -/* Blanking sources for COMP instance: COMP2 */ -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) -#define COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0) /*!< Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) -#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1) /*!< Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ -#define COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2) /*!< Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator */ +#define COMP_BLANKINGSRC_NONE (0x00000000U) /*!RTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line rising edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** @@ -370,135 +348,135 @@ typedef struct * @retval None */ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** * @brief Enable the COMP1 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Generate a software interrupt on the COMP1 EXTI line. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Check whether the COMP1 EXTI line flag is set. * @retval RESET or SET */ -#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Clear the COMP1 EXTI flag. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line rising edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line falling edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line falling edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Enable the COMP2 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Generate a software interrupt on the COMP2 EXTI line. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Check whether the COMP2 EXTI line flag is set. * @retval RESET or SET */ -#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Clear the COMP2 EXTI flag. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2) /** * @} @@ -514,11 +492,12 @@ typedef struct /** @defgroup COMP_Private_Constants COMP Private Constants * @{ */ + /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ -#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM21) /*!< EXTI line 21 connected to COMP1 output */ -#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM22) /*!< EXTI line 22 connected to COMP2 output */ +#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output */ +#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output */ /** * @} */ @@ -526,10 +505,10 @@ typedef struct /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ -#define COMP_EXTI_IT ((uint32_t) 0x01) /*!< EXTI line event with interruption */ -#define COMP_EXTI_EVENT ((uint32_t) 0x02) /*!< EXTI line event only (without interruption) */ -#define COMP_EXTI_RISING ((uint32_t) 0x10) /*!< EXTI line event on rising edge */ -#define COMP_EXTI_FALLING ((uint32_t) 0x20) /*!< EXTI line event on falling edge */ +#define COMP_EXTI_IT (0x01U) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT (0x02U) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING (0x10U) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING (0x20U) /*!< EXTI line event on falling edge */ /** * @} */ @@ -551,8 +530,8 @@ typedef struct * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ -#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? \ - COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) /** * @} */ @@ -576,7 +555,7 @@ typedef struct ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)) #endif -/* Note: On this STM32 family, comparator input minus parameters are */ +/* Note: On this STM32 serie, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ @@ -630,74 +609,29 @@ typedef struct #define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \ ((__POL__) == COMP_OUTPUTPOL_INVERTED)) -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) - -#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)) - -#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) - -#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)) - -#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) - -#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)) - -#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ + ) + +#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) + #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ @@ -785,6 +719,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); } #endif +#endif /* COMP1 || COMP2 */ + #endif /* __STM32L4xx_HAL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h index d0a45d7df2e..5ad54eb7133 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32l4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 - * @brief HAL configuration file. + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. ****************************************************************************** * @attention * @@ -52,7 +52,9 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED +// For MBED we use the CAN legacy for now +//#define HAL_CAN_MODULE_ENABLED +#define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -62,8 +64,10 @@ #define HAL_DFSDM_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_DMA2D_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED #define HAL_FIREWALL_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED +#define HAL_GFXMMU_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED #define HAL_NAND_MODULE_ENABLED @@ -75,7 +79,9 @@ #define HAL_IWDG_MODULE_ENABLED #define HAL_LCD_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED #define HAL_OPAMP_MODULE_ENABLED +#define HAL_OSPI_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_QSPI_MODULE_ENABLED @@ -239,6 +245,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ @@ -263,6 +273,10 @@ #include "stm32l4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -303,10 +317,18 @@ #include "stm32l4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -379,6 +401,10 @@ #include "stm32l4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /* ALL MBED targets use same stm32_assert.h */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c index c39d7c6d14a..99afff61e42 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cortex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -337,6 +335,9 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPre */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } @@ -352,6 +353,9 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } @@ -365,6 +369,9 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -426,6 +433,46 @@ __weak void HAL_SYSTICK_Callback(void) } #if (__MPU_PRESENT == 1) +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} + /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h index 037c29e4723..f3eea8a70c1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention @@ -289,40 +287,6 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -#if (__MPU_PRESENT == 1) -/** - * @brief Disable the MPU. - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} -#endif /* __MPU_PRESENT */ /** * @} */ @@ -343,6 +307,8 @@ void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c index 5e1d25a24ac..ffa5acb0343 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c @@ -2,15 +2,13 @@ ****************************************************************************** * @file stm32l4xx_hal_crc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 - * @brief CRC HAL module driver. - * This file provides firmware functions to manage the following + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: * + Initialization and de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim =============================================================================== ##### How to use this driver ##### @@ -22,11 +20,11 @@ (++) specify initialization value (IP default or non-default one) (++) specify input data format (++) specify input or output data inversion mode if any - (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the - input data buffer starting with the previously computed CRC as + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as initialization value - (+) Use HAL_CRC_Calculate() function to compute the CRC value of the - input data buffer starting with the defined initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value (default or non-default) to initiate CRC calculation @endverbatim @@ -94,20 +92,20 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 * @{ */ -/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the CRC according to the specified parameters + (+) Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle (+) DeInitialize the CRC peripheral (+) Initialize the CRC MSP (MCU Specific Package) (+) DeInitialize the CRC MSP - + @endverbatim * @{ */ @@ -125,28 +123,28 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if(hcrc->State == HAL_CRC_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } - - hcrc->State = HAL_CRC_STATE_BUSY; - - /* check whether or not non-default generating polynomial has been + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been * picked up by user */ - assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) { /* initialize IP with default generating polynomial */ - WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); } else @@ -157,67 +155,67 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) return HAL_ERROR; } } - - /* check whether or not non-default CRC initial value has been + + /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) { - WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); } - + /* set input data inversion mode */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); - + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + /* set output data inversion mode */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); - + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CRC peripheral. + * @brief DeInitialize the CRC peripheral. * @param hcrc: CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) -{ +{ /* Check the CRC handle allocation */ if(hcrc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - + /* Check the CRC peripheral state */ if(hcrc->State == HAL_CRC_STATE_BUSY) { return HAL_BUSY; } - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + /* Reset CRC calculation unit */ __HAL_CRC_DR_RESET(hcrc); - + /* Reset IDR register content */ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; @@ -268,19 +266,19 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @} */ -/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer using the combination of the previous CRC value and the new one - + [..] or - + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer independently of the previous CRC value. @@ -288,35 +286,35 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @{ */ -/** +/** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. + * provided by hcrc->InputDataFormat. * @param BufferLength: input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; /* CRC input data buffer index */ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - + /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + switch (hcrc->InputDataFormat) { - case CRC_INPUTDATA_FORMAT_WORDS: + case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ for(index = 0; index < BufferLength; index++) { @@ -324,63 +322,63 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ } temp = hcrc->Instance->DR; break; - - case CRC_INPUTDATA_FORMAT_BYTES: + + case CRC_INPUTDATA_FORMAT_BYTES: temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: + + case CRC_INPUTDATA_FORMAT_HALFWORDS: temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return temp; } -/** +/** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. + * provided by hcrc->InputDataFormat. * @param BufferLength: input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ + */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; /* CRC input data buffer index */ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - + /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); - + switch (hcrc->InputDataFormat) { - case CRC_INPUTDATA_FORMAT_WORDS: + case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ for(index = 0; index < BufferLength; index++) { @@ -388,28 +386,28 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t } temp = hcrc->Instance->DR; break; - - case CRC_INPUTDATA_FORMAT_BYTES: + + case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: + + case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return temp; } @@ -418,12 +416,12 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -454,9 +452,9 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @{ */ -/** +/** * @brief Enter 8-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. + * Specific data handling to optimize processing time. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer * @param BufferLength: input data buffer length @@ -465,63 +463,72 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { uint32_t i = 0; /* input data buffer index */ - + uint16_t data; + __IO uint16_t *pReg; + /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the IP */ for(i = 0; i < (BufferLength/4); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; } /* last bytes specific handling */ if ((BufferLength%4) != 0) { if (BufferLength%4 == 1) { - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i]; } if (BufferLength%4 == 2) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; + data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; } if (BufferLength%4 == 3) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i+2]; } } - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return hcrc->Instance->DR; } -/** +/** * @brief Enter 16-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. + * Specific data handling to optimize processing time. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer * @param BufferLength: input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ + */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { uint32_t i = 0; /* input data buffer index */ - + __IO uint16_t *pReg; + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, - * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ for(i = 0; i < (BufferLength/2); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; } if ((BufferLength%2) != 0) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = pBuffer[2*i]; } - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return hcrc->Instance->DR; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h index 6bbae9f187e..035242c9dcf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_crc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -156,7 +154,7 @@ typedef struct /** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial * @{ */ -#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ /** * @} */ @@ -164,7 +162,7 @@ typedef struct /** @defgroup CRC_Default_InitValue Default CRC computation initialization value * @{ */ -#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF /*!< Initial CRC default value */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ /** * @} */ @@ -172,8 +170,8 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) /*!< Enable default generating polynomial 0x04C11DB7 */ -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) /*!< Disable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ /** * @} */ @@ -181,8 +179,8 @@ typedef struct /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ */ -#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) /*!< Enable initial CRC default value */ -#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) /*!< Disable initial CRC default value */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ /** * @} */ @@ -190,10 +188,10 @@ typedef struct /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ -#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) /*!< Resort to a 32-bit long generating polynomial */ -#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ -#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ -#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ +#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B (CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B (CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ /** * @} */ @@ -201,10 +199,10 @@ typedef struct /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ -#define HAL_CRC_LENGTH_32B 32 /*!< 32-bit long CRC */ -#define HAL_CRC_LENGTH_16B 16 /*!< 16-bit long CRC */ -#define HAL_CRC_LENGTH_8B 8 /*!< 8-bit long CRC */ -#define HAL_CRC_LENGTH_7B 7 /*!< 7-bit long CRC */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ /** * @} */ @@ -216,10 +214,10 @@ typedef struct * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) /*!< Undefined input data format */ -#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) /*!< Input data in byte format */ -#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) /*!< Input data in half-word format */ -#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) /*!< Input data in word format */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ /** * @} */ @@ -265,17 +263,19 @@ typedef struct #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** - * @brief Store a 8-bit data in the Independent Data(ID) register. + * @brief Store data in the Independent Data (ID) register. * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __VALUE__: Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) /** - * @brief Return the 8-bit data stored in the Independent Data(ID) register. + * @brief Return the data stored in the Independent Data (ID) register. * @param __HANDLE__: CRC handle - * @retval 8-bit value of the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c index e1ce5df19e2..cc30ffe0746 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the CRC peripheral. @@ -144,7 +142,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* no polynomial definition vs. polynomial length issue possible */ break; default: - break; + return HAL_ERROR; } /* set generating polynomial */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h index 7f6907df651..4e20acf7f80 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRC HAL extended module. ****************************************************************************** * @attention @@ -63,10 +61,10 @@ /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) /*!< No input data inversion */ -#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE (CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD (CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD (CRC_CR_REV_IN) /*!< Word-wise input data inversion */ /** * @} */ @@ -74,8 +72,8 @@ /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) /*!< No output data inversion */ -#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE (CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c index 833873cbdc5..0be7c96a571 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -92,7 +90,7 @@ #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1450,7 +1448,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* HAL_CRYP_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h index 315f76c8bb9..dcb2f5d66aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -457,7 +455,7 @@ typedef struct /** - * @brief Enable the CRYP interrupt. + * @brief Enable the CRYP interrupt. * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. * This parameter can be one of the following values: @@ -687,7 +685,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c index 11340c08266..586dd48ed2e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CRYPEx HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the Cryptography (CRYP) peripheral. @@ -43,7 +41,7 @@ #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -484,7 +482,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if (((pInputData == NULL) && (Size != 0)) || \ + ((pInputData != NULL) && (Size == 0)) || \ + ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))) { return HAL_ERROR; } @@ -950,7 +950,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ + {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; if (hcryp->State == HAL_CRYP_STATE_READY) @@ -1141,7 +1145,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -1230,7 +1234,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* If required, manage input data size not multiple of 32 bits */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Wrap-up in padding with zero-words if applicable */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -1404,15 +1408,22 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } #if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) + { + /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ + if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + { + return HAL_ERROR; + } + } #else - if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { if ((pInputData == NULL) || (Size == 0)) { return HAL_ERROR; } - } + } +#endif } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { @@ -2186,7 +2197,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ + {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; uint32_t intermediate_data[4] = {0}; if(hcryp->State == HAL_CRYP_STATE_BUSY) @@ -2249,7 +2264,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - /* Mark that the header phase is over */ + /* Mark that the header phase is suspended */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; /* Process Unlocked */ @@ -2318,7 +2333,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -2372,7 +2387,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) applied to the last block of payload */ if (difflengthmod4 != 0) { - intermediate_data[difflength/4] &= mask[difflengthmod4-1]; + intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; } @@ -2484,8 +2499,8 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_SUSPENDED; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -2539,7 +2554,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /* If required, manage input data size not multiple of 32 bits */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Wrap-up in padding with zero-words if applicable */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -2964,7 +2979,12 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ uint32_t difflengthmod4 = difflength%4; uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ + {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + uint32_t intermediate_data[4] = {0}; #if defined(AES_CR_NPBLB) @@ -3004,7 +3024,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -3047,7 +3067,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ applied to the last block of payload */ if (difflengthmod4 != 0) { - intermediate_data[difflength/4] &= mask[difflengthmod4-1]; + intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; } @@ -3109,7 +3129,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* HAL_CRYP_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h index d82497ae060..19f83a6519f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRYPEx HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ @@ -137,7 +135,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c index fe5e15f5efd..e9b7187443c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -26,6 +24,7 @@ 1 channel : STM32L451xx STM32L452xx STM32L462xx 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx + STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx When 2 channels are available, the 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode): @@ -474,6 +473,28 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + if(Channel == DAC_CHANNEL_1) + { + /* Check if software trigger enabled */ + if(((DAC_CR_TEN1 & ~(DAC_CR_TSEL1)) == (hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)))) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + } + else + { + /* Check if software trigger enabled */ + if(((DAC_CR_TEN2 & ~(DAC_CR_TSEL2)) == (hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)))) + { + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) if(Channel == DAC_CHANNEL_1) @@ -622,7 +643,8 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** * @brief Enables DAC and starts conversion of channel. @@ -751,6 +773,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @brief Disables DAC and stop conversion of channel. @@ -777,7 +800,8 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Disable the DMA channel */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { @@ -797,8 +821,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); @@ -858,7 +883,8 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) } } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { /* Check underrun flag of DAC channel 1 */ @@ -882,6 +908,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ } /** @@ -1025,12 +1052,13 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) assert_param(IS_DAC_CHANNEL(Channel)); /* Returns the DAC channel data output register value */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) return hdac->Instance->DOR1; #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(Channel == DAC_CHANNEL_1) { return hdac->Instance->DOR1; @@ -1041,6 +1069,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ } /** @@ -1058,9 +1087,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf { uint32_t tmpreg1 = 0, tmpreg2 = 0; uint32_t tickstart = 0; +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hclkfreq = 0; +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - /* Check the DAC parameters */ - + /* Check the DAC parameters */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); @@ -1181,6 +1215,34 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf tmpreg2 = (sConfig->DAC_Trigger); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + if(DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency) + { + tmpreg1 |= DAC_CR_HFSEL; + } + else + { + if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE == sConfig->DAC_HighFrequency) + { + tmpreg1 &= ~(DAC_CR_HFSEL); + } + else /* Automatic selection */ + { + hclkfreq = HAL_RCC_GetHCLKFreq(); + if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) + { + /* High frequency enable when HCLK frequency higher than 80 */ + tmpreg1 |= DAC_CR_HFSEL; + } + else + { + /* High frequency disable when HCLK frequency higher than 80 */ + tmpreg1 &= ~(DAC_CR_HFSEL); + } + } + } + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h index 8ea78f220b3..f19d72be8e6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32l4xx_hal_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -117,6 +115,11 @@ DAC_SampleAndHoldConfTypeDef; */ typedef struct { +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode + This parameter can be a value of @ref DAC_HighFrequency */ +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. This parameter can be a value of @ref DAC_SampleAndHold */ @@ -176,15 +179,15 @@ typedef struct #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register @@ -200,7 +203,25 @@ typedef struct #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + /** * @} */ @@ -220,10 +241,12 @@ typedef struct */ #define DAC_CHANNEL_1 ((uint32_t)0x00000000) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define DAC_CHANNEL_2 ((uint32_t)0x00000010) #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} @@ -290,6 +313,18 @@ typedef struct /** * @} */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup DAC_HighFrequency DAC high frequency interface mode + * @{ + */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE ((uint32_t)0x00000000) /*!< High frequency interface mode disabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ ((uint32_t)DAC_CR_HFSEL) /*!< High frequency interface mode enabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC ((uint32_t)0x00000002) /*!< High frequency interface mode automatic */ + +/** + * @} + */ +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} @@ -404,13 +439,15 @@ typedef struct ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) #endif /* STM32L451xx STM32L452xx STM32L462xx */ @@ -420,7 +457,7 @@ typedef struct #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x0000000FF) +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c index 49abcae0bf4..d139620350d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. @@ -199,7 +197,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** * @brief Set the specified data holding register value for dual DAC channel. @@ -310,6 +309,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @brief Run the self calibration of one DAC channel. @@ -363,7 +363,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC tmp = (uint32_t)hdac->Instance; #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); @@ -374,6 +375,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); #endif /* STM32L451xx STM32L452xx STM32L462xx */ @@ -524,7 +526,8 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions @@ -563,15 +566,17 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) * @} */ -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions @@ -630,6 +635,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #endif /* HAL_DAC_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h index 4b0cbb12c83..f9c82155ee3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention @@ -139,9 +137,30 @@ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ -#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) -#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x0000003FF) +#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ + ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ + ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC)) + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + +#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF) + +#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF) #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) @@ -204,18 +223,22 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue); @@ -230,10 +253,12 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /* Peripheral Control functions ***********************************************/ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); @@ -246,7 +271,8 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup DACEx_Private_Functions * @{ @@ -263,6 +289,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c index f62ffe45d40..caa181294f3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dcmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -51,12 +49,10 @@ be large enough to ensure the capture of a frame. (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), - (++) resort to a user-defined work buffer and associate it to the DCMI handle with - the function HAL_DCMIEx_WorkBuffer_Associate(), (++) the DMA must be configured in circular mode, either for snapshot or continuous capture mode, (++) during capture, the driver copies the image data samples from DCMI DR register - to the work buffer, + at the end of the final destination buffer used as a work buffer, (++) at each DMA half (respectively complete) transfer interrupt, the first (resp. second) half of the work buffer is copied to the final destination thru a second DMA channel. @@ -134,7 +130,8 @@ #ifdef HAL_DCMI_MODULE_ENABLED -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -417,9 +414,8 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) * @param pData: The destination memory buffer address. * @param Length: The length of capture to be transferred (in 32-bit words). * @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length), - * user must beforehand associate a work buffer to the DCMI handle thru the API - * HAL_DCMIEx_WorkBuffer_Associate(). Then, HAL_DCMI_Start_DMA() - * initiates a circular DMA transfer from DCMI DR to the work buffer and each + * the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA() + * initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each * half and complete transfer interrupt triggers a copy from the work buffer to * the final destination pData thru a second DMA channel. * @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end, @@ -1264,7 +1260,8 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) * @} */ -#endif /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_DCMI_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h index 7243fc837aa..278566e144c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dcmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -43,7 +41,9 @@ extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -645,7 +645,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); * @} */ -#endif /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h index 9dde4bccd2e..fcee1d4ecab 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_def.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -124,10 +122,13 @@ typedef enum (__HANDLE__)->Lock = HAL_UNLOCKED; \ }while (0) #endif /* USE_RTOS */ + +// Added for MBED PR #3062 #if defined (__CC_ARM) #pragma diag_suppress 3731 #endif +// Added for MBED PR #3062 static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; @@ -137,7 +138,7 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) } while (__STREXW(newValue, ptr)); } - +// Added for MBED PR #3062 static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; @@ -147,7 +148,7 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) } while (__STREXW(newValue, ptr)); } -#if defined ( __GNUC__ ) && !defined ( __CC_ARM ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -158,7 +159,7 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c index 8cd6cc65340..3de4618edca 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: @@ -198,7 +196,9 @@ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /** @defgroup DFSDM DFSDM * @brief DFSDM HAL driver module * @{ @@ -209,30 +209,10 @@ /** @defgroup DFSDM_Private_Define DFSDM Private Define * @{ */ -#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV) -#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD) -#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR) -#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET) -#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS) -#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR) #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8 -#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH) -#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH) -#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF) -#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF) -#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF) -#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF) -#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA) -#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA) -#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT) -#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT) -#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX) -#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN) -#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT) -#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF) -#define DFSDM_MSB_MASK 0xFFFF0000U -#define DFSDM_LSB_MASK 0x0000FFFFU -#define DFSDM_CKAB_TIMEOUT 5000U +#define DFSDM_MSB_MASK 0xFFFF0000U +#define DFSDM_LSB_MASK 0x0000FFFFU +#define DFSDM_CKAB_TIMEOUT 5000U #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) #define DFSDM1_CHANNEL_NUMBER 4U #else /* STM32L451xx || STM32L452xx || STM32L462xx */ @@ -294,7 +274,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DFSDM channel according to the specified parameters * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -345,7 +325,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << - DFSDM_CHCFGR1_CLK_DIV_OFFSET); + DFSDM_CHCFGR1_CKOUTDIV_Pos); } /* enable the DFSDM global interface */ @@ -367,12 +347,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET)); + ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | - (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET)); + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; @@ -388,7 +368,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /** * @brief De-initialize the DFSDM channel. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -434,7 +414,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief Initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -449,7 +429,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief De-initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -488,7 +468,7 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -515,9 +495,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -540,8 +520,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /** * @brief This function allows to poll for the clock absence detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -568,7 +548,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs tickstart = HAL_GetTick(); /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) == 0) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -582,7 +562,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs } /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Return function status */ return HAL_OK; @@ -591,7 +571,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to stop clock absence detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -615,7 +595,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); } /* Return function status */ return status; @@ -627,7 +607,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -654,9 +634,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -682,7 +662,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /** * @brief Clock absence detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -698,7 +678,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief This function allows to stop clock absence detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -722,7 +702,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); @@ -734,10 +714,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to start short circuit detection in polling mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -762,7 +742,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ { /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); /* Start short circuit detection */ @@ -774,8 +754,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ /** * @brief This function allows to poll for the short circuit detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -802,7 +782,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd tickstart = HAL_GetTick(); /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0) + while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -816,7 +796,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd } /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Return function status */ return HAL_OK; @@ -825,7 +805,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to stop short circuit detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -849,7 +829,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); } /* Return function status */ return status; @@ -858,10 +838,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /** * @brief This function allows to start short circuit detection in interrupt mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -889,7 +869,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); /* Start short circuit detection */ @@ -901,7 +881,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief Short circuit detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -917,7 +897,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha /** * @brief This function allows to stop short circuit detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -941,7 +921,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Disable short circuit detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); @@ -952,7 +932,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to get channel analog watchdog value. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -962,8 +942,8 @@ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief This function allows to modify channel offset value. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Offset : DFSDM channel offset. + * @param hdfsdm_channel DFSDM channel handle. + * @param Offset DFSDM channel offset. * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. * @retval HAL status. */ @@ -986,7 +966,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf { /* Modify channel offset */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); - hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET); + hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos); } /* Return function status */ return status; @@ -1011,7 +991,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /** * @brief This function allows to get the current DFSDM channel handle state. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1041,7 +1021,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp /** * @brief Initialize the DFSDM filter according to the specified parameters * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1131,7 +1111,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Set filter parameters */ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) | + ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_Pos) | (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); /* Store regular and injected triggers and injected scan mode*/ @@ -1151,7 +1131,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief De-initializes the DFSDM filter. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1179,7 +1159,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief Initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1194,7 +1174,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief De-initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1228,10 +1208,10 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief This function allows to select channel and to enable/disable * continuous mode for regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channel for regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channel for regular conversion. * This parameter can be a value of @ref DFSDM_Channel_Selection. - * @param ContinuousMode : Enable/disable continuous mode for regular conversion. + * @param ContinuousMode Enable/disable continuous mode for regular conversion. * This parameter can be a value of @ref DFSDM_ContinuousMode. * @retval HAL status */ @@ -1275,8 +1255,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to select channels for injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels for injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels for injected conversion. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -1347,7 +1327,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h * @brief This function allows to start regular conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1375,8 +1355,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to poll for the end of regular conversion. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1437,7 +1417,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop regular conversion in polling mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1467,7 +1447,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm * @brief This function allows to start regular conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1498,7 +1478,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to stop regular conversion in interrupt mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1534,9 +1514,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1611,9 +1591,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1684,7 +1664,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef /** * @brief This function allows to stop regular conversion in DMA mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1722,8 +1702,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to get regular conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1741,7 +1721,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /* Extract channel and regular conversion value */ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); /* return regular conversion value */ return value; @@ -1751,7 +1731,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte * @brief This function allows to start injected conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1779,8 +1759,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to poll for the end of injected conversion. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1851,7 +1831,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in polling mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1881,7 +1861,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd * @brief This function allows to start injected conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1912,7 +1892,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to stop injected conversion in interrupt mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1948,9 +1928,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2023,9 +2003,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2094,7 +2074,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in DMA mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2132,8 +2112,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to get injected conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2151,7 +2131,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /* Extract channel and injected conversion value */ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); /* return regular conversion value */ return value; @@ -2159,8 +2139,8 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief This function allows to start filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. - * @param awdParam : DFSDM filter analog watchdog parameters. + * @param hdfsdm_filter DFSDM filter handle. + * @param awdParam DFSDM filter analog watchdog parameters. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2192,15 +2172,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /* Set thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \ + hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ awdParam->HighBreakSignal); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \ + hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ awdParam->LowBreakSignal); /* Set channels and interrupt for analog watchdog */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); - hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \ + hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \ DFSDM_FLTCR2_AWDIE); } /* Return function status */ @@ -2209,7 +2189,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to stop filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2247,8 +2227,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /** * @brief This function allows to start extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels where extreme detector is enabled. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels where extreme detector is enabled. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -2272,7 +2252,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi { /* Set channels for extreme detector */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); } /* Return function status */ return status; @@ -2280,7 +2260,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /** * @brief This function allows to stop extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2316,8 +2296,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get extreme detector maximum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2336,7 +2316,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Extract channel and extreme detector maximum value */ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); /* return extreme detector maximum value */ return value; @@ -2344,8 +2324,8 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get extreme detector minimum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2364,7 +2344,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Extract channel and extreme detector minimum value */ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); /* return extreme detector minimum value */ return value; @@ -2372,7 +2352,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get conversion time value. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ @@ -2388,7 +2368,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil reg = hdfsdm_filter->Instance->FLTCNVTIMR; /* Extract conversion time value */ - value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET); + value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); /* return extreme detector minimum value */ return value; @@ -2396,7 +2376,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function handles the DFSDM interrupts. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2485,7 +2465,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; if(threshold == DFSDM_AWD_HIGH_THRESHOLD) { - reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET; + reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; } while((reg & 1) == 0) { @@ -2494,7 +2474,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear analog watchdog flag */ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \ + (1 << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ (1 << channel); /* Call analog watchdog callback */ @@ -2508,7 +2488,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t reg = 0; uint32_t channel = 0; - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); while(channel < DFSDM1_CHANNEL_NUMBER) { @@ -2519,7 +2499,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) { /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Call clock absence callback */ HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); @@ -2538,7 +2518,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t channel = 0; /* Get channel */ - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); while((reg & 1) == 0) { channel++; @@ -2546,7 +2526,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Call short circuit detection callback */ HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); @@ -2557,7 +2537,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2572,7 +2552,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half regular conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2589,7 +2569,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2604,7 +2584,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half injected conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2619,9 +2599,9 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * /** * @brief Filter analog watchdog callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @param Threshold : Low or high threshold has been reached. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. + * @param Threshold Low or high threshold has been reached. * @retval None */ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2639,7 +2619,7 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief Error callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2672,7 +2652,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get the current DFSDM filter handle state. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2683,7 +2663,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to get the current DFSDM filter error. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2707,7 +2687,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief DMA half transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2721,7 +2701,7 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) @@ -2735,7 +2715,7 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2749,7 +2729,7 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) @@ -2763,7 +2743,7 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) @@ -2780,7 +2760,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function allows to get the number of injected channels. - * @param Channels : bitfield of injected channels. + * @param Channels bitfield of injected channels. * @retval Number of injected channels. */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) @@ -2803,7 +2783,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) /** * @brief This function allows to get the channel number from channel instance. - * @param Instance : DFSDM channel instance. + * @param Instance DFSDM channel instance. * @retval Channel number. */ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) @@ -2828,7 +2808,8 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) channel = 3; } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) else if(Instance == DFSDM1_Channel4) { channel = 4; @@ -2845,14 +2826,14 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) { channel = 7; } -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return channel; } /** * @brief This function allows to really start regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2893,7 +2874,7 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2929,7 +2910,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really start injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2973,7 +2954,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -3019,7 +3000,9 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @} */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ + +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* HAL_DFSDM_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h index 7af5ae4675d..17de1fc91e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention @@ -45,7 +43,9 @@ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -91,7 +91,8 @@ typedef struct { uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, - STM32L496xx, STM32L4A6xx products. + STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, + STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products. This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. This parameter can be a value of @ref DFSDM_Channel_DataPacking */ @@ -271,9 +272,10 @@ typedef struct */ #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ /** * @} @@ -352,6 +354,22 @@ typedef struct #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ +#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ + DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ + DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ + DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ #else #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ @@ -440,7 +458,7 @@ typedef struct #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) -#else /* STM32L451xx || STM32L452xx || STM32L462xx */ +#else #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) @@ -483,13 +501,13 @@ typedef struct */ /** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. + * @param __HANDLE__ DFSDM channel handle. * @retval None */ #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) /** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. + * @param __HANDLE__ DFSDM filter handle. * @retval None */ #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) @@ -499,6 +517,11 @@ typedef struct */ /* End of exported macros ----------------------------------------------------*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include DFSDM HAL Extension module */ +#include "stm32l4xx_hal_dfsdm_ex.h" +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions * @{ @@ -644,14 +667,17 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) #else #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) @@ -686,6 +712,19 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) +#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) #else #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ @@ -720,7 +759,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CHANNEL) == DFSDM_CHANNEL_2) || \ ((CHANNEL) == DFSDM_CHANNEL_3)) #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) -#else /* STM32L451xx || STM32L452xx || STM32L462xx */ +#else #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_2) || \ @@ -745,7 +784,11 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe /** * @} */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c new file mode 100644 index 00000000000..2304f973046 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dfsdm_ex.c + * @author MCD Application Team + * @brief DFSDM Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the DFSDM Peripheral Controller: + * + Set and get pulses skipping on channel. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @defgroup DFSDMEx DFSDMEx + * @brief DFSDM Extended HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions + * @{ + */ + +/** @defgroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions + * @brief DFSDM extended channel operation functions + * +@verbatim + =============================================================================== + ##### Extended channel operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Set and get value of pulses skipping on channel + +@endverbatim + * @{ + */ + +/** + * @brief Set value of pulses skipping. + * @param hdfsdm_channel DFSDM channel handle. + * @param PulsesValue Value of pulses to be skipped. + * This parameter must be a number between Min_Data = 0 and Max_Data = 63. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check pulses value */ + assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Set new value of pulses skipping */ + hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP); + } + else + { + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Get value of pulses skipping. + * @param hdfsdm_channel DFSDM channel handle. + * @param PulsesValue Value of pulses to be skipped. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Get value of remaining pulses to be skipped */ + *PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP); + } + else + { + status = HAL_ERROR; + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h new file mode 100644 index 00000000000..ec267194494 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dfsdm_ex.h + * @author MCD Application Team + * @brief Header file of DFSDM HAL extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_DFSDM_EX_H +#define __STM32L4xx_HAL_DFSDM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DFSDMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions + * @{ + */ + +/** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions + * @{ + */ + +HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue); +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t* PulsesValue); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros + * @{ + */ + +#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE) ((VALUE) < 64U) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_DFSDM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c index 78da7a3a3d6..9963ae866e8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: @@ -16,7 +14,7 @@ ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is + (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. @@ -25,15 +23,18 @@ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. - Prior to HAL_DMA_Init the CLK shall be enabled for both DMA thanks to: - __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX + thanks to: + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; + (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. - + (#) Use HAL_DMA_Abort() function to abort the current transfer - + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** ================================= [..] @@ -52,13 +53,12 @@ In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e. a member of DMA handle structure). + add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** - ============================================= + ============================================= [..] - Below the list of most used macros in DMA HAL driver. + Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. @@ -66,10 +66,10 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** @@ -125,6 +125,11 @@ * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +#if defined(DMAMUX1) +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); +#endif /* DMAMUX1 */ + /** * @} */ @@ -136,7 +141,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * @verbatim =============================================================================== @@ -144,11 +149,11 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, + and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. + reference manual. @endverbatim * @{ @@ -181,19 +186,16 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) - { - assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); - } - - /* calculation of the channel index */ + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } - else + else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; @@ -206,10 +208,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Get the CR register value */ tmp = hdma->Instance->CCR; - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ - DMA_CCR_DIR)); + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | @@ -220,6 +222,48 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; + +#if defined(DMAMUX1) + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } +#endif /* DMAMUX1 */ + +#if !defined (DMAMUX1) + /* Set request selection */ if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) { @@ -230,18 +274,22 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); /* Configure request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); } else /* DMA2 */ { /* Reset request selection for DMA2 Channelx */ DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); - + /* Configure request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); } } +#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ + /* STM32L496xx || STM32L4A6xx */ + /* Clean callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; @@ -256,7 +304,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; - + return HAL_OK; } @@ -268,52 +316,91 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { + /* Check the DMA handle allocation */ - if(hdma == NULL) + if (NULL == hdma ) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; - - /* Calculation of the channel index */ + /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } - else + else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } - + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0; /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + +#if !defined (DMAMUX1) /* Reset DMA channel selection register */ if (DMA1 == hdma->DmaBaseAddress) { /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); } - else + else { /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + } +#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ + /* STM32L496xx || STM32L4A6xx */ + +#if defined(DMAMUX1) + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Reset Request generator parameters if any */ + if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + +#endif /* DMAMUX1 */ - /* Initialize the error code */ + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ @@ -372,22 +459,22 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - status = HAL_BUSY; - } + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } return status; } @@ -409,19 +496,19 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback ) @@ -434,17 +521,36 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } + +#ifdef DMAMUX1 + + /* Check if DMAMUX Synchronization is enabled*/ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + +#endif /* DMAMUX1 */ + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else - { + { /* Process Unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; - } + } return status; } @@ -458,31 +564,49 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; - if(HAL_DMA_STATE_BUSY != hdma->State) + /* Check the DMA peripheral handle */ + if(NULL == hdma) { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; + return HAL_ERROR; } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); +#if defined(DMAMUX1) + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; +#endif /* DMAMUX1 */ + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + +#if defined(DMAMUX1) + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } - return status; + +#endif /* DMAMUX1 */ + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return status; } /** @@ -492,38 +616,60 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - + status = HAL_ERROR; } else - { + { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - + /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - + +#if defined(DMAMUX1) + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + +#else /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - +#endif /* DMAMUX1 */ + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ + + /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); - } + } } return status; } @@ -536,7 +682,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param Timeout: Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0; @@ -545,7 +691,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - + __HAL_UNLOCK(hdma); return HAL_ERROR; } @@ -555,7 +701,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } - + /* Get the level transfer complete flag */ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { @@ -571,9 +717,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Get tick */ tickstart = HAL_GetTick(); - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) { - if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) + if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -601,7 +747,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); @@ -610,6 +756,35 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp } } +#if defined(DMAMUX1) + /*Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } +#endif /* DMAMUX1 */ + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ @@ -624,9 +799,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); } - + /* Process unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); return HAL_OK; } @@ -641,7 +816,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; - + /* Half Transfer Complete Interrupt management ******************************/ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) { @@ -663,14 +838,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->XferHalfCpltCallback(hdma); } } - + /* Transfer Complete Interrupt management ***********************************/ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { /* Disable the transfer complete and error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; @@ -723,17 +898,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Channel. * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback: pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) { HAL_StatusTypeDef status = HAL_OK; - + /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) @@ -741,32 +916,32 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; - + case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; - break; + break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; - break; - + break; + case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; - break; - + break; + default: status = HAL_ERROR; - break; + break; } } else { status = HAL_ERROR; - } - + } + /* Release Lock */ __HAL_UNLOCK(hdma); - + return status; } @@ -777,14 +952,14 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) @@ -792,42 +967,42 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; - + case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; - break; + break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; - break; - + break; + case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; - break; - + break; + case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; - break; - + break; + default: status = HAL_ERROR; - break; + break; } } else { status = HAL_ERROR; - } - + } + /* Release Lock */ __HAL_UNLOCK(hdma); - + return status; } - + /** * @} */ @@ -840,7 +1015,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state @@ -896,9 +1071,20 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { +#if defined(DMAMUX1) + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } +#endif + /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - + /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; @@ -922,6 +1108,57 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t } } +#if defined(DMAMUX1) + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t channel_number = 0; + DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; + + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + { + /* DMA1 */ + DMAMUX1_ChannelBase = DMAMUX1_Channel0; + } + else + { + /* DMA2 */ + DMAMUX1_ChannelBase = DMAMUX1_Channel7; + } + channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1U << channel_number; +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + + hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); +} + +#endif /* DMAMUX1 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h index eedd7f6750c..c11a47ccae6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -55,7 +53,6 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ @@ -114,17 +111,17 @@ typedef enum }HAL_DMA_LevelCompleteTypeDef; -/** +/** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ - + HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ + }HAL_DMA_CallbackIDTypeDef; /** @@ -133,13 +130,13 @@ typedef enum typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ - + DMA_InitTypeDef Init; /*!< DMA communication parameters */ - + HAL_LockTypeDef Lock; /*!< DMA locking object */ - + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - + void *Parent; /*!< Parent object state */ void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ @@ -148,13 +145,29 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + +#if defined(DMAMUX1) + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + +#endif /* DMAMUX1 */ + }DMA_HandleTypeDef; /** * @} @@ -169,11 +182,14 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ + /** * @} */ @@ -181,6 +197,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_request DMA request * @{ */ +#if !defined (DMAMUX1) + #define DMA_REQUEST_0 ((uint32_t)0x00000000) #define DMA_REQUEST_1 ((uint32_t)0x00000001) #define DMA_REQUEST_2 ((uint32_t)0x00000002) @@ -189,6 +207,131 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_5 ((uint32_t)0x00000005) #define DMA_REQUEST_6 ((uint32_t)0x00000006) #define DMA_REQUEST_7 ((uint32_t)0x00000007) + +#endif + +#if defined(DMAMUX1) + +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ + +#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ + +#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ +#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ + +#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ +#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ + +#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ +#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ + +#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ +#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ +#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ +#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ + +#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ +#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ +#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ +#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ +#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ +#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ + +#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ +#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ +#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ +#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ + +#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ +#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ + +#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ +#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ +#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ +#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ + +#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ +#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ + +#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ +#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ +#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ + +#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ +#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ +#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ +#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ +#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ +#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ +#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ + +#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ + +#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ +#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ + +#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ +#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ + +#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ +#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ +#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ +#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ +#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ +#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ + +#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ +#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ +#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ + +#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ +#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ + +#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ +#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ +#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ +#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ + +#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ + +#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ +#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ + +#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ + +#endif /* DMAMUX1 */ + /** * @} */ @@ -497,6 +640,11 @@ typedef struct __DMA_HandleTypeDef * @} */ +#if defined(DMAMUX1) +/* Include DMA HAL Extension module */ +#include "stm32l4xx_hal_dma_ex.h" +#endif /* DMAMUX1 */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions @@ -521,7 +669,7 @@ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, u HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); @@ -561,6 +709,8 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) +#if !defined (DMAMUX1) + #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ ((REQUEST) == DMA_REQUEST_1) || \ ((REQUEST) == DMA_REQUEST_2) || \ @@ -569,6 +719,13 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((REQUEST) == DMA_REQUEST_5) || \ ((REQUEST) == DMA_REQUEST_6) || \ ((REQUEST) == DMA_REQUEST_7)) +#endif + +#if defined(DMAMUX1) + +#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) + +#endif /* DMAMUX1 */ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ @@ -588,7 +745,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c index 78d37764421..d5088c5e7b7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -130,7 +128,8 @@ #ifdef HAL_DMA2D_MODULE_ENABLED -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -243,6 +242,10 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode)); + assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(hdma2d->State == HAL_DMA2D_STATE_RESET) { @@ -256,13 +259,21 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) hdma2d->State = HAL_DMA2D_STATE_BUSY; /* DMA2D CR register configuration -------------------------------------------*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode); +#else MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); +#else MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* DMA2D OOR register configuration ------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); /* DMA2D OPFCCR RBS and AI fields setting */ MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), \ @@ -585,7 +596,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) /* Abort the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); @@ -634,7 +645,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /* Suspend the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); @@ -689,7 +700,7 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /* Resume the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); @@ -1761,7 +1772,8 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ * @} */ -#endif /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_DMA2D_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h index 90f62da76d0..cb389d6659a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -43,7 +41,8 @@ extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -112,6 +111,16 @@ typedef struct uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) for the output pixel format converter. This parameter can be one value of @ref DMA2D_RB_Swap. */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). + This parameter can be one value of @ref DMA2D_Bytes_Swap. */ + + uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. + This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + } DMA2D_InitTypeDef; @@ -143,7 +152,6 @@ typedef struct uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). This parameter can be one value of @ref DMA2D_RB_Swap. */ - } DMA2D_LayerCfgTypeDef; /** @@ -204,10 +212,14 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Mode DMA2D Mode * @{ */ -#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ -#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ -#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ -#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ +#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ +#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -271,6 +283,27 @@ typedef struct __DMA2D_HandleTypeDef * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode + * @{ + */ +#define DMA2D_LOM_PIXELS ((uint32_t)0x00000000U) /*!< Line offsets expressed in pixels */ +#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ +/** + * @} + */ + +/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap + * @{ + */ +#define DMA2D_BYTES_REGULAR ((uint32_t)0x00000000U) /*!< Bytes in regular order in output FIFO */ +#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode * @{ */ @@ -280,7 +313,6 @@ typedef struct __DMA2D_HandleTypeDef * @} */ - /** @defgroup DMA2D_Interrupts DMA2D Interrupts * @{ */ @@ -562,8 +594,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); * @{ */ #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ + ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) +#else #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) @@ -587,6 +627,15 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ ((RB_Swap) == DMA2D_RB_SWAP)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ + ((LOM) == DMA2D_LOM_BYTES)) + +#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ + ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) @@ -609,6 +658,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); */ #endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c new file mode 100644 index 00000000000..50b09d59081 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(DMAMUX1) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + +@endverbatim + * @{ + */ + + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + /*Check if the DMA state is ready */ + if(hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG( hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID) , \ + ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + (pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /*DMA State not Ready*/ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters*/ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ + pRequestGeneratorConfig->Polarity; + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if(hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h new file mode 100644 index 00000000000..0ce4b2ae207 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_DMA_EX_H +#define __STM32L4xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(DMAMUX1) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMA Synchro definition + */ + + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + + +}HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +}HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ +#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ +#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ +#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ +#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ +#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ +#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ +#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ +#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ +#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ +#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ +#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ +#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ +#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ +#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */ +#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */ +#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */ +#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ +#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c new file mode 100644 index 00000000000..570bef2b503 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c @@ -0,0 +1,2379 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dsi.c + * @author MCD Application Team + * @brief DSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DSI peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DSI_MODULE_ENABLED + +#if defined(DSI) + +/** @addtogroup DSI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup DSI_Private_Constants + * @{ + */ +#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ + +#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ + DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ + DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ + DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) +#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) +#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX +#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX +#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) +#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE +#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE +#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE +#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE +#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Generic DSI packet header configuration + * @param DSIx: Pointer to DSI register base + * @param ChannelID: Virtual channel ID of the header packet + * @param DataType: Packet data type of the header packet + * This parameter can be any value of : + * @ref DSI_SHORT_WRITE_PKT_Data_Type + * or @ref DSI_LONG_WRITE_PKT_Data_Type + * or @ref DSI_SHORT_READ_PKT_Data_Type + * or DSI_MAX_RETURN_PKT_SIZE + * @param Data0: Word count LSB + * @param Data1: Word count MSB + * @retval None + */ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, + uint32_t ChannelID, + uint32_t DataType, + uint32_t Data0, + uint32_t Data1) +{ + /* Update the DSI packet header with new information */ + DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U)); +} + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DSI_Exported_Functions + * @{ + */ + +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DSI + (+) De-initialize the DSI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DSI according to the specified + * parameters in the DSI_InitTypeDef and create the associated handle. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + uint32_t tickstart; + uint32_t unitIntervalx4; + uint32_t tempIDF; + + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); + assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); + assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); + assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); + assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); + + if(hdsi->State == HAL_DSI_STATE_RESET) + { + /* Initialize the low level hardware */ + HAL_DSI_MspInit(hdsi); + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /**************** Turn on the regulator and enable the DSI PLL ****************/ + + /* Enable the regulator */ + __HAL_DSI_REG_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the regulator is ready */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /*************************** Set the PHY parameters ***************************/ + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + + /************************ Set the DSI clock parameters ************************/ + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + + /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ + /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ + /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ + tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; + unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); + + /* Set the bit period in high-speed mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; + hdsi->Instance->WPCR[0U] |= unitIntervalx4; + + /****************************** Error management *****************************/ + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + hdsi->ErrorMsk = 0U; + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DSI peripheral registers to their default reset + * values. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* D-PHY clock and digital disable */ + hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Disable the regulator */ + __HAL_DSI_REG_DISABLE(hdsi); + + /* DeInit the low level hardware */ + HAL_DSI_MspDeInit(hdsi); + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable the error monitor flags + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ActiveErrors: indicates which error interrupts will be enabled. + * This parameter can be any combination of @ref DSI_Error_Data_Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + + /* Store active errors to the handle */ + hdsi->ErrorMsk = ActiveErrors; + + if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle DSI interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handles DSI interrupt request. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) +{ + uint32_t ErrorStatus0, ErrorStatus1; + + /* Tearing Effect Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) + { + /* Clear the Tearing Effect Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); + + /* Tearing Effect Callback */ + HAL_DSI_TearingEffectCallback(hdsi); + } + } + + /* End of Refresh Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) + { + /* Clear the End of Refresh Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); + + /* End of Refresh Callback */ + HAL_DSI_EndOfRefreshCallback(hdsi); + } + } + + /* Error Interrupts management ***********************************************/ + if(hdsi->ErrorMsk != 0U) + { + ErrorStatus0 = hdsi->Instance->ISR[0U]; + ErrorStatus0 &= hdsi->Instance->IER[0U]; + ErrorStatus1 = hdsi->Instance->ISR[1U]; + ErrorStatus1 &= hdsi->Instance->IER[1U]; + + if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; + } + + if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; + } + + if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_TX; + } + + if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_RX; + } + + if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; + } + + if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; + } + + if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; + } + + if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; + } + + if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; + } + + if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; + } + + /* Check only selected errors */ + if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + { + /* DSI error interrupt user callback */ + HAL_DSI_ErrorCallback(hdsi); + } + } +} + +/** + * @brief Tearing Effect DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_TearingEffectCallback could be implemented in the user file + */ +} + +/** + * @brief End of Refresh DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_EndOfRefreshCallback could be implemented in the user file + */ +} + +/** + * @brief Operation Error DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the Generic interface read-back Virtual Channel ID + (+) Select video mode and configure the corresponding parameters + (+) Configure command transmission mode: High-speed or Low-power + (+) Configure the flow control + (+) Configure the DSI PHY timer + (+) Configure the DSI HOST timeout + (+) Configure the DSI HOST timeout + (+) Start/Stop the DSI module + (+) Refresh the display in command mode + (+) Controls the display color mode in Video mode + (+) Control the display shutdown in Video mode + (+) write short DCS or short Generic command + (+) write long DCS or long Generic command + (+) Read command (DCS or generic) + (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) + (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) + (+) Start/Stop test pattern generation + (+) Slew-Rate And Delay Tuning + (+) Low-Power Reception Filter Tuning + (+) Activate an additional current path on all lanes to meet the SDDTx parameter + (+) Custom lane pins configuration + (+) Set custom timing for the PHY + (+) Force the Clock/Data Lane in TX Stop Mode + (+) Force LP Receiver in Low-Power Mode + (+) Force Data Lanes in RX Mode after a BTA + (+) Enable a pull-down on the lanes to prevent from floating states when unused + (+) Switch off the contention detection on data lanes + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelID: Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; + hdsi->Instance->GVCIDR |= VirtualChannelID; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select video mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); + assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); + assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); + assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); + assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); + assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); + assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); + assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); + assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); + assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); + assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); + /* Check the LooselyPacked variant only in 18-bit mode */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); + } + + /* Select video mode by resetting CMDM and DSIM bits */ + hdsi->Instance->MCR &= ~DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + + /* Configure the video mode transmission type */ + hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; + hdsi->Instance->VMCR |= VidCfg->Mode; + + /* Configure the video packet size */ + hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; + hdsi->Instance->VPCR |= VidCfg->PacketSize; + + /* Set the chunks number to be transmitted through the DSI link */ + hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; + hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; + + /* Set the size of the null packet */ + hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; + hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U); + + /* Enable/disable the loosely packed variant to 18-bit configuration */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; + hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; + } + + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ + hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; + hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; + + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ + hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; + hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; + + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ + hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; + hdsi->Instance->VLCR |= VidCfg->HorizontalLine; + + /* Set the Vertical Synchronization Active (VSA) */ + hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; + hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; + + /* Set the Vertical Back Porch (VBP)*/ + hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; + hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; + + /* Set the Vertical Front Porch (VFP)*/ + hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; + hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; + + /* Set the Vertical Active period*/ + hdsi->Instance->VVACR &= ~DSI_VVACR_VA; + hdsi->Instance->VVACR |= VidCfg->VerticalActive; + + /* Configure the command transmission mode */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; + hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; + + /* Low power largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U); + + /* Low power VACT largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; + hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; + + /* Enable LP transition in HFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; + + /* Enable LP transition in HBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; + + /* Enable LP transition in VACT period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; + + /* Enable LP transition in VFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; + + /* Enable LP transition in VBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; + + /* Enable LP transition in vertical sync period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; + + /* Enable the request for an acknowledge response at the end of a frame */ + hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; + hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select adapted command mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); + assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); + assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); + assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); + assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); + assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); + assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); + + /* Select command mode by setting CMDM and DSIM bits */ + hdsi->Instance->MCR |= DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U); + + /* Configure the maximum allowed size for write memory command */ + hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; + hdsi->Instance->LCCR |= CmdCfg->CommandSize; + + /* Configure the tearing effect source and polarity and select the refresh mode */ + hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); + + /* Configure the tearing effect acknowledge request */ + hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; + hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; + + /* Enable the Tearing Effect interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); + + /* Enable the End of Refresh interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure command transmission mode: High-speed or Low-power + * and enable/disable acknowledge request after packet transmission + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * the DSI command transmission mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); + assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); + assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); + assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); + assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); + assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); + assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); + assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); + assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); + assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); + assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); + assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); + assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); + + /* Select High-speed or Low-power for command transmission */ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ + DSI_CMCR_GSW1TX |\ + DSI_CMCR_GSW2TX |\ + DSI_CMCR_GSR0TX |\ + DSI_CMCR_GSR1TX |\ + DSI_CMCR_GSR2TX |\ + DSI_CMCR_GLWTX |\ + DSI_CMCR_DSW0TX |\ + DSI_CMCR_DSW1TX |\ + DSI_CMCR_DSR0TX |\ + DSI_CMCR_DLWTX |\ + DSI_CMCR_MRDPS); + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ + LPCmd->LPGenShortWriteOneP |\ + LPCmd->LPGenShortWriteTwoP |\ + LPCmd->LPGenShortReadNoP |\ + LPCmd->LPGenShortReadOneP |\ + LPCmd->LPGenShortReadTwoP |\ + LPCmd->LPGenLongWrite |\ + LPCmd->LPDcsShortWriteNoP |\ + LPCmd->LPDcsShortWriteOneP |\ + LPCmd->LPDcsShortReadNoP |\ + LPCmd->LPDcsLongWrite |\ + LPCmd->LPMaxReadPacket); + + /* Configure the acknowledge request after each packet transmission */ + hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; + hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the flow control parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param FlowControl: flow control feature(s) to be enabled. + * This parameter can be any combination of @ref DSI_FlowControl. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); + + /* Set the DSI Host Protocol Configuration Register */ + hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; + hdsi->Instance->PCR |= FlowControl; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI PHY timer parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * the DSI PHY timing parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) +{ + uint32_t maxTime; + /* Process locked */ + __HAL_LOCK(hdsi); + + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; + + /* Clock lane timer configuration */ + + /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two + High-Speed transmission. + To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed + to Low-Power and from Low-Power to High-Speed. + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. + + Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. + */ + hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U)); + + /* Data lane timer configuration */ + hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U)); + + /* Configure the wait period to request HS transmission after a stop state */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI HOST timeout parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * the DSI host timeout parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Set the timeout clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; + hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U); + + /* High-speed transmission timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; + hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U); + + /* Low-power reception timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; + hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; + + /* High-speed read timeout */ + hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; + hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; + + /* Low-power read timeout */ + hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; + hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; + + /* High-speed write timeout */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; + + /* High-speed write presp mode */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; + + /* Low-speed write timeout */ + hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; + hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; + + /* BTA timeout */ + hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; + hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Enable the DSI host */ + __HAL_DSI_ENABLE(hdsi); + + /* Enable the DSI wrapper */ + __HAL_DSI_WRAPPER_ENABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Refresh the display in command mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the display */ + hdsi->Instance->WCR |= DSI_WCR_LTDCEN; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Controls the display color mode in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ColorMode: Color mode (full or 8-colors). + * This parameter can be any value of @ref DSI_Color_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_MODE(ColorMode)); + + /* Update the display color mode */ + hdsi->Instance->WCR &= ~DSI_WCR_COLM; + hdsi->Instance->WCR |= ColorMode; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Control the display shutdown in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @ref DSI_ShutDown + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHUT_DOWN(Shutdown)); + + /* Update the display Shutdown */ + hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; + hdsi->Instance->WCR |= Shutdown; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI short packet data type. + * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code. + * @param Param2: DSC parameter or second generic parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + Param1, + Param2); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief write long DCS or long Generic command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI long packet data type. + * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams: Number of parameters. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable) +{ + uint32_t uicounter, nbBytes, count; + uint32_t tickstart; + uint32_t fifoword; + uint8_t* pparams = ParametersTable; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ + fifoword = Param1; + nbBytes = (NbParams < 3U) ? NbParams : 3U; + + for(count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count))); + } + hdsi->Instance->GPDR = fifoword; + + uicounter = NbParams - nbBytes; + pparams += nbBytes; + /* Set the Next parameters on the write FIFO command*/ + while(uicounter != 0U) + { + nbBytes = (uicounter < 4U) ? uicounter : 4U; + fifoword = 0U; + for(count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count)); + } + hdsi->Instance->GPDR = fifoword; + + uicounter -= nbBytes; + pparams += nbBytes; + } + + /* Configure the packet to send a long DCS command */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + ((NbParams+1U)&0x00FFU), + (((NbParams+1U)&0xFF00U)>>8U)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Read command (DCS or generic) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelNbr: Virtual channel ID + * @param Array: pointer to a buffer to store the payload of a read back operation. + * @param Size: Data size to be read (in byte). + * @param Mode: DSI read packet data type. + * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd: DCS get/read command. + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable) +{ + uint32_t tickstart; + uint8_t* pdata = Array; + uint32_t datasize = Size; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if(datasize > 2U) + { + /* set max return packet size */ + if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + + /* Configure the packet to read command */ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check that the payload read FIFO is not empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Get the first byte */ + *((uint32_t *)pdata) = (hdsi->Instance->GPDR); + if (datasize > 4U) + { + datasize -= 4U; + pdata += 4U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Get the remaining bytes if any */ + while(((int)(datasize)) > 0U) + { + if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) + { + *((uint32_t *)pdata) = (hdsi->Instance->GPDR); + datasize -= 4U; + pdata += 4U; + } + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* ULPS Request on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_URDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the D-PHY active lanes enter into ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Exit ULPS on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_UEDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms*/ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Clock lane configuration: no more HS request */ + hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; + + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLSAI2); + + /* ULPS Request on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms */ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); + + /* Restore clock lane configuration to HS */ + hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Mode: Pattern generator mode + * This parameter can be one of the following values: + * 0 : Color bars (horizontal or vertical) + * 1 : BER pattern (vertical only) + * @param Orientation: Pattern generator orientation + * This parameter can be one of the following values: + * 0 : Vertical color bars + * 1 : Horizontal color bars + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Configure pattern generator mode and orientation */ + hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); + hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U)); + + /* Enable pattern generator by setting PGE bit */ + hdsi->Instance->VMCR |= DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable pattern generator by clearing PGE bit */ + hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set Slew-Rate And Delay Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CommDelay: Communication delay to be adjusted. + * This parameter can be any value of @ref DSI_Communication_Delay + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param Value: Custom value of the slew-rate or delay + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); + assert_param(IS_DSI_LANE_GROUP(Lane)); + + switch(CommDelay) + { + case DSI_SLEW_RATE_HSTX: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Slew Rate Control on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; + hdsi->Instance->WPCR[1U] |= Value<<16U; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Slew Rate Control on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; + hdsi->Instance->WPCR[1U] |= Value<<18U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_SLEW_RATE_LPTX: + if(Lane == DSI_CLOCK_LANE) + { + /* Low-Power transmission Slew Rate Compensation on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; + hdsi->Instance->WPCR[1U] |= Value<<6U; + } + else if(Lane == DSI_DATA_LANES) + { + /* Low-Power transmission Slew Rate Compensation on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; + hdsi->Instance->WPCR[1U] |= Value<<8U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_HS_DELAY: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Delay on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; + hdsi->Instance->WPCR[1U] |= Value; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Delay on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; + hdsi->Instance->WPCR[1U] |= Value<<2U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Low-Power Reception Filter Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Low-Power RX low-pass Filtering Tuning */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; + hdsi->Instance->WPCR[1U] |= Frequency<<25U; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Activate an additional current path on all lanes to meet the SDDTx parameter + * defined in the MIPI D-PHY specification + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Activate/Disactivate additional current path on all lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; + hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Custom lane pins configuration + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CustomLane: Function to be applyed on selected lane. + * This parameter can be any value of @ref DSI_CustomLane + * @param Lane: select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @ref DSI_Lane_Select + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); + assert_param(IS_DSI_LANE(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(CustomLane) + { + case DSI_SWAP_LANE_PINS: + if(Lane == DSI_CLK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_INVERT_HS_SIGNAL: + if(Lane == DSI_CLK_LANE) + { + /* Invert HS signal on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Invert HS signal on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Invert HS signal on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set custom timing for the PHY + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Timing: PHY timing to be adjusted. + * This parameter can be any value of @ref DSI_PHY_Timing + * @param State: ENABLE or DISABLE + * @param Value: Custom value of the timing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_PHY_TIMING(Timing)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(Timing) + { + case DSI_TCLK_POST: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; + hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; + } + + break; + case DSI_TLPX_CLK: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; + hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; + } + + break; + case DSI_THS_EXIT: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; + hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; + } + + break; + case DSI_TLPX_DATA: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; + hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; + } + + break; + case DSI_THS_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; + hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; + } + + break; + case DSI_THS_TRAIL: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; + hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; + } + + break; + case DSI_THS_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; + hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; + } + + break; + case DSI_TCLK_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; + hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; + } + + break; + case DSI_TCLK_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; + hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; + } + + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force the Clock/Data Lane in TX Stop Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_LANE_GROUP(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + if(Lane == DSI_CLOCK_LANE) + { + /* Force/Unforce the Clock Lane in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); + } + else if(Lane == DSI_DATA_LANES) + { + /* Force/Unforce the Data Lanes in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force LP Receiver in Low-Power Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force/Unforce LP Receiver in Low-Power Mode */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; + hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force Data Lanes in RX Mode after a BTA + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force Data Lanes in RX Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable a pull-down on the lanes to prevent from floating states when unused + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Enable/Disable pull-down on lanes */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Switch off the contention detection on data lanes + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Contention Detection on Data Lanes OFF */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DSI state. + (+) Get error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DSI state + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL state + */ +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +{ + return hdsi->State; +} + +/** + * @brief Return the DSI error code + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DSI */ + +#endif /* HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h new file mode 100644 index 00000000000..5baeb926e3f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h @@ -0,0 +1,1296 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dsi.h + * @author MCD Application Team + * @brief Header file of DSI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_DSI_H +#define __STM32L4xx_HAL_DSI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(DSI) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup DSI DSI + * @brief DSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DSI Init Structure definition + */ +typedef struct +{ + uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control + This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ + + uint32_t TXEscapeCkdiv; /*!< TX Escape clock division + The values 0 and 1 stop the TX_ESC clock generation */ + + uint32_t NumberOfLanes; /*!< Number of lanes + This parameter can be any value of @ref DSI_Number_Of_Lanes */ + +}DSI_InitTypeDef; + +/** + * @brief DSI PLL Clock structure definition + */ +typedef struct +{ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ + + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ + + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ + +}DSI_PLLInitTypeDef; + +/** + * @brief DSI Video mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using + 18-bit configuration). + This parameter can be any value of @ref DSI_LooselyPacked */ + + uint32_t Mode; /*!< Video mode type + This parameter can be any value of @ref DSI_Video_Mode_Type */ + + uint32_t PacketSize; /*!< Video packet size */ + + uint32_t NumberOfChunks; /*!< Number of chunks */ + + uint32_t NullPacketSize; /*!< Null packet size */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ + + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ + + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ + + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ + + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ + + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ + + uint32_t VerticalActive; /*!< Vertical active duration */ + + uint32_t LPCommandEnable; /*!< Low-power command enable + This parameter can be any value of @ref DSI_LP_Command */ + + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP and VFP regions */ + + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VACT region */ + + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable + This parameter can be any value of @ref DSI_LP_HFP */ + + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable + This parameter can be any value of @ref DSI_LP_HBP */ + + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable + This parameter can be any value of @ref DSI_LP_VACT */ + + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable + This parameter can be any value of @ref DSI_LP_VFP */ + + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable + This parameter can be any value of @ref DSI_LP_VBP */ + + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable + This parameter can be any value of @ref DSI_LP_VSYNC */ + + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable + This parameter can be any value of @ref DSI_FBTA_acknowledge */ + +}DSI_VidCfgTypeDef; + +/** + * @brief DSI Adapted command mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + pixels. This parameter can be any value between 0x00 and 0xFFFFU */ + + uint32_t TearingEffectSource; /*!< Tearing effect source + This parameter can be any value of @ref DSI_TearingEffectSource */ + + uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity + This parameter can be any value of @ref DSI_TearingEffectPolarity */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted + This parameter can be any value of @ref DSI_Vsync_Polarity */ + + uint32_t AutomaticRefresh; /*!< Automatic refresh mode + This parameter can be any value of @ref DSI_AutomaticRefresh */ + + uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable + This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ + +}DSI_CmdCfgTypeDef; + +/** + * @brief DSI command transmission mode configuration + */ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ + + uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ + + uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ + + uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ + + uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ + + uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ + + uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ + + uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ + + uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ + + uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ + + uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ + + uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission + This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ + + uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable + This parameter can be any value of @ref DSI_AcknowledgeRequest */ + +}DSI_LPCmdTypeDef; + +/** + * @brief DSI PHY Timings definition + */ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed + to low-power transmission */ + + uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed + to low-power transmission */ + + uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ + + uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the + Stop state */ + +}DSI_PHY_TimerTypeDef; + +/** + * @brief DSI HOST Timeouts definition + */ +typedef struct +{ + uint32_t TimeoutCkdiv; /*!< Time-out clock division */ + + uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ + + uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ + + uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ + + uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ + + uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ + + uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode + This parameter can be any value of @ref DSI_HS_PrespMode */ + + uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ + + uint32_t BTATimeout; /*!< BTA time-out */ + +}DSI_HOST_TimeoutTypeDef; + +/** + * @brief DSI States Structure definition + */ +typedef enum +{ + HAL_DSI_STATE_RESET = 0x00U, + HAL_DSI_STATE_READY = 0x01U, + HAL_DSI_STATE_ERROR = 0x02U, + HAL_DSI_STATE_BUSY = 0x03U, + HAL_DSI_STATE_TIMEOUT = 0x04U +}HAL_DSI_StateTypeDef; + +/** + * @brief DSI Handle Structure definition + */ +typedef struct +{ + DSI_TypeDef *Instance; /*!< Register base address */ + DSI_InitTypeDef Init; /*!< DSI required parameters */ + HAL_LockTypeDef Lock; /*!< DSI peripheral status */ + __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ + __IO uint32_t ErrorCode; /*!< DSI Error code */ + uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ +}DSI_HandleTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_DCS_Command DSI DCS Command + * @{ + */ +#define DSI_ENTER_IDLE_MODE 0x39U +#define DSI_ENTER_INVERT_MODE 0x21U +#define DSI_ENTER_NORMAL_MODE 0x13U +#define DSI_ENTER_PARTIAL_MODE 0x12U +#define DSI_ENTER_SLEEP_MODE 0x10U +#define DSI_EXIT_IDLE_MODE 0x38U +#define DSI_EXIT_INVERT_MODE 0x20U +#define DSI_EXIT_SLEEP_MODE 0x11U +#define DSI_GET_3D_CONTROL 0x3FU +#define DSI_GET_ADDRESS_MODE 0x0BU +#define DSI_GET_BLUE_CHANNEL 0x08U +#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU +#define DSI_GET_DISPLAY_MODE 0x0DU +#define DSI_GET_GREEN_CHANNEL 0x07U +#define DSI_GET_PIXEL_FORMAT 0x0CU +#define DSI_GET_POWER_MODE 0x0AU +#define DSI_GET_RED_CHANNEL 0x06U +#define DSI_GET_SCANLINE 0x45U +#define DSI_GET_SIGNAL_MODE 0x0EU +#define DSI_NOP 0x00U +#define DSI_READ_DDB_CONTINUE 0xA8U +#define DSI_READ_DDB_START 0xA1U +#define DSI_READ_MEMORY_CONTINUE 0x3EU +#define DSI_READ_MEMORY_START 0x2EU +#define DSI_SET_3D_CONTROL 0x3DU +#define DSI_SET_ADDRESS_MODE 0x36U +#define DSI_SET_COLUMN_ADDRESS 0x2AU +#define DSI_SET_DISPLAY_OFF 0x28U +#define DSI_SET_DISPLAY_ON 0x29U +#define DSI_SET_GAMMA_CURVE 0x26U +#define DSI_SET_PAGE_ADDRESS 0x2BU +#define DSI_SET_PARTIAL_COLUMNS 0x31U +#define DSI_SET_PARTIAL_ROWS 0x30U +#define DSI_SET_PIXEL_FORMAT 0x3AU +#define DSI_SET_SCROLL_AREA 0x33U +#define DSI_SET_SCROLL_START 0x37U +#define DSI_SET_TEAR_OFF 0x34U +#define DSI_SET_TEAR_ON 0x35U +#define DSI_SET_TEAR_SCANLINE 0x44U +#define DSI_SET_VSYNC_TIMING 0x40U +#define DSI_SOFT_RESET 0x01U +#define DSI_WRITE_LUT 0x2DU +#define DSI_WRITE_MEMORY_CONTINUE 0x3CU +#define DSI_WRITE_MEMORY_START 0x2CU +/** + * @} + */ + +/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type + * @{ + */ +#define DSI_VID_MODE_NB_PULSES 0U +#define DSI_VID_MODE_NB_EVENTS 1U +#define DSI_VID_MODE_BURST 2U +/** + * @} + */ + +/** @defgroup DSI_Color_Mode DSI Color Mode + * @{ + */ +#define DSI_COLOR_MODE_FULL 0x00000000U +#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM +/** + * @} + */ + +/** @defgroup DSI_ShutDown DSI ShutDown + * @{ + */ +#define DSI_DISPLAY_ON 0x00000000U +#define DSI_DISPLAY_OFF DSI_WCR_SHTDN +/** + * @} + */ + +/** @defgroup DSI_LP_Command DSI LP Command + * @{ + */ +#define DSI_LP_COMMAND_DISABLE 0x00000000U +#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE +/** + * @} + */ + +/** @defgroup DSI_LP_HFP DSI LP HFP + * @{ + */ +#define DSI_LP_HFP_DISABLE 0x00000000U +#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE +/** + * @} + */ + +/** @defgroup DSI_LP_HBP DSI LP HBP + * @{ + */ +#define DSI_LP_HBP_DISABLE 0x00000000U +#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VACT DSI LP VACT + * @{ + */ +#define DSI_LP_VACT_DISABLE 0x00000000U +#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE +/** + * @} + */ + +/** @defgroup DSI_LP_VFP DSI LP VFP + * @{ + */ +#define DSI_LP_VFP_DISABLE 0x00000000U +#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE +/** + * @} + */ + +/** @defgroup DSI_LP_VBP DSI LP VBP + * @{ + */ +#define DSI_LP_VBP_DISABLE 0x00000000U +#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VSYNC DSI LP VSYNC + * @{ + */ +#define DSI_LP_VSYNC_DISABLE 0x00000000U +#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE +/** + * @} + */ + +/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge + * @{ + */ +#define DSI_FBTAA_DISABLE 0x00000000U +#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE +/** + * @} + */ + +/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source + * @{ + */ +#define DSI_TE_DSILINK 0x00000000U +#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC +/** + * @} + */ + +/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity + * @{ + */ +#define DSI_TE_RISING_EDGE 0x00000000U +#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL +/** + * @} + */ + +/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity + * @{ + */ +#define DSI_VSYNC_FALLING 0x00000000U +#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL +/** + * @} + */ + +/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh + * @{ + */ +#define DSI_AR_DISABLE 0x00000000U +#define DSI_AR_ENABLE DSI_WCFGR_AR +/** + * @} + */ + +/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request + * @{ + */ +#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE +/** + * @} + */ + +/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request + * @{ + */ +#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP + * @{ + */ +#define DSI_LP_GSW0P_DISABLE 0x00000000U +#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP + * @{ + */ +#define DSI_LP_GSW1P_DISABLE 0x00000000U +#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP + * @{ + */ +#define DSI_LP_GSW2P_DISABLE 0x00000000U +#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP + * @{ + */ +#define DSI_LP_GSR0P_DISABLE 0x00000000U +#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP + * @{ + */ +#define DSI_LP_GSR1P_DISABLE 0x00000000U +#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP + * @{ + */ +#define DSI_LP_GSR2P_DISABLE 0x00000000U +#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite + * @{ + */ +#define DSI_LP_GLW_DISABLE 0x00000000U +#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP + * @{ + */ +#define DSI_LP_DSW0P_DISABLE 0x00000000U +#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP + * @{ + */ +#define DSI_LP_DSW1P_DISABLE 0x00000000U +#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP + * @{ + */ +#define DSI_LP_DSR0P_DISABLE 0x00000000U +#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write + * @{ + */ +#define DSI_LP_DLW_DISABLE 0x00000000U +#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet + * @{ + */ +#define DSI_LP_MRDP_DISABLE 0x00000000U +#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS +/** + * @} + */ + +/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode + * @{ + */ +#define DSI_HS_PM_DISABLE 0x00000000U +#define DSI_HS_PM_ENABLE DSI_TCCR3_PM +/** + * @} + */ + + +/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control + * @{ + */ +#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U +#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR +/** + * @} + */ + +/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes + * @{ + */ +#define DSI_ONE_DATA_LANE 0U +#define DSI_TWO_DATA_LANES 1U +/** + * @} + */ + +/** @defgroup DSI_FlowControl DSI Flow Control + * @{ + */ +#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE +#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE +#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE +#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE +#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ + DSI_FLOW_CONTROL_EOTP_TX) +/** + * @} + */ + +/** @defgroup DSI_Color_Coding DSI Color Coding + * @{ + */ +#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 0x00000005U +/** + * @} + */ + +/** @defgroup DSI_LooselyPacked DSI Loosely Packed + * @{ + */ +#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE +#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity + * @{ + */ +#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP +/** + * @} + */ + +/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity + * @{ + */ +#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP +/** + * @} + */ + +/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity + * @{ + */ +#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U +#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP +/** + * @} + */ + +/** @defgroup DSI_PLL_IDF DSI PLL IDF + * @{ + */ +#define DSI_PLL_IN_DIV1 0x00000001U +#define DSI_PLL_IN_DIV2 0x00000002U +#define DSI_PLL_IN_DIV3 0x00000003U +#define DSI_PLL_IN_DIV4 0x00000004U +#define DSI_PLL_IN_DIV5 0x00000005U +#define DSI_PLL_IN_DIV6 0x00000006U +#define DSI_PLL_IN_DIV7 0x00000007U +/** + * @} + */ + +/** @defgroup DSI_PLL_ODF DSI PLL ODF + * @{ + */ +#define DSI_PLL_OUT_DIV1 0x00000000U +#define DSI_PLL_OUT_DIV2 0x00000001U +#define DSI_PLL_OUT_DIV4 0x00000002U +#define DSI_PLL_OUT_DIV8 0x00000003U +/** + * @} + */ + +/** @defgroup DSI_Flags DSI Flags + * @{ + */ +#define DSI_FLAG_TE DSI_WISR_TEIF +#define DSI_FLAG_ER DSI_WISR_ERIF +#define DSI_FLAG_BUSY DSI_WISR_BUSY +#define DSI_FLAG_PLLLS DSI_WISR_PLLLS +#define DSI_FLAG_PLLL DSI_WISR_PLLLIF +#define DSI_FLAG_PLLU DSI_WISR_PLLUIF +#define DSI_FLAG_RRS DSI_WISR_RRS +#define DSI_FLAG_RR DSI_WISR_RRIF +/** + * @} + */ + +/** @defgroup DSI_Interrupts DSI Interrupts + * @{ + */ +#define DSI_IT_TE DSI_WIER_TEIE +#define DSI_IT_ER DSI_WIER_ERIE +#define DSI_IT_PLLL DSI_WIER_PLLLIE +#define DSI_IT_PLLU DSI_WIER_PLLUIE +#define DSI_IT_RR DSI_WIER_RRIE +/** + * @} + */ + +/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ +/** + * @} + */ + +/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_Error_Data_Type DSI Error Data Type + * @{ + */ +#define HAL_DSI_ERROR_NONE 0U +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +/** + * @} + */ + +/** @defgroup DSI_Lane_Group DSI Lane Group + * @{ + */ +#define DSI_CLOCK_LANE 0x00000000U +#define DSI_DATA_LANES 0x00000001U +/** + * @} + */ + +/** @defgroup DSI_Communication_Delay DSI Communication Delay + * @{ + */ +#define DSI_SLEW_RATE_HSTX 0x00000000U +#define DSI_SLEW_RATE_LPTX 0x00000001U +#define DSI_HS_DELAY 0x00000002U +/** + * @} + */ + +/** @defgroup DSI_CustomLane DSI CustomLane + * @{ + */ +#define DSI_SWAP_LANE_PINS 0x00000000U +#define DSI_INVERT_HS_SIGNAL 0x00000001U +/** + * @} + */ + +/** @defgroup DSI_Lane_Select DSI Lane Select + * @{ + */ +#define DSI_CLK_LANE 0x00000000U +#define DSI_DATA_LANE0 0x00000001U +#define DSI_DATA_LANE1 0x00000002U +/** + * @} + */ + +/** @defgroup DSI_PHY_Timing DSI PHY Timing + * @{ + */ +#define DSI_TCLK_POST 0x00000000U +#define DSI_TLPX_CLK 0x00000001U +#define DSI_THS_EXIT 0x00000002U +#define DSI_TLPX_DATA 0x00000003U +#define DSI_THS_ZERO 0x00000004U +#define DSI_THS_TRAIL 0x00000005U +#define DSI_THS_PREPARE 0x00000006U +#define DSI_TCLK_ZERO 0x00000007U +#define DSI_TCLK_PREPARE 0x00000008U +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Reset DSI handle state. + * @param __HANDLE__: DSI handle + * @retval None + */ +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) + +/** + * @brief Enables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Enables the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disable the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Enables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Enables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Get the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_BUSY : Busy Flag + * @arg DSI_FLAG_PLLLS: PLL Lock Status + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RRS : Regulator Ready Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) + +/** + * @brief Clears the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval None + */ +#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) + +/** + * @brief Enables the specified DSI interrupts. + * @param __HANDLE__: DSI handle. + * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DSI interrupts. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DSI interrupt source is enabled or not. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * This parameter can be one of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Functions DSI Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); + +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); + +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DSI_Private_Types DSI Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup DSI_Private_Defines DSI Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Variables DSI Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Constants DSI Private Constants + * @{ + */ +#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DSI_Private_Macros DSI Private Macros + * @{ + */ +#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) +#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ + ((IDF) == DSI_PLL_IN_DIV2) || \ + ((IDF) == DSI_PLL_IN_DIV3) || \ + ((IDF) == DSI_PLL_IN_DIV4) || \ + ((IDF) == DSI_PLL_IN_DIV5) || \ + ((IDF) == DSI_PLL_IN_DIV6) || \ + ((IDF) == DSI_PLL_IN_DIV7)) +#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ + ((ODF) == DSI_PLL_OUT_DIV2) || \ + ((ODF) == DSI_PLL_OUT_DIV4) || \ + ((ODF) == DSI_PLL_OUT_DIV8)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) +#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ + ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ + ((VideoModeType) == DSI_VID_MODE_BURST)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) +#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) +#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) +#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ + ((MODE) == DSI_GEN_LONG_PKT_WRITE)) +#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ + ((Timing) == DSI_TLPX_CLK ) || \ + ((Timing) == DSI_THS_EXIT ) || \ + ((Timing) == DSI_TLPX_DATA ) || \ + ((Timing) == DSI_THS_ZERO ) || \ + ((Timing) == DSI_THS_TRAIL ) || \ + ((Timing) == DSI_THS_PREPARE ) || \ + ((Timing) == DSI_TCLK_ZERO ) || \ + ((Timing) == DSI_TCLK_PREPARE)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_DSI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c index 7f385889cc4..f3fd43776a0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_firewall.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FIREWALL HAL module driver. * This file provides firmware functions to manage the Firewall * Peripheral initialization and enabling. @@ -11,19 +9,19 @@ * @verbatim =============================================================================== - ##### How to use this driver ##### + ##### How to use this driver ##### =============================================================================== [..] The FIREWALL HAL driver can be used as follows: - + (#) Declare a FIREWALL_InitTypeDef initialization structure. - + (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API - + (#) To ensure that any code executed outside the protected segment closes the - FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling + FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment or HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment @@ -58,7 +56,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -68,12 +66,12 @@ * @{ */ -/** @defgroup FIREWALL FIREWALL +/** @defgroup FIREWALL FIREWALL * @brief HAL FIREWALL module driver * @{ */ #ifdef HAL_FIREWALL_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -86,27 +84,27 @@ * @{ */ -/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions - * @brief Initialization and Configuration Functions +/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions + * @brief Initialization and Configuration Functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This subsection provides the functions allowing to initialize the Firewall. - Initialization is done by HAL_FIREWALL_Config(): + Initialization is done by HAL_FIREWALL_Config(): (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro. - + (+) Set the protected code segment address start and length. - - (+) Set the protected non-volatile and/or volatile data segments - address starts and lengths if applicable. - + + (+) Set the protected non-volatile and/or volatile data segments + address starts and lengths if applicable. + (+) Set the volatile data segment execution and sharing status. - - (+) Length must be set to 0 for an unprotected segment. + + (+) Length must be set to 0 for an unprotected segment. @endverbatim * @{ @@ -115,7 +113,7 @@ /** * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters. * @param fw_init: Firewall initialization structure - * @note The API returns HAL_ERROR if the Firewall is already enabled. + * @note The API returns HAL_ERROR if the Firewall is already enabled. * @retval HAL status */ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) @@ -125,7 +123,7 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) { return HAL_ERROR; } - + /* Enable Firewall clock */ __HAL_RCC_FIREWALL_CLK_ENABLE(); @@ -134,53 +132,58 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) { return HAL_ERROR; } - + /* Check Firewall configuration addresses and lengths when segment is protected */ /* Code segment */ if (fw_init->CodeSegmentLength != 0) { assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress)); - assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); + assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); + /* Make sure that NonVDataSegmentLength is properly set to prevent code segment access */ + if (fw_init->NonVDataSegmentLength < 0x100) + { + return HAL_ERROR; + } } /* Non volatile data segment */ if (fw_init->NonVDataSegmentLength != 0) { assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress)); - assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); + assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); } /* Volatile data segment */ if (fw_init->VDataSegmentLength != 0) { assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress)); - assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); + assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); } - + /* Check Firewall Configuration Register parameters */ assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution)); assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared)); - - + + /* Configuration */ - + /* Protected code segment start address configuration */ WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress)); /* Protected code segment length configuration */ WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength)); - + /* Protected non volatile data segment start address configuration */ WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress)); /* Protected non volatile data segment length configuration */ WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength)); - + /* Protected volatile data segment start address configuration */ WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress)); /* Protected volatile data segment length configuration */ - WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); - + WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); + /* Set Firewall Configuration Register VDE and VDS bits - (volatile data execution and shared configuration) */ + (volatile data execution and shared configuration) */ MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared); - + return HAL_OK; } @@ -189,71 +192,71 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) * @param fw_config: Firewall configuration, type is same as initialization structure * @note This API can't be executed inside a code area protected by the Firewall * when the Firewall is enabled - * @note If NVDSL register is different from 0, that is, if the non volatile data segment - * is defined, this API can't be executed when the Firewall is enabled. - * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status + * @note If NVDSL register is different from 0, that is, if the non volatile data segment + * is defined, this API can't be executed when the Firewall is enabled. + * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status * @retval None */ void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config) { - /* Enable Firewall clock, in case no Firewall configuration has been carried + /* Enable Firewall clock, in case no Firewall configuration has been carried out up to this point */ __HAL_RCC_FIREWALL_CLK_ENABLE(); /* Retrieve code segment protection setting */ fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD); fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG); - + /* Retrieve non volatile data segment protection setting */ fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD); fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG); - + /* Retrieve volatile data segment protection setting */ fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD); - fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG); - + fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG); + /* Retrieve volatile data execution setting */ fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE); - + /* Retrieve volatile data shared setting */ fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS); - + return; } /** - * @brief Enable FIREWALL. + * @brief Enable FIREWALL. * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register. - * Once enabled, the Firewall cannot be disabled by software. Only a - * system reset can set again FWDIS bit. + * Once enabled, the Firewall cannot be disabled by software. Only a + * system reset can set again FWDIS bit. * @retval None */ void HAL_FIREWALL_EnableFirewall(void) { /* Clears FWDIS bit of SYSCFG CFGR1 register */ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS); - + } /** - * @brief Enable FIREWALL pre arm. - * @note When FPA bit is set, any code executed outside the protected segment - * will close the Firewall. + * @brief Enable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment + * will close the Firewall. * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro - * but can't be executed inside a code area protected by the Firewall. - * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. - * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, + * but can't be executed inside a code area protected by the Firewall. + * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. + * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, * when the non volatile data segment is not defined), * ** this API can be executed when the Firewall is closed - * ** when the Firewall is opened, user should resort to + * ** when the Firewall is opened, user should resort to * __HAL_FIREWALL_PREARM_ENABLE() macro instead * @note When the Firewall is enabled and NVDSL register is different from 0 * (that is, when the non volatile data segment is defined) - * ** FW_CR register can be accessed only when the Firewall is opened: - * user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead. + * ** FW_CR register can be accessed only when the Firewall is opened: + * user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead. * @retval None */ void HAL_FIREWALL_EnablePreArmFlag(void) @@ -265,21 +268,21 @@ void HAL_FIREWALL_EnablePreArmFlag(void) /** * @brief Disable FIREWALL pre arm. - * @note When FPA bit is reset, any code executed outside the protected segment + * @note When FPA bit is reset, any code executed outside the protected segment * when the Firewall is opened will generate a system reset. * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro * but can't be executed inside a code area protected by the Firewall. - * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. - * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, + * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. + * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, * when the non volatile data segment is not defined), * ** this API can be executed when the Firewall is closed - * ** when the Firewall is opened, user should resort to + * ** when the Firewall is opened, user should resort to * __HAL_FIREWALL_PREARM_DISABLE() macro instead * @note When the Firewall is enabled and NVDSL register is different from 0 * (that is, when the non volatile data segment is defined) - * ** FW_CR register can be accessed only when the Firewall is opened: - * user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead. - + * ** FW_CR register can be accessed only when the Firewall is opened: + * user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead. + * @retval None */ void HAL_FIREWALL_DisablePreArmFlag(void) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h index 77add8b1dc5..00954474b9a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_firewall.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FIREWALL HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c index d95af67b923..ec118ec8373 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -120,7 +118,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 +#else #define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 +#endif /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables @@ -320,7 +322,8 @@ void HAL_FLASH_IRQHandler(void) /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); #endif @@ -337,7 +340,8 @@ void HAL_FLASH_IRQHandler(void) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) #else (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) @@ -500,18 +504,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { + HAL_StatusTypeDef status = HAL_OK; + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); - } - else - { - return HAL_ERROR; + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - return HAL_OK; + return status; } /** @@ -642,13 +650,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t tickstart = HAL_GetTick(); while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart) >= Timeout) { return HAL_TIMEOUT; } @@ -661,7 +669,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) #else (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) @@ -746,7 +755,8 @@ static void FLASH_SetErrorCode(void) } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h index b74c513b777..e05c897baa8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -176,7 +174,8 @@ typedef struct #define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) #define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) #endif /** @@ -197,7 +196,8 @@ typedef struct */ #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ #else @@ -237,7 +237,8 @@ typedef struct #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ #endif @@ -267,20 +268,29 @@ typedef struct #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ +#else #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ #endif +#endif #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ +#endif /** * @} */ @@ -361,7 +371,8 @@ typedef struct */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode * @{ */ @@ -370,6 +381,16 @@ typedef struct /** * @} */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type + * @{ + */ +#define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ +#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ +/** + * @} + */ +#else /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type * @{ */ @@ -379,7 +400,18 @@ typedef struct * @} */ #endif +#endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type + * @{ + */ +#define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ +#define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ +#endif +/** + * @} + */ /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type * @{ */ @@ -409,7 +441,8 @@ typedef struct #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 * @{ */ @@ -448,6 +481,19 @@ typedef struct #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ +#endif /** * @} */ @@ -455,16 +501,16 @@ typedef struct /** @defgroup FLASH_Keys FLASH Keys * @{ */ -#define FLASH_KEY1 ((uint32_t)0x45670123U) /*!< Flash key1 */ -#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash key2: used with FLASH_KEY1 +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access */ -#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ -#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 +#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ +#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR */ -#define FLASH_OPTKEY1 ((uint32_t)0x08192A3BU) /*!< Flash option byte key1 */ -#define FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU) /*!< Flash option byte key2: used with FLASH_OPTKEY1 +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations */ /** * @} @@ -486,7 +532,8 @@ typedef struct #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ #endif #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ @@ -512,10 +559,6 @@ typedef struct * @} */ -/** - * @} - */ - /* Exported macros -----------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @brief macros to control FLASH features @@ -779,7 +822,10 @@ uint32_t HAL_FLASH_GetError(void); */ #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) #else @@ -788,13 +834,19 @@ uint32_t HAL_FLASH_GetError(void); #endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) #else #define FLASH_BANK_SIZE (FLASH_SIZE) #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_PAGE_SIZE ((uint32_t)0x1000) +#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) +#else #define FLASH_PAGE_SIZE ((uint32_t)0x800) +#endif #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ /** @@ -810,7 +862,8 @@ uint32_t HAL_FLASH_GetError(void); ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2) || \ ((BANK) == FLASH_BANK_BOTH)) @@ -827,17 +880,23 @@ uint32_t HAL_FLASH_GetError(void); ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) +#else #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) +#endif #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) +#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ @@ -855,7 +914,8 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) #else @@ -866,7 +926,9 @@ uint32_t HAL_FLASH_GetError(void); ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ ((LEVEL) == OB_RDP_LEVEL_2)*/) -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) +#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) #else #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) @@ -891,12 +953,17 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) +#endif + #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) @@ -905,7 +972,8 @@ uint32_t HAL_FLASH_GetError(void); #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) @@ -913,11 +981,26 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) +#else #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ ((LATENCY) == FLASH_LATENCY_1) || \ ((LATENCY) == FLASH_LATENCY_2) || \ ((LATENCY) == FLASH_LATENCY_3) || \ ((LATENCY) == FLASH_LATENCY_4)) +#endif +/** + * @} + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c index bd6efe72883..1ba98a0c1b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extended peripheral: @@ -85,7 +83,7 @@ */ /** @defgroup FLASHEx FLASHEx - * @brief FALSH Extended HAL module driver + * @brief FLASH Extended HAL module driver * @{ */ @@ -124,7 +122,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC */ /* Exported functions -------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ @@ -208,7 +206,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* If the erase operation is completed, disable the MER1 and MER2 Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); #else @@ -405,7 +404,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) #else @@ -424,7 +424,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->USERConfig = FLASH_OB_GetUser(); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) #else if(pOBInit->PCROPConfig == FLASH_BANK_1) @@ -440,9 +441,83 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * @} */ +#if defined (FLASH_CFGR_LVEN) +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions + * @brief Extended specific configuration functions + * +@verbatim + =============================================================================== + ##### Extended specific configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + specific configurations. + +@endverbatim + * @{ + */ + +/** + * @brief Configuration of the LVE pin of the Flash (managed by power controller + * or forced to low in order to use an external SMPS) + * @param ConfigLVE: Configuration of the LVE pin, + * This parameter can be one of the following values: + * @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller + * @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used) + * + * @note Before enforcing the LVE pin to low, the SOC should be in low voltage + * range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_LVE_PIN(ConfigLVE)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Check that the voltage scaling is range 2 */ + if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Configure the LVEN bit */ + MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); + + /* Check that the bit has been correctly configured */ + if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) + { + status = HAL_ERROR; + } + } + else + { + /* Not allow to force Flash LVE pin if not in voltage range 2 */ + status = HAL_ERROR; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + /** * @} - */ + */ +#endif /* FLASH_CFGR_LVEN */ + +/** + * @} + */ /* Private functions ---------------------------------------------------------*/ @@ -460,6 +535,9 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) */ static void FLASH_MassErase(uint32_t Banks) { +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != RESET) +#endif { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); @@ -471,7 +549,8 @@ static void FLASH_MassErase(uint32_t Banks) } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Set the Mass Erase Bit for the bank 2 if requested */ if((Banks & FLASH_BANK_2) != RESET) { @@ -479,6 +558,12 @@ static void FLASH_MassErase(uint32_t Banks) } #endif } +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + else + { + SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); + } +#endif /* Proceed to erase all sectors */ SET_BIT(FLASH->CR, FLASH_CR_STRT); @@ -500,7 +585,15 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) assert_param(IS_FLASH_PAGE(Page)); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + { + CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); + } + else +#endif { assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); @@ -604,7 +697,8 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO (WRPStartOffset | (WRDPEndOffset << 16))); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(WRPArea == OB_WRPAREA_BANK2_AREAA) { MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), @@ -787,7 +881,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((UserType & OB_USER_BFB2) != RESET) { /* BFB2 option byte should be modified */ @@ -800,12 +895,21 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon if((UserType & OB_USER_DUALBANK) != RESET) { +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + /* DUALBANK option byte should be modified */ + assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M)); + + /* Set value and mask for DUALBANK option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M); + optr_reg_mask |= FLASH_OPTR_DB1M; +#else /* DUALBANK option byte should be modified */ assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); /* Set value and mask for DUALBANK option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); optr_reg_mask |= FLASH_OPTR_DUALBANK; +#endif } #endif @@ -841,7 +945,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((UserType & OB_USER_nSWBOOT0) != RESET) { /* nSWBOOT0 option byte should be modified */ @@ -905,7 +1010,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR uint32_t reg_value = 0; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) uint32_t bank2_addr; #endif @@ -921,7 +1027,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR if(status == HAL_OK) { #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) { @@ -937,6 +1044,29 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR bank1_addr = FLASH_BASE; #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + { + /* Configure the Proprietary code readout protection */ + if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) + { + reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); + + reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); + } + else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) + { + reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); + + reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); + } + } + else +#endif { /* Configure the Proprietary code readout protection */ if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) @@ -948,7 +1078,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = ((PCROPStartAddr - bank2_addr) >> 3); @@ -1007,7 +1138,8 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_ *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(WRPArea == OB_WRPAREA_BANK2_AREAA) { *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); @@ -1082,12 +1214,14 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t reg_value = 0; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) uint32_t bank2_addr; #endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) { @@ -1103,6 +1237,28 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, bank1_addr = FLASH_BASE; #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + { + if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) + { + reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); + *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; + + reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); + *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; + } + else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) + { + reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); + *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; + + reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); + *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; + } + } + else +#endif { if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { @@ -1113,7 +1269,8 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, *PCROPEndAddr = (reg_value << 3) + bank1_addr; } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h index 80e85f17200..63d5c9fcd1c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FLASH HAL Extended module. ****************************************************************************** * @attention @@ -52,15 +50,32 @@ /** @addtogroup FLASHEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +#if defined (FLASH_CFGR_LVEN) +/** @addtogroup FLASHEx_Exported_Constants + * @{ + */ +/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration + * @{ + */ +#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */ +#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */ +/** + * @} + */ + +/** + * @} + */ +#endif /* FLASH_CFGR_LVEN */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ */ @@ -75,19 +90,40 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); /** * @} - */ + */ +#if defined (FLASH_CFGR_LVEN) +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE); /** * @} - */ + */ +#endif /* FLASH_CFGR_LVEN */ /** * @} - */ + */ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#if defined (FLASH_CFGR_LVEN) +#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED)) +#endif /* FLASH_CFGR_LVEN */ +/** + @endcond + */ + +/** + * @} + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c index 6382464fc45..fbd9462a1aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM @@ -132,6 +130,122 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) return HAL_OK; } +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/** + * @brief Program the FLASH DBANK User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To modify the DBANK option byte, no PCROP region should be defined. + * To deactivate PCROP, user should perform RDP changing + * + * @param DBankConfig: The FLASH DBANK User Option Byte value. + * This parameter can be one of the following values: + * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data + * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data + * + * @retval HAL status + */ +__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) +{ + register uint32_t count, reg; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check if the PCROP is disabled */ + reg = FLASH->PCROP1SR; + if (reg > FLASH->PCROP1ER) + { + reg = FLASH->PCROP2SR; + if (reg > FLASH->PCROP2ER) + { + /* Disable Flash prefetch */ + __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); + + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + { + /* Disable Flash instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + + /* Flush Flash instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + } + + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + /* Disable Flash data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + + /* Flush Flash data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + } + + /* Disable WRP zone 1 of 1st bank if needed */ + reg = FLASH->WRP1AR; + if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_STRT)) <= + ((reg & FLASH_WRP1AR_WRP1A_END) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_END))) + { + MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); + } + + /* Disable WRP zone 2 of 1st bank if needed */ + reg = FLASH->WRP1BR; + if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_STRT)) <= + ((reg & FLASH_WRP1BR_WRP1B_END) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_END))) + { + MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); + } + + /* Disable WRP zone 1 of 2nd bank if needed */ + reg = FLASH->WRP2AR; + if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_STRT)) <= + ((reg & FLASH_WRP2AR_WRP2A_END) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_END))) + { + MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); + } + + /* Disable WRP zone 2 of 2nd bank if needed */ + reg = FLASH->WRP2BR; + if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_STRT)) <= + ((reg & FLASH_WRP2BR_WRP2B_END) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_END))) + { + MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); + } + + /* Modify the DBANK user option byte */ + MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); + + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Wait for last operation to be completed */ + /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ + count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8 / 1000); + do + { + if (count-- == 0) + { + break; + } + } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); + + /* If the option byte program operation is completed, disable the OPTSTRT Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h index a09dd20d661..b0988b0278e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention @@ -100,6 +98,9 @@ /* Peripheral Control functions ************************************************/ __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); +#endif /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c new file mode 100644 index 00000000000..1a8dd036577 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c @@ -0,0 +1,567 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_gfxmmu.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Graphic MMU (GFXMMU) peripheral: + * + Initialization and De-initialization. + * + LUT configuration. + * + Modify physical buffer adresses. + * + Error management. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() : + (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts are used, enable and configure GFXMMU global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the number of blocks per line, default value, physical + buffer addresses and interrupts using the HAL_GFXMMU_Init() function. + + *** LUT configuration *** + ========================= + [..] + (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a + range of lines). + (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM. + (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT. + + *** Modify physical buffer adresses *** + ======================================= + [..] + (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses. + + *** Error management *** + ======================== + [..] + (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when + an error occurs. This function will call HAL_GFXMMU_ErrorCallback(). + Use HAL_GFXMMU_GetError() to get the error code. + + *** De-initialization *** + ========================= + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() : + (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts has been used, disable GFXMMU global interrupt with + HAL_NVIC_DisableIRQ(). + (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ +#ifdef HAL_GFXMMU_MODULE_ENABLED +#if defined(GFXMMU) +/** @defgroup GFXMMU GFXMMU + * @brief GFXMMU HAL driver module + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define GFXMMU_LUTXL_FVB_OFFSET 8U +#define GFXMMU_LUTXL_LVB_OFFSET 16U +#define GFXMMU_CR_ITS_MASK 0x1FU +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the GFXMMU. + (+) De-initialize the GFXMMU. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GFXMMU according to the specified parameters in the + * GFXMMU_InitTypeDef structure and initialize the associated handle. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if(hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address)); + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation)); + + /* Call GFXMMU MSP init function */ + HAL_GFXMMU_MspInit(hgfxmmu); + + /* Configure blocks per line and interrupts parameters on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE | GFXMMU_CR_192BM); + hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine); + if(hgfxmmu->Init.Interrupts.Activation == ENABLE) + { + assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts)); + hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts; + } + + /* Configure default value on GFXMMU_DVR register */ + hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue; + + /* Configure physical buffer adresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address; + hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address; + hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address; + hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address; + + /* Reset GFXMMU error code */ + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Set GFXMMU to ready state */ + hgfxmmu->State = HAL_GFXMMU_STATE_READY; + } + /* Return function status */ + return status; +} + +/** + * @brief De-initialize the GFXMMU. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if(hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + + /* Disable all interrupts on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE); + + /* Call GFXMMU MSP de-init function */ + HAL_GFXMMU_MspDeInit(hgfxmmu); + + /* Set GFXMMU to reset state */ + hgfxmmu->State = HAL_GFXMMU_STATE_RESET; + } + /* Return function status */ + return status; +} + +/** + * @brief Initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspInit could be implemented in the user file. + */ +} + +/** + * @brief De-initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspDeInit could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions + * @brief GFXMMU operation functions + * +@verbatim + ============================================================================== + ##### Operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure LUT. + (+) Modify physical buffer adresses. + (+) Manage error. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to copy LUT from flash to look up RAM. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line enabled on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines enabled on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @param Address Start address of LUT in flash. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + else + { + uint32_t current_address, current_line, lutxl_address, lutxh_address; + + /* Initialize local variables */ + current_address = Address; + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Copy LUT from flash to look up RAM */ + while(current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = *((uint32_t *)current_address); + current_address += 4U; + *((uint32_t *)lutxh_address) = *((uint32_t *)current_address); + current_address += 4U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to disable a range of LUT lines. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line to disable on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines to disable on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + else + { + uint32_t current_line, lutxl_address, lutxh_address; + + /* Initialize local variables */ + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Disable LUT lines */ + while(current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to configure one line of LUT. + * @param hgfxmmu GFXMMU handle. + * @param lutLine LUT line parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber)); + assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock)); + assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset)); + + /* Check GFXMMU state */ + if(hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + uint32_t lutxl_address, lutxh_address; + + /* Initialize local variables */ + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]); + + /* Configure LUT line */ + if(lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE) + { + /* Enable and configure LUT line */ + *((uint32_t *)lutxl_address) = (lutLine->LineStatus | + (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) | + (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET)); + *((uint32_t *)lutxh_address) = lutLine->LineOffset; + } + else + { + /* Disable LUT line */ + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to modify physical buffer addresses. + * @param hgfxmmu GFXMMU handle. + * @param Buffers Buffers parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address)); + + /* Check GFXMMU state */ + if(hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + /* Modify physical buffer adresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = Buffers->Buf0Address; + hgfxmmu->Instance->B1CR = Buffers->Buf1Address; + hgfxmmu->Instance->B2CR = Buffers->Buf2Address; + hgfxmmu->Instance->B3CR = Buffers->Buf3Address; + } + /* Return function status */ + return status; +} + +/** + * @brief This function handles the GFXMMU interrupts. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t flags, interrupts, error; + + /* Read current flags and interrupts and determine which error occurs */ + flags = hgfxmmu->Instance->SR; + interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK); + error = (flags & interrupts); + + if(error != 0U) + { + /* Clear flags on GFXMMU_FCR register */ + hgfxmmu->Instance->FCR = error; + + /* Update GFXMMU error code */ + hgfxmmu->ErrorCode |= error; + + /* Call GFXMMU error callback */ + HAL_GFXMMU_ErrorCallback(hgfxmmu); + } +} + +/** + * @brief Error callback. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_GFXMMU_ErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @brief GFXMMU state functions + * +@verbatim + ============================================================================== + ##### State functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get GFXMMU handle state. + (+) Get GFXMMU error code. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to get the current GFXMMU handle state. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU state. + */ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Return GFXMMU handle state */ + return hgfxmmu->State; +} + +/** + * @brief This function allows to get the current GFXMMU error code. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU error code. + */ +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t error_code; + + /* Enter in critical section */ + __disable_irq(); + + /* Store and reset GFXMMU error code */ + error_code = hgfxmmu->ErrorCode; + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Exit from critical section */ + __enable_irq(); + + /* Return GFXMMU error code */ + return error_code; +} + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ +#endif /* GFXMMU */ +#endif /* HAL_GFXMMU_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h new file mode 100644 index 00000000000..7c8e6622b3c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_gfxmmu.h + * @author MCD Application Team + * @brief Header file of GFXMMU HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_GFXMMU_H +#define __STM32L4xx_HAL_GFXMMU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(GFXMMU) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup GFXMMU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types + * @{ + */ + +/** + * @brief HAL GFXMMU states definition + */ +typedef enum +{ + HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */ + HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */ +}HAL_GFXMMU_StateTypeDef; + +/** + * @brief GFXMMU buffers structure definition + */ +typedef struct +{ + uint32_t Buf0Address; /*!< Physical address of buffer 0. */ + uint32_t Buf1Address; /*!< Physical address of buffer 1. */ + uint32_t Buf2Address; /*!< Physical address of buffer 2. */ + uint32_t Buf3Address; /*!< Physical address of buffer 3. */ +}GFXMMU_BuffersTypeDef; + +/** + * @brief GFXMMU interrupts structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Interrupts enable/disable */ + uint32_t UsedInterrupts; /*!< Interrupts used. + This parameter can be a values combination of @ref GFXMMU_Interrupts. + @note: Usefull only when interrupts are enabled. */ +}GFXMMU_InterruptsTypeDef; + +/** + * @brief GFXMMU init structure definition + */ +typedef struct +{ + uint32_t BlocksPerLine; /*!< Number of blocks of 16 bytes per line. + This parameter can be a value of @ref GFXMMU_BlocksPerLine. */ + uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */ + GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */ + GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */ +}GFXMMU_InitTypeDef; + +/** + * @brief GFXMMU handle structure definition + */ +typedef struct +{ + GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */ + GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */ + HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */ + __IO uint32_t ErrorCode; /*!< GFXMMU error code */ +}GFXMMU_HandleTypeDef; + +/** + * @brief GFXMMU LUT line structure definition + */ +typedef struct +{ + uint32_t LineNumber; /*!< LUT line number. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */ + uint32_t LineStatus; /*!< LUT line enable/disable. + This parameter can be a value of @ref GFXMMU_LutLineStatus. */ + uint32_t FirstVisibleBlock; /*!< First visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + uint32_t LastVisibleBlock; /*!< Last visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer. + This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208. + @note: Line offset has to be computed with the following formula: + LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */ +}GFXMMU_LutLineTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants + * @{ + */ + +/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line + * @{ + */ +#define GFXMMU_256BLOCKS 0x00000000U /*!< 256 blocks of 16 bytes per line */ +#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */ +/** + * @} + */ + +/** @defgroup GFXMMU_Interrupts GFXMMU interrupts + * @{ + */ +#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */ +#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */ +#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */ +#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */ +#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */ +/** + * @} + */ + +/** @defgroup GFXMMU_Error_Code GFXMMU Error Code + * @{ + */ +#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error */ +#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */ +#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */ +#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */ +#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */ +#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */ +/** + * @} + */ + +/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status + * @{ + */ +#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled */ +#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros + * @{ + */ + +/** @brief Reset GFXMMU handle state. + * @param __HANDLE__ GFXMMU handle. + * @retval None + */ +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions + * @{ + */ +/* Operation functions ********************************************************/ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address); + +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber); + +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); + +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers); + +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); + +void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @{ + */ +/* State function *************************************************************/ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); + +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros +* @{ +*/ +#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \ + ((VALUE) == GFXMMU_192BLOCKS)) + +#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U) + +#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U) + +#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U) + +#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U)) + +#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \ + ((VALUE) == GFXMMU_LUT_LINE_ENABLE)) + +#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U) + +#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208)) +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GFXMMU */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_GFXMMU_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c index 7b52c96902f..280eb31cfcb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h index d386421f53b..9f4bbac5440 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h index b58d43c787f..63c69cb9e0e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of GPIO HAL Extended module. ****************************************************************************** * @attention @@ -572,6 +570,150 @@ #endif /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ +#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ +#define GPIO_AF5_OCTOSPIM_P1 ((uint8_t)0x05) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF5_OCTOSPIM_P2 ((uint8_t)0x05) /* OctoSPI Manager Port 2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ +#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF10_OCTOSPIM_P2 ((uint8_t)0x0A) /* OctoSPI Manager Port 2 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ +#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ +#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} */ @@ -641,6 +783,18 @@ #endif /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c index 2b84bd69cc3..7fbd5f94f0b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -140,7 +138,7 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -182,6 +180,14 @@ * @} */ +/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit + * @{ + */ +#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20 /*!< Number of words below which DMA suspension is aborted */ +/** + * @} + */ + /** * @} */ @@ -1083,9 +1089,32 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) } else { - /* Set State as suspended (it may be required to update it if suspension failed). - The context saving operations must be carried out to be able to resume later on. */ - hhash->State = HAL_HASH_STATE_SUSPENDED; + + /* Make sure there is enough time to suspend the processing */ + tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; + if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) + { + /* No suspension attempted since almost to the end of the transferred data. */ + /* Best option for user code is to wrap up low priority message hashing */ + return HAL_ERROR; + } + + /* Wait for DMAS to be reset */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) + { + return HAL_ERROR; + } + + /* Wait for DMAS to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } /* Disable DMA channel */ HAL_DMA_Abort(hhash->hdmain); @@ -1093,6 +1122,16 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Clear DMAE bit */ CLEAR_BIT(HASH->CR,HASH_CR_DMAE); + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) + { + return HAL_ERROR; + } + /* At this point, DMA interface is disabled and no transfer is on-going */ /* Retrieve from the DMA handle how many words remain to be written */ tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; @@ -1108,7 +1147,6 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) priority block processing (HASH case) - re-attempt a new suspension (HMAC case) */ - hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } else @@ -1126,6 +1164,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } + /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */ hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; @@ -1134,6 +1173,9 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) } + /* Set State as suspended */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + return HAL_OK; } @@ -2250,6 +2292,7 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, processing was suspended */ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */ + } /* Set the HASH DMA transfert complete callback */ @@ -2668,7 +2711,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h index 17682fa6af9..be9bb69822a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -570,7 +568,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c index ffa5eecfca7..0b5fe23b97c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral for SHA-224 and SHA-256 @@ -99,7 +97,7 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -927,7 +925,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h index 3e930ed5ac0..8a0011e62c7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -170,7 +168,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c index e909779e375..8409955e3bd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -73,7 +71,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -207,7 +206,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_num = epnum & 0x7F; hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); hhcd->hc[ch_num].speed = speed; - /* reset to 0 */ + + // Added for MBED PR #3432 + /* reset to 0 */ hhcd->hc[ch_num].toggle_out = 0; hhcd->hc[ch_num].toggle_in = 0; @@ -347,6 +348,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint16_t length, uint8_t do_ping) { + // Added for MBED PR #3432 if ((hhcd->hc[ch_num].ep_is_in != direction)) { if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){ /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */ @@ -402,6 +404,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].do_ping = do_ping; } } + // Added for MBED PR #3432 else if ((token == 1) && (direction == 1)) { if( hhcd->hc[ch_num].toggle_in == 0) @@ -911,6 +914,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) { + // Added for MBED PR #3432 int reactivate = 0; __HAL_HCD_MASK_HALT_HC_INT(chnum); @@ -940,6 +944,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + // Added for MBED PR #3432 #4231 if ( hhcd->hc[chnum].urb_state != URB_ERROR) { tmpreg |= USB_OTG_HCCHAR_CHENA; reactivate = 1; @@ -947,6 +952,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) USBx_HC(chnum)->HCCHAR = tmpreg; } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + // Added for MBED PR #3432 #4231 if (hhcd->hc[chnum].state == 0) reactivate = 1; if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); } @@ -1279,6 +1285,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) */ #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h index 2c347361266..d79b1e531e7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" @@ -252,7 +251,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); */ #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c index 7b6fb65d988..f926f76d795 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -238,7 +236,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -303,8 +301,8 @@ /* Private macro -------------------------------------------------------------*/ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ + ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -366,7 +364,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -406,7 +404,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - if(hi2c->State == HAL_I2C_STATE_RESET) + if (hi2c->State == HAL_I2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; @@ -444,7 +442,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); } @@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { hi2c->Instance->CR2 = (I2C_CR2_ADD10); } @@ -493,7 +491,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -557,7 +555,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * @verbatim =============================================================================== @@ -569,7 +567,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function + The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. @@ -630,7 +628,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -638,7 +636,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -646,7 +644,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -654,7 +652,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -665,12 +663,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -684,15 +682,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -707,9 +705,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -754,7 +752,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -762,7 +760,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -789,12 +787,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -809,15 +807,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -832,9 +830,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -865,7 +863,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /** - * @brief Transmits in slave mode an amount of data in blocking mode. + * @brief Transmits in slave mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -877,9 +875,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -902,7 +900,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -910,13 +908,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -924,26 +922,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -959,12 +957,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Normal use case for Transmitter mode */ /* A NACK is generated to confirm the end of transfer */ @@ -977,10 +975,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1017,9 +1015,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1042,7 +1040,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1050,33 +1048,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferCount--; } - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; } @@ -1092,12 +1090,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1108,10 +1106,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1149,9 +1147,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1168,8 +1166,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1185,7 +1183,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current @@ -1218,9 +1216,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1237,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1252,7 +1250,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1283,7 +1281,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1323,7 +1321,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -1332,7 +1330,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1385,9 +1383,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1404,8 +1402,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1416,7 +1414,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; @@ -1454,7 +1452,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); @@ -1493,9 +1491,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1512,8 +1510,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1524,7 +1522,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; @@ -1541,7 +1539,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1562,7 +1560,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); @@ -1596,12 +1594,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1642,7 +1640,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; return HAL_OK; } @@ -1662,9 +1660,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1737,9 +1735,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1750,7 +1748,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1765,9 +1763,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1782,7 +1780,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1796,9 +1794,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1813,15 +1811,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1833,13 +1831,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1889,9 +1888,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1902,7 +1901,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1917,9 +1916,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1935,7 +1934,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -1949,7 +1948,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, do { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1959,15 +1958,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1978,13 +1977,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -2033,14 +2033,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2060,8 +2060,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2073,9 +2073,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2090,12 +2090,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -2132,14 +2132,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2159,8 +2159,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2172,9 +2172,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2230,14 +2230,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2257,8 +2257,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2270,9 +2270,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2346,14 +2346,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2374,7 +2374,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2386,9 +2386,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2416,7 +2416,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2458,9 +2458,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2474,16 +2474,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2491,14 +2491,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } - } + } } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2517,7 +2517,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2535,8 +2535,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - }while(I2C_Trials < Trials); + } + while (I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; @@ -2579,7 +2580,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2591,11 +2592,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + // Added for MBED PR #3324 hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); hi2c->XferISR = I2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2606,6 +2608,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } + /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2645,7 +2654,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2657,11 +2666,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + // Added for MBED PR #3324 hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2672,8 +2682,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2706,9 +2723,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2718,10 +2735,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); @@ -2741,11 +2758,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2780,9 +2797,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2792,15 +2809,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); } - + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2815,11 +2832,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2847,7 +2864,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -2875,7 +2892,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); @@ -2904,7 +2921,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if(hi2c->Mode == HAL_I2C_MODE_MASTER) + if (hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2923,7 +2940,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -2944,7 +2961,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief This function handles I2C event interrupt request. @@ -2959,7 +2976,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) + if (hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } @@ -2977,7 +2994,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -2986,7 +3003,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -2995,7 +3012,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -3004,7 +3021,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -3077,8 +3094,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -3228,7 +3245,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @} - */ + */ /** * @} @@ -3246,14 +3263,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3266,27 +3283,27 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -3294,7 +3311,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { hi2c->XferSize = hi2c->XferCount; - if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } @@ -3307,7 +3324,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call TxCpltCallback() if no stop mode is set */ - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSequentialCplt(hi2c); @@ -3320,14 +3337,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ - if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -3347,7 +3364,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3367,26 +3384,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3414,9 +3431,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; @@ -3424,24 +3441,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->XferCount--; } - if((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); - } + } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3450,7 +3467,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } else { - if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ @@ -3460,7 +3477,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3480,7 +3497,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; uint32_t xfermode = 0U; @@ -3488,14 +3505,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3504,18 +3521,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if(hi2c->XferCount != 0U) + + if (hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -3533,7 +3550,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui hi2c->XferCount -= hi2c->XferSize; /* Enable DMA Request */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } @@ -3549,7 +3566,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3569,18 +3586,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3590,17 +3607,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3626,12 +3643,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3642,7 +3659,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3654,9 +3671,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3665,18 +3682,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } -return HAL_OK; + return HAL_OK; } /** @@ -3693,12 +3710,12 @@ return HAL_OK; */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3709,7 +3726,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3721,9 +3738,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3732,17 +3749,17 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -3763,7 +3780,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -3771,19 +3788,19 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2U) + if (hi2c->AddrEventCount == 2U) { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3885,7 +3902,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3901,7 +3918,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) HAL_I2C_SlaveTxCpltCallback(hi2c); } - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3937,7 +3954,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if((ITFlags & I2C_FLAG_AF) != RESET) + if ((ITFlags & I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3950,16 +3967,16 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Call the corresponding callback to inform upper layer of End of Transfer */ - if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; @@ -3985,7 +4002,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4022,7 +4039,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); @@ -4037,26 +4054,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); } /* All data are not transferred, so set error code accordingly */ - if(hi2c->XferCount != 0U) + if (hi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4070,19 +4087,19 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } } - else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; @@ -4094,7 +4111,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) HAL_I2C_ListenCpltCallback(hi2c); } /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4132,12 +4149,12 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4177,9 +4194,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -4193,10 +4210,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ - if(hi2c->State != HAL_I2C_STATE_ABORT) + if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; @@ -4206,7 +4223,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } /* Abort DMA TX transfer if any */ - if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4218,14 +4235,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } /* Abort DMA RX transfer if any */ - else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -4237,16 +4254,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } - else if(hi2c->State == HAL_I2C_STATE_ABORT) + else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4272,13 +4289,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { - hi2c->Instance->TXDR = 0x00U; + hi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); } @@ -4291,13 +4308,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4309,7 +4326,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4348,13 +4365,13 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4366,7 +4383,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4405,7 +4422,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4417,12 +4434,12 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4432,10 +4449,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ - if(hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); } @@ -4458,14 +4475,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4487,21 +4504,21 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4524,19 +4541,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4558,38 +4575,49 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4610,18 +4638,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4644,7 +4672,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4676,25 +4704,14 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -4708,28 +4725,28 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr { uint32_t tmpisr = 0U; - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -4737,31 +4754,31 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr } else { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } } - + /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ @@ -4781,49 +4798,49 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter { uint32_t tmpisr = 0U; - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h index 93bbd5eaf37..7a8f85f292c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32L4xx_HAL_I2C_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" +#include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -52,7 +50,7 @@ /** @addtogroup I2C * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types @@ -60,13 +58,13 @@ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition + * @brief I2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization + This parameter calculated by referring to I2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. @@ -90,9 +88,9 @@ typedef struct uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ -}I2C_InitTypeDef; +} I2C_InitTypeDef; -/** +/** * @} */ @@ -122,7 +120,7 @@ typedef struct * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ - */ + */ typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ @@ -139,7 +137,7 @@ typedef enum HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -}HAL_I2C_StateTypeDef; +} HAL_I2C_StateTypeDef; /** * @} @@ -170,9 +168,9 @@ typedef enum HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -}HAL_I2C_ModeTypeDef; +} HAL_I2C_ModeTypeDef; -/** +/** * @} */ @@ -213,7 +211,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -228,7 +226,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -}I2C_HandleTypeDef; +} I2C_HandleTypeDef; /** * @} */ @@ -313,7 +311,7 @@ typedef struct __I2C_HandleTypeDef /** * @} */ - + /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ @@ -337,9 +335,9 @@ typedef struct __I2C_HandleTypeDef * @{ */ #define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -431,7 +429,7 @@ typedef struct __I2C_HandleTypeDef * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified I2C interrupt source is enabled or not. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the I2C interrupt source to check. @@ -506,7 +504,7 @@ typedef struct __I2C_HandleTypeDef #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) @@ -527,7 +525,7 @@ typedef struct __I2C_HandleTypeDef */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** @@ -538,7 +536,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); * @{ */ /* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -547,7 +545,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - /******* Non-Blocking mode: Interrupt */ +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -563,7 +561,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - /******* Non-Blocking mode: DMA */ +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -604,11 +602,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants @@ -617,7 +615,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros @@ -681,7 +679,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions @@ -690,15 +688,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /* Private functions are defined in stm32l4xx_hal_i2c.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c index 2602734c8dd..bd4e329dd21 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c @@ -2,10 +2,8 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions * @@ -19,7 +17,8 @@ (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop modes + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== @@ -96,8 +95,9 @@ ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters + (+) Configure Noise Filters (+) Configure Wake Up Feature + (+) Configure Fast Mode Plus @endverbatim * @{ @@ -116,7 +116,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -162,7 +162,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -200,17 +200,17 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ } /** - * @brief Enable I2C wakeup from stop mode. + * @brief Enable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -239,17 +239,17 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) } /** - * @brief Disable I2C wakeup from stop mode. + * @brief Disable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -262,7 +262,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) /* Enable wakeup from stop mode */ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - __HAL_I2C_ENABLE(hi2c); + __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h index e6d115a1bab..726a83fba8a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #define __STM32L4xx_HAL_I2C_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,7 +50,7 @@ /** @addtogroup I2CEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -101,7 +99,7 @@ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -152,7 +150,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c index 99d40492983..ecefca38d5d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_irda.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -158,14 +156,41 @@ * @{ */ #define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ + #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ /* Private macros ------------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ IRDA clock source. + * @param __BAUD__ Baud rate set by the user. + * @param __PRESCALER__ IRDA clock prescaler value. + * @retval Division result + */ +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) +#else +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ IRDA clock source. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) +#endif + /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +static const uint16_t IRDAPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; +#else +#endif + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup IRDA_Private_Functions * @{ @@ -186,7 +211,7 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @} @@ -248,9 +273,9 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); */ /** - * @brief Initialize the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Initialize the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and initialize the associated handle. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -302,8 +327,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) } /** - * @brief DeInitialize the IRDA peripheral. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DeInitialize the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -336,8 +361,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) } /** - * @brief Initialize the IRDA MSP. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Initialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -352,8 +377,8 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) } /** - * @brief DeInitialize the IRDA MSP. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DeInitialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -376,7 +401,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) * @verbatim =============================================================================== - ##### IO operation functions ##### + ##### IO operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the IRDA data transfers. @@ -388,7 +413,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: the communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. @@ -453,11 +478,11 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) */ /** - * @brief Send an amount of data in blocking mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Send an amount of data in blocking mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -525,11 +550,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u } /** - * @brief Receive an amount of data in blocking mode. + * @brief Receive an amount of data in blocking mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -600,11 +625,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui } /** - * @brief Send an amount of data in interrupt mode. + * @brief Send an amount of data in interrupt mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -631,8 +656,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData __HAL_UNLOCK(hirda); /* Enable the IRDA Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); - +#endif + return HAL_OK; } else @@ -642,11 +671,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData } /** - * @brief Receive an amount of data in interrupt mode. + * @brief Receive an amount of data in interrupt mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -677,7 +706,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, __HAL_UNLOCK(hirda); /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); +#else SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); +#endif /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -691,11 +724,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, } /** - * @brief Send an amount of data in DMA mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Send an amount of data in DMA mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -752,11 +785,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat } /** - * @brief Receive an amount of data in DMA mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Receive an amount of data in DMA mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @note When the IRDA parity is enabled (PCE = 1), the received data contains * the parity bit (MSB position). * @retval HAL status @@ -818,9 +851,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /** - * @brief Pause the DMA Transfer. + * @brief Pause the DMA Transfer. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) @@ -852,9 +885,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) } /** - * @brief Resume the DMA Transfer. + * @brief Resume the DMA Transfer. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) @@ -887,9 +920,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) } /** - * @brief Stop the DMA Transfer. + * @brief Stop the DMA Transfer. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) @@ -950,7 +983,11 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -1018,7 +1055,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) @@ -1061,7 +1102,11 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Rx request if enabled */ @@ -1112,7 +1157,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) uint32_t abortcplt = 1; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised @@ -1236,7 +1285,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) @@ -1302,7 +1355,11 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Rx request if enabled */ @@ -1358,8 +1415,8 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) } /** - * @brief Handle IRDA interrupt request. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Handle IRDA interrupt request. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1375,7 +1432,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) if (errorflags == RESET) { /* IRDA in mode Receiver ---------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) +#else if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { IRDA_Receive_IT(hirda); return; @@ -1386,7 +1447,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) cr3its = READ_REG(hirda->Instance->CR3); if( (errorflags != RESET) && ( ((cr3its & USART_CR3_EIE) != RESET) +#if defined(USART_CR1_FIFOEN) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)) ) +#else || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +#endif { /* IRDA parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) @@ -1414,7 +1479,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA Over-Run interrupt occurred -----------------------------------------*/ if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#else + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#endif { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); @@ -1425,7 +1494,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) { /* IRDA in mode Receiver ---------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) +#else if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { IRDA_Receive_IT(hirda); } @@ -1484,7 +1557,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* End if some error occurs */ /* IRDA in mode Transmitter ------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET)) +#else if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { IRDA_Transmit_IT(hirda); return; @@ -1549,7 +1626,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1651,9 +1728,9 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) */ /** - * @brief Return the IRDA handle state. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @brief Return the IRDA handle state. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL state */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) @@ -1667,8 +1744,8 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) } /** - * @brief Return the IRDA handle error code. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Return the IRDA handle error code. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ @@ -1690,8 +1767,8 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) */ /** - * @brief Configure the IRDA peripheral. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Configure the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1708,6 +1785,9 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler)); +#endif /*-------------------------- USART CR1 Configuration -----------------------*/ /* Configure the IRDA Word Length, Parity and transfer Mode: @@ -1721,27 +1801,55 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /*-------------------------- USART CR3 Configuration -----------------------*/ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); +#if defined(USART_PRESC_PRESCALER) + /*--------------------- USART clock PRESC Configuration ----------------*/ + /* Configure + * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */ + MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); +#endif + /*-------------------------- USART GTPR Configuration ----------------------*/ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); + tmpreg = 0; switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_PCLK2: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_UNDEFINED: default: @@ -1749,12 +1857,22 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) break; } + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hirda->Instance->BRR = tmpreg; + } + else + { + ret = HAL_ERROR; + } + return ret; } /** - * @brief Check the IRDA Idle State. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Check the IRDA Idle State. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1820,7 +1938,11 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); hirda->gState = HAL_IRDA_STATE_READY; @@ -1845,7 +1967,11 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* At end of Tx process, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; @@ -1861,7 +1987,11 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore hirda->RxState to Ready */ @@ -1914,7 +2044,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1944,7 +2074,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1956,8 +2086,8 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA IRDA communication error callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA IRDA communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2147,7 +2277,11 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if(hirda->TxXferCount == 0) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); +#endif /* Enable the IRDA Transmit Complete Interrupt */ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); @@ -2181,9 +2315,9 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) * @brief Wrap up transmission in non-blocking mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable the IRDA Transmit Complete Interrupt */ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); @@ -2192,8 +2326,6 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) hirda->gState = HAL_IRDA_STATE_READY; HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; } /** @@ -2228,7 +2360,11 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) if(--hirda->RxXferCount == 0) { /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h index 4fced53ab0d..148d4e78d6a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_irda.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -66,7 +64,8 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */ + Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) + where usart_ker_ckpres is the IRDA input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref IRDA_Word_Length */ @@ -87,6 +86,12 @@ typedef struct uint16_t PowerMode; /*!< Specifies the IRDA power mode. This parameter can be a value of @ref IRDA_Low_Power */ + +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source. + This parameter can be a value of @ref IRDA_ClockPrescaler. */ +#endif + }IRDA_InitTypeDef; /** @@ -154,13 +159,13 @@ typedef enum */ typedef enum { - HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_IRDA_ERROR_BUSY = 0x20 /*!< Busy Error */ + HAL_IRDA_ERROR_NONE = 0x00U, /*!< No error */ + HAL_IRDA_ERROR_PE = 0x01U, /*!< Parity error */ + HAL_IRDA_ERROR_NE = 0x02U, /*!< Noise error */ + HAL_IRDA_ERROR_FE = 0x04U, /*!< frame error */ + HAL_IRDA_ERROR_ORE = 0x08U, /*!< Overrun error */ + HAL_IRDA_ERROR_DMA = 0x10U, /*!< DMA transfer error */ + HAL_IRDA_ERROR_BUSY = 0x20U /*!< Busy Error */ }HAL_IRDA_ErrorTypeDef; /** @@ -168,12 +173,12 @@ typedef enum */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }IRDA_ClockSourceTypeDef; /** @@ -181,7 +186,7 @@ typedef enum */ typedef struct { - USART_TypeDef *Instance; /*!< IRDA registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ @@ -189,7 +194,7 @@ typedef struct uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - __IO uint16_t TxXferCount; /* !Instance->ICR = (__FLAG__)) /** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) /** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) /** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) /** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) /** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) /** @brief Check whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag @@ -493,8 +537,8 @@ typedef enum /** @brief Enable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -509,8 +553,8 @@ typedef enum ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -526,8 +570,8 @@ typedef enum /** @brief Check whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -537,13 +581,13 @@ typedef enum * @arg @ref IRDA_IT_NE Noise Error interrupt * @arg @ref IRDA_IT_FE Framing Error interrupt * @arg @ref IRDA_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -551,15 +595,15 @@ typedef enum * @arg @ref IRDA_IT_IDLE Idle line detection interrupt * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt * @arg @ref IRDA_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) - +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag @@ -573,8 +617,8 @@ typedef enum /** @brief Set a specific IRDA request flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request @@ -585,25 +629,25 @@ typedef enum #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None - */ + */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None - */ + */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -619,7 +663,7 @@ typedef enum /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. */ #define IRDA_MASK_COMPUTATION(__HANDLE__) \ @@ -660,20 +704,20 @@ typedef enum } while(0) /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. - * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) /** * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__: IRDA frame length. + * @param __LENGTH__ IRDA frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ @@ -682,7 +726,7 @@ typedef enum /** * @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__: IRDA frame parity. + * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ @@ -691,22 +735,42 @@ typedef enum /** * @brief Ensure that IRDA communication mode is valid. - * @param __MODE__: IRDA communication mode. + * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) /** * @brief Ensure that IRDA power mode is valid. - * @param __MODE__: IRDA power mode. + * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ ((__MODE__) == IRDA_POWERMODE_NORMAL)) +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Ensure that IRDA clock Prescaler is valid. + * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) +#endif + /** * @brief Ensure that IRDA state is valid. - * @param __STATE__: IRDA state mode. + * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ @@ -722,7 +786,7 @@ typedef enum /** * @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__: IRDA sampling rate. + * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ @@ -730,7 +794,7 @@ typedef enum /** * @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__: IRDA DMA TX mode. + * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ @@ -738,7 +802,7 @@ typedef enum /** * @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__: IRDA DMA RX mode. + * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ @@ -746,7 +810,7 @@ typedef enum /** * @brief Ensure that IRDA request is valid. - * @param __PARAM__: IRDA request. + * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h index 5a193565772..487795de3d0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IRDA HAL Extended module. ****************************************************************************** * @attention @@ -66,11 +64,13 @@ */ /** @brief Report the IRDA clock source. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c index 9917a4f678b..e5080c41b1e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h index bead6ad7a7c..b11dc2119f9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c index 0bd57fdbcda..9c6bdc857f7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LCD Controller HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LCD Controller (LCD) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h index dc7f4bf57b9..754cf5615ab 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LCD Controller HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c index 362dfa5fe00..01b100fb109 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LPTIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h index d5426a7b688..ee1a6b3d65c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c new file mode 100644 index 00000000000..885043f72ae --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c @@ -0,0 +1,1896 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc.c + * @author MCD Application Team + * @brief LTDC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LTDC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Program the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, + the pixel clock polarity, Data Enable polarity and the LTDC background color value + using HAL_LTDC_Init() function + + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size + and the image size using HAL_LTDC_ConfigLayer() function for foreground + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + HAL_LTDC_EnableCLUT functions. + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() + and HAL_LTDC_EnableColorKeying functions. + + (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() + function + + (#) If needed, reconfigure and change the pixel format value, the alpha value + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following + functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), + HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). + + (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). + + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + an immediate reload is required. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if + the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + *** LTDC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in LTDC HAL driver. + + (+) __HAL_LTDC_ENABLE: Enable the LTDC. + (+) __HAL_LTDC_DISABLE: Disable the LTDC. + (+) __HAL_LTDC_LAYER_ENABLE: Enable a LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable a LTDC Layer. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + + [..] + (@) You can refer to the LTDC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp = 0, tmp1 = 0; + + /* Check the LTDC peripheral state */ + if(hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + + if(hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + uint32_t itsources = READ_REG(hltdc->Instance->IER); + + /* Transfer Error Interrupt management ***************************************/ + if(((isrflags & LTDC_ISR_TERRIF) != RESET) && ((itsources & LTDC_IER_TERRIE) != RESET)) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ + HAL_LTDC_ErrorCallback(hltdc); + } + + /* FIFO underrun Interrupt management ***************************************/ + if(((isrflags & LTDC_ISR_FUIF) != RESET) && ((itsources & LTDC_IER_FUIE) != RESET)) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ + HAL_LTDC_ErrorCallback(hltdc); + } + + /* Line Interrupt management ************************************************/ + if(((isrflags & LTDC_ISR_LIF) != RESET) && ((itsources & LTDC_IER_LIE) != RESET)) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ + HAL_LTDC_LineEventCallback(hltdc); + } + + /* Register reload Interrupt management ***************************************/ + if(((isrflags & LTDC_ISR_RRIF) != RESET) && ((itsources & LTDC_IER_RRIE) != RESET)) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Register reload interrupt Callback */ + HAL_LTDC_ReloadEventCallback(hltdc); + } +} + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t counter = 0; + uint32_t pcounter = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for(counter = 0; (counter < CLUTSize); counter++) + { + if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + } + else + { + tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + } + pcounter = (uint32_t)pCLUT + sizeof(*pCLUT); + pCLUT = (uint32_t *)pcounter; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. +* @retval LTDC Error Code +*/ +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @brief Configure the LTDC peripheral + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16); + tmp2 = (pLayerCfg->Alpha0 << 24); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + + if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3)); + + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4S7xx || STM32L4S9xx */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h new file mode 100644 index 00000000000..b5f308980a4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc.h + * @author MCD Application Team + * @brief Header file of LTDC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_LTDC_H +#define __STM32L4xx_HAL_LTDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State structures definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +}HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +typedef struct +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +} LTDC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 ((uint32_t)0x00000000U) /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 ((uint32_t)0x00000001U) /*!< LTDC Layer 2 */ +/** + * @} + */ + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ +#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ +#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ +#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ +#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ +#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ +#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) + +/** + * @brief Enable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Specify the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + +/* Include LTDC HAL Extension module */ +#include "stm32l4xx_hal_ltdc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4R7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_LTDC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c new file mode 100644 index 00000000000..bc0eab10fec --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc_ex.c + * @author MCD Application Team + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#if defined (STM32L4R9xx) || defined (STM32L4S9xx) + +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* STM32L4R9xx || STM32L4S9xx */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h new file mode 100644 index 00000000000..ff827cb2f9b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h @@ -0,0 +1,101 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc_ex.h + * @author MCD Application Team + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_LTDC_EX_H +#define __STM32L4xx_HAL_LTDC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L4R9xx) || defined (STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" +#include "stm32l4xx_hal_dsi.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDCEx_Exported_Functions + * @{ + */ + +/** @addtogroup LTDCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R9xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_LTDC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c index bce42d5748b..d66dda6cefd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nand.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -86,7 +84,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1128,5 +1127,6 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h index f0395451e1e..1292ae8727e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nand.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -297,6 +296,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c index 1ab593b1705..585ffaa0ef0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nor.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -86,7 +84,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1063,5 +1062,6 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h index 9749c3a068b..d302ee479d6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nor.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -293,6 +292,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c index 330f51901ad..3aa42edc218 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief OPAMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the operational amplifier(s) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h index 0a664ccdd75..a9dca5c23e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of OPAMP HAL module. ****************************************************************************** * @attention @@ -300,29 +298,40 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; ((INPUT) == OPAMP_PGA_MODE) || \ ((INPUT) == OPAMP_FOLLOWER_MODE)) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) - +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_INVERTINGINPUT_IO1)) -#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ +#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH)) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ - ((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \ + ((INPUT) == OPAMP_INVERTINGINPUT_IO1) || \ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO)) -#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ +#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO)) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \ ((GAIN) == OPAMP_PGA_GAIN_4) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c index 1c5d0bff6e4..8a0f250e93f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended OPAMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) @@ -68,7 +66,8 @@ */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup OPAMPEx_Exported_Functions_Group1 * @brief Extended operation functions diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h index 904fb4fa6fa..ac507d88793 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of OPAMP HAL Extended module. ****************************************************************************** * @attention @@ -62,7 +60,9 @@ */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + /* I/O operation functions *****************************************************/ /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c new file mode 100644 index 00000000000..5c87b74618c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c @@ -0,0 +1,2564 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ospi.c + * @author MCD Application Team + * @brief OSPI HAL module driver. + This file provides firmware functions to manage the following + functionalities of the OctoSPI interface (OSPI). + + Initialization and de-initialization functions + + Hyperbus configuration + + Indirect functional mode management + + Memory-mapped functional mode management + + Auto-polling functional mode management + + Interrupts and flags management + + DMA channel configuration for indirect functional mode + + Errors management and abort functionality + + IO manager configuration + + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_OSPI_MspInit() : + (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE(). + (++) Reset OctoSPI IP with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). + (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). + (++) If interrupt or DMA mode is used, enable and configure OctoSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure + DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the fifo threshold, the dual-quad mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay + and the CS boundary using the HAL_OSPI_Init() function. + (#) When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + function. + + *** Indirect functional mode *** + ================================ + [..] + (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() + or HAL_OSPI_Command_IT() functions : + (++) Instruction phase : the mode used and if present the size, the instruction + opcode and the DTR mode. + (++) Address phase : the mode used and if present the size, the address + value and the DTR mode. + (++) Alternate-bytes phase : the mode used and if present the size, the + alternate bytes values and the DTR mode. + (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (++) Data phase : the mode used and if present the number of bytes and the DTR mode. + (++) Data strobe (DQS) mode : the activation (or not) of this mode + (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (++) Flash identifier : in dual-quad mode, indicates which flash is concerned + (++) Operation type : always common configuration + (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() + function : + (++) Address space : indicate if the access will be done in register or memory + (++) Address size + (++) Number of data + (++) Data strobe (DQS) mode : the activation (or not) of this mode + (#) If no data is required for the command (only for regular mode, not for + Hyperbus mode), it is sent directly to the memory : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. + (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or + HAL_OSPI_Transmit_IT() after the command configuration : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and + HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. + (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or + HAL_OSPI_Receive_IT() after the command configuration : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and + HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. + + *** Auto-polling functional mode *** + ==================================== + [..] + (#) Configure the command sequence by the same way than the indirect mode + (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() + or HAL_OSPI_AutoPolling_IT() functions : + (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + (#) After the configuration : + (++) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached. + + *** Memory-mapped functional mode *** + ===================================== + [..] + (#) Configure the command sequence by the same way than the indirect mode except + for the operation type in regular mode : + (++) Operation type equals to read configuration : the command configuration + applies to read access in memory-mapped mode + (++) Operation type equals to write configuration : the command configuration + applies to write access in memory-mapped mode + (++) Both read and write configuration should be performed before activating + memory-mapped mode + (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() + functions : + (++) The timeout activation and the timeout period. + (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on + the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. + + *** Errors management and abort functionality *** + ================================================= + [..] + (#) HAL_OSPI_GetError() function gives the error raised during the last operation. + (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (++) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. + + *** Control functions *** + ========================= + [..] + (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. + (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. + (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI IP. + (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + + *** IO manager configuration functions *** + ========================================== + [..] + (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup OSPI OSPI + * @brief OSPI HAL module driver + * @{ + */ + +#ifdef HAL_OSPI_MODULE_ENABLED + +/** + @cond 0 + */ +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +#define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */ +#define OSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)OCTOSPI_CR_FMODE_0) /*!< Indirect read mode */ +#define OSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)OCTOSPI_CR_FMODE_1) /*!< Automatic polling mode */ +#define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)OCTOSPI_CR_FMODE) /*!< Memory-mapped mode */ + +#define OSPI_CFG_STATE_MASK 0x00000004U +#define OSPI_BUSY_STATE_MASK 0x00000008U + +#define OSPI_NB_INSTANCE 2 +#define OSPI_IOM_NB_PORTS 2 + +/* Private macro -------------------------------------------------------------*/ +#define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ + ((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \ + ((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \ + ((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +static void OSPI_DMACplt (DMA_HandleTypeDef *hdma); +static void OSPI_DMAHalfCplt (DMA_HandleTypeDef *hdma); +static void OSPI_DMAError (DMA_HandleTypeDef *hdma); +static void OSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup OSPI_Exported_Functions OSPI Exported Functions + * @{ + */ + +/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Initialize the OctoSPI. + (+) De-initialize the OctoSPI. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the OSPI mode according to the specified parameters + * in the OSPI_InitTypeDef and initialize the associated handle. + * @param hospi : OSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Check the parameters of the initialization structure */ + assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold)); + assert_param(IS_OSPI_DUALQUAD_MODE (hospi->Init.DualQuad)); + assert_param(IS_OSPI_MEMORY_TYPE (hospi->Init.MemoryType)); + assert_param(IS_OSPI_DEVICE_SIZE (hospi->Init.DeviceSize)); + assert_param(IS_OSPI_CS_HIGH_TIME (hospi->Init.ChipSelectHighTime)); + assert_param(IS_OSPI_FREE_RUN_CLK (hospi->Init.FreeRunningClock)); + assert_param(IS_OSPI_CLOCK_MODE (hospi->Init.ClockMode)); + assert_param(IS_OSPI_WRAP_SIZE (hospi->Init.WrapSize)); + assert_param(IS_OSPI_CLK_PRESCALER (hospi->Init.ClockPrescaler)); + assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting)); + assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle)); + assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary)); + + /* Initialize error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_NONE; + + /* Check if the state is the reset state */ + if (hospi->State == HAL_OSPI_STATE_RESET) + { + /* Initialization of the low level hardware */ + HAL_OSPI_MspInit(hospi); + + /* Configure the default timeout for the OSPI memory access */ + status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); + } + + if (status == HAL_OK) + { + /* Configure memory type, device size, chip select high time, free running clock, clock mode */ + MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), + (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1) << OCTOSPI_DCR1_DEVSIZE_Pos) | + ((hospi->Init.ChipSelectHighTime - 1) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.FreeRunningClock | + hospi->Init.ClockMode)); + + /* Configure wrap size */ + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); + + /* Configure chip select boundary */ + hospi->Instance->DCR3 = (hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos); + + + /* Configure FIFO threshold */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1) << OCTOSPI_CR_FTHRES_Pos)); + + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Configure clock prescaler */ + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1) << OCTOSPI_DCR2_PRESCALER_Pos)); + + /* Configure Dual Quad mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); + + /* Configure sample shifting and delay hold quarter cycle */ + MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); + + /* Enable OctoSPI */ + __HAL_OSPI_ENABLE(hospi); + + /* Initialize the OSPI state */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT; + } + else + { + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Initialize the OSPI MSP. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_MspInit can be implemented in the user file + */ +} + +/** + * @brief De-Initialize the OSPI peripheral. + * @param hospi : OSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Disable OctoSPI */ + __HAL_OSPI_DISABLE(hospi); + + /* De-initialize the low-level hardware */ + HAL_OSPI_MspDeInit(hospi); + + /* Reset the driver state */ + hospi->State = HAL_OSPI_STATE_RESET; + } + + return status; +} + +/** + * @brief DeInitialize the OSPI MSP. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief OSPI Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Handle the interrupts. + (+) Handle the command sequence (regular and Hyperbus). + (+) Handle the Hyperbus configuration. + (+) Transmit data in blocking, interrupt or DMA mode. + (+) Receive data in blocking, interrupt or DMA mode. + (+) Manage the auto-polling functional mode. + (+) Manage the memory-mapped functional mode. + +@endverbatim + * @{ + */ + +/** + * @brief Handle OSPI interrupt request. + * @param hospi : OSPI handle + * @retval None + */ +void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) +{ + __IO uint32_t *data_reg = &hospi->Instance->DR; + uint32_t flag = hospi->Instance->SR; + uint32_t itsource = hospi->Instance->CR; + uint32_t currentstate = hospi->State; + + /* OctoSPI fifo threshold interrupt occurred -------------------------------*/ + if (((flag & HAL_OSPI_FLAG_FT) != 0) && ((itsource & HAL_OSPI_IT_FT) != 0)) + { + if (currentstate == HAL_OSPI_STATE_BUSY_TX) + { + /* Write a data in the fifo */ + *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + hospi->XferCount--; + } + else if (currentstate == HAL_OSPI_STATE_BUSY_RX) + { + /* Read a data from the fifo */ + *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + hospi->XferCount--; + } + + if (hospi->XferCount == 0) + { + /* All data have been received or transmitted for the transfer */ + /* Disable fifo threshold interrupt */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT); + } + + /* Fifo threshold callback */ + HAL_OSPI_FifoThresholdCallback(hospi); + } + /* OctoSPI transfer complete interrupt occurred ----------------------------*/ + else if (((flag & HAL_OSPI_FLAG_TC) != 0) && ((itsource & HAL_OSPI_IT_TC) != 0)) + { + if (currentstate == HAL_OSPI_STATE_BUSY_RX) + { + if (((flag & OCTOSPI_SR_FLEVEL) != 0) && (hospi->XferCount > 0)) + { + /* Read the last data received in the fifo */ + *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void*)data_reg); + hospi->XferCount--; + } + else if(hospi->XferCount == 0) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TC; + + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* RX complete callback */ + HAL_OSPI_RxCpltCallback(hospi); + } + } + else + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TC; + + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + if (currentstate == HAL_OSPI_STATE_BUSY_TX) + { + /* TX complete callback */ + HAL_OSPI_TxCpltCallback(hospi); + } + else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) + { + /* Command complete callback */ + HAL_OSPI_CmdCpltCallback(hospi); + } + else if (currentstate == HAL_OSPI_STATE_ABORT) + { + if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE) + { + /* Abort called by the user */ + /* Abort complete callback */ + HAL_OSPI_AbortCpltCallback(hospi); + } + else + { + /* Abort due to an error (eg : DMA error) */ + /* Error callback */ + HAL_OSPI_ErrorCallback(hospi); + } + } + } + } + /* OctoSPI status match interrupt occurred ---------------------------------*/ + else if (((flag & HAL_OSPI_FLAG_SM) != 0) && ((itsource & HAL_OSPI_IT_SM) != 0)) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_SM; + + /* Check if automatic poll mode stop is activated */ + if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0) + { + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + + /* Status match callback */ + HAL_OSPI_StatusMatchCallback(hospi); + } + /* OctoSPI transfer error interrupt occurred -------------------------------*/ + else if (((flag & HAL_OSPI_FLAG_TE) != 0) && ((itsource & HAL_OSPI_IT_TE) != 0)) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TE; + + /* Disable all interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); + + /* Set error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER; + + /* Check if the DMA is enabled */ + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + { + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA transfer on the DMA side */ + hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; + HAL_DMA_Abort_IT(hospi->hdma); + } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ + HAL_OSPI_ErrorCallback(hospi); + } + } + /* OctoSPI timeout interrupt occurred --------------------------------------*/ + else if (((flag & HAL_OSPI_FLAG_TO) != 0) && ((itsource & HAL_OSPI_IT_TO) != 0)) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TO; + + /* Timeout callback */ + HAL_OSPI_TimeOutCallback(hospi); + } +} + +/** + * @brief Set the command configuration. + * @param hospi : OSPI handle + * @param cmd : structure that contains the command configuration information + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); + + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) + { + assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); + } + + assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) + { + assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); + assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); + } + + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize)); + assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode)); + } + + assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode)); + if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize)); + assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode)); + } + + assert_param(IS_OSPI_DATA_MODE(cmd->DataMode)); + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + { + assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData)); + } + assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode)); + assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles)); + } + + assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); + assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); + + /* Check the state of the driver */ + if (((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || + ((hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || + ((hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_NONE; + + /* Configure the registers */ + status = OSPI_ConfigCmd(hospi, cmd); + + if (status == HAL_OK) + { + if (cmd->DataMode == HAL_OSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so wait until TC flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); + + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + } + else + { + /* Update the state */ + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + { + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) + { + if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) + { + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + else + { + hospi->State = HAL_OSPI_STATE_READ_CMD_CFG; + } + } + else + { + if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) + { + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + else + { + hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG; + } + } + } + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Set the command configuration in interrupt mode. + * @param hospi : OSPI handle + * @param cmd : structure that contains the command configuration information + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); + + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) + { + assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); + } + + assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) + { + assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); + assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); + } + + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize)); + assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode)); + } + + assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode)); + if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize)); + assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode)); + } + + assert_param(IS_OSPI_DATA_MODE(cmd->DataMode)); + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData)); + assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode)); + assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles)); + } + + assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); + assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); + + /* Check the state of the driver */ + if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) && + (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_NONE; + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Configure the registers */ + status = OSPI_ConfigCmd(hospi, cmd); + + if (status == HAL_OK) + { + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_CMD; + + /* Enable the transfer complete and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE); + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the Hyperbus parameters. + * @param hospi : OSPI handle + * @param cfg : Structure containing the Hyperbus configuration + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus configuration structure */ + assert_param(IS_OSPI_RW_RECOVERY_TIME (cfg->RWRecoveryTime)); + assert_param(IS_OSPI_ACCESS_TIME (cfg->AccessTime)); + assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency)); + assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode)); + + /* Check the state of the driver */ + if ((hospi->State == HAL_OSPI_STATE_HYPERBUS_INIT) || (hospi->State == HAL_OSPI_STATE_READY)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure Hyperbus configuration Latency register */ + WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | + (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) | + cfg->WriteZeroLatency | cfg->LatencyMode)); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Set the Hyperbus command configuration. + * @param hospi : OSPI handle + * @param cmd : Structure containing the Hyperbus command + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus command structure */ + assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace)); + assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize)); + assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData)); + assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); + + /* Check the state of the driver */ + if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + + /* Configure the address space in the DCR1 register */ + MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace); + + /* Configure the CCR and WCCR registers with the address size and the following configuration : + - DQS signal enabled (used as RWDS) + - DTR mode enabled on address and data + - address and data on 8 lines */ + WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | + cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2)); + WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | + cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2)); + + /* Configure the DLR register with the number of data */ + WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1)); + + /* Configure the AR register with the address value */ + WRITE_REG(hospi->Instance->AR, cmd->Address); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hospi->Instance->DR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + do + { + /* Wait till fifo threshold flag is set to send data */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + hospi->XferCount--; + } while (hospi->XferCount > 0); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hospi->Instance->DR; + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + + do + { + /* Wait till fifo threshold or transfer complete flags are set to read received data */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + hospi->XferCount--; + } while(hospi->XferCount > 0); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_TX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_RX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp; + uint32_t data_size = hospi->Instance->DLR + 1; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + hospi->XferCount = data_size; + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) + { + if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 1); + } + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) + { + if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 2); + } + } + + if (status == HAL_OK) + { + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_TX; + + /* Set the DMA transfer complete callback */ + hospi->hdma->XferCpltCallback = OSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hospi->hdma->XferErrorCallback = OSPI_DMAError; + + /* Clear the DMA abort callback */ + hospi->hdma->XferAbortCallback = NULL; + + /* Configure the direction of the DMA */ + hospi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); + + /* Enable the transmit DMA Channel */ + tmp = (uint32_t*)((void*)&pData); + HAL_DMA_Start_IT(hospi->hdma, *(uint32_t*)tmp, (uint32_t)&hospi->Instance->DR, hospi->XferSize); + + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer. + * @note This function is used only in Indirect Read Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp; + uint32_t data_size = hospi->Instance->DLR + 1; + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + hospi->XferCount = data_size; + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) + { + if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 1); + } + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) + { + if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 2); + } + } + + if (status == HAL_OK) + { + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_RX; + + /* Set the DMA transfer complete callback */ + hospi->hdma->XferCpltCallback = OSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hospi->hdma->XferErrorCallback = OSPI_DMAError; + + /* Clear the DMA abort callback */ + hospi->hdma->XferAbortCallback = NULL; + + /* Configure the direction of the DMA */ + hospi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); + + /* Enable the transmit DMA Channel */ + tmp = (uint32_t*)((void *)&pData); + HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, *(uint32_t*)tmp, hospi->XferSize); + + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the OSPI Automatic Polling Mode in blocking mode. + * @param hospi : OSPI handle + * @param cfg : structure that contains the polling configuration information. + * @param Timeout : Timeout duration + * @note This function is used only in Automatic Polling Mode + * @note This function should not be used when the memory is in octal mode (see Errata Sheet) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); + assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); + assert_param(IS_OSPI_INTERVAL (cfg->Interval)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + + /* Check the state */ + if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG (hospi->Instance->PSMAR, cfg->Match); + WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); + WRITE_REG (hospi->Instance->PIR, cfg->Interval); + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + + /* Wait till status match flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear status match flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. + * @param hospi : OSPI handle + * @param cfg : structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @note This function should not be used when the memory is in octal mode (see Errata Sheet) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); + assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); + assert_param(IS_OSPI_INTERVAL (cfg->Interval)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG (hospi->Instance->PSMAR, cfg->Match); + WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); + WRITE_REG (hospi->Instance->PIR, cfg->Interval); + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING; + + /* Enable the status match and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the Memory Mapped mode. + * @param hospi : OSPI handle + * @param cfg : structure that contains the memory mapped configuration information. + * @note This function is used only in Memory mapped Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the memory-mapped configuration structure */ + assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); + + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED; + + if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE) + { + assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); + + /* Configure register */ + WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO); + + /* Enable the timeout interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO); + } + + /* Configure CR register with functional mode as memory-mapped */ + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), + (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Transfer Error callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief FIFO Threshold callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ + __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_StatusMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_TimeOutCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief OSPI control and State functions + * +@verbatim + =============================================================================== + ##### Peripheral Control and State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Check in run-time the state of the driver. + (+) Check the error code set during last operation. + (+) Abort any operation. + (+) Manage the Fifo threshold. + (+) Configure the timeout duration used in the driver. + +@endverbatim + * @{ + */ + +/** +* @brief Abort the current transmission. +* @param hospi : OSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is in one of the busy or configured states */ + if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + { + /* Check if the DMA is enabled */ + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + { + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA transfer on the DMA side */ + status = HAL_DMA_Abort(hospi->hdma); + if (status != HAL_OK) + { + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + } + } + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** +* @brief Abort the current transmission (non-blocking function) +* @param hospi : OSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the state is in one of the busy or configured states */ + if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + { + /* Disable all interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_ABORT; + + /* Check if the DMA is enabled */ + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + { + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA transfer on the DMA side */ + hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; + HAL_DMA_Abort_IT(hospi->hdma); + } + else + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** @brief Set OSPI Fifo threshold. + * @param hospi : OSPI handle. + * @param Threshold : Threshold of the Fifo. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the state */ + if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0) + { + /* Synchronize initialization structure with the new fifo threshold value */ + hospi->Init.FifoThreshold = Threshold; + + /* Configure new fifo threshold */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1) << OCTOSPI_CR_FTHRES_Pos)); + + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** @brief Get OSPI Fifo threshold. + * @param hospi : OSPI handle. + * @retval Fifo threshold + */ +uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi) +{ + return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1); +} + +/** @brief Set OSPI timeout. + * @param hospi : OSPI handle. + * @param Timeout : Timeout for the memory access. + * @retval None + */ +HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout) +{ + hospi->Timeout = Timeout; + return HAL_OK; +} + +/** +* @brief Return the OSPI error code. +* @param hospi : OSPI handle +* @retval OSPI Error Code +*/ +uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi) +{ + return hospi->ErrorCode; +} + +/** + * @brief Return the OSPI handle state. + * @param hospi : OSPI handle + * @retval HAL state + */ +uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) +{ + /* Return OSPI handle state */ + return hospi->State; +} + +/** + * @} + */ + +/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief OSPI IO Manager configuration function + * +@verbatim + =============================================================================== + ##### IO Manager configuration function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Configure the IO manager. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the OctoSPI IO manager. + * @param hospi : OSPI handle + * @param cfg : Configuration of the IO Manager for the instance + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t instance = 0; + uint8_t index = 0, ospi_enabled = 0, other_instance = 0; + OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; + + /* Check the parameters of the OctoSPI IO Manager configuration structure */ + assert_param(IS_OSPIM_PORT(cfg->ClkPort)); + assert_param(IS_OSPIM_PORT(cfg->DQSPort)); + assert_param(IS_OSPIM_PORT(cfg->NCSPort)); + assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); + assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); + + if (hospi->Instance == OCTOSPI1) + { + instance = 0; + other_instance = 1; + } + else + { + instance = 1; + other_instance = 0; + } + + /**************** Get current configuration of the instances ****************/ + for (index = 0; index < OSPI_NB_INSTANCE; index++) + { + if (OSPIM_GetConfig(index+1, &(IOM_cfg[index])) != HAL_OK) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + } + + if (status == HAL_OK) + { + /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/ + if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0) + { + CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); + ospi_enabled |= 0x1; + } + if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0) + { + CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); + ospi_enabled |= 0x2; + } + + /***************** Deactivation of previous configuration *****************/ + if (IOM_cfg[instance].ClkPort != 0) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + } + + /********************* Deactivation of other instance *********************/ + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || + (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + } + + /******************** Activation of new configuration *********************/ + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); + + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + } + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + } + + /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ + if ((ospi_enabled & 0x1) != 0) + { + SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); + } + if ((ospi_enabled & 0x2) != 0) + { + SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); + } + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** + @cond 0 + */ +/** + * @brief DMA OSPI process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = 0; + + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Enable the OSPI transfer complete Interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); +} + +/** + * @brief DMA OSPI process half complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = (hospi->XferCount >> 1); + + if (hospi->State == HAL_OSPI_STATE_BUSY_RX) + { + HAL_OSPI_RxHalfCpltCallback(hospi); + } + else + { + HAL_OSPI_TxHalfCpltCallback(hospi); + } +} + +/** + * @brief DMA OSPI communication error callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMAError(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = 0; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Abort the OctoSPI */ + HAL_OSPI_Abort_IT(hospi); +} + +/** + * @brief DMA OSPI abort complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = 0; + + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_ABORT) + { + /* DMA abort called by OctoSPI abort */ + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + else + { + /* DMA abort called due to a transfer error interrupt */ + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ + HAL_OSPI_ErrorCallback(hospi); + } +} + +/** + * @brief Wait for a flag state until timeout. + * @param hospi : OSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @param Tickstart : Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is in expected state */ + while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hospi->State = HAL_OSPI_STATE_ERROR; + hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the registers for the regular command mode. + * @param hospi : OSPI handle + * @param cmd : structure that contains the command configuration information + * @retval HAL status + */ +static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg; + + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + + /* Configure the flash ID */ + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) + { + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId); + } + + if (cmd->OperationType != HAL_OSPI_OPTYPE_WRITE_CFG) + { + ccr_reg = &(hospi->Instance->CCR); + tcr_reg = &(hospi->Instance->TCR); + ir_reg = &(hospi->Instance->IR); + abr_reg = &(hospi->Instance->ABR); + } + else + { + ccr_reg = &(hospi->Instance->WCCR); + tcr_reg = &(hospi->Instance->WTCR); + ir_reg = &(hospi->Instance->WIR); + abr_reg = &(hospi->Instance->WABR); + } + + /* Configure the CCR register with DQS and SIOO modes */ + *ccr_reg = (cmd->DQSMode | cmd->SIOOMode); + + if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) + { + /* Configure the ABR register with alternate bytes value */ + *abr_reg = cmd->AlternateBytes; + + /* Configure the CCR register with alternate bytes communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE), + (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize)); + } + + /* Configure the TCR register with the number of dummy cycles */ + MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles); + + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hospi->Instance->DLR = (cmd->NbData - 1); + } + } + + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) + { + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + /* ---- Command with instruction, address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | + OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | + OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | + cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | + cmd->DataMode | cmd->DataDtrMode)); + } + else + { + /* ---- Command with instruction and address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | + OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | + cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); + } + } + + /* Configure the IR register with the instruction value */ + *ir_reg = cmd->Instruction; + + /* Configure the AR register with the address value */ + hospi->Instance->AR = cmd->Address; + } + else + { + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + /* ---- Command with instruction and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | + OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | + cmd->DataMode | cmd->DataDtrMode)); + } + else + { + /* ---- Command with only instruction ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); + } + } + + /* Configure the IR register with the instruction value */ + *ir_reg = cmd->Instruction; + + } + } + else + { + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + /* ---- Command with address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | + OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), + (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | + cmd->DataMode | cmd->DataDtrMode)); + } + else + { + /* ---- Command with only address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), + (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); + } + + /* Configure the AR register with the instruction value */ + hospi->Instance->AR = cmd->Address; + } + else + { + /* ---- Invalid command configuration (no instruction, no address) ---- */ + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Get the current IOM configuration for an OctoSPI instance. + * @param instance_nb : number of the instance + * @param cfg : configuration of the IO Manager for the instance + * @retval HAL status + */ +static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t reg = 0, value = 0; + uint32_t index = 0; + + if ((instance_nb == 0) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) + { + /* Invalid parameter -> error returned */ + status = HAL_ERROR; + } + else + { + /* Initialize the structure */ + cfg->ClkPort = cfg->DQSPort = cfg->NCSPort = cfg->IOLowPort = cfg->IOHighPort = 0; + + if (instance_nb == 1) + { + value = 0; + } + else if (instance_nb == 2) + { + value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); + } + + /* Get the information about the instance */ + for (index = 0; index < OSPI_IOM_NB_PORTS; index ++) + { + reg = OCTOSPIM->PCR[index]; + + if ((reg & OCTOSPIM_PCR_CLKEN) != 0) + { + /* The clock is enabled on this port */ + if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) + { + /* The clock correspond to the instance passed as parameter */ + cfg->ClkPort = index+1; + } + } + + if ((reg & OCTOSPIM_PCR_DQSEN) != 0) + { + /* The DQS is enabled on this port */ + if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) + { + /* The DQS correspond to the instance passed as parameter */ + cfg->DQSPort = index+1; + } + } + + if ((reg & OCTOSPIM_PCR_NCSEN) != 0) + { + /* The nCS is enabled on this port */ + if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) + { + /* The nCS correspond to the instance passed as parameter */ + cfg->NCSPort = index+1; + } + } + + if ((reg & OCTOSPIM_PCR_IOLEN) != 0) + { + /* The IO Low is enabled on this port */ + if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) + { + /* The IO Low correspond to the instance passed as parameter */ + if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0) + { + cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + } + else + { + cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + } + } + } + + if ((reg & OCTOSPIM_PCR_IOHEN) != 0) + { + /* The IO High is enabled on this port */ + if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) + { + /* The IO High correspond to the instance passed as parameter */ + if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0) + { + cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + } + else + { + cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + } + } + } + } + } + + /* Return function status */ + return status; +} + +/** + @endcond + */ + +/** + * @} + */ + +#endif /* HAL_OSPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h new file mode 100644 index 00000000000..82eb12e4b2e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h @@ -0,0 +1,968 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ospi.h + * @author MCD Application Team + * @brief Header file of OSPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_OSPI_H +#define __STM32L4xx_HAL_OSPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup OSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup OSPI_Exported_Types OSPI Exported Types + * @{ + */ + +/** + * @brief OSPI Init structure definition + */ +typedef struct +{ + uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + This parameter can be a value between 1 and 32 */ + uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to + quad mode on two different devices to increase the throughput. + This parameter can be a value of @ref OSPI_DualQuad */ + uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. + This parameter can be a value of @ref OSPI_MemoryType */ + uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value between 1 and 32 */ + uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 8 */ + uint32_t FreeRunningClock; /* It enables or not the free running clock. + This parameter can be a value of @ref OSPI_FreeRunningClock */ + uint32_t ClockMode; /* It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref OSPI_ClockMode */ + uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref OSPI_WrapSize */ + uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 1 and 256 */ + uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref OSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. + This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ + uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value between 0 and 31 */ +}OSPI_InitTypeDef; + +/** + * @brief HAL OSPI Handle Structure definition + */ +typedef struct +{ + OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ + OSPI_InitTypeDef Init; /* OSPI initialization parameters */ + uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ + __IO uint32_t XferSize; /* Number of data to transfer */ + __IO uint32_t XferCount; /* Counter of data transferred */ + DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */ + __IO uint32_t State; /* Internal state of the OSPI HAL driver */ + __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ + uint32_t Timeout; /* Timeout used for the OSPI external device access */ +}OSPI_HandleTypeDef; + +/** + * @brief HAL OSPI Regular Command Structure definition + */ +typedef struct +{ + uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref OSPI_OperationType */ + uint32_t FlashId; /* It indicates which external device is selected for this command (it + applies only if Dualquad is disabled in the initialization structure). + This parameter can be a value of @ref OSPI_FlashId */ + uint32_t Instruction; /* It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t InstructionMode; /* It indicates the mode of the instruction. + This parameter can be a value of @ref OSPI_InstructionMode */ + uint32_t InstructionSize; /* It indicates the size of the instruction. + This parameter can be a value of @ref OSPI_InstructionSize */ + uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref OSPI_InstructionDtrMode */ + uint32_t Address; /* It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressMode; /* It indicates the mode of the address. + This parameter can be a value of @ref OSPI_AddressMode */ + uint32_t AddressSize; /* It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref OSPI_AddressDtrMode */ + uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesMode */ + uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesSize */ + uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ + uint32_t DataMode; /* It indicates the mode of the data. + This parameter can be a value of @ref OSPI_DataMode */ + uint32_t NbData; /* It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF */ + uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref OSPI_DataDtrMode */ + uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31 */ + uint32_t DQSMode; /* It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ + uint32_t SIOOMode; /* It enables or not the SIOO mode. + This parameter can be a value of @ref OSPI_SIOOMode */ +}OSPI_RegularCmdTypeDef; + +/** + * @brief HAL OSPI Hyperbus Configuration Structure definition + */ +typedef struct +{ + uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255 */ + uint32_t AccessTime; /* It indicates the number of cycles for the device acces time. + This parameter can be a value between 0 and 255 */ + uint32_t WriteZeroLatency; /* It enables or not the latency for the write access. + This parameter can be a value of @ref OSPI_WriteZeroLatency */ + uint32_t LatencyMode; /* It configures the latency mode. + This parameter can be a value of @ref OSPI_LatencyMode */ +}OSPI_HyperbusCfgTypeDef; + +/** + * @brief HAL OSPI Hyperbus Command Structure definition + */ +typedef struct +{ + uint32_t AddressSpace; /* It indicates the address space accessed by the command. + This parameter can be a value of @ref OSPI_AddressSpace */ + uint32_t Address; /* It contains the address to be sent tot he device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressSize; /* It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t NbData; /* It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be any value between 1 and 4 */ + uint32_t DQSMode; /* It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ +}OSPI_HyperbusCmdTypeDef; + +/** + * @brief HAL OSPI Auto Polling mode configuration structure definition + */ +typedef struct +{ + uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t MatchMode; /* Specifies the method used for determining a match. + This parameter can be a value of @ref OSPI_MatchMode */ + uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref OSPI_AutomaticStop */ + uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. + This parameter can be any value between 0 and 0xFFFF */ +}OSPI_AutoPollingTypeDef; + +/** + * @brief HAL OSPI Memory Mapped mode configuration structure definition + */ +typedef struct +{ + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref OSPI_TimeOutActivation */ + uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. + This parameter can be any value between 0 and 0xFFFF */ +}OSPI_MemoryMappedTypeDef; + +/** + * @brief HAL OSPI IO Manager Configuration structure definition + */ +typedef struct +{ + uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins. + This parameter can be a value between 1 and 8 */ + uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin. + This parameter can be a value between 1 and 8 */ + uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin. + This parameter can be a value between 1 and 8 */ + uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. + This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. + This parameter can be a value of @ref OSPIM_IOPort */ +}OSPIM_CfgTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup OSPI_Exported_Constants OSPI Exported Constants + * @{ + */ + +/** @defgroup OSPI_State OSPI State + * @{ + */ +#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ +#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ +#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ +#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ +#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ +#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ +#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ +#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ +#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ +#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ +#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ +#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ +#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ +/** + * @} + */ + +/** @defgroup OSPI_ErrorCode OSPI Error Code + * @{ + */ +#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ +#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ +#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ +#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ +/** + * @} + */ + +/** @defgroup OSPI_DualQuad OSPI Dual-Quad + * @{ + */ +#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ +#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ +/** + * @} + */ + +/** @defgroup OSPI_MemoryType OSPI Memory Type + * @{ + */ +#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ +#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ +#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ +/** + * @} + */ + +/** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock + * @{ + */ +#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ +#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ +/** + * @} + */ + +/** @defgroup OSPI_ClockMode OSPI Clock Mode + * @{ + */ +#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ +#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ +/** + * @} + */ + +/** @defgroup OSPI_WrapSize OSPI Wrap-Size + * @{ + */ +#define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ +#define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ +#define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ +#define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ +#define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ +/** + * @} + */ + +/** @defgroup OSPI_SampleShifting OSPI Sample Shifting + * @{ + */ +#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ +#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ +/** + * @} + */ + +/** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle + * @{ + */ +#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ +#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ +/** + * @} + */ + +/** @defgroup OSPI_OperationType OSPI Operation Type + * @{ + */ +#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ +#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ +#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ +/** + * @} + */ + +/** @defgroup OSPI_FlashID OSPI Flash Id + * @{ + */ +#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ +#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ +/** + * @} + */ + +/** @defgroup OSPI_InstructionMode OSPI Instruction Mode + * @{ + */ +#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ +#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ +#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ +#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ +#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_InstructionSize OSPI Instruction Size + * @{ + */ +#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ +#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ +#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ +#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ +/** + * @} + */ + +/** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode + * @{ + */ +#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ +#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ +/** + * @} + */ + +/** @defgroup OSPI_AddressMode OSPI Address Mode + * @{ + */ +#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ +#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ +#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ +#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ +#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_AddressSize OSPI Address Size + * @{ + */ +#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ +#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ +#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ +#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ +/** + * @} + */ + +/** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode + * @{ + */ +#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ +#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ +/** + * @} + */ + +/** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode + * @{ + */ +#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ +#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ +#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ +#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size + * @{ + */ +#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ +/** + * @} + */ + +/** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode + * @{ + */ +#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ +#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ +/** + * @} + */ + +/** @defgroup OSPI_DataMode OSPI Data Mode + * @{ + */ +#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ +#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ +#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ +#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ +#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode + * @{ + */ +#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ +#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ +/** + * @} + */ + +/** @defgroup OSPI_DQSMode OSPI DQS Mode + * @{ + */ +#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ +#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ +/** + * @} + */ + +/** @defgroup OSPI_SIOOMode OSPI SIOO Mode + * @{ + */ +#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ +#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ +/** + * @} + */ + +/** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation + * @{ + */ +#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ +#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ +/** + * @} + */ + +/** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode + * @{ + */ +#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ +#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ +/** + * @} + */ + +/** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space + * @{ + */ +#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ +#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ +/** + * @} + */ + +/** @defgroup OSPI_MatchMode OSPI Match Mode + * @{ + */ +#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ +#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ +/** + * @} + */ + +/** @defgroup OSPI_AutomaticStop OSPI Automatic Stop + * @{ + */ +#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ +#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ +/** + * @} + */ + +/** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation + * @{ + */ +#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ +#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ +/** + * @} + */ + +/** @defgroup OSPI_Flags OSPI Flags + * @{ + */ +#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ +#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ +#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ +#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ +#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ +#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ +/** + * @} + */ + +/** @defgroup OSPI_Interrupts OSPI Interrupts + * @{ + */ +#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ +#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ +#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ +#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ +#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ +/** + * @} + */ + +/** @defgroup OSPI_Timeout_definition OSPI Timeout definition + * @{ + */ +#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ +/** + * @} + */ + +/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port + * @{ + */ +#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1)) /*!< Port 1 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ +#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup OSPI_Exported_Macros OSPI Exported Macros + * @{ + */ +/** @brief Reset OSPI handle state. + * @param __HANDLE__: OSPI handle. + * @retval None + */ +#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) + +/** @brief Enable the OSPI peripheral. + * @param __HANDLE__: specifies the OSPI Handle. + * @retval None + */ +#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) + +/** @brief Disable the OSPI peripheral. + * @param __HANDLE__: specifies the OSPI Handle. + * @retval None + */ +#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) + +/** @brief Enable the specified OSPI interrupt. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __INTERRUPT__: specifies the OSPI interrupt source to enable. + * This parameter can be one of the following values: + * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt + * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt + * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt + * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt + * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt + * @retval None + */ +#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + + +/** @brief Disable the specified OSPI interrupt. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __INTERRUPT__: specifies the OSPI interrupt source to disable. + * This parameter can be one of the following values: + * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt + * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt + * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt + * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt + * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt + * @retval None + */ +#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Check whether the specified OSPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __INTERRUPT__: specifies the OSPI interrupt source to check. + * This parameter can be one of the following values: + * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt + * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt + * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt + * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt + * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the selected OSPI flag is set or not. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __FLAG__: specifies the OSPI flag to check. + * This parameter can be one of the following values: + * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag + * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag + * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag + * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag + * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag + * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag + * @retval None + */ +#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) + +/** @brief Clears the specified OSPI's flag status. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __FLAG__: specifies the OSPI clear register flag that needs to be set + * This parameter can be one of the following values: + * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag + * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag + * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag + * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag + * @retval None + */ +#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup OSPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup OSPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup OSPI_Exported_Functions_Group2 + * @{ + */ +/* OSPI IRQ handler function */ +void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); + +/* OSPI command configuration functions */ +HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); + +/* OSPI indirect mode functions */ +HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); + +/* OSPI status flag polling mode functions */ +HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); + +/* OSPI memory-mapped mode functions */ +HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); + +/* Callback functions in non-blocking modes ***********************************/ +void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); + +/* OSPI indirect mode functions */ +void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); + +/* OSPI status flag polling mode functions */ +void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); + +/* OSPI memory-mapped mode functions */ +void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); + +/** + * @} + */ + +/* Peripheral Control and State functions ************************************/ +/** @addtogroup OSPI_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); +uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); +uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); +uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); + +/** + * @} + */ + +/* OSPI IO Manager configuration function ************************************/ +/** @addtogroup OSPI_Exported_Functions_Group4 + * @{ + */ +HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1) && ((THRESHOLD) <= 32)) + +#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ + ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) + +#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) + +#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 32)) + +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1) && ((TIME) <= 8)) + +#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ + ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) + +#define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ + ((MODE) == HAL_OSPI_CLOCK_MODE_3)) + +#define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ + ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ + ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ + ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ + ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) + +#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 256)) + +#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ + ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) + +#define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ + ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) + +#define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ + ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ + ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) + +#define IS_OSPI_FLASH_ID(FLASH) (((FLASH) == HAL_OSPI_FLASH_ID_1) || \ + ((FLASH) == HAL_OSPI_FLASH_ID_2)) + +#define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) + +#define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ + ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ + ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ + ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) + +#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) + +#define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ + ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ + ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ + ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ + ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) + +#define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ + ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ + ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ + ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) + +#define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) + +#define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) + +#define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ + ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ + ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ + ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) + +#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) + +#define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ + ((MODE) == HAL_OSPI_DATA_1_LINE) || \ + ((MODE) == HAL_OSPI_DATA_2_LINES) || \ + ((MODE) == HAL_OSPI_DATA_4_LINES) || \ + ((MODE) == HAL_OSPI_DATA_8_LINES)) + +#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1) + +#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) + +#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31) + +#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ + ((MODE) == HAL_OSPI_DQS_ENABLE)) + +#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ + ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) + +#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255) + +#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255) + +#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ + ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) + +#define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ + ((MODE) == HAL_OSPI_FIXED_LATENCY)) + +#define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ + ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) + +#define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ + ((MODE) == HAL_OSPI_MATCH_MODE_OR)) + +#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ + ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) + +#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFF) + +#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) + +#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) + +#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) + +#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31) + +#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 2)) + +#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ + ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ + ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ + ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) +/** + @endcond + */ + +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_OSPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c index 34cf7ec9873..453922e7409 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -87,7 +85,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -163,8 +162,11 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) - hpcd->EPLock[index].Lock = HAL_UNLOCKED; + + // Added for MBED PR #3062 + for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + hpcd->EPLock[index].Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); } @@ -470,6 +472,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { fifoemptymsk = 0x1 << epnum; + + // Added for MBED PR #3062 atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); @@ -1189,6 +1193,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0; ep->num = ep_addr & 0x7F; + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); if ((ep_addr & 0x7F) == 0 ) @@ -1199,6 +1204,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u { USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); } + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1234,7 +1241,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->xfer_count = 0; ep->is_in = 1; ep->num = ep_addr & 0x7F; - + + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); if ((ep_addr & 0x7F) == 0 ) @@ -1245,7 +1253,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); } - + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1273,13 +1282,17 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep->is_stall = 1; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - + + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); + USB_EPSetStall(hpcd->Instance , ep); if((ep_addr & 0x7F) == 0) { USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1307,9 +1320,13 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep->is_stall = 0; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - + + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); + USB_EPClearStall(hpcd->Instance , ep); + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1323,7 +1340,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); + if ((ep_addr & 0x80) == 0x80) { USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); @@ -1332,7 +1351,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_FlushRxFifo(hpcd->Instance); } - + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1445,6 +1465,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t if(len <= 0) { fifoemptymsk = 0x1 << epnum; + // Added for MBED PR #3062 atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); } @@ -1667,7 +1688,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_PCD_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h index 01be38c5fdc..ff07fdfd25b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -46,7 +44,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" @@ -118,6 +117,8 @@ typedef USB_TypeDef PCD_TypeDef; typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; #endif /* USB */ + +// Added for MBED PR #3062 typedef struct { HAL_LockTypeDef Lock; @@ -134,6 +135,7 @@ typedef struct PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ +// Added for MBED PR #3062 PCD_EPLockDef EPLock[15]; __IO PCD_StateTypeDef State; /*!< PCD communication state */ uint32_t Setup[12]; /*!< Setup packet buffer */ @@ -867,7 +869,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c index d90cf064cb3..8a3cc9a3452 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PCD Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -45,18 +43,20 @@ /** @addtogroup STM32L4xx_HAL_Driver * @{ */ -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) /** @defgroup PCDEx PCDEx * @brief PCD Extended HAL module driver * @{ */ +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ + defined(STM32L452xx) || defined(STM32L462xx) || \ + defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -503,6 +503,15 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ + +#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ + /* STM32L452xx || STM32L462xx || */ + /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + /** * @} */ @@ -511,11 +520,4 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h index 45054ab3207..f27c8b6a4ad 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -46,7 +44,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -124,7 +123,8 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c index 0ba3d39d61b..3f5877b4d90 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h index 7a2b6ae5468..f33df34e85e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c index 9280365e545..1c08c0feff2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -63,11 +61,11 @@ #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */ -#elif defined (STM32L496xx) || defined (STM32L4A6xx) +#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */ #endif -#if defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */ #endif @@ -127,11 +125,28 @@ /** * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 + * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) */ uint32_t HAL_PWREx_GetVoltageRange(void) { +#if defined(PWR_CR5_R1MODE) + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + return PWR_REGULATOR_VOLTAGE_SCALE2; + } + else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) + { + /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ + return PWR_REGULATOR_VOLTAGE_SCALE1; + } + else + { + return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; + } +#else return (PWR->CR1 & PWR_CR1_VOS); +#endif } @@ -141,6 +156,11 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * @param VoltageScaling: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: + @if STM32L4S9xx + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, + * typical output voltage at 1.2 V, + * system frequency up to 120 MHz. + @endif * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, * typical output voltage at 1.2 V, * system frequency up to 80 MHz. @@ -150,7 +170,8 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * @note When moving from Range 1 to Range 2, the system frequency must be decreased to * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 2 to Range 1, the system frequency can be increased to - * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For + * some devices, the system frequency can be increased up to 120 MHz. * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. @@ -161,7 +182,76 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) uint32_t wait_loop_index = 0; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + +#if defined(PWR_CR5_R1MODE) + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) + { + /* If current range is range 2 */ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Make sure Range 1 Boost is enabled */ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); + + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); + while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + /* If current range is range 1 normal or boost mode */ + else + { + /* Enable Range 1 Boost (no issue if bit already reset) */ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); + } + } + else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + { + /* If current range is range 2 */ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Make sure Range 1 Boost is disabled */ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); + + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); + while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + /* If current range is range 1 normal or boost mode */ + else + { + /* Disable Range 1 Boost (no issue if bit already set) */ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); + } + } + else + { + /* Set Range 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); + /* No need to wait for VOSF to be cleared for this transition */ + /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ + } +#else + /* If Set Range 1 */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) { @@ -191,6 +281,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No need to wait for VOSF to be cleared for this transition */ } } +#endif return HAL_OK; } @@ -658,8 +749,52 @@ void HAL_PWREx_DisableSRAM2ContentRetention(void) } +#if defined(PWR_CR1_RRSTP) +/** + * @brief Enable SRAM3 content retention in Stop 2 mode. + * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in + * Stop 2 mode and its content is kept. + * @retval None + */ +void HAL_PWREx_EnableSRAM3ContentRetention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_RRSTP); +} +/** + * @brief Disable SRAM3 content retention in Stop 2 mode. + * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode + * and its content is lost. + * @retval None + */ +void HAL_PWREx_DisableSRAM3ContentRetention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); +} +#endif /* PWR_CR1_RRSTP */ + +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins. + * @retval None + */ +void HAL_PWREx_EnableDSIPinsPDActivation(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + + +/** + * @brief Disable pull-down activation on DSI pins. + * @retval None + */ +void HAL_PWREx_DisableDSIPinsPDActivation(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} +#endif /* PWR_CR3_DSIPDEN */ + #if defined(PWR_CR2_PVME1) /** * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h index 8d044036c27..2830478169e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention @@ -155,8 +153,11 @@ typedef struct /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale * @{ */ -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ +#if defined(PWR_CR5_R1MODE) +#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ +#endif +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ /** * @} */ @@ -717,7 +718,8 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN5_LOW)) #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_2) ||\ ((TYPE) == PWR_PVM_3) ||\ @@ -745,8 +747,15 @@ typedef struct ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) +#if defined(PWR_CR5_R1MODE) +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#endif + #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) @@ -779,7 +788,8 @@ typedef struct ((GPIO) == PWR_GPIO_F) ||\ ((GPIO) == PWR_GPIO_G) ||\ ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L496xx) || defined (STM32L4A6xx) +#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ @@ -829,6 +839,14 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void); void HAL_PWREx_DisablePullUpPullDownConfig(void); void HAL_PWREx_EnableSRAM2ContentRetention(void); void HAL_PWREx_DisableSRAM2ContentRetention(void); +#if defined(PWR_CR1_RRSTP) +void HAL_PWREx_EnableSRAM3ContentRetention(void); +void HAL_PWREx_DisableSRAM3ContentRetention(void); +#endif /* PWR_CR1_RRSTP */ +#if defined(PWR_CR3_DSIPDEN) +void HAL_PWREx_EnableDSIPinsPDActivation(void); +void HAL_PWREx_DisableDSIPinsPDActivation(void); +#endif /* PWR_CR3_DSIPDEN */ #if defined(PWR_CR2_PVME1) void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_DisablePVM1(void); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c index 1beb35b41d4..27ae77c5673 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_qspi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief QSPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). @@ -168,6 +166,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" +#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -241,7 +241,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -263,9 +263,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) @@ -291,7 +289,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES))); + ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); @@ -299,21 +297,19 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) if(status == HAL_OK) { /* Configure QSPI Clock Prescaler and Sample Shift */ -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), - ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); #else MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), - ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting)); #endif /* Configure QSPI Flash Size, CS High Time and Clock Mode */ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) | + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ @@ -335,7 +331,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -369,10 +365,10 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ -__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) + __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -384,10 +380,10 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ -__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) + __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -423,7 +419,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -433,7 +429,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT)) + if(((flag & QSPI_FLAG_FT) != 0) && ((itsource & QSPI_IT_FT) !=0 )) { data_reg = &hqspi->Instance->DR; @@ -445,7 +441,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->TxXferCount > 0) { /* Fill the FIFO until the threshold is reached */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } else @@ -465,7 +461,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0) { /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); hqspi->RxXferCount--; } else @@ -483,7 +479,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC)) + else if(((flag & QSPI_FLAG_TC) != 0) && ((itsource & QSPI_IT_TC) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); @@ -494,7 +490,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -516,7 +512,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -532,7 +528,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); hqspi->RxXferCount--; } else @@ -547,7 +543,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); #endif - + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -585,7 +581,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM)) + else if(((flag & QSPI_FLAG_SM) != 0) && ((itsource & QSPI_IT_SM) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); @@ -605,7 +601,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE)) + else if(((flag & QSPI_FLAG_TE) != 0) && ((itsource & QSPI_IT_TE) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); @@ -616,7 +612,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -629,14 +625,14 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; - + /* Error callback */ HAL_QSPI_ErrorCallback(hqspi); } } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO)) + else if(((flag & QSPI_FLAG_TO) != 0) && ((itsource & QSPI_IT_TO) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); @@ -648,7 +644,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration * @note This function is used only in Indirect Read or Write Modes @@ -738,7 +734,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status @@ -826,19 +822,19 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp else { status = HAL_BUSY; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } - + /* Return function status */ return status; } /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status @@ -855,7 +851,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ @@ -879,7 +875,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u break; } - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -923,8 +919,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status @@ -969,7 +965,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui break; } - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); hqspi->RxXferCount--; } @@ -979,7 +975,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); if (status == HAL_OK) - { + { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -1012,8 +1008,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1072,8 +1068,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1136,8 +1132,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1174,7 +1170,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1205,43 +1201,43 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - + /* Configure size and pointer of the handle */ hqspi->TxXferSize = hqspi->TxXferCount; hqspi->pTxBuffPtr = pData; - + /* Configure QSPI: CCR register with functional mode as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); - + /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)&pData; + tmp = (uint32_t*)((void*)&pData); HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } @@ -1250,7 +1246,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat { hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1258,18 +1254,18 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat else { status = HAL_BUSY; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } - + return status; } /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1292,7 +1288,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - if(pData != NULL) + if(pData != NULL ) { /* Configure counters of the handle */ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) @@ -1324,7 +1320,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1338,46 +1334,46 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - + /* Configure size and pointer of the handle */ hqspi->RxXferSize = hqspi->RxXferCount; hqspi->pRxBuffPtr = pData; - + /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); - + /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; + tmp = (uint32_t*)((void*)&pData); HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - + /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } @@ -1404,9 +1400,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @param Timeout : Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status @@ -1505,9 +1501,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1598,7 +1594,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman else { status = HAL_BUSY; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1609,9 +1605,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1664,9 +1660,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT if (status == HAL_OK) { /* Configure QSPI: CR register with timeout counter enable */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); @@ -1698,7 +1694,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1713,7 +1709,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1728,7 +1724,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1743,7 +1739,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1758,7 +1754,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1773,7 +1769,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1788,10 +1784,10 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ -__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) + __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -1803,7 +1799,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1818,7 +1814,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1833,7 +1829,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1870,7 +1866,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -1881,7 +1877,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -1891,7 +1887,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -1905,11 +1901,11 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Process unlocked */ __HAL_UNLOCK(hqspi); - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Abort DMA channel */ status = HAL_DMA_Abort(hqspi->hdma); if(status != HAL_OK) @@ -1917,21 +1913,21 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; } } - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - + /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if(status == HAL_OK) - { + if (status == HAL_OK) + { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Wait until BUSY flag is reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); } - + if (status == HAL_OK) { /* Update state */ @@ -1944,7 +1940,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -1956,18 +1952,18 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_ABORT; - + /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Abort DMA channel */ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; HAL_DMA_Abort_IT(hqspi->hdma); @@ -1976,10 +1972,10 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Enable the QSPI Transfer Complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } @@ -1988,8 +1984,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout. - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. + * @param hqspi : QSPI handle. + * @param Timeout : Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -1998,8 +1994,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @param hqspi : QSPI handle. + * @param Threshold : Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2016,7 +2012,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES))); + ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); } else { @@ -2031,12 +2027,12 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. + * @param hqspi : QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) { - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1); + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1); } /** @@ -2045,7 +2041,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) /** * @brief DMA QSPI receive process complete callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2059,7 +2055,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2097,7 +2093,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2117,7 +2113,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2144,25 +2140,26 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /* DMA Abort called due to a transfer error interrupt */ /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; - + /* Error callback */ HAL_QSPI_ErrorCallback(hqspi); } } + /** * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is in expected state */ - while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) + while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -2181,9 +2178,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param FunctionalMode : functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2213,7 +2210,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction, address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); @@ -2229,7 +2226,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); @@ -2242,7 +2239,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); @@ -2257,7 +2254,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only instruction ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } @@ -2275,7 +2272,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); @@ -2291,7 +2288,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } @@ -2303,7 +2300,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); @@ -2320,7 +2317,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } @@ -2342,4 +2339,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h index 9b2e82197da..cef4014d75e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_qspi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -46,6 +44,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -81,9 +81,7 @@ typedef struct This parameter can be a value of @ref QSPI_ChipSelectHighTime */ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ uint32_t DualFlash; /* Specifies the Dual Flash Mode State @@ -206,10 +204,10 @@ typedef struct /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */ /** * @} @@ -248,9 +246,7 @@ typedef struct * @} */ -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) /** @defgroup QSPI_Flash_Select QSPI Flash Select * @{ */ @@ -328,7 +324,7 @@ typedef struct /** @defgroup QSPI_DataMode QSPI Data Mode * @{ */ -#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!State = HAL_QSPI_STATE_RESET) /** @brief Enable the QSPI peripheral. - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) @@ -507,7 +501,7 @@ typedef struct * @arg QSPI_FLAG_TE: QSPI Transfer error flag * @retval None */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. * @param __HANDLE__: specifies the QSPI Handle. @@ -611,9 +605,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ ((CLKMODE) == QSPI_CLOCK_MODE_3)) -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) #define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \ ((FLASH) == QSPI_FLASH_ID_2)) @@ -658,9 +650,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CCR_DHHC) #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) #else @@ -696,7 +686,9 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); /** * @} */ - + +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c index 222237da3d7..06a9b266583 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -87,12 +85,12 @@ * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */ +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} */ @@ -106,25 +104,21 @@ #define MCO1_PIN GPIO_PIN_8 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) /** * @} */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCC_Private_Functions RCC Private Functions * @{ */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +static uint32_t RCC_GetSysClockFreqFromPLLSource(void); +#endif /** * @} */ @@ -150,11 +144,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); [..] Internal/external clock and PLL configuration (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. - + (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. It can be used to generate the clock for the USB OTG FS (48 MHz). - The number of flash wait states is automatically adjusted when MSI range is updated with - HAL_RCC_OscConfig() and the MSI is used as System clock source. + The number of flash wait states is automatically adjusted when MSI range is updated with + HAL_RCC_OscConfig() and the MSI is used as System clock source. (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. @@ -212,21 +206,41 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz - to work correctly, while the SDMMC1 and RNG peripherals require a frequency + to work correctly, while the SDMMC1 and RNG peripherals require a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1 - through PLLQ divider. You have to enable the peripheral clock and use + through PLLQ divider. You have to enable the peripheral clock and use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. The clock source frequency should be adapted depending on the device voltage range as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. @endverbatim - - Table 1. HCLK clock frequency. - +-------------------------------------------------------+ + + Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices + +--------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |--------------------------------------| + | | voltage range 1 | voltage range 2 | + | | 1.2 V | 1.0 V | + |-----------------|-------------------|------------------| + |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | + |-----------------|-------------------|------------------| + |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | + |-----------------|-------------------|------------------| + |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | + |-----------------|-------------------|------------------| + |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | + |-----------------|-------------------|------------------| + |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | + |-----------------|-------------------|------------------| + |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | + +--------------------------------------------------------+ + + Table 2. HCLK clock frequency for other STM32L4 devices + +-------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |-------------------------------------| | | voltage range 1 | voltage range 2 | @@ -253,28 +267,63 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 OFF * - All interrupts disabled + * - All interrupt and reset flags cleared * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks - * @retval None + * @retval HAL status */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { + uint32_t tickstart = 0; + /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); /* Insure MSIRDY bit is set before writing default MSIRANGE value */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); } - + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Set MSIRANGE default value */ MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); - + /* Reset CFGR register (MSI is selected as system clock source) */ CLEAR_REG(RCC->CFGR); + /* Update the SystemCoreClock global variable for MSI as system clock source */ + SystemCoreClock = MSI_VALUE; + + /* Configure the source of time base considering new system clock settings */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Insure MSI selected as system clock source */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till system clock source is ready */ + while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */ #if defined(RCC_PLLSAI2_SUPPORT) - + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); #else @@ -282,7 +331,27 @@ void HAL_RCC_DeInit(void) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); #endif /* RCC_PLLSAI2_SUPPORT */ - + + /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ + /* Get start tick */ + tickstart = HAL_GetTick(); + +#if defined(RCC_PLLSAI2_SUPPORT) + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + +#else + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + +#endif + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset PLLCFGR register */ CLEAR_REG(RCC->PLLCFGR); SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); @@ -292,11 +361,11 @@ void HAL_RCC_DeInit(void) SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); #if defined(RCC_PLLSAI2_SUPPORT) - + /* Reset PLLSAI2CFGR register */ CLEAR_REG(RCC->PLLSAI2CFGR); SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 ); - + #endif /* RCC_PLLSAI2_SUPPORT */ /* Reset HSEBYP bit */ @@ -305,8 +374,13 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIER); - /* Update the SystemCoreClock global variable */ - SystemCoreClock = MSI_VALUE; + /* Clear all interrupt flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Clear all reset flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + return HAL_OK; } /** @@ -378,12 +452,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) { return HAL_ERROR; - } + } } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; - + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); } @@ -439,7 +513,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) @@ -490,7 +564,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) { @@ -594,7 +668,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; - + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); @@ -605,12 +679,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); @@ -774,14 +848,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable all PLL outputs to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); #else @@ -821,6 +895,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles + @if STM32L4S9xx + * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles + * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles + * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles + * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles + * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles + * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles + * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles + * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles + * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles + * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles + * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles + @endif * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function @@ -830,7 +917,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * the MSI frequency is set to its default value 4 MHz. * * @note The HSI can be selected as system clock source after - * from STOP modes or in case of failure of the HSE used directly or indirectly + * from STOP modes or in case of failure of the HSE used directly or indirectly * as system clock (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target @@ -849,6 +936,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t pllfreq = 0; + uint32_t hpre = RCC_SYSCLK_DIV1; +#endif /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); @@ -860,75 +951,99 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) - { - return HAL_ERROR; - } - } /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) { return HAL_ERROR; } - } - /* MSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ + /* Compute target PLL output frequency */ + pllfreq = RCC_GetSysClockFreqFromPLLSource(); + + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + if((pllfreq > 80000000U) && + (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) + || + ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) { - return HAL_ERROR; + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; } +#endif } - /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - return HAL_ERROR; + /* Check the HSE ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* MSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + { + /* Check the MSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + return HAL_ERROR; + } } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ + pllfreq = HAL_RCC_GetSysClockFreq(); + + /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ + if(pllfreq > 80000000U) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } +#endif + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick*/ tickstart = HAL_GetTick(); - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { @@ -936,52 +1051,72 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + else { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + else { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } } } - + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else + { + /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ + if(hpre == RCC_SYSCLK_DIV2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); + } + } +#endif + /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } - + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { @@ -997,7 +1132,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -1009,7 +1144,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim @@ -1018,7 +1153,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui =============================================================================== [..] This subsection provides a set of functions allowing to: - + (+) Ouput clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @@ -1123,11 +1258,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* Get SYSCLK source */ if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE); + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } else { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE); + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; @@ -1156,25 +1291,25 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ; + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: - pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); + pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U; + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } @@ -1203,7 +1338,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** @@ -1215,7 +1350,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** @@ -1240,11 +1375,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_HSI48_SUPPORT */ /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1254,7 +1389,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the MSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION) + if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION) { RCC_OscInitStruct->MSIState = RCC_MSI_ON; } @@ -1263,11 +1398,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->MSIState = RCC_MSI_OFF; } - RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM)); - RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) ); + RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos; + RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } @@ -1276,14 +1411,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM)); + RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -1293,7 +1428,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } @@ -1304,7 +1439,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration ---------------------------------------------*/ - if((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) + if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; } @@ -1317,7 +1452,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_HSI48_SUPPORT */ /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1325,15 +1460,15 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U); - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV)); + RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; #else - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET) + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) { RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; } @@ -1362,19 +1497,19 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); } /** @@ -1434,7 +1569,7 @@ __weak void HAL_RCC_CSSCallback(void) * @{ */ /** - * @brief Update number of Flash wait states in line with MSI range and current + * @brief Update number of Flash wait states in line with MSI range and current voltage range. * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 * @retval HAL status @@ -1443,7 +1578,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { uint32_t vos = 0; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) { vos = HAL_PWREx_GetVoltageRange(); @@ -1454,7 +1589,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) vos = HAL_PWREx_GetVoltageRange(); __HAL_RCC_PWR_CLK_DISABLE(); } - + if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) { if(msirange > RCC_MSIRANGE_8) @@ -1475,6 +1610,22 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) } else { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(msirange >= RCC_MSIRANGE_8) + { + /* MSI >= 16Mhz */ + latency = FLASH_LATENCY_2; /* 2WS */ + } + else + { + if(msirange == RCC_MSIRANGE_7) + { + /* MSI 8Mhz */ + latency = FLASH_LATENCY_1; /* 1WS */ + } + /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ + } +#else if(msirange > RCC_MSIRANGE_8) { /* MSI > 16Mhz */ @@ -1487,27 +1638,82 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) /* MSI 16Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ } - else if(msirange == RCC_MSIRANGE_7) + else if(msirange == RCC_MSIRANGE_7) { /* MSI 8Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ } /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ } +#endif } - + __HAL_FLASH_SET_LATENCY(latency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != latency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) { return HAL_ERROR; } - + return HAL_OK; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Compute SYSCLK frequency based on PLL SYSCLK source. + * @retval SYSCLK frequency + */ +static uint32_t RCC_GetSysClockFreqFromPLLSource(void) +{ + uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; + uint32_t sysclockfreq = 0U; + + if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) + { + /* Get MSI range source */ + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + } + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + } + + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + sysclockfreq = pllvco/pllr; + + return sysclockfreq; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h index 709970c95ba..9c8014cdef0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -71,7 +69,8 @@ typedef struct This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. + This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ @@ -121,7 +120,7 @@ typedef struct uint32_t MSIClockRange; /*!< The MSI frequency range. This parameter can be a value of @ref RCC_MSI_Clock_Range */ - uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x/STM32L49x/STM32L4Ax devices). + uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). This parameter can be a value of @ref RCC_HSI48_Config */ RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ @@ -162,7 +161,7 @@ typedef struct /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} @@ -171,14 +170,14 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */ +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -187,9 +186,9 @@ typedef struct /** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ /** * @} */ @@ -197,9 +196,9 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ /** * @} */ @@ -207,14 +206,14 @@ typedef struct /** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ #else -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /** @@ -224,8 +223,8 @@ typedef struct /** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ @@ -233,10 +232,10 @@ typedef struct /** @defgroup RCC_MSI_Config MSI Config * @{ */ -#define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */ -#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ +#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ +#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ -#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */ +#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ /** * @} */ @@ -245,8 +244,8 @@ typedef struct /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ -#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ -#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ /** * @} */ @@ -254,7 +253,7 @@ typedef struct /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ -#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ /** * @} */ @@ -263,9 +262,9 @@ typedef struct /** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */ -#define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */ -#define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ @@ -274,39 +273,39 @@ typedef struct * @{ */ #if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */ -#define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */ -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */ -#define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */ -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */ -#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */ -#define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */ -#define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */ -#define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */ -#define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */ -#define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */ -#define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */ -#define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */ -#define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */ -#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ -#define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */ -#define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */ -#define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */ -#define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */ -#define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */ -#define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */ -#define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */ -#define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */ -#define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */ -#define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */ -#define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */ -#define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */ -#define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */ -#define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */ +#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ #else -#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ /** * @} @@ -315,10 +314,10 @@ typedef struct /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ */ -#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */ -#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */ -#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */ -#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */ +#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ /** * @} */ @@ -326,10 +325,10 @@ typedef struct /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider * @{ */ -#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */ -#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */ -#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */ -#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */ +#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ /** * @} */ @@ -337,7 +336,7 @@ typedef struct /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ -#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ @@ -375,7 +374,14 @@ typedef struct * @{ */ #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ +#else +#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ /** * @} */ @@ -404,10 +410,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ @@ -465,10 +471,10 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ @@ -476,8 +482,8 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000U) -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ @@ -485,7 +491,7 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ -#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ @@ -503,7 +509,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler * @{ */ -#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ +#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ @@ -545,34 +551,34 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */ -#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */ +#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ #if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */ +#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ #endif /* RCC_PLLSAI2_SUPPORT */ /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */ -#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */ -#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */ -#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */ -#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ -#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */ -#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ +#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ #if defined(RCC_HSI48_SUPPORT) /* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */ +#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -581,19 +587,19 @@ typedef struct /** @defgroup RCC_LSEDrive_Config LSE Drive Config * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ /** * @} */ -/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock +/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock * @{ */ -#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */ -#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ /** * @} */ @@ -632,6 +638,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ @@ -655,7 +671,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) - + #if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -664,13 +680,27 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ UNUSED(tmpreg); \ } while(0) -#endif /* DMA2D */ +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) @@ -679,7 +709,11 @@ typedef struct #if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) -#endif /* DMA2D */ +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) +#endif /* GFXMMU */ /** * @} @@ -800,7 +834,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* DCMI */ #if defined(AES) @@ -820,7 +854,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ @@ -831,6 +865,26 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ + #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) @@ -880,6 +934,14 @@ typedef struct #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ + /** * @} */ @@ -912,6 +974,26 @@ typedef struct } while(0) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) #endif /* FMC_BANK1 */ @@ -920,6 +1002,14 @@ typedef struct #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) +#endif /* OCTOSPI2 */ + /** * @} */ @@ -1123,7 +1213,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ UNUSED(tmpreg); \ } while(0) - + #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1319,7 +1409,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ @@ -1327,7 +1417,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ UNUSED(tmpreg); \ } while(0) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1418,12 +1508,32 @@ typedef struct } while(0) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1453,6 +1563,14 @@ typedef struct #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) +#endif /* DSI */ + /** * @} */ @@ -1469,6 +1587,10 @@ typedef struct #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) @@ -1479,11 +1601,19 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) +#endif /* GFXMMU */ + #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) @@ -1494,6 +1624,10 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) +#endif /* GFXMMU */ + /** * @} */ @@ -1508,7 +1642,7 @@ typedef struct #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) @@ -1840,9 +1974,9 @@ typedef struct #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) @@ -1872,12 +2006,20 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) @@ -1907,6 +2049,14 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) +#endif /* DSI */ + /** * @} */ @@ -1921,6 +2071,10 @@ typedef struct #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) @@ -1931,6 +2085,10 @@ typedef struct #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) @@ -1938,6 +2096,10 @@ typedef struct #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) @@ -1948,6 +2110,10 @@ typedef struct #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + /** * @} */ @@ -2006,6 +2172,14 @@ typedef struct #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) +#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ + #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) @@ -2057,6 +2231,14 @@ typedef struct #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) +#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ + /** * @} */ @@ -2075,6 +2257,14 @@ typedef struct #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) +#endif /* OCTOSPI2 */ + #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) #if defined(FMC_BANK1) @@ -2085,6 +2275,14 @@ typedef struct #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) +#endif /* OCTOSPI2 */ + /** * @} */ @@ -2278,9 +2476,9 @@ typedef struct #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) @@ -2310,14 +2508,22 @@ typedef struct #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) +#endif /* DSI */ + #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) @@ -2347,6 +2553,14 @@ typedef struct #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) +#endif /* DSI */ + /** * @} */ @@ -2364,6 +2578,10 @@ typedef struct #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) @@ -2376,11 +2594,19 @@ typedef struct #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) @@ -2393,6 +2619,10 @@ typedef struct #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + /** * @} */ @@ -2436,6 +2666,10 @@ typedef struct #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) #endif /* USB_OTG_FS */ @@ -2456,6 +2690,14 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) @@ -2487,6 +2729,10 @@ typedef struct #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) #endif /* USB_OTG_FS */ @@ -2507,6 +2753,14 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + /** * @} */ @@ -2524,6 +2778,14 @@ typedef struct #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ @@ -2532,6 +2794,14 @@ typedef struct #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ @@ -2745,9 +3015,9 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) @@ -2777,12 +3047,20 @@ typedef struct #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) @@ -2812,6 +3090,14 @@ typedef struct #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) +#endif /* DSI */ + /** * @} */ @@ -2829,6 +3115,10 @@ typedef struct #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) @@ -2841,11 +3131,19 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) +#endif /* GFXMMU */ + #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) @@ -2858,6 +3156,10 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) +#endif /* GFXMMU */ + /** * @} */ @@ -2901,6 +3203,10 @@ typedef struct #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) #endif /* USB_OTG_FS */ @@ -2921,6 +3227,14 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) @@ -2952,6 +3266,10 @@ typedef struct #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) #endif /* USB_OTG_FS */ @@ -2972,6 +3290,14 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + /** * @} */ @@ -2989,14 +3315,31 @@ typedef struct #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) #endif /* FMC_BANK1 */ + #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) #endif /* FMC_BANK1 */ @@ -3210,9 +3553,9 @@ typedef struct #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) @@ -3242,12 +3585,20 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) @@ -3277,13 +3628,21 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) +#endif /* DSI */ + /** * @} */ /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset - * @{ - */ + * @{ + */ /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) @@ -3300,8 +3659,8 @@ typedef struct */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable or disable the RTC clock. * @note As the RTC is in the Backup domain and write access is denied to @@ -3342,13 +3701,13 @@ typedef struct /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). * @retval None */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM)) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) /** * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) @@ -3400,13 +3759,13 @@ typedef struct * and temperature that influence the frequency of the internal MSI RC. * Refer to the Application Note AN3300 for more details on how to * calibrate the MSI. - * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value + * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_MSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 255. * @retval None */ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode @@ -3418,7 +3777,7 @@ typedef struct * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready * (MSIRDY=1). * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz @@ -3443,7 +3802,7 @@ typedef struct /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz @@ -3472,8 +3831,8 @@ typedef struct */ #define __HAL_RCC_GET_MSI_RANGE() \ ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ - (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ - (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) + READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ + READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -3503,7 +3862,7 @@ typedef struct * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. - * @param __STATE__: specifies the new state of the HSE. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. @@ -3532,8 +3891,8 @@ typedef struct /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE @@ -3541,7 +3900,7 @@ typedef struct * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. + * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. @@ -3591,9 +3950,9 @@ typedef struct * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * - * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected @@ -3612,12 +3971,12 @@ typedef struct /** @brief Macro to get the RTC clock source. * @retval The returned value can be one of the following: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected */ -#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macros to enable or disable the main PLL. * @note After enabling the main PLL, the application software should wait on @@ -3633,7 +3992,7 @@ typedef struct /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry @@ -3641,20 +4000,21 @@ typedef struct * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * @retval None - * + * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL source division factor M. * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 1 and Max_Data = 8. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. + * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. * @retval None - * + * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) @@ -3663,7 +4023,7 @@ typedef struct * @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry @@ -3671,28 +4031,29 @@ typedef struct * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * - * @param __PLLM__: specifies the division factor for PLL VCO input clock. - * This parameter must be a number between 1 and 8. + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. + * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. * - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * - * @param __PLLP__: specifies the division factor for SAI clock. + * @param __PLLP__ specifies the division factor for SAI clock. * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x * else (2 to 31). * - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. * This parameter must be in the range (2, 4, 6 or 8). * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work * correctly. - * @param __PLLR__: specifies the division factor for the main system clock. + * @param __PLLR__ specifies the division factor for the main system clock. * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. * This parameter must be in the range (2, 4, 6 or 8). * @retval None @@ -3701,14 +4062,14 @@ typedef struct #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - (uint32_t)((__PLLP__) << 27U)) - + (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ + ((uint32_t)(__PLLP__) << 27U)) #else - + #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) + (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ + (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ + (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ @@ -3720,14 +4081,14 @@ typedef struct * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) /** * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime - * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot + * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot * be stopped if used as System Clock. - * @param __PLLCLOCKOUT__: specifies the PLL clock to be output. + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. * This parameter can be one or a combination of the following values: * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * high-quality audio performance on SAI interface in case. @@ -3742,7 +4103,7 @@ typedef struct /** * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked. + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. * This parameter can be one of the following values: * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * high-quality audio performance on SAI interface in case. @@ -3755,7 +4116,7 @@ typedef struct /** * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__: specifies the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. @@ -3774,7 +4135,7 @@ typedef struct * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) +#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) /** * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. @@ -3782,7 +4143,7 @@ typedef struct * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). - * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. @@ -3791,11 +4152,11 @@ typedef struct * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) /** * @brief Macro to configure the wake up from stop clock. - * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. + * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. * This parameter can be one of the following values: * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source @@ -3819,9 +4180,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 @endif @@ -3841,9 +4199,8 @@ typedef struct * @{ */ -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. +/** @brief Enable RCC interrupt(s). + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3857,9 +4214,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif @@ -3867,9 +4221,8 @@ typedef struct */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. +/** @brief Disable RCC interrupt(s). + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3883,9 +4236,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif @@ -3893,9 +4243,8 @@ typedef struct */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3910,18 +4259,15 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif * @retval None */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) /** @brief Check whether the RCC interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3936,25 +4282,22 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. * @retval None */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) +#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) /** @brief Check whether the selected RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready @@ -3965,9 +4308,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 @endif @@ -3986,18 +4326,16 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #if defined(RCC_HSI48_SUPPORT) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ - ? 1U : 0U) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #else #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ - ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #endif /* RCC_HSI48_SUPPORT */ /** @@ -4007,20 +4345,20 @@ typedef struct /** * @} */ - + /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ /* Defines used for Flags */ -#define CR_REG_INDEX ((uint32_t)1U) -#define BDCR_REG_INDEX ((uint32_t)2U) -#define CSR_REG_INDEX ((uint32_t)3U) +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U #if defined(RCC_HSI48_SUPPORT) -#define CRRCR_REG_INDEX ((uint32_t)4U) +#define CRRCR_REG_INDEX 4U #endif /* RCC_HSI48_SUPPORT */ -#define RCC_FLAG_MASK ((uint32_t)0x1FU) +#define RCC_FLAG_MASK 0x1FU /** * @} */ @@ -4055,13 +4393,13 @@ typedef struct #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM))) +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) #if defined(RCC_HSI48_SUPPORT) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) @@ -4075,7 +4413,11 @@ typedef struct ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#if defined(RCC_PLLM_DIV_1_16_SUPPORT) +#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) +#else #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) +#endif /*RCC_PLLM_DIV_1_16_SUPPORT */ #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -4097,9 +4439,16 @@ typedef struct (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) + (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) +#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ + (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ + (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ + (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ #endif /* RCC_PLLSAI2_SUPPORT */ #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ @@ -4137,7 +4486,7 @@ typedef struct ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) @@ -4194,7 +4543,7 @@ typedef struct */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c index e3f89b1de64..7c31e73fb57 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extended peripheral: @@ -60,9 +58,9 @@ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ -#define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define DIVIDER_P_UPDATE 0U #define DIVIDER_Q_UPDATE 1U @@ -99,7 +97,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim @@ -143,6 +141,9 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) + @endif * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock @@ -154,6 +155,9 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) + @endif * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock @if STM32L443xx * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) @@ -173,12 +177,23 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u @if STM32L486xx * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) @endif @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) + * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) + * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) + @endif * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. @@ -230,6 +245,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /* RCC_PLLSAI2_SUPPORT */ case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI1 clock source config set later after clock selection check */ break; @@ -279,6 +297,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk break; case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI2 clock source config set later after clock selection check */ break; @@ -304,7 +325,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { FlagStatus pwrclkchanged = RESET; - + /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); @@ -314,14 +335,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while((PWR->CR1 & PWR_CR1_DBP) == RESET) + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { @@ -331,11 +352,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } if(ret == HAL_OK) - { + { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - - if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection)) + + if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); @@ -362,7 +383,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - + if(ret == HAL_OK) { /* Apply new RTC clock source selection */ @@ -483,7 +504,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } -#if defined(I2C2) +#if defined(I2C2) /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) @@ -507,7 +528,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } -#if defined(I2C4) +#if defined(I2C4) /*-------------------------- I2C4 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) @@ -540,7 +561,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -559,17 +580,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - - if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) + + if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } +#if defined(RCC_CCIPR2_SDMMCSEL) + else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ + { + /* Enable PLLSAI3CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); + } +#endif else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -595,7 +623,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -612,7 +640,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - + if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ @@ -631,7 +659,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -669,8 +697,109 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /*-------------------------- DFSDM1 audio clock source configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM1 interface audio clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + + /*-------------------------- LTDC clock source configuration --------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); + + /* Disable the PLLSAI2 */ + __HAL_RCC_PLLSAI2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI2 is ready */ + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if(ret == HAL_OK) + { + /* Configure the LTDC clock source */ + __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); + + /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ + ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); + } + + if(ret != HAL_OK) + { + /* set overall return value */ + status = ret; + } + } + +#endif /* LTDC */ + +#if defined(DSI) + + /*-------------------------- DSI clock source configuration ---------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + /* Check the parameters */ + assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection)); + + /* Configure the DSI clock source */ + __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + + if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2) + { + /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ + ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); + + if(ret != HAL_OK) + { + /* set overall return value */ + status = ret; + } + } + } + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + + /*-------------------------- OctoSPIx clock source configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + /* Check the parameters */ + assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection)); + + /* Configure the OctoSPI clock source */ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + + if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) + { + /* Enable PLL48M1CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); + } + } + +#endif /* OCTOSPI1 || OCTOSPI2 */ + return status; } @@ -733,7 +862,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ RCC_PERIPHCLK_RTC ; - + #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ @@ -750,26 +879,61 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ RCC_PERIPHCLK_RTC ; +#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI; + +#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC; + +#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI; + #endif /* STM32L431xx */ /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ - - PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC)); - PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U; - PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)); - PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U; - PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U; - PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U; + + PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; +#else + PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; + PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; + PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; #if defined(RCC_PLLSAI2_SUPPORT) /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; +#else PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; - PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)); - PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U; - PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U; +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; + PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; #endif /* RCC_PLLSAI2_SUPPORT */ @@ -792,7 +956,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the UART5 clock source ----------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); #endif /* UART5 */ - + /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); @@ -853,11 +1017,31 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) #if defined(DFSDM1_Filter0) /* Get the DFSDM1 clock source ---------------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Get the DFSDM1 audio clock source ---------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ + +#if defined(LTDC) + /* Get the LTDC clock source -----------------------------------------------*/ + PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* LTDC */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OctoSPIclock source --------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ } /** - * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs + * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: @@ -881,6 +1065,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) + @endif * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock @@ -892,6 +1079,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) + @endif * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock @if STM32L443xx * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) @@ -907,16 +1097,28 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock @if STM32L462xx * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - @endif + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + @endif @if STM32L486xx * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) @endif @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) + * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) + * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) + @endif * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) @@ -946,7 +1148,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { - frequency = HSE_VALUE / 32; + frequency = HSE_VALUE / 32U; } /* Clock not enabled for RTC*/ else @@ -957,7 +1159,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else { /* Other external peripheral clock source than RTC */ - + /* Compute PLL clock input */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ { @@ -998,8 +1200,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllvco = 0U; } +#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U)); + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif switch(PeriphClk) { @@ -1011,7 +1215,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(PeriphClk == RCC_PERIPHCLK_SAI1) { srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - + if(srcclk == RCC_SAI1CLKSOURCE_PIN) { frequency = EXTERNAL_SAI1_CLOCK_VALUE; @@ -1021,14 +1225,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else /* RCC_PERIPHCLK_SAI2 */ { srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - + if(srcclk == RCC_SAI2CLKSOURCE_PIN) { frequency = EXTERNAL_SAI2_CLOCK_VALUE; } /* Else, PLL clock output to check below */ } - + #else case RCC_PERIPHCLK_SAI1: @@ -1036,14 +1240,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(PeriphClk == RCC_PERIPHCLK_SAI1) { srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); - + if(srcclk == RCC_SAI1CLKSOURCE_PIN) { frequency = EXTERNAL_SAI1_CLOCK_VALUE; } /* Else, PLL clock output to check below */ } - + #endif /* SAI2 */ if(frequency == 0U) @@ -1054,10 +1258,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) { /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN); + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV); -#endif + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) @@ -1076,11 +1280,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV); -#endif + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) @@ -1095,16 +1303,26 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = (pllvco * plln) / pllp; } } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #else if(srcclk == RCC_SAI1CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) { /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN); + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV); -#endif + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) @@ -1116,7 +1334,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - + frequency = (pllvco * plln) / pllp; } else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) @@ -1128,17 +1346,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* No clock source */ frequency = 0U; - } + } } else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) { if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV); -#endif + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) @@ -1150,7 +1372,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - + frequency = (pllvco * plln) / pllp; } else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) @@ -1162,7 +1384,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* No clock source */ frequency = 0U; - } + } } #endif /* SAI2 */ @@ -1172,8 +1394,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#endif /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N); + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) @@ -1198,23 +1427,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } break; - + #if defined(USB_OTG_FS) || defined(USB) - + case RCC_PERIPHCLK_USB: #endif /* USB_OTG_FS || USB */ case RCC_PERIPHCLK_RNG: -#if defined(SDMMC1) +#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) case RCC_PERIPHCLK_SDMMC1: -#endif /* SDMMC1 */ +#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - + if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) @@ -1231,9 +1460,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else { @@ -1244,9 +1477,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); } else { @@ -1269,11 +1506,109 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } #endif /* RCC_HSI48_SUPPORT */ break; - + +#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) + + case RCC_PERIPHCLK_SDMMC1: + + if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + else + { + frequency = 0U; + } + } + else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ + { + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); + + if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + else + { + frequency = 0U; + } + } + else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + } + else + { + frequency = 0U; + } + } + else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif + /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); + } + else + { + frequency = 0U; + } + } + else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ + { + frequency = HSI48_VALUE; + } + else /* No clock source */ + { + frequency = 0U; + } + } + break; + +#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ + case RCC_PERIPHCLK_USART1: /* Get the current USART1 source */ srcclk = __HAL_RCC_GET_USART1_SOURCE(); - + if(srcclk == RCC_USART1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); @@ -1300,7 +1635,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART2: /* Get the current USART2 source */ srcclk = __HAL_RCC_GET_USART2_SOURCE(); - + if(srcclk == RCC_USART2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1329,7 +1664,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART3: /* Get the current USART3 source */ srcclk = __HAL_RCC_GET_USART3_SOURCE(); - + if(srcclk == RCC_USART3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1360,7 +1695,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_UART4: /* Get the current UART4 source */ srcclk = __HAL_RCC_GET_UART4_SOURCE(); - + if(srcclk == RCC_UART4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1391,7 +1726,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_UART5: /* Get the current UART5 source */ srcclk = __HAL_RCC_GET_UART5_SOURCE(); - + if(srcclk == RCC_UART5CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1416,11 +1751,11 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; #endif /* UART5 */ - + case RCC_PERIPHCLK_LPUART1: /* Get the current LPUART1 source */ srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - + if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1445,9 +1780,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; case RCC_PERIPHCLK_ADC: - + srcclk = __HAL_RCC_GET_ADC_SOURCE(); - + if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); @@ -1456,9 +1791,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); } } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) @@ -1466,9 +1805,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#endif /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); } } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ @@ -1484,7 +1827,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_DFSDM1: /* Get the current DFSDM1 source */ srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - + if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); @@ -1495,12 +1838,40 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + + case RCC_PERIPHCLK_DFSDM1AUDIO: + /* Get the current DFSDM1 audio source */ + srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + + if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) + { + frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); + } + else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for DFSDM1 audio source */ + else + { + frequency = 0U; + } + break; + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ case RCC_PERIPHCLK_I2C1: /* Get the current I2C1 source */ srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - + if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1525,7 +1896,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C2: /* Get the current I2C2 source */ srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - + if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1550,7 +1921,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C3: /* Get the current I2C3 source */ srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - + if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1575,7 +1946,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C4: /* Get the current I2C4 source */ srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - + if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1600,7 +1971,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_LPTIM1: /* Get the current LPTIM1 source */ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - + if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1627,7 +1998,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_LPTIM2: /* Get the current LPTIM2 source */ srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - + if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1656,7 +2027,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_SWPMI1: /* Get the current SWPMI1 source */ srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - + if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1674,6 +2045,45 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #endif /* SWPMI1 */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + + case RCC_PERIPHCLK_OSPI: + /* Get the current OctoSPI clock source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); + + if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + else if(srcclk == RCC_OSPICLKSOURCE_PLL) + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + } + else + { + frequency = 0U; + } + } + /* Clock not enabled for OctoSPI */ + else + { + frequency = 0U; + } + break; + +#endif /* OCTOSPI1 || OCTOSPI2 */ + default: break; } @@ -1689,12 +2099,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * -@verbatim +@verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the + This subsection provides a set of functions allowing to control the activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, Low speed clock output and clock after wake-up from STOP mode. @endverbatim @@ -1737,12 +2147,18 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) } } - if(status == HAL_OK) + if(status == HAL_OK) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI1 Multiplication factor N */ + /* Configure the PLLSAI1 Division factors M, P, Q and R */ + __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); +#else /* Configure the PLLSAI1 Multiplication factor N */ /* Configure the PLLSAI1 Division factors P, Q and R */ __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); - /* Configure the PLLSAI1 Clock output(s) */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ @@ -1761,7 +2177,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) } } } - + return status; } @@ -1789,21 +2205,21 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) break; } } - - /* Disable the PLLSAI1 Clock outputs */ + + /* Disable the PLLSAI1 Clock outputs */ __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); /* Reset PLL source to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + return status; } @@ -1825,6 +2241,9 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M)); assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N)); assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P)); +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q)); +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R)); assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut)); @@ -1844,12 +2263,26 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) } } - if(status == HAL_OK) + if(status == HAL_OK) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) + /* Configure the PLLSAI2 Multiplication factor N */ + /* Configure the PLLSAI2 Division factors M, P, Q and R */ + __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); +#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI2 Multiplication factor N */ + /* Configure the PLLSAI2 Division factors M, P and R */ + __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); +#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT) + /* Configure the PLLSAI2 Multiplication factor N */ + /* Configure the PLLSAI2 Division factors P, Q and R */ + __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); +#else /* Configure the PLLSAI2 Multiplication factor N */ /* Configure the PLLSAI2 Division factors P and R */ __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); - /* Configure the PLLSAI2 Clock output(s) */ +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ + /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ @@ -1868,7 +2301,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) } } } - + return status; } @@ -1896,19 +2329,23 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) break; } } - - /* Disable the PLLSAI2 Clock outputs */ + + /* Disable the PLLSAI2 Clock outputs */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); +#else __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN); +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ /* Reset PLL source to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + return status; } @@ -1916,7 +2353,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) /** * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. - * @param WakeUpClk Wakeup clock + * @param WakeUpClk Wakeup clock * This parameter can be one of the following values: * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection @@ -1927,14 +2364,14 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) { assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); - + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); } /** * @brief Configure the MSI range after standby mode. * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param MSIRange MSI range + * @param MSIRange MSI range * This parameter can be one of the following values: * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz @@ -1945,7 +2382,7 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) { assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); - + __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); } @@ -1969,7 +2406,7 @@ void HAL_RCCEx_EnableLSECSS(void) void HAL_RCCEx_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - + /* Disable LSE CSS IT if any */ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } @@ -1986,7 +2423,7 @@ void HAL_RCCEx_EnableLSECSS_IT(void) /* Enable LSE CSS IT */ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); - + /* Enable IT on EXTI Line 19 */ __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); @@ -2007,7 +2444,7 @@ void HAL_RCCEx_LSECSS_IRQHandler(void) /* Clear RCC LSE CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); } -} +} /** * @brief RCCEx LSE Clock Security System interrupt callback. @@ -2033,7 +2470,7 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) GPIO_InitTypeDef GPIO_InitStruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; - + /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); @@ -2058,9 +2495,9 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } - + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - + if(backupchanged == SET) { HAL_PWR_DisableBkUpAccess(); @@ -2079,7 +2516,7 @@ void HAL_RCCEx_DisableLSCO(void) { FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; - + /* Update LSCOEN bit in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -2092,9 +2529,9 @@ void HAL_RCCEx_DisableLSCO(void) HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } - + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); - + /* Restore previous configuration */ if(backupchanged == SET) { @@ -2134,7 +2571,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) #if defined(CRS) -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions * @verbatim @@ -2152,11 +2589,11 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (##) Prepare synchronization configuration necessary for HSI48 calibration (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. - (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate directly reload value with target and sychronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. - (+++) Configures CRS registers with synchronization configuration + (+++) Configures CRS registers with synchronization configuration (+++) Enables automatic calibration and frequency error counter feature Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be @@ -2168,23 +2605,23 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (+++) Call function HAL_RCCEx_CRSWaitSynchronization() (+++) According to CRS status, user can decide to adjust again the calibration or continue application if synchronization is OK - + (#) User can retrieve information related to synchronization in calling function HAL_RCCEx_CRSGetSynchronizationInfo() (#) Regarding synchronization status and synchronization information, user can try a new calibration in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler (CRS_IRQn/CRS_IRQHandler) (++) Call function HAL_RCCEx_CRSConfig() (++) Enable CRS_IRQn (thanks to NVIC functions) (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from + (++) Implement CRS status management in the following user callbacks called from HAL_RCCEx_CRS_IRQHandler(): (+++) HAL_RCCEx_CRS_SyncOkCallback() (+++) HAL_RCCEx_CRS_SyncWarnCallback() @@ -2193,7 +2630,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) - + @endverbatim * @{ */ @@ -2206,7 +2643,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { uint32_t value = 0; - + /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); @@ -2228,15 +2665,15 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) /* Set the RELOAD[15:0] bits according to ReloadValue value */ value |= pInit->ReloadValue; /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM)); + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM))); - + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + /* START AUTOMATIC SYNCHRONIZATION*/ - + /* Enable Automatic trimming & Frequency error counter */ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); } @@ -2251,7 +2688,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) } /** - * @brief Return synchronization info + * @brief Return synchronization info * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure * @retval None */ @@ -2259,18 +2696,18 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo { /* Check the parameter */ assert_param(pSynchroInfo != NULL); - + /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - + pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM)); + pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP)); + pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); + pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); } /** @@ -2292,10 +2729,10 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart = 0U; - + /* Get timeout */ tickstart = HAL_GetTick(); - + /* Wait for CRS flag or timeout detection */ do { @@ -2311,51 +2748,51 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { /* CRS SYNC event OK */ crsstatus |= RCC_CRS_SYNCOK; - + /* Clear CRS SYNC event OK bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); } - + /* Check CRS SYNCWARN flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ crsstatus |= RCC_CRS_SYNCWARN; - + /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); } - + /* Check CRS TRIM overflow flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_TRIMOVF; - + /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); } - + /* Check CRS Error flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_SYNCERR; - + /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); } - + /* Check CRS SYNC Missed flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) { /* CRS SYNC Missed */ crsstatus |= RCC_CRS_SYNCMISS; - + /* Clear CRS SYNC Missed bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); } - + /* Check CRS Expected SYNC flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) { @@ -2425,7 +2862,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) /* Clear CRS Error flags */ WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - + /* user error callback */ HAL_RCCEx_CRS_ErrorCallback(crserror); } @@ -2467,7 +2904,7 @@ __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) /** * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. + * @param Error Combination of Error status. * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS @@ -2487,7 +2924,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) /** * @} */ - + #endif /* CRS */ /** @@ -2519,16 +2956,18 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); - + /* Check that PLLSAI1 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { - /* PLL clock source and divider M already set, check that no request for change */ + /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) - || + || (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M) +#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + || + (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) +#endif ) { status = HAL_ERROR; @@ -2561,14 +3000,19 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u status = HAL_ERROR; break; } - + if(status == HAL_OK) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Set PLLSAI1 clock source */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); +#else /* Set PLLSAI1 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM)); + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); +#endif } } - + if(status == HAL_OK) { /* Disable the PLLSAI1 */ @@ -2587,41 +3031,79 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } } - if(status == HAL_OK) + if(status == HAL_OK) { if(Divider == DIVIDER_P_UPDATE) { assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + + /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#else /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - (PllSai1->PLLSAI1P << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); #else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } else if(Divider == DIVIDER_Q_UPDATE) { assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } else { assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ @@ -2640,14 +3122,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } } - if(status == HAL_OK) + if(status == HAL_OK) { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); } } } - + return status; } @@ -2674,16 +3156,18 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); - + /* Check that PLLSAI2 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { - /* PLL clock source and divider M already set, check that no request for change */ + /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) - || + || (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai2->PLLSAI2M) +#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + || + (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) +#endif ) { status = HAL_ERROR; @@ -2716,14 +3200,19 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u status = HAL_ERROR; break; } - + if(status == HAL_OK) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Set PLLSAI2 clock source */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); +#else /* Set PLLSAI2 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM)); + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); +#endif } } - + if(status == HAL_OK) { /* Disable the PLLSAI2 */ @@ -2742,25 +3231,81 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } } - if(status == HAL_OK) + if(status == HAL_OK) { if(Divider == DIVIDER_P_UPDATE) { assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P)); +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + + /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#else + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#else /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, - (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | - ((PllSai2->PLLSAI2P >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))); +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); +#else + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + else if(Divider == DIVIDER_Q_UPDATE) + { + assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#else + /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + } +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ else { assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#else /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, - (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | - (((PllSai2->PLLSAI2R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))); + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ @@ -2779,14 +3324,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } } - if(status == HAL_OK) + if(status == HAL_OK) { /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); } } } - + return status; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h index deb2b1c9299..b0000a7abee 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RCC HAL Extended module. ****************************************************************************** * @attention @@ -54,7 +52,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ @@ -69,8 +67,13 @@ typedef struct uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ +#else uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ +#endif uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices. */ @@ -99,8 +102,13 @@ typedef struct uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ +#else uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ +#endif uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices. */ @@ -108,6 +116,11 @@ typedef struct uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. + This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ +#endif + uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ @@ -177,7 +190,7 @@ typedef struct uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - + #if defined(I2C4) uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. @@ -233,16 +246,43 @@ typedef struct uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. + This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + + uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. + This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ + +#endif /* LTDC */ + +#if defined(DSI) + + uint32_t DsiClockSelection; /*!< Specifies DSI clock source. + This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + + uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. + This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ + +#endif + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #if defined(CRS) -/** - * @brief RCC_CRS Init structure definition +/** + * @brief RCC_CRS Init structure definition */ typedef struct { @@ -267,8 +307,8 @@ typedef struct }RCC_CRSInitTypeDef; -/** - * @brief RCC_CRS Synchronization structure definition +/** + * @brief RCC_CRS Synchronization structure definition */ typedef struct { @@ -278,12 +318,12 @@ typedef struct uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x3F */ - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF */ - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ @@ -302,8 +342,8 @@ typedef struct /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source * @{ */ -#define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */ -#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ /** * @} */ @@ -311,46 +351,58 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) +#define RCC_PERIPHCLK_USART1 0x00000001U +#define RCC_PERIPHCLK_USART2 0x00000002U #if defined(USART3) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U) +#define RCC_PERIPHCLK_USART3 0x00000004U #endif #if defined(UART4) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U) +#define RCC_PERIPHCLK_UART4 0x00000008U #endif #if defined(UART5) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_UART5 0x00000010U #endif -#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_LPUART1 0x00000020U +#define RCC_PERIPHCLK_I2C1 0x00000040U #if defined(I2C2) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_I2C2 0x00000080U #endif -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U) -#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_I2C3 0x00000100U +#define RCC_PERIPHCLK_LPTIM1 0x00000200U +#define RCC_PERIPHCLK_LPTIM2 0x00000400U +#define RCC_PERIPHCLK_SAI1 0x00000800U #if defined(SAI2) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_SAI2 0x00001000U #endif #if defined(USB_OTG_FS) || defined(USB) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_USB 0x00002000U #endif -#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_ADC 0x00004000U #if defined(SWPMI1) -#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_SWPMI1 0x00008000U #endif #if defined(DFSDM1_Filter0) -#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_DFSDM1 0x00010000U +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U) -#define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_RTC 0x00020000U +#define RCC_PERIPHCLK_RNG 0x00040000U #if defined(SDMMC1) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SDMMC1 0x00080000U #endif #if defined(I2C4) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_I2C4 0x00100000U +#endif +#if defined(LTDC) +#define RCC_PERIPHCLK_LTDC 0x00400000U +#endif +#if defined(DSI) +#define RCC_PERIPHCLK_DSI 0x00800000U +#endif +#if defined(OCTOSPI1) || defined(OCTOSPI2) +#define RCC_PERIPHCLK_OSPI 0x01000000U #endif /** * @} @@ -360,7 +412,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) @@ -371,7 +423,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) @@ -383,7 +435,7 @@ typedef struct /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source * @{ */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) @@ -396,7 +448,7 @@ typedef struct /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source * @{ */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) @@ -409,7 +461,7 @@ typedef struct /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source * @{ */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) @@ -421,7 +473,7 @@ typedef struct /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source * @{ */ -#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) @@ -432,7 +484,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /** @@ -443,7 +495,7 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source * @{ */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /** @@ -454,34 +506,44 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 /** * @} */ - + #if defined(I2C4) /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source * @{ */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /** * @} */ -#endif /* I2C4 */ +#endif /* I2C4 */ /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) +#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 +#else #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 +#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) +#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 +#else #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -490,10 +552,17 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) +#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 +#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 +#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) +#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 +#else #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -502,7 +571,7 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL @@ -513,7 +582,7 @@ typedef struct /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source * @{ */ -#define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL @@ -526,13 +595,16 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ #else -#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ #endif /* RCC_HSI48_SUPPORT */ -#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL +#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ +#if defined(RCC_CCIPR2_SDMMCSEL) +#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ +#endif /* RCC_CCIPR2_SDMMCSEL */ /** * @} */ @@ -542,9 +614,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_RNGCLKSOURCE_HSI48 0x00000000U #else -#define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_RNGCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 @@ -558,9 +630,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_USBCLKSOURCE_HSI48 0x00000000U #else -#define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_USBCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 @@ -573,7 +645,7 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ -#define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_ADCCLKSOURCE_NONE 0x00000000U #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 @@ -587,7 +659,7 @@ typedef struct /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source * @{ */ -#define RCC_SWPMI1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /** * @} @@ -598,13 +670,65 @@ typedef struct /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source * @{ */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL +#else #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/** + * @} + */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U +#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 +#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /** * @} */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source + * @{ + */ +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR +/** + * @} + */ +#endif /* LTDC */ + +#if defined(DSI) +/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U +#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL +/** + * @} + */ +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source + * @{ + */ +#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U +#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 +#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 +/** + * @} + */ +#endif /* OCTOSPI1 || OCTOSPI2 */ + /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ @@ -618,13 +742,13 @@ typedef struct /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ -#define RCC_CRS_NONE ((uint32_t)0x00000000U) -#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) -#define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) -#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) -#define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) -#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) -#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U /** * @} */ @@ -632,7 +756,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -642,7 +766,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -657,8 +781,8 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} */ @@ -666,16 +790,16 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} */ - + /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ /** * @} */ @@ -683,9 +807,9 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ + corresponds to a higher output frequency */ /** * @} */ @@ -693,8 +817,8 @@ typedef struct /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ /** * @} */ @@ -713,7 +837,7 @@ typedef struct /** * @} */ - + /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags * @{ */ @@ -748,6 +872,11 @@ typedef struct * @note PLLSAI1 clock source is common with the main PLL (configured through * __HAL_RCC_PLL_CONFIG() macro) * + @if STM32L4S9xx + * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + @endif * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO @@ -769,24 +898,50 @@ typedef struct * * @retval None */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + +#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ + (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) + +#else + +#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) + +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#else + #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \ - ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))) + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) #else #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \ - (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))) - + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) + #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /** * @brief Macro to configure the PLLSAI1 clock multiplication factor N. * @@ -803,7 +958,26 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + +/** @brief Macro to configure the PLLSAI1 input clock division factor M. + * + * @note This function must be used only when the PLLSAI1 is disabled. + * @note PLLSAI1 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL_CONFIG() macro) + * + * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + * @retval None + */ + +#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ /** @brief Macro to configure the PLLSAI1 clock division factor P. * @@ -821,12 +995,12 @@ typedef struct #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)) - + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) + #else #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ @@ -843,7 +1017,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /** @brief Macro to configure the PLLSAI1 clock division factor R. * @@ -858,7 +1032,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /** * @brief Macros to enable or disable the PLLSAI1. @@ -910,6 +1084,11 @@ typedef struct * @note PLLSAI2 clock source is common with the main PLL (configured through * __HAL_RCC_PLL_CONFIG() macro) * + @if STM32L4S9xx + * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + @endif * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO @@ -920,27 +1099,74 @@ typedef struct * else (2 to 31). * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P * + @if STM32L4S9xx + * @param __PLLSAI2Q__ specifies the division factor for DSI clock. + * This parameter must be in the range (2, 4, 6 or 8). + * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q + * + @endif * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. * This parameter must be in the range (2, 4, 6 or 8). * * @retval None */ -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \ - ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV))) +# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + +# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + +# else + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + +# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ #else +# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \ - (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))) - -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +# else + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) + +# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ + +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ /** @@ -959,7 +1185,26 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + +/** @brief Macro to configure the PLLSAI2 input clock division factor M. + * + * @note This function must be used only when the PLLSAI2 is disabled. + * @note PLLSAI2 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL_CONFIG() macro) + * + * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + * @retval None + */ + +#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ /** @brief Macro to configure the PLLSAI2 clock division factor P. * @@ -974,7 +1219,26 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + +/** @brief Macro to configure the PLLSAI2 clock division factor Q. + * + * @note This function must be used only when the PLLSAI2 is disabled. + * @note PLLSAI2 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL_CONFIG() macro) + * + * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. + * This parameter must be in the range (2, 4, 6 or 8). + * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q + * + * @retval None + */ +#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ /** @brief Macro to configure the PLLSAI2 clock division factor R. * @@ -989,7 +1253,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /** * @brief Macros to enable or disable the PLLSAI2. @@ -1002,14 +1266,26 @@ typedef struct #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) /** - * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2). + * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). * @note Enabling and disabling those clocks can be done without the need to stop the PLL. * This is mainly used to save Power. * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. * This parameter can be one or a combination of the following values: + @if STM32L486xx * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4A6xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4S9xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. + @endif * @retval None */ @@ -1018,12 +1294,24 @@ typedef struct #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) /** - * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2). + * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. * This parameter can be one of the following values: + @if STM32L486xx * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4A6xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4S9xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. + @endif * @retval SET / RESET */ #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) @@ -1039,23 +1327,25 @@ typedef struct @if STM32L486xx * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 @endif - @if STM32L4A6xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) + @if STM32L4S9xx + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 + @endif * @if STM32L443xx * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. @endif - @if STM32L462xx - * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. - @endif * * @retval None */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) +#else +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: @@ -1063,17 +1353,18 @@ typedef struct @if STM32L486xx * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 @endif - @if STM32L4A6xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) * - * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 + * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 * clock source when PLLs are disabled for devices without PLLSAI2. * */ -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) +#else +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined(SAI2) @@ -1086,11 +1377,19 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) + @if STM32L4S9xx + * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 + @endif * * @retval None */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) +#else +#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the SAI2 clock source. * @retval The clock source can be one of the following values: @@ -1099,7 +1398,11 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) */ -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) +#else +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* SAI2 */ @@ -1113,7 +1416,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: @@ -1121,7 +1424,7 @@ typedef struct * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) +#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) #if defined(I2C2) @@ -1135,7 +1438,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: @@ -1143,7 +1446,7 @@ typedef struct * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) +#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) #endif /* I2C2 */ @@ -1157,7 +1460,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: @@ -1165,7 +1468,7 @@ typedef struct * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) +#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) #if defined(I2C4) @@ -1179,7 +1482,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) /** @brief Macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: @@ -1187,7 +1490,7 @@ typedef struct * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock */ -#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))) +#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) #endif /* I2C4 */ @@ -1203,7 +1506,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @@ -1212,7 +1515,7 @@ typedef struct * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) +#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) /** @brief Macro to configure the USART2 clock (USART2CLK). * @@ -1225,7 +1528,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: @@ -1234,7 +1537,7 @@ typedef struct * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) +#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) #if defined(USART3) @@ -1249,7 +1552,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: @@ -1258,7 +1561,7 @@ typedef struct * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) +#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) #endif /* USART3 */ @@ -1275,7 +1578,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: @@ -1284,7 +1587,7 @@ typedef struct * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))) +#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) #endif /* UART4 */ @@ -1301,7 +1604,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: @@ -1310,7 +1613,7 @@ typedef struct * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))) +#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) #endif /* UART5 */ @@ -1325,7 +1628,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: @@ -1334,7 +1637,7 @@ typedef struct * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) +#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * @@ -1347,7 +1650,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: @@ -1356,7 +1659,7 @@ typedef struct * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). * @@ -1369,7 +1672,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) /** @brief Macro to get the LPTIM2 clock source. * @retval The clock source can be one of the following values: @@ -1378,84 +1681,87 @@ typedef struct * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) +#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) #if defined(SDMMC1) /** @brief Macro to configure the SDMMC1 clock. * - @if STM32L443xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif - @if STM32L462xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif @if STM32L486xx * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. @endif - @if STM32L4A6xx + * + @if STM32L443xx * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. @endif * * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. * This parameter can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 + @if STM32L486xx + * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock @endif - @if STM32L462xx + @if STM32L443xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock - @endif - @if STM32L486xx - * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock @endif - @if STM32L4A6xx + @if STM32L4S9xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock @endif + * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock * @retval None */ +#if defined(RCC_CCIPR2_SDMMCSEL) +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + do \ + { \ + if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ + { \ + SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ + } \ + } while(0) +#else #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) +#endif /* RCC_CCIPR2_SDMMCSEL */ /** @brief Macro to get the SDMMC1 clock. * @retval The clock source can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 + @if STM32L486xx + * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock @endif - @if STM32L462xx + @if STM32L443xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock - @endif - @if STM32L486xx - * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock @endif - @if STM32L4A6xx + @if STM32L4S9xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock @endif + * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock */ -#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#if defined(RCC_CCIPR2_SDMMCSEL) +#define __HAL_RCC_GET_SDMMC1_SOURCE() \ + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#else +#define __HAL_RCC_GET_SDMMC1_SOURCE() \ + (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) +#endif /* RCC_CCIPR2_SDMMCSEL */ #endif /* SDMMC1 */ @@ -1465,16 +1771,10 @@ typedef struct * * @param __RNG_CLKSOURCE__ specifies the RNG clock source. * This parameter can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 @endif * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock @@ -1483,27 +1783,21 @@ typedef struct * @retval None */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 @endif * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock */ -#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #if defined(USB_OTG_FS) || defined(USB) @@ -1513,16 +1807,10 @@ typedef struct * * @param __USB_CLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 @endif * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock @@ -1531,27 +1819,21 @@ typedef struct * @retval None */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 @endif * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #endif /* USB_OTG_FS || USB */ @@ -1563,14 +1845,11 @@ typedef struct @if STM32L486xx * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices @endif - @if STM32L4A6xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock * @retval None */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: @@ -1579,12 +1858,9 @@ typedef struct @if STM32L486xx * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices @endif - @if STM32L4A6xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock */ -#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) +#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) #if defined(SWPMI1) @@ -1596,14 +1872,14 @@ typedef struct * @retval None */ #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) /** @brief Macro to get the SWPMI1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock */ -#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))) +#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) #endif /* SWPMI1 */ @@ -1615,18 +1891,119 @@ typedef struct * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock * @retval None */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) +#else #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the DFSDM1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock */ -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) +#else +#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @brief Macro to configure the DFSDM1 audio clock. + * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock + * @retval None + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 audio clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + +/** @brief Macro to configure the LTDC clock. + * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock + * @retval None + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) + +#endif /* LTDC */ + +#if defined(DSI) + +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock + * @retval None + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) + +/** @brief Macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + +/** @brief Macro to configure the OctoSPI clock. + * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock + * @retval None + */ +#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) + +/** @brief Macro to get the OctoSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock + */ +#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) + +#endif /* OCTOSPI1 || OCTOSPI2 */ + /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ @@ -1746,8 +2123,8 @@ typedef struct do { \ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - + } while(0) + /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. @@ -1756,7 +2133,7 @@ typedef struct do { \ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0) /** * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. @@ -1826,7 +2203,7 @@ typedef struct * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ /* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ @@ -1870,7 +2247,7 @@ typedef struct */ /* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ @@ -1893,7 +2270,7 @@ typedef struct /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features * @{ - */ + */ /** * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. @@ -1922,8 +2299,8 @@ typedef struct /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to * reach the expected synchronization on the zero value. The formula is the following: * RELOAD = (fTARGET / fSYNC) -1 * @param __FTARGET__ Target frequency (value in Hz) @@ -2170,6 +2547,87 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) +#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) + +#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) + +#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) + #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ @@ -2262,7 +2720,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) - + #if defined(I2C4) #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ @@ -2274,11 +2732,20 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) +#else #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #else @@ -2291,35 +2758,52 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) +#else #define IS_RCC_SAI2CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* RCC_PLLSAI2_SUPPORT */ #define IS_RCC_LPTIM1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) #define IS_RCC_LPTIM2CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) #if defined(SDMMC1) -#if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) +#elif defined(RCC_HSI48_SUPPORT) + +#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) #else #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ @@ -2400,11 +2884,51 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) + +#endif /* LTDC */ + +#if defined(DSI) + +#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + +#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) + +#endif /* OCTOSPI1 || OCTOSPI2 */ + #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) +#else #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -2424,7 +2948,11 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) +#else #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -2434,6 +2962,11 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ + ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) @@ -2452,7 +2985,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) - + #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c index 9d94bf14803..469c6af21d8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -122,11 +120,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { return HAL_ERROR; } - - assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); - - __HAL_LOCK(hrng); - + + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); +#if defined(RNG_CR_CED) + assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); +#endif /* defined(RNG_CR_CED) */ + if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -135,18 +134,21 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } - + /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; +#if defined(RNG_CR_CED) + /* Clock Error Detection configuration */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); +#endif /* defined(RNG_CR_CED) */ + /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; - __HAL_UNLOCK(hrng); - /* Return function status */ return HAL_OK; } @@ -163,21 +165,27 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) { return HAL_ERROR; } + +#if defined(RNG_CR_CED) + /* Clear Clock Error Detection bit */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED); +#endif /* defined(RNG_CR_CED) */ + /* Disable the RNG Peripheral */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - + /* Clear RNG interrupt status flags */ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); - + /* DeInit the low level hardware */ HAL_RNG_MspDeInit(hrng); - + /* Update the RNG state */ hrng->State = HAL_RNG_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hrng); - + /* Return the function status */ return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h index 53fcd334e08..4eedd1bb245 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -59,6 +57,16 @@ * @{ */ +#if defined(RNG_CR_CED) +/** + * @brief RNG Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection */ +}RNG_InitTypeDef; +#endif /* defined(RNG_CR_CED) */ + /** * @brief RNG HAL State Structure definition */ @@ -69,7 +77,7 @@ typedef enum HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ - + }HAL_RNG_StateTypeDef; /** @@ -77,14 +85,18 @@ typedef enum */ typedef struct { - RNG_TypeDef *Instance; /*!< Register base address */ - - HAL_LockTypeDef Lock; /*!< RNG locking object */ - - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - + RNG_TypeDef *Instance; /*!< Register base address */ + +#if defined(RNG_CR_CED) + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ +#endif /* defined(RNG_CR_CED) */ + + HAL_LockTypeDef Lock; /*!< RNG locking object */ + + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + uint32_t RandomNumber; /*!< Last Generated RNG Data */ - + }RNG_HandleTypeDef; /** @@ -116,6 +128,17 @@ typedef struct * @} */ +#if defined(RNG_CR_CED) +/** @defgroup RNG_Clock_Error_Detection RNG Clock Error Detection + * @{ + */ +#define RNG_CED_ENABLE ((uint32_t)0x00000000) /*!< Clock error detection enabled */ +#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +#endif /* defined(RNG_CR_CED) */ + /** * @} */ @@ -176,7 +199,7 @@ typedef struct * @retval None */ #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) - + /** * @brief Disable the RNG interrupt. * @param __HANDLE__: RNG Handle @@ -266,6 +289,23 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @addtogroup RNG_Private_Macros RNG Private Macros + * @{ + */ + +#if defined(RNG_CR_CED) +/** + * @brief Verify the RNG Clock Error Detection mode. + * @param __MODE__: RNG Clock Error Detection mode + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ + ((__MODE__) == RNG_CED_DISABLE)) +#endif /* defined(RNG_CR_CED) */ + +/** + * @} + */ /* Private functions prototypes ----------------------------------------------*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c index 636adf26920..73ffaf2f118 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h index be41b872af9..ed269a98ca6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -268,8 +266,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x00000000) +#define RTC_FORMAT_BCD ((uint32_t)0x00000001) /** * @} */ @@ -718,10 +716,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_TR_RESERVED_MASK 0x007F7F7FU +#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU #define RTC_TIMEOUT_VALUE 1000 diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c index 0f334cd37cf..31a6fe7de19 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h index df4c98ce7c9..102703f1e96 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c index 160fd53c8cc..02f941c9707 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sai.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: @@ -73,6 +71,11 @@ (+@) Number of SLOT x SLOT size = Frame length (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. + [..] + (@) For STM32L4Rx/STM32L4Sx devices, PDM interface can be activated through HAL_SAI_Init function. + Please note that PDM interface is only available for SAI1 sub-block A. + PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function. + [..] Three operation modes are available within this driver : @@ -200,7 +203,6 @@ typedef enum { #define SAI_FIFO_SIZE 8 #define SAI_DEFAULT_TIMEOUT 4 #define SAI_LONG_TIMEOUT 1000 -#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT) /** * @} @@ -265,6 +267,7 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); (++) FIFO Threshold (++) Frame Config (++) Slot Config + (++) PDM Config (only for STM32L4Rx/STM32L4Sx devices) (+) Call the function HAL_SAI_DeInit() to restore the default configuration of the selected SAI peripheral. @@ -277,12 +280,12 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * @brief Initialize the structure FrameInit, SlotInit and the low part of * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol @ref SAI_Protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: Number of slot. + * @param nbslot Number of slot. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -320,7 +323,7 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco /** * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -354,6 +357,9 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Check the SAI Block Frame parameters */ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); @@ -368,6 +374,23 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Check the SAI PDM parameters */ + assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation)); + if(hsai->Init.PdmInit.Activation == ENABLE) + { + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr)); + assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable)); + /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */ + if((hsai->Instance != SAI1_Block_A) || + (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || + (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) + { + return HAL_ERROR; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + if(hsai->State == HAL_SAI_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -423,7 +446,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { @@ -439,7 +463,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) SAI1->GCR = tmpregisterGCR; #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { @@ -448,7 +473,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /* In this case, the MCKDIV value is calculated to get AudioFrequency */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) { @@ -464,8 +490,35 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure Master Clock Divider using the following formula : + - If NOMCK = 1 : + MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1)) + - If NOMCK = 0 : + MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */ + if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) + { /* NOMCK = 1 */ + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); + } + else + { /* NOMCK = 0 */ + uint32_t tmposr; + tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2 : 1; + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256); + } + hsai->Init.Mckdiv = tmpval / 10; + /* Round result to the nearest integer */ + if((tmpval % 10) > 8) + { + hsai->Init.Mckdiv+= 1; + } +#else /* Configure Master Clock using the following formula : MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 @@ -479,6 +532,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { hsai->Init.Mckdiv+= 1; } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ @@ -493,6 +547,19 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /* SAI Block Configuration -------------------------------------------------*/ /* SAI CR1 Configuration */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR); + + hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ + hsai->Init.MckOverSampling); +#else hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ @@ -503,6 +570,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) ckstr_bits | syncen_bits | \ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI CR2 Configuration */ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); @@ -525,6 +593,22 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* SAI PDM Configuration ---------------------------------------------------*/ + if(hsai->Instance == SAI1_Block_A) + { + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + if(hsai->Init.PdmInit.Activation == ENABLE) + { + /* Configure and enable PDM interface */ + SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | + ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_Pos)); + SAI1->PDMCR |= SAI_PDMCR_PDMEN; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; @@ -539,7 +623,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI peripheral. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -563,6 +647,18 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Disable SAI PDM interface */ + if(hsai->Instance == SAI1_Block_A) + { + /* Reset PDM delays */ + SAI1->PDMDLY = 0U; + + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_SAI_MspDeInit(hsai); @@ -580,7 +676,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -596,7 +692,7 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -638,17 +734,14 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) (+) Blocking mode functions are : (++) HAL_SAI_Transmit() (++) HAL_SAI_Receive() - (++) HAL_SAI_TransmitReceive() (+) Non Blocking mode functions with Interrupt are : (++) HAL_SAI_Transmit_IT() (++) HAL_SAI_Receive_IT() - (++) HAL_SAI_TransmitReceive_IT() (+) Non Blocking mode functions with DMA are : (++) HAL_SAI_Transmit_DMA() (++) HAL_SAI_Receive_DMA() - (++) HAL_SAI_TransmitReceive_DMA() (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SAI_TxCpltCallback() @@ -661,11 +754,11 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) @@ -761,11 +854,11 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -859,10 +952,10 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -921,10 +1014,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -981,7 +1074,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1001,7 +1094,7 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) /** * @brief Resume the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1028,7 +1121,7 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) /** * @brief Stop the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1060,6 +1153,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Disable SAI peripheral */ SAI_Disable(hsai); + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + hsai->State = HAL_SAI_STATE_READY; /* Process Unlocked */ @@ -1070,7 +1166,7 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /** * @brief Abort the current transfer and disable the SAI. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1123,10 +1219,10 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1210,10 +1306,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1280,9 +1376,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param val: value sent during the mute @ref SAI_Block_Mute_Value + * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) @@ -1300,7 +1396,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1316,10 +1412,10 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param callback: function called when the mute is detected. - * @param counter: number a data before mute detection max 63. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) @@ -1330,7 +1426,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback { /* set the mute counter */ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); - SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET)); + SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos)); hsai->mutecallback = callback; /* enable the IT interrupt */ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); @@ -1341,7 +1437,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1360,7 +1456,7 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1536,7 +1632,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1552,7 +1648,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1568,7 +1664,7 @@ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1584,7 +1680,7 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1600,7 +1696,7 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1636,7 +1732,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL state */ @@ -1647,7 +1743,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI error code. -* @param hsai: pointer to a SAI_HandleTypeDef structure that contains +* @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. * @retval SAI Error Code */ @@ -1671,12 +1767,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol. - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: number of slot minimum value is 2 and max is 16. + * @param nbslot number of slot minimum value is 2 and max is 16. * the value must be a multiple of 2. * @retval HAL status */ @@ -1766,11 +1862,11 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot: number of slot minimum value is 1 and the max is 16. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -1836,7 +1932,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Fill the fifo. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1865,9 +1961,9 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param mode: SAI_MODE_DMA or SAI_MODE_IT + * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) @@ -1899,7 +1995,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1925,7 +2021,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1949,7 +2045,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1974,7 +2070,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1999,7 +2095,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2025,7 +2121,7 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2051,7 +2147,7 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) } /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2078,7 +2174,7 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief DMA SAI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2103,7 +2199,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI transmit process half complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2116,7 +2212,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2139,7 +2235,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2151,7 +2247,7 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** * @brief DMA SAI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2180,7 +2276,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI Abort callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h index 383d35fadf8..1c956e73487 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sai.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -76,6 +74,20 @@ typedef enum */ typedef void (*SAIcallback)(void); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief SAI PDM Init structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Enable/disable PDM interface */ + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + uint32_t ClockEnable; /*!< Specifies which clock must be enabled. + This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ +}SAI_PdmInitTypeDef; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition * @brief SAI Init Structure definition * @{ @@ -101,7 +113,14 @@ typedef struct uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. This parameter can be a value of @ref SAI_Block_NoDivider - @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length + @note: For STM32L4Rx/STM32L4Sx devices : + If bit NOMCK in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NOMCK in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint. There is no MCLK_x clock + which can be output. + For other devices : + If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values without constraint since the input clock of @@ -116,7 +135,13 @@ typedef struct uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for AudioFrequency the user choice - This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 63 on STM32L4Rx/STM32L4Sx devices. + This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. + This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ @@ -127,6 +152,10 @@ typedef struct uint32_t TriState; /*!< Specifies the companding mode type. This parameter can be a value of @ref SAI_TRIState_Management */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* This part of the structure is automatically filled if your are using the high level initialisation function HAL_SAI_InitProtocol */ @@ -314,6 +343,26 @@ typedef struct __SAI_HandleTypeDef * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling + * @{ + */ +#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U) +#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR) +/** + * @} + */ + +/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable + * @{ + */ +#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1) +#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2) +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SAI_Block_Mode SAI Block Mode * @{ */ @@ -391,7 +440,11 @@ typedef struct __SAI_HandleTypeDef * @{ */ #define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK) +#else #define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -564,14 +617,14 @@ typedef struct __SAI_HandleTypeDef */ /** @brief Reset SAI handle state. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -586,8 +639,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -601,8 +654,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -616,8 +669,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection @@ -638,6 +691,11 @@ typedef struct __SAI_HandleTypeDef * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include SAI HAL Extension module */ +#include "stm32l4xx_hal_sai_ex.h" +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SAI_Exported_Functions @@ -738,6 +796,16 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ + ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) + +#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) + +#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ + (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ ((MODE) == SAI_MODEMASTER_RX) || \ ((MODE) == SAI_MODESLAVE_TX) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c new file mode 100644 index 00000000000..44bd907dc53 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sai_ex.c + * @author MCD Application Team + * @brief SAI Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the SAI Peripheral Controller: + * + Modify PDM microphone delays. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ +#ifdef HAL_SAI_MODULE_ENABLED +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @defgroup SAIEx SAIEx + * @brief SAI Extended HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_OFFSET 8U +#define SAI_PDM_RIGHT_DELAY_OFFSET 4U + +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @brief SAIEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Modify PDM microphone delays + +@endverbatim + * @{ + */ + +/** + * @brief Configure PDM microphone delays. + * @param hsai SAI handle. + * @param pdmMicDelay Microphone delays configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that SAI sub-block is SAI1 sub-block A */ + if(hsai->Instance != SAI1_Block_A) + { + status = HAL_ERROR; + } + else + { + /* Check microphone delay parameters */ + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay)); + + /* Check SAI state */ + if(hsai->State != HAL_SAI_STATE_RESET) + { + /* Reset current delays for specified microphone */ + SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); + + /* Apply new microphone delays */ + SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \ + (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* HAL_SAI_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h new file mode 100644 index 00000000000..3a3828dad1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h @@ -0,0 +1,132 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sai_ex.h + * @author MCD Application Team + * @brief Header file of SAI HAL extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_SAI_EX_H +#define __STM32L4xx_HAL_SAI_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SAIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup SAIEx_Exported_Types SAIEx Exported Types + * @{ + */ + +/** + * @brief PDM microphone delay structure definition + */ +typedef struct +{ + uint32_t MicPair; /*!< Specifies which pair of microphones is selected. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + + uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ + + uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ +}SAIEx_PdmMicDelayParamTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ + +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros + * @{ + */ + +#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_SAI_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c index 5ea713557ec..d76c7386a1d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -37,7 +35,8 @@ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; - (##) Perform DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + (##) On STM32L4Rx/STM32L4Sxx devices, no DMA configuration is need, an internal DMA for SDMMC IP is used. + (##) On other devices, perform DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() and HAL_SD_WriteBlocks_DMA() APIs). (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. @@ -233,9 +232,10 @@ * @{ */ -/** @addtogroup SD +/** @defgroup SD SD + * @brief SD HAL module driver * @{ - */ + */ #ifdef HAL_SD_MODULE_ENABLED @@ -266,11 +266,13 @@ static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSC static HAL_StatusTypeDef SD_PowerOFF (SD_HandleTypeDef *hsd); static HAL_StatusTypeDef SD_Write_IT (SD_HandleTypeDef *hsd); static HAL_StatusTypeDef SD_Read_IT (SD_HandleTypeDef *hsd); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SD_DMAReceiveCplt (DMA_HandleTypeDef *hdma); static void SD_DMAError (DMA_HandleTypeDef *hdma); static void SD_DMATxAbort (DMA_HandleTypeDef *hdma); static void SD_DMARxAbort (DMA_HandleTypeDef *hdma); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @} */ @@ -312,7 +314,9 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); @@ -334,6 +338,28 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) return HAL_ERROR; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the bus wide */ + if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= 0x00100000; + /* Enable High Speed */ + if(HAL_SDEx_HighSpeed(hsd) != HAL_OK) + { + return HAL_ERROR; + } + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; @@ -361,12 +387,22 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; Init.BusWide = SDMMC_BUS_WIDE_1B; Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; Init.ClockDiv = SDMMC_INIT_CLK_DIV; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Initialize SDMMC peripheral interface with default configuration */ status = SDMMC_Init(hsd->Instance, Init); if(status != HAL_OK) @@ -374,8 +410,10 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Disable SDMMC Clock */ __HAL_SD_DISABLE(hsd); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* Set Power State to ON */ status = SDMMC_PowerState_ON(hsd->Instance); @@ -384,9 +422,11 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Enable SDMMC Clock */ __HAL_SD_ENABLE(hsd); - +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + /* Required power up waiting time before starting the SD initialization sequence */ HAL_Delay(2U); @@ -553,8 +593,15 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ SDMMC_ConfigData(hsd->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Read block(s) in polling mode */ if(NumberOfBlocks > 1) @@ -602,6 +649,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 return HAL_TIMEOUT; } } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Send stop transmission command in case of multiblock read */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) @@ -647,6 +697,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Empty FIFO if there is still any data */ while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) { @@ -662,9 +713,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 return HAL_ERROR; } } +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -734,6 +786,22 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + SDMMC_ConfigData(hsd->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -758,15 +826,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_ERROR; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Write block(s) in polling mode */ while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { @@ -789,7 +848,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_TIMEOUT; } } - +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Send stop transmission command in case of multiblock write */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { @@ -835,7 +897,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -897,15 +959,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui BlockAdd *= 512U; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) @@ -917,6 +970,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + SDMMC_ConfigData(hsd->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Read Blocks in IT mode */ if(NumberOfBlocks > 1U) { @@ -1010,6 +1079,19 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u return HAL_ERROR; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -1034,6 +1116,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1042,6 +1125,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; SDMMC_ConfigData(hsd->Instance, &config); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ return HAL_OK; } @@ -1090,6 +1174,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Initialize data control register */ hsd->Instance->DCTRL = 0U; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); /* Set the DMA transfer complete callback */ @@ -1106,21 +1191,16 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable SD DMA transfer */ __HAL_SD_DMA_ENABLE(hsd); +#else + hsd->pRxBuffPtr = (uint32_t*)pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { BlockAdd *= 512U; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) @@ -1131,6 +1211,28 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + SDMMC_ConfigData(hsd->Instance, &config); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsd->Instance->IDMABASE0 = (uint32_t) pData ; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Read Blocks in DMA mode */ if(NumberOfBlocks > 1U) @@ -1151,6 +1253,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; @@ -1203,6 +1308,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Initialize data control register */ hsd->Instance->DCTRL = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->pTxBuffPtr = (uint32_t*)pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; +#else /* Enable SD Error interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); @@ -1214,6 +1323,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Set the DMA Abort callback */ hsd->hdmatx->XferAbortCallback = NULL; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { @@ -1230,6 +1340,24 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsd->Instance->IDMABASE0 = (uint32_t) pData ; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) @@ -1250,11 +1378,15 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Enable SDMMC DMA transfer */ __HAL_SD_DMA_ENABLE(hsd); @@ -1269,6 +1401,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; SDMMC_ConfigData(hsd->Instance, &config); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ return HAL_OK; } @@ -1396,8 +1529,14 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if((hsd->Context & SD_CONTEXT_IT) != RESET) { @@ -1412,7 +1551,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) @@ -1426,6 +1565,32 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } else if((hsd->Context & SD_CONTEXT_DMA) != RESET) { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->Instance->DLEN = 0; + hsd->Instance->DCTRL = 0; + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */ + if((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } + } + + hsd->State = HAL_SD_STATE_READY; + if(((hsd->Context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + { + HAL_SD_TxCpltCallback(hsd); + } + if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + { + HAL_SD_RxCpltCallback(hsd); + } +#else if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); @@ -1445,20 +1610,17 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_TxCpltCallback(hsd); } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE); - SD_Write_IT(hsd); } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF); - SD_Read_IT(hsd); } @@ -1483,15 +1645,33 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - if((hsd->Context & SD_CONTEXT_DMA) != RESET) + if((hsd->Context & SD_CONTEXT_IT) != RESET) { - /* Abort the SD DMA Streams */ + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + HAL_SD_ErrorCallback(hsd); + } + else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Disable Internal DMA */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + HAL_SD_ErrorCallback(hsd); + } +#else + /* Abort the SD DMA channel */ if(hsd->hdmatx != NULL) { /* Set the DMA Tx abort callback */ @@ -1518,14 +1698,40 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; HAL_SD_AbortCallback(hsd); } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } - else if((hsd->Context & SD_CONTEXT_IT) != RESET) + } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET) + { + if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0) { - /* Set the SD state to ready to be able to start again the process */ - hsd->State = HAL_SD_STATE_READY; - HAL_SD_ErrorCallback(hsd); + /* Current buffer is buffer0, Transfer complete for buffer1 */ + if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd); + } + else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ + { + HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd); + } + } + else /* SD_DMA_BUFFER1 */ + { + /* Current buffer is buffer1, Transfer complete for buffer0 */ + if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd); + } + else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ + { + HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd); + } } + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } /** @@ -1650,7 +1856,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef pCID->OEM_AppliID = tmp << 8; /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); + tmp = (uint8_t)((hsd->CID[0] & 0x0000FF00) >> 8); pCID->OEM_AppliID |= tmp; /* Byte 3 */ @@ -2030,11 +2236,39 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { /* Configure the SDMMC peripheral */ Init.ClockEdge = hsd->Init.ClockEdge; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) Init.ClockBypass = hsd->Init.ClockBypass; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ Init.ClockPowerSave = hsd->Init.ClockPowerSave; Init.BusWide = WideMode; Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if 0 + /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ + // if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV) + if(hsd->Init.ClockDiv >= SDMMC_TRANSFER_CLK_DIV) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else + { + if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else + { + /* No High speed SD card */ + // Init.ClockDiv = SDMMC_NSpeed_CLK_DIV; + Init.ClockDiv = SDMMC_TRANSFER_CLK_DIV; + } + } +#else Init.ClockDiv = hsd->Init.ClockDiv; +#endif +#else + Init.ClockDiv = hsd->Init.ClockDiv; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ SDMMC_Init(hsd->Instance, Init); } @@ -2084,22 +2318,27 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; +#else if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Abort the SD DMA Tx Stream */ + /* Abort the SD DMA Tx channel */ if(hsd->hdmatx != NULL) { HAL_DMA_Abort(hsd->hdmatx); } - /* Abort the SD DMA Rx Stream */ + /* Abort the SD DMA Rx channel */ if(hsd->hdmarx != NULL) { HAL_DMA_Abort(hsd->hdmarx); } } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->State = HAL_SD_STATE_READY; CardState = HAL_SD_GetCardState(hsd); @@ -2124,19 +2363,40 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypedef CardState; - /* DIsable All interrupts */ + /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + HAL_SD_AbortCallback(hsd); + } +#else if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Abort the SD DMA Tx Stream */ + /* Abort the SD DMA Tx channel */ if(hsd->hdmatx != NULL) { hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; @@ -2145,7 +2405,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) hsd->hdmatx = NULL; } } - /* Abort the SD DMA Rx Stream */ + /* Abort the SD DMA Rx channel */ if(hsd->hdmarx != NULL) { hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; @@ -2159,6 +2419,9 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /* No transfer ongoing on both DMA channels*/ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) @@ -2174,6 +2437,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) HAL_SD_AbortCallback(hsd); } } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } @@ -2191,6 +2455,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief DMA SD transmit process complete callback * @param hdma: DMA handle @@ -2230,7 +2495,7 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -2287,14 +2552,16 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) /* All DMA channels are aborted */ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { HAL_SD_AbortCallback(hsd); } @@ -2324,14 +2591,16 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) /* All DMA channels are aborted */ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { HAL_SD_AbortCallback(hsd); } @@ -2342,6 +2611,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) } } } +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Initializes the sd card. @@ -2423,8 +2693,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) return errorstate; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Configure SDMMC peripheral interface */ SDMMC_Init(hsd->Instance, hsd->Init); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* All cards are initialized */ return HAL_SD_ERROR_NONE; @@ -2456,6 +2728,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { hsd->SdCard.CardVersion = CARD_V1_X; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while(validvoltage == 0) { @@ -2486,11 +2759,13 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) } /* Card type is SDSC */ hsd->SdCard.CardType = CARD_SDSC; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ } else { hsd->SdCard.CardVersion = CARD_V2_X; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while(validvoltage == 0) { @@ -2528,8 +2803,115 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { hsd->SdCard.CardType = CARD_SDSC; } +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } + else + { + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((!validvoltage) && (count < SDMMC_MAX_VOLT_TRIAL)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31) == 1) ? 1 : 0); + count++; + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + + /* Start switching procedue */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; + + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Check to CKSTOP */ + while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP); + + /* Clear CKSTOP Flag */ + hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; + + /* Check to BusyD0 */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + { + /* Error when activate Voltage Switch in SDMMC IP */ + return SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Enable Transceiver Switch PIN */ + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); + + /* Switch ready */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; + + /* Check VSWEND Flag */ + while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND); + + /* Clear VSWEND Flag */ + hsd->Instance->ICR = SDMMC_FLAG_VSWEND; + + /* Check BusyD0 status */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + { + /* Error when enabling 1.8V mode */ + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + /* Switch to 1.8V OK */ + + /* Disable VSWITCH FLAG from SDMMC IP */ + hsd->Instance->POWER = 0x13; + /* Clean Status flags */ + hsd->Instance->ICR = 0xFFFFFFFF; + } + } + } + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + return HAL_SD_ERROR_NONE; } @@ -2600,7 +2982,11 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Get status data */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) +#else while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { @@ -2631,7 +3017,11 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) return HAL_SD_ERROR_RX_OVERRUN; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) +#else while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); pSDstatus++; @@ -2643,7 +3033,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Clear all the static status flags*/ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); return HAL_SD_ERROR_NONE; } @@ -2815,6 +3205,23 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) return errorstate; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) + { + if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0)) + { + tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); + tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); + index++; + } + + + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } +#else while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) @@ -2828,6 +3235,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) return HAL_SD_ERROR_TIMEOUT; } } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { @@ -2851,8 +3259,8 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { /* No error flag set */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h index da41cd65512..b1748fe7a86 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -52,10 +50,9 @@ * @{ */ -/** @defgroup SD SD - * @brief SD HAL module driver +/** @addtogroup SD * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup SD_Exported_Types SD Exported Types @@ -126,6 +123,11 @@ typedef struct uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + + uint32_t CardSpeed; /*!< Specifies the card Speed */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ }HAL_SD_CardInfoTypeDef; /** @@ -153,10 +155,13 @@ typedef struct __IO uint32_t ErrorCode; /*!< SD Card Error codes */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ uint32_t CSD[4]; /*!< SD card specific data table */ @@ -332,6 +337,13 @@ typedef struct /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards * @{ */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ +#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ +#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards + and <104Mo/s for SDR104, Spec version 3.01 */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define CARD_SDSC ((uint32_t)0x00000000U) #define CARD_SDHC_SDXC ((uint32_t)0x00000001U) #define CARD_SECURED ((uint32_t)0x00000003U) @@ -359,6 +371,7 @@ typedef struct * @{ */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief Enable the SD device. * @retval None @@ -382,6 +395,7 @@ typedef struct * @retval None */ #define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Enable the SD device interrupt. @@ -615,6 +629,10 @@ typedef struct * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include SD HAL Extension module */ +#include "stm32l4xx_hal_sd_ex.h" +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SD_Exported_Functions SD Exported Functions * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c new file mode 100644 index 00000000000..4ee52988896 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c @@ -0,0 +1,550 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sd_ex.c + * @author MCD Application Team + * @brief SD card Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SD Extension HAL driver can be used as follows: + (+) Set card in High Speed mode using HAL_SDEx_HighSpeed() function. + (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. + (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup SDEx SDEx + * @brief SD HAL extended module driver + * @{ + */ + +#ifdef HAL_SD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDEx_Exported_Functions + * @{ + */ + +/** @addtogroup SDEx_Exported_Functions_Group1 + * @brief High Speed function + * +@verbatim + ============================================================================== + ##### High Speed function ##### + ============================================================================== + [..] + This section provides function allowing to configure the card in High Speed mode. + +@endverbatim + * @{ + */ + +/** + * @brief Switches the SD card to High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock between 50 and 120 MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_OK; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint8_t SD_hs[64] = {0}; + uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; + uint32_t Timeout = HAL_GetTick(); + + if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) && + (hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE)) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + + if (errorstate != HAL_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); + + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); + if(errorstate != HAL_OK) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + } + + tempbuff += 8; + } + + if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + errorstate = 0; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((SD_hs[13]& 2) != 2) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + } + + return errorstate; +} + +/** + * @brief Enable/Disable the SD Transciver 1.8V Mode Callback. + * @param status: Voltage Switch State + * @retval None + */ +__weak void HAL_SDEx_DriveTransceiver_1_8V_Callback(FlagStatus status) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(status); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_EnableTransciver could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup SDEx_Exported_Functions_Group2 + * @brief Multibuffer functions + * +@verbatim + ============================================================================== + ##### Multibuffer functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure the multibuffer mode and start read and write + multibuffer mode for SD HAL driver. + +@endverbatim + * @{ + */ + +/** + * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. + * @param hsd: SD handle + * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data + * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data + * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize) +{ + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0; + hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1; + hsd->Instance->IDMABSIZE = (uint32_t) (BLOCKSIZE * BufferSize); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * @param hsd: SD handle + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + + if(hsd->State == HAL_SD_STATE_READY) + { + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + { + hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + +// /* Set Block Size for Card */ +// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); +// if(errorstate != HAL_SD_ERROR_NONE) +// { +// hsd->State = HAL_SD_STATE_READY; +// hsd->ErrorCode |= errorstate; +// return HAL_ERROR; +// } + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + + /* Read Blocks in DMA mode */ + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + +} + +/** + * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * @param hsd: SD handle + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + + if(hsd->State == HAL_SD_STATE_READY) + { + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + { + hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + +// /* Set Block Size for Card */ +// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); +// if(errorstate != HAL_SD_ERROR_NONE) +// { +// hsd->State = HAL_SD_STATE_READY; +// hsd->ErrorCode |= errorstate; +// return HAL_ERROR; +// } + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + + /* Write Blocks in DMA mode */ + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Change the DMA Buffer0 or Buffer1 address on the fly. + * @param hsd: pointer to a SD_HandleTypeDef structure. + * @param Buffer: the buffer to be changed, This parameter can be one of + * the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1 + * @param pDataBuffer: The new address + * @note The BUFFER0 address can be changed only when the current transfer use + * BUFFER1 and the BUFFER1 address can be changed only when the current + * transfer use BUFFER0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +{ + if(Buffer == SD_DMA_BUFFER0) + { + /* change the buffer0 address */ + hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer; + } + else + { + /* change the memory1 address */ + hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer; + } + + return HAL_OK; +} + +/** + * @brief Read DMA Buffer 0 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Read DMA Buffer 1 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Write DMA Buffer 0 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Write DMA Buffer 1 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h new file mode 100644 index 00000000000..a187e6143bd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h @@ -0,0 +1,144 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sd_ex.h + * @author MCD Application Team + * @brief Header file of SD HAL extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_SD_EX_H +#define __STM32L4xx_HAL_SD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDEx_Exported_Types SDEx Exported Types + * @{ + */ + +/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure + * @{ + */ +typedef enum +{ + SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */ + SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */ + +}HAL_SDEx_DMABuffer_MemoryTypeDef; + + +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDEx_Exported_Functions SDEx Exported Functions + * @{ + */ + +/** @defgroup SDEx_Exported_Functions_Group1 HighSpeed functions + * @{ + */ +uint32_t HAL_SDEx_HighSpeed (SD_HandleTypeDef *hsd); + +void HAL_SDEx_DriveTransceiver_1_8V_Callback(FlagStatus status); + +/** + * @} + */ + +/** @defgroup SDEx_Exported_Functions_Group2 MultiBuffer functions + * @{ + */ +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); + +void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L4xx_HAL_SDEx_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c index 13b4a081dcc..af7665a3d52 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -24,20 +22,20 @@ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: (++) Enable the USARTx interface clock. (++) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -153,17 +151,46 @@ */ #define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#if defined(USART_CR1_FIFOEN) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#else +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#endif + +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ + USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ + +#if defined(USART_CR1_FIFOEN) +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#else +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#endif + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup SMARTCARD_Private_Variables SMARTCARD Private Variables + * @{ + */ +static const uint16_t SMARTCARDPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; +/** + * @} + */ +#endif + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SMARTCARD_Private_Functions * @{ @@ -182,9 +209,15 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(USART_CR1_FIFOEN) +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +#endif +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(USART_CR1_FIFOEN) +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /** * @} */ @@ -244,10 +277,10 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar */ /** - * @brief Initialize the SMARTCARD mode according to the specified + * @brief Initialize the SMARTCARD mode according to the specified * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) @@ -306,9 +339,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) @@ -347,32 +380,32 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief Initialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) + __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspInit can be implemented in the user file */ } /** - * @brief DeInitialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) + __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspDeInit can be implemented in the user file */ @@ -461,9 +494,13 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ /** - * @brief Send an amount of data in blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in blocking mode. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @param Timeout Timeout duration. @@ -488,7 +525,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -542,9 +579,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui } /** - * @brief Receive an amount of data in blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in blocking mode. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @param Timeout Timeout duration. @@ -601,9 +642,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin } /** - * @brief Send an amount of data in interrupt mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -617,20 +665,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - hsmartcard->pTxBuffPtr = pData; - hsmartcard->TxXferSize = Size; + + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - + hsmartcard->TxISR = NULL; + /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - + /* Disable Rx, enable Tx */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); @@ -638,16 +687,43 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the SMARTCARD Error Interrupt: (Frame error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); - + +#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + } + else +#endif + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); +#endif + } + return HAL_OK; } else @@ -657,9 +733,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Receive an amount of data in interrupt mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @retval HAL status @@ -684,12 +767,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); - + /* Configure Rx interrupt processing */ +#if defined(USART_CR1_FIFOEN) + if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + } + else +#endif + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); +#else + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); +#endif + } + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -702,9 +810,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Send an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -774,9 +882,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard } /** - * @brief Receive an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), @@ -838,7 +946,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, /** * @brief Abort ongoing transfers (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) @@ -847,12 +955,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) @@ -906,7 +1019,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) @@ -915,11 +1028,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); +#else /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Check if a receive process is ongoing or not. If not disable ERR IT */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) @@ -959,7 +1078,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /** * @brief Abort ongoing Receive transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) @@ -968,11 +1087,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +#else /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -1012,7 +1138,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Abort ongoing transfers (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) @@ -1023,14 +1149,20 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t abortcplt = 1; +#if defined(USART_CR1_FIFOEN) + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ @@ -1062,7 +1194,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the SMARTCARD DMA Tx request if enabled */ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { @@ -1118,6 +1250,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->TxXferCount = 0; hsmartcard->RxXferCount = 0; + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; + /* Reset errorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; @@ -1138,7 +1274,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) @@ -1149,11 +1285,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); +#else /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Check if a receive process is ongoing or not. If not disable ERR IT */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) @@ -1186,6 +1328,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Reset Tx transfer counter */ hsmartcard->TxXferCount = 0; + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1197,10 +1342,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart { /* Reset Tx transfer counter */ hsmartcard->TxXferCount = 0; - + + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - + /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1214,7 +1362,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /** * @brief Abort ongoing Receive transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) @@ -1228,28 +1376,35 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +#else /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); - + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if(hsmartcard->hdmarx != NULL) { /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { @@ -1261,13 +1416,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc { /* Reset Rx transfer counter */ hsmartcard->RxXferCount = 0; - + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); } @@ -1276,127 +1434,156 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc { /* Reset Rx transfer counter */ hsmartcard->RxXferCount = 0; - + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); } - + return HAL_OK; } /** * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR); uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); - uint32_t cr3its; + uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == RESET) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - SMARTCARD_Receive_IT(hsmartcard); - /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */ + if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} return; } } - + /* If some errors occur */ - cr3its = READ_REG(hsmartcard->Instance->CR3); - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) ) +#if defined(USART_CR1_FIFOEN) + if( (errorflags != RESET) + && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) +#else + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +#endif { /* SMARTCARD parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; } - + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; } - + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + if( ((isrflags & USART_ISR_ORE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET)) ) +#else + if( ((isrflags & USART_ISR_ORE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET)) ) +#endif { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } - + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; } - + /* Call SMARTCARD Error Call back function if need be --------------------------*/ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET) ) +#endif { - SMARTCARD_Receive_IT(hsmartcard); + if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} } - + /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception */ if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET) || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ SMARTCARD_EndRxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel */ if(hsmartcard->hdmarx != NULL) { /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { @@ -1417,27 +1604,28 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } } /* other error type to be considered as blocking : - - Frame error in Transmission + - Frame error in Transmission */ - else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) + else if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ SMARTCARD_EndTxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - + /* Abort the SMARTCARD DMA Tx channel */ if(hsmartcard->hdmatx != NULL) { /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA TX */ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { @@ -1460,15 +1648,15 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) { @@ -1476,69 +1664,93 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) __HAL_UNLOCK(hsmartcard); HAL_SMARTCARD_RxCpltCallback(hsmartcard); /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); return; } - + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { - SMARTCARD_Transmit_IT(hsmartcard); + if (hsmartcard->TxISR != NULL) {hsmartcard->TxISR(hsmartcard);} return; } - + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) + if( (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) { SMARTCARD_EndTransmit_IT(hsmartcard); return; } + +#if defined(USART_CR1_FIFOEN) + /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + { + HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard); + return; + } + + /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + { + HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard); + return; + } +#endif } /** - * @brief Tx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) + __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. */ } /** - * @brief SMARTCARD error callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. */ @@ -1547,7 +1759,7 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) @@ -1563,7 +1775,7 @@ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) @@ -1579,7 +1791,7 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs /** * @brief SMARTCARD Abort Receive Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) @@ -1597,7 +1809,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm */ /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions + * @brief SMARTCARD State and Errors functions * @verbatim ============================================================================== @@ -1617,8 +1829,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm /** * @brief Return the SMARTCARD handle state. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1627,15 +1839,15 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar uint32_t temp1= 0x00, temp2 = 0x00; temp1 = hsmartcard->gState; temp2 = hsmartcard->RxState; - + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } /** * @brief Return the SMARTCARD handle error code. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD handle Error Code + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. +* @retval SMARTCARD handle Error Code */ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) { @@ -1650,14 +1862,14 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions * @{ */ /** * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1680,6 +1892,9 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler)); +#endif /*-------------------------- USART CR1 Configuration -----------------------*/ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). @@ -1687,8 +1902,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - tmpreg |= (uint32_t) hsmartcard->Init.WordLength; + tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -1707,15 +1921,22 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * to hsmartcard->Init.NACKEnable * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; - tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS); - MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg); + tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); + +#if defined(USART_PRESC_PRESCALER) + /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/ + /* Configure + * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */ + MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler); +#endif /*-------------------------- USART GTPR Configuration ----------------------*/ - tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS)); + tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); @@ -1725,28 +1946,69 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); + tmpreg = 0; switch (clocksource) { - case SMARTCARD_CLOCKSOURCE_PCLK1: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_PCLK2: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_HSI: - hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_LSE: - hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + case SMARTCARD_CLOCKSOURCE_PCLK1: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_PCLK2: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_HSI: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HSI_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_LSE: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((LSE_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hsmartcard->Instance->BRR = tmpreg; } + else + { + ret = HAL_ERROR; + } + +#if defined(USART_CR1_FIFOEN) + /* Initialize the number of data to process during RX/TX ISR execution */ + hsmartcard->NbTxDataToProcess = 1; + hsmartcard->NbRxDataToProcess = 1; +#endif + + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; return ret; } @@ -1754,8 +2016,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1816,8 +2078,8 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1864,7 +2126,7 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar /** * @brief Handle SMARTCARD Communication Timeout. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. * @param Status The new Flag status (SET or RESET). * @param Tickstart Tick start value @@ -1882,12 +2144,16 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +#endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); return HAL_TIMEOUT; @@ -1901,13 +2167,17 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* At end of Tx process, restore hsmartcard->gState to Ready */ @@ -1918,13 +2188,17 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore hsmartcard->RxState to Ready */ @@ -1933,7 +2207,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** - * @brief DMA SMARTCARD transmit process complete callback. + * @brief DMA SMARTCARD transmit process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1952,7 +2226,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SMARTCARD receive process complete callback. + * @brief DMA SMARTCARD receive process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -2074,7 +2348,7 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); - + hsmartcard->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ @@ -2085,7 +2359,7 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ hsmartcard->TxXferCount = 0; hsmartcard->RxXferCount = 0; @@ -2155,13 +2429,14 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once + * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() - * @retval HAL status + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) @@ -2169,34 +2444,67 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartca if(hsmartcard->TxXferCount == 0) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); +#endif /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); - - return HAL_OK; } else { hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); hsmartcard->TxXferCount--; - - return HAL_OK; } } - else +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - return HAL_BUSY; + for(nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(hsmartcard->TxXferCount == 0) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + } + else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + { + hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->TxXferCount--; + } + } } } +#endif /** * @brief Wrap up transmission in non-blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); @@ -2217,61 +2525,132 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); } - + /* Tx process is ended, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - HAL_SMARTCARD_TxCpltCallback(hsmartcard); + /* Clear TxISR function pointer */ + hsmartcard->TxISR = NULL; - return HAL_OK; + HAL_SMARTCARD_TxCpltCallback(hsmartcard); } /** * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). - * @retval HAL status + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - + if(--hsmartcard->RxXferCount == 0) { +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); +#else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE); - +#endif + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD Parity Error Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + HAL_SMARTCARD_RxCpltCallback(hsmartcard); - - return HAL_OK; } - - return HAL_OK; } else { /* Clear RXNE interrupt flag */ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } +} - return HAL_BUSY; +#if defined(USART_CR1_FIFOEN) +/** + * @brief Receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + for(nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + + if(--hsmartcard->RxXferCount == 0) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((hsmartcard->RxXferCount != 0U)) && (hsmartcard->RxXferCount < hsmartcard->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); } } +#endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h index ad6d966b732..b6fe5b04369 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -66,7 +64,8 @@ typedef struct { uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */ + Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) + where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ @@ -97,7 +96,9 @@ typedef struct Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ - uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */ + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. + This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied + by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -120,6 +121,11 @@ typedef struct disabled. Otherwise, its maximum value is 7 (before signalling an error) */ +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */ +#endif + }SMARTCARD_InitTypeDef; /** @@ -235,40 +241,53 @@ typedef enum /** * @brief SMARTCARD handle Structure definition */ -typedef struct +typedef struct __SMARTCARD_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ + + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ + uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ - __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ - uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ - __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ +#if defined(USART_CR1_FIFOEN) + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ +#endif - DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ + void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ + void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - HAL_LockTypeDef Lock; /*!< Locking object */ + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ - __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + HAL_LockTypeDef Lock; /*!< Locking object */ - uint32_t ErrorCode; /*!< SmartCard Error code */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + uint32_t ErrorCode; /*!< SmartCard Error code */ }SMARTCARD_HandleTypeDef; @@ -297,7 +316,7 @@ typedef enum /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ -#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */ +#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */ /** * @} */ @@ -305,17 +324,17 @@ typedef enum /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits * @{ */ -#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */ -#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */ +#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */ +#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ /** * @} - */ - + */ + /** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ -#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */ -#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */ +#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */ /** * @} */ @@ -323,9 +342,9 @@ typedef enum /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode * @{ */ -#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */ -#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */ -#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */ +#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */ /** * @} */ @@ -333,8 +352,8 @@ typedef enum /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) /*!< SMARTCARD frame low polarity */ -#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */ +#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */ /** * @} */ @@ -342,8 +361,8 @@ typedef enum /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SMARTCARD frame phase on first clock transition */ -#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */ +#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */ /** * @} */ @@ -351,8 +370,8 @@ typedef enum /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ -#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ +#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ /** * @} */ @@ -360,8 +379,8 @@ typedef enum /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method * @{ */ -#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame one-bit sample disabled */ -#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */ /** * @} */ @@ -370,8 +389,8 @@ typedef enum /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ -#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */ -#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD NACK transmission enabled */ +#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */ /** * @} */ @@ -379,17 +398,39 @@ typedef enum /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD receiver timeout disabled */ -#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */ +#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */ /** * @} */ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler + * @{ + */ +#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + +/** + * @} + */ +#endif + /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ -#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ /** * @} */ @@ -397,8 +438,8 @@ typedef enum /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ -#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ @@ -406,8 +447,8 @@ typedef enum /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion * @{ */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ -#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ /** * @} */ @@ -415,8 +456,8 @@ typedef enum /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap * @{ */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ -#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ /** * @} */ @@ -424,8 +465,8 @@ typedef enum /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable * @{ */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ -#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ @@ -433,8 +474,8 @@ typedef enum /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error * @{ */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ -#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ /** * @} */ @@ -442,8 +483,8 @@ typedef enum /** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first * @{ */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ /** * @} */ @@ -451,32 +492,8 @@ typedef enum /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters * @{ */ -#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive data flush request */ -#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */ -/** - * @} - */ - -/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register - * @{ - */ -#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */ -/** - * @} - */ - -/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register - * @{ - */ -#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */ -/** - * @} - */ - -/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register - * @{ - */ -#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */ /** * @} */ @@ -484,7 +501,7 @@ typedef enum /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask * @{ */ -#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ /** * @} */ @@ -499,7 +516,7 @@ typedef enum */ /** @brief Reset SMARTCARD handle states. - * @param __HANDLE__: SMARTCARD handle. + * @param __HANDLE__ SMARTCARD handle. * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -508,7 +525,7 @@ typedef enum } while(0) /** @brief Flush the Smartcard Data registers. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ @@ -518,8 +535,8 @@ typedef enum } while(0) /** @brief Clear the specified SMARTCARD pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag @@ -527,86 +544,92 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - @if STM32L443xx - * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) - @endif + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag * @retval None */ #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) /** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) /** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) /** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) /** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) /** @brief Check whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - @if STM32L443xx * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) - @endif * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref SMARTCARD_FLAG_BUSY Busy flag * @arg @ref SMARTCARD_FLAG_EOBF End of block flag * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag + * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag + * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag * @arg @ref SMARTCARD_FLAG_NE Noise error flag * @arg @ref SMARTCARD_FLAG_FE Framing error flag * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag + * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag + * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag + * @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - /** @brief Enable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ @@ -614,20 +637,24 @@ typedef enum ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ @@ -636,51 +663,57 @@ typedef enum /** @brief Check whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt - * @arg @ref SMARTCARD_IT_NE Noise error interrupt - * @arg @ref SMARTCARD_IT_FE Framing error interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt source to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag @@ -688,19 +721,18 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - @if STM32L443xx * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) - @endif * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag * @retval None */ -#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request @@ -710,25 +742,25 @@ typedef enum #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -745,42 +777,42 @@ typedef enum /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). - * @param __BAUDRATE__: Baud rate set by the configuration function. + * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. - * @param __LENGTH__: block length. + * @param __LENGTH__ block length. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) /** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__: receiver timeout value. + * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. - * @param __COUNT__: number of retransmissions. + * @param __COUNT__ number of retransmissions. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) /** * @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__: SMARTCARD frame length. + * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) /** * @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__: SMARTCARD frame number of stop bits. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ @@ -788,7 +820,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__: SMARTCARD frame parity. + * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ @@ -796,28 +828,28 @@ typedef enum /** * @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__: SMARTCARD communication mode. + * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00)) +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__: SMARTCARD frame polarity. + * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** * @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__: SMARTCARD frame phase. + * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) /** * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ @@ -825,7 +857,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__: SMARTCARD frame sampling. + * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ @@ -833,7 +865,7 @@ typedef enum /** * @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__: SMARTCARD NACK transmission setting. + * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ @@ -841,15 +873,65 @@ typedef enum /** * @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__: SMARTCARD receiver timeout setting. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) +/** + * @brief Ensure that SMARTCARD clock Prescaler is valid. + * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) + +/** + * @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__ SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + /** * @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__: SMARTCARD advanced features initialization. + * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ @@ -863,7 +945,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__: SMARTCARD frame TX inversion setting. + * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ @@ -871,7 +953,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__: SMARTCARD frame RX inversion setting. + * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ @@ -879,7 +961,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__: SMARTCARD frame data inversion setting. + * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ @@ -887,7 +969,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ @@ -895,7 +977,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__: SMARTCARD frame overrun setting. + * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -903,7 +985,7 @@ typedef enum /** * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -911,7 +993,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__: SMARTCARD frame MSB first setting. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -919,7 +1001,7 @@ typedef enum /** * @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__: SMARTCARD request parameter. + * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c index a73b80ec74e..6f17643d670 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SMARTCARD HAL module driver. * This file provides extended firmware functions to manage the following * functionalities of the SmartCard. @@ -73,13 +71,69 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* Exported functions --------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions * @{ */ -/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions +/** @defgroup SMARTCARDEx_Exported_Functions_Group2 IO operation functions + * @brief Extended SMARTCARD Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_SMARTCARDEx_RxFifoFullCallback() + (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief SMARTCARD RX Fifo full callback. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD TX Fifo empty callback. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral Control functions * @brief Extended control functions * @verbatim @@ -92,6 +146,10 @@ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature + (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold @endverbatim * @{ @@ -99,21 +157,21 @@ /** * @brief Update on the fly the SMARTCARD block length in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @param BlockLength SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) { - MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS)); + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); } /** * @brief Update on the fly the receiver timeout value in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout * value must be less or equal to 0x0FFFFFFFF. * @retval None */ @@ -125,7 +183,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ /** * @brief Enable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -157,7 +215,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @brief Disable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -187,10 +245,229 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef } } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Enable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update TX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update RX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} +#endif +/** + * @} + */ + /** * @} */ +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; + uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) + { + hsmartcard->NbTxDataToProcess = 1; + hsmartcard->NbRxDataToProcess = 1; + } + else + { + rx_fifo_depth = 8; /* RX Fifo size */ + tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + hsmartcard->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + } +} +#endif /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h index e2b7cbe68fb..e59ba1112cc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention @@ -70,50 +68,93 @@ #define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ /** * @} - */ - + */ + /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ -#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ +#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */ -#endif /* USART_TCBGT_SUPPORT */ +#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */ +#endif /* USART_TCBGT_SUPPORT */ /** * @} */ +#if defined(USART_CR1_FIFOEN) +/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level + * @brief SMARTCARD TXFIFO level + * @{ + */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level + * @brief SMARTCARD RXFIFO level + * @{ + */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ +#endif - - /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ -#endif /* USART_TCBGT_SUPPORT */ -#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ -#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ -#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ -#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ -#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ +#endif /* USART_TCBGT_SUPPORT */ +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */ +#else #define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ -#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#endif +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */ +#else #define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ -#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ -#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ -#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ -#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ -#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#endif +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */ +#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */ +#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */ +#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */ +#endif /** * @} */ @@ -128,23 +169,35 @@ * - ZZZZZ : Flag position in the ISR register(5 bits) * @{ */ -#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */ -#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */ -#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */ -#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */ -#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */ +#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ +#endif +#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ +#endif +#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ -#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */ -#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */ -#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */ -#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */ - -#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */ -#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */ +#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ +#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */ -#endif /* USART_TCBGT_SUPPORT */ +#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ +#endif + +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ +#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */ +#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */ +#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */ +#endif /** * @} */ @@ -154,13 +207,16 @@ */ #define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ #define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise detected clear flag */ #define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ #define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */ +#endif #define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ -#endif /* USART_TCBGT_SUPPORT */ +#endif #define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ #define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ /** @@ -170,7 +226,27 @@ /** * @} */ + /* Exported macros -----------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Constants SMARTCARDEx Private Constants + * @{ + */ +#if defined(USART_CR1_FIFOEN) +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ +#endif +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros * @{ @@ -297,24 +373,24 @@ #endif /* STM32L432xx || STM32L442xx */ /** @brief Set the Transmission Completion flag - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). * @retval None */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ - do { \ - if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ - { \ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } \ - else \ - { \ + } \ + else \ + { \ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ - } \ - } while(0) + } \ + } while(0) #else #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ do { \ @@ -323,22 +399,23 @@ #endif /** @brief Return the transmission completion flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is * reported. * @retval Transmission completion flag */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) #else #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) #endif - + + /** * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. - * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) */ #if defined(USART_TCBGT_SUPPORT) @@ -350,7 +427,7 @@ /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMARTCARDEx_Exported_Functions @@ -358,9 +435,22 @@ */ /* Initialization and de-initialization functions ****************************/ -/* IO operation methods *******************************************************/ +/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 + * @{ + */ -/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 +/* IO operation functions *****************************************************/ +#if defined(USART_CR1_FIFOEN) +void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); +#endif + +/** + * @} + */ + + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 * @{ */ @@ -370,6 +460,13 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(USART_CR1_FIFOEN) +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); +#endif + /** * @} */ @@ -378,6 +475,9 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ + +/* Private functions ---------------------------------------------------------*/ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c index fdbd04224d0..8aeaa1b4976 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c @@ -2,25 +2,23 @@ ****************************************************************************** * @file stm32l4xx_hal_smbus.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SMBUS HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, * based on I2C principles of operation : * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The SMBUS HAL driver can be used as follows: - + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: - SMBUS_HandleTypeDef hsmbus; + SMBUS_HandleTypeDef hsmbus; (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock @@ -28,7 +26,7 @@ (+++) Enable the clock for the SMBUS GPIOs (+++) Configure SMBUS pins as alternate function open-drain (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SMBUSx interrupt priority + (+++) Configure the SMBUSx interrupt priority (+++) Enable the NVIC SMBUS IRQ Channel (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, @@ -92,7 +90,7 @@ [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention @@ -121,8 +119,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -156,7 +154,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -172,6 +170,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -184,19 +184,19 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and + [..] This subsection provides a set of functions allowing to initialize and deinitialize the SMBUSx peripheral: - (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, IT and NVIC ). - (+) Call the function HAL_SMBUS_Init() to configure the selected device with + (+) Call the function HAL_SMBUS_Init() to configure the selected device with the selected configuration: (++) Clock Timing (++) Bus Timeout @@ -212,31 +212,31 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre (++) Peripheral mode - (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration - of the selected SMBUSx peripheral. + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and - HAL_SMBUS_ConfigDigitalFilter(). + HAL_SMBUS_ConfigDigitalFilter(). @endverbatim * @{ */ /** - * @brief Initialize the SMBUS according to the specified parameters + * @brief Initialize the SMBUS according to the specified parameters * in the SMBUS_InitTypeDef and initialize the associated handle. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) -{ +{ /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); @@ -250,7 +250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); - if(hsmbus->State == HAL_SMBUS_STATE_RESET) + if (hsmbus->State == HAL_SMBUS_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; @@ -258,17 +258,17 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); } - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); - - /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ /* Configure SMBUSx: Frequency range */ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ /* Configure SMBUSx: Bus Timeout */ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; @@ -277,10 +277,10 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - if(hsmbus->Init.OwnAddress1 != 0U) + + if (hsmbus->Init.OwnAddress1 != 0U) { - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); } @@ -292,41 +292,41 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ /* Configure SMBUSx: Addressing Master mode */ - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) { hsmbus->Instance->CR2 = (I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ /* AUTOEND and NACK bit will be manage during Transfer process */ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); - + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) + && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } /* Enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitialize the SMBUS peripheral. + * @brief DeInitialize the SMBUS peripheral. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -334,29 +334,29 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the SMBUS Peripheral Clock */ __HAL_SMBUS_DISABLE(hsmbus); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_SMBUS_MspDeInit(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; hsmbus->State = HAL_SMBUS_STATE_RESET; - - /* Release Lock */ + + /* Release Lock */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } @@ -373,7 +373,7 @@ __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspInit could be implemented in the user file - */ + */ } /** @@ -389,7 +389,7 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspDeInit could be implemented in the user file - */ + */ } /** @@ -407,7 +407,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); @@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); @@ -490,20 +490,19 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin } } - /** * @} */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the SMBUS data + This subsection provides a set of functions allowing to manage the SMBUS data transfers. (#) Blocking mode function to check if device is ready for usage is : @@ -512,7 +511,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin (#) There is only one mode of transfer: (++) Non-Blocking mode : The communication is performed using Interrupts. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the + The end of the data processing will be indicated through the dedicated SMBUS IRQ when using Interrupt mode. (#) Non-Blocking mode functions with Interrupt are : @@ -550,15 +549,15 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ +{ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Prepare transfer parameters */ @@ -568,12 +567,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -584,17 +583,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -603,32 +602,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); - + return HAL_OK; } else { return HAL_BUSY; - } + } } /** @@ -647,27 +646,27 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - + /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - - if(Size > MAX_NBYTE_SIZE) + + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -675,20 +674,20 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 { hsmbus->XferSize = Size; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -697,24 +696,24 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -728,18 +727,18 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) { - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + /* Keep the same state as previous */ /* to perform as well the call of the corresponding end of transfer callback */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; } - else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; } @@ -750,32 +749,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ return HAL_ERROR; } hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -792,11 +791,11 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -804,10 +803,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -822,7 +821,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Convert OTHER_xxx XferOptions if any */ SMBUS_ConvertOtherXferOptions(hsmbus); - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -832,32 +831,32 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - + /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -867,8 +866,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } else { - return HAL_ERROR; - } + return HAL_ERROR; + } } /** @@ -885,22 +884,22 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -921,7 +920,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -932,12 +931,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -947,7 +946,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } else { - return HAL_ERROR; + return HAL_ERROR; } } @@ -960,10 +959,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) { hsmbus->State = HAL_SMBUS_STATE_LISTEN; - + /* Enable the Address Match interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } @@ -976,13 +975,13 @@ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) { /* Disable Address listen mode only if a transfer is not ongoing */ - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Disable the Address Match interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } else @@ -1000,7 +999,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; /* Clear ALERT flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); @@ -1008,7 +1007,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) /* Enable Alert Interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** * @brief Disable the SMBUS alert mode with Interrupt. @@ -1019,16 +1018,16 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; - + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + /* Disable Alert Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** - * @brief Check if target device is ready for communication. + * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value @@ -1038,72 +1037,72 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ +{ uint32_t tickstart = 0U; - + __IO uint32_t SMBUS_Trials = 0U; - - if(hsmbus->State == HAL_SMBUS_STATE_READY) + + if (hsmbus->State == HAL_SMBUS_STATE_READY) { - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + do { /* Generate Start */ - hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); - + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); return HAL_TIMEOUT; } - } + } } - + /* Check if the NACKF flag has not been set */ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } else { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -1114,31 +1113,32 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Clear STOP Flag, auto generated with autoend*/ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - + /* Check if the maximum allowed number of trials has been reached */ if (SMBUS_Trials++ == Trials) { /* Generate Stop */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - }while(SMBUS_Trials < Trials); + } + } + while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; - } + } else { return HAL_BUSY; @@ -1161,28 +1161,28 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t tmpisrvalue = 0U; - + /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); - + /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) - { + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Master_ISR(hsmbus); } } - + /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1190,15 +1190,15 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Master_ISR(hsmbus); } - } - - /* SMBUS in mode Listener Only --------------------------------------------------*/ + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { @@ -1215,79 +1215,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) */ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); - } - - /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); - } - - /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); - } - - /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; - - /* Clear TIMEOUT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); - } - - /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - } - - /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; - - /* Clear PEC error flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); - } - - /* Call the Error Callback in case of Error detected */ - if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) - { - /* Do not Reset the HAL state in case of ALERT error */ - if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) - { - if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) - { - /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ - /* keep HAL_SMBUS_STATE_LISTEN if set */ - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - } - } - - /* Call the Error callback to prevent upper layer */ - HAL_SMBUS_ErrorCallback(hsmbus); - } + SMBUS_ITErrorHandler(hsmbus); } /** @@ -1303,7 +1231,7 @@ __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1334,7 +1262,7 @@ __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1357,8 +1285,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @brief Slave Address Match callback. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param TransferDirection: Master request Transfer Direction (Write/Read) - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -1402,22 +1330,22 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ErrorCallback() could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1449,14 +1377,14 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) /** * @} - */ + */ /** * @} - */ + */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1466,42 +1394,45 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) { uint16_t DevAddress; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - + /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); @@ -1511,21 +1442,21 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + /* REenable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1537,64 +1468,64 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) - { + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferSize--; - hsmbus->XferCount--; + hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); - - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) + else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ - if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1603,10 +1534,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1614,30 +1545,30 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } /* Call TxCpltCallback() if no stop mode is set */ - else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ - + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1646,10 +1577,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1657,39 +1588,39 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { uint8_t TransferDirection = 0U; uint16_t SlaveAddrCode = 0U; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1711,58 +1642,58 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { TransferDirection = SMBUS_GET_DIR(hsmbus); SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); - + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); } - else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { - if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1U) + if (hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0U) + else if (hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ hsmbus->PreviousState = hsmbus->State; hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1777,13 +1708,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; } - } - else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + } + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -1793,7 +1724,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1802,21 +1733,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0U) + if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferCount--; hsmbus->XferSize--; } - - if(hsmbus->XferCount == 0U) + + if (hsmbus->XferCount == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1833,17 +1764,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } /* Check if STOPF is set */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1861,30 +1792,30 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Clear ADDR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_SMBUS_ListenCpltCallback(hsmbus); } } /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + + return HAL_OK; +} /** * @brief Manage the enabling of Interrupts. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1892,40 +1823,40 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { /* Enable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Enable ERR, TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Enable ERR, TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; } - + /* Enable interrupts only at the end */ /* to avoid the risk of SMBUS interrupt handle execution before */ /* all interrupts requested done */ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); - return HAL_OK; + return HAL_OK; } /** * @brief Manage the disabling of Interrupts. @@ -1934,60 +1865,60 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Disable TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1998,9 +1929,95 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); - + return HAL_OK; } + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + /** * @brief Handle SMBUS Communication Timeout. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -2010,26 +2027,26 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + if (Status == RESET) + { + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } @@ -2037,25 +2054,25 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu } else { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; } /** @@ -2080,26 +2097,15 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - - /* Get the CR2 register value */ - tmpreg = hsmbus->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - + /* update CR2 register */ - hsmbus->Instance->CR2 = tmpreg; -} + MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} /** * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. @@ -2111,14 +2117,14 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ /* set XferOptions to SMBUS_FIRST_FRAME */ - if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) { hsmbus->XferOptions = SMBUS_FIRST_FRAME; } /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ /* it request implicitly to generate a restart condition */ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ - else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) { hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; } @@ -2126,7 +2132,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ - else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; } @@ -2134,7 +2140,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ - else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h index 9582dc5188b..bc7dba982db 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smbus.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32L4xx_HAL_SMBUS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" +#include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -52,25 +50,25 @@ /** @addtogroup SMBUS * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Types SMBUS Exported Types * @{ - */ - + */ + /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition - * @brief SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization + This parameter calculated by referring to SMBUS initialization section in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. This parameter can be a value of @ref SMBUS_Analog_Filter */ - + uint32_t OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ @@ -99,51 +97,51 @@ typedef struct This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; -/** +/** * @} */ /** @defgroup HAL_state_definition HAL state definition - * @brief HAL State definition + * @brief HAL State definition * @{ - */ + */ #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ -/** +/** * @} */ /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition - * @brief SMBUS Error Code definition + * @brief SMBUS Error Code definition * @{ - */ + */ #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ -/** +/** * @} */ -/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition - * @brief SMBUS handle Structure definition +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition * @{ */ typedef struct @@ -168,11 +166,11 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ -}SMBUS_HandleTypeDef; +} SMBUS_HandleTypeDef; /** * @} */ - + /** * @} */ @@ -281,9 +279,9 @@ typedef struct */ #define SMBUS_NO_STARTSTOP (0x00000000U) -#define SMBUS_GENERATE_STOP I2C_CR2_STOP -#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define SMBUS_GENERATE_START_WRITE I2C_CR2_START +#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -298,7 +296,7 @@ typedef struct */ #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) -#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -340,7 +338,7 @@ typedef struct * Elements values convention: 0xXXXXYYYY * - XXXXXXXX : Flag mask * @{ - */ + */ #define SMBUS_FLAG_TXE I2C_ISR_TXE #define SMBUS_FLAG_TXIS I2C_ISR_TXIS @@ -369,8 +367,8 @@ typedef struct /* Exported macros ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros * @{ - */ - + */ + /** @brief Reset SMBUS handle state. * @param __HANDLE__ specifies the SMBUS Handle. * @retval None @@ -388,7 +386,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) @@ -404,11 +402,11 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified SMBUS interrupt source is enabled or not. * @param __HANDLE__ specifies the SMBUS Handle. * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. @@ -420,7 +418,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -429,69 +427,69 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) - * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert * @arg @ref SMBUS_FLAG_BUSY Bus busy * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) - * + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) - + /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert - * + * * @retval None */ #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - + /** @brief Enable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} - */ - - + */ + + /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -517,7 +515,7 @@ typedef struct ((MASK) == SMBUS_OA2_MASK04) || \ ((MASK) == SMBUS_OA2_MASK05) || \ ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) + ((MASK) == SMBUS_OA2_MASK07)) #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ ((CALL) == SMBUS_GENERALCALL_ENABLE)) @@ -540,8 +538,8 @@ typedef struct ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) - - + + #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ ((REQUEST) == SMBUS_GENERATE_START_READ) || \ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ @@ -581,7 +579,7 @@ typedef struct /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions @@ -591,13 +589,13 @@ typedef struct /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - + /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); /** @@ -607,7 +605,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions * @{ */ - + /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling * @{ @@ -654,7 +652,7 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions * @{ */ @@ -668,7 +666,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup SMBUS_Private_Functions SMBUS Private Functions @@ -677,19 +675,19 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /* Private functions are defined in stm32l4xx_hal_smbus.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c index 95068ef614f..b69650029c8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -35,7 +33,7 @@ (+++) Enable the DMAx clock (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel - (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS @@ -54,17 +52,15 @@ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks [..] Master Receive mode restriction: - (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI does not initiate a new transfer the following procedure has to be respected: (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() [..] - The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI - modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the - maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on - the APBx peripheral clock frequency (fPCLK) used by the SPI instance. - + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. @endverbatim @@ -267,7 +263,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -366,7 +362,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif /* USE_SPI_CRC */ - /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */ + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); @@ -392,7 +388,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -426,7 +422,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -442,7 +438,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -495,11 +491,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -507,7 +503,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -655,6 +650,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } + // Added for MBED PR #4975 if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { __HAL_SPI_DISABLE(hspi); } @@ -679,11 +675,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -693,7 +689,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 #endif /* USE_SPI_CRC */ uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { @@ -747,12 +742,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Set the Rx Fifo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -910,12 +905,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, @@ -929,7 +924,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -986,12 +980,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Set the Rx Fifo threshold */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) { - /* set fiforxthreshold according the reception data length: 16bit */ + /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthreshold according the reception data length: 8bit */ + /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1071,7 +1065,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { - /* check TXE flag */ + /* Check TXE flag */ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { if (hspi->TxXferCount > 1U) @@ -1112,7 +1106,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxXferCount -= 2U; if (hspi->RxXferCount <= 1U) { - /* set fiforxthresold before to switch on 8 bit data size */ + /* Set RX Fifo threshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -1186,13 +1180,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } error : @@ -1203,16 +1193,15 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1287,16 +1276,15 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { @@ -1336,13 +1324,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Set fiforxthresold according the reception data length: 16 bit */ + /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* Set fiforxthresold according the reception data length: 8 bit */ + /* Set RX Fifo threshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } @@ -1392,18 +1380,17 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1474,12 +1461,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check if packing mode is enabled and if there is more than 2 data to receive */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) { - /* Set fiforxthresold according the reception data length: 16 bit */ + /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* Set fiforxthresold according the reception data length: 8 bit */ + /* Set RX Fifo threshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1501,17 +1488,17 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - - /* check tx dma handle */ + + /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); /* Check Direction parameter */ @@ -1614,25 +1601,25 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - - /* check rx dma handle */ + + /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; - - /* check tx dma handle */ + + /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ @@ -1685,17 +1672,17 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* Set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -1747,12 +1734,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, @@ -1760,8 +1747,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - - /* check rx & tx dma handles */ + + /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1813,8 +1800,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } #endif /* USE_SPI_CRC */ - - /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); @@ -1826,7 +1811,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } else { - /* Set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) @@ -1845,7 +1830,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* Set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -2268,7 +2253,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2288,7 +2273,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2307,8 +2292,8 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) } /** - * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2339,7 +2324,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2434,8 +2419,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /** - * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2450,8 +2435,8 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2466,8 +2451,8 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2482,8 +2467,8 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2498,8 +2483,8 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2514,8 +2499,8 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2530,8 +2515,8 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2584,7 +2569,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2596,7 +2581,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2620,8 +2605,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ /** - * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2667,8 +2652,8 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2759,7 +2744,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2844,7 +2829,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2857,7 +2842,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2870,7 +2855,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2883,7 +2868,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -3041,7 +3026,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3055,7 +3040,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -3066,7 +3051,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount--; } - /* check end of the reception */ + /* Check end of the reception */ if (hspi->RxXferCount == 0U) { #if (USE_SPI_CRC != 0U) @@ -3091,7 +3076,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3107,7 +3092,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) hspi->CRCSize--; - /* check end of the reception */ + /* Check end of the reception */ if (hspi->CRCSize == 0U) { /* Disable RXNE and ERR interrupt */ @@ -3123,7 +3108,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3143,7 +3128,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->TxXferCount--; } - /* check the end of the transmission */ + /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) { #if (USE_SPI_CRC != 0U) @@ -3169,7 +3154,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3203,7 +3188,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3227,7 +3212,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3265,7 +3250,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3290,7 +3275,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3323,7 +3308,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3346,7 +3331,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3379,7 +3364,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3403,7 +3388,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3428,13 +3413,13 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, @@ -3480,13 +3465,13 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, } /** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Fifo: Fifo to check - * @param State: Fifo state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, @@ -3542,10 +3527,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3579,9 +3564,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /** * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3592,6 +3577,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { @@ -3605,12 +3591,13 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + return HAL_OK; } /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3667,7 +3654,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3709,7 +3696,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3748,22 +3735,22 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { __IO uint32_t count; - + /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); - + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - + /* Check RXNEIE is disabled */ do { @@ -3792,19 +3779,19 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { __IO uint32_t count; - + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - + /* Check TXEIE is disabled */ do { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h index 2e51ffb9895..3aa540374e7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -398,16 +396,16 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -417,9 +415,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI handle. + * @param __HANDLE__ specifies the SPI handle. * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to disable. + * @param __INTERRUPT__ specifies the interrupt source to disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -429,9 +427,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -441,9 +439,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -459,14 +457,14 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -479,7 +477,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -492,7 +490,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -504,14 +502,14 @@ typedef struct __SPI_HandleTypeDef }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -527,90 +525,168 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) - -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_1LINE)) +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_15BIT) || \ - ((DATASIZE) == SPI_DATASIZE_14BIT) || \ - ((DATASIZE) == SPI_DATASIZE_13BIT) || \ - ((DATASIZE) == SPI_DATASIZE_12BIT) || \ - ((DATASIZE) == SPI_DATASIZE_11BIT) || \ - ((DATASIZE) == SPI_DATASIZE_10BIT) || \ - ((DATASIZE) == SPI_DATASIZE_9BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT) || \ - ((DATASIZE) == SPI_DATASIZE_7BIT) || \ - ((DATASIZE) == SPI_DATASIZE_6BIT) || \ - ((DATASIZE) == SPI_DATASIZE_5BIT) || \ - ((DATASIZE) == SPI_DATASIZE_4BIT)) +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) -#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ - ((NSSP) == SPI_NSS_PULSE_DISABLE)) +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ - ((MODE) == SPI_TIMODE_ENABLE)) +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_16BIT)) +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c index 543a289eb7f..813a8ff429e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : @@ -65,7 +63,7 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions * @{ @@ -90,8 +88,8 @@ */ /** - * @brief Flush the RX fifo. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h index 1835b59de39..99261d60be6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SPI HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c index caec73775b8..69aa39213e1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sram.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -95,7 +93,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -695,5 +694,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h index 4c3cb948f3a..9eea5ab71ba 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sram.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -192,6 +191,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c index 19e029ec238..68b13096880 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_swpmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SWPMI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Single Wire Protocol Master Interface (SWPMI). diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h index 1f78f9d82e4..2df60ff9ac0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_swpmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SWPMI HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c index 3b2fd25ce5d..f60505f99ca 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -192,7 +190,11 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Base handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) @@ -207,6 +209,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -231,7 +234,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM Base peripheral - * @param htim: TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) @@ -258,7 +261,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -273,7 +276,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Base MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -289,7 +292,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) @@ -312,7 +315,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) @@ -335,7 +338,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) @@ -355,7 +358,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) @@ -374,9 +377,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -420,7 +423,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) @@ -469,7 +472,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Output Compare handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) @@ -484,6 +491,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -508,7 +516,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) @@ -535,7 +543,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -550,7 +558,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -565,8 +573,8 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -599,8 +607,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -633,8 +641,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -701,8 +709,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -769,8 +777,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -778,8 +786,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -890,8 +898,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -987,7 +995,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) @@ -1002,6 +1014,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1026,7 +1039,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1053,7 +1066,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1068,7 +1081,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM PWM MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1083,8 +1096,8 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1117,8 +1130,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1154,8 +1167,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1220,8 +1233,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1286,15 +1299,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1405,8 +1418,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1500,7 +1513,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Input Capture handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) @@ -1515,6 +1532,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1539,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) @@ -1566,7 +1584,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1581,7 +1599,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Input Capture MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) @@ -1596,8 +1614,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1622,8 +1640,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1648,8 +1666,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1707,8 +1725,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1767,15 +1785,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1881,9 +1899,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /** - * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1971,8 +1989,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM OnePulse handle - * @param OnePulseMode: Select the One pulse mode. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -1991,6 +2013,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -2021,7 +2044,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitialize the TIM One Pulse - * @param htim: TIM One Pulse handle + * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) @@ -2048,7 +2071,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2063,7 +2086,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2078,8 +2101,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2114,8 +2137,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2150,8 +2173,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2192,8 +2215,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2258,8 +2281,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Encoder Interface configuration structure + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2276,6 +2303,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2349,7 +2379,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitialize the TIM Encoder interface - * @param htim: TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2376,7 +2406,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2391,7 +2421,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2406,8 +2436,8 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2433,7 +2463,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); } break; - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2450,8 +2480,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2461,9 +2491,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1 and 2 + /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { @@ -2472,13 +2502,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); } break; - + case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); } break; - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -2496,8 +2526,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2519,14 +2549,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2546,8 +2576,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2597,15 +2627,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2717,8 +2747,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2784,7 +2814,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) @@ -2940,9 +2970,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to configure + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2973,7 +3003,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 1 in Output Compare */ + /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); } break; @@ -2991,7 +3021,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, case TIM_CHANNEL_3: { /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); @@ -3042,9 +3072,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: TIM IC handle - * @param sConfig: TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3139,9 +3169,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM PWM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be configured + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3284,13 +3314,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: TIM One Pulse handle - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled + * @param InputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3306,89 +3336,90 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O if(OutputChannel != InputChannel) { - /* Process Locked */ - __HAL_LOCK(htim); + /* Process Locked */ + __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; + /* Extract the Ouput compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) - { - case TIM_CHANNEL_1: { + case TIM_CHANNEL_1: + { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { + TIM_OC1_SetConfig(htim->Instance, &temp1); + } + break; + case TIM_CHANNEL_2: + { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - TIM_OC2_SetConfig(htim->Instance, &temp1); + TIM_OC2_SetConfig(htim->Instance, &temp1); + } + break; + default: + break; } - break; - default: - break; - } + switch (InputChannel) - { - case TIM_CHANNEL_1: { + case TIM_CHANNEL_1: + { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ + /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + case TIM_CHANNEL_2: + { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC2PSC Bits */ + /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - /* Select the Trigger source */ + /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; + htim->Instance->SMCR |= TIM_TS_TI2FP2; - /* Select the Slave Mode */ + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; - default: - break; - } + default: + break; + } - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); - return HAL_OK; -} + return HAL_OK; + } else { return HAL_ERROR; @@ -3397,8 +3428,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3419,7 +3450,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3428,8 +3459,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ @@ -3560,8 +3591,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3620,8 +3651,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3642,7 +3673,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3651,8 +3682,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ @@ -3784,8 +3815,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3844,8 +3875,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: TIM handle - * @param EventSource: specifies the event source. + * @param htim TIM handle + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3856,7 +3887,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) @@ -3885,10 +3916,10 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 @@ -3917,7 +3948,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - + /* Clear the OCREF clear selection bit */ tmpsmcr &= ~TIM_SMCR_OCCS; @@ -3952,7 +3983,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, htim->Instance->SMCR |= TIM_SMCR_OCCS; } break; - + default: break; } @@ -4054,8 +4085,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /** * @brief Configures the clock source to be used - * @param htim: TIM handle - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4096,7 +4127,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -4122,7 +4153,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -4141,20 +4172,20 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); } break; - + case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - /* Check TI2 input conditioning related parameters */ + /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); @@ -4180,7 +4211,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); } break; - + case TIM_CLOCKSOURCE_ITR0: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4189,7 +4220,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); } break; - + case TIM_CLOCKSOURCE_ITR1: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4198,7 +4229,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); } break; - + case TIM_CLOCKSOURCE_ITR2: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4207,7 +4238,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); } break; - + case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4230,8 +4261,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: TIM handle. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4264,8 +4295,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4283,7 +4314,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI htim->State = HAL_TIM_STATE_BUSY; TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - + /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); @@ -4292,28 +4323,28 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - + __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; @@ -4328,15 +4359,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit - * @param htim: TIM handle. - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4428,7 +4459,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -4443,7 +4474,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non-blocking mode - * @param htim : TIM OC handle + * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -4457,7 +4488,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non-blocking mode - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) @@ -4472,7 +4503,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -4487,7 +4518,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -4502,7 +4533,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) @@ -4536,7 +4567,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base handle state. - * @param htim: TIM Base handle + * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) @@ -4546,7 +4577,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC handle state. - * @param htim: TIM Ouput Compare handle + * @param htim TIM Ouput Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4556,7 +4587,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM handle state. - * @param htim: TIM handle + * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) @@ -4566,7 +4597,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture handle state. - * @param htim: TIM IC handle + * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) @@ -4576,7 +4607,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode handle state. - * @param htim: TIM OPM handle + * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) @@ -4586,7 +4617,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode handle state. - * @param htim: TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4600,7 +4631,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) @@ -4614,7 +4645,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) @@ -4646,7 +4677,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) } /** * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) @@ -4679,7 +4710,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4693,7 +4724,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) @@ -4707,8 +4738,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: TIM Base configuration structure + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4731,6 +4762,10 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= (uint32_t)Structure->ClockDivision; } + /* Set the auto-reload preload */ + tmpcr1 &= ~TIM_CR1_ARPE; + tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; + TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ @@ -4753,7 +4788,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Time Ouput Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4827,7 +4862,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4903,7 +4938,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4977,7 +5012,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5035,7 +5070,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Ouput Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -5088,7 +5123,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Ouput Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -5161,7 +5196,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - + /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { @@ -5173,91 +5208,91 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - + tmpccmr1 = htim->Instance->CCMR1; + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - + /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - + htim->Instance->CCER = tmpccer; + } break; - + case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_ITR0: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR1: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR2: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + default: break; } @@ -5266,17 +5301,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 @@ -5321,12 +5356,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5356,17 +5391,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 @@ -5404,12 +5439,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5439,17 +5474,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 @@ -5487,17 +5522,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be @@ -5535,7 +5570,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param InputTriggerSource: The Input Trigger source. + * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5563,17 +5598,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ @@ -5597,7 +5632,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h index 368389fdd2a..bfc0194b005 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -85,6 +83,9 @@ typedef struct - the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** @@ -463,20 +464,20 @@ typedef struct * @} */ -/** @defgroup TIM_Output_Compare_State TIM Output Compare State +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) +#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ /** * @} */ -/** @defgroup TIM_Output_Fast_State TIM Output Fast State +/** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) /** * @} */ @@ -490,6 +491,15 @@ typedef struct * @} */ +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +/** + * @} + */ + /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ @@ -593,9 +603,9 @@ typedef struct * @} */ -/** @defgroup TIM_Commutation_Source TIM Commutation Source +/** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ - */ + */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) /** @@ -656,16 +666,16 @@ typedef struct /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) /** * @} */ @@ -781,7 +791,7 @@ typedef struct * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) /** * @} */ @@ -800,14 +810,14 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) /** * @} */ @@ -815,22 +825,22 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) -#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) -#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) -#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_RESET ((uint32_t)0x00000000) +#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) +#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) +#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) +#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) /** * @} */ @@ -999,28 +1009,28 @@ typedef struct */ /** @brief Reset TIM handle state. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -1036,7 +1046,7 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ @@ -1053,15 +1063,15 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1077,8 +1087,8 @@ typedef struct /** @brief Disable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1093,8 +1103,8 @@ typedef struct #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1103,14 +1113,13 @@ typedef struct * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @arg TIM_DMA_BREAK: Break DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1119,14 +1128,13 @@ typedef struct * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @arg TIM_DMA_BREAK: Break DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1134,11 +1142,11 @@ typedef struct * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1149,8 +1157,8 @@ typedef struct #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1158,11 +1166,11 @@ typedef struct * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1174,8 +1182,8 @@ typedef struct /** * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1190,8 +1198,8 @@ typedef struct #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1207,7 +1215,7 @@ typedef struct /** * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1217,32 +1225,32 @@ mode. /** * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the Prescaler new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1253,20 +1261,20 @@ mode. /** * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ @@ -1278,22 +1286,25 @@ mode. /** * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1309,14 +1320,18 @@ mode. /** * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ @@ -1326,8 +1341,8 @@ mode. /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1335,7 +1350,7 @@ mode. * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1348,8 +1363,8 @@ mode. /** * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value @@ -1357,7 +1372,7 @@ mode. * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_5: get capture/compare 5 register value * @arg TIM_CHANNEL_6: get capture/compare 6 register value - * @retval None + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ @@ -1367,10 +1382,52 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__: TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None @@ -1380,9 +1437,9 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__: TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit @@ -1391,17 +1448,17 @@ mode. */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - + /** * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge @@ -1412,7 +1469,7 @@ mode. TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) - + /** * @} */ @@ -1430,7 +1487,7 @@ mode. * @} */ /* End of private constants --------------------------------------------------*/ - + /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ @@ -1466,7 +1523,7 @@ mode. ((__BASE__) == TIM_DMABASE_OR3)) -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ @@ -1479,6 +1536,9 @@ mode. ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ ((__STATE__) == TIM_OCFAST_ENABLE)) @@ -1514,7 +1574,7 @@ mode. ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1963,7 +2023,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); /** * @} -*/ +*/ /* End of private functions --------------------------------------------------*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c index 39039e4c42f..754c1a71165 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -113,7 +111,7 @@ /* Private define ------------------------------------------------------------*/ #define BDTR_BKF_SHIFT (16) #define BDTR_BK2F_SHIFT (20) -#define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000) +#define TIMx_ETRSEL_MASK ((uint32_t)0x0003C000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -150,8 +148,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Hall Sensor configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -164,9 +162,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen return HAL_ERROR; } - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -229,7 +228,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitialize the TIM Hall Sensor interface - * @param htim: TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -256,7 +255,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -271,7 +270,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -286,16 +285,16 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral */ @@ -307,16 +306,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -328,19 +327,19 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral */ @@ -352,16 +351,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -376,15 +375,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM Hall Sensor handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -401,8 +400,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 htim->State = HAL_TIM_STATE_BUSY; } } - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callback */ @@ -425,16 +424,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -475,13 +474,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -505,13 +503,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -535,13 +532,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -585,7 +581,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -602,13 +598,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -675,15 +670,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -792,13 +786,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -892,13 +885,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -921,13 +913,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -951,13 +942,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1018,13 +1008,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1071,7 +1060,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) @@ -1092,15 +1081,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1209,13 +1197,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1298,8 +1285,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1323,8 +1310,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1352,8 +1339,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1383,8 +1370,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1447,15 +1434,15 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1496,15 +1483,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1549,15 +1536,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1601,8 +1588,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: TIM handle. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1663,8 +1650,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: TIM handle - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1672,7 +1659,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) { uint32_t tmpbdtr = 0; - + /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); @@ -1683,13 +1670,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - + /* Check input state */ __HAL_LOCK(htim); - + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); @@ -1700,22 +1687,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); - + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { + /* Check the parameters */ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - + /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } - + /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; - + __HAL_UNLOCK(htim); return HAL_OK; @@ -1723,12 +1711,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the break input source. - * @param htim: TIM handle. - * @param BreakInput: Break input to configure + * @param htim TIM handle. + * @param BreakInput Break input to configure * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig: Break input source configuration + * @param sBreakInputConfig Break input source configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, @@ -1748,22 +1736,24 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) { assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); } #else assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Check input state */ __HAL_LOCK(htim); - + switch(sBreakInputConfig->Source) { case TIM_BREAKINPUTSOURCE_BKIN: @@ -1791,81 +1781,87 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, } break; -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) case TIM_BREAKINPUTSOURCE_DFSDM1: { bkin_enable_mask = TIM1_OR2_BKDF1BK0E; bkin_enable_bitpos = 8; } - break; -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ + break; +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ default: break; } - + switch(BreakInput) { case TIM_BREAKINPUT_BRK: { /* Get the TIMx_OR2 register value */ tmporx = htim->Instance->OR2; - + /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - + /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } - + /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmporx; + htim->Instance->OR2 = tmporx; } break; case TIM_BREAKINPUT_BRK2: { /* Get the TIMx_OR3 register value */ tmporx = htim->Instance->OR3; - + /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - + /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } - + /* Set TIMx_OR3 */ - htim->Instance->OR3 = tmporx; + htim->Instance->OR3 = tmporx; } - break; + break; default: break; } - + __HAL_UNLOCK(htim); return HAL_OK; @@ -1873,7 +1869,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /** * @brief Configures the TIMx Remapping input capabilities. - * @param htim: TIM handle. + * @param htim TIM handle. * @param Remap: specifies the TIM remapping source. * @if STM32L486xx @@ -1898,7 +1894,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * field4 can have the following values: * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant + * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant @endif @if STM32L443xx * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3): @@ -1917,7 +1913,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output * - * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant + * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant * @endif @if STM32L486xx @@ -1995,7 +1991,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * field4 can have the following values: * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant + * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant * @endif * For TIM15, the parameter is a combination of 3 fields (field1 | field2): @@ -2005,7 +2001,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE * * field2 can have the following values: - * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection + * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively @@ -2042,34 +2038,31 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { uint32_t tmpor1 = 0; uint32_t tmpor2 = 0; - + __HAL_LOCK(htim); /* Check parameters */ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); assert_param(IS_TIM_REMAP(Remap)); - + /* Set ETR_SEL bit field (if required) */ if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) { tmpor2 = htim->Instance->OR2; tmpor2 &= ~TIMx_ETRSEL_MASK; tmpor2 |= (Remap & TIMx_ETRSEL_MASK); - + /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmpor2; + htim->Instance->OR2 = tmpor2; } - + /* Set other remapping capabilities */ tmpor1 = Remap; tmpor1 &= ~TIMx_ETRSEL_MASK; /* Set TIMx_OR1 */ - htim->Instance->OR1 = Remap; - - /* Set TIMx_OR1 */ - htim->Instance->OR1 = tmpor1; - + htim->Instance->OR1 = tmpor1; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); @@ -2079,8 +2072,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim: TIM handle. - * @param Channels: specifies the reference signal(s) the OC5REF is combined with. + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF @@ -2134,7 +2127,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Hall commutation changed callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) @@ -2149,7 +2142,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) @@ -2183,7 +2176,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface handle state. - * @param htim: TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) @@ -2197,7 +2190,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) @@ -2212,12 +2205,12 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h index 61df2f10dd4..eae1c9a328b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention @@ -59,28 +57,28 @@ * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; -/** - * @brief TIM Break/Break2 input configuration +/** + * @brief TIM Break/Break2 input configuration */ typedef struct { uint32_t Source; /*!< Specifies the source of the timer break input. @@ -119,15 +117,18 @@ typedef struct { /* STM32L496xx || STM32L4A6xx */ #define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ +#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ #define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ @@ -145,7 +146,8 @@ typedef struct { #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ #define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ @@ -154,7 +156,8 @@ typedef struct { #define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) @@ -166,12 +169,19 @@ typedef struct { #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ -#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ -#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ #define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ +#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ +#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ #define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ @@ -179,16 +189,20 @@ typedef struct { #define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ #define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ @@ -205,13 +219,15 @@ typedef struct { /* STM32L496xx || STM32L4A6xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ #define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ #define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -233,11 +249,13 @@ typedef struct { #define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -259,7 +277,7 @@ typedef struct { /** * @} */ - + /** * @} */ @@ -286,7 +304,8 @@ typedef struct { #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ @@ -295,7 +314,9 @@ typedef struct { #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) @@ -312,7 +333,7 @@ typedef struct { * @{ */ -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ @@ -409,7 +430,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ @@ -420,7 +441,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ @@ -452,7 +473,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c index d0aad5aba10..ffb54c8bb12 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tsc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and De-initialization diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h index f1c3386132a..32f5bb622b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tsc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TSC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c index 206c426c907..8aa955c8597 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -31,8 +29,9 @@ (+++) Enable the NVIC USART IRQ handle. (++) UART interrupts handling: -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) are managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes. + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() and HAL_UART_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. @@ -42,7 +41,7 @@ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) @@ -118,11 +117,28 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#if defined(USART_CR1_FIFOEN) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#else +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#endif + +#if defined(USART_CR1_FIFOEN) +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#else +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#endif + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ -#define UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */ -#define UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */ /** * @} */ @@ -145,9 +161,20 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +#if defined(USART_CR1_FIFOEN) +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +#endif +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +#if defined(USART_CR1_FIFOEN) +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +#endif + /** * @} */ @@ -220,8 +247,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /** * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -231,7 +258,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* Check the parameters */ @@ -242,49 +269,49 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -294,47 +321,47 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -342,9 +369,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. * This parameter can be one of the following values: * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection @@ -357,12 +384,12 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe { return HAL_ERROR; } - + /* Check the LIN UART instance */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - + /* LIN mode limited to 16-bit oversampling only */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) { @@ -373,47 +400,47 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe { return HAL_ERROR; } - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - + /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -421,10 +448,10 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. * This parameter can be one of the following values: * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark @@ -444,53 +471,53 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add { return HAL_ERROR; } - + /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { /* If address mark wake up method is chosen, set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); } - + /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -498,7 +525,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitialize the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -508,42 +535,42 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; - + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + /* Process Unlock */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Initialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file */ @@ -551,14 +578,14 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) /** * @brief DeInitialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspDeInit can be implemented in the user file */ @@ -647,39 +674,43 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; + + huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + + while(huart->TxXferCount > 0U) { - huart->TxXferCount--; if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; @@ -687,25 +718,27 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pData += 2U; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } + huart->TxXferCount--; } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -716,10 +749,14 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -727,35 +764,34 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uint16_t* tmp; uint16_t uhMask; uint32_t tickstart = 0; - + /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; + + huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; - + /* as long as data have to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { - huart->RxXferCount--; if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; @@ -764,20 +800,21 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); } + huart->RxXferCount--; } - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -788,9 +825,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -798,27 +835,66 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->TxISR = NULL; + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Transmit Data Register Empty Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - + +#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else +#endif + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +#endif + } + return HAL_OK; } else @@ -829,9 +905,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -839,33 +915,73 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; huart->RxXferCount = Size; - + huart->RxISR = NULL; + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART Parity Error and Data Register not empty Interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - + +#if defined(USART_CR1_FIFOEN) + /* Configure Rx interrupt processing*/ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else +#endif + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +#else + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif + } + return HAL_OK; } else @@ -876,9 +992,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -886,46 +1002,46 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - + /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; - + /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; - + /* Enable the UART transmit DMA channel */ HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); - + /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ + in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + return HAL_OK; } else @@ -936,9 +1052,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @retval HAL status @@ -948,48 +1064,48 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - + /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; - + /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ + in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + return HAL_OK; } else @@ -1000,14 +1116,14 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pause the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { @@ -1020,27 +1136,27 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the UART DMA Rx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Resume the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ @@ -1050,65 +1166,65 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the UART DMA Rx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Stop the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + /* Stop UART DMA Tx request if ongoing */ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel */ if(huart->hdmatx != NULL) { HAL_DMA_Abort(huart->hdmatx); } - + UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ if(huart->hdmarx != NULL) { HAL_DMA_Abort(huart->hdmarx); } - + UART_EndRxTransfer(huart); } - + return HAL_OK; } @@ -1127,55 +1243,70 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmatx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmatx); } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmarx); } } - + /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + return HAL_OK; } @@ -1194,30 +1325,42 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmatx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmatx); } } - + /* Reset Tx transfer counter */ - huart->TxXferCount = 0; - + huart->TxXferCount = 0U; + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + return HAL_OK; } @@ -1236,34 +1379,41 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmarx); } } - + /* Reset Rx transfer counter */ - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + return HAL_OK; } @@ -1283,10 +1433,14 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { - uint32_t abortcplt = 1; + uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -1325,7 +1479,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { /* Disable DMA Tx at UART level */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmatx != NULL) { @@ -1339,16 +1493,16 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } else { - abortcplt = 0; + abortcplt = 0U; } } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmarx != NULL) { @@ -1359,36 +1513,51 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } - + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortCpltCallback(huart); } - + return HAL_OK; } @@ -1409,20 +1578,24 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmatx != NULL) { /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - + /* Abort DMA TX */ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) { @@ -1433,11 +1606,14 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0; - + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortTransmitCpltCallback(huart); } @@ -1445,15 +1621,26 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0; + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortTransmitCpltCallback(huart); } - + return HAL_OK; } @@ -1474,21 +1661,25 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { @@ -1499,14 +1690,20 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else { /* Reset Rx transfer counter */ - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortReceiveCpltCallback(huart); } @@ -1514,115 +1711,144 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else { /* Reset Rx transfer counter */ - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortReceiveCpltCallback(huart); } - + return HAL_OK; } /** * @brief Handle UART interrupt request. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { uint32_t isrflags = READ_REG(huart->Instance->ISR); uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its; + uint32_t cr3its = READ_REG(huart->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); if (errorflags == RESET) { /* UART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - UART_Receive_IT(huart); + if (huart->RxISR != NULL) {huart->RxISR(huart);} return; } } - + /* If some errors occur */ - cr3its = READ_REG(huart->Instance->CR3); +#if defined(USART_CR1_FIFOEN) + if( (errorflags != RESET) + && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) +#else if( (errorflags != RESET) && ( ((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +#endif { /* UART parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + huart->ErrorCode |= HAL_UART_ERROR_PE; } - + /* UART frame error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + huart->ErrorCode |= HAL_UART_ERROR_FE; } - + /* UART noise error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + huart->ErrorCode |= HAL_UART_ERROR_NE; } /* UART Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) +#else + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || + ((cr3its & USART_CR3_EIE) != RESET))) +#endif { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + huart->ErrorCode |= HAL_UART_ERROR_ORE; } - + /* Call UART Error Call back function if need be --------------------------*/ if(huart->ErrorCode != HAL_UART_ERROR_NONE) { /* UART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - UART_Receive_IT(huart); + if (huart->RxISR != NULL) {huart->RxISR(huart);} } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + consider error as blocking */ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { + { /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { @@ -1645,46 +1871,67 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ HAL_UART_ErrorCallback(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - cr3its = READ_REG(huart->Instance->CR3); if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); /* Set the UART state ready to be able to start again the process */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; HAL_UARTEx_WakeupCallback(huart); return; } - + /* UART in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - UART_Transmit_IT(huart); +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif + { + if (huart->TxISR != NULL) {huart->TxISR(huart);} return; } - + /* UART in mode Transmitter (transmission end) -----------------------------*/ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); return; } - + +#if defined(USART_CR1_FIFOEN) + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + { + HAL_UARTEx_TxFifoEmptyCallback(huart); + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + { + HAL_UARTEx_RxFifoFullCallback(huart); + return; + } +#endif } /** * @brief Tx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1699,14 +1946,14 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1714,14 +1961,14 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ @@ -1729,14 +1976,14 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ @@ -1744,7 +1991,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1818,9 +2065,11 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) UART_SetConfig() API configures the UART peripheral (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver (+) HAL_LIN_SendBreak() API transmits the break characters @@ -1831,49 +2080,49 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Enable USART mute mode by setting the MME bit in the CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart: UART handle. + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** * @brief Enter UART mute mode (means UART actually enters mute mode). * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -1883,7 +2132,7 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) @@ -1891,23 +2140,24 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -1915,47 +2165,48 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Transmit break characters. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Send break characters */ - huart->Instance->RQR |= UART_SENDBREAK_REQUEST; - + SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } - /** * @} */ @@ -1977,25 +2228,25 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** - * @brief Return the UART handle state. + * @brief Return the UART handle state. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. + * the configuration information for the specified UART. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1= 0x00, temp2 = 0x00; + uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = huart->gState; temp2 = huart->RxState; - + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** - * @brief Return the UART handle error code. +* @brief Return the UART handle error code. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code + * the configuration information for the specified UART. +* @retval UART Error Code */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { @@ -2015,99 +2266,126 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp = 0x0000U; + uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; - + uint32_t lpuart_ker_ck_pres = 0x00000000U; + /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); if(UART_INSTANCE_LOWPOWER(huart)) { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); } else { assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); } - + assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); +#endif + /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); - + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ + * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - + /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) */ + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) + * - set TXFTCFG bit according to huart->Init.TxFifoThreshold value + * - set RXFTCFG bit according to huart->Init.RxFifoThreshold value */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; + if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; } - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); - + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + +#if defined(USART_PRESC_PRESCALER) + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); +#endif + /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - + /* Check LPUART instance */ if(UART_INSTANCE_LOWPOWER(huart)) { /* Retrieve frequency clock */ - tmpreg = 0; - switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - tmpreg = HAL_RCC_GetPCLK1Freq(); +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq()/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); +#endif break; case UART_CLOCKSOURCE_HSI: - tmpreg = (uint32_t) HSI_VALUE; +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; +#endif break; case UART_CLOCKSOURCE_SYSCLK: - tmpreg = HAL_RCC_GetSysClockFreq(); +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq()/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); +#endif break; case UART_CLOCKSOURCE_LSE: - tmpreg = (uint32_t) LSE_VALUE; +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } - + /* if proper clock source reported */ - if (tmpreg != 0) + if (lpuart_ker_ck_pres != 0U) { /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ( (tmpreg < (3 * huart->Init.BaudRate) ) || - (tmpreg > (4096 * huart->Init.BaudRate) )) + if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) { ret = HAL_ERROR; } @@ -2116,26 +2394,43 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_HSI: - tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_SYSCLK: - tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_LSE: - tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; } - - if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX)) + + /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { - huart->Instance->BRR = tmpreg; + huart->Instance->BRR = usartdiv; } else { @@ -2150,112 +2445,179 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_PCLK2: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_HSI: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_SYSCLK: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_LSE: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } - - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); - huart->Instance->BRR = brrtemp; + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } else { switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_PCLK2: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_HSI: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_SYSCLK: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_LSE: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } } - + +#if defined(USART_CR1_FIFOEN) + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; +#endif + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + return ret; - } /** * @brief Configure the UART peripheral advanced features. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - + /* if required, configure TX pin active level inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); } - + /* if required, configure RX pin active level inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); } - + /* if required, configure data inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - + /* if required, configure RX/TX pins swap */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); } - + /* if required, configure RX overrun detection disabling */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } - + /* if required, configure DMA disabling on reception error */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } - + /* if required, configure auto Baud rate detection scheme */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { @@ -2269,7 +2631,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); } } - + /* if required, configure MSB first on communication line */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) { @@ -2285,14 +2647,14 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Check if the Transmitter is enabled */ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { @@ -2313,24 +2675,24 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) return HAL_TIMEOUT; } } - + /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Handle UART Communication Timeout. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) @@ -2341,17 +2703,22 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; + + huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); + return HAL_TIMEOUT; } } @@ -2362,13 +2729,17 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -2377,17 +2748,24 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; } @@ -2402,13 +2780,13 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - huart->TxXferCount = 0; - + { + huart->TxXferCount = 0U; + /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ + in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } @@ -2417,7 +2795,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { HAL_UART_TxCpltCallback(huart); } - } /** @@ -2428,7 +2805,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + HAL_UART_TxHalfCpltCallback(huart); } @@ -2440,24 +2817,24 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; } - + HAL_UART_RxCpltCallback(huart); } @@ -2469,7 +2846,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + HAL_UART_RxHalfCpltCallback(huart); } @@ -2481,23 +2858,23 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + /* Stop UART DMA Tx request if ongoing */ if ( (huart->gState == HAL_UART_STATE_BUSY_TX) &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) { - huart->RxXferCount = 0; + huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } - + huart->ErrorCode |= HAL_UART_ERROR_DMA; HAL_UART_ErrorCallback(huart); } @@ -2505,15 +2882,15 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication abort callback, when initiated by HAL services on Error * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - huart->RxXferCount = 0; - huart->TxXferCount = 0; - + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + HAL_UART_ErrorCallback(huart); } @@ -2530,7 +2907,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); huart->hdmatx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ if(huart->hdmarx != NULL) { @@ -2541,19 +2918,27 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortCpltCallback(huart); } @@ -2572,7 +2957,7 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); huart->hdmarx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ if(huart->hdmatx != NULL) { @@ -2583,19 +2968,22 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortCpltCallback(huart); } @@ -2612,12 +3000,20 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - huart->TxXferCount = 0; - + + huart->TxXferCount = 0U; + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortTransmitCpltCallback(huart); } @@ -2633,139 +3029,408 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - huart->RxXferCount = 0; - + + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortReceiveCpltCallback(huart); } /** - * @brief Send an amount of data in interrupt mode. + * @brief TX interrrupt handler for 7 or 8 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval HAL status + * @param huart UART handle. + * @retval None */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if(huart->TxXferCount == 0) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +#endif + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->TxXferCount--; + } + } +} +/** + * @brief TX interrrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { if(huart->TxXferCount == 0) { /* Disable the UART Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +#endif /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; } else { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2; + huart->TxXferCount--; + } + } +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(huart->TxXferCount == 0U) { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; + /* Disable the TX FIFO threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ } - else + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->TxXferCount--; } - huart->TxXferCount--; - - return HAL_OK; } } - else +} + +/** + * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) { - return HAL_BUSY; + for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } } } +#endif /** * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + HAL_UART_TxCpltCallback(huart); +} - return HAL_OK; +/** + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + + if(--huart->RxXferCount == 0) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + HAL_UART_RxCpltCallback(huart); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } } /** - * @brief Receive an amount of data in interrupt mode. + * @brief RX interrrupt handler for 9 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval HAL status + * @param huart UART handle. + * @retval None */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { uint16_t* tmp; - uint16_t uhMask = huart->Mask; + uint16_t uhMask = huart->Mask; uint16_t uhdata; - + /* Check that a Rx process is ongoing */ if(huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - } - else - { - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - } - + tmp = (uint16_t*) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr +=2; + if(--huart->RxXferCount == 0) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - +#endif + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; HAL_UART_RxCpltCallback(huart); - - return HAL_OK; } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} - return HAL_OK; +#if defined(USART_CR1_FIFOEN) +/** + * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) + { + for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->RxXferCount--; + + if(huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + HAL_UART_RxCpltCallback(huart); + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} - return HAL_BUSY; +/** + * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) + { + for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t*) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr +=2; + huart->RxXferCount--; + + if(huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + HAL_UART_RxCpltCallback(huart); + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } +#endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h index d4b5cfa2b59..34e100955fe 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -66,12 +64,19 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: + UART: + ===== - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + + where (uart/lpuart)_ker_ck_pres is the UART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref UARTEx_Word_Length. */ @@ -99,6 +104,12 @@ typedef struct uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ +#endif + }UART_InitTypeDef; /** @@ -207,13 +218,12 @@ typedef enum */ typedef enum { - HAL_UART_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_UART_ERROR_BUSY = 0x20 /*!< Busy Error */ + HAL_UART_ERROR_NONE = 0x00U, /*!< No error */ + HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */ + HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */ + HAL_UART_ERROR_FE = 0x04U, /*!< frame error */ + HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */ + HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */ }HAL_UART_ErrorTypeDef; /** @@ -221,53 +231,71 @@ typedef enum */ typedef enum { - UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }UART_ClockSourceTypeDef; /** * @brief UART handle Structure definition */ -typedef struct +typedef struct __UART_HandleTypeDef { - USART_TypeDef *Instance; /*!< UART registers base address */ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ - UART_InitTypeDef Init; /*!< UART communication parameters */ + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferSize; /*!< UART Tx Transfer size */ + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferSize; /*!< UART Rx Transfer size */ + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + uint16_t Mask; /*!< UART Rx RDR register mask */ - uint16_t Mask; /*!< UART Rx RDR register mask */ +#if defined(USART_CR1_FIFOEN) + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ +#endif + +#if defined(USART_CR2_SLVEN) + uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. + This parameter can be a value of @ref UARTEx_Slave_Mode. */ +#endif - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - HAL_LockTypeDef Lock; /*!< Locking object */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - __IO uint32_t ErrorCode; /*!< UART Error code */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ }UART_HandleTypeDef; @@ -284,7 +312,7 @@ typedef struct * @{ */ #define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 ((uint32_t)0x00000000) /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ #define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ #define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ /** @@ -294,9 +322,9 @@ typedef struct /** @defgroup UART_Parity UART Parity * @{ */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ /** * @} */ @@ -304,10 +332,10 @@ typedef struct /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */ -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */ -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ /** * @} */ @@ -315,9 +343,9 @@ typedef struct /** @defgroup UART_Mode UART Transfer Mode * @{ */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ @@ -325,8 +353,8 @@ typedef struct /** @defgroup UART_State UART State * @{ */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */ -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ /** * @} */ @@ -334,8 +362,8 @@ typedef struct /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} */ @@ -343,19 +371,40 @@ typedef struct /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +#if defined(USART_PRESC_PRESCALER) +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ /** * @} */ +#endif /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ /** * @} */ @@ -363,8 +412,8 @@ typedef struct /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ /** * @} */ @@ -372,8 +421,8 @@ typedef struct /** @defgroup UART_LIN UART Local Interconnection Network mode * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ /** * @} */ @@ -381,8 +430,8 @@ typedef struct /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ /** * @} */ @@ -390,8 +439,8 @@ typedef struct /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ /** * @} */ @@ -399,8 +448,8 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ /** * @} */ @@ -408,8 +457,8 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ /** * @} */ @@ -417,8 +466,8 @@ typedef struct /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ /** * @} */ @@ -426,11 +475,11 @@ typedef struct /** @defgroup UART_Request_Parameters UART Request Parameters * @{ */ -#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ /** * @} */ @@ -438,15 +487,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ /** * @} */ @@ -454,8 +503,8 @@ typedef struct /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ /** * @} */ @@ -463,8 +512,8 @@ typedef struct /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ @@ -472,8 +521,8 @@ typedef struct /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ /** * @} */ @@ -481,8 +530,8 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ /** * @} */ @@ -490,8 +539,8 @@ typedef struct /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ @@ -499,8 +548,8 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ /** * @} */ @@ -508,8 +557,8 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ /** * @} */ @@ -517,8 +566,8 @@ typedef struct /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ /** * @} */ @@ -526,8 +575,8 @@ typedef struct /** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable * @{ */ -#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ /** * @} */ @@ -535,8 +584,8 @@ typedef struct /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ /** * @} */ @@ -544,7 +593,7 @@ typedef struct /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -552,9 +601,9 @@ typedef struct /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000) /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ /** * @} */ @@ -562,8 +611,8 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ /** * @} */ @@ -571,7 +620,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ /** * @} */ @@ -579,7 +628,7 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ /** * @} */ @@ -587,7 +636,7 @@ typedef struct /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ */ -#define UART_IT_MASK ((uint32_t)0x001F) /*!< UART interruptions flags mask */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ /** * @} */ @@ -595,7 +644,7 @@ typedef struct /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value * @{ */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /*!< UART polling-based communications time-out value */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ /** * @} */ @@ -605,28 +654,40 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define UART_FLAG_REACK ((uint32_t)0x00400000) /*!< UART receive enable acknowledge flag */ -#define UART_FLAG_TEACK ((uint32_t)0x00200000) /*!< UART transmit enable acknowledge flag */ -#define UART_FLAG_WUF ((uint32_t)0x00100000) /*!< UART wake-up from stop mode flag */ -#define UART_FLAG_RWU ((uint32_t)0x00080000) /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF ((uint32_t)0x00040000) /*!< UART send break flag */ -#define UART_FLAG_CMF ((uint32_t)0x00020000) /*!< UART character match flag */ -#define UART_FLAG_BUSY ((uint32_t)0x00010000) /*!< UART busy flag */ -#define UART_FLAG_ABRF ((uint32_t)0x00008000) /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE ((uint32_t)0x00004000) /*!< UART auto Baud rate error */ -#define UART_FLAG_EOBF ((uint32_t)0x00001000) /*!< UART end of block flag */ -#define UART_FLAG_RTOF ((uint32_t)0x00000800) /*!< UART receiver timeout flag */ -#define UART_FLAG_CTS ((uint32_t)0x00000400) /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF ((uint32_t)0x00000100) /*!< UART LIN break detection flag */ -#define UART_FLAG_TXE ((uint32_t)0x00000080) /*!< UART transmit data register empty */ -#define UART_FLAG_TC ((uint32_t)0x00000040) /*!< UART transmission complete */ -#define UART_FLAG_RXNE ((uint32_t)0x00000020) /*!< UART read data register not empty */ -#define UART_FLAG_IDLE ((uint32_t)0x00000010) /*!< UART idle flag */ -#define UART_FLAG_ORE ((uint32_t)0x00000008) /*!< UART overrun error */ -#define UART_FLAG_NE ((uint32_t)0x00000004) /*!< UART noise error */ -#define UART_FLAG_FE ((uint32_t)0x00000002) /*!< UART frame error */ -#define UART_FLAG_PE ((uint32_t)0x00000001) /*!< UART parity error */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#if defined(USART_CR1_FIFOEN) +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#else +#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ +#endif +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#if defined(USART_CR1_FIFOEN) +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#else +#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ +#endif +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ /** * @} */ @@ -641,19 +702,41 @@ typedef struct * - ZZZZZ : Flag position in the ISR register(5bits) * @{ */ -#define UART_IT_PE ((uint32_t)0x0028) /*!< UART parity error interruption */ -#define UART_IT_TXE ((uint32_t)0x0727) /*!< UART transmit data register empty interruption */ -#define UART_IT_TC ((uint32_t)0x0626) /*!< UART transmission complete interruption */ -#define UART_IT_RXNE ((uint32_t)0x0525) /*!< UART read data register not empty interruption */ -#define UART_IT_IDLE ((uint32_t)0x0424) /*!< UART idle interruption */ -#define UART_IT_LBD ((uint32_t)0x0846) /*!< UART LIN break detection interruption */ -#define UART_IT_CTS ((uint32_t)0x096A) /*!< UART CTS interruption */ -#define UART_IT_CM ((uint32_t)0x112E) /*!< UART character match interruption */ -#define UART_IT_WUF ((uint32_t)0x1476) /*!< UART wake-up from stop mode interruption */ -#define UART_IT_ERR ((uint32_t)0x0060) /*!< UART error interruption */ -#define UART_IT_ORE ((uint32_t)0x0300) /*!< UART overrun error interruption */ -#define UART_IT_NE ((uint32_t)0x0200) /*!< UART noise error interruption */ -#define UART_IT_FE ((uint32_t)0x0100) /*!< UART frame error interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#endif +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#endif +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#if defined(USART_CR1_FIFOEN) +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#endif + +/* Elements values convention: 000000000XXYYYYYb + - YYYYY : Interrupt source position in the XX register (5bits) + - XX : Interrupt source register (2bits) + - 01: CR1 register + - 10: CR2 register + - 11: CR3 register */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +/* Elements values convention: 0000ZZZZ00000000b + - ZZZZ : Flag position in the ISR register(4bits) */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -666,11 +749,12 @@ typedef struct #define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#if defined(USART_CR1_FIFOEN) +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#endif #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ -#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ /** @@ -688,7 +772,7 @@ typedef struct */ /** @brief Reset UART handle states. - * @param __HANDLE__: UART handle. + * @param __HANDLE__ UART handle. * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -696,8 +780,8 @@ typedef struct (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ } while(0) /** @brief Flush the UART Data registers. - * @param __HANDLE__: specifies the UART Handle. - * @retval None + * @param __HANDLE__ specifies the UART Handle. + * @retval None */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ @@ -706,19 +790,18 @@ typedef struct } while(0) /** @brief Clear the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag - * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None @@ -726,39 +809,51 @@ typedef struct #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) +#if defined(USART_CR1_FIFOEN) +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) +#endif + /** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref UART_FLAG_WUF Wake up from stop mode flag @@ -768,13 +863,13 @@ typedef struct * @arg @ref UART_FLAG_BUSY Busy flag * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_EOBF End of block flag - * @arg @ref UART_FLAG_RTOF Receiver timeout flag * @arg @ref UART_FLAG_CTS CTS Change flag * @arg @ref UART_FLAG_LBDF LIN Break detection flag * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -785,109 +880,131 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_ORE Overrun Error interrupt - * @arg @ref UART_IT_NE Noise Error interrupt - * @arg @ref UART_IT_FE Framing Error interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt source to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @arg @ref UART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag - * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref UART_SENDBREAK_REQUEST Send Break Request @@ -896,31 +1013,31 @@ typedef struct * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Enable CTS flow control. * @note This macro allows to enable CTS hardware flow control for a given UART instance, @@ -931,7 +1048,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ @@ -949,7 +1066,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ @@ -967,7 +1084,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ @@ -985,7 +1102,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ @@ -993,65 +1110,105 @@ typedef struct CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0) +/** + * @} + */ +/* Private variables -----------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup UART_Private_Variables UART Private Variables + * @{ + */ +static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; /** * @} */ +#endif /* Private macros --------------------------------------------------------*/ /** @defgroup UART_Private_Macros UART Private Macros * @{ */ +#if defined(USART_PRESC_PRESCALER) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) + +#else + /** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__: LPUART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) +#endif /* USART_PRESC_PRESCALER */ + /** @brief Check whether or not UART instance is Low Power UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET ) +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) /** @brief Check UART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz) + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) /** @brief Check UART assertion time. - * @param __TIME__: 5-bit value assertion time. + * @param __TIME__ 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** @brief Check UART deassertion time. - * @param __TIME__: 5-bit value deassertion time. + * @param __TIME__ 5-bit value deassertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__: UART frame number of stop bits. + * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ @@ -1061,7 +1218,7 @@ typedef struct /** * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__: LPUART frame number of stop bits. + * @param __STOPBITS__ LPUART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ @@ -1069,7 +1226,7 @@ typedef struct /** * @brief Ensure that UART frame parity is valid. - * @param __PARITY__: UART frame parity. + * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ @@ -1078,7 +1235,7 @@ typedef struct /** * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__: UART hardware flow control. + * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ @@ -1089,14 +1246,14 @@ typedef struct /** * @brief Ensure that UART communication mode is valid. - * @param __MODE__: UART communication mode. + * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. - * @param __STATE__: UART state. + * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ @@ -1104,7 +1261,7 @@ typedef struct /** * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__: UART oversampling. + * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ @@ -1112,7 +1269,7 @@ typedef struct /** * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__: UART frame sampling. + * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ @@ -1120,7 +1277,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__: UART auto Baud rate detection mode. + * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ @@ -1130,7 +1287,7 @@ typedef struct /** * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__: UART receiver timeout setting. + * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ @@ -1138,7 +1295,7 @@ typedef struct /** * @brief Ensure that UART LIN state is valid. - * @param __LIN__: UART LIN state. + * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ @@ -1146,7 +1303,7 @@ typedef struct /** * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__: UART LIN break detection length. + * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ @@ -1154,7 +1311,7 @@ typedef struct /** * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__: UART DMA TX state. + * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ @@ -1162,7 +1319,7 @@ typedef struct /** * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__: UART DMA RX state. + * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ @@ -1170,7 +1327,7 @@ typedef struct /** * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__: UART half-duplex state. + * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ @@ -1178,7 +1335,7 @@ typedef struct /** * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__: UART wake-up method . + * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ @@ -1186,7 +1343,7 @@ typedef struct /** * @brief Ensure that UART request parameter is valid. - * @param __PARAM__: UART request parameter. + * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ @@ -1197,7 +1354,7 @@ typedef struct /** * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__: UART advanced features initialization. + * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ @@ -1212,7 +1369,7 @@ typedef struct /** * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__: UART frame TX inversion setting. + * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ @@ -1220,7 +1377,7 @@ typedef struct /** * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__: UART frame RX inversion setting. + * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ @@ -1228,7 +1385,7 @@ typedef struct /** * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__: UART frame data inversion setting. + * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ @@ -1236,7 +1393,7 @@ typedef struct /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__: UART frame RX/TX pins swap setting. + * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ @@ -1244,7 +1401,7 @@ typedef struct /** * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__: UART frame overrun setting. + * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -1252,7 +1409,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__: UART auto Baud rate state. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ @@ -1260,7 +1417,7 @@ typedef struct /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__: UART DMA enabling or disabling on error setting. + * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -1268,7 +1425,7 @@ typedef struct /** * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__: UART frame MSB first setting. + * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1276,7 +1433,7 @@ typedef struct /** * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__: UART stop mode state. + * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ @@ -1284,7 +1441,7 @@ typedef struct /** * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__: UART mute mode state. + * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ @@ -1292,21 +1449,67 @@ typedef struct /** * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__: UART wake-up selection. + * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) /** * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__: UART driver enable polarity. + * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ ((__POLARITY__) == UART_DE_POLARITY_LOW)) +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c index 49a416e5a13..363a37943ed 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -21,6 +19,16 @@ (#) For the UART RS485 Driver Enable mode, initialize the UART registers by calling the HAL_RS485Ex_Init() API. + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. @endverbatim ****************************************************************************** @@ -76,6 +84,9 @@ * @{ */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#if defined(USART_CR1_FIFOEN) +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +#endif /** * @} */ @@ -147,26 +158,26 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. - * This parameter can be one of the following values: + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). * @retval HAL status */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { uint32_t temp = 0x0; - + /* Check the UART handle allocation */ if(huart == NULL) { @@ -174,60 +185,131 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, } /* Check the Driver Enable UART instance */ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - + /* Check the Driver Enable polarity */ assert_param(IS_UART_DE_POLARITY(Polarity)); - + /* Check the Driver Enable assertion time */ assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - + /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - + /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - + /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + + (#) TX/RX Fifos Callbacks: + (+) HAL_UARTEx_RxFifoFullCallback() + (+) HAL_UARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ + __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + /** * @} */ @@ -249,7 +331,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode (+) HAL_UARTEx_DisableStopMode() API disables the above functionality (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt - + (+) HAL_UARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_UARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_UARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold @endverbatim * @{ @@ -265,8 +353,8 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status @@ -278,21 +366,21 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { return HAL_ERROR; } - + /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState to Ready */ return (UART_CheckIdleState(huart)); } @@ -300,46 +388,48 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /** * @brief Set Wakeup from Stop mode interrupt flag selection. - * @param huart: UART handle. - * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_STARTBIT - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart = 0; - + /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); } - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Wait until REACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { @@ -350,76 +440,386 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return status; } /** * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart: UART handle. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Set UESM bit */ SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Disable UART Stop Mode. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Clear UESM bit */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#if defined(USART_CR2_SLVEN) +/** + * @brief Enable the SPI slave mode. + * @note When the UART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the UART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the UART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(huart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->SlaveMode = UART_SLAVEMODE_ENABLE; + + huart->gState = HAL_UART_STATE_READY; + + /* Enable UART */ + __HAL_UART_ENABLE(huart); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + /* Disable SPI slave mode */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->SlaveMode = UART_SLAVEMODE_ENABLE; + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param huart UART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref UART_NSS_HARD + * @arg @ref UART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); + assert_param(IS_UART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } +#endif +#if defined(USART_CR1_FIFOEN) /** - * @brief UART wakeup from Stop mode callback. - * @param huart: UART handle. - * @retval None + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status */ -__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file. - */ + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; } +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} +#endif + /** * @} */ @@ -434,21 +834,55 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) /** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart: UART handle. - * @param WakeUpSelection: UART wake up from stop mode parameters. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. * @retval None */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - + /* Set the USART address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - + /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; + uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + } + else + { + rx_fifo_depth = 8; /* RX Fifo size */ + tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + } +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h index 8977d53da85..926662f36bf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of UART HAL Extended module. ****************************************************************************** * @attention @@ -84,25 +82,66 @@ typedef struct * @{ */ -/** @defgroup UARTEx_Word_Length UART Word Length +/** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ -/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ +#if defined(USART_CR2_SLVEN) +/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management + * @{ + */ +#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ +#endif + /** * @} */ @@ -124,7 +163,21 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @} */ +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + /* IO operation functions *****************************************************/ +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#if defined(USART_CR1_FIFOEN) +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); +#endif + +/** + * @} + */ /** @addtogroup UARTEx_Exported_Functions_Group3 * @{ @@ -135,7 +188,20 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#if defined(USART_CR2_SLVEN) +HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig); +#endif + +#if defined(USART_CR1_FIFOEN) +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +#endif + /** * @} @@ -145,17 +211,48 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); * @} */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Constants UARTEx Private Constants + * @{ + */ +#if defined(USART_CR2_SLVEN) +/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode + * @{ + */ +#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ +#endif +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup UARTEx_Private_Macros UARTEx Private Macros * @{ */ /** @brief Report the UART clock source. - * @param __HANDLE__: specifies the UART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -242,7 +339,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); break; \ } \ } \ - else if ((__HANDLE__)->Instance == UART5) \ + else if((__HANDLE__)->Instance == UART5) \ { \ switch(__HAL_RCC_GET_UART5_SOURCE()) \ { \ @@ -600,7 +697,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); /** * @brief Ensure that UART frame length is valid. - * @param __LENGTH__: UART frame length. + * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ @@ -609,12 +706,48 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); /** * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__: UART wake-up address length. + * @param __ADDRESS__ UART wake-up address length. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) +#if defined(USART_CR2_SLVEN) +/** + * @brief Ensure that UART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ UART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \ + ((__NSS__) == UART_NSS_SOFT)) +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c index d6502a6a872..af1c56627fa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_usart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter @@ -43,8 +41,8 @@ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode (Receiver/Transmitter) in the husart handle Init structure. + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. (#) Initialize the USART registers by calling the HAL_USART_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) @@ -107,10 +105,25 @@ */ #define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ #define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */ + +#if defined(USART_CR1_FIFOEN) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \ + USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */ +#else #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ +#endif + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ /** * @} */ @@ -133,10 +146,21 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +#if defined(USART_CR1_FIFOEN) +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +#endif +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); +#if defined(USART_CR1_FIFOEN) +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +#endif + + /** * @} */ @@ -249,13 +273,13 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) } /** - * @brief DeInitialize the USART peripheral. + * @brief DeInitialize the USART peripheral. * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { - /* Check the USART handle allocation */ + /* Check the USART handle allocation */ if(husart == NULL) { return HAL_ERROR; @@ -284,14 +308,14 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Initialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ -__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) + __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspInit can be implemented in the user file */ @@ -299,14 +323,14 @@ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) /** * @brief DeInitialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ -__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) + __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspDeInit can be implemented in the user file */ @@ -317,7 +341,7 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions + * @brief USART Transmit and Receive functions * @verbatim =============================================================================== @@ -410,24 +434,23 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->TxXferSize = Size; husart->TxXferCount = Size; - + /* Check the remaining data to be sent */ while(husart->TxXferCount > 0) { - husart->TxXferCount--; - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -441,19 +464,29 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa { husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); } + + husart->TxXferCount--; } - + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + /* At end of Tx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -464,7 +497,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. * @param husart USART handle. * @param pRxData Pointer to data buffer. * @param Size Amount of data to be received. @@ -476,51 +509,54 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat uint16_t* tmp; uint16_t uhMask; uint32_t tickstart = 0; - + if(husart->State == HAL_USART_STATE_READY) { if((pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->RxXferSize = Size; husart->RxXferCount = Size; - + /* Computation of USART mask to apply to RDR register */ USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - + /* as long as data have to be received */ while(husart->RxXferCount > 0) { - husart->RxXferCount--; - - /* Wait until TC flag is set to send dummy byte in order to generate the - * clock for the slave to send data. - * Whatever the frame length (7, 8 or 9-bit long), the same dummy value - * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) +#if defined(USART_CR2_SLVEN) + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) +#endif { - return HAL_TIMEOUT; + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); } - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); - + /* Wait for RXNE Flag */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pRxData ; @@ -531,14 +567,26 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } + + husart->RxXferCount--; + } - + +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + /* At end of Rx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -548,7 +596,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat } /** - * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. @@ -568,6 +616,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -586,14 +635,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - /* Check the remain data to be sent */ - while(husart->TxXferCount > 0) +#if defined(USART_CR2_SLVEN) + if ((husart->SlaveMode == USART_SLAVEMODE_ENABLE) || (husart->TxXferCount == 0x01U)) +#else + if (husart->TxXferCount == 0x01U) +#endif { - husart->TxXferCount--; - husart->RxXferCount--; - - /* Wait until TC flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + /* Wait until TXE flag is set to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -601,28 +650,60 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pTxData; husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; + pTxData += 2U; } else - { + { husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); } - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + while ((husart->TxXferCount > 0) || (husart->RxXferCount > 0)) + { + if (husart->TxXferCount > 0) { - tmp = (uint16_t*) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + /* Wait until TXE flag is set to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pTxData; + husart->Instance->TDR = (*tmp & uhMask); + pTxData += 2; + } + else + { + husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + } + + husart->TxXferCount--; } - else + + if (husart->RxXferCount > 0) { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pRxData ; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + pRxData +=2; + } + else + { + *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } + + husart->RxXferCount--; } } @@ -659,12 +740,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /* Process Locked */ __HAL_LOCK(husart); - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; husart->TxXferCount = Size; + husart->TxISR = NULL; husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; + husart->State = HAL_USART_STATE_BUSY_TX; /* The USART Error Interrupts: (Frame error, noise error, overrun error) are not managed by the USART Transmit Process to avoid the overrun interrupt @@ -672,11 +754,45 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT to benefit for the frame error and noise interrupts the usart mode should be configured only for transmit "USART_MODE_TX" */ - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); +#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the TX FIFO threshold interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); + } + else +#endif + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } return HAL_OK; } @@ -687,8 +803,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT } /** - * @brief Receive an amount of data in interrupt mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. * @param husart USART handle. * @param pRxData pointer to data buffer. * @param Size amount of data to be received. @@ -696,6 +812,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { +#if defined(USART_CR1_FIFOEN) + uint8_t nb_dummy_data; +#endif + if(husart->State == HAL_USART_STATE_READY) { if((pRxData == NULL ) || (Size == 0)) @@ -706,34 +826,87 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Process Locked */ __HAL_LOCK(husart); - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; husart->RxXferCount = Size; + husart->RxISR = NULL; USART_MASK_COMPUTATION(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Send dummy byte in order to generate the clock for the Slave to send the next data */ - if(husart->Init.WordLength == USART_WORDLENGTH_9B) +#if defined(USART_CR1_FIFOEN) + /* Configure Rx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF); + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else +#endif { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +#else + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif } +#if defined(USART_CR2_SLVEN) + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) +#endif + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ +#if defined(USART_CR1_FIFOEN) + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0 ; nb_dummy_data--) + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + else +#endif + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + return HAL_OK; } else @@ -743,7 +916,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx } /** - * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. @@ -774,18 +947,69 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; + +#if defined(USART_CR1_FIFOEN) + /* Configure TxRx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the TX and RX FIFO Threshold interrupts */ + SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); + } + else +#endif + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +#else SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); +#endif + + /* Enable the USART Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); +#endif + } return HAL_OK; } @@ -796,7 +1020,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint } /** - * @brief Send an amount of data in DMA mode. + * @brief Send an amount of data in DMA mode. * @param husart USART handle. * @param pTxData pointer to data buffer. * @param Size amount of data to be sent. @@ -854,13 +1078,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p } /** - * @brief Receive an amount of data in DMA mode. + * @brief Receive an amount of data in DMA mode. * @param husart USART handle. * @param pRxData pointer to data buffer. * @param Size amount of data to be received. * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -899,15 +1123,21 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive mode */ - /* Set the USART DMA Tx Complete and Error callback to Null */ - husart->hdmatx->XferErrorCallback = NULL; - husart->hdmatx->XferHalfCpltCallback = NULL; - husart->hdmatx->XferCpltCallback = NULL; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - +#if defined(USART_CR2_SLVEN) + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + tmp = (uint32_t*)&pRxData; + /* Set the USART DMA Tx Complete and Error callback to Null */ + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + } +#endif + /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -934,7 +1164,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR } /** - * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. @@ -1018,7 +1248,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin } /** - * @brief Pause the DMA Transfer. + * @brief Pause the DMA Transfer. * @param husart USART handle. * @retval HAL status */ @@ -1040,14 +1270,14 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } + } if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { + { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Disable the USART DMA Rx request */ + /* Disable the USART DMA Rx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } } @@ -1059,7 +1289,7 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) } /** - * @brief Resume the DMA Transfer. + * @brief Resume the DMA Transfer. * @param husart USART handle. * @retval HAL status */ @@ -1077,7 +1307,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) { /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -1097,7 +1327,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) } /** - * @brief Stop the DMA Transfer. + * @brief Stop the DMA Transfer. * @param husart USART handle. * @retval HAL status */ @@ -1108,7 +1338,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ + the stream and the corresponding call back is executed. */ /* Disable the USART Tx/Rx DMA requests */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); @@ -1145,9 +1375,14 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) @@ -1188,6 +1423,17 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) /* Clear the Error flags in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + /* Restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -1215,9 +1461,14 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t abortcplt = 1; - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#endif /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ @@ -1311,6 +1562,17 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) /* Clear the Error flags in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + +#endif + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + /* Restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -1330,116 +1592,151 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { uint32_t isrflags = READ_REG(husart->Instance->ISR); uint32_t cr1its = READ_REG(husart->Instance->CR1); - uint32_t cr3its; - uint32_t errorflags; + uint32_t cr3its = READ_REG(husart->Instance->CR3); + uint32_t errorflags; + /* If no error occurs */ +#if defined(USART_CR2_SLVEN) + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); +#else errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); +#endif if (errorflags == RESET) { /* USART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - USART_Receive_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } + if (husart->RxISR != NULL) {husart->RxISR(husart);} return; } } - + /* If some errors occur */ - cr3its = READ_REG(husart->Instance->CR3); +#if defined(USART_CR1_FIFOEN) + if( (errorflags != RESET) + && ( ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) +#else if( (errorflags != RESET) && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) +#endif { /* USART parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - + husart->ErrorCode |= HAL_USART_ERROR_PE; } - + /* USART frame error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - + husart->ErrorCode |= HAL_USART_ERROR_FE; } - + /* USART noise error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - + husart->ErrorCode |= HAL_USART_ERROR_NE; } - + /* USART Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) +#else + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || + ((cr3its & USART_CR3_EIE) != RESET))) +#endif { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - + husart->ErrorCode |= HAL_USART_ERROR_ORE; } - + +#if defined(USART_CR2_SLVEN) + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if(((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + return; + } + else + { + __HAL_USART_CLEAR_UDRFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_UDR; + } + } +#endif + /* Call USART Error Call back function if need be --------------------------*/ if(husart->ErrorCode != HAL_USART_ERROR_NONE) { /* USART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - USART_Receive_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } + if (husart->RxISR != NULL) {husart->RxISR(husart);} } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + consider error as blocking */ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) { /* Blocking error : transfer is aborted - Set the USART state ready to be able to start again the process, - Disable Interrupts, and disable DMA requests, if ongoing */ + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - + /* Disable the USART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); - + /* Abort the USART DMA Tx channel */ if(husart->hdmatx != NULL) { /* Set the USART Tx DMA Abort callback to NULL : no callback - executed at end of DMA abort procedure */ + executed at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; /* Abort DMA TX */ HAL_DMA_Abort_IT(husart->hdmatx); } - + /* Abort the USART DMA Rx channel */ if(husart->hdmarx != NULL) { /* Set the USART Rx DMA Abort callback : - will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) { @@ -1462,49 +1759,64 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ HAL_USART_ErrorCallback(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - - + + /* USART in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET))) +#else + if(((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - USART_Transmit_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } + if (husart->TxISR != NULL) {husart->TxISR(husart);} return; } - + /* USART in mode Transmitter (transmission end) -----------------------------*/ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { USART_EndTransmit_IT(husart); return; } - + +#if defined(USART_CR1_FIFOEN) + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + { + HAL_USARTEx_TxFifoEmptyCallback(husart); + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + { + HAL_USARTEx_RxFifoFullCallback(husart); + return; + } +#endif } /** * @brief Tx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxCpltCallback can be implemented in the user file. */ @@ -1512,14 +1824,14 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ -__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) + __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1527,14 +1839,14 @@ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_RxCpltCallback can be implemented in the user file. */ @@ -1542,14 +1854,14 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_RxHalfCpltCallback can be implemented in the user file */ @@ -1557,14 +1869,14 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxRxCpltCallback can be implemented in the user file */ @@ -1572,14 +1884,14 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_ErrorCallback can be implemented in the user file. */ @@ -1623,7 +1935,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) /** * @brief Return the USART handle state. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle state */ @@ -1634,7 +1946,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) /** * @brief Return the USART error code. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle Error Code */ @@ -1662,17 +1974,22 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ static void USART_EndTransfer(USART_HandleTypeDef *husart) { - /* Disable TXEIE and TCIE interrupts */ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE)); +#if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#endif /* At end of process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; } /** - * @brief DMA USART transmit process complete callback. + * @brief DMA USART transmit process complete callback. * @param hdma DMA handle. * @retval None */ @@ -1682,7 +1999,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { + { husart->TxXferCount = 0; if(husart->State == HAL_USART_STATE_BUSY_TX) @@ -1706,7 +2023,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART transmit process half complete callback. + * @brief DMA USART transmit process half complete callback. * @param hdma DMA handle. * @retval None */ @@ -1718,30 +2035,30 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART receive process complete callback. + * @brief DMA USART receive process complete callback. * @param hdma DMA handle. * @retval None */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); - + /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { husart->RxXferCount = 0; - + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ + in USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ + clock to the slave device */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - + if(husart->State == HAL_USART_STATE_BUSY_RX) { HAL_USART_RxCpltCallback(husart); @@ -1765,12 +2082,11 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { HAL_USART_TxRxCpltCallback(husart); } - } - + } } /** - * @brief DMA USART receive process half complete callback. + * @brief DMA USART receive process half complete callback. * @param hdma DMA handle. * @retval None */ @@ -1783,7 +2099,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMAError(DMA_HandleTypeDef *hdma) @@ -1849,7 +2165,7 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); /* Restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; /* Call user Abort complete callback */ HAL_USART_AbortCpltCallback(husart); @@ -1916,15 +2232,11 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar { if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - husart->State= HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_TIMEOUT; } } @@ -1934,7 +2246,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Configure the USART peripheral. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) @@ -1954,62 +2266,109 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); assert_param(IS_USART_PARITY(husart->Init.Parity)); assert_param(IS_USART_MODE(husart->Init.Mode)); - - +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); +#endif + /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE and RE bits and configure * the USART Word Length, Parity and Mode: * set the M bits according to husart->Init.WordLength value * set PCE and PS bits according to husart->Init.Parity value * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*---------------------------- USART CR2 Configuration ---------------------*/ - /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value + * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = 0; tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); - tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); + tmpreg |= (uint32_t)husart->Init.StopBits; MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* no CR3 register configuration */ +#if defined(USART_PRESC_PRESCALER) + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ + MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); +#endif /*-------------------------- USART BRR Configuration -----------------------*/ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ USART_GETCLOCKSOURCE(husart, clocksource); + switch (clocksource) { - case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + case USART_CLOCKSOURCE_PCLK1: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_PCLK2: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_HSI: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_SYSCLK: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_LSE: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); - husart->Instance->BRR = brrtemp; - + /* USARTDIV must be greater than or equal to 0d16 */ + if (usartdiv >= USART_BRR_MIN) + { + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + +#if defined(USART_CR1_FIFOEN) + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->NbTxDataToProcess = 1; + husart->NbRxDataToProcess = 1; +#endif + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + return ret; } @@ -2063,59 +2422,158 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Transmit_IT(). * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. * @param husart USART handle. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; - /* Check that a Tx process is ongoing */ - if(husart->State == HAL_USART_STATE_BUSY_TX) + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - if(husart->TxXferCount == 0) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->TxXferCount--; + } + } +} - return HAL_OK; +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + if(husart->TxXferCount == 0) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } else { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + tmp = (uint16_t*) husart->pTxBuffPtr; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->pTxBuffPtr += 2; + husart->TxXferCount--; + } + } +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint8_t nb_tx_data; + /* Check that a Tx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(husart->TxXferCount == 0) { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ } - else + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->TxXferCount--; } - - husart->TxXferCount--; - - return HAL_OK; - } + } } - else +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - return HAL_BUSY; + for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(husart->TxXferCount == 0) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + tmp = (uint16_t*) husart->pTxBuffPtr; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->pTxBuffPtr += 2; + husart->TxXferCount--; + } + } } } +#endif /** * @brief Wraps up transmission in non-blocking mode. * @param husart Pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) { /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TC); @@ -2123,12 +2581,27 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - /* Tx process is ended, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxCpltCallback(husart); - - return HAL_OK; + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxCpltCallback(husart); + } + else if (husart->RxXferCount == 0) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } @@ -2136,135 +2609,369 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) * @brief Simplex receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. * @param husart USART handle - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; uint16_t uhMask = husart->Mask; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + + if(--husart->RxXferCount == 0) { - tmp = (uint16_t*) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } - else +#if defined(USART_CR2_SLVEN) + else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + uint16_t uhMask = husart->Mask; + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + tmp = (uint16_t*) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2; + if(--husart->RxXferCount == 0) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Rx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_RxCpltCallback(husart); - - return HAL_OK; + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } + } +#if defined(USART_CR2_SLVEN) + else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } - - return HAL_OK; - } - else - { - return HAL_BUSY; } } +#if defined(USART_CR1_FIFOEN) /** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @brief Simplex receive an amount of data in non-blocking mode. * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_TransmitReceive_IT(). - * @param husart: USART handle. + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @retval None * @retval HAL status */ -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint16_t* tmp; uint16_t uhMask = husart->Mask; - - if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - - if(husart->TxXferCount != 0x00) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) + for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + + if(--husart->RxXferCount == 0) { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (uint16_t)(*tmp & uhMask); - husart->pTxBuffPtr += 2; - } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask); + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } - husart->TxXferCount--; - - /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) +#if defined(USART_CR2_SLVEN) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif { - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } } } - - if(husart->RxXferCount != 0x00) + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + +#if defined(USART_CR2_SLVEN) + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && + (husart->TxXferCount == 0U)) +#else + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->TxXferCount == 0U)) +#endif { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + uint16_t uhMask = husart->Mask; + uint8_t nb_rx_data; + + /* Check that a Tx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + tmp = (uint16_t*) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2; + + if(--husart->RxXferCount == 0) { - tmp = (uint16_t*) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } - else +#if defined(USART_CR2_SLVEN) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } - husart->RxXferCount--; } } - - /* Check the latest data received */ - if(husart->RxXferCount == 0) + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) { - /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxRxCpltCallback(husart); - - return HAL_OK; + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + +#if defined(USART_CR2_SLVEN) + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && + (husart->TxXferCount == 0U)) +#else + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->TxXferCount == 0U)) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } } - - return HAL_OK; } else { - return HAL_BUSY; + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); } } +#endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h index a7ed6ebb474..baea5261eec 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -66,7 +64,11 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */ + Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. + @note Oversampling by 8 is systematically applied to achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -93,6 +95,12 @@ typedef struct uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_Last_Bit. */ + +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref USART_ClockPrescaler. */ +#endif + }USART_InitTypeDef; /** @@ -100,14 +108,14 @@ typedef struct */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ }HAL_USART_StateTypeDef; /** @@ -115,12 +123,13 @@ typedef enum */ typedef enum { - HAL_USART_ERROR_NONE = 0x00, /*!< No error */ - HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ + HAL_USART_ERROR_NONE = 0x00U, /*!< No error */ + HAL_USART_ERROR_PE = 0x01U, /*!< Parity error */ + HAL_USART_ERROR_NE = 0x02U, /*!< Noise error */ + HAL_USART_ERROR_FE = 0x04U, /*!< frame error */ + HAL_USART_ERROR_ORE = 0x08U, /*!< Overrun error */ + HAL_USART_ERROR_DMA = 0x10U, /*!< DMA transfer error */ + HAL_USART_ERROR_UDR = 0x20U /*!< SPI slave underrun error */ }HAL_USART_ErrorTypeDef; /** @@ -128,47 +137,65 @@ typedef enum */ typedef enum { - USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }USART_ClockSourceTypeDef; /** * @brief USART handle Structure definition */ -typedef struct +typedef struct __USART_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ - USART_InitTypeDef Init; /*!< USART communication parameters */ + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ - uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ - uint16_t TxXferSize; /*!< USART Tx Transfer size */ + uint16_t RxXferSize; /*!< USART Rx Transfer size */ - __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + uint16_t Mask; /*!< USART Rx RDR register mask */ - uint16_t RxXferSize; /*!< USART Rx Transfer size */ +#if defined(USART_CR1_FIFOEN) + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint16_t Mask; /*!< USART Rx RDR register mask */ + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref USARTEx_FIFO_mode. */ +#endif + +#if defined(USART_CR2_SLVEN) + uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. + This parameter can be a value of @ref USARTEx_Slave_Mode. */ +#endif + + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ - DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ - DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ - HAL_LockTypeDef Lock; /*!< Locking object */ + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ - __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO uint32_t ErrorCode; /*!< USART Error code */ + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ }USART_HandleTypeDef; @@ -184,10 +211,10 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ -#define USART_STOPBITS_1 ((uint32_t)0x00000000) /*!< USART frame with 1 stop bit */ -#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ /** * @} */ @@ -195,19 +222,19 @@ typedef struct /** @defgroup USART_Parity USART Parity * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ -#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ -#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ /** * @} */ /** @defgroup USART_Mode USART Mode * @{ - */ -#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ -#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ -#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ @@ -215,8 +242,8 @@ typedef struct /** @defgroup USART_Over_Sampling USART Over Sampling * @{ */ -#define USART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */ +#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} */ @@ -224,8 +251,8 @@ typedef struct /** @defgroup USART_Clock USART Clock * @{ */ -#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */ -#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ /** * @} */ @@ -233,8 +260,8 @@ typedef struct /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */ -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ /** * @} */ @@ -242,8 +269,8 @@ typedef struct /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */ -#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ /** * @} */ @@ -251,17 +278,38 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */ -#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_ClockPrescaler USART Clock Prescaler + * @{ + */ +#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ /** * @} */ +#endif /** @defgroup USART_Request_Parameters USART Request Parameters * @{ */ -#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ /** * @} */ @@ -271,20 +319,31 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */ -#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */ -#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */ -#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */ -#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */ -#define USART_FLAG_LBDF ((uint32_t)0x00000100) /*!< USART LIN break detection flag */ -#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */ -#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */ -#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */ -#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */ -#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */ -#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */ -#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */ -#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */ +#if defined(USART_CR1_FIFOEN) +#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */ +#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ +#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ +#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#else +#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ +#endif +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +#if defined(USART_CR2_SLVEN) +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#endif /** * @} */ @@ -300,15 +359,24 @@ typedef struct * @{ */ -#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */ -#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */ -#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */ -#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */ -#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */ -#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */ -#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */ -#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */ -#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */ +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#if defined(USART_CR1_FIFOEN) +#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ +#endif +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ + /** * @} */ @@ -316,21 +384,26 @@ typedef struct /** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags * @{ */ -#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#if defined(USART_CR1_FIFOEN) +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#endif +#if defined(USART_CR2_SLVEN) +#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ +#endif /** * @} */ /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask * @{ - */ -#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ /** * @} */ @@ -345,22 +418,28 @@ typedef struct */ /** @brief Reset USART handle state. - * @param __HANDLE__: USART handle. + * @param __HANDLE__ USART handle. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Check whether the specified USART flag is set or not. - * @param __HANDLE__: specifies the USART Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: + * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref USART_FLAG_RXFF RXFIFO Full flag + * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref USART_FLAG_BUSY Busy flag - * @arg @ref USART_FLAG_CTS CTS Change flag + * @arg @ref USART_FLAG_UDR SPI slave underrun error flag * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -371,137 +450,178 @@ typedef struct #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified USART pending flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: - * @arg @ref USART_CLEAR_PEF - * @arg @ref USART_CLEAR_FEF - * @arg @ref USART_CLEAR_NEF - * @arg @ref USART_CLEAR_OREF - * @arg @ref USART_CLEAR_IDLEF - * @arg @ref USART_CLEAR_TCF - * @arg @ref USART_CLEAR_CTSF + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the USART PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) /** @brief Clear the USART FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) /** @brief Clear the USART NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) /** @brief Clear the USART ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) /** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) +#if defined(USART_CR1_FIFOEN) +/** @brief Clear the USART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) +#endif + +#if defined(USART_CR2_SLVEN) +/** @brief Clear SPI slave underrun error flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) +#endif + /** @brief Enable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to enable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_ORE OverRun Error interrupt - * @arg @ref USART_IT_NE Noise Error interrupt - * @arg @ref USART_IT_FE Framing Error interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_ORE OverRun Error interrupt - * @arg @ref USART_IT_NE Noise Error interrupt - * @arg @ref USART_IT_FE Framing Error interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ - (((uint16_t)(__IT__)) & USART_IT_MASK))) + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None */ #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific USART request flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __REQ__: specifies the request flag to set. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. * This parameter can be one of the following values: * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request @@ -511,49 +631,81 @@ typedef struct #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ + */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ -#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ +/* Private variables -----------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_Private_Variables USART Private Variables + * @{ + */ +static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; /** * @} */ +#endif /* Private macros --------------------------------------------------------*/ /** @defgroup USART_Private_Macros USART Private Macros * @{ */ -/** @brief Check USART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8). - * @retval Test result (TRUE or FALSE). +#if defined(USART_PRESC_PRESCALER) +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result */ -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) +#else +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) +#endif + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on L4 + * divided by the smallest oversampling used on the USART (i.e. 8) + * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) +#else +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) +#endif /** * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__: USART frame number of stop bits. + * @param __STOPBITS__ USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ @@ -563,23 +715,23 @@ typedef struct /** * @brief Ensure that USART frame parity is valid. - * @param __PARITY__: USART frame parity. + * @param __PARITY__ USART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ ((__PARITY__) == USART_PARITY_EVEN) || \ - ((__PARITY__) == USART_PARITY_ODD)) + ((__PARITY__) == USART_PARITY_ODD)) /** * @brief Ensure that USART communication mode is valid. - * @param __MODE__: USART communication mode. + * @param __MODE__ USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) /** * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__: USART oversampling. + * @param __SAMPLING__ USART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ @@ -587,7 +739,7 @@ typedef struct /** * @brief Ensure that USART clock state is valid. - * @param __CLOCK__: USART clock state. + * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) */ #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ @@ -595,21 +747,21 @@ typedef struct /** * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__: USART frame polarity. + * @param __CPOL__ USART frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) /** * @brief Ensure that USART frame phase is valid. - * @param __CPHA__: USART frame phase. + * @param __CPHA__ USART frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) /** * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__: USART frame last bit clock pulse setting. + * @param __LASTBIT__ USART frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ @@ -617,12 +769,32 @@ typedef struct /** * @brief Ensure that USART request parameter is valid. - * @param __PARAM__: USART request parameter. + * @param __PARAM__ USART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Ensure that USART Prescaler is valid. + * @param __CLOCKPRESCALER__ USART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) + +#endif /** * @} */ @@ -671,20 +843,18 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); -void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); -void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); /** * @} */ -/* Peripheral Control functions ***********************************************/ - /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c new file mode 100644 index 00000000000..d2b1b3d70f2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c @@ -0,0 +1,551 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_usart_ex.c + * @author MCD Application Team + * @brief Extended USART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + * + Peripheral Control functions + * + * + @verbatim + ============================================================================== + ##### USART peripheral extended features ##### + ============================================================================== + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx + * @brief USART Extended HAL module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_Private_Functions USARTEx Private Functions + * @{ + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); +/** + * @} + */ +#endif + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions + * @{ + */ + +/** @defgroup USARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended USART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_USARTEx_RxFifoFullCallback() + (+) HAL_USARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief USART RX Fifo full callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + +/** + * @} + */ + +/** @defgroup USARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + +@endverbatim + * @{ + */ + +#if defined(USART_CR2_SLVEN) +/** + * @brief Enable the SPI slave mode. + * @note When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable SPI slave mode */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param husart USART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref USART_NSS_HARD + * @arg @ref USART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + assert_param(IS_USART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Enable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_ENABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_DISABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param husart USART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_TXFIFO_THRESHOLD_1_8 + * @arg @ref USART_TXFIFO_THRESHOLD_1_4 + * @arg @ref USART_TXFIFO_THRESHOLD_1_2 + * @arg @ref USART_TXFIFO_THRESHOLD_3_4 + * @arg @ref USART_TXFIFO_THRESHOLD_7_8 + * @arg @ref USART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update TX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param husart USART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_RXFIFO_THRESHOLD_1_8 + * @arg @ref USART_RXFIFO_THRESHOLD_1_4 + * @arg @ref USART_RXFIFO_THRESHOLD_1_2 + * @arg @ref USART_RXFIFO_THRESHOLD_3_4 + * @arg @ref USART_RXFIFO_THRESHOLD_7_8 + * @arg @ref USART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update RX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USARTEx_Private_Functions + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param husart USART handle. + * @retval None + */ +void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; + uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + + if (husart->FifoMode == USART_FIFOMODE_DISABLE) + { + husart->NbTxDataToProcess = 1; + husart->NbRxDataToProcess = 1; + } + else + { + rx_fifo_depth = 8; /* RX Fifo size */ + tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + husart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + } +} +#endif +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h index cf01f076319..bea5add84fc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USART HAL Extended module. ****************************************************************************** * @attention @@ -63,18 +61,86 @@ /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ +#if defined(USART_CR2_SLVEN) +/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management + * @{ + */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ /** * @} */ +#endif -/* Exported functions --------------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level + * @{ + */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ +#endif + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ +#if defined(USART_CR2_SLVEN) +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode + * @{ + */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ +#endif +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup USARTEx_Private_Macros USARTEx Private Macros @@ -207,7 +273,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. */ #define USART_MASK_COMPUTATION(__HANDLE__) \ @@ -250,18 +316,96 @@ /** * @brief Ensure that USART frame length is valid. - * @param __LENGTH__: USART frame length. + * @param __LENGTH__ USART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ ((__LENGTH__) == USART_WORDLENGTH_8B) || \ ((__LENGTH__) == USART_WORDLENGTH_9B)) +#if defined(USART_CR2_SLVEN) +/** + * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ USART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ + ((__NSS__) == USART_NSS_SOFT)) +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that USART TXFIFO threshold level is valid. + * @param __THRESHOLD__ USART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) +#endif /** * @} */ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* IO operation functions *****************************************************/ +#if defined(USART_CR1_FIFOEN) +void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); +void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); +#endif + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +#if defined(USART_CR2_SLVEN) +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); +#endif + +#if defined(USART_CR1_FIFOEN) +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +#endif + +/** + * @} + */ + +/** + * @} + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c index 5e8ce3077ac..ce4a280195b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h index 70393553482..75759788f57 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c index 1a309d0f684..ead41c287d8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief ADC LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h index 52c31cb96fb..f859f8783a3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -77,6 +75,9 @@ extern "C" { #define ADC_SQR4_REGOFFSET (0x00000300U) #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#if defined(CORE_CM0PLUS) +#define ADC_SQRX_REGOFFSET_POS (8U) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ +#endif #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ @@ -114,6 +115,9 @@ extern "C" { #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) +#if defined(CORE_CM0PLUS) +#define ADC_JDRX_REGOFFSET_POS (8U) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ +#endif /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ @@ -208,6 +212,9 @@ extern "C" { #define ADC_SMPR1_REGOFFSET (0x00000000U) #define ADC_SMPR2_REGOFFSET (0x02000000U) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) +#if defined(CORE_CM0PLUS) +#define ADC_SMPRX_REGOFFSET_POS (25U) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ +#endif #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U) #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ @@ -289,7 +296,11 @@ extern "C" { #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ - +#if defined(CORE_CM0PLUS) +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000U) /* Selection of 1 bit to discriminate differential mode: mask of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16U) /* Selection of 1 bit to discriminate differential mode: position of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4U) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ +#endif /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ @@ -316,12 +327,19 @@ extern "C" { #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) +#define ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ + /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) - +#if defined(CORE_CM0PLUS) +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000U) /* Selection of 1 bit to discriminate threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16U) /* Selection of 1 bit to discriminate threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4U) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ +#endif /* Internal mask for ADC offset: */ /* Internal register offset for ADC offset number configuration */ @@ -846,7 +864,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} @@ -855,23 +873,23 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ -#if defined(ADC_CFGR_DFSDMCFG) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} */ -#endif /* ADC_CFGR_DFSDMCFG */ +#endif #if defined(ADC_SMPR1_SMPPLUS) /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration @@ -882,12 +900,12 @@ typedef struct /** * @} */ -#endif /* ADC_SMPR1_SMPPLUS */ +#endif /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} @@ -896,7 +914,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ @@ -919,7 +937,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ @@ -992,7 +1010,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode * @{ */ -#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** * @} @@ -1001,7 +1019,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ /** @@ -1011,7 +1029,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ @@ -1022,7 +1040,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group injected sequencer discontinuous mode disable */ #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} @@ -1077,7 +1095,7 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ @@ -1187,7 +1205,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ -#define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ @@ -1199,7 +1217,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define LL_ADC_OVS_REG_CONT (0x00000000U)/*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_CONT (0x00000000U) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} @@ -1208,7 +1226,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ @@ -1223,7 +1241,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ @@ -1240,7 +1258,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ @@ -1255,7 +1273,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ @@ -1267,7 +1285,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ @@ -1490,7 +1508,7 @@ typedef struct * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (7) @@ -1993,8 +2011,13 @@ typedef struct * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ +#if defined(CORE_CM0PLUS) +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) +#else #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW) +#endif /** * @brief Helper macro to set the ADC calibration value with both single ended @@ -2009,8 +2032,13 @@ typedef struct * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ +#if defined(CORE_CM0PLUS) +#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ + (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) +#else #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__)) +#endif #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -2166,7 +2194,7 @@ typedef struct * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -2559,9 +2587,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx */ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { +#if defined(CORE_CM0PLUS) + MODIFY_REG(ADCx->CALFACT, + SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, + CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); +#else MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); +#endif } /** @@ -2586,7 +2620,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); +#else return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); +#endif } /** @@ -3204,7 +3242,6 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } - /** * @brief Set ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: @@ -3473,11 +3510,15 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); +#endif MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))); + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -3578,11 +3619,15 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); +#endif - return (uint32_t) (READ_BIT(*preg, + return (uint32_t) ((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -3702,7 +3747,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); } -#if defined(ADC_CFGR_DFSDMCFG) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) /** * @brief Set ADC group regular conversion data transfer to DFSDM. * @note DFSDM transfer cannot be used if DMA transfer is enabled. @@ -3737,7 +3782,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG)); } -#endif /* ADC_CFGR_DFSDMCFG */ +#endif /** * @brief Set ADC group regular behavior in case of overrun: @@ -4020,7 +4065,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, some fast channels are available: fast analog inputs + * @note On STM32L4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -4083,8 +4128,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))); + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); } /** @@ -4157,9 +4202,9 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - return (uint32_t)(READ_BIT(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))) - << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + return (uint32_t)((READ_BIT(ADCx->JSQR, + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4294,7 +4339,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, some fast channels are available: fast analog inputs + * @note On STM32L4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -4517,10 +4562,10 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, ADC_JSQR_JL , TriggerSource | (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) | - ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) | - ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) | - ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) | - ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) | + (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | SequencerNbRanks ); } @@ -4638,11 +4683,19 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), + SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +#endif } /** @@ -4730,12 +4783,21 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) + >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) + ); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) ); +#endif } /** @@ -4753,7 +4815,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. - * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) + * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * are internally fixed to single-ended inputs configuration. * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. @@ -4763,7 +4825,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * ADC must be ADC disabled. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime + * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_1 @@ -4780,6 +4842,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 * @param SingleDiff This parameter can be a combination of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED @@ -4810,15 +4873,14 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. - * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) + * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * are internally fixed to single-ended inputs configuration. * @note One or several values can be selected. In this case, the value * returned is null if all channels are in single ended-mode. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime + * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 @@ -4833,6 +4895,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 * @retval 0: channel in single-ended mode, else: channel in differential mode */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) @@ -4998,12 +5061,21 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + MODIFY_REG(*preg, + (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & AWDy); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); +#endif } /** @@ -5130,51 +5202,59 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */ - /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */ - register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK)); + register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - /* Set variable of AWD1 monitored channel according to AWD1 features */ - /* and ADC channel definition: */ - /* - channel ID with number */ - /* - channel ID with bitfield */ - /* - AWD1 single or all channels */ - /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */ - /* AWD2 or AWD3 selected). */ - register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS); - - register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup - | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle) - | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & 0x00000001U)) - ) - * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS)) - ); - - /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */ - /* features and ADC channel definition: */ - /* - channel ID with number */ - /* - channel ID with bitfield */ - /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */ - /* shift AWD1 equivalent single-all channels out of register) */ - /* - AWD2-3 enable or disable */ - /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */ - /* channel can be read back if only 1 channel monitoring */ - /* is activated, therefore the channel monitoring value channel "3" */ - /* is not not supported by this function, there is no risk of */ - /* conflict. */ - register uint32_t AWD23Enabled = ((0x00000001U >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */ - - register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup - | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - | ((ADC_CFGR_AWD1SGL) >> ((0x00000001U >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U)) - | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) - ) >> AWD23Enabled - ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U)); + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if(AnalogWDMonitChannels != 0) + { + if(AWDy == LL_ADC_AWD1) + { + if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (( AnalogWDMonitChannels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) + ); + } + } + else + { + if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK + | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) + ); + } + else + { + /* AWD monitoring a single channel */ + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = ( AnalogWDMonitChannels + | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) + ); + } + } + } - return (AWD1ChannelGroup | AWD23ChannelGroup); + return AnalogWDMonitChannels; + } /** @@ -5232,7 +5312,11 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); +#endif MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5271,7 +5355,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. + * on either ADC groups regular or injected. * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n @@ -5286,7 +5370,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) @@ -5296,11 +5380,19 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow)); +#endif } /** @@ -5333,12 +5425,21 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + (AWDThresholdsHighLow | ADC_TR1_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) + ); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> POSITION_VAL(AWDThresholdsHighLow) ); +#endif } /** @@ -6284,7 +6385,11 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6311,7 +6416,11 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6338,7 +6447,11 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6365,7 +6478,11 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6392,7 +6509,11 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h index c4ffe5a34e7..a547514fcb3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_bus.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of BUS LL module. @verbatim @@ -92,12 +90,18 @@ extern "C" { #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(DMAMUX1) +#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN +#endif /* DMAMUX1 */ #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN #if defined(DMA2D) #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN #endif /* DMA2D */ +#if defined(GFXMMU) +#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN +#endif /* GFXMMU */ #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN /** * @} @@ -140,7 +144,16 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN #endif /* HASH */ #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#if defined(OCTOSPIM) +#define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN +#endif /* OCTOSPIM */ +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN +#if defined(SRAM3_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN +#endif /* SRAM3_BASE */ /** * @} */ @@ -152,7 +165,15 @@ extern "C" { #if defined(FMC_Bank1_R) #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN #endif /* FMC_Bank1_R */ +#if defined(QUADSPI) #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN +#endif /* OCTOSPI2 */ /** * @} */ @@ -240,9 +261,9 @@ extern "C" { #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #if defined(TIM8) @@ -261,6 +282,12 @@ extern "C" { #if defined(DFSDM1_Channel0) #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN #endif /* DFSDM1_Channel0 */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ /** * @} */ @@ -293,17 +320,21 @@ extern "C" { * @brief Enable AHB1 peripherals clock. * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -321,17 +352,21 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * @brief Check if AHB1 peripheral clock is enabled or not * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -345,17 +380,21 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @brief Disable AHB1 peripherals clock. * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -369,18 +408,22 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * @brief Force AHB1 peripherals reset. * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -394,18 +437,22 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @brief Release AHB1 peripherals reset. * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1ENR DMA2DRST LL_AHB1_GRP1_ReleaseReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -419,19 +466,23 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -449,19 +500,23 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -495,7 +550,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -512,6 +569,8 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -541,7 +600,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -558,6 +619,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -583,7 +646,9 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -600,6 +665,8 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -625,7 +692,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -643,6 +712,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -668,7 +739,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -686,6 +759,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -707,12 +782,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -724,12 +802,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) * @arg @ref LL_AHB2_GRP1_PERIPH_ADC * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -755,12 +836,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -772,12 +856,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) * @arg @ref LL_AHB2_GRP1_PERIPH_ADC * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -798,10 +885,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) /** * @brief Enable AHB3 peripherals clock. * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -818,10 +909,14 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB3 peripheral clock is enabled or not * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -834,10 +929,14 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB3 peripherals clock. * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -850,11 +949,15 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB3 peripherals reset. * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -867,11 +970,15 @@ __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB3 peripherals reset. * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -884,10 +991,14 @@ __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep + * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -904,10 +1015,14 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep + * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -1547,7 +1662,9 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_FW @@ -1562,6 +1679,8 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1589,7 +1708,9 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_FW @@ -1604,6 +1725,8 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -1626,7 +1749,9 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) @@ -1640,6 +1765,8 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1662,7 +1789,9 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG @@ -1677,6 +1806,8 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1699,7 +1830,9 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG @@ -1714,6 +1847,8 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1736,7 +1871,9 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep + * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) @@ -1750,6 +1887,8 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1776,7 +1915,9 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep + * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) @@ -1790,6 +1931,8 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c index 27b494cdc0c..9f902eb443f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_comp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief COMP LL module driver ****************************************************************************** * @attention @@ -94,7 +92,7 @@ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ -#if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT) +#if defined(COMP_CSR_INMESEL_1) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -108,30 +106,6 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5) \ ) -#elif defined(COMP_CSR_INMESEL_1) -#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5) \ - ) -#elif defined(DAC_CHANNEL2_SUPPORT) -#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ - ) #else #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ @@ -139,6 +113,7 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ ) @@ -156,14 +131,25 @@ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) -#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + ? ( \ + (1U) \ + ) \ + : \ + (((__COMP_INSTANCE__) == COMP1) \ + ? ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + ) \ + : \ + ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ + ) \ + ) \ ) /** @@ -241,7 +227,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus)); assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis)); assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); - assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource)); + assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource)); /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ @@ -305,8 +291,8 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /** * @brief Set each @ref LL_COMP_InitTypeDef field to default value. - * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure - * whose fields will be set to default values. + * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure + * whose fields will be set to default values. * @retval None */ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h index 8d5d8f6ff33..8b02ddb71e0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_comp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of COMP LL module. ****************************************************************************** * @attention @@ -64,7 +62,7 @@ extern "C" { */ /* COMP registers bits positions */ -#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ +#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ /** * @} @@ -127,7 +125,7 @@ typedef struct /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ -#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */ +#define LL_COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */ #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ /** * @} @@ -136,7 +134,7 @@ typedef struct /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ -#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */ +#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< COMP power mode to high speed */ #define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ /** @@ -146,7 +144,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection * @{ */ -#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -163,9 +161,7 @@ typedef struct #define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */ #define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */ #define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ -#if defined(DAC_CHANNEL2_SUPPORT) #define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ -#endif #define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ #define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ #if defined(COMP_CSR_INMESEL_1) @@ -187,9 +183,7 @@ typedef struct #define LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT #define LL_COMP_INVERTINGINPUT_VREFINT LL_COMP_INPUT_MINUS_VREFINT #define LL_COMP_INVERTINGINPUT_DAC1 LL_COMP_INPUT_MINUS_DAC1_CH1 -#if defined(DAC_CHANNEL2_SUPPORT) #define LL_COMP_INVERTINGINPUT_DAC2 LL_COMP_INPUT_MINUS_DAC1_CH2 -#endif #define LL_COMP_INVERTINGINPUT_IO1 LL_COMP_INPUT_MINUS_IO1 #define LL_COMP_INVERTINGINPUT_IO2 LL_COMP_INPUT_MINUS_IO2 #if defined(COMP_CSR_INMESEL_1) @@ -210,7 +204,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis * @{ */ -#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */ +#define LL_COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ #define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ @@ -221,7 +215,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity * @{ */ -#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ +#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ #define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */ /** * @} @@ -230,7 +224,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source * @{ */ -#define LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U) /*!__REG__, (__VALUE__)) +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) /** * @brief Read a value in CRC register @@ -354,7 +352,10 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) */ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) { - *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData; + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); + *pReg = InData; } /** @@ -418,10 +419,11 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) /** * @brief Return data stored in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. * @rmtoll IDR IDR LL_CRC_Read_IDR * @param CRCx CRC Instance - * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + * @retval Value stored in CRC_IDR register */ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) { @@ -430,15 +432,20 @@ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) /** * @brief Store data in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. * @rmtoll IDR IDR LL_CRC_Write_IDR * @param CRCx CRC Instance - * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF + * @param InData value to be stored in CRC_IDR register * @retval None */ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) { +#if (CRC_IDR_IDR == 0x0FFU) *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +#else + WRITE_REG(CRCx->IDR, InData); +#endif } /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c index a0a8108087b..83b775ad360 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_crs.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CRS LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h index 40267e697e0..4eb39e09890 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_crs.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRS LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c index 79f8ba4867a..30a154f9703 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DAC LL module driver ****************************************************************************** * @attention @@ -78,6 +76,22 @@ ) #endif /* DAC_CHANNEL2_SUPPORT */ +#if defined (DAC_CR_TSEL1_3) +#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + ) +#else #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ @@ -88,6 +102,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) +#endif /* DAC_CR_TSEL1_3 */ #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h index 74c41604b7a..e312a599c3a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -269,14 +267,29 @@ typedef struct /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source * @{ */ -#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ -#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ -#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#if defined (DAC_CR_TSEL1_3) +#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ +#else +#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c index 88ab69fa2ee..c60a79c7e20 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32l4xx_ll_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA LL module driver. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,8 +81,11 @@ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) +#if defined(DMAMUX1) +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 93U) +#else #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ ((__VALUE__) == LL_DMA_REQUEST_1) || \ ((__VALUE__) == LL_DMA_REQUEST_2) || \ @@ -93,6 +94,7 @@ ((__VALUE__) == LL_DMA_REQUEST_5) || \ ((__VALUE__) == LL_DMA_REQUEST_6) || \ ((__VALUE__) == LL_DMA_REQUEST_7)) +#endif /* DMAMUX1 */ #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ @@ -226,8 +228,13 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Reset DMAx_Channely memory address register */ LL_DMA_WriteReg(tmp, CMAR, 0U); +#if defined(DMAMUX1) + /* Reset Request register field for DMAx Channel */ + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQUEST_MEM2MEM); +#else /* Reset Request register field for DMAx Channel */ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); +#endif /* DMAMUX1 */ if (Channel == LL_DMA_CHANNEL_1) { @@ -347,11 +354,19 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM */ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); +#if defined(DMAMUX1) + /*--------------------------- DMAMUXx CCR Configuration ---------------------- + * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : + * - PeriphRequest: DMA_CxCR[7:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); +#else /*--------------------------- DMAx CSELR Configuration ----------------------- - * Configure the peripheral base address with parameter : + * Configure the DMA request for DMA instance on Channel x with parameter : * - PeriphRequest: DMA_CSELR[31:0] bits */ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); +#endif /* DMAMUX1 */ return SUCCESS; } @@ -364,16 +379,20 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) { /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = (uint32_t)0x00000000U; + DMA_InitStruct->NbData = 0x00000000U; +#if defined(DMAMUX1) + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQUEST_MEM2MEM; +#else DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; +#endif /* DMAMUX1 */ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h index 65ac16c4050..f6c75b04167 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA LL module. ****************************************************************************** * @attention @@ -45,6 +43,9 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx.h" +#if defined(DMAMUX1) +#include "stm32l4xx_ll_dmamux.h" +#endif /* DMAMUX1 */ /** @addtogroup STM32L4xx_LL_Driver * @{ @@ -77,6 +78,8 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +#if defined(DMAMUX1) +#else /** @defgroup DMA_LL_Private_Constants DMA Private Constants * @{ */ @@ -88,8 +91,27 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = /** * @} */ +#endif /* DMAMUX1 */ /* Private macros ------------------------------------------------------------*/ +#if defined(DMAMUX1) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). + */ +#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) + +/** + * @} + */ +#else #if defined(USE_FULL_LL_DRIVER) /** @defgroup DMA_LL_Private_Macros DMA Private Macros * @{ @@ -98,6 +120,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = * @} */ #endif /*USE_FULL_LL_DRIVER*/ +#endif /* DMAMUX1 */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) @@ -159,11 +182,19 @@ typedef struct This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ +#if defined(DMAMUX1) + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#else uint32_t PeriphRequest; /*!< Specifies the peripheral request. This parameter can be a value of @ref DMA_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#endif /* DMAMUX1 */ uint32_t Priority; /*!< Specifies the channel priority level. This parameter can be a value of @ref DMA_LL_EC_PRIORITY @@ -266,15 +297,15 @@ typedef struct /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ -#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ -#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} @@ -283,7 +314,7 @@ typedef struct /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction * @{ */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** @@ -293,7 +324,7 @@ typedef struct /** @defgroup DMA_LL_EC_MODE Transfer mode * @{ */ -#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ /** * @} @@ -303,7 +334,7 @@ typedef struct * @{ */ #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -312,7 +343,7 @@ typedef struct * @{ */ #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -320,7 +351,7 @@ typedef struct /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment * @{ */ -#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** @@ -330,7 +361,7 @@ typedef struct /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment * @{ */ -#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** @@ -340,7 +371,7 @@ typedef struct /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level * @{ */ -#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ @@ -348,20 +379,123 @@ typedef struct * @} */ +#if defined(DMAMUX1) +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQUEST_MEM2MEM 0U /*!< Memory to memory transfer */ +#define LL_DMAMUX_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ +#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ +#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ +#define LL_DMAMUX_REQUEST_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ +#define LL_DMAMUX_REQUEST_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQUEST_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQUEST_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQUEST_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQUEST_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQUEST_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ +#define LL_DMAMUX_REQUEST_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQUEST_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQUEST_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQUEST_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQUEST_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQUEST_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQUEST_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ +#define LL_DMAMUX_REQUEST_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ +#define LL_DMAMUX_REQUEST_USART1_RX 24U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQUEST_USART1_TX 25U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQUEST_USART2_RX 26U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQUEST_USART2_TX 27U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQUEST_USART3_RX 28U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQUEST_USART3_TX 29U /*!< DMAMUX USART3 TX request */ +#define LL_DMAMUX_REQUEST_UART4_RX 30U /*!< DMAMUX UART4 RX request */ +#define LL_DMAMUX_REQUEST_UART4_TX 31U /*!< DMAMUX UART4 TX request */ +#define LL_DMAMUX_REQUEST_UART5_RX 32U /*!< DMAMUX UART5 RX request */ +#define LL_DMAMUX_REQUEST_UART5_TX 33U /*!< DMAMUX UART5 TX request */ +#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ +#define LL_DMAMUX_REQUEST_SAI1_A 36U /*!< DMAMUX SAI1 A request */ +#define LL_DMAMUX_REQUEST_SAI1_B 37U /*!< DMAMUX SAI1 B request */ +#define LL_DMAMUX_REQUEST_SAI2_A 38U /*!< DMAMUX SAI2 A request */ +#define LL_DMAMUX_REQUEST_SAI2_B 39U /*!< DMAMUX SAI2 B request */ +#define LL_DMAMUX_REQUEST_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ +#define LL_DMAMUX_REQUEST_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ +#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ +#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ +#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ +#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ +#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ +#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ +#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ +#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ +#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ +#define LL_DMAMUX_REQUEST_DCMI 90U /*!< DMAMUX DCMI request */ +#define LL_DMAMUX_REQUEST_AES_IN 91U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQUEST_AES_OUT 92U /*!< DMAMUX AES_OUT request */ +#define LL_DMAMUX_REQUEST_HASH_IN 93U /*!< DMAMUX HASH_IN request */ +/** + * @} + */ +#else /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request * @{ */ -#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */ -#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */ -#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */ -#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */ -#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */ -#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */ -#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */ -#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ /** * @} */ +#endif /* DMAMUX1 */ /** * @} @@ -1198,6 +1332,238 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } +#if defined(DMAMUX1) +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 + * @arg @ref LL_DMAMUX_REQUEST_ADC1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP + * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX + * @arg @ref LL_DMAMUX_REQUEST_USART1_RX + * @arg @ref LL_DMAMUX_REQUEST_USART1_TX + * @arg @ref LL_DMAMUX_REQUEST_USART2_RX + * @arg @ref LL_DMAMUX_REQUEST_USART2_TX + * @arg @ref LL_DMAMUX_REQUEST_USART3_RX + * @arg @ref LL_DMAMUX_REQUEST_USART3_TX + * @arg @ref LL_DMAMUX_REQUEST_UART4_RX + * @arg @ref LL_DMAMUX_REQUEST_UART4_TX + * @arg @ref LL_DMAMUX_REQUEST_UART5_RX + * @arg @ref LL_DMAMUX_REQUEST_UART5_TX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX + * @arg @ref LL_DMAMUX_REQUEST_SAI1_A + * @arg @ref LL_DMAMUX_REQUEST_SAI1_B + * @arg @ref LL_DMAMUX_REQUEST_SAI2_A + * @arg @ref LL_DMAMUX_REQUEST_SAI2_B + * @arg @ref LL_DMAMUX_REQUEST_OSPI1 + * @arg @ref LL_DMAMUX_REQUEST_OSPI2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQUEST_DCMI + * @arg @ref LL_DMAMUX_REQUEST_AES_IN + * @arg @ref LL_DMAMUX_REQUEST_AES_OUT + * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 + * @arg @ref LL_DMAMUX_REQUEST_ADC1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP + * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX + * @arg @ref LL_DMAMUX_REQUEST_USART1_RX + * @arg @ref LL_DMAMUX_REQUEST_USART1_TX + * @arg @ref LL_DMAMUX_REQUEST_USART2_RX + * @arg @ref LL_DMAMUX_REQUEST_USART2_TX + * @arg @ref LL_DMAMUX_REQUEST_USART3_RX + * @arg @ref LL_DMAMUX_REQUEST_USART3_TX + * @arg @ref LL_DMAMUX_REQUEST_UART4_RX + * @arg @ref LL_DMAMUX_REQUEST_UART4_TX + * @arg @ref LL_DMAMUX_REQUEST_UART5_RX + * @arg @ref LL_DMAMUX_REQUEST_UART5_TX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX + * @arg @ref LL_DMAMUX_REQUEST_SAI1_A + * @arg @ref LL_DMAMUX_REQUEST_SAI1_B + * @arg @ref LL_DMAMUX_REQUEST_SAI2_A + * @arg @ref LL_DMAMUX_REQUEST_SAI2_B + * @arg @ref LL_DMAMUX_REQUEST_OSPI1 + * @arg @ref LL_DMAMUX_REQUEST_OSPI2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQUEST_DCMI + * @arg @ref LL_DMAMUX_REQUEST_AES_IN + * @arg @ref LL_DMAMUX_REQUEST_AES_OUT + * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} +#else /** * @brief Set DMA request for DMA instance on Channel x. * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. @@ -1267,6 +1633,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); } +#endif /* DMAMUX1 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c index 2bdd4e5aaa3..3f1012ea3e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA2D LL module driver. ****************************************************************************** * @attention @@ -73,10 +71,19 @@ /** @addtogroup DMA2D_LL_Private_Macros * @{ */ +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) +#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ + ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \ + ((MODE) == LL_DMA2D_MODE_R2M)) +#else #define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ ((MODE) == LL_DMA2D_MODE_R2M)) +#endif #define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ @@ -202,6 +209,12 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed)); assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue)); assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha)); +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + assert_param(IS_LL_DMA2D_SWAP_MODE(DMA2D_InitStruct->OutputSwapMode)); +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + assert_param(IS_LL_DMA2D_OFFSET_MODE(DMA2D_InitStruct->LineOffsetMode)); +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset)); assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode)); assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode)); @@ -213,11 +226,21 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U)) { /* DMA2D CR register configuration -------------------------------------------*/ +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + MODIFY_REG(DMA2Dx->CR, (DMA2D_CR_MODE | DMA2D_CR_LOM), \ + (DMA2D_InitStruct->Mode | DMA2D_InitStruct->LineOffsetMode)); +#else LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode); +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB | DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), \ + (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->OutputSwapMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); +#else MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \ (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ /* DMA2D OOR register configuration ------------------------------------------*/ LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); @@ -256,12 +279,18 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888; DMA2D_InitStruct->NbrOfLines = 0x0U; DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U; +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + DMA2D_InitStruct->LineOffsetMode = LL_DMA2D_LINE_OFFSET_PIXELS; +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ DMA2D_InitStruct->LineOffset = 0x0U; DMA2D_InitStruct->OutputBlue = 0x0U; DMA2D_InitStruct->OutputGreen = 0x0U; DMA2D_InitStruct->OutputRed = 0x0U; DMA2D_InitStruct->OutputAlpha = 0x0U; DMA2D_InitStruct->OutputMemoryAddress = 0x0U; +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + DMA2D_InitStruct->OutputSwapMode = LL_DMA2D_SWAP_MODE_REGULAR; +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h index d0069d03b40..3cf689e7111 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA2D LL module. ****************************************************************************** * @attention @@ -135,8 +133,23 @@ typedef struct This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. + - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + uint32_t LineOffset; /*!< Specifies the output line offset value. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on STM32L496xx/STM32L4A6xx + else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices. This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ @@ -355,7 +368,11 @@ typedef struct #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ -#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ +#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */ +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */ +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */ +#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ /** * @} */ @@ -401,6 +418,17 @@ typedef struct * @} */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) +/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode + * @{ + */ +#define LL_DMA2D_SWAP_MODE_REGULAR ((uint32_t)0x00000000) /*!< Regular order */ +#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ +/** + * @} + */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap * @{ */ @@ -419,6 +447,17 @@ typedef struct * @} */ +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) +/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode + * @{ + */ +#define LL_DMA2D_LINE_OFFSET_PIXELS ((uint32_t)0x00000000) /*!< Line offsets are expressed in pixels */ +#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ +/** + * @} + */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode * @{ */ @@ -567,6 +606,10 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) * @arg @ref LL_DMA2D_MODE_M2M_PFC * @arg @ref LL_DMA2D_MODE_M2M_BLEND * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*) + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) @@ -583,6 +626,10 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_PFC * @arg @ref LL_DMA2D_MODE_M2M_BLEND * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*) + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) { @@ -676,11 +723,73 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) +/** + * @brief Set DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @param OutputSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); +} + +/** + * @brief Return DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); +} +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) +/** + * @brief Set DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @param LineOffsetMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); +} + +/** + * @brief Return DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); +} +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + /** * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). * @rmtoll OOR LO LL_DMA2D_SetLineOffset * @param DMA2Dx DMA2D Instance + @if DMA2D_LINE_OFFSET_MODE_SUPPORT + * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF + @else * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF + @endif * @retval None */ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) @@ -692,7 +801,11 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). * @rmtoll OOR LO LL_DMA2D_GetLineOffset * @param DMA2Dx DMA2D Instance + @if DMA2D_LINE_OFFSET_MODE_SUPPORT + * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF + @else * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF + @endif */ __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h new file mode 100644 index 00000000000..66a10c9d19e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h @@ -0,0 +1,1795 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_LL_DMAMUX_H +#define __STM32L4xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0U /*!< Memory to memory transfer */ +#define LL_DMAMUX_REQ_GENERATOR0 1U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 2U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 3U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 4U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQ_ADC1 5U /*!< DMAMUX ADC1 request */ +#define LL_DMAMUX_REQ_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ +#define LL_DMAMUX_REQ_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ +#define LL_DMAMUX_REQ_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ +#define LL_DMAMUX_REQ_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ +#define LL_DMAMUX_REQ_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQ_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ +#define LL_DMAMUX_REQ_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQ_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQ_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ +#define LL_DMAMUX_REQ_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ +#define LL_DMAMUX_REQ_USART1_RX 24U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 25U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 26U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 27U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQ_USART3_RX 28U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 29U /*!< DMAMUX USART3 TX request */ +#define LL_DMAMUX_REQ_UART4_RX 30U /*!< DMAMUX UART4 RX request */ +#define LL_DMAMUX_REQ_UART4_TX 31U /*!< DMAMUX UART4 TX request */ +#define LL_DMAMUX_REQ_UART5_RX 32U /*!< DMAMUX UART5 RX request */ +#define LL_DMAMUX_REQ_UART5_TX 33U /*!< DMAMUX UART5 TX request */ +#define LL_DMAMUX_REQ_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ +#define LL_DMAMUX_REQ_SAI1_A 36U /*!< DMAMUX SAI1 A request */ +#define LL_DMAMUX_REQ_SAI1_B 37U /*!< DMAMUX SAI1 B request */ +#define LL_DMAMUX_REQ_SAI2_A 38U /*!< DMAMUX SAI2 A request */ +#define LL_DMAMUX_REQ_SAI2_B 39U /*!< DMAMUX SAI2 B request */ +#define LL_DMAMUX_REQ_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ +#define LL_DMAMUX_REQ_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ +#define LL_DMAMUX_REQ_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQ_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQ_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ +#define LL_DMAMUX_REQ_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ +#define LL_DMAMUX_REQ_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ +#define LL_DMAMUX_REQ_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ +#define LL_DMAMUX_REQ_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ +#define LL_DMAMUX_REQ_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ +#define LL_DMAMUX_REQ_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ +#define LL_DMAMUX_REQ_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ +#define LL_DMAMUX_REQ_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ +#define LL_DMAMUX_REQ_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQ_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQ_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQ_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQ_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQ_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ +#define LL_DMAMUX_REQ_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ +#define LL_DMAMUX_REQ_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ +#define LL_DMAMUX_REQ_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ +#define LL_DMAMUX_REQ_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ +#define LL_DMAMUX_REQ_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ +#define LL_DMAMUX_REQ_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ +#define LL_DMAMUX_REQ_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ +#define LL_DMAMUX_REQ_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ +#define LL_DMAMUX_REQ_DCMI 90U /*!< DMAMUX DCMI request */ +#define LL_DMAMUX_REQ_AES_IN 91U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 92U /*!< DMAMUX AES_OUT request */ +#define LL_DMAMUX_REQ_HASH_IN 93U /*!< DMAMUX HASH_IN request */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 1U /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 2U /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 3U /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 4U /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 5U /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 6U /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 7U /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 8U /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 9U /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 10U /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 11U /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 12U /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 13U /*!< Synchronization signal from EXTI Line13 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 14U /*!< Synchronization signal from EXTI Line14 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 15U /*!< Synchronization signal from EXTI Line15 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 16U /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 17U /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 18U /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 19U /*!< Synchronization signal from DMAMUX channel3 Event */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT 20U /*!< Synchronization signal from LPTIM1 Ouput */ +#define LL_DMAMUX_SYNC_LPTIM2_OUT 21U /*!< Synchronization signal from LPTIM2 Ouput */ +#define LL_DMAMUX_SYNC_DSI_TE 22U /*!< Synchronization signal from DSI Tearing Effect */ +#define LL_DMAMUX_SYNC_DSI_REFRESH_END 23U /*!< Synchronization signal from DSI End of Refresh */ +#define LL_DMAMUX_SYNC_DMA2D_TX_END 24U /*!< Synchronization signal from DMA2D End of Transfer */ +#define LL_DMAMUX_SYNC_LTDC_LINE_IT 25U /*!< Synchronization signal from LTDC Line Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 1U /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 2U /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 3U /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 4U /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 5U /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 6U /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 7U /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 8U /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 9U /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 10U /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 11U /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 12U /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 13U /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 14U /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 15U /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 16U /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 17U /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 18U /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 19U /*!< Request signal generation from DMAMUX channel3 Event */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT 20U /*!< Request signal generation from LPTIM1 Ouput */ +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT 21U /*!< Request signal generation from LPTIM2 Ouput */ +#define LL_DMAMUX_REQ_GEN_DSI_TE 22U /*!< Request signal generation from DSI Tearing Effect */ +#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END 23U /*!< Request signal generation from DSI End of Refresh */ +#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END 24U /*!< Request signal generation from DMA2D End of Transfer */ +#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT 25U /*!< Request signal generation from LTDC Line Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel-1)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ, RequestNb - 1); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ) + 1); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_DSI_TE + * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END + * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_DSI_TE + * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END + * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END + * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END + * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE)); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_LL_DMAMUX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c index e94a1192ba4..c97b41c1268 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_exti.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief EXTI LL module driver. ****************************************************************************** * @attention @@ -108,11 +106,15 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR1, 0x00000000U); /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER1, 0x00000000U); - /* Pending register set to default reset values */ + /* Pending register clear */ LL_EXTI_WriteReg(PR1, 0x007DFFFFU); /* Interrupt mask register 2 set to default reset values */ +#if defined(LL_EXTI_LINE_40) + LL_EXTI_WriteReg(IMR2, 0x00000187U); +#else LL_EXTI_WriteReg(IMR2, 0x00000087U); +#endif /* Event mask register 2 set to default reset values */ LL_EXTI_WriteReg(EMR2, 0x00000000U); /* Rising Trigger selection register 2 set to default reset values */ @@ -121,7 +123,7 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR2, 0x00000000U); /* Software interrupt event register 2 set to default reset values */ LL_EXTI_WriteReg(SWIER2, 0x00000000U); - /* Pending register 2 set to default reset values */ + /* Pending register 2 clear */ LL_EXTI_WriteReg(PR2, 0x00000078U); return SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h index 8e31cc7a09f..9127ab2f913 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_exti.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention @@ -187,6 +185,9 @@ typedef struct #if defined(EXTI_IMR2_IM39) #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ #endif +#if defined(EXTI_IMR2_IM40) +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#endif #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ @@ -329,13 +330,15 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) @@ -400,13 +403,15 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) @@ -471,13 +476,15 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) @@ -545,13 +552,15 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -610,13 +619,15 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -676,13 +687,15 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c index 509f8b2c721..c052ded246d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_fmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -111,7 +109,17 @@ /* --- BCR Register ---*/ /* BCR register clear mask */ -#if defined(FMC_BCR1_WFDIS) +#if defined(FMC_BCRx_NBLSET) +#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ + FMC_BCRx_MTYP | FMC_BCRx_MWID |\ + FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ + FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ + FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ + FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ + FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ + FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS |\ + FMC_BCRx_NBLSET)) +#elif defined(FMC_BCR1_WFDIS) #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ FMC_BCRx_MTYP | FMC_BCRx_MWID |\ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ @@ -133,16 +141,29 @@ /* --- BTR Register ---*/ /* BTR register clear mask */ -#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ - FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ - FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ - FMC_BTRx_ACCMOD)) +#if defined(FMC_BTRx_DATAHLD) +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ + FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ + FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ + FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD)) +#else +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ + FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ + FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ + FMC_BTRx_ACCMOD)) +#endif /* FMC_BTRx_DATAHLD */ /* --- BWTR Register ---*/ /* BWTR register clear mask */ -#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD | \ - FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD | \ - FMC_BWTRx_BUSTURN)) +#if defined(FMC_BWTRx_DATAHLD) +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ + FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ + FMC_BWTRx_ACCMOD)) +#endif /* FMC_BWTRx_DATAHLD */ /** * @} @@ -234,6 +255,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); #endif /* FMC_BCR1_WFDIS */ +#if defined(FMC_BCRx_NBLSET) + assert_param(IS_FMC_NBLSETUP_TIME(Init->NBLSetupTime)); +#endif /* FMC_BCRx_NBLSET */ assert_param(IS_FMC_PAGESIZE(Init->PageSize)); /* Disable NORSRAM Device */ @@ -258,6 +282,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) | Init->WriteFifo #endif /* FMC_BCR1_WFDIS */ +#if defined(FMC_BCRx_NBLSET) + | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) +#endif /* FMC_BCRx_NBLSET */ | Init->PageSize ) ); @@ -280,6 +307,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) | Init->WriteFifo #endif /* FMC_BCR1_WFDIS */ +#if defined(FMC_BCRx_NBLSET) + | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) +#endif /* FMC_BCRx_NBLSET */ | Init->PageSize ) ); @@ -297,8 +327,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); } - #endif /* FMC_BCR1_WFDIS */ + return HAL_OK; } @@ -356,6 +386,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); +#if defined(FMC_BTRx_DATAHLD) + assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); +#endif /* FMC_BTRx_DATAHLD */ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); @@ -363,14 +396,17 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1], \ - BTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | \ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | \ - (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | \ - (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | \ + MODIFY_REG(Device->BTCR[Bank + 1], + BTR_CLEAR_MASK, + (uint32_t)(Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | + ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | +#if defined(FMC_BTRx_DATAHLD) + ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | +#endif /* FMC_BTRx_DATAHLD */ + ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | + (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | + (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | (Timing->AccessMode))); /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ @@ -408,18 +444,24 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); +#if defined(FMC_BTRx_DATAHLD) + assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); +#endif /* FMC_BTRx_DATAHLD */ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - MODIFY_REG(Device->BWTR[Bank], \ - BWTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | \ - Timing->AccessMode | \ + MODIFY_REG(Device->BWTR[Bank], + BWTR_CLEAR_MASK, + (uint32_t)(Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | + ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | +#if defined(FMC_BTRx_DATAHLD) + ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | +#endif /* FMC_BTRx_DATAHLD */ + Timing->AccessMode | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BWTRx_BUSTURN)))); } else diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h index c6e66f07c78..e22ecd214d9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_fmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention @@ -91,8 +89,12 @@ extern "C" { #if defined(FMC_BCR1_WFDIS) #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) - #endif /* FMC_BCR1_WFDIS */ + +#if defined(FMC_BCRx_NBLSET) +#define IS_FMC_NBLSETUP_TIME(__TIME__) ((__TIME__) <= 3) +#endif /* FMC_BCRx_NBLSET */ + #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ ((__MODE__) == FMC_ACCESS_MODE_B) || \ ((__MODE__) == FMC_ACCESS_MODE_C) || \ @@ -247,6 +249,16 @@ extern "C" { * @} */ +#if defined(FMC_BTRx_DATAHLD) +/** @defgroup FMC_Data_Hold_Time + * @{ + */ +#define IS_FMC_DATAHOLD_TIME(__TIME__) ((__TIME__) <= 3) +/** + * @} + */ +#endif /* FMC_BTRx_DATAHLD */ + /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration * @{ */ @@ -333,6 +345,13 @@ typedef struct This parameter can be a value of @ref FMC_Write_FIFO. @note This Parameter is not available for STM32L47x/L48x devices. */ +#if defined(FMC_BCRx_NBLSET) + uint32_t NBLSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the byte lane (NBL) setup time from NBLx low to Chip select NEx low. + This parameter can be a value between Min_Data = 0 and Max_Data = 3. + @note This parameter is used for SRAMs, ROMs and NOR Flash memories. */ +#endif /* FMC_BCRx_NBLSET */ + uint32_t PageSize; /*!< Specifies the memory page size. This parameter can be a value of @ref FMC_Page_Size */ }FMC_NORSRAM_InitTypeDef; @@ -358,6 +377,16 @@ typedef struct @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ +#if defined(FMC_BTRx_DATAHLD) + uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data hold time. + This parameter can be a value between Min_Data = 0 and Max_Data = 3. + @note This parameter value corresponds to x HCLK cycles for read and + x+1 HCLK cycles for write. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ +#endif /* FMC_BTRx_DATAHLD */ + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. @@ -725,9 +754,9 @@ typedef struct * @brief FMC Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) -#define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) -#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) +#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) +#define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) +#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c index ea68657a926..0bd742a8d26 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief GPIO LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h index 0b0a30722c3..ae61d32827a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c index 123155a1b41..8d8105b0de5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_i2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief I2C LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h index bcb74180e87..564210d4892 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of I2C LL module. ****************************************************************************** * @attention @@ -283,14 +281,14 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -1099,7 +1097,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) + uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); @@ -2106,9 +2104,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h index d691da4efa5..0ab5630db21 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c index 5eef8c67eee..c776c5c67c3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LPTIM LL module driver. ****************************************************************************** * @attention @@ -63,23 +61,23 @@ /** @addtogroup LPTIM_LL_Private_Macros * @{ */ -#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) - -#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) - -#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) - -#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) +#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + +#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -169,10 +167,10 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); - assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); - assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); /* Set CKSEL bitfield according to ClockSource value */ /* Set PRESC bitfield according to Prescaler value */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h index 3edb39542b4..fc04402a399 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LPTIM LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c index 7b1459a329b..dc74d16025f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lpuart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LPUART LL module driver. ****************************************************************************** * @attention @@ -75,6 +73,21 @@ /* Check of parameters for configuration of LPUART registers */ +#if defined(USART_PRESC_PRESCALER) +#define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + +#endif /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ /* value : */ /* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ @@ -172,6 +185,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART /* Check the parameters */ assert_param(IS_LPUART_INSTANCE(LPUARTx)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); +#endif assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); @@ -211,6 +227,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); /* Configure the LPUART Baud Rate : +#if defined(USART_PRESC_PRESCALER) + - prescaler value is required +#endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -220,11 +239,22 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART status = SUCCESS; LL_LPUART_SetBaudRate(LPUARTx, periphclk, +#if defined(USART_PRESC_PRESCALER) + LPUART_InitStruct->PrescalerValue, +#endif LPUART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 0x300 */ assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR)); } +#if defined(USART_PRESC_PRESCALER) + + /*---------------------------- LPUART PRESC Configuration ----------------------- + * Configure LPUARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. + */ + LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); +#endif } return (status); @@ -240,6 +270,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) { /* Set LPUART_InitStruct fields to default values */ +#if defined(USART_PRESC_PRESCALER) + LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; +#endif LPUART_InitStruct->BaudRate = 9600U; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h index 076c3bd3882..d91b7294587 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lpuart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LPUART LL module. ****************************************************************************** * @attention @@ -58,6 +56,30 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ +#endif /* Private constants ---------------------------------------------------------*/ /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants @@ -93,6 +115,13 @@ extern "C" { */ typedef struct { +#if defined(USART_PRESC_PRESCALER) + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ + +#endif uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ @@ -143,6 +172,9 @@ typedef struct #define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ +#endif #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ @@ -160,9 +192,17 @@ typedef struct #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#else #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#endif #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#else #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#endif #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ @@ -172,6 +212,12 @@ typedef struct #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#endif /** * @} */ @@ -181,17 +227,48 @@ typedef struct * @{ */ #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#else #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#endif #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#else #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#endif #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#endif #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#endif /** * @} */ +#if defined(USART_CR1_FIFOEN) + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ +#endif /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ @@ -232,6 +309,27 @@ typedef struct /** * @} */ +#if defined(USART_PRESC_PRESCALER) + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +/** + * @} + */ +#endif /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ @@ -376,10 +474,30 @@ typedef struct * @brief Compute LPUARTDIV value according to Peripheral Clock and * expected Baud Rate (20-bit value of LPUARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + @if USART_PRESC_PRESCALER + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __PRESCALER__ Prescaler value + @endif * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ +#if defined(USART_PRESC_PRESCALER) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#else #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#endif /** * @} @@ -439,6 +557,137 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } +#if defined(USART_CR1_FIFOEN) +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); +} +#endif + /** * @brief LPUART enabled in STOP Mode * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that @@ -677,6 +926,55 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); } +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} +#endif + /** * @brief Set the length of the stop bits * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength @@ -1086,12 +1384,35 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) * @rmtoll BRR BRR LL_LPUART_SetBaudRate * @param LPUARTx LPUART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + @endif * @param BaudRate Baud Rate * @retval None */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) +#else __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate) +#endif { +#if defined(USART_PRESC_PRESCALER) + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); +#else LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); +#endif } /** @@ -1101,18 +1422,44 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri * @rmtoll BRR BRR LL_LPUART_GetBaudRate * @param LPUARTx LPUART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + @endif * @retval Baud Rate */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +#else __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk) +#endif { register uint32_t lpuartdiv = 0x0U; register uint32_t brrresult = 0x0U; +#if defined(USART_PRESC_PRESCALER) + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue])); +#endif lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; if (lpuartdiv >= LPUART_BRR_MIN_VALUE) { +#if defined(USART_PRESC_PRESCALER) + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); +#else brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); +#endif } return (brrresult); @@ -1336,6 +1683,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); +} +#else + /** * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE @@ -1346,6 +1710,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); } +#endif /** * @brief Check if the LPUART Transmission Complete Flag is set or not @@ -1358,6 +1723,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); +} +#else + /** * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE @@ -1368,6 +1750,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); } +#endif /** * @brief Check if the LPUART CTS interrupt Flag is set or not @@ -1468,6 +1851,53 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); +} +#endif + /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE @@ -1523,6 +1953,20 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Clear TX FIFO Empty Flag + * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); +} +#endif + /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC @@ -1586,6 +2030,23 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Enable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE @@ -1596,6 +2057,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Enable Transmission Complete Interrupt @@ -1608,6 +2070,23 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Enable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE @@ -1618,6 +2097,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Enable Parity Error Interrupt @@ -1641,6 +2121,31 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Enable Error Interrupt * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing @@ -1678,6 +2183,31 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Disable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE @@ -1689,6 +2219,23 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Disable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE @@ -1699,6 +2246,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Disable Transmission Complete Interrupt @@ -1711,6 +2259,23 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Disable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE @@ -1721,6 +2286,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Disable Parity Error Interrupt @@ -1744,6 +2310,31 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Disable Error Interrupt * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing @@ -1781,6 +2372,31 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE @@ -1792,6 +2408,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); +} +#else + /** * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE @@ -1802,6 +2435,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } +#endif /** * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. @@ -1814,6 +2448,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); +} +#else + /** * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled. * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE @@ -1824,6 +2475,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } +#endif /** * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. @@ -1846,6 +2498,30 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); +} +#endif /** * @brief Check if the LPUART Error Interrupt is enabled or disabled. @@ -1880,6 +2556,31 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); +} +#endif + /** * @} */ @@ -2100,7 +2801,13 @@ __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) } /** + @if USART_CR1_FIFOEN + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + @else * @brief Request a Receive Data flush + @endif * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush * @param LPUARTx LPUART Instance * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c index 49be22d1bb0..6e0653a3836 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_opamp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief OPAMP LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h index 22ee05d63b0..a77c0044e42 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_opamp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of OPAMP LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c index 7c6d7b16db8..b934799fda3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h index d870a8477de..1d1f4624c3b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PWR LL module. ****************************************************************************** * @attention @@ -185,7 +183,7 @@ extern "C" { /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR * @{ */ -#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000) +#define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U) #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) /** * @} @@ -218,22 +216,22 @@ extern "C" { /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT * @{ */ -#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001) -#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002) -#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004) -#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008) -#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010) -#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020) -#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040) -#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080) -#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100) -#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200) -#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400) -#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800) -#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000) -#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000) -#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000) -#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000) +#define LL_PWR_GPIO_BIT_0 (0x00000001U) +#define LL_PWR_GPIO_BIT_1 (0x00000002U) +#define LL_PWR_GPIO_BIT_2 (0x00000004U) +#define LL_PWR_GPIO_BIT_3 (0x00000008U) +#define LL_PWR_GPIO_BIT_4 (0x00000010U) +#define LL_PWR_GPIO_BIT_5 (0x00000020U) +#define LL_PWR_GPIO_BIT_6 (0x00000040U) +#define LL_PWR_GPIO_BIT_7 (0x00000080U) +#define LL_PWR_GPIO_BIT_8 (0x00000100U) +#define LL_PWR_GPIO_BIT_9 (0x00000200U) +#define LL_PWR_GPIO_BIT_10 (0x00000400U) +#define LL_PWR_GPIO_BIT_11 (0x00000800U) +#define LL_PWR_GPIO_BIT_12 (0x00001000U) +#define LL_PWR_GPIO_BIT_13 (0x00002000U) +#define LL_PWR_GPIO_BIT_14 (0x00004000U) +#define LL_PWR_GPIO_BIT_15 (0x00008000U) /** * @} */ @@ -303,16 +301,6 @@ __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); } -/** - * @brief Check if the regulator is in low-power mode - * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); -} - /** * @brief Switch from run main mode to run low-power mode. * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode @@ -333,8 +321,19 @@ __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) LL_PWR_DisableLowPowerRunMode(); } +/** + * @brief Check if the regulator is in low-power mode + * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); +} + /** * @brief Set the main internal regulator output voltage + * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices. * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling * @param VoltageScaling This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 @@ -358,6 +357,38 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); } +#if defined(PWR_CR5_R1MODE) +/** + * @brief Enable main regulator voltage range 1 boost mode + * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) +{ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); +} + +/** + * @brief Disable main regulator voltage range 1 boost mode + * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) +{ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); +} + +/** + * @brief Check if the main regulator voltage range 1 boost mode is enabled + * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) +{ + return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET); +} +#endif /* PWR_CR5_R1MODE */ + /** * @brief Enable access to the backup domain * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess @@ -419,6 +450,70 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); } +#if defined(PWR_CR1_RRSTP) +/** + * @brief Enable SRAM3 content retention in Stop mode + * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_RRSTP); +} + +/** + * @brief Disable SRAM3 content retention in Stop mode + * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); +} + +/** + * @brief Check if SRAM3 content retention in Stop mode is enabled + * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)); +} +#endif /* PWR_CR1_RRSTP */ + +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Disable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Check if pull-down activation on DSI pins is enabled + * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) +{ + return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); +} +#endif /* PWR_CR3_DSIPDEN */ + #if defined(PWR_CR2_PVME1) /** * @brief Enable VDDUSB supply @@ -661,7 +756,7 @@ __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) } /** - * @brief Check if pull-up and pull-down configuration is enabled + * @brief Check if pull-up and pull-down configuration is enabled * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg * @retval State of bit (1 or 0). */ @@ -670,6 +765,38 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); } +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableDSIPullDown(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Disable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Check if pull-down activation on DSI pins is enabled + * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) +{ + return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); +} +#endif /* PWR_CR3_DSIPDEN */ + /** * @brief Enable SRAM2 content retention in Standby mode * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention @@ -691,7 +818,7 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) } /** - * @brief Check if SRAM2 content retention in Standby mode is enabled + * @brief Check if SRAM2 content retention in Standby mode is enabled * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention * @retval State of bit (1 or 0). */ @@ -1374,7 +1501,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) /** * @brief Indicate whether the regulator is ready in main mode or is in low-power mode - * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. + * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF * @retval State of bit (1 or 0). */ @@ -1407,14 +1534,14 @@ ErrorStatus LL_PWR_DeInit(void); */ #endif /* USE_FULL_LL_DRIVER */ -/** Legacy definitions for compatibility purpose -@cond 0 -*/ +/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name + * @{ + */ /* Old functions name kept for legacy purpose, to be replaced by the */ /* current functions name. */ #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS /** -@endcond + * @} */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c index 5d750e968c3..d3c5a0f0531 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -60,7 +58,7 @@ /** @addtogroup RCC_LL_Private_Macros * @{ */ -#if defined(RCC_CCIPR_USART3SEL) +#if defined(RCC_CCIPR_USART3SEL) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) @@ -80,19 +78,24 @@ #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) -#if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL) +#if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) +#elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) -#elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL) +#elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) #else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) -#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */ +#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */ #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) @@ -103,8 +106,13 @@ #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) #endif /* RCC_CCIPR_SAI2SEL */ +#if defined(RCC_CCIPR2_SDMMCSEL) +#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE)) +#endif /* RCC_CCIPR2_SDMMCSEL */ + #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) + #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) #if defined(USB_OTG_FS) || defined(USB) @@ -117,10 +125,24 @@ #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE)) #endif /* SWPMI1 */ -#if defined(DFSDM1_Channel0) +#if defined(DFSDM1_Channel0) #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)) +#endif /* RCC_CCIPR2_DFSDM1SEL */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) +#endif /* DSI */ + +#if defined(LTDC) +#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) +#endif /* LTDC */ + +#if defined(OCTOSPI1) +#define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE)) +#endif /* OCTOSPI */ /** * @} @@ -142,7 +164,14 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); #if defined(RCC_PLLSAI2_SUPPORT) uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); +#if defined(LTDC) +uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void); +#else uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void); +#endif /* LTDC */ +#if defined(DSI) +uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void); +#endif /* DSI */ #endif /*RCC_PLLSAI2_SUPPORT*/ /** * @} @@ -162,7 +191,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void); * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source - * - HSE, HSI, PLL and PLLSAIxSource OFF + * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled @@ -183,11 +212,11 @@ ErrorStatus LL_RCC_DeInit(void) /* Insure MSIRDY bit is set before writing default MSIRANGE value */ while (LL_RCC_MSI_IsReady() == 0U) { - __NOP(); } /* Set MSIRANGE default value */ LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); + /* Set MSITRIM bits to the reset value*/ LL_RCC_MSI_SetCalibTrimming(0); @@ -199,7 +228,7 @@ ErrorStatus LL_RCC_DeInit(void) vl_mask = 0xFFFFFFFFU; - /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */ + /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */ CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON)); @@ -214,6 +243,18 @@ ErrorStatus LL_RCC_DeInit(void) /* Write new mask in CR register */ LL_RCC_WriteReg(CR, vl_mask); +#if defined(RCC_PLLSAI2_SUPPORT) + /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + { + } +#else + /* Wait for PLLRDY, PLLSAI1RDY bits to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + { + } +#endif + /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); @@ -231,6 +272,21 @@ ErrorStatus LL_RCC_DeInit(void) /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000U); + /* Clear all interrupt flags */ + vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ + RCC_CICR_PLLSAI1RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC; +#if defined(RCC_HSI48_SUPPORT) + vl_mask |= RCC_CICR_HSI48RDYC; +#endif +#if defined(RCC_PLLSAI2_SUPPORT) + vl_mask |= RCC_CICR_PLLSAI2RDYC; +#endif + + LL_RCC_WriteReg(CICR, vl_mask); + + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + return SUCCESS; } @@ -604,6 +660,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) return i2c_frequency; } + /** * @brief Return LPUARTx clock frequency * @param LPUARTxSource This parameter can be one of the following values: @@ -829,6 +886,45 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) return sai_frequency; } +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Return SDMMCx kernel clock frequency + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE + * @retval SDMMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource) +{ + uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource)); + + /* SDMMC1CLK kernel clock frequency */ + switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */ + sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE); + break; + + case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */ + if (LL_RCC_PLL_IsReady()) + { + sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI(); + } + break; + + default: + sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return sdmmc_frequency; +} +#endif + /** * @brief Return SDMMCx clock frequency * @param SDMMCxSource This parameter can be one of the following values: @@ -847,12 +943,14 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) /* SDMMC1CLK clock frequency */ switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) { +#if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1) case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */ if (LL_RCC_PLLSAI1_IsReady()) { sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */ if (LL_RCC_PLL_IsReady()) @@ -861,6 +959,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) } break; +#if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI) case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */ if (LL_RCC_MSI_IsReady()) { @@ -870,6 +969,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) LL_RCC_MSI_GetRangeAfterStandby())); } break; +#endif #if defined(RCC_HSI48_SUPPORT) case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ @@ -1039,14 +1139,14 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) } break; -#if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2) case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */ if (LL_RCC_PLLSAI2_IsReady()) { adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC(); } break; -#endif /* RCC_PLLSAI2_SUPPORT */ +#endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */ case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ adc_frequency = RCC_GetSystemClockFreq(); @@ -1124,8 +1224,161 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) return dfsdm_frequency; } + +#if defined(RCC_CCIPR2_DFSDM1SEL) +/** + * @brief Return DFSDMx Audio clock frequency + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval DFSDM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) +{ + uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); + + /* DFSDM1CLK clock frequency */ + switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) + { + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */ + dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE); + break; + + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */ + if (LL_RCC_MSI_IsReady()) + { + dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + } + break; + + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */ + default: + if (LL_RCC_HSI_IsReady()) + { + dfsdm_frequency = HSI_VALUE; + } + break; + } + + return dfsdm_frequency; +} +#endif /* RCC_CCIPR2_DFSDM1SEL */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** + * @brief Return DSI clock frequency + * @param DSIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval DSI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) +{ + uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); + + /* DSICLK clock frequency */ + switch (LL_RCC_GetDSIClockSource(DSIxSource)) + { + case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */ + if (LL_RCC_PLLSAI2_IsReady()) + { + dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI(); + } + break; + + case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ + default: + dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return dsi_frequency; +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Return LTDC clock frequency + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval LTDC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready + */ +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) +{ + uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); + + if (LL_RCC_PLLSAI2_IsReady()) + { + ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC(); + } + + return ltdc_frequency; +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Return OCTOSPI clock frequency + * @param OCTOSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval OCTOSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready + */ +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) +{ + uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource)); + + /* OCTOSPI clock frequency */ + switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource)) + { + case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */ + octospi_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */ + if (LL_RCC_MSI_IsReady()) + { + octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + } + break; + + case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */ + if (LL_RCC_PLL_IsReady()) + { + octospi_frequency = RCC_PLL_GetFreqDomain_48M(); + } + break; + + default: + octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + break; + } + + return octospi_frequency; +} +#endif /* OCTOSPI1 */ + /** * @} */ @@ -1333,6 +1586,48 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); } +#if defined(DSI) +/** + * @brief Return PLL clock frequency used for DSI clock + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ + /* DSICLK = PLLSAI2_VCO / PLLSAI2R */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + } + + return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), + LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR()); +} +#endif /* DSI */ /** * @brief Return PLLSAI1 clock frequency used for SAI domain @@ -1342,7 +1637,11 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ +#else /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ +#endif /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1382,7 +1681,11 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ +#else /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ +#endif /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1422,7 +1725,11 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ +#else /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ +#endif /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1463,7 +1770,11 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ +#else /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */ +#endif /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1491,10 +1802,59 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) LL_RCC_MSI_GetRangeAfterStandby())); break; } +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), + LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP()); +#else return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP()); +#endif } +#if defined(LTDC) +/** + * @brief Return PLLSAI2 clock frequency used for LTDC domain + * @retval PLLSAI2 clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ + /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + } + + return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), + LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR()); +} + +#else + /** * @brief Return PLLSAI2 clock frequency used for ADC domain * @retval PLLSAI2 clock frequency (in Hz) @@ -1534,8 +1894,9 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR()); } -#endif /*RCC_PLLSAI2_SUPPORT*/ +#endif /* LTDC */ +#endif /*RCC_PLLSAI2_SUPPORT*/ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h index e0d119a20a6..e1d4b8667b0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -62,7 +60,9 @@ extern "C" { * @{ */ -static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16}; +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ /** * @} @@ -90,6 +90,7 @@ static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; * @} */ #endif /*USE_FULL_LL_DRIVER*/ + /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Exported_Types RCC Exported Types @@ -127,7 +128,7 @@ typedef struct /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to + * @note These values could be modified in the user environment according to * HW set-up. * @{ */ @@ -146,8 +147,8 @@ typedef struct #if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ - #if defined(RCC_HSI48_SUPPORT) + #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ @@ -488,23 +489,49 @@ typedef struct /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection * @{ */ +#if defined(RCC_CCIPR2_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ +#else #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */ - -#if defined(RCC_CCIPR_SAI2SEL) +#endif /* RCC_CCIPR2_SAI1SEL */ + +#if defined(RCC_CCIPR2_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ +#elif defined(RCC_CCIPR_SAI2SEL) #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */ -#endif /* RCC_CCIPR_SAI2SEL *//** +#endif /* RCC_CCIPR2_SAI2SEL */ +/** + * @} + */ + +#if defined(RCC_CCIPR2_SDMMCSEL) +/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */ +/** * @} */ +#endif /* RCC_CCIPR2_SDMMCSEL */ /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection * @{ @@ -559,7 +586,7 @@ typedef struct */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ -#if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ @@ -579,16 +606,69 @@ typedef struct #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection * @{ */ +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ +#else #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ +#endif /* RCC_CCIPR2_DFSDM1SEL */ /** * @} */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source * @{ */ @@ -651,14 +731,30 @@ typedef struct /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source * @{ */ +#if defined(RCC_CCIPR2_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ +#else #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */ -#if defined(RCC_CCIPR_SAI2SEL) +#endif /* RCC_CCIPR2_SAI1SEL */ +#if defined(RCC_CCIPR2_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ +#elif defined(RCC_CCIPR_SAI2SEL) #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */ -#endif /* RCC_CCIPR_SAI2SEL */ +#endif /* RCC_CCIPR2_SAI2SEL */ /** * @} */ +#if defined(RCC_CCIPR2_SDMMCSEL) +/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source + * @{ + */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR2_SDMMCSEL */ + /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source * @{ */ @@ -704,15 +800,60 @@ typedef struct #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CCIPR2_ADFSDM1SEL */ /** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source * @{ */ +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */ +#else #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */ +#endif /* RCC_CCIPR2_DFSDM1SEL */ /** * @} */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + + /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ @@ -724,6 +865,7 @@ typedef struct * @} */ + /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source * @{ */ @@ -735,17 +877,27 @@ typedef struct * @} */ -/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor +/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor * @{ */ -#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */ -#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */ -#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */ -#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */ -#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */ -#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */ -#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */ -#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */ +#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */ +#if defined(RCC_PLLM_DIV_1_16_SUPPORT) +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */ +#endif /* RCC_PLLM_DIV_1_16_SUPPORT */ /** * @} */ @@ -766,35 +918,35 @@ typedef struct */ #if defined(RCC_PLLP_DIV_2_31_SUPPORT) #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */ -#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */ #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */ -#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 5 */ -#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 6 */ -#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */ #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */ -#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 9 */ -#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 10 */ -#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */ -#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 12 */ -#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 13 */ -#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 14 */ -#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */ #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */ -#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 17 */ -#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 18 */ -#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */ -#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 20 */ -#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 21 */ -#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 22 */ -#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */ -#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 24 */ -#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 25 */ -#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 26 */ -#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */ -#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 28 */ -#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */ -#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */ -#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */ #else #define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */ #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */ @@ -814,6 +966,31 @@ typedef struct * @} */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M) + * @{ + */ +#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */ +#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */ +#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */ +#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */ +#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */ +#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */ +#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */ +#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */ +#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */ +#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */ +#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */ +#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */ +#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */ +#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */ +#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */ +#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */ +/** + * @} + */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) * @{ */ @@ -830,35 +1007,35 @@ typedef struct */ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */ -#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ +#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */ -#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ -#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ -#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ +#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ +#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ +#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */ -#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ -#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ -#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ -#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ -#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ -#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ -#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ +#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ +#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ +#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ +#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ +#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ +#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ +#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */ -#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ -#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ -#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ -#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ -#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ -#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ -#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ -#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ -#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ -#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ -#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ -#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ -#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ -#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ -#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ +#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ +#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ +#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ +#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ +#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ +#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ +#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ +#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ +#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ +#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ +#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ +#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ +#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ +#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ +#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ #else #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ @@ -879,11 +1056,82 @@ typedef struct */ #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M) + * @{ + */ +#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */ +#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */ +#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */ +#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */ +#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */ +#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */ +#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */ +#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */ +#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */ +#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */ +#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */ +#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */ +#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */ +#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */ +#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */ +#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */ +/** + * @} + */ +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q) + * @{ + */ +#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */ +#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */ +#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */ +#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P) * @{ */ +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */ +#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */ +#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */ +#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */ +#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */ +#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ +#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */ +#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */ +#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */ +#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */ +#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */ +#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */ +#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */ +#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */ +#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */ +#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ +#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */ +#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */ +#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */ +#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */ +#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */ +#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */ +#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */ +#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */ +#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */ +#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */ +#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */ +#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */ +#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */ +#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ +#else #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ /** * @} */ @@ -898,6 +1146,19 @@ typedef struct /** * @} */ + +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR) + * @{ + */ +#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */ +#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */ +#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */ +#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ #endif /* RCC_PLLSAI2_SUPPORT */ /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection @@ -974,6 +1235,16 @@ typedef struct * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param __PLLN__ Between 8 and 86 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 @@ -1000,6 +1271,16 @@ typedef struct * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param __PLLN__ Between 8 and 86 * @param __PLLP__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 @@ -1035,7 +1316,7 @@ typedef struct * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ - ((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos)) + ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) #else /** @@ -1062,6 +1343,7 @@ typedef struct (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ + /** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1076,6 +1358,16 @@ typedef struct * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param __PLLN__ Between 8 and 86 * @param __PLLQ__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 @@ -1087,7 +1379,68 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + +#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1138,7 +1491,8 @@ typedef struct */ #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ - ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos)) + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + #else /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain @@ -1163,8 +1517,45 @@ typedef struct #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U)) + #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) + +#else /** * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1191,6 +1582,44 @@ typedef struct ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) + +#else /** * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1217,6 +1646,123 @@ typedef struct ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +#else /** * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1240,6 +1786,49 @@ typedef struct #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \ (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U)) + +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @param __PLLSAI2DIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ + (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos]))) +#else /** * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1266,6 +1855,45 @@ typedef struct ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U)) +#endif /* LTDC */ + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \ + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U)) +#endif /* DSI */ + + /** * @brief Helper macro to calculate the HCLK frequency @@ -1295,7 +1923,7 @@ typedef struct * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) /** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) @@ -1308,7 +1936,7 @@ typedef struct * @arg @ref LL_RCC_APB2_DIV_16 * @retval PCLK2 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) /** * @brief Helper macro to calculate the MSI frequency (in Hz) @@ -1452,6 +2080,16 @@ __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); } +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)); +} + /** * @brief Enable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Enable @@ -1579,7 +2217,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) /** * @brief Get HSI48 Calibration value * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF */ __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) { @@ -2284,7 +2922,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) */ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U))); } @@ -2309,7 +2947,11 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) /** * @brief Configure SAIx clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource + @else * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource + @endif * @param SAIxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) @@ -2325,8 +2967,29 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) */ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) { +#if defined(RCC_CCIPR2_SAI1SEL) + MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); +#else MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +#endif /* RCC_CCIPR2_SAI1SEL */ +} + +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Configure SDMMC1 kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); } +#endif /* RCC_CCIPR2_SDMMCSEL */ /** * @brief Configure SDMMC1 clock source @@ -2336,7 +2999,7 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) * * (*) value not defined in all devices. * @retval None @@ -2417,9 +3080,29 @@ __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source); +} +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + /** * @brief Configure DFSDM Kernel clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource + @else * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource + @endif * @param DFSDMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK @@ -2427,13 +3110,65 @@ __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) */ __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource) { +#if defined(RCC_CCIPR2_DFSDM1SEL) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource); +#else MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource); +#endif /* RCC_CCIPR2_DFSDM1SEL */ } #endif /* DFSDM1_Channel0 */ +#if defined(DSI) /** - * @brief Get USARTx clock source - * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource + * @brief Configure DSI clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure LTDC Clock Source + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source); +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Configure OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source); +} +#endif /* OCTOSPI1 */ + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource * @param USARTx This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE * @arg @ref LL_RCC_USART2_CLKSOURCE @@ -2528,8 +3263,8 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); - return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x0000FF0000U) >> 16U)) >> ((I2Cx & 0x0000FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); } /** @@ -2555,7 +3290,11 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) /** * @brief Get SAIx clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource + @else * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource + @endif * @param SAIx This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) @@ -2575,8 +3314,30 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) */ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) { +#if defined(RCC_CCIPR2_SAI1SEL) + return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); +#else return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); +#endif /* RCC_CCIPR2_SAI1SEL */ +} + +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Get SDMMCx kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); } +#endif /* RCC_CCIPR2_SDMMCSEL */ /** * @brief Get SDMMCx clock source @@ -2586,9 +3347,9 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) * * (*) value not defined in all devices. */ @@ -2672,9 +3433,30 @@ __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); +} +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + /** * @brief Get DFSDMx Kernel clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource + @else * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource + @endif * @param DFSDMx This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE * @retval Returned value can be one of the following values: @@ -2683,10 +3465,64 @@ __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) */ __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) { +#if defined(RCC_CCIPR2_DFSDM1SEL) + return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); +#else return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx)); +#endif /* RCC_CCIPR2_DFSDM1SEL */ } #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Get LTDC Clock Source + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource + * @param LTDCx This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Get OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource + * @param OCTOSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); +} +#endif /* OCTOSPI1 */ /** * @} */ @@ -2820,8 +3656,8 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) /** * @brief Configure PLL used for SYSCLK Domain * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLR can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLR can be written only when PLL is disabled. * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n @@ -2840,6 +3676,16 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param PLLN Between 8 and 86 * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 @@ -2858,8 +3704,8 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, /** * @brief Configure PLL used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLP can be written only when PLL is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n @@ -2879,6 +3725,16 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param PLLN Between 8 and 86 * @param PLLP This parameter can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 @@ -2917,8 +3773,8 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, /** * @brief Configure PLL used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLP can be written only when PLL is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n @@ -2959,8 +3815,8 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, /** * @brief Configure PLL used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLQ can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLQ can be written only when PLL is disabled. * @note This can be selected for USB, RNG, SDMMC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n @@ -2980,6 +3836,16 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param PLLN Between 8 and 86 * @param PLLQ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 @@ -2994,6 +3860,35 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); } +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN @@ -3007,7 +3902,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Get Main PLL division factor for PLLP - * @note used for PLLSAI3CLK (SAI1 and SAI2 clock) + * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 @@ -3048,7 +3943,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) #else /** * @brief Get Main PLL division factor for PLLP - * @note used for PLLSAI3CLK (SAI1 and SAI2 clock) + * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_7 @@ -3062,7 +3957,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) /** * @brief Get Main PLL division factor for PLLQ - * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) + * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 @@ -3077,7 +3972,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) /** * @brief Get Main PLL division factor for PLLR - * @note used for PLLCLK (system clock) + * @note Used for PLLCLK (system clock) * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 @@ -3090,20 +3985,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); } -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_NONE - * @arg @ref LL_RCC_PLLSOURCE_MSI - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider @@ -3116,6 +3997,16 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { @@ -3232,11 +4123,58 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)); } +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Configure PLLSAI1 used for 48Mhz domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. + * @note This can be selected for USB, RNG, SDMMC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, + PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); +} +#else /** * @brief Configure PLLSAI1 used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. * @note This can be selected for USB, RNG, SDMMC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n @@ -3269,13 +4207,86 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); } +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI1 used for SAI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); +} +#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Configure PLLSAI1 used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n @@ -3329,12 +4340,18 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P * @arg @ref LL_RCC_PLLSAI1P_DIV_31 * @retval None */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); +} #else /** * @brief Configure PLLSAI1 used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n @@ -3360,23 +4377,65 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P * @arg @ref LL_RCC_PLLSAI1P_DIV_17 * @retval None */ -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); -#else MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ } +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Configure PLLSAI1 used for ADC domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled. + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, + PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); +} +#else /** * @brief Configure PLLSAI1 used for ADC domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLR can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLR can be written only when PLLSAI1 is disabled. * @note This can be selected for ADC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n @@ -3409,6 +4468,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); } +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ /** * @brief Get SAI1PLL multiplication factor for VCO @@ -3423,7 +4483,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Get SAI1PLL division factor for PLLSAI1P - * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). + * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1P_DIV_2 @@ -3457,28 +4517,28 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) * @arg @ref LL_RCC_PLLSAI1P_DIV_30 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); +} #else /** * @brief Get SAI1PLL division factor for PLLSAI1P - * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). + * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1P_DIV_7 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 */ -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) { -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); -#else return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ } +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ /** * @brief Get SAI1PLL division factor for PLLSAI1Q - * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) + * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 @@ -3493,7 +4553,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void) /** * @brief Get PLLSAI1 division factor for PLLSAIR - * @note used for PLLADC1CLK (ADC clock) + * @note Used for PLLADC1CLK (ADC clock) * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1R_DIV_2 @@ -3506,6 +4566,34 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R)); } +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Get Division factor for the PLLSAI1 + * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M)); +} +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /** * @brief Enable PLLSAI1 output mapped on SAI domain clock * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI @@ -3611,11 +4699,148 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)); } +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, + PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); +} +#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); +} +#else /** * @brief Configure PLLSAI2 used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI2 and PLLSAI2 are disabled - * @note PLLN/PLLP can be written only when PLLSAI2 is disabled + * PLLSAI2 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled. * @note This can be selected for SAI1 or SAI2 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n @@ -3646,12 +4871,113 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); } +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */ +#if defined(DSI) +/** + * @brief Configure PLLSAI2 used for DSI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled. + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure PLLSAI2 used for LTDC domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM); + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); +} +#else /** * @brief Configure PLLSAI2 used for ADC domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI2 and PLLSAI2 are disabled - * @note PLLN/PLLR can be written only when PLLSAI2 is disabled + * PLLSAI2 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. * @note This can be selected for ADC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n @@ -3684,6 +5010,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR); } +#endif /* LTDC */ /** * @brief Get SAI2PLL multiplication factor for VCO @@ -3695,9 +5022,51 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void) return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos); } +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Get SAI2PLL division factor for PLLSAI2P + * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). + * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV)); +} +#else /** * @brief Get SAI2PLL division factor for PLLSAI2P - * @note used for PLLSAI2CLK (SAI1 or SAI2 clock). + * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI2P_DIV_7 @@ -3707,10 +5076,28 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) { return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P)); } +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +/** + * @brief Get division factor for PLLSAI2Q + * @note Used for PLLDSICLK (DSI clock) + * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q)); +} +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ /** * @brief Get SAI2PLL division factor for PLLSAI2R - * @note used for PLLADC2CLK (ADC clock) + * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI2R_DIV_2 @@ -3723,6 +5110,51 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)); } +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +/** + * @brief Get Division factor for the PLLSAI2 + * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M)); +} +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +/** + * @brief Get PLLSAI2 division factor for PLLSAI2DIVR + * @note Used for LTDC domain clock + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)); +} +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ + /** * @brief Enable PLLSAI2 output mapped on SAI domain clock * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI @@ -3745,6 +5177,53 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void) CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); } +#if defined(DSI) +/** + * @brief Enable PLLSAI2 output mapped on DSI domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); +} + +/** + * @brief Disable PLLSAI2 output mapped on DSI domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Enable PLLSAI2 output mapped on LTDC domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} + +/** + * @brief Disable PLLSAI2 output mapped on LTDC domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} +#else /** * @brief Enable PLLSAI2 output mapped on ADC domain clock * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC @@ -3766,12 +5245,15 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void) { CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); } +#endif /* LTDC */ /** * @} */ #endif /* RCC_PLLSAI2_SUPPORT */ + + /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management * @{ */ @@ -4439,6 +5921,9 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#if defined(RCC_CCIPR2_SDMMCSEL) +uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); +#endif uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); #if defined(USB_OTG_FS) || defined(USB) @@ -4450,7 +5935,19 @@ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource); #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +#if defined(RCC_CCIPR2_DFSDM1SEL) +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* RCC_CCIPR2_DFSDM1SEL */ #endif /* DFSDM1_Channel0 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +#if defined(OCTOSPI1) +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); +#endif /* OCTOSPI1 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c index e1c3b4acee6..5ded9ba331f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RNG LL module driver. ****************************************************************************** * @attention @@ -60,6 +58,18 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @addtogroup RNG_LL_Private_Macros + * @{ + */ +#if defined(RNG_CR_CED) +#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ + ((__MODE__) == LL_RNG_CED_DISABLE)) +#endif /* defined(RNG_CR_CED) */ + +/** + * @} + */ + /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -92,6 +102,42 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) return (SUCCESS); } +#if defined(RNG_CR_CED) +/** + * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct. + * @param RNGx RNG Instance + * @param RNG_InitStruct: pointer to a LL_RNG_InitTypeDef structure + * that contains the configuration information for the specified RNG peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection)); + + /* Clock Error Detection configuration */ + MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_RNG_InitTypeDef field to default value. + * @param RNG_InitStruct: pointer to a @ref LL_RNG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Set RNG_InitStruct fields to default values */ + RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE; + +} +#endif /* defined(RNG_CR_CED) */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h index 94325a4ac48..2c49eac9a16 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RNG LL module. ****************************************************************************** * @attention @@ -62,11 +60,47 @@ extern "C" { /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures + * @{ + */ + + +#if defined(RNG_CR_CED) +/** + * @brief LL RNG Init Structure Definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection. + This parameter can be one value of @ref RNG_LL_CED. + + This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */ +}LL_RNG_InitTypeDef; +#endif /* defined(RNG_CR_CED) */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants * @{ */ + +#if defined(RNG_CR_CED) +/** @defgroup RNG_LL_CED Clock Error Detection + * @{ + */ +#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ +#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +#endif /* defined(RNG_CR_CED) */ + /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_RNG_ReadReg function * @{ @@ -168,6 +202,42 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)); } +#if defined(RNG_CR_CED) +/** + * @brief Enable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_EnableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_CED); +} + +/** + * @brief Disable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_DisableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CED); +} + +/** + * @brief Check if RNG Clock Error Detection is enabled + * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +{ + return (!(READ_BIT(RNGx->CR, RNG_CR_CED) == (RNG_CR_CED))); +} +#endif /* defined(RNG_CR_CED) */ + + /** * @} */ @@ -324,7 +394,10 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ - +#if defined(RNG_CR_CED) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); +#endif /* defined(RNG_CR_CED) */ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c index 6c359de2701..1fff8e3f768 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RTC LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h index a935f5ab0e2..41ace5a83ec 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -63,8 +61,8 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) @@ -223,8 +221,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ /** * @} */ @@ -614,8 +612,8 @@ typedef struct * @{ */ #define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ /** * @} */ @@ -1293,7 +1291,12 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); } /** @@ -1627,7 +1630,13 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c index d0434cdcc13..c245cca9cbb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -234,7 +232,9 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); @@ -242,12 +242,20 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) /* Set SDMMC configuration parameters */ /* Write to SDMMC CLKCR */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv); +#else MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ Init.ClockBypass |\ Init.ClockPowerSave |\ Init.BusWide |\ Init.HardwareFlowControl |\ Init.ClockDiv); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } @@ -324,11 +332,32 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) { /* Set power state to ON */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; + +#else SDMMCx->POWER = SDMMC_POWER_PWRCTRL; + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Set SDMMC Power state to Power-Cycle. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to Power Cycle*/ + SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1; + + return HAL_OK; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @brief Set SDMMC Power state to OFF. * @param SDMMCx: Pointer to SDMMC register base @@ -337,7 +366,13 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) { /* Set power state to OFF */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL); + +#else SDMMCx->POWER = (uint32_t)0x00000000; + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } @@ -894,7 +929,11 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate = SDMMC_ERROR_NONE; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + sdmmc_cmdinit.Argument = Argument; +#else sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1125,6 +1164,32 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) return errorstate; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param None + * @retval HAL status + */ +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = 0x00000000; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT); + + return errorstate; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} @@ -1156,7 +1221,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); return SDMMC_ERROR_NONE; } @@ -1207,7 +1272,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1330,7 +1395,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { /* No error flag set */ /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1363,10 +1428,9 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else - { /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1417,7 +1481,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1465,11 +1529,19 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { /* Card is SD V2.0 compliant */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h index 8b1b0183c69..41996af8e05 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of low layer SDMMC HAL module. ****************************************************************************** * @attention @@ -69,9 +67,11 @@ typedef struct uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or disabled when the bus is idle. @@ -86,6 +86,11 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Transceiver */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + }SDMMC_InitTypeDef; @@ -200,7 +205,11 @@ typedef struct and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ +#else #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ +#endif #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ @@ -307,6 +316,11 @@ typedef struct #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) +#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) +#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) @@ -334,8 +348,8 @@ typedef struct */ #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) -#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ -#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ +#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ /** @defgroup SDMMC_LL_Clock_Edge Clock Edge @@ -350,6 +364,7 @@ typedef struct * @} */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass * @{ */ @@ -361,6 +376,7 @@ typedef struct /** * @} */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving * @{ @@ -403,12 +419,31 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Division Clock Division * @{ */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ +#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400) +#else #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SDMMC_LL_Transceiver Transceiver + * @{ + */ +#define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U) + +#define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \ + ((MODE) == SDMMC_TRANSCEIVER_ENABLE)) +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SDMMC_LL_Command_Index Command Index * @{ */ @@ -470,6 +505,19 @@ typedef struct ((RESP) == SDMMC_RESP3) || \ ((RESP) == SDMMC_RESP4)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode + * @{ + */ +#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) +#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) +#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) +#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) + +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -536,7 +584,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 +#else #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) @@ -571,28 +623,39 @@ typedef struct /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources * @{ */ -#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL -#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL -#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT -#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT -#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR -#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR -#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND -#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT -#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND -#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND -#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE -#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF -#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF -#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF -#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE -#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE -#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT -#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT -#define SDMMC_IT_TXACT SDMMC_STA_TXACT -#define SDMMC_IT_RXACT SDMMC_STA_RXACT -#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL -#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE +#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE +#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE +#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE +#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE +#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE +#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE +#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE +#else +#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE +#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE +#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE +#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE +#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE +#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE +#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -617,16 +680,56 @@ typedef struct #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD +#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT +#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT +#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT +#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 +#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END +#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL +#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT +#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND +#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP +#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE +#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC +#else #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL - +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ + SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ + SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ + SDMMC_FLAG_IDMABTC)) + +#else #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND)) + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -648,9 +751,15 @@ typedef struct /* ---------------------- SDMMC registers bit mask --------------------------- */ /* --- CLKCR Register ---*/ /* CLKCR register clear mask */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ + SDMMC_CLKCR_WIDBUS |\ + SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) +#else #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* --- DCTRL Register ---*/ /* SDMMC DCTRL Clear Mask */ @@ -659,15 +768,29 @@ typedef struct /* --- CMD Register ---*/ /* CMD Register clear mask */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ + SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ + SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) +#else #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* SDMMC Initialization Frequency (400KHz max) */ +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */ +/* SDMMC Data Transfer Frequency (25MHz max) */ +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */ +#else /* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ /* SDMMC Data Transfer Frequency (25MHz max) */ -#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -678,6 +801,7 @@ typedef struct * @{ */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief Enable the SDMMC device. * @param __INSTANCE__: SDMMC Instance @@ -704,6 +828,7 @@ typedef struct * @retval None */ #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Enable the SDMMC device interrupt. @@ -966,15 +1091,23 @@ typedef struct * @param __INSTANCE__: Pointer to SDMMC register base * @retval None */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) +#else +#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Disable the SD I/O Suspend command sending. * @param __INSTANCE__: Pointer to SDMMC register base * @retval None */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) - +#else +#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + /** * @brief Enable the CMDTRANS mode. * @param __INSTANCE__ : Pointer to SDMMC register base @@ -1025,6 +1158,9 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); * @{ */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); @@ -1067,6 +1203,9 @@ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c index 4d3e2602336..99e28de2353 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SPI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h index 16fc9cdc47d..b88bcd537ce 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SPI LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c index 949bc6d327c..083b96f1412 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_swpmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SWPMI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h index a2452f46a06..4193ed5c220 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_swpmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SWPMI LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h index 409db3d0b52..e1ed4940052 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_system.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -77,15 +75,12 @@ extern "C" { * @{ */ -/* Defines used for position in the register */ -#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID) - /** * @brief Power-down in Run mode Flash key */ -#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ -#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 - to unlock the RUN_PD bit in FLASH_ACR */ +#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ +#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ /** * @} @@ -377,6 +372,19 @@ extern "C" { #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#if defined(FLASH_ACR_LATENCY_5WS) +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +#endif /** * @} */ @@ -1049,7 +1057,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** @@ -1390,6 +1398,19 @@ __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) * @arg @ref LL_FLASH_LATENCY_2 * @arg @ref LL_FLASH_LATENCY_3 * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 (*) + * @arg @ref LL_FLASH_LATENCY_6 (*) + * @arg @ref LL_FLASH_LATENCY_7 (*) + * @arg @ref LL_FLASH_LATENCY_8 (*) + * @arg @ref LL_FLASH_LATENCY_9 (*) + * @arg @ref LL_FLASH_LATENCY_10 (*) + * @arg @ref LL_FLASH_LATENCY_11 (*) + * @arg @ref LL_FLASH_LATENCY_12 (*) + * @arg @ref LL_FLASH_LATENCY_13 (*) + * @arg @ref LL_FLASH_LATENCY_14 (*) + * @arg @ref LL_FLASH_LATENCY_15 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) @@ -1406,6 +1427,19 @@ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) * @arg @ref LL_FLASH_LATENCY_2 * @arg @ref LL_FLASH_LATENCY_3 * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 (*) + * @arg @ref LL_FLASH_LATENCY_6 (*) + * @arg @ref LL_FLASH_LATENCY_7 (*) + * @arg @ref LL_FLASH_LATENCY_8 (*) + * @arg @ref LL_FLASH_LATENCY_9 (*) + * @arg @ref LL_FLASH_LATENCY_10 (*) + * @arg @ref LL_FLASH_LATENCY_11 (*) + * @arg @ref LL_FLASH_LATENCY_12 (*) + * @arg @ref LL_FLASH_LATENCY_13 (*) + * @arg @ref LL_FLASH_LATENCY_14 (*) + * @arg @ref LL_FLASH_LATENCY_15 (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c index ca7cfed782a..4ae0d28f2a6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief TIM LL module driver. ****************************************************************************** * @attention @@ -172,24 +170,24 @@ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) @@ -323,11 +321,11 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) { /* Set the default configuration */ - TIM_InitStruct->Prescaler = (uint16_t)0x0000U; + TIM_InitStruct->Prescaler = (uint16_t)0x0000; TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; + TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; } /** @@ -703,7 +701,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; - TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; @@ -716,7 +714,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) /** * @brief Configure the Break and Dead Time feature of the timer instance. * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR - * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -732,7 +730,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; - + /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); @@ -741,10 +739,10 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); - + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - + /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); @@ -765,16 +763,16 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); - + /* Set the BREAK2 input related BDTR bit-fields */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); } - + /* Set TIMx_BDTR */ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); - + return SUCCESS; } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h index 0556e17596d..ab0dd4e6d67 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM LL module. ****************************************************************************** * @attention @@ -159,7 +157,7 @@ static const uint8_t SHIFT_TAB_OISx[] = #endif /* DFSDM1_Channel0 */ #define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /*!< BRK2 BKIN2 input polarity */ #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ +#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ /* Remap mask definitions */ #define TIMx_OR1_RMP_SHIFT 16U @@ -171,22 +169,26 @@ static const uint8_t SHIFT_TAB_OISx[] = #endif /* ADC3 */ #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT) #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#if defined(ADC2) && defined(ADC3) #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) +#else +#define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#endif /* ADC2 & ADC3 */ #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ -#define DT_DELAY_1 ((uint8_t)0x7FU) -#define DT_DELAY_2 ((uint8_t)0x3FU) -#define DT_DELAY_3 ((uint8_t)0x1FU) -#define DT_DELAY_4 ((uint8_t)0x1FU) +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ -#define DT_RANGE_1 ((uint8_t)0x00U) -#define DT_RANGE_2 ((uint8_t)0x80U) -#define DT_RANGE_3 ((uint8_t)0xC0U) -#define DT_RANGE_4 ((uint8_t)0xE0U) +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) /** Legacy definitions for compatibility purpose @cond 0 @@ -450,8 +452,8 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; -/** - * @brief BDTR (Break and Dead Time) structure definition +/** + * @brief BDTR (Break and Dead Time) structure definition */ typedef struct { @@ -459,31 +461,31 @@ typedef struct This parameter can be a value of @ref TIM_LL_EC_OSSR This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() - + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ - uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() @@ -494,17 +496,17 @@ typedef struct This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() @@ -515,21 +517,21 @@ typedef struct This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ } LL_TIM_BDTR_InitTypeDef; @@ -593,7 +595,7 @@ typedef struct #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ /** * @} - */ + */ #endif /* USE_FULL_LL_DRIVER */ /** @defgroup TIM_LL_EC_IT IT Defines @@ -825,7 +827,7 @@ typedef struct * @{ */ #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ -#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ +#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ /** * @} @@ -834,9 +836,9 @@ typedef struct /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode * @{ */ -#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ -#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ +#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ +#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ /** * @} */ @@ -894,14 +896,14 @@ typedef struct /** @defgroup TIM_LL_EC_TS Trigger Selection * @{ */ -#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ -#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ -#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ -#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ -#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ -#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ -#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ -#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ +#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ +#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ +#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ +#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ +#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ +#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ +#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ +#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ /** * @} */ @@ -1162,11 +1164,12 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap * @{ */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ @@ -1335,6 +1338,7 @@ typedef struct /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros * @{ */ + /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); @@ -1359,9 +1363,9 @@ typedef struct */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ + (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1482,7 +1486,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) { - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** @@ -1493,18 +1497,18 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance - * @retval State of bit (1 or 0). + * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); } /** @@ -1573,6 +1577,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode * @param TIMx Timer instance @@ -2515,7 +2522,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -3644,11 +3651,11 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n - * OR2 BKDFBK0E LL_TIM_EnableBreakInputSource\n - * OR3 BKINE LL_TIM_EnableBreakInputSource\n - * OR3 BKCMP1E LL_TIM_EnableBreakInputSource\n - * OR3 BKCMP2E LL_TIM_EnableBreakInputSource\n - * OR3 BKDFBK0E LL_TIM_EnableBreakInputSource + * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n + * OR3 BK2INE LL_TIM_EnableBreakInputSource\n + * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n + * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -3673,11 +3680,11 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n - * OR2 BKDFBK0E LL_TIM_DisableBreakInputSource\n - * OR3 BKINE LL_TIM_DisableBreakInputSource\n - * OR3 BKCMP1E LL_TIM_DisableBreakInputSource\n - * OR3 BKCMP2E LL_TIM_DisableBreakInputSource\n - * OR3 BKDFBK0E LL_TIM_DisableBreakInputSource + * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n + * OR3 BK2INE LL_TIM_DisableBreakInputSource\n + * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -3699,14 +3706,12 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * @brief Set the polarity of the break signal for the timer break input. * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. - * @rmtoll OR2 BKINE LL_TIM_SetBreakInputSourcePolarity\n - * OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n - * OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n - * OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKINE LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKINP LL_TIM_SetBreakInputSourcePolarity + * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c index 211b7cd9430..a49c43007c2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief USART LL module driver. ****************************************************************************** * @attention @@ -73,9 +71,28 @@ * @{ */ +#if defined(USART_PRESC_PRESCALER) +#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + +#endif /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U) +#else #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) +#endif /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \ @@ -222,6 +239,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check the parameters */ assert_param(IS_UART_INSTANCE(USARTx)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue)); +#endif assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); @@ -295,6 +315,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini } /* Configure the USART Baud Rate : +#if defined(USART_PRESC_PRESCALER) + - prescaler value is required +#endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -304,12 +327,23 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini status = SUCCESS; LL_USART_SetBaudRate(USARTx, periphclk, +#if defined(USART_PRESC_PRESCALER) + USART_InitStruct->PrescalerValue, +#endif USART_InitStruct->OverSampling, USART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR(USARTx->BRR)); } + +#if defined(USART_PRESC_PRESCALER) + /*---------------------------- USART PRESC Configuration ----------------------- + * Configure USARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value. + */ + LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue); +#endif } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -326,6 +360,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) { /* Set USART_InitStruct fields to default values */ +#if defined(USART_PRESC_PRESCALER) + USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; +#endif USART_InitStruct->BaudRate = 9600U; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h index 9fc806da081..da5cd195ff1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USART LL module. ****************************************************************************** * @attention @@ -58,6 +56,30 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint16_t USART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ +#endif /* Private constants ---------------------------------------------------------*/ /** @defgroup USART_LL_Private_Constants USART Private Constants @@ -88,6 +110,13 @@ extern "C" { */ typedef struct { +#if defined(USART_PRESC_PRESCALER) + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ + +#endif uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ @@ -176,6 +205,9 @@ typedef struct #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ +#endif #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ @@ -184,6 +216,9 @@ typedef struct #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ +#if defined(USART_CR2_SLVEN) +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ +#endif #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ /** @@ -199,14 +234,25 @@ typedef struct #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#else #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#endif #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#else #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#endif #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#if defined(USART_CR2_SLVEN) +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#endif #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ @@ -216,9 +262,17 @@ typedef struct #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#endif #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ #endif +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#endif /** * @} */ @@ -228,23 +282,56 @@ typedef struct * @{ */ #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#else #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#endif #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#else #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#endif #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#endif #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#endif #if defined(USART_TCBGT_SUPPORT) #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ #endif +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#endif +/** + * @} + */ + +#if defined(USART_CR1_FIFOEN) +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ /** * @} */ +#endif /** @defgroup USART_LL_EC_DIRECTION Communication Direction * @{ @@ -334,6 +421,27 @@ typedef struct * @} */ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +/** + * @} + */ +#endif + /** @defgroup USART_LL_EC_STOPBITS Stop Bits * @{ */ @@ -508,19 +616,59 @@ typedef struct * @brief Compute USARTDIV value according to Peripheral Clock and * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + @if USART_PRESC_PRESCALER + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __PRESCALER__ Prescaler value + @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ +#if defined(USART_PRESC_PRESCALER) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#else #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#endif /** * @brief Compute USARTDIV value according to Peripheral Clock and * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + @if USART_PRESC_PRESCALER + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __PRESCALER__ Prescaler value + @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ +#if defined(USART_PRESC_PRESCALER) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#else #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#endif /** * @} @@ -576,6 +724,154 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief FIFO Mode Enable + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); +} +#endif + /** * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that @@ -970,6 +1266,60 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); } +#if defined(USART_PRESC_PRESCALER) + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} +#endif + /** * @brief Enable Clock output on SCLK pin * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not @@ -1577,28 +1927,56 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * @rmtoll BRR BRR LL_USART_SetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + @endif * @param OverSampling This parameter can be one of the following values: * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 * @param BaudRate Baud Rate * @retval None */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, + uint32_t BaudRate) +#else __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate) +#endif { register uint32_t usartdiv = 0x0U; register uint32_t brrtemp = 0x0U; if (OverSampling == LL_USART_OVERSAMPLING_8) { +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, PrescalerValue, BaudRate)); +#else usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); +#endif brrtemp = usartdiv & 0xFFF0U; brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); USARTx->BRR = brrtemp; } else { +#if defined(USART_PRESC_PRESCALER) + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, PrescalerValue, BaudRate)); +#else USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +#endif } } @@ -1610,15 +1988,37 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @rmtoll BRR BRR LL_USART_GetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + @endif * @param OverSampling This parameter can be one of the following values: * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) +#else __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +#endif { register uint32_t usartdiv = 0x0U; register uint32_t brrresult = 0x0U; +#if defined(USART_PRESC_PRESCALER) + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[PrescalerValue])); +#endif usartdiv = USARTx->BRR; @@ -1627,14 +2027,22 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe if ((usartdiv & 0xFFF7U) != 0U) { usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; +#if defined(USART_PRESC_PRESCALER) + brrresult = (periphclkpresc * 2U) / usartdiv; +#else brrresult = (PeriphClk * 2U) / usartdiv; +#endif } } else { if ((usartdiv & 0xFFFFU) != 0U) { +#if defined(USART_PRESC_PRESCALER) + brrresult = periphclkpresc / usartdiv; +#else brrresult = PeriphClk / usartdiv; +#endif } } return (brrresult); @@ -2020,6 +2428,97 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) * @} */ +#if defined(USART_CR2_SLVEN) + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef* USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)); +} + +/** + * @} + */ +#endif + /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature * @{ */ @@ -2566,6 +3065,25 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); +} +#else + /** * @brief Check if the USART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE @@ -2576,6 +3094,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); } +#endif /** * @brief Check if the USART Transmission Complete Flag is set or not @@ -2588,6 +3107,25 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); +} +#else + /** * @brief Check if the USART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE @@ -2598,6 +3136,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); } +#endif /** * @brief Check if the USART LIN Break Detection Flag is set or not @@ -2662,6 +3201,22 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); } +#if defined(USART_CR2_SLVEN) + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)); +} +#endif + /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not @@ -2767,7 +3322,37 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); +} +#endif + #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not @@ -2781,6 +3366,35 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); +} +#endif + /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_USART_ClearFlag_PE @@ -2836,6 +3450,22 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} +#endif + /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_USART_ClearFlag_TC @@ -2848,6 +3478,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) } #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag @@ -2911,6 +3542,22 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); } +#if defined(USART_CR2_SLVEN) + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} +#endif + /** * @brief Clear Character Match Flag * @rmtoll ICR CMCF LL_USART_ClearFlag_CM @@ -2954,6 +3601,25 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Enable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE @@ -2964,6 +3630,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Enable Transmission Complete Interrupt @@ -2976,6 +3643,25 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) SET_BIT(USARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Enable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE @@ -2986,6 +3672,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Enable Parity Error Interrupt @@ -3033,6 +3720,33 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) SET_BIT(USARTx->CR1, USART_CR1_EOBIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Enable LIN Break Detection Interrupt * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3087,7 +3801,24 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) SET_BIT(USARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} +#endif + #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt @@ -3103,6 +3834,22 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Disable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE @@ -3114,6 +3861,25 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Disable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE @@ -3124,6 +3890,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Disable Transmission Complete Interrupt @@ -3136,6 +3903,25 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Disable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE @@ -3146,6 +3932,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Disable Parity Error Interrupt @@ -3193,6 +3980,35 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Disable LIN Break Detection Interrupt * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3247,6 +4063,22 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} +#endif + #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -3263,6 +4095,22 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE @@ -3274,6 +4122,25 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); +} +#else + /** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE @@ -3284,6 +4151,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } +#endif /** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. @@ -3296,6 +4164,25 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); +} +#else + /** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE @@ -3306,6 +4193,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } +#endif /** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. @@ -3353,6 +4241,35 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); +} +#endif + /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3403,7 +4320,24 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); +} +#endif + #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. @@ -3419,6 +4353,22 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); +} +#endif + /** * @} */ @@ -3652,7 +4602,15 @@ __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) } /** + @if USART_CR1_FIFOEN + * @brief Request a Receive Data and FIFO flush + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + @else * @brief Request a Receive Data flush + @endif * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush * @param USARTx USART Instance * @retval None @@ -3663,7 +4621,13 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) } /** + @if USART_CR1_FIFOEN + * @brief Request a Transmit data and FIFO flush + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + @else * @brief Request a Transmit data flush + @endif * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c index d31a3b1f241..ce44b68be8b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usb.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -67,7 +65,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_LL_USB_DRIVER * @{ @@ -571,6 +570,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0) { + // Added for MBED PR #3062 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num); } } @@ -681,6 +681,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0) { + // Added for MBED PR #3062 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num)); } @@ -1407,6 +1408,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /* Write packet into the Tx FIFO. */ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); + // Added for MBED PR #3432 hc->xfer_count = hc->xfer_len; } @@ -2386,7 +2388,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h index 9b30b103fa8..d10baf2e602 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usb.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention @@ -46,7 +44,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -605,7 +604,8 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c index 57c477b0c98..dff9d0b8ff5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_utils.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief UTILS LL module driver. ****************************************************************************** * @attention @@ -40,6 +38,13 @@ #include "stm32l4xx_ll_system.h" #include "stm32l4xx_ll_pwr.h" +// Removed from MBED PR #3410 +//#ifdef USE_FULL_ASSERT +//#include "stm32_assert.h" +//#else +//#define assert_param(expr) ((void)0U) +//#endif /* USE_FULL_ASSERT */ + /** @addtogroup STM32L4xx_LL_Driver * @{ */ @@ -54,8 +59,13 @@ /** @addtogroup UTILS_LL_Private_Constants * @{ */ -#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#else +#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#endif /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */ @@ -68,6 +78,15 @@ #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to HCLK Frequency */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#else #define UTILS_SCALE1_LATENCY1_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ #define UTILS_SCALE1_LATENCY2_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ #define UTILS_SCALE1_LATENCY3_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ @@ -75,6 +94,7 @@ #define UTILS_SCALE2_LATENCY1_FREQ 6000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ #define UTILS_SCALE2_LATENCY2_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ #define UTILS_SCALE2_LATENCY3_FREQ 18000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ +#endif /** * @} */ @@ -216,29 +236,51 @@ void LL_mDelay(uint32_t Delay) [..] System, AHB and APB buses clocks configuration - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80000000 Hz. + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is + 120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others. @endverbatim @internal Depending on the device voltage range, the maximum frequency should be adapted accordingly: - (++) Table 1. HCLK clock frequency. - (++) +-------------------------------------------------------+ - (++) | Latency | HCLK clock frequency (MHz) | - (++) | |-------------------------------------| - (++) | | voltage range 1 | voltage range 2 | - (++) | | 1.2 V | 1.0 V | - (++) |-----------------|------------------|------------------| - (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | - (++) |-----------------|------------------|------------------| - (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | - (++) |-----------------|------------------|------------------| - (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | - (++) |-----------------|------------------|------------------| - (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | - (++) |-----------------|------------------|------------------| - (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | - (++) +-------------------------------------------------------+ + (++) Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices + (++) +--------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |--------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.0 V | + (++) |-----------------|-------------------|------------------| + (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | + (++) |-----------------|-------------------|------------------| + (++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | + (++) |-----------------|-------------------|------------------| + (++) |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | + (++) |-----------------|-------------------|------------------| + (++) |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | + (++) |-----------------|-------------------|------------------| + (++) |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | + (++) |-----------------|-------------------|------------------| + (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | + (++) +--------------------------------------------------------+ + + (++) Table 2. HCLK clock frequency for other STM32L4 devices + (++) +-------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |-------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.0 V | + (++) |-----------------|------------------|------------------| + (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | + (++) |-----------------|------------------|------------------| + (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | + (++) |-----------------|------------------|------------------| + (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | + (++) |-----------------|------------------|------------------| + (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | + (++) |-----------------|------------------|------------------| + (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | + (++) +-------------------------------------------------------+ + @endinternal * @{ */ @@ -262,7 +304,7 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) * - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR) * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM) * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLR: ensure that max frequency at 80000000 Hz is reached (PLLVCO_output / PLLR) + * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR) * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains @@ -276,6 +318,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U, msi_range = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = 0U; +#endif /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) @@ -292,7 +337,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */ case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */ case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */ - /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/ + /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/ status = ERROR; break; @@ -345,8 +390,28 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + hpre = UTILS_ClkInitStruct->AHBCLKDivider; + if(hpre == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + } + } +#endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Apply definitive AHB prescaler value if necessary */ + if((status == SUCCESS) && (hpre != 0U)) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + } +#endif } } else @@ -365,7 +430,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR) * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM) * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLR: ensure that max frequency at 80000000 Hz is reach (PLLVCO_output / PLLR) + * - PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR) * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains @@ -379,6 +444,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = 0U; +#endif /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) @@ -400,8 +468,28 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + hpre = UTILS_ClkInitStruct->AHBCLKDivider; + if(hpre == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + } + } +#endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Apply definitive AHB prescaler value if necessary */ + if((status == SUCCESS) && (hpre != 0U)) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + } +#endif } else { @@ -419,7 +507,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR) * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM) * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLR: ensure that max frequency at 80000000 Hz is reached (PLLVCO_output / PLLR) + * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR) * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 * @param HSEBypass This parameter can be one of the following values: * @arg @ref LL_UTILS_HSEBYPASS_ON @@ -437,6 +525,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = 0U; +#endif /* Check the parameters */ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); @@ -473,8 +564,28 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + hpre = UTILS_ClkInitStruct->AHBCLKDivider; + if(hpre == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + } + } +#endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Apply definitive AHB prescaler value if necessary */ + if((status == SUCCESS) && (hpre != 0U)) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + } +#endif } else { @@ -519,6 +630,37 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) { if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) + { + /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) { /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */ @@ -541,11 +683,28 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } - /* else HCLK_Frequency < 16MHz default LL_FLASH_LATENCY_0 0WS */ + /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */ } +#endif } else /* SCALE2 */ { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) { /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */ @@ -563,8 +722,9 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } - /* else HCLK_Frequency < 6MHz default LL_FLASH_LATENCY_0 0WS */ + /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */ } +#endif } LL_FLASH_SetLatency(latency); @@ -604,7 +764,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); - /* - PLLR: ensure that max frequency at 80000000 Hz is reached */ + /* - PLLR: ensure that max frequency at 120000000 Hz is reached */ pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1) * 2); assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); @@ -634,8 +794,8 @@ static ErrorStatus UTILS_PLL_IsBusy(void) /* PLLSAI1 configuration cannot be modified */ status = ERROR; } - #if defined(RCC_PLLSAI2_SUPPORT) + /* Check if PLLSAI2 is busy*/ if(LL_RCC_PLLSAI2_IsReady() != 0U) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h index cc764390b7d..01a32c8ab8e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_utils.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of UTILS LL module. @verbatim ============================================================================== @@ -189,6 +187,11 @@ typedef struct #define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000010U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */ /** * @} */ @@ -243,7 +246,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void) */ __STATIC_INLINE uint32_t LL_GetFlashSize(void) { - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); } /** @@ -260,12 +263,17 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { - return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); } /** @@ -279,7 +287,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) /** * @brief This function configures the Cortex-M SysTick source of the time base. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param Ticks Number of ticks * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h index 19528d25273..01ba7d09875 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c index 4e9cc827c4b..f8719f6b4d4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32l4xx.c * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File * * This file provides two functions and one global variable to be called from @@ -110,15 +108,15 @@ #include "stm32l4xx.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -167,12 +165,12 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 4000000; + uint32_t SystemCoreClock = 4000000U; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \ - 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; /** * @} */ @@ -189,6 +187,7 @@ * @{ */ +// Removed from MBED PR #4740 /*+ MBED */ #if 0 /*- MBED */ @@ -205,24 +204,25 @@ void SystemInit(void) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; /* Reset CFGR register */ - RCC->CFGR = 0x00000000; + RCC->CFGR = 0x00000000U; /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; + RCC->CR &= 0xEAF6FFFFU; /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; + RCC->PLLCFGR = 0x00001000U; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= 0xFFFBFFFFU; /* Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -280,16 +280,16 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2; + uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; /* Get MSI Range frequency--------------------------------------------------*/ if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8; + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; } else { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4; + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; @@ -314,7 +314,7 @@ void SystemCoreClockUpdate(void) SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ; + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; switch (pllsource) { @@ -330,8 +330,8 @@ void SystemCoreClockUpdate(void) pllvco = (msirange / pllm); break; } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2; + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; SystemCoreClock = pllvco/pllr; break; @@ -341,7 +341,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index 8bc710070a1..1ae5e9f24f2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,187 +27,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "serial_api_hal.h" #if DEVICE_SERIAL -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include -#include "PeripheralPins.h" +#include "serial_api_hal.h" -#define UART_NUM (6) +#if defined (TARGET_STM32L432xC) + #define UART_NUM (3) +#elif defined (TARGET_STM32L433xC) + #define UART_NUM (4) +#else + #define UART_NUM (6) // max value (TARGET_STM32L475xG / TARGET_STM32L476xG / TARGET_STM32L486xG / TARGET_STM32L496xG) +#endif -static uint32_t serial_irq_ids[UART_NUM] = {0}; +uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj_s->uart != (UARTName)NC); - - // Enable USART clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_ENABLE(); - obj_s->index = 0; - } - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_ENABLE(); - obj_s->index = 1; - } - -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_ENABLE(); - obj_s->index = 2; - } -#endif - -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_ENABLE(); - obj_s->index = 3; - } -#endif - -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_ENABLE(); - obj_s->index = 4; - } -#endif - -#if defined(LPUART1_BASE) - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_ENABLE(); - obj_s->index = 5; - } -#endif - - // Configure UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj_s->baudrate = 9600; - obj_s->databits = UART_WORDLENGTH_8B; - obj_s->stopbits = UART_STOPBITS_1; - obj_s->parity = UART_PARITY_NONE; - -#if DEVICE_SERIAL_FC - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; -#endif - - obj_s->pin_tx = tx; - obj_s->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj_s->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - // Reset UART and disable clock - if (obj_s->uart == UART_1) { - __HAL_RCC_USART1_FORCE_RESET(); - __HAL_RCC_USART1_RELEASE_RESET(); - __HAL_RCC_USART1_CLK_DISABLE(); - } - - if (obj_s->uart == UART_2) { - __HAL_RCC_USART2_FORCE_RESET(); - __HAL_RCC_USART2_RELEASE_RESET(); - __HAL_RCC_USART2_CLK_DISABLE(); - } - -#if defined(USART3_BASE) - if (obj_s->uart == UART_3) { - __HAL_RCC_USART3_FORCE_RESET(); - __HAL_RCC_USART3_RELEASE_RESET(); - __HAL_RCC_USART3_CLK_DISABLE(); - } -#endif - -#if defined(UART4_BASE) - if (obj_s->uart == UART_4) { - __HAL_RCC_UART4_FORCE_RESET(); - __HAL_RCC_UART4_RELEASE_RESET(); - __HAL_RCC_UART4_CLK_DISABLE(); - } -#endif - -#if defined(UART5_BASE) - if (obj_s->uart == UART_5) { - __HAL_RCC_UART5_FORCE_RESET(); - __HAL_RCC_UART5_RELEASE_RESET(); - __HAL_RCC_UART5_CLK_DISABLE(); - } -#endif - -#if defined(LPUART1_BASE) - if (obj_s->uart == LPUART_1) { - __HAL_RCC_LPUART1_FORCE_RESET(); - __HAL_RCC_LPUART1_RELEASE_RESET(); - __HAL_RCC_LPUART1_CLK_DISABLE(); - } -#endif - - // Configure GPIOs - pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj_s->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - struct serial_s *obj_s = SERIAL_S(obj); - - obj_s->baudrate = baudrate; - init_uart(obj); -} - /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ @@ -491,7 +328,7 @@ static IRQn_Type serial_get_irq_n(serial_t *obj) irq_n = USART2_IRQn; break; -#if defined(UART3_BASE) +#if defined(USART3_BASE) case 2: irq_n = USART3_IRQn; break; @@ -806,7 +643,7 @@ void serial_rx_abort_asynch(serial_t *obj) } } -#endif +#endif /* DEVICE_SERIAL_ASYNCH */ #if DEVICE_SERIAL_FC @@ -865,6 +702,6 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi init_uart(obj); } -#endif +#endif /* DEVICE_SERIAL_FC */ -#endif +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index bd2d7342472..246f5d19715 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -57,14 +57,14 @@ void can_init_freq (can_t *obj, PinName rd, PinName td, int hz) __HAL_RCC_CAN1_CLK_ENABLE(); obj->index = 0; } -#if defined(CAN2_BASE) && defined(CAN_2) +#if defined(CAN2_BASE) && (CAN_NUM > 1) else if (can == CAN_2) { __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters __HAL_RCC_CAN2_CLK_ENABLE(); obj->index = 1; } #endif -#if defined(CAN3_BASE) && defined(CAN_3) +#if defined(CAN3_BASE) && (CAN_NUM > 2) else if (can == CAN_3) { __HAL_RCC_CAN3_CLK_ENABLE(); obj->index = 2; @@ -103,7 +103,13 @@ void can_init_freq (can_t *obj, PinName rd, PinName td, int hz) can_registers_init(obj); + /* Bits 27:14 are available for dual CAN configuration and are reserved for + single CAN configuration: */ +#if defined(CAN3_BASE) && (CAN_NUM > 2) + uint32_t filter_number = (can == CAN_1 || can == CAN_3) ? 0 : 14; +#else uint32_t filter_number = (can == CAN_1) ? 0 : 14; +#endif can_filter(obj, 0, 0, CANStandard, filter_number); } @@ -132,14 +138,14 @@ void can_free(can_t *obj) __HAL_RCC_CAN1_RELEASE_RESET(); __HAL_RCC_CAN1_CLK_DISABLE(); } -#if defined(CAN2_BASE) && defined(CAN_2) +#if defined(CAN2_BASE) && (CAN_NUM > 1) if (can == CAN_2) { __HAL_RCC_CAN2_FORCE_RESET(); __HAL_RCC_CAN2_RELEASE_RESET(); __HAL_RCC_CAN2_CLK_DISABLE(); } #endif -#if defined(CAN3_BASE) && defined(CAN_3) +#if defined(CAN3_BASE) && (CAN_NUM > 2) if (can == CAN_3) { __HAL_RCC_CAN3_FORCE_RESET(); __HAL_RCC_CAN3_RELEASE_RESET(); @@ -277,9 +283,9 @@ int can_write(can_t *obj, CAN_Message msg, int cc) can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (!(msg.format)) { - can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | msg.type); + can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | (msg.type << 1)); } else { - can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | msg.type); + can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | (msg.type << 1)); } /* Set up the DLC */ @@ -462,11 +468,11 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t sFilterConfig.FilterIdLow = 0x0; sFilterConfig.FilterMaskIdHigh = mask << 5; sFilterConfig.FilterMaskIdLow = 0x0; // allows both remote and data frames - } else if (format == CANExtended) { + } else { // format == CANExtended sFilterConfig.FilterIdHigh = id >> 13; // EXTID[28:13] - sFilterConfig.FilterIdLow = (0x00FF & (id << 3)) | (1 << 2); // EXTID[12:0] + sFilterConfig.FilterIdLow = (0xFFFF & (id << 3)) | (1 << 2); // EXTID[12:0] + IDE sFilterConfig.FilterMaskIdHigh = mask >> 13; - sFilterConfig.FilterMaskIdLow = (0x00FF & (mask << 3)) | (1 << 2); + sFilterConfig.FilterMaskIdLow = (0xFFFF & (mask << 3)) | (1 << 2); } sFilterConfig.FilterFIFOAssignment = 0; @@ -562,7 +568,7 @@ void CAN1_SCE_IRQHandler(void) { can_irq(CAN_1, 0); } -#if defined(CAN2_BASE) && defined(CAN_2) +#if defined(CAN2_BASE) && (CAN_NUM > 1) void CAN2_RX0_IRQHandler(void) { can_irq(CAN_2, 1); @@ -576,18 +582,18 @@ void CAN2_SCE_IRQHandler(void) can_irq(CAN_2, 1); } #endif -#if defined(CAN3_BASE) && defined(CAN_3) +#if defined(CAN3_BASE) && (CAN_NUM > 2) void CAN3_RX0_IRQHandler(void) { - can_irq(CAN_3, 1); + can_irq(CAN_3, 2); } void CAN3_TX_IRQHandler(void) { - can_irq(CAN_3, 1); + can_irq(CAN_3, 2); } void CAN3_SCE_IRQHandler(void) { - can_irq(CAN_3, 1); + can_irq(CAN_3, 2); } #endif #endif // else @@ -630,7 +636,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) return; } } -#if defined(CAN2_BASE) && defined(CAN_2) +#if defined(CAN2_BASE) && (CAN_NUM > 1) else if ((CANName) can == CAN_2) { switch (type) { case IRQ_RX: @@ -663,7 +669,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) } } #endif -#if defined(CAN3_BASE) && defined(CAN_3) +#if defined(CAN3_BASE) && (CAN_NUM > 2) else if ((CANName) can == CAN_3) { switch (type) { case IRQ_RX: @@ -711,4 +717,3 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) } #endif // DEVICE_CAN - diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c index 7e84f34418e..2fb605413f0 100644 --- a/targets/TARGET_STM/hal_tick_32b.c +++ b/targets/TARGET_STM/hal_tick_32b.c @@ -42,7 +42,7 @@ void timer_irq_handler(void) if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) { if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) { __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); - uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + uint32_t val = __HAL_TIM_GET_COUNTER(&TimMasterHandle); if ((val - PreviousVal) >= HAL_TICK_DELAY) { // Increment HAL variable HAL_IncTick(); @@ -114,7 +114,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) // Channel 2 for HAL tick HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); - PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + PreviousVal = __HAL_TIM_GET_COUNTER(&TimMasterHandle); __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 31330863d88..b757e3b005a 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -413,7 +413,7 @@ void i2c_frequency(i2c_t *obj, int hz) #ifdef I2C_ANALOGFILTER_ENABLE /* Enable the Analog I2C Filter */ - HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE); + HAL_I2CEx_ConfigAnalogFilter(handle,I2C_ANALOGFILTER_ENABLE); #endif // I2C configuration diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 689833ffcd6..7b12b34736b 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,39 +27,273 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "device.h" #if DEVICE_LOWPOWERTIMER -#include "ticker_api.h" -#include "lp_ticker_api.h" -#include "rtc_api.h" #include "rtc_api_hal.h" -static uint8_t lp_ticker_inited = 0; +#if MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM + +LPTIM_HandleTypeDef LptimHandle; + +volatile uint32_t lp_SlaveCounter = 0; +volatile uint32_t lp_oc_int_part = 0; +volatile uint16_t lp_TickPeriod_us; +volatile uint8_t lp_Fired = 0; + +static void LPTIM1_IRQHandler(void); +static void (*irq_handler)(void); + void lp_ticker_init(void) { - if (lp_ticker_inited) return; - lp_ticker_inited = 1; + /* Check if LPTIM is already configured */ +#if (TARGET_STM32L0) + if (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET) { + return; + } +#else + if (__HAL_RCC_LPTIM1_IS_CLK_ENABLED()) { + return; + } +#endif - rtc_init(); - rtc_set_irq_handler((uint32_t) lp_ticker_irq_handler); + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + +#if MBED_CONF_TARGET_LSE_AVAILABLE + + /* Enable LSE clock */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + + /* Select the LSE clock as LPTIM peripheral clock */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; +#if (TARGET_STM32L0) + RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSE; +#else + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE; +#endif + +#else /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + /* Enable LSI clock */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + + /* Select the LSI clock as LPTIM peripheral clock */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; +#if (TARGET_STM32L0) + RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSI; +#else + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; +#endif + +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("HAL_RCC_OscConfig ERROR\n"); + return; + } + + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) { + error("HAL_RCCEx_PeriphCLKConfig ERROR\n"); + return; + } + + __HAL_RCC_LPTIM1_CLK_ENABLE(); + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + + /* Initialize the LPTIM peripheral */ + LptimHandle.Instance = LPTIM1; + LptimHandle.State = HAL_LPTIM_STATE_RESET; + LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + + /* Prescaler impact: + tick period = Prescaler division factor / LPTIM clock + Example with LPTIM clock = 32768 Hz LSE + Prescaler = LPTIM_PRESCALER_DIV1 => lp_TickPeriod_us = 31us => 2s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV2 => lp_TickPeriod_us = 61us => 4s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV4 => lp_TickPeriod_us = 122us => 8s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV8 => lp_TickPeriod_us = 244us => 16s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV16 => lp_TickPeriod_us = 488us => 32s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV32 => lp_TickPeriod_us = 976us => 64s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV64 => lp_TickPeriod_us = 1.9ms => 128s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV128 => lp_TickPeriod_us = 3.9ms => 256s with 16b timer + */ + LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV2; + lp_TickPeriod_us = 2 * 1000000 / RTC_CLOCK; + + LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; +#if (TARGET_STM32L4) + LptimHandle.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + LptimHandle.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; +#endif /* TARGET_STM32L4 */ + + if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) { + error("HAL_LPTIM_Init ERROR\n"); + return; + } + + NVIC_SetVector(LPTIM1_IRQn, (uint32_t)LPTIM1_IRQHandler); + NVIC_EnableIRQ(LPTIM1_IRQn); + +#if !(TARGET_STM32L4) + /* EXTI lines are not configured by default */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); +#endif + + __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_ARRM); + __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPM); + __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPOK); + HAL_LPTIM_Counter_Start(&LptimHandle, 0xFFFF); } -uint32_t lp_ticker_read(void) +static void LPTIM1_IRQHandler(void) { - uint32_t usecs = 0; - time_t time = 0; + LptimHandle.Instance = LPTIM1; - lp_ticker_init(); + if (lp_Fired) { + lp_Fired = 0; + if (irq_handler) { + irq_handler(); + } + } + + /* Compare match interrupt */ + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) != RESET) { + if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPM) != RESET) { + /* Clear Compare match flag */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); + + if (lp_oc_int_part > 0) { + lp_oc_int_part--; + } else { + if (irq_handler) { + irq_handler(); + } + } + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) != RESET) { + if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPOK) != RESET) { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); + } + } + + /* Autoreload match interrupt */ + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) != RESET) { + if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_ARRM) != RESET) { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_ARRM); + lp_SlaveCounter++; + } + } + +#if !(TARGET_STM32L4) + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); +#endif +} + + +uint32_t lp_ticker_read_TickCounter(void) +{ + uint16_t cntH_old, cntH, cntL; + + LptimHandle.Instance = LPTIM1; + /* same algo as us_ticker_read in us_ticker_16b.c */ do { - time = rtc_read(); - usecs = rtc_read_subseconds(); - } while (time != rtc_read()); + cntH_old = lp_SlaveCounter; + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) == SET) { + cntH_old += 1; + } + cntL = LPTIM1->CNT; + cntH = lp_SlaveCounter; + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) == SET) { + cntH += 1; + } + } while (cntH_old != cntH); + uint32_t lp_time = (uint32_t)(cntH << 16 | cntL); + return lp_time; +} - return (time * 1000000) + usecs; +uint32_t lp_ticker_read(void) +{ + lp_ticker_init(); + return lp_ticker_read_TickCounter() * (uint32_t)lp_TickPeriod_us; +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + // Disable IRQs + core_util_critical_section_enter(); + + uint32_t timestamp_TickCounter = timestamp / (uint32_t)lp_TickPeriod_us; + + LptimHandle.Instance = LPTIM1; + irq_handler = (void (*)(void))lp_ticker_irq_handler; + + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); + __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp_TickCounter & 0xFFFF); + + /* CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed */ + while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) { + } + + /* same algo as us_ticker_set_interrupt in us_ticker_16b.c */ + uint32_t current_time_TickCounter = lp_ticker_read_TickCounter(); + uint32_t delta = timestamp_TickCounter - current_time_TickCounter; + lp_oc_int_part = (delta - 1) >> 16; + if ( ((delta - 1) & 0xFFFF) >= 0x8000 && + __HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) == SET ) { + ++lp_oc_int_part; + } + + // Enable IRQs + core_util_critical_section_exit(); +} + +void lp_ticker_fire_interrupt(void) +{ + lp_Fired = 1; + NVIC_SetPendingIRQ(LPTIM1_IRQn); +} + +void lp_ticker_disable_interrupt(void) +{ + LptimHandle.Instance = LPTIM1; + __HAL_LPTIM_DISABLE_IT(&LptimHandle, LPTIM_IT_CMPM); +} + +void lp_ticker_clear_interrupt(void) +{ + LptimHandle.Instance = LPTIM1; + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); +} + +#else /* MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ + +void lp_ticker_init(void) +{ + rtc_init(); +} + +uint32_t lp_ticker_read(void) +{ + uint32_t usecs = rtc_read_us(); + return usecs; } void lp_ticker_set_interrupt(timestamp_t timestamp) @@ -82,7 +316,9 @@ void lp_ticker_disable_interrupt(void) void lp_ticker_clear_interrupt(void) { - + NVIC_ClearPendingIRQ(RTC_WKUP_IRQn); } -#endif +#endif /* MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ + +#endif /* DEVICE_LOWPOWERTIMER */ diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index 5bdba667353..7cd20829611 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -52,7 +52,8 @@ #elif defined(TARGET_STM32F303VC) #define INITIAL_SP (0x2000A000UL) -#elif defined(TARGET_STM32L432KC) +#elif defined(TARGET_STM32L432KC) ||\ + defined (TARGET_STM32L433RC) #define INITIAL_SP (0x20010000UL) #elif (defined(TARGET_STM32F303RE) ||\ diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 23f7625012b..76cad5d18b8 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,33 +27,22 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #if DEVICE_RTC -#include "rtc_api.h" #include "rtc_api_hal.h" -#include "mbed_error.h" #include "mbed_mktime.h" static RTC_HandleTypeDef RtcHandle; -#if RTC_LSI -#define RTC_CLOCK LSI_VALUE -#else -#define RTC_CLOCK LSE_VALUE -#endif +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM -#if DEVICE_LOWPOWERTIMER -#define RTC_ASYNCH_PREDIV ((RTC_CLOCK - 1) / 0x8000) -#define RTC_SYNCH_PREDIV (RTC_CLOCK / (RTC_ASYNCH_PREDIV + 1) - 1) -#else -#define RTC_ASYNCH_PREDIV (0x007F) -#define RTC_SYNCH_PREDIV (RTC_CLOCK / (RTC_ASYNCH_PREDIV + 1) - 1) -#endif +#define GET_TICK_PERIOD(VALUE) (2048 * 1000000 / VALUE) /* 1s / SynchPrediv value * 2^11 (value to get the maximum precision value with no u32 overflow) */ -#if DEVICE_LOWPOWERTIMER static void (*irq_handler)(void); static void RTC_IRQHandler(void); -#endif +static uint32_t lp_TickPeriod_us = GET_TICK_PERIOD(4095); /* default SynchPrediv value = 4095 */ +#endif /* DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ void rtc_init(void) { @@ -61,38 +50,38 @@ void rtc_init(void) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; // Enable access to Backup domain + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWR_EnableBkUpAccess(); - RtcHandle.Instance = RTC; - RtcHandle.State = HAL_RTC_STATE_RESET; + if (rtc_isenabled()) { + return; + } -#if !RTC_LSI - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; +#if MBED_CONF_TARGET_LSE_AVAILABLE + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE); - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - } else { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("Cannot initialize RTC with LSE\n"); } + __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { error("PeriphClkInitStruct RTC failed with LSE\n"); } -#else /* !RTC_LSI */ - __HAL_RCC_PWR_CLK_ENABLE(); - +#else /* MBED_CONF_TARGET_LSE_AVAILABLE */ // Reset Backup domain __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! RCC_OscInitStruct.LSEState = RCC_LSE_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_ON; @@ -108,46 +97,54 @@ void rtc_init(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { error("PeriphClkInitStruct RTC failed with LSI\n"); } -#endif /* !RTC_LSI */ +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ // Enable RTC __HAL_RCC_RTC_ENABLE(); + RtcHandle.Instance = RTC; + RtcHandle.State = HAL_RTC_STATE_RESET; + #if TARGET_STM32F1 RtcHandle.Init.AsynchPrediv = RTC_AUTO_1_SECOND; #else /* TARGET_STM32F1 */ RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; - RtcHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV; + + /* PREDIV_A : 7-bit asynchronous prescaler */ +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM + /* PREDIV_A is set to a small value to improve the SubSeconds resolution */ + /* with a 32768Hz clock, PREDIV_A=7 gives a precision of 244us */ + RtcHandle.Init.AsynchPrediv = 7; +#else + /* PREDIV_A is set to the maximum value to improve the consumption */ + RtcHandle.Init.AsynchPrediv = 0x007F; +#endif + /* PREDIV_S : 15-bit synchronous prescaler */ + /* PREDIV_S is set in order to get a 1 Hz clock */ + RtcHandle.Init.SynchPrediv = RTC_CLOCK / (RtcHandle.Init.AsynchPrediv + 1) - 1; RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; #endif /* TARGET_STM32F1 */ +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM + lp_TickPeriod_us = GET_TICK_PERIOD(RtcHandle.Init.SynchPrediv); +#endif + if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); + error("RTC initialization failed"); } -#if DEVICE_LOWPOWERTIMER + rtc_synchronize(); // Wait for RSF -#if !RTC_LSI - if (!rtc_isenabled()) -#endif /* !RTC_LSI */ - { + if (!rtc_isenabled()) { rtc_write(0); } - - NVIC_ClearPendingIRQ(RTC_WKUP_IRQn); - NVIC_DisableIRQ(RTC_WKUP_IRQn); - NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler); - NVIC_EnableIRQ(RTC_WKUP_IRQn); - -#endif /* DEVICE_LOWPOWERTIMER */ } void rtc_free(void) { -#if RTC_LSI +#if !MBED_CONF_TARGET_LSE_AVAILABLE // Enable Power clock __HAL_RCC_PWR_CLK_ENABLE(); @@ -241,7 +238,10 @@ time_t rtc_read(void) timeinfo.tm_isdst = -1; // Convert to timestamp - time_t t = _rtc_mktime(&timeinfo); + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } return t; } @@ -255,7 +255,7 @@ void rtc_write(time_t t) // Convert the time into a tm struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { return; } @@ -279,8 +279,12 @@ void rtc_write(time_t t) #endif /* TARGET_STM32F1 */ // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN); + if (HAL_RTC_SetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN) != HAL_OK) { + error("HAL_RTC_SetDate error\n"); + } + if (HAL_RTC_SetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN) != HAL_OK) { + error("HAL_RTC_SetTime error\n"); + } } int rtc_isenabled(void) @@ -292,11 +296,20 @@ int rtc_isenabled(void) #endif /* TARGET_STM32F1 */ } -#if DEVICE_LOWPOWERTIMER +void rtc_synchronize(void) +{ + RtcHandle.Instance = RTC; + if (HAL_RTC_WaitForSynchro(&RtcHandle) != HAL_OK) { + error("rtc_synchronize error\n"); + } +} + +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM static void RTC_IRQHandler(void) { /* Update HAL state */ + RtcHandle.Instance = RTC; HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle); /* In case of registered handler, call it. */ if (irq_handler) { @@ -304,35 +317,70 @@ static void RTC_IRQHandler(void) } } -void rtc_set_irq_handler(uint32_t handler) +uint32_t rtc_read_us(void) { - irq_handler = (void (*)(void))handler; -} + RTC_TimeTypeDef timeStruct = {0}; + RTC_DateTypeDef dateStruct = {0}; -uint32_t rtc_read_subseconds(void) -{ - return 1000000.f * ((double)(RTC_SYNCH_PREDIV - RTC->SSR) / (RTC_SYNCH_PREDIV + 1)); + RtcHandle.Instance = RTC; + HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN); + + /* Reading RTC current time locks the values in calendar shadow registers until Current date is read + to ensure consistency between the time and date values */ + HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN); + + if (timeStruct.SubSeconds > timeStruct.SecondFraction) { + /* SS can be larger than PREDIV_S only after a shift operation. In that case, the correct + time/date is one second less than as indicated by RTC_TR/RTC_DR. */ + timeStruct.Seconds -= 1; + } + uint32_t RTCTime = timeStruct.Seconds + timeStruct.Minutes * 60 + timeStruct.Hours * 60 * 60; + uint32_t Time_us = ((timeStruct.SecondFraction - timeStruct.SubSeconds) * lp_TickPeriod_us) >> 11; + + return (RTCTime * 1000000) + Time_us ; } void rtc_set_wake_up_timer(uint32_t delta) { - uint32_t wake_up_counter = delta / (2000000 / RTC_CLOCK); + /* Ex for Wakeup period resolution with RTCCLK=32768 Hz : + * RTCCLK_DIV2: ~122us < wakeup period < ~4s + * RTCCLK_DIV4: ~244us < wakeup period < ~8s + * RTCCLK_DIV8: ~488us < wakeup period < ~16s + * RTCCLK_DIV16: ~976us < wakeup period < ~32s + * CK_SPRE_16BITS: 1s < wakeup period < (0xFFFF+ 1) x 1 s = 65536 s (18 hours) + * CK_SPRE_17BITS: 18h+1s < wakeup period < (0x1FFFF+ 1) x 1 s = 131072 s (36 hours) + */ + uint32_t WakeUpClock[6] = {RTC_WAKEUPCLOCK_RTCCLK_DIV2, RTC_WAKEUPCLOCK_RTCCLK_DIV4, RTC_WAKEUPCLOCK_RTCCLK_DIV8, RTC_WAKEUPCLOCK_RTCCLK_DIV16, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, RTC_WAKEUPCLOCK_CK_SPRE_17BITS}; + uint8_t ClockDiv[4] = {2, 4, 8, 16}; + uint32_t WakeUpCounter; + uint8_t DivIndex = 0; + + do { + WakeUpCounter = delta / (ClockDiv[DivIndex] * 1000000 / RTC_CLOCK); + DivIndex++; + } while ( (WakeUpCounter > 0xFFFF) && (DivIndex < 4) ); + + if (WakeUpCounter > 0xFFFF) { + WakeUpCounter = delta / 1000000; + DivIndex++; + } - if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, wake_up_counter, - RTC_WAKEUPCLOCK_RTCCLK_DIV2) != HAL_OK) { - error("Set wake up timer failed\n"); + irq_handler = (void (*)(void))lp_ticker_irq_handler; + NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler); + NVIC_EnableIRQ(RTC_WKUP_IRQn); + + RtcHandle.Instance = RTC; + if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex - 1]) != HAL_OK) { + error("rtc_set_wake_up_timer init error (%d)\n", DivIndex); } } void rtc_deactivate_wake_up_timer(void) { + RtcHandle.Instance = RTC; HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle); } -void rtc_synchronize(void) -{ - HAL_RTC_WaitForSynchro(&RtcHandle); -} -#endif /* DEVICE_LOWPOWERTIMER */ +#endif /* DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ #endif /* DEVICE_RTC */ diff --git a/targets/TARGET_STM/rtc_api_hal.h b/targets/TARGET_STM/rtc_api_hal.h index 14a345438d3..ff1722a0e8a 100644 --- a/targets/TARGET_STM/rtc_api_hal.h +++ b/targets/TARGET_STM/rtc_api_hal.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* -* Copyright (c) 2016, STMicroelectronics +* Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,25 +33,29 @@ #include #include "rtc_api.h" +#include "ticker_api.h" +#include "lp_ticker_api.h" +#include "us_ticker_api.h" +#include "hal_tick.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include "mbed_debug.h" #ifdef __cplusplus extern "C" { #endif -/* - * Extend rtc_api.h - */ -/** Set the given function as handler of wakeup timer event. - * - * @param handler The function to set as handler - */ -void rtc_set_irq_handler(uint32_t handler); +#if MBED_CONF_TARGET_LSE_AVAILABLE +#define RTC_CLOCK LSE_VALUE +#else +#define RTC_CLOCK LSI_VALUE +#endif -/** Read the subsecond register. +/** Read RTC time with subsecond precision. * - * @return The remaining time as microseconds (0-999999) + * @return Time is microsecond */ -uint32_t rtc_read_subseconds(void); +uint32_t rtc_read_us(void); /** Program a wake up timer event in delta microseconds. * diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index 5d6167b61e3..29050a5b7c2 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,15 +27,403 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "mbed_assert.h" -#include "mbed_error.h" -#include "serial_api.h" -#include "serial_api_hal.h" -#include "PeripheralPins.h" #if DEVICE_SERIAL -void init_uart(serial_t *obj) +#include "serial_api_hal.h" + +int stdio_uart_inited = 0; // used in platform/mbed_board.c and platform/mbed_retarget.cpp +serial_t stdio_uart; + +extern UART_HandleTypeDef uart_handlers[]; +extern uint32_t serial_irq_ids[]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + struct serial_s *obj_s = SERIAL_S(obj); + int IndexNumber = 0; + uint8_t stdio_config = 0; + + // Determine the UART to use (UART_1, UART_2, ...) + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object + obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT(obj_s->uart != (UARTName)NC); + + if ((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX)) { + stdio_config = 1; + } + else { + if (uart_tx == pinmap_peripheral(STDIO_UART_TX, PinMap_UART_TX)) { + error("Error: new serial object is using same UART as STDIO"); + } + } + + // Enable USART clock +#if defined(USART1_BASE) + if (obj_s->uart == UART_1) { + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); + __HAL_RCC_USART1_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined (USART2_BASE) + if (obj_s->uart == UART_2) { + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + __HAL_RCC_USART2_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART3_BASE) + if (obj_s->uart == UART_3) { + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); + __HAL_RCC_USART3_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_UART4_FORCE_RESET(); + __HAL_RCC_UART4_RELEASE_RESET(); + __HAL_RCC_UART4_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_USART4_FORCE_RESET(); + __HAL_RCC_USART4_RELEASE_RESET(); + __HAL_RCC_USART4_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_UART5_FORCE_RESET(); + __HAL_RCC_UART5_RELEASE_RESET(); + __HAL_RCC_UART5_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_USART5_FORCE_RESET(); + __HAL_RCC_USART5_RELEASE_RESET(); + __HAL_RCC_USART5_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART6_BASE) + if (obj_s->uart == UART_6) { + __HAL_RCC_USART6_FORCE_RESET(); + __HAL_RCC_USART6_RELEASE_RESET(); + __HAL_RCC_USART6_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_UART7_FORCE_RESET(); + __HAL_RCC_UART7_RELEASE_RESET(); + __HAL_RCC_UART7_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_USART7_FORCE_RESET(); + __HAL_RCC_USART7_RELEASE_RESET(); + __HAL_RCC_USART7_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_UART8_FORCE_RESET(); + __HAL_RCC_UART8_RELEASE_RESET(); + __HAL_RCC_UART8_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(USART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_USART8_FORCE_RESET(); + __HAL_RCC_USART8_RELEASE_RESET(); + __HAL_RCC_USART8_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART9_BASE) + if (obj_s->uart == UART_9) { + __HAL_RCC_UART9_FORCE_RESET(); + __HAL_RCC_UART9_RELEASE_RESET(); + __HAL_RCC_UART9_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + +#if defined(UART10_BASE) + if (obj_s->uart == UART_10) { + __HAL_RCC_UART10_FORCE_RESET(); + __HAL_RCC_UART10_RELEASE_RESET(); + __HAL_RCC_UART10_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + + +#if defined(LPUART1_BASE) + if (obj_s->uart == LPUART_1) { + __HAL_RCC_LPUART1_FORCE_RESET(); + __HAL_RCC_LPUART1_RELEASE_RESET(); + __HAL_RCC_LPUART1_CLK_ENABLE(); + obj_s->index = IndexNumber; + } + IndexNumber++; +#endif + + // Configure UART pins + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + // Configure UART + obj_s->baudrate = 9600; // baudrate default value + if (stdio_config) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json +#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */ + } + else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + obj_s->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json +#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */ + } + obj_s->databits = UART_WORDLENGTH_8B; + obj_s->stopbits = UART_STOPBITS_1; + obj_s->parity = UART_PARITY_NONE; + +#if DEVICE_SERIAL_FC + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; +#endif + + obj_s->pin_tx = tx; + obj_s->pin_rx = rx; + + init_uart(obj); /* init_uart will be called again in serial_baud function, so don't worry if init_uart returns HAL_ERROR */ + + // For stdio management in platform/mbed_board.c and platform/mbed_retarget.cpp + if (stdio_config) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + struct serial_s *obj_s = SERIAL_S(obj); + + // Reset UART and disable clock +#if defined(USART1_BASE) + if (obj_s->uart == UART_1) { + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); + __HAL_RCC_USART1_CLK_DISABLE(); + } +#endif + +#if defined(USART2_BASE) + if (obj_s->uart == UART_2) { + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + __HAL_RCC_USART2_CLK_DISABLE(); + } +#endif + +#if defined(USART3_BASE) + if (obj_s->uart == UART_3) { + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); + __HAL_RCC_USART3_CLK_DISABLE(); + } +#endif + +#if defined(UART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_UART4_FORCE_RESET(); + __HAL_RCC_UART4_RELEASE_RESET(); + __HAL_RCC_UART4_CLK_DISABLE(); + } +#endif + +#if defined(USART4_BASE) + if (obj_s->uart == UART_4) { + __HAL_RCC_USART4_FORCE_RESET(); + __HAL_RCC_USART4_RELEASE_RESET(); + __HAL_RCC_USART4_CLK_DISABLE(); + } +#endif + +#if defined(UART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_UART5_FORCE_RESET(); + __HAL_RCC_UART5_RELEASE_RESET(); + __HAL_RCC_UART5_CLK_DISABLE(); + } +#endif + +#if defined(USART5_BASE) + if (obj_s->uart == UART_5) { + __HAL_RCC_USART5_FORCE_RESET(); + __HAL_RCC_USART5_RELEASE_RESET(); + __HAL_RCC_USART5_CLK_DISABLE(); + } +#endif + +#if defined(USART6_BASE) + if (obj_s->uart == UART_6) { + __HAL_RCC_USART6_FORCE_RESET(); + __HAL_RCC_USART6_RELEASE_RESET(); + __HAL_RCC_USART6_CLK_DISABLE(); + } +#endif + +#if defined(UART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_UART7_FORCE_RESET(); + __HAL_RCC_UART7_RELEASE_RESET(); + __HAL_RCC_UART7_CLK_DISABLE(); + } +#endif + +#if defined(USART7_BASE) + if (obj_s->uart == UART_7) { + __HAL_RCC_USART7_FORCE_RESET(); + __HAL_RCC_USART7_RELEASE_RESET(); + __HAL_RCC_USART7_CLK_DISABLE(); + } +#endif + +#if defined(UART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_UART8_FORCE_RESET(); + __HAL_RCC_UART8_RELEASE_RESET(); + __HAL_RCC_UART8_CLK_DISABLE(); + } +#endif + +#if defined(USART8_BASE) + if (obj_s->uart == UART_8) { + __HAL_RCC_USART8_FORCE_RESET(); + __HAL_RCC_USART8_RELEASE_RESET(); + __HAL_RCC_USART8_CLK_DISABLE(); + } +#endif + +#if defined(UART9_BASE) + if (obj_s->uart == UART_9) { + __HAL_RCC_UART9_FORCE_RESET(); + __HAL_RCC_UART9_RELEASE_RESET(); + __HAL_RCC_UART9_CLK_DISABLE(); + } +#endif + +#if defined(UART10_BASE) + if (obj_s->uart == UART_10) { + __HAL_RCC_UART10_FORCE_RESET(); + __HAL_RCC_UART10_RELEASE_RESET(); + __HAL_RCC_UART10_CLK_DISABLE(); + } +#endif + +#if defined(LPUART1_BASE) + if (obj_s->uart == LPUART_1) { + __HAL_RCC_LPUART1_FORCE_RESET(); + __HAL_RCC_LPUART1_RELEASE_RESET(); + __HAL_RCC_LPUART1_CLK_DISABLE(); + } +#endif + + // Configure GPIOs + pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + + serial_irq_ids[obj_s->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + struct serial_s *obj_s = SERIAL_S(obj); + + obj_s->baudrate = baudrate; + if (init_uart(obj) != HAL_OK) { + +#if defined(LPUART1_BASE) + /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */ + if (obj_s->uart == LPUART_1) { + /* Try to change LPUART clock source */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if (baudrate == 9600) { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + if (init_uart(obj) == HAL_OK){ + return; + } + } + else { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + if (init_uart(obj) == HAL_OK){ + return; + } + } + } +#endif /* LPUART1_BASE */ + + debug("Cannot initialize UART with baud rate %u\n", baudrate); + } +} + +HAL_StatusTypeDef init_uart(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; @@ -64,9 +452,7 @@ void init_uart(serial_t *obj) huart->Init.Mode = UART_MODE_TX_RX; } - if (HAL_UART_Init(huart) != HAL_OK) { - error("Cannot initialize UART\n"); - } + return HAL_UART_Init(huart); } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) diff --git a/targets/TARGET_STM/serial_api_hal.h b/targets/TARGET_STM/serial_api_hal.h index e4a1892f527..c5cea54e0b5 100644 --- a/targets/TARGET_STM/serial_api_hal.h +++ b/targets/TARGET_STM/serial_api_hal.h @@ -32,7 +32,12 @@ #define MBED_SERIAL_API_HAL_H #include "serial_api.h" +#include +#include "mbed_assert.h" +#include "mbed_debug.h" +#include "mbed_error.h" +#include "PeripheralPins.h" #ifdef __cplusplus extern "C" { @@ -47,14 +52,12 @@ extern "C" { #define SERIAL_S(obj) (obj) #endif -extern UART_HandleTypeDef uart_handlers[]; - /** Initialize and configure the UART peripheral * * @param obj The serial object containing the configuration */ -void init_uart(serial_t *obj); +HAL_StatusTypeDef init_uart(serial_t *obj); #ifdef __cplusplus } diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index d41edfe5b74..b4e36c892db 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -29,12 +29,8 @@ */ #if DEVICE_SLEEP -#include "cmsis.h" -#include "us_ticker_api.h" #include "sleep_api.h" #include "rtc_api_hal.h" -#include "hal_tick.h" -#include "mbed_critical.h" extern void HAL_SuspendTick(void); extern void HAL_ResumeTick(void); @@ -68,16 +64,16 @@ void hal_deepsleep(void) #if TARGET_STM32L4 int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED(); int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR; - + if (!pwrClockEnabled) { __HAL_RCC_PWR_CLK_ENABLE(); } if (lowPowerModeEnabled) { HAL_PWREx_DisableLowPowerRunMode(); } - + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); - + if (lowPowerModeEnabled) { HAL_PWREx_EnableLowPowerRunMode(); } @@ -101,8 +97,15 @@ void hal_deepsleep(void) TimMasterHandle.Instance = TIM_MST; __HAL_TIM_SET_COUNTER(&TimMasterHandle, EnterTimeUS); -#if DEVICE_LOWPOWERTIMER - rtc_synchronize(); +#if DEVICE_RTC + /* Wait for RTC RSF bit synchro if RTC is configured */ +#if (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) + if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) { +#else /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */ + if (__HAL_RCC_GET_RTC_SOURCE()) { +#endif /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */ + rtc_synchronize(); + } #endif } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h index 3147299bbdc..05bad32dc9d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h index d9cd0fef8a3..d3f9b7d58a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h index 13cbb9af1a0..1a1c9c9f83a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h index 976dce7abac..ccac6294382 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h index 976dce7abac..ccac6294382 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h index 022148984c3..b9ad628edc9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h @@ -24,6 +24,8 @@ #ifndef MBED_CLOCKING_H #define MBED_CLOCKING_H +#include "em_cmu.h" + /* Clock definitions */ #define LFXO 0 #define HFXO 1 @@ -51,8 +53,8 @@ #ifndef CORE_CLOCK_SOURCE #define CORE_CLOCK_SOURCE HFRCO #if defined(_CMU_HFRCOCTRL_BAND_MASK) -#define HFRCO_FREQUENCY_ENUM _CMU_HFRCOCTRL_BAND_21MHZ -#define HFRCO_FREQUENCY 21000000 +#define HFRCO_FREQUENCY_ENUM _CMU_HFRCOCTRL_BAND_21MHZ +#define HFRCO_FREQUENCY 21000000 #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) #define HFRCO_FREQUENCY_ENUM cmuHFRCOFreq_32M0Hz #define HFRCO_FREQUENCY 32000000 @@ -103,4 +105,13 @@ # endif #endif +/* Adjust this to change speed of RTC and LP ticker ticks */ +#define RTC_CLOCKDIV cmuClkDiv_8 +/* Adjust this to match RTC_CLOCKDIV as integer value */ +#define RTC_CLOCKDIV_INT 8U +/* Adjust this to match RTC_CLOCKDIV as shift for 1 second worth of ticks. + * E.g. with 32768 Hz crystal and CLOCKDIV of 8, 1 second is 4096 ticks. + * 4096 equals 1 << 12, so RTC_FREQ_SHIFT needs to be 12. */ +#define RTC_FREQ_SHIFT 12U + #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c index e3ded3571f2..bc8f479a6cd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c @@ -39,9 +39,13 @@ void mbed_sdk_init() CHIP_Init(); #if defined(_SILICON_LABS_32B_SERIES_1) - EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; +#if defined(EMU_NO_DCDC) + EMU_DCDCPowerOff(); +#else + EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_STK_DEFAULT; EMU_DCDCInit(&dcdcInit); - +#endif + #if (CORE_CLOCK_SOURCE == HFXO) // Only init HFXO if not already done (e.g. by bootloader) if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c index 8447f3e94f6..fc590a7ca7c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c @@ -25,7 +25,6 @@ #include "pinmap.h" #include "em_cmu.h" #include "mbed_assert.h" -#include "sleepmodes.h" void gpio_write(gpio_t *obj, int value) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c index 823d7a74660..b47627f76f7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c @@ -31,10 +31,8 @@ #include "em_gpio.h" #include "em_cmu.h" #include "sleep_api.h" -#include "sleepmodes.h" #define NUM_GPIO_CHANNELS (16) -#define GPIO_LEAST_ACTIVE_SLEEPMODE EM3 /* Macro return index of the LSB flag which is set. */ #if ((__CORTEX_M == 3) || (__CORTEX_M == 4)) @@ -142,21 +140,16 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) if(GPIO->IEN == 0) was_disabled = true; GPIO_IntConfig((GPIO_Port_TypeDef)((obj->pin >> 4) & 0xF), obj->pin &0xF, obj->risingEdge, obj->fallingEdge, obj->risingEdge || obj->fallingEdge); - if ((GPIO->IEN != 0) && (obj->risingEdge || obj->fallingEdge) && was_disabled) { - blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE); - } } inline void gpio_irq_enable(gpio_irq_t *obj) { - if(GPIO->IEN == 0) blockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE); GPIO_IntEnable(1 << (obj->pin & 0xF)); // pin mask for pins to enable } inline void gpio_irq_disable(gpio_irq_t *obj) { GPIO_IntDisable(1 << (obj->pin & 0xF)); // pin mask for pins to disable - if(GPIO->IEN == 0) unblockSleepMode(GPIO_LEAST_ACTIVE_SLEEPMODE); } /***************************************************************************//** diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c index 8e5b16c873b..608c5c7c2e2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c @@ -28,10 +28,10 @@ #if DEVICE_I2C #include "mbed_assert.h" +#include "mbed_sleep.h" #include "i2c_api.h" #include "PeripheralPins.h" #include "pinmap_function.h" -#include "sleepmodes.h" #include "em_i2c.h" #include "em_cmu.h" @@ -508,7 +508,7 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer)); if(retval == i2cTransferInProgress) { - blockSleepMode(EM1); + sleep_manager_lock_deep_sleep(); } else { // something happened, and the transfer did not go through // So, we need to clean up @@ -541,7 +541,7 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj) // Disable interrupt i2c_enable_interrupt(obj, 0, false); - unblockSleepMode(EM1); + sleep_manager_unlock_deep_sleep(); return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events; case i2cTransferNack: @@ -549,7 +549,7 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj) // Disable interrupt i2c_enable_interrupt(obj, 0, false); - unblockSleepMode(EM1); + sleep_manager_unlock_deep_sleep(); return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events; default: @@ -557,7 +557,7 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj) // Disable interrupt i2c_enable_interrupt(obj, 0, false); - unblockSleepMode(EM1); + sleep_manager_unlock_deep_sleep(); // return error return I2C_EVENT_ERROR & obj->i2c.events; @@ -578,19 +578,19 @@ uint8_t i2c_active(i2c_t *obj) */ void i2c_abort_asynch(i2c_t *obj) { - // Do not deactivate I2C twice - if (!i2c_active(obj)) return; - // Disable interrupt i2c_enable_interrupt(obj, 0, false); + // Do not deactivate I2C twice + if (!i2c_active(obj)) return; + // Abort obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT; // Block until free while(i2c_active(obj)); - unblockSleepMode(EM1); + sleep_manager_unlock_deep_sleep(); } #endif //DEVICE_I2C ASYNCH diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c index 684ed188c90..9c08b320905 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c @@ -25,14 +25,25 @@ #include "clocking.h" #if DEVICE_LOWPOWERTIMER +/******************************************************************************* + * The Silicon Labs lp_ticker implementation is mapped on top of an extended RTC + * API, since the RTC is available in the lowest energy modes. By default, the + * RTC counter is configured to run at 4kHz, giving us a quarter-ms resolution + * for the low power timer, which should be good enough for a low power use + * case. + * + * On Silicon Labs devices, the lowest width RTC implementation has a 24-bit + * counter, which gets extended with a further 32-bit software counter. This + * gives 56 bits of actual width, which with the default speed maps to + * 557462 years before the extended RTC counter wraps around. We are pretty + * certain no device is going to have that amount of uptime. + * (At max speed the wraparound is at 69730 years, which is unlikely as well) + ******************************************************************************/ + #include "rtc_api.h" #include "rtc_api_HAL.h" #include "lp_ticker_api.h" - #include "mbed_critical.h" -#if (defined RTCC_COUNT) && (RTCC_COUNT > 0) -#include "em_rtcc.h" -#endif static int rtc_reserved = 0; @@ -57,135 +68,55 @@ void lp_ticker_free() } } -#ifndef RTCC_COUNT - -/* RTC API */ - void lp_ticker_set_interrupt(timestamp_t timestamp) { - uint64_t timestamp_ticks; - uint64_t current_ticks = RTC_CounterGet(); - timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)); - - /* Initialize RTC */ - lp_ticker_init(); + uint64_t rtc_compare_value; + uint64_t current_ticks = rtc_get_full(); + timestamp_t current_time = lp_ticker_read(); /* calculate offset value */ timestamp_t offset = timestamp - current_time; - if(offset > 0xEFFFFFFF) offset = 100; - - /* map offset to RTC value */ - // ticks = offset * RTC frequency div 1000000 - timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000; - timestamp_ticks += current_ticks; - - /* RTC has 24 bit resolution */ - timestamp_ticks &= 0xFFFFFF; - - /* check for RTC limitation */ - if((timestamp_ticks - RTC_CounterGet()) >= 0x800000) timestamp_ticks = RTC_CounterGet() + 2; - /* Set callback */ - RTC_FreezeEnable(true); - RTC_CompareSet(0, (uint32_t)timestamp_ticks); - RTC_IntEnable(RTC_IF_COMP0); - RTC_FreezeEnable(false); -} - -void lp_ticker_fire_interrupt(void) -{ - RTC_IntSet(RTC_IFS_COMP0); -} - -inline void lp_ticker_disable_interrupt() -{ - RTC_IntDisable(RTC_IF_COMP0); -} - -inline void lp_ticker_clear_interrupt() -{ - RTC_IntClear(RTC_IF_COMP0); -} - -timestamp_t lp_ticker_read() -{ - lp_ticker_init(); - - uint64_t ticks_temp; - uint64_t ticks = RTC_CounterGet(); - - /* ticks = counter tick value - * timestamp = value in microseconds - * timestamp = ticks * 1.000.000 / RTC frequency - */ - - ticks_temp = (ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT); - return (timestamp_t) (ticks_temp & 0xFFFFFFFF); -} - -#else - -/* RTCC API */ - -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - uint64_t timestamp_ticks; - uint64_t current_ticks = RTCC_CounterGet(); - timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)); - - /* Initialize RTC */ - lp_ticker_init(); - - /* calculate offset value */ - timestamp_t offset = timestamp - current_time; - if(offset > 0xEFFFFFFF) offset = 100; + /* If the requested timestamp is too far in the future, we might not be able + * to set the interrupt accurately due to potentially having ticked between + * calculating the timestamp to set and us calculating the offset. */ + if(offset > 0xFFFF0000) offset = 100; /* map offset to RTC value */ // ticks = offset * RTC frequency div 1000000 - timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000; - // checking the rounding. If timeout is wanted between RTCC ticks, irq should be configured to - // trigger in the latter RTCC-tick. Otherwise ticker-api fails to send timer event to its client - if(((timestamp_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) < offset){ - timestamp_ticks++; - } - - timestamp_ticks += current_ticks; + rtc_compare_value = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000; - /* RTCC has 32 bit resolution */ - timestamp_ticks &= 0xFFFFFFFF; + /* If RTC offset is less then 2 RTC ticks, the interrupt won't fire */ + if(rtc_compare_value < 2) { + rtc_compare_value = 2; + } - /* check for RTCC limitation */ - if((timestamp_ticks - RTCC_CounterGet()) >= 0x80000000) timestamp_ticks = RTCC_CounterGet() + 2; + rtc_compare_value += current_ticks; - /* init channel */ - RTCC_CCChConf_TypeDef ccchConf = RTCC_CH_INIT_COMPARE_DEFAULT; - RTCC_ChannelInit(0,&ccchConf); - /* Set callback */ - RTCC_ChannelCCVSet(0, (uint32_t)timestamp_ticks); - RTCC_IntEnable(RTCC_IF_CC0); + rtc_set_comp0_value(rtc_compare_value, true); } -void lp_ticker_fire_interrupt(void) +inline void lp_ticker_fire_interrupt(void) { - RTCC_IntSet(RTCC_IFS_CC0); + rtc_force_comp0(); } inline void lp_ticker_disable_interrupt() { - RTCC_IntDisable(RTCC_IF_CC0); + rtc_enable_comp0(false); } inline void lp_ticker_clear_interrupt() { - RTCC_IntClear(RTCC_IF_CC0); + /* No need to clear interrupt flag, since that already happens at RTC level */ } timestamp_t lp_ticker_read() { lp_ticker_init(); - + uint64_t ticks_temp; - uint64_t ticks = RTCC_CounterGet(); + uint64_t ticks = rtc_get_full(); /* ticks = counter tick value * timestamp = value in microseconds @@ -196,6 +127,4 @@ timestamp_t lp_ticker_read() return (timestamp_t) (ticks_temp & 0xFFFFFFFF); } -#endif /* RTCC */ - #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c index 85812e2bef1..5ad3b9714c4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c @@ -26,11 +26,11 @@ #if DEVICE_PWMOUT #include "mbed_assert.h" +#include "mbed_sleep.h" #include "pwmout_api.h" #include "pinmap.h" #include "PeripheralPins.h" #include "device_peripherals.h" -#include "sleepmodes.h" #include "em_cmu.h" #include "em_gpio.h" @@ -180,7 +180,7 @@ void pwmout_init(pwmout_t *obj, PinName pin) return; } else { pwmout_set_channel_route(pwmout_get_channel_route(obj->channel)); - blockSleepMode(EM1); + sleep_manager_lock_deep_sleep(); pwmout_enable(obj, true); pwmout_enable_pins(obj, true); } @@ -226,7 +226,7 @@ void pwmout_free(pwmout_t *obj) { if(pwmout_disable_channel_route(pwmout_get_channel_route(obj->channel))) { //Channel was previously enabled, so do housekeeping - unblockSleepMode(EM1); + sleep_manager_unlock_deep_sleep(); } else { //This channel was disabled already } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c index 1b8919c8037..81e64cbc00d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c @@ -28,7 +28,6 @@ #include "rtc_api_HAL.h" #include "em_cmu.h" #include "sleep_api.h" -#include "sleepmodes.h" #if (defined RTC_COUNT) && (RTC_COUNT > 0) #include "em_rtc.h" @@ -38,19 +37,21 @@ #include "em_rtcc.h" #endif -static bool rtc_inited = false; -static time_t time_base = 0; -static uint32_t useflags = 0; -static uint32_t time_extend = 0; +static bool rtc_inited = false; +static bool rtc_cancelled = false; +static time_t time_base = 0; +static uint32_t useflags = 0; +static uint32_t time_extend = 0; +static uint32_t extended_comp0 = 0; -static void (*comp0_handler)(void) = NULL; - -#ifndef RTCC_COUNT +static void (*comp0_handler)(void) = NULL; +#ifndef RTCC_PRESENT /* Using RTC API */ -#define RTC_LEAST_ACTIVE_SLEEPMODE EM2 -#define RTC_NUM_BITS (24) +#if RTC_CLOCKDIV_INT > 16 +#error invalid prescaler value RTC_CLOCKDIV_INT, since LP ticker resolution will exceed 1ms. +#endif void RTC_IRQHandler(void) { @@ -63,24 +64,31 @@ void RTC_IRQHandler(void) } if (flags & RTC_IF_COMP0) { RTC_IntClear(RTC_IF_COMP0); - if (comp0_handler != NULL) { + if (comp0_handler != NULL && ((time_extend == extended_comp0) || (rtc_cancelled))) { + rtc_cancelled = false; comp0_handler(); } } } -uint32_t rtc_get_32bit(void) -{ - uint32_t pending = (RTC_IntGet() & RTC_IF_OF) ? 1 : 0; - return (RTC_CounterGet() + ((time_extend + pending) << RTC_NUM_BITS)); -} - uint64_t rtc_get_full(void) { uint64_t ticks = 0; - ticks += time_extend; - ticks = ticks << RTC_NUM_BITS; - ticks += RTC_CounterGet(); + + do + { + ticks = RTC_CounterGet(); + + if (RTC_IntGet() & RTC_IF_OF) { + RTC_IntClear(RTC_IF_OF); + /* RTC has overflowed in a critical section, so handle the overflow here */ + time_extend += 1; + } + + ticks += (uint64_t)time_extend << RTC_BITS; + } + while ( (ticks & RTC_MAX_VALUE) != RTC_CounterGet() ); + return ticks; } @@ -111,7 +119,6 @@ void rtc_init_real(uint32_t flags) /* Initialize */ RTC_Init(&init); - blockSleepMode(RTC_LEAST_ACTIVE_SLEEPMODE); rtc_inited = true; } } @@ -131,17 +138,42 @@ void rtc_free_real(uint32_t flags) NVIC_DisableIRQ(RTC_IRQn); RTC_Reset(); CMU_ClockEnable(cmuClock_RTC, false); - unblockSleepMode(RTC_LEAST_ACTIVE_SLEEPMODE); rtc_inited = false; } } -#else +void rtc_enable_comp0(bool enable) +{ + RTC_FreezeEnable(true); + if (!enable) { + RTC_IntDisable(RTC_IF_COMP0); + } else { + RTC_IntEnable(RTC_IF_COMP0); + } + RTC_FreezeEnable(false); +} -/* Using RTCC API */ +void rtc_set_comp0_value(uint64_t value, bool enable) +{ + rtc_enable_comp0(false); + + /* Set callback */ + RTC_FreezeEnable(true); + extended_comp0 = (uint32_t) (value >> RTC_BITS); + RTC_CompareSet(0, (uint32_t) (value & RTC_MAX_VALUE)); + RTC_FreezeEnable(false); -#define RTCC_LEAST_ACTIVE_SLEEPMODE EM2 -#define RTCC_NUM_BITS (32) + rtc_enable_comp0(enable); +} + +void rtc_force_comp0(void) +{ + rtc_cancelled = true; + RTC_IntSet(RTC_IFS_COMP0); +} + +#else +/* Using RTCC API */ void RTCC_IRQHandler(void) { @@ -156,23 +188,30 @@ void RTCC_IRQHandler(void) if (flags & RTCC_IF_CC0) { RTCC_IntClear(RTCC_IF_CC0); - if (comp0_handler != NULL) { + if (comp0_handler != NULL && ((time_extend == extended_comp0) || (rtc_cancelled))) { comp0_handler(); } } } -uint32_t rtc_get_32bit(void) -{ - return RTCC_CounterGet(); -} - uint64_t rtc_get_full(void) { uint64_t ticks = 0; - ticks += time_extend; - ticks = ticks << RTCC_NUM_BITS; - ticks += RTCC_CounterGet(); + + do + { + ticks = RTCC_CounterGet(); + + if (RTCC_IntGet() & RTCC_IF_OF) { + RTCC_IntClear(RTCC_IF_OF); + /* RTCC has overflowed in critical section, so handle the rollover here */ + time_extend += 1; + } + + ticks += (uint64_t)time_extend << RTC_BITS; + } + while ( (ticks & RTC_MAX_VALUE) != RTCC_CounterGet() ); + return ticks; } @@ -191,10 +230,18 @@ void rtc_init_real(uint32_t flags) init.enable = 1; init.precntWrapOnCCV0 = false; init.cntWrapOnCCV1 = false; -#if RTC_CLOCKDIV_INT == 8 +#if RTC_CLOCKDIV_INT == 1 + init.presc = rtccCntPresc_1; +#elif RTC_CLOCKDIV_INT == 2 + init.presc = rtccCntPresc_2; +#elif RTC_CLOCKDIV_INT == 4 + init.presc = rtccCntPresc_4; +#elif RTC_CLOCKDIV_INT == 8 init.presc = rtccCntPresc_8; +#elif RTC_CLOCKDIV_INT == 16 + init.presc = rtccCntPresc_16; #else -#error invalid prescaler value RTC_CLOCKDIV_INT +#error invalid prescaler value RTC_CLOCKDIV_INT, since LP ticker resolution will exceed 1ms. #endif /* Enable Interrupt from RTC */ @@ -204,8 +251,6 @@ void rtc_init_real(uint32_t flags) /* Initialize */ RTCC_Init(&init); - - blockSleepMode(RTCC_LEAST_ACTIVE_SLEEPMODE); rtc_inited = true; } } @@ -225,11 +270,39 @@ void rtc_free_real(uint32_t flags) NVIC_DisableIRQ(RTCC_IRQn); RTCC_Reset(); CMU_ClockEnable(cmuClock_RTCC, false); - unblockSleepMode(RTCC_LEAST_ACTIVE_SLEEPMODE); rtc_inited = false; } } +void rtc_enable_comp0(bool enable) +{ + if(!enable) { + RTCC_IntDisable(RTCC_IF_CC0); + } else { + RTCC_IntEnable(RTCC_IF_CC0); + } +} + +void rtc_set_comp0_value(uint64_t value, bool enable) +{ + rtc_enable_comp0(false); + + /* init channel */ + RTCC_CCChConf_TypeDef ccchConf = RTCC_CH_INIT_COMPARE_DEFAULT; + RTCC_ChannelInit(0,&ccchConf); + /* Set callback */ + extended_comp0 = (uint32_t) (value >> RTC_BITS); + RTCC_ChannelCCVSet(0, (uint32_t) (value & RTC_MAX_VALUE)); + + rtc_enable_comp0(enable); +} + +void rtc_force_comp0(void) +{ + rtc_cancelled = true; + RTCC_IntSet(RTCC_IFS_CC0); +} + #endif /* RTCC_COUNT */ void rtc_set_comp0_handler(uint32_t handler) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h index a265e13e470..702c42ccd76 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h @@ -26,15 +26,18 @@ #include #include "rtc_api.h" -#include "em_rtc.h" +#include "clocking.h" -#define RTC_CLOCKDIV cmuClkDiv_8 -#define RTC_CLOCKDIV_INT 8 -#define RTC_FREQ_SHIFT 12 +#define RTC_INIT_LPTIMER (1U << 1) +#define RTC_INIT_RTC (1U << 0) - -#define RTC_INIT_LPTIMER (1 << 1) -#define RTC_INIT_RTC (1 << 0) +#if defined(RTCC_PRESENT) +#define RTC_BITS (32U) +#define RTC_MAX_VALUE (0xFFFFFFFFUL) +#elif defined(RTC_PRESENT) +#define RTC_BITS (24U) +#define RTC_MAX_VALUE (0xFFFFFFUL) +#endif #ifdef __cplusplus extern "C" { @@ -42,6 +45,11 @@ extern "C" { /* Purpose of this file: extend rtc_api.h to include EFM-specific stuff*/ void rtc_set_comp0_handler(uint32_t handler); +void rtc_enable_comp0(bool enable); +void rtc_set_comp0_value(uint64_t value, bool enable); +void rtc_force_comp0(void); + +uint64_t rtc_get_full(void); void rtc_init_real(uint32_t flags); void rtc_free_real(uint32_t flags); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index c5f2227dce8..987ee98375c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -26,6 +26,7 @@ #if DEVICE_SERIAL #include "mbed_assert.h" +#include "mbed_sleep.h" #include "serial_api.h" #include "serial_api_HAL.h" #include @@ -44,10 +45,6 @@ #include "dma_api.h" #include "sleep_api.h" #include "buffer.h" -#include "sleepmodes.h" - -#define SERIAL_LEAST_ACTIVE_SLEEPMODE EM1 -#define SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART EM2 /** Validation of LEUART register block pointer reference * for assert statements. */ @@ -2239,13 +2236,11 @@ static void serial_unblock_sleep(serial_t *obj) { if( obj->serial.sleep_blocked > 0 ) { #ifdef LEUART_USING_LFXO - if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){ - unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART); - }else{ - unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + if(!LEUART_REF_VALID(obj->serial.periph.leuart) || (LEUART_BaudrateGet(obj->serial.periph.leuart) > (LEUART_LF_REF_FREQ/2))){ + sleep_manager_unlock_deep_sleep(); } #else - unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_unlock_deep_sleep(); #endif obj->serial.sleep_blocked--; } @@ -2255,13 +2250,13 @@ static void serial_block_sleep(serial_t *obj) { obj->serial.sleep_blocked++; #ifdef LEUART_USING_LFXO - if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){ - blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART); - }else{ - blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + if(!LEUART_REF_VALID(obj->serial.periph.leuart) || (LEUART_BaudrateGet(obj->serial.periph.leuart) > (LEUART_LF_REF_FREQ/2))){ + /* LEUART configured to a baudrate triggering the use of HFCLK, so prevent HFCLK from getting turned off */ + sleep_manager_lock_deep_sleep(); } #else - blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + /* HFCLK unavailable in deepsleep */ + sleep_manager_lock_deep_sleep(); #endif } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c index 39827f189c6..d789977d0f0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c @@ -25,32 +25,15 @@ #if DEVICE_SLEEP #include "sleep_api.h" -#include "sleepmodes.h" #include "em_emu.h" -#include "mbed_critical.h" - -uint32_t sleep_block_counter[NUM_SLEEP_MODES] = {0}; /** * Sleep mode. - * Enter the lowest possible sleep mode that is not blocked by ongoing activity. + * Stop the core clock using a WFI. */ void hal_sleep(void) { - if (sleep_block_counter[0] > 0) { - /* Blocked everything below EM0, so just return */ - return; - } else if (sleep_block_counter[1] > 0) { - /* Blocked everything below EM1, enter EM1 */ - EMU_EnterEM1(); - } else if (sleep_block_counter[2] > 0) { - /* Blocked everything below EM2, enter EM2 */ - EMU_EnterEM2(true); - } else { - /* Blocked everything below EM3, enter EM3 */ - EMU_EnterEM3(true); - } /* Never enter EM4, as mbed has no way of configuring EM4 wakeup */ - return; + EMU_EnterEM1(); } /** @@ -69,35 +52,4 @@ void hal_deepsleep(void) EMU_EnterEM2(true); } -/** Block the microcontroller from sleeping below a certain mode - * - * This will block sleep() from entering an energy mode below the one given. - * -- To be called by peripheral HAL's -- - * - * After the peripheral is finished with the operation, it should call unblock with the same state - * - */ -void blockSleepMode(sleepstate_enum minimumMode) -{ - core_util_critical_section_enter(); - sleep_block_counter[minimumMode]++; - core_util_critical_section_exit(); -} - -/** Unblock the microcontroller from sleeping below a certain mode - * - * This will unblock sleep() from entering an energy mode below the one given. - * -- To be called by peripheral HAL's -- - * - * This should be called after all transactions on a peripheral are done. - */ -void unblockSleepMode(sleepstate_enum minimumMode) -{ - core_util_critical_section_enter(); - if(sleep_block_counter[minimumMode] > 0) { - sleep_block_counter[minimumMode]--; - } - core_util_critical_section_exit(); -} - #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h deleted file mode 100644 index 31ff5930da5..00000000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file sleepmodes.h - ******************************************************************************* - * @section License - * (C) Copyright 2015 Silicon Labs, http://www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef MBED_SLEEPMODES_H -#define MBED_SLEEPMODES_H - -#include "em_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* -* Blocks all sleepmodes below the one passed as argument -* -* @param minimumMode The lowest-power sleep mode which must remain active -*/ -void blockSleepMode(sleepstate_enum minimumMode); - -/* -* Unblocks a previously-blocked sleep mode -* -*@param minimumMode The same sleepmode that was previously passed to blockSleepMode -*/ -void unblockSleepMode(sleepstate_enum minimumMode); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c index b2306c60c7f..e832536ed20 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c @@ -26,6 +26,7 @@ #if DEVICE_SPI #include "mbed_assert.h" +#include "mbed_sleep.h" #include "PeripheralPins.h" #include "pinmap.h" #include "pinmap_function.h" @@ -39,12 +40,9 @@ #include "em_cmu.h" #include "em_dma.h" #include "sleep_api.h" -#include "sleepmodes.h" static uint16_t fill_word = SPI_FILL_WORD; -#define SPI_LEAST_ACTIVE_SLEEPMODE EM1 - static inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj) { switch ((int)obj->spi.spi) { @@ -1188,7 +1186,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, spi_enable_event(obj, event, true); // Set the sleep mode - blockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_lock_deep_sleep(); /* And kick off the transfer */ spi_master_transfer_dma(obj, tx, rx, tx_length, rx_length, (void*)handler, hint); @@ -1244,7 +1242,7 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) /* Wait transmit to complete, before user code is indicated*/ while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); - unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_unlock_deep_sleep(); /* return to CPP land to say we're finished */ return SPI_EVENT_COMPLETE; } else { @@ -1262,7 +1260,7 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) /* disable interrupts */ spi_enable_interrupt(obj, (uint32_t)NULL, false); - unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_unlock_deep_sleep(); /* Return the event back to userland */ return event; } @@ -1370,7 +1368,7 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) /* Wait for transmit to complete, before user code is indicated */ while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); - unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_unlock_deep_sleep(); /* return to CPP land to say we're finished */ return SPI_EVENT_COMPLETE; @@ -1391,7 +1389,7 @@ uint32_t spi_irq_handler_asynch(spi_t* obj) /* Wait for transmit to complete, before user code is indicated */ while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); - unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_unlock_deep_sleep(); /* Return the event back to userland */ return event; @@ -1433,7 +1431,7 @@ void spi_abort_asynch(spi_t *obj) } // Release sleep mode block - unblockSleepMode(SPI_LEAST_ACTIVE_SLEEPMODE); + sleep_manager_unlock_deep_sleep(); } #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c index efee1824f94..74ac081768d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c @@ -28,10 +28,7 @@ #include "em_cmu.h" #include "em_timer.h" #include "clocking.h" -#include "sleep_api.h" -#include "sleepmodes.h" -#define TIMER_LEAST_ACTIVE_SLEEPMODE EM1 /** * Timer functions for microsecond ticker. * mbed expects a 32-bit timer. Since the EFM32 only has 16-bit timers, @@ -159,10 +156,6 @@ void us_ticker_set_interrupt(timestamp_t timestamp) uint32_t goal = timestamp; uint32_t trigger; - if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) == 0) { - //Timer was disabled, but is going to be enabled. Set sleep mode. - blockSleepMode(TIMER_LEAST_ACTIVE_SLEEPMODE); - } TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0); /* convert us delta value back to timer ticks */ @@ -216,10 +209,6 @@ void us_ticker_fire_interrupt(void) void us_ticker_disable_interrupt(void) { - if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) != 0) { - //Timer was enabled, but is going to get disabled. Clear sleepmode. - unblockSleepMode(TIMER_LEAST_ACTIVE_SLEEPMODE); - } /* Disable compare channel interrupts */ TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0); } diff --git a/targets/targets.json b/targets/targets.json old mode 100755 new mode 100644 index f6d3f95f782..9916e1b7aa3 --- a/targets/targets.json +++ b/targets/targets.json @@ -622,7 +622,7 @@ }, "EV_COG_AD4050LZ": { "inherits": ["Target"], - "core": "Cortex-M4", + "core": "Cortex-M4F", "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"], "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"], @@ -691,7 +691,7 @@ "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"], "inherits": ["Target"], "detect_code": ["0217"], - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "MK82FN256xxx15" }, @@ -706,6 +706,12 @@ "extra_labels": ["STM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], + "config": { + "lse_available": { + "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used", + "value": "1" + } + }, "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"] }, "LPC54114": { @@ -738,7 +744,6 @@ "FF_LPC546XX": { "inherits": ["LPC546XX"], "extra_labels_remove" : ["LPCXpresso"], - "features_remove": ["LWIP"], "supported_form_factors": [""], "detect_code": ["8081"] }, @@ -775,7 +780,8 @@ } }, "detect_code": ["0791"], - "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "overrides": {"lse_available": 0}, + "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "device_has_add": ["SERIAL_FC"], "default_lib": "small", "release_versions": ["2"], @@ -795,7 +801,8 @@ } }, "detect_code": ["0785"], - "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "overrides": {"lse_available": 0}, + "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "device_has_add": ["CAN", "SERIAL_FC"], "default_lib": "small", "release_versions": ["2"], @@ -815,7 +822,7 @@ }, "detect_code": ["0755"], "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], - "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F070RB" }, @@ -833,7 +840,7 @@ }, "detect_code": ["0730"], "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F072RB" }, @@ -851,7 +858,7 @@ }, "detect_code": ["0750"], "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F091RC" }, @@ -873,7 +880,7 @@ } }, "detect_code": ["0700"], - "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH"], + "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F103RB" }, @@ -896,7 +903,7 @@ }, "detect_code": ["0835"], "macros_add": ["USBHOST_OTHER"], - "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC"], + "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], "device_name": "STM32F207ZG" @@ -924,7 +931,6 @@ "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"], - "macros_add": ["RTC_LSI=1"], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", @@ -932,6 +938,7 @@ "macro_name": "CLOCK_SOURCE" } }, + "overrides": {"lse_available": 0}, "detect_code": ["0775"], "default_lib": "small", "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"], @@ -951,7 +958,7 @@ } }, "detect_code": ["0745"], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F303RE" }, @@ -968,7 +975,7 @@ } }, "detect_code": ["0747"], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F303ZE" }, @@ -1004,7 +1011,7 @@ }, "detect_code": ["0720"], "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], - "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"], + "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH", "LOWPOWERTIMER"], "release_versions": ["2", "5"], "device_name": "STM32F401RE" }, @@ -1018,6 +1025,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0744"], @@ -1068,6 +1079,28 @@ "bootloader_supported": true }, "DISCO_F413ZH": { + "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 + } + }, + "detect_code": ["0743"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32F413ZH" + }, + "NUCLEO_F413ZH": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", @@ -1219,6 +1252,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "macros_add": ["USBHOST_OTHER"], @@ -1243,6 +1280,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"], @@ -1267,6 +1308,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "supported_form_factors": ["ARDUINO"], @@ -1289,6 +1334,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0780"], @@ -1308,6 +1357,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0790"], @@ -1326,6 +1379,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0715"], @@ -1344,6 +1401,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0760"], @@ -1378,12 +1439,39 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0770"], "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"], "release_versions": ["2", "5"], - "device_name": "STM32L432KC" + "device_name": "STM32L432KC", + "bootloader_supported": true + }, + "NUCLEO_L433RC_P": { + "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO", "MORPHO"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_MSI", + "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 + } + }, + "detect_code": ["0779"], + "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32L433RC", + "bootloader_supported": true }, "NUCLEO_L476RG": { "inherits": ["FAMILY_STM32"], @@ -1395,6 +1483,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0765"], @@ -1432,6 +1524,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0827"], @@ -1479,7 +1575,7 @@ "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F3", "STM32F303", "STM32F303xC", "STM32F303VC"], - "macros_add": ["RTC_LSI=1"], + "overrides": {"lse_available": 0}, "supported_toolchains": ["GCC_ARM"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"], "device_name": "STM32F303VC" @@ -1488,7 +1584,6 @@ "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F3", "STM32F334x8","STM32F334C8"], - "macros_add": ["RTC_LSI=1"], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", @@ -1496,6 +1591,7 @@ "macro_name": "CLOCK_SOURCE" } }, + "overrides": {"lse_available": 0}, "detect_code": ["0810"], "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"], "default_lib": "small", @@ -1506,9 +1602,18 @@ "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"], - "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], - "macros_add": ["RTC_LSI=1", "USB_STM_HAL"], + "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI", + "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "macros_add": ["USB_STM_HAL"], + "overrides": {"lse_available": 0}, "device_has_add": ["ANALOGOUT"], + "release_versions": ["2", "5"], "device_name": "STM32F407VG" }, "DISCO_F429ZI": { @@ -1527,7 +1632,8 @@ "macro_name": "CLOCK_SOURCE_USB" } }, - "macros_add": ["RTC_LSI=1", "USB_STM_HAL", "USBHOST_OTHER"], + "overrides": {"lse_available": 0}, + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F429ZI", @@ -1546,7 +1652,7 @@ } }, "detect_code": ["0788"], - "macros_add": ["USB_STM_HAL"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F469NI" @@ -1555,14 +1661,19 @@ "inherits": ["FAMILY_STM32"], "core": "Cortex-M0+", "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"], - "macros": ["RTC_LSI=1"], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 + } }, + "overrides": {"lse_available": 0}, "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "FLASH"], "default_lib": "small", "release_versions": ["2"], @@ -1578,6 +1689,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0833"], @@ -1599,9 +1714,14 @@ "usb_speed": { "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)", "value": "1" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0815"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], @@ -1617,9 +1737,14 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI", "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0817"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], @@ -1634,6 +1759,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "supported_form_factors": ["ARDUINO"], @@ -1653,6 +1782,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0820"], @@ -1701,7 +1834,8 @@ "macro_name": "MODEM_ON_BOARD_UART" } }, - "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000", "RTC_LSI=1"], + "overrides": {"lse_available": 0}, + "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"], "post_binary_hook": { "function": "MTSCode.combine_bins_mts_dragonfly", "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"] @@ -1710,6 +1844,47 @@ "release_versions": ["2", "5"], "device_name": "STM32F411RE" }, + "MTB_MTS_DRAGONFLY": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32F4", "STM32F411RE"], + "config": { + "modem_is_on_board": { + "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.", + "value": 1, + "macro_name": "MODEM_ON_BOARD" + }, + "modem_data_connection_type": { + "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.", + "value": 1, + "macro_name": "MODEM_ON_BOARD_UART" + }, + "usb_tx": { + "help": "Value PB_6", + "value": "PB_6" + }, + "usb_rx": { + "help": "Value PB_7", + "value": "PB_7" + }, + "stdio_uart": { + "help": "Value: UART_1", + "value": "UART_1", + "macro_name": "STDIO_UART" + } + }, + "overrides": { + "lse_available": 0 + }, + "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"], + "post_binary_hook": { + "function": "MTSCode.combine_bins_mtb_mts_dragonfly", + "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"] + }, + "release_versions": ["2", "5"], + "device_name": "STM32F411RE", + "bootloader_supported": true + }, "XDOT_L151CC": { "inherits": ["FAMILY_STM32"], "core": "Cortex-M3", @@ -1737,7 +1912,7 @@ "core": "Cortex-M3", "default_toolchain": "uARM", "extra_labels_add": ["STM32L1", "STM32L152RC"], - "macros": ["RTC_LSI=1"], + "overrides": {"lse_available": 0}, "detect_code": ["4100"], "device_has_add": ["ANALOGOUT"], "default_lib": "small", @@ -1769,18 +1944,13 @@ "supported_form_factors": ["ARDUINO"], "release_versions": ["5"], "config": { - "usb_tx": { + "stdio_uart_tx": { "help": "Value: D8(default) or D1", "value": "D8" }, - "usb_rx": { + "stdio_uart_rx": { "help": "Value: D2(default) or D0", "value": "D2" - }, - "stdio_uart": { - "help": "Value: UART_1(default) or UART_3", - "value": "UART_1", - "macro_name": "STDIO_UART" } } }, @@ -1788,21 +1958,20 @@ "inherits": ["MODULE_UBLOX_ODIN_W2"], "release_versions": ["5"], "config": { - "usb_tx": { + "stdio_uart_tx": { "help": "Value: PA_9(default) or PD_8", "value": "PA_9" }, - "usb_rx": { + "stdio_uart_rx": { "help": "Value: PA_10(default) or PD_9", "value": "PA_10" - }, - "stdio_uart": { - "help": "Value: UART_1(default) or UART_3", - "value": "UART_1", - "macro_name": "STDIO_UART" } } }, + "MTB_UBLOX_ODIN_W2": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "release_versions": ["5"] + }, "UBLOX_C030": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], @@ -1821,7 +1990,8 @@ "macro_name": "MODEM_ON_BOARD_UART" } }, - "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"], + "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=12000000", "GNSSBAUD=9600"], + "overrides": {"lse_available": 0}, "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"], "features": ["LWIP"], "public": false, @@ -1842,7 +2012,7 @@ "default_toolchain": "uARM", "program_cycle_s": 1.5, "extra_labels_add": ["STM32L1", "STM32L151RC"], - "macros": ["RTC_LSI=1"], + "overrides": {"lse_available": 0}, "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], "device_has_add": ["ANALOGOUT"], "default_lib": "small", @@ -2357,28 +2527,25 @@ "features": ["BLE"], "release_versions": ["2", "5"] }, - "RZ_A1H": { - "supported_form_factors": ["ARDUINO"], + "RZ_A1XX": { + "inherits": ["Target"], "core": "Cortex-A9", - "program_cycle_s": 2, - "extra_labels": ["RENESAS", "MBRZA1H"], "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], - "inherits": ["Target"], + "extra_labels": ["RENESAS", "RZ_A1XX"], "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "features": ["LWIP"], - "release_versions": ["2"] + "program_cycle_s": 2 + }, + "RZ_A1H": { + "inherits": ["RZ_A1XX"], + "supported_form_factors": ["ARDUINO"], + "extra_labels_add": ["RZA1H", "MBRZA1H"], + "release_versions": ["2", "5"] }, "VK_RZ_A1H": { - "inherits": ["Target"], - "core": "Cortex-A9", - "extra_labels": ["RENESAS", "VKRZA1H"], - "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], - "default_toolchain": "ARM", - "program_cycle_s": 2, - "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"], - "features": ["LWIP"], - "default_lib": "std", - "release_versions": ["2"] + "inherits": ["RZ_A1XX"], + "extra_labels": ["RZA1H", "VKRZA1H"], + "release_versions": [] }, "MAXWSNENV": { "inherits": ["Target"], @@ -2873,6 +3040,7 @@ "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], + "device_name": "EFM32PG12B500F1024GL125", "public": false, "bootloader_supported": true }, @@ -2925,11 +3093,13 @@ "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], + "device_name": "EFR32MG12P332F1024GL125", "public": false, "bootloader_supported": true }, "TB_SENSE_12": { "inherits": ["EFR32MG12P332F1024GL125"], + "device_name": "EFR32MG12P332F1024GL125", "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"], "forced_reset_timeout": 5, "config": { @@ -3197,7 +3367,7 @@ "MCU_NRF52840": { "inherits": ["Target"], "core": "Cortex-M4F", - "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"], "device_has": ["STCLK_OFF_DURING_SLEEP"], "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"], "OUTPUT_EXT": "hex", @@ -3239,7 +3409,8 @@ "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"], "device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"], "release_versions": ["2", "5"], - "device_name": "nRF52840_xxAA" + "device_name": "nRF52840_xxAA", + "bootloader_supported": true }, "BLUEPILL_F103C8": { "inherits": ["FAMILY_STM32"], @@ -3426,23 +3597,31 @@ "VBLUNO51_LEGACY": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "extra_labels_add": ["VBLUNO51"] }, "VBLUNO51_BOOT": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K_BOOT"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "extra_labels_add": ["VBLUNO51"], "macros_add": ["TARGET_VBLUNO51"] }, "VBLUNO51_OTA": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K_OTA"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "extra_labels_add": ["VBLUNO51"], "macros_add": ["TARGET_VBLUNO51"] }, "VBLUNO51": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K_UNIFIED"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2"], "device_name": "nRF51822_xxAC" @@ -3457,6 +3636,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0823"], diff --git a/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin b/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin new file mode 100644 index 00000000000..e5c640df1c3 Binary files /dev/null and b/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin differ diff --git a/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin b/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin index 0ca1906689f..5179455fb5b 100644 Binary files a/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin and b/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin differ diff --git a/tools/build_api.py b/tools/build_api.py index cbe2f8d2531..1ed66530816 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -441,13 +441,6 @@ def scan_resources(src_paths, toolchain, dependencies_paths=None, if (hasattr(toolchain.target, "release_versions") and "5" not in toolchain.target.release_versions and "rtos" in toolchain.config.lib_config_data): - if "Cortex-A" in toolchain.target.core: - raise NotSupportedException( - ("%s Will be supported in mbed OS 5.6. " - "To use the %s, please checkout the mbed OS 5.4 release branch. " - "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice " - "for more information") % (toolchain.target.name, toolchain.target.name)) - else: raise NotSupportedException("Target does not support mbed OS 5") return resources @@ -1006,19 +999,6 @@ def build_mbed_libs(target, toolchain_name, verbose=False, config.add_config_files([MBED_CONFIG_FILE]) toolchain.set_config_data(toolchain.config.get_config_data()) - # CMSIS - toolchain.info("Building library %s (%s, %s)" % - ('CMSIS', target.name, toolchain_name)) - cmsis_src = MBED_CMSIS_PATH - resources = toolchain.scan_resources(cmsis_src) - - toolchain.copy_files(resources.headers, build_target) - toolchain.copy_files(resources.linker_script, build_toolchain) - toolchain.copy_files(resources.bin_files, build_toolchain) - - objects = toolchain.compile_sources(resources, tmp_path) - toolchain.copy_files(objects, build_toolchain) - # mbed toolchain.info("Building library %s (%s, %s)" % ('MBED', target.name, toolchain_name)) @@ -1034,9 +1014,12 @@ def build_mbed_libs(target, toolchain_name, verbose=False, toolchain.copy_files(resources.headers, dest) library_incdirs.append(dest) - # Target specific sources - hal_src = MBED_TARGETS_PATH - hal_implementation = toolchain.scan_resources(hal_src) + cmsis_implementation = toolchain.scan_resources(MBED_CMSIS_PATH) + toolchain.copy_files(cmsis_implementation.headers, build_target) + toolchain.copy_files(cmsis_implementation.linker_script, build_toolchain) + toolchain.copy_files(cmsis_implementation.bin_files, build_toolchain) + + hal_implementation = toolchain.scan_resources(MBED_TARGETS_PATH) toolchain.copy_files(hal_implementation.headers + hal_implementation.hex_files + hal_implementation.libraries + @@ -1045,8 +1028,8 @@ def build_mbed_libs(target, toolchain_name, verbose=False, toolchain.copy_files(hal_implementation.linker_script, build_toolchain) toolchain.copy_files(hal_implementation.bin_files, build_toolchain) incdirs = toolchain.scan_resources(build_target).inc_dirs - objects = toolchain.compile_sources(hal_implementation, - library_incdirs + incdirs) + objects = toolchain.compile_sources(cmsis_implementation + hal_implementation, + library_incdirs + incdirs + [tmp_path]) toolchain.copy_files(objects, build_toolchain) # Common Sources diff --git a/tools/build_travis.py b/tools/build_travis.py index 395dbd593a1..370282f0835 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -22,303 +22,383 @@ import os import sys +from argparse import ArgumentParser + ################################################################################ # Configure builds here # "libs" can contain "dsp", "usb" -build_list = ( - { "target": "LPC1768", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "LPC11U24", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "OC_MBUINO", "toolchains": "GCC_ARM", "libs": [] }, - - { "target": "LPC11U24_301", "toolchains": "GCC_ARM", "libs": [] }, - - { "target": "B96B_F446VE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L053R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L152RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F030R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F042K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F070RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F072RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F091RC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM" }, - { "target": "NUCLEO_F207ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F303K8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F303RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F303ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F410RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F412ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L432KC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L476RG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L011K4", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_L073RZ", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NUCLEO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F446RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F446ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F746ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_F767ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUCLEO_L496ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "MOTE_L152RC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "ELMO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "MTS_MDOT_F405RG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "MTS_MDOT_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "MTS_DRAGONFLY_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "ARCH_MAX", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "DISCO_F051R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F303VC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F334C8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F401VC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "DISCO_F407VG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "DISCO_F413ZH", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F469NI", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F746NG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_F769NI", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DISCO_L475VG_IOT01A", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "DISCO_L476VG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "DISCO_L072CZ_LRWAN1", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - - { "target": "LPC1114", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "LPC11U35_401", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "UBLOX_C027", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "LPC11U35_501", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "LPC11U68", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "LPC11U37H_401", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "KL05Z", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "KL25Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "KL27Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "KL43Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "KL46Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "K20D50M", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "TEENSY3_1", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "K64F", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "K22F", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "LPC4088", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "ARCH_PRO", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "LPC1549", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NRF51822", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "DELTA_DFCM_NNN40", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NRF51_DK", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "NRF51_MICROBIT", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "EFM32ZG_STK3200", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "EFM32HG_STK3400", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "EFM32LG_STK3600", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "EFM32GG_STK3700", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "EFM32WG_STK3800", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "EFM32PG_STK3401", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "MAXWSNENV", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "MAX32600MBED", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "MAX32620HSP", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "SAMR21G18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "SAMD21J18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "SAMD21G18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - { "target": "SAML21J18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, - - { "target": "NUMAKER_PFM_NUC472", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUMAKER_PFM_M453", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - { "target": "NUMAKER_PFM_M487", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, - ) +build_list = [ + { + "STM": + ( + { "target": "B96B_F446VE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L053R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L152RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F030R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F042K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F070RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F072RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F091RC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM" }, + { "target": "NUCLEO_F207ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F303K8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F303RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F303ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F410RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F412ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F413ZH", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_L432KC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L476RG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L011K4", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L073RZ", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F446RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F446ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F746ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_F767ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_L496ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + + { "target": "MOTE_L152RC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + + { "target": "ELMO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + + { "target": "MTS_MDOT_F405RG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "MTS_MDOT_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "MTS_DRAGONFLY_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "ARCH_MAX", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + + { "target": "DISCO_F051R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F303VC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F334C8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F401VC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + + { "target": "DISCO_F407VG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "DISCO_F413ZH", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F469NI", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F746NG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_F769NI", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DISCO_L475VG_IOT01A", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "DISCO_L476VG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "DISCO_L072CZ_LRWAN1", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + ), + }, + + { + "NXP": + ( + { "target": "LPC1768", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "LPC11U24", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "OC_MBUINO", "toolchains": "GCC_ARM", "libs": [] }, + + { "target": "LPC11U24_301", "toolchains": "GCC_ARM", "libs": [] }, + { "target": "LPC1114", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "LPC11U35_401", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "UBLOX_C027", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "LPC11U35_501", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "LPC11U68", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "LPC11U37H_401", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "LPC1549", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "KL05Z", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "KL25Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "KL27Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "KL43Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "KL46Z", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "K20D50M", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "TEENSY3_1", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "K64F", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "K22F", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "LPC4088", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "ARCH_PRO", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + ) + }, + + { + "NORDIC": + ( + { "target": "NRF51822", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "DELTA_DFCM_NNN40", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NRF51_DK", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NRF51_MICROBIT", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + ) + }, + + { + "SILICON_LABS": + ( + { "target": "EFM32ZG_STK3200", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "EFM32HG_STK3400", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "EFM32LG_STK3600", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "EFM32GG_STK3700", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "EFM32WG_STK3800", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "EFM32PG_STK3401", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + ) + }, + + { + "MAXIM": + ( + { "target": "MAXWSNENV", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "MAX32600MBED", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "MAX32620HSP", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + ) + }, + + { + "ATMEL": + ( + { "target": "SAMR21G18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "SAMD21J18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "SAMD21G18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "SAML21J18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + ) + }, + + + { + "NUVOTON": + ( + { "target": "NUMAKER_PFM_NUC472", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUMAKER_PFM_M453", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUMAKER_PFM_M487", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + ) + }, + + + { + "RENESAS": + ( + { "target": "RZ_A1H", "toolchains": "GCC_ARM" }, + ) + } +] ################################################################################ # Configure example test building (linking against external mbed SDK libraries) linking_list = [ - {"target": "LPC1768", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_15", "MBED_16", "MBED_17"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "K64F", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "K22F", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "KL43Z", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F446RE", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F446ZE", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F401RE", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F411RE", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F412ZG", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - } - }, - {"target": "NUCLEO_F429ZI", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F207ZG", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F746ZG", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_F767ZI", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUCLEO_L476RG", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - } + { + "NXP": ( + {"target": "LPC1768", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_15", "MBED_16", "MBED_17"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "K64F", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "K22F", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "KL43Z", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + ) }, - {"target": "DISCO_F429ZI", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - } + + { + "STM": ( + {"target": "NUCLEO_F446RE", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F446ZE", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F401RE", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F411RE", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F412ZG", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + } + }, + {"target": "NUCLEO_F413ZH", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F429ZI", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F207ZG", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F746ZG", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_F767ZI", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUCLEO_L476RG", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + } + }, + {"target": "DISCO_F429ZI", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + } + }, + {"target": "DISCO_F407VG", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "DISCO_F413ZH", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + } + }, + {"target": "NUCLEO_F303ZE", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "DISCO_L475VG_IOT01A", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "DISCO_L476VG", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "DISCO_L072CZ_LRWAN1", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + } + }, + ) }, - {"target": "DISCO_F407VG", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "DISCO_F413ZH", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - } - }, - {"target": "NUCLEO_F303ZE", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], + { + "NUVOTON": ( + {"target": "NUMAKER_PFM_NUC472", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUMAKER_PFM_M453", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "NUMAKER_PFM_M487", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "usb" : ["USB_1", "USB_2" ,"USB_3"], + } } + ) }, - {"target": "DISCO_L475VG_IOT01A", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "DISCO_L476VG", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "DISCO_L072CZ_LRWAN1", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - } - }, - {"target": "NUMAKER_PFM_NUC472", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUMAKER_PFM_M453", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - }, - {"target": "NUMAKER_PFM_M487", - "toolchains": "GCC_ARM", - "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], - "usb" : ["USB_1", "USB_2" ,"USB_3"], - } - } - ] + { + "RENESAS": + ( + { + "target": "RZ_A1H", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + } + }, + ) + } +] ################################################################################ # Driver -def run_builds(dry_run): - for build in build_list: - toolchain_list = build["toolchains"] - if type(toolchain_list) != type([]): toolchain_list = [toolchain_list] - for toolchain in toolchain_list: - cmdline = "python tools/build.py -m %s -t %s -j 4 -c --silent "% (build["target"], toolchain) - libs = build.get("libs", []) - if libs: - cmdline = cmdline + " ".join(["--" + l for l in libs]) - print "Executing: " + cmdline - if not dry_run: - if os.system(cmdline) != 0: - sys.exit(1) - - -def run_test_linking(dry_run): +def run_builds(dry_run, vendor): + for vendor_list in build_list: + if vendor in vendor_list: + for build in vendor_list[vendor]: + toolchain_list = build["toolchains"] + if type(toolchain_list) != type([]): toolchain_list = [toolchain_list] + for toolchain in toolchain_list: + cmdline = "python tools/build.py -m %s -t %s -c --silent "% (build["target"], toolchain) + libs = build.get("libs", []) + if libs: + cmdline = cmdline + " ".join(["--" + l for l in libs]) + print "Executing: " + cmdline + if not dry_run: + if os.system(cmdline) != 0: + sys.exit(1) + + +def run_test_linking(dry_run, vendor): """ Function run make.py commands to build and link simple mbed SDK tests against few libraries to make sure there are no simple linking errors. """ - for link in linking_list: - toolchain_list = link["toolchains"] - if type(toolchain_list) != type([]): - toolchain_list = [toolchain_list] - for toolchain in toolchain_list: - tests = link["tests"] - # Call make.py for each test group for particular library - for test_lib in tests: - test_names = tests[test_lib] - test_lib_switch = "--" + test_lib if test_lib else "" - cmdline = "python tools/make.py -m %s -t %s -c --silent %s -n %s " % (link["target"], toolchain, test_lib_switch, ",".join(test_names)) - print "Executing: " + cmdline - if not dry_run: - if os.system(cmdline) != 0: - sys.exit(1) - -def run_test_testsuite(dry_run): + for vendor_list in linking_list: + if vendor in vendor_list: + for link in vendor_list[vendor]: + toolchain_list = link["toolchains"] + if type(toolchain_list) != type([]): + toolchain_list = [toolchain_list] + for toolchain in toolchain_list: + tests = link["tests"] + # Call make.py for each test group for particular library + for test_lib in tests: + test_names = tests[test_lib] + test_lib_switch = "--" + test_lib if test_lib else "" + cmdline = "python tools/make.py -m %s -t %s -c --silent %s -n %s " % (link["target"], toolchain, test_lib_switch, ",".join(test_names)) + print "Executing: " + cmdline + if not dry_run: + if os.system(cmdline) != 0: + sys.exit(1) + +def run_test_testsuite(dry_run, vendor): cmdline = "python tools/singletest.py --version" print "Executing: " + cmdline if not dry_run: @@ -326,6 +406,16 @@ def run_test_testsuite(dry_run): sys.exit(1) if __name__ == "__main__": - run_builds("-s" in sys.argv) - run_test_linking("-s" in sys.argv) - run_test_testsuite("-s" in sys.argv) + parser = ArgumentParser() + + parser.add_argument("--vendor", + metavar="vendor", + type=str.upper, + help="Select a vendor to run travis tests" + ) + + options = parser.parse_args() + + run_builds("-s" in sys.argv, options.vendor) + run_test_linking("-s" in sys.argv, options.vendor) + run_test_testsuite("-s" in sys.argv, options.vendor) diff --git a/tools/config/__init__.py b/tools/config/__init__.py index e6d888fda3c..ee491c99df9 100644 --- a/tools/config/__init__.py +++ b/tools/config/__init__.py @@ -372,6 +372,20 @@ class Config(object): "LOWPAN_BORDER_ROUTER", "LOWPAN_HOST", "LOWPAN_ROUTER", "NANOSTACK_FULL", "THREAD_BORDER_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER", "ETHERNET_HOST" ] + @classmethod + def find_app_config(cls, top_level_dirs): + app_config_location = None + for directory in top_level_dirs: + full_path = os.path.join(directory, cls.__mbed_app_config_name) + if os.path.isfile(full_path): + if app_config_location is not None: + raise ConfigException("Duplicate '%s' file in '%s' and '%s'" + % (cls.__mbed_app_config_name, + cls.app_config_location, full_path)) + else: + app_config_location = full_path + return app_config_location + def __init__(self, tgt, top_level_dirs=None, app_config=None): """Construct a mbed configuration @@ -391,16 +405,8 @@ def __init__(self, tgt, top_level_dirs=None, app_config=None): """ config_errors = [] self.app_config_location = app_config - if self.app_config_location is None: - for directory in top_level_dirs or []: - full_path = os.path.join(directory, self.__mbed_app_config_name) - if os.path.isfile(full_path): - if self.app_config_location is not None: - raise ConfigException("Duplicate '%s' file in '%s' and '%s'" - % (self.__mbed_app_config_name, - self.app_config_location, full_path)) - else: - self.app_config_location = full_path + if self.app_config_location is None and top_level_dirs: + self.app_config_location = self.find_app_config(top_level_dirs) try: self.app_config_data = json_file_to_dict(self.app_config_location) \ if self.app_config_location else {} diff --git a/tools/detect_targets.py b/tools/detect_targets.py index b9aa80df1ca..b6407ae93ad 100644 --- a/tools/detect_targets.py +++ b/tools/detect_targets.py @@ -112,15 +112,14 @@ def get_interface_version(mount_point): """ if get_module_avail('mbed_lstools'): try : - mbeds = mbed_lstools.create() - details_txt = mbeds.get_details_txt(mount_point) + mbedls = mbed_lstools.create() + mbeds = mbedls.list_mbeds(unique_names=True, read_details_txt=True) - if 'Interface Version' in details_txt: - return details_txt['Interface Version'] - - elif 'Version' in details_txt: - return details_txt['Version'] + for mbed in mbeds: + if mbed['mount_point'] == mount_point: + if 'daplink_version' in mbed: + return mbed['daplink_version'] except : return 'unknown' diff --git a/tools/export/GettingStarted.html b/tools/export/GettingStarted.html index 9fce79ce031..226e4f7bd7c 100644 --- a/tools/export/GettingStarted.html +++ b/tools/export/GettingStarted.html @@ -3,9 +3,9 @@ + content="1;url="https://os.mbed.com/docs/latest/tools/exporting.html> Page Redirection diff --git a/tools/export/__init__.py b/tools/export/__init__.py index 501be59d151..c15669618f0 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -33,6 +33,7 @@ from tools.export import sw4stm32, e2studio, zip, cmsis, uvision, cdt, vscode from tools.export import gnuarmeclipse from tools.export import qtcreator +from tools.export import nb from tools.targets import TARGET_NAMES EXPORTERS = { @@ -57,6 +58,7 @@ 'eclipse_iar' : cdt.EclipseIAR, 'eclipse_armc5' : cdt.EclipseArmc5, 'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse, + 'netbeans': nb.GNUARMNetbeans, 'mcuxpresso': mcuxpresso.MCUXpresso, 'qtcreator': qtcreator.QtCreator, 'vscode_gcc_arm' : vscode.VSCodeGcc, diff --git a/tools/export/cmsis/__init__.py b/tools/export/cmsis/__init__.py index 2bf62ff267f..b036d674aa2 100644 --- a/tools/export/cmsis/__init__.py +++ b/tools/export/cmsis/__init__.py @@ -2,13 +2,13 @@ from os.path import sep, join, exists from itertools import groupby from xml.etree.ElementTree import Element, tostring -import ntpath import re import json from tools.arm_pack_manager import Cache from tools.targets import TARGET_MAP from tools.export.exporters import Exporter, TargetNotSupportedException +from tools.utils import split_path class fileCMSIS(): """CMSIS file class. @@ -37,7 +37,8 @@ def __init__(self, target): if not target_info: raise TargetNotSupportedException("Target not supported in CMSIS pack") self.url = target_info['pdsc_file'] - self.pack_url, self.pack_id = ntpath.split(self.url) + self.pdsc_url, self.pdsc_id, _ = split_path(self.url) + self.pack_url, self.pack_id, _ = split_path(target_info['pack_file']) self.dname = target_info["_cpu_name"] self.core = target_info["_core"] self.dfpu = target_info['processor']['fpu'] diff --git a/tools/export/e2studio/__init__.py b/tools/export/e2studio/__init__.py index dbd0ff818da..5195919f7d0 100644 --- a/tools/export/e2studio/__init__.py +++ b/tools/export/e2studio/__init__.py @@ -28,13 +28,7 @@ class E2Studio(GNUARMEclipse): # override def generate(self): - jinja_ctx = self.collect_tmpl_vars() - - print - print 'Create a e2 studio C++ managed project' - print 'Project name: {0}'.format(self.project_name) - print 'Target: {0}'.format(self.toolchain.target.name) - print 'Toolchain: {0}'.format(self.TOOLCHAIN) + jinja_ctx = self.create_jinja_ctx() self.gen_file('e2studio/.cproject.tmpl', jinja_ctx, '.cproject', trim_blocks=True, lstrip_blocks=True) self.gen_file('e2studio/.gdbinit.tmpl', jinja_ctx, '.gdbinit') @@ -43,6 +37,3 @@ def generate(self): self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx, '.project', trim_blocks=True, lstrip_blocks=True) self.gen_file('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore') self.gen_file('gnuarmeclipse/makefile.targets.tmpl', jinja_ctx, 'makefile.targets', trim_blocks=True, lstrip_blocks=True) - - print - print 'Done. Import the project located at \'{0}\' in e2 studio.'.format(self.project_name) diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index ac1861727e4..ad1096f158d 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -5,6 +5,9 @@ "STM32L476VG": { "OGChipSelectEditMenu": "STM32L476VG\tST STM32L476VG" }, + "STM32L475VG": { + "OGChipSelectEditMenu": "STM32L475VG\tST STM32L475VG" + }, "LPC11U24FBD48/401": { "OGChipSelectEditMenu": "LPC11U24FBD64_401\tNXP LPC11U24FBD64_401" }, @@ -245,5 +248,11 @@ "OGChipSelectEditMenu": "TMPM066FWUG\tToshiba TMPM066FWUG", "GFPUCoreSlave": 21, "GBECoreSlave": 21 + }, + "ADuCM3029": { + "OGChipSelectEditMenu": "ADuCM3029\tAnalogDevices ADuCM3029" + }, + "ADuCM4050": { + "OGChipSelectEditMenu": "ADuCM4050\tAnalogDevices ADuCM4050" } } diff --git a/tools/export/nb/Makefile.tmpl b/tools/export/nb/Makefile.tmpl new file mode 100644 index 00000000000..511311c6ef2 --- /dev/null +++ b/tools/export/nb/Makefile.tmpl @@ -0,0 +1,139 @@ +# +# There exist several targets which are by default empty and which can be +# used for execution of your targets. These targets are usually executed +# before and after some main targets. They are: +# +# .build-pre: called before 'build' target +# .build-post: called after 'build' target +# .clean-pre: called before 'clean' target +# .clean-post: called after 'clean' target +# .clobber-pre: called before 'clobber' target +# .clobber-post: called after 'clobber' target +# .all-pre: called before 'all' target +# .all-post: called after 'all' target +# .help-pre: called before 'help' target +# .help-post: called after 'help' target +# +# Targets beginning with '.' are not intended to be called on their own. +# +# Main targets can be executed directly, and they are: +# +# build build a specific configuration +# clean remove built files from a configuration +# clobber remove all built files +# all build all configurations +# help print help mesage +# +# Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and +# .help-impl are implemented in nbproject/makefile-impl.mk. +# +# Available make variables: +# +# CND_BASEDIR base directory for relative paths +# CND_DISTDIR default top distribution directory (build artifacts) +# CND_BUILDDIR default top build directory (object files, ...) +# CONF name of current configuration +# CND_PLATFORM_${CONF} platform name (current configuration) +# CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration) +# CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration) +# CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration) +# CND_PACKAGE_DIR_${CONF} directory of package (current configuration) +# CND_PACKAGE_NAME_${CONF} name of package (current configuration) +# CND_PACKAGE_PATH_${CONF} path to package (current configuration) +# +# NOCDDL + + +# Environment +MKDIR=mkdir +CP=cp +CCADMIN=CCadmin + +BUILDDIR = BUILD +PLATFORM = {{target}} +ELF2BIN = '{{elf2bin_cmd}}' +TARGET = ${CND_DISTDIR}/${CONF}/${CND_PLATFORM}/{{name}} + + +# build +build: .build-post + +.build-pre: +# Add your pre 'build' code here... + +.build-post: .build-impl +# Add your post 'build' code here... + $(ELF2BIN) -O binary ${TARGET}.elf ${TARGET}.bin + +@echo "===== bin file ready to flash: $(TARGET).bin =====" + $(ELF2BIN) -O ihex ${TARGET}.elf ${TARGET}.hex + cp ${TARGET}.* ${CND_BUILDDIR}/${CONF}/${CND_PLATFORM} + +# clean +clean: .clean-post + +.clean-pre: +# Add your pre 'clean' code here... + +.clean-post: .clean-impl +# Add your post 'clean' code here... + + +# clobber +clobber: .clobber-post + +.clobber-pre: +# Add your pre 'clobber' code here... + +.clobber-post: .clobber-impl +# Add your post 'clobber' code here... + + +# all +all: .all-post + +.all-pre: +# Add your pre 'all' code here... + +.all-post: .all-impl +# Add your post 'all' code here... + + +# build tests +build-tests: .build-tests-post + +.build-tests-pre: +# Add your pre 'build-tests' code here... + +.build-tests-post: .build-tests-impl +# Add your post 'build-tests' code here... + + +# run tests +test: .test-post + +.test-pre: build-tests +# Add your pre 'test' code here... + +.test-post: .test-impl +# Add your post 'test' code here... + + +# help +help: .help-post + +.help-pre: +# Add your pre 'help' code here... + +.help-post: .help-impl +# Add your post 'help' code here... + + + +# include project implementation makefile +include nbproject/Makefile-impl.mk + +# include project make variables +include nbproject/Makefile-variables.mk + +CND_BUILDDIR = ${BUILDDIR} +CND_PLATFORM = ${PLATFORM} diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py new file mode 100644 index 00000000000..c435b0d37de --- /dev/null +++ b/tools/export/nb/__init__.py @@ -0,0 +1,392 @@ +import os +import copy + +from os.path import relpath, join, exists, dirname, basename +from os import makedirs +from json import load + +from tools.export.exporters import Exporter, apply_supported_whitelist +from tools.targets import TARGET_MAP +from tools.utils import NotSupportedException +from tools.build_api import prepare_toolchain + +POST_BINARY_WHITELIST = set([ + "TEENSY3_1Code.binary_hook", + "MCU_NRF51Code.binary_hook", + "LPCTargetCode.lpc_patch", + "LPC4088Code.binary_hook" +]) + + +class GNUARMNetbeans(Exporter): + NAME = 'GNU ARM Netbeans' + TOOLCHAIN = 'GCC_ARM' + + @classmethod + def is_target_supported(cls, target_name): + target = TARGET_MAP[target_name] + return apply_supported_whitelist( + cls.TOOLCHAIN, POST_BINARY_WHITELIST, target) + + @staticmethod + def prepare_sys_lib(libname): + return "-l" + libname + + def toolchain_flags(self, toolchain): + """Returns a dictionary of toolchain flags. + Keys of the dictionary are: + cxx_flags - c++ flags + c_flags - c flags + ld_flags - linker flags + asm_flags - assembler flags + common_flags - common options + + The difference from the above is that it takes a parameter. + """ + + # Note: use the config options from the currently selected toolchain. + config_header = self.toolchain.get_config_header() + + flags = {key + "_flags": copy.deepcopy(value) for key, value + in toolchain.flags.iteritems()} + if config_header: + config_header = relpath(config_header, + self.resources.file_basepath[config_header]) + header_options = self.toolchain.get_config_option(config_header) + flags['c_flags'] += header_options + flags['cxx_flags'] += header_options + return flags + + @staticmethod + def get_defines_and_remove_from_flags(flags_in, str_key): + defines = [] + flags_temp = copy.deepcopy(flags_in) + for f in flags_temp[str_key]: + f = f.strip() + if f.startswith('-D'): + defines.append(f[2:]) + flags_in[str_key].remove(f) + + return defines + + @staticmethod + def get_includes_and_remove_from_flags(flags_in, str_key): + includes = [] + flags_temp = copy.deepcopy(flags_in) + next_is_include = False + for f in flags_temp[str_key]: + f = f.strip() + if next_is_include: + includes.append(f) + flags_in[str_key].remove(f) + next_is_include = False + continue + if f == "-include": + flags_in[str_key].remove(f) + next_is_include = True + + return includes + + @staticmethod + def get_c_std_and_remove_from_flag(flags_in, str_key): + comp_std = '' + c_std = { + 'c90': 'c90', 'c89': 'c90', 'gnu90': 'gnu90', 'gnu89': 'gnu90', + 'c99': 'c99', 'c9x': 'c99', 'gnu99': 'gnu99', 'gnu9x': 'gnu98', + 'c11': 'c11', 'c1x': 'c11', 'gnu11': 'gnu11', 'gnu1x': 'gnu11' + } + cpp_std = { + 'c++98': 'cpp98', 'c++03': 'cpp98', + 'gnu++98': 'gnucpp98', 'gnu++03': 'gnucpp98', + 'c++0x': 'cpp0x', 'gnu++0x': 'gnucpp0x', + 'c++11': 'cpp11', 'gnu++11': 'gnucpp11', + 'c++1y': 'cpp1y', 'gnu++1y': 'gnucpp1y', + 'c++14': 'cpp14', 'gnu++14': 'gnucpp14', + 'c++1z': 'cpp1z', 'gnu++1z': 'gnucpp1z', + } + + flags_temp = copy.deepcopy(flags_in) + for f in flags_temp[str_key]: + f = f.strip() + if f.startswith('-std='): + comp_std = f[len('-std='):] + flags_in[str_key].remove(f) + elif f.startswith('-'): + std = f[len('-'):] + if std in c_std or std in cpp_std: + comp_std = std + flags_in[str_key].remove(f) + return comp_std + + def validate_resources(self): + if not self.resources.linker_script: + raise NotSupportedException("No linker script found.") + + def create_jinja_ctx(self): + self.options = {} + flags = {} + self.validate_resources() + # Convert all Backslashes to Forward Slashes + self.resources.win_to_unix() + + print 'Include folders: {0}'.format(len(self.resources.inc_dirs)) + + print 'Symbols: {0}'.format(len(self.toolchain.get_symbols())) + + self.ld_script = self.filter_dot( + self.resources.linker_script) + print 'Linker script: {0}'.format(self.ld_script) + + # Read in all profiles, we'll extract compiler options. + profiles = self.get_all_profiles() + + profile_ids = [s.lower() for s in profiles] + profile_ids.sort() + for prof_id in profile_ids: + # There are 4 categories of options, a category common too + # all tools and a specific category for each of the tools. + opts = {} + opts['defines'] = {} + opts['common'] = {} + opts['as'] = {} + opts['c'] = {} + opts['cpp'] = {} + opts['ld'] = {} + + opts['id'] = prof_id + opts['name'] = opts['id'].capitalize() + + print + print 'Build configuration: {0}'.format(opts['name']) + + profile = profiles[prof_id] + + # A small hack, do not bother with src_path again, + # pass an empty string to avoid crashing. + src_paths = [''] + target_name = self.toolchain.target.name + + toolchain = prepare_toolchain( + src_paths, "", target_name, self.TOOLCHAIN, build_profile=[profile]) + + flags = self.toolchain_flags(toolchain) + + print 'Common flags:', ' '.join(flags['common_flags']) + print 'C++ flags:', ' '.join(flags['cxx_flags']) + print 'C flags:', ' '.join(flags['c_flags']) + print 'ASM flags:', ' '.join(flags['asm_flags']) + print 'Linker flags:', ' '.join(flags['ld_flags']) + + opts['defines'] = self.get_defines_and_remove_from_flags(flags, 'common_flags') + opts['forced_includes'] = self.get_includes_and_remove_from_flags(flags, 'common_flags') + opts['common'] = flags['common_flags'] + opts['as'] = flags['asm_flags'] + opts['c'] = flags['c_flags'] + opts['cpp'] = flags['cxx_flags'] + opts['ld'] = flags['ld_flags'] + + self.options[prof_id] = opts + + sources = [] # list of strings + + forced_includes = self.get_includes_and_remove_from_flags(flags, 'c_flags') + forced_includes += self.get_includes_and_remove_from_flags(flags, 'cxx_flags') + + # Remove Duplicates + forced_includes = list(set(forced_includes)) + + c_std = self.get_c_std_and_remove_from_flag(flags, 'c_flags') + cpp_std = self.get_c_std_and_remove_from_flag(flags, 'cxx_flags') + + # Make one list of all resources + for r_type in ['c_sources', 's_sources', 'cpp_sources']: + sources.extend(getattr(self.resources, r_type)) + + # Remove all leading './' + c_sources = [self.filter_dot(field) for field in self.resources.c_sources] + cpp_sources = [self.filter_dot(field) for field in self.resources.cpp_sources] + s_sources = [self.filter_dot(field) for field in self.resources.s_sources] + headers = [self.filter_dot(field) for field in self.resources.headers] + sources = [self.filter_dot(field) for field in sources] + include_paths = [self.filter_dot(field) for field in self.resources.inc_dirs] + + sys_libs = [self.prepare_sys_lib(lib) for lib + in self.toolchain.sys_libs] + preproc = " ".join([basename(self.toolchain.preproc[0])] + + self.toolchain.preproc[1:] + + self.toolchain.ld[1:]) + + if 'nbproject' in include_paths: + include_paths.remove('nbproject') + + jinja_ctx = { + 'name': self.project_name, + 'target': self.toolchain.target.name, + 'elf_location': join('BUILD', self.project_name) + '.elf', + 'c_symbols': self.toolchain.get_symbols(), + 'asm_symbols': self.toolchain.get_symbols(True), + 'c_flags': flags['c_flags'], + 'cxx_flags': flags['cxx_flags'], + 'ld_flags': self.flags['ld_flags'], + 'asm_flags': self.flags['asm_flags'], + 'common_flags': self.flags['common_flags'], + 'include_paths': include_paths, + 'forced_includes': forced_includes, + 'c_sources': c_sources, + 'cpp_sources': cpp_sources, + 's_sources': s_sources, + 'headers': headers, + 'headers_folder': self.get_netbeans_file_list(sorted(headers)), + 'sources_folder': self.get_netbeans_file_list(sorted(sources)), + 'options': self.options, + 'c_std': self.get_netbeans_c_std(c_std), + 'cpp_std': self.get_netbeans_cpp_std(cpp_std), + 'linker_script': self.ld_script, + 'linker_libs': sys_libs, + 'pp_cmd': preproc, + 'cc_cmd': self.toolchain.cc[0], + 'cppc_cmd': self.toolchain.cppc[0], + 'asm_cmd': self.toolchain.asm[0], + 'ld_cmd': self.toolchain.ld[0], + 'elf2bin_cmd': self.toolchain.elf2bin + } + return jinja_ctx + + def generate(self): + """Generate Makefile, configurations.xml & project.xml Netbeans project file + """ + jinja_ctx = self.create_jinja_ctx() + + print + print 'Create a GNU ARM Netbeans C++ managed project' + print 'Project name: {0}'.format(self.project_name) + print 'Target: {0}'.format(self.toolchain.target.name) + print 'Toolchain: {0}'.format(self.TOOLCHAIN) + + if not exists(join(self.export_dir, 'nbproject')): + makedirs(join(self.export_dir, 'nbproject')) + + self.gen_file('nb/configurations.tmpl', jinja_ctx, 'nbproject/configurations.xml') + self.gen_file('nb/project.tmpl', jinja_ctx, 'nbproject/project.xml') + self.gen_file('nb/mbedignore.tmpl', jinja_ctx, '.mbedignore') + self.gen_file('nb/Makefile.tmpl', jinja_ctx, 'Makefile') + + print + print 'Done. Import the \'{0}\' project in Netbeans.'.format(self.project_name) + + # ------------------------------------------------------------------------- + + @staticmethod + def filter_dot(str_in): + """ + Remove the './' prefix, if present. + This function assumes that resources.win_to_unix() + replaced all windows backslashes with slashes. + """ + if str_in is None: + return None + if str_in[:2] == './': + return str_in[2:] + return str_in + + # ------------------------------------------------------------------------- + + @staticmethod + def get_all_profiles(): + tools_path = dirname(dirname(dirname(__file__))) + file_names = [join(tools_path, "profiles", fn) for fn in os.listdir( + join(tools_path, "profiles")) if fn.endswith(".json")] + + profiles = {} + + for fn in file_names: + content = load(open(fn)) + profile_name = basename(fn).replace(".json", "") + profiles[profile_name] = content + + return profiles + + @staticmethod + def get_netbeans_file_list(file_list): + cur_dir = '' + prev_dir = '' + output = [] + folder_count = 1 + dir_depth = 0 + for item in file_list: + cur_dir = os.path.dirname(item) + dir_temp = os.path.normpath(cur_dir) + prev_dir_temp = os.path.normpath(prev_dir) + dir_list = dir_temp.split(os.sep) + prev_dir_list = prev_dir_temp.split(os.sep) + dir_depth = len(dir_list) + + # Current File is in Directory: Compare the given dir with previous Dir + if cur_dir and prev_dir != cur_dir: + # evaluate all matched items (from current and previous list) + matched = [] + for element in dir_list: + if element in prev_dir_list: + matched.append(element) + + # calculate difference between matched and length + diff = dir_depth - len(matched) + + # if previous dir was not root + if prev_dir != '': + # if the elements count is not equal we calculate the difference + if len(dir_list) != len(prev_dir_list): + dir_depth_prev = len(prev_dir_list) + delta = dir_depth_prev - len(matched) + + for i in range(dir_depth_prev - delta, dir_depth_prev): + output.append('') + + # if the elements count is equal, we subtract the matched length from the total length + else: + for i in range(len(matched), len(dir_list)): + output.append('') + + for i in range(dir_depth - diff, dir_depth): + output.append('') + folder_count += 1 + + # Current File is in root + else: + # Close Tag if we are in root and the previous dir wasn't + if cur_dir == '' and prev_dir != '': + for i in range(0, len(prev_dir_list)): + output.append('') + + # Save the Current Dir + prev_dir = cur_dir + output.append('' + str(item) + '') + + if cur_dir != '': + # close all open tags + output.append('' * dir_depth) + + return output + + @staticmethod + def get_netbeans_c_std(c_std): + c_std_netbeans = 0 + if '89' in c_std: + c_std_netbeans = 2 + elif '99' in c_std: + c_std_netbeans = 3 + elif '11' in c_std: + c_std_netbeans = 10 + return c_std_netbeans + + @staticmethod + def get_netbeans_cpp_std(cpp_std): + cpp_std_netbeans = 0 + if '98' in cpp_std: + cpp_std_netbeans = 4 + elif '11' in cpp_std: + cpp_std_netbeans = 8 + elif '14' in cpp_std: + cpp_std_netbeans = 11 + return cpp_std_netbeans diff --git a/tools/export/nb/configurations.tmpl b/tools/export/nb/configurations.tmpl new file mode 100644 index 00000000000..b53397a025e --- /dev/null +++ b/tools/export/nb/configurations.tmpl @@ -0,0 +1,177 @@ + + + + + {% for header in headers_folder -%} + {{ header }} + {% endfor %} + + + {{ linker_script }} + + + + + {% for source in sources_folder -%} + {{ source }} + {% endfor %} + + + + + + + Makefile + + + ^(nbproject)$ + + . + + Makefile + + {% for id in options -%} + {% set opts = options[id] %} + + + default + true + false + + + + {{ c_std }} + + {% for inc_dir in include_paths -%}{% if inc_dir -%} + {{ inc_dir }} + {% endif -%} + {% endfor -%} + + + {% for inc_file in forced_includes -%} + {{ inc_file }} + {% endfor -%} + + {%- for flag in c_flags -%}{{ flag+" "}}{%- endfor -%} + {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%} + + + {% for item in opts['defines'] -%} + {{ item }} + {% endfor -%} + {% for symbol in c_symbols -%} + {{ symbol }} + {% endfor -%} + + {{cc_cmd}} + + + {{ cpp_std }} + + {% for inc_dir in include_paths -%}{% if inc_dir -%} + {{ inc_dir }} + {% endif -%} + {% endfor -%} + + + {% for inc_file in forced_includes -%} + {{ inc_file }} + {% endfor -%} + + {%- for flag in cxx_flags -%}{{ flag+" "}}{%- endfor -%} + {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%} + + + {% for item in opts['defines'] -%} + {{ item }} + {% endfor -%} + {% for symbol in c_symbols -%} + {{ symbol }} + {% endfor -%} + + {{cppc_cmd}} + + + 5 + + + 5 + + {% for inc_dir in include_paths -%}{% if inc_dir -%} + {{ inc_dir }} + {% endif -%} + {% endfor -%} + + + {% for inc_file in forced_includes -%} + {{ inc_file }} + {% endfor -%} + + {%- for flag in asm_flags -%}{{ flag+" "}}{%- endfor -%} + {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%} + + + {% for symbol in asm_symbols -%} + {{ symbol }} + {% endfor -%} + + {{asm_cmd}} + + + ${CND_DISTDIR}/${CND_CONF}/{{target}}/{{name}}.elf + ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld + {{ld_cmd}} + -T ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld {%- for symbol in opts['ld'] -%}{{" "+symbol}}{%- endfor -%} {%- for item in linker_libs -%}{{" "+item}}{%- endfor -%} + + + {% for h in headers -%} + + + {% endfor -%} + {% for s in c_sources -%} + + + + + {% endfor -%} + {% for s in cpp_sources -%} + + + + + {% endfor -%} + {% for s in s_sources -%} + + + {% endfor -%} + + + {{pp_cmd}} -o $@ $< + Create ELF File using Link Script + ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld + + + + + + + + {% endfor -%} + + diff --git a/tools/export/nb/mbedignore.tmpl b/tools/export/nb/mbedignore.tmpl new file mode 100644 index 00000000000..805fc686b52 --- /dev/null +++ b/tools/export/nb/mbedignore.tmpl @@ -0,0 +1,2 @@ +nbproject/private/*.cpp +nbproject/private/*.c diff --git a/tools/export/nb/project.tmpl b/tools/export/nb/project.tmpl new file mode 100644 index 00000000000..3d4ea0d1bf6 --- /dev/null +++ b/tools/export/nb/project.tmpl @@ -0,0 +1,28 @@ + + + org.netbeans.modules.cnd.makeproject + + + {{name}} + c + cpp + h + UTF-8 + + + + + Debug + 1 + + + Release + 1 + + + + false + + + + diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index 9d55dae8fef..8bcf75f9a48 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -189,6 +189,11 @@ class Sw4STM32(GNUARMEclipse): 'name': 'NUCLEO-F411RE', 'mcuId': 'STM32F411RETx' }, + 'NUCLEO_F413ZH': + { + 'name': 'NUCLEO-F413ZH', + 'mcuId': 'STM32F413ZHTx' + }, 'NUCLEO_F429ZI': { 'name': 'NUCLEO-F429ZI', diff --git a/tools/export/uvision/uvision.tmpl b/tools/export/uvision/uvision.tmpl index 49c708c3bb1..f49c79659d4 100644 --- a/tools/export/uvision/uvision.tmpl +++ b/tools/export/uvision/uvision.tmpl @@ -394,7 +394,7 @@ {{asm_flags}} - {{include_paths}} + diff --git a/tools/memap.py b/tools/memap.py index a2efd0e230d..b5c1b68814a 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -2,89 +2,42 @@ """Memory Map File Analyser for ARM mbed""" -import sys -import os +from abc import abstractmethod, ABCMeta +from sys import stdout, exit, argv +from os import sep +from os.path import basename, dirname, join, relpath, commonprefix import re import csv import json -import argparse +from argparse import ArgumentParser from copy import deepcopy from prettytable import PrettyTable from utils import argparse_filestring_type, \ argparse_lowercase_hyphen_type, argparse_uppercase_type -RE_ARMCC = re.compile( - r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$') -RE_IAR = re.compile( - r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s' - r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$') -RE_CMDLINE_FILE_IAR = re.compile(r'^#\s+(.+\.o)') -RE_LIBRARY_IAR = re.compile(r'^(.+\.a)\:.+$') -RE_OBJECT_LIBRARY_IAR = re.compile(r'^\s+(.+\.o)\s.*') - -RE_OBJECT_FILE_GCC = re.compile(r'^(.+\/.+\.o)$') -RE_LIBRARY_OBJECT_GCC = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$') -RE_STD_SECTION_GCC = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$') -RE_FILL_SECTION_GCC = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$') - -RE_OBJECT_ARMCC = re.compile(r'(.+\.(l|ar))\((.+\.o)\)') - - -class MemapParser(object): - """An object that represents parsed results, parses the memory map files, - and writes out different file types of memory results - """ - - print_sections = ('.text', '.data', '.bss') - - misc_flash_sections = ('.interrupts', '.flash_config') - - other_sections = ('.interrupts_ram', '.init', '.ARM.extab', +class _Parser(object): + """Internal interface for parsing""" + __metaclass__ = ABCMeta + SECTIONS = ('.text', '.data', '.bss', '.heap', '.stack') + MISC_FLASH_SECTIONS = ('.interrupts', '.flash_config') + OTHER_SECTIONS = ('.interrupts_ram', '.init', '.ARM.extab', '.ARM.exidx', '.ARM.attributes', '.eh_frame', '.init_array', '.fini_array', '.jcr', '.stab', '.stabstr', '.ARM.exidx', '.ARM') - # sections to print info (generic for all toolchains) - sections = ('.text', '.data', '.bss', '.heap', '.stack') - def __init__(self): - """ General initialization - """ - - # list of all modules and their sections - self.modules = dict() # full list - doesn't change with depth - self.short_modules = dict() # short version with specific depth - - # sections must be defined in this order to take irrelevant out - self.all_sections = self.sections + self.other_sections + \ - self.misc_flash_sections + ('unknown', 'OUTPUT') - - # Memory report (sections + summary) - self.mem_report = [] - - # Just the memory summary section - self.mem_summary = dict() - - self.subtotal = dict() - - self.misc_flash_mem = 0 - - # Modules passed to the linker on the command line - # this is a dict because modules are looked up by their basename - self.cmd_modules = {} - + self.modules = dict() def module_add(self, object_name, size, section): - """ Adds a module / section to the list + """ Adds a module or section to the list Positional arguments: object_name - name of the entry to add size - the size of the module being added section - the section the module contributes to """ - if not object_name or not size or not section: return @@ -93,7 +46,7 @@ def module_add(self, object_name, size, section): self.modules[object_name][section] += size return - obj_split = os.sep + os.path.basename(object_name) + obj_split = sep + basename(object_name) for module_path, contents in self.modules.items(): if module_path.endswith(obj_split) or module_path == object_name: contents.setdefault(section, 0) @@ -110,15 +63,38 @@ def module_replace(self, old_object, new_object): self.modules[new_object] = self.modules[old_object] del self.modules[old_object] - def check_new_section_gcc(self, line): - """ Check whether a new section in a map file has been detected (only - applies to gcc) + @abstractmethod + def parse_mapfile(self, mapfile): + """Parse a given file object pointing to a map file Positional arguments: - line - the line to check for a new section + mapfile - an open file object that reads a map file + + return value - a dict mapping from object names to section dicts, + where a section dict maps from sections to sizes """ + raise NotImplemented + + +class _GccParser(_Parser): + RE_OBJECT_FILE = re.compile(r'^(.+\/.+\.o)$') + RE_LIBRARY_OBJECT = re.compile(r'^.+' + sep + r'lib((.+\.a)\((.+\.o)\))$') + RE_STD_SECTION = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$') + RE_FILL_SECTION = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$') + + ALL_SECTIONS = _Parser.SECTIONS + _Parser.OTHER_SECTIONS + \ + _Parser.MISC_FLASH_SECTIONS + ('unknown', 'OUTPUT') + + def check_new_section(self, line): + """ Check whether a new section in a map file has been detected + + Positional arguments: + line - the line to check for a new section - for i in self.all_sections: + return value - A section name, if a new section was found, False + otherwise + """ + for i in self.ALL_SECTIONS: if line.startswith(i): # should name of the section (assuming it's a known one) return i @@ -129,72 +105,65 @@ def check_new_section_gcc(self, line): return False # everything else, means no change in section - def parse_object_name_gcc(self, line): + def parse_object_name(self, line): """ Parse a path to object file Positional arguments: - txt - the path to parse the object and module name from - """ + line - the path to parse the object and module name from - line = line.replace('\\', '/') - test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line) + return value - an object file name + """ + test_re_mbed_os_name = re.match(self.RE_OBJECT_FILE, line) if test_re_mbed_os_name: - object_name = test_re_mbed_os_name.group(1) # corner case: certain objects are provided by the GCC toolchain if 'arm-none-eabi' in line: - return '[lib]/misc/' + object_name + return join('[lib]', 'misc', basename(object_name)) return object_name else: - - test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line) + test_re_obj_name = re.match(self.RE_LIBRARY_OBJECT, line) if test_re_obj_name: - object_name = test_re_obj_name.group(1) + '/' + \ - test_re_obj_name.group(2) - - return '[lib]/' + object_name - + return join('[lib]', test_re_obj_name.group(2), + test_re_obj_name.group(3)) else: print "Unknown object name found in GCC map file: %s" % line return '[misc]' - def parse_section_gcc(self, line): + def parse_section(self, line): """ Parse data from a section of gcc map file examples: 0x00004308 0x7c ./BUILD/K64F/GCC_ARM/mbed-os/hal/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.o - .text 0x00000608 0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/HAL_CM4.o + .text 0x00000608 0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN/HAL_CM4.o Positional arguments: line - the line to parse a section from """ - - is_fill = re.match(RE_FILL_SECTION_GCC, line) + is_fill = re.match(self.RE_FILL_SECTION, line) if is_fill: o_name = '[fill]' o_size = int(is_fill.group(2), 16) return [o_name, o_size] - is_section = re.match(RE_STD_SECTION_GCC, line) + is_section = re.match(self.RE_STD_SECTION, line) if is_section: o_size = int(is_section.group(2), 16) if o_size: - o_name = self.parse_object_name_gcc(is_section.group(3)) + o_name = self.parse_object_name(is_section.group(3)) return [o_name, o_size] return ["", 0] - def parse_map_file_gcc(self, file_desc): + def parse_mapfile(self, file_desc): """ Main logic to decode gcc map files Positional arguments: file_desc - a stream object to parse as a gcc map file """ - current_section = 'unknown' with file_desc as infile: @@ -204,97 +173,141 @@ def parse_map_file_gcc(self, file_desc): break for line in infile: - next_section = self.check_new_section_gcc(line) + next_section = self.check_new_section(line) if next_section == "OUTPUT": break elif next_section: current_section = next_section - object_name, object_size = self.parse_section_gcc(line) - + object_name, object_size = self.parse_section(line) self.module_add(object_name, object_size, current_section) - common_prefix = os.path.dirname(os.path.commonprefix([ + common_prefix = dirname(commonprefix([ o for o in self.modules.keys() if (o.endswith(".o") and not o.startswith("[lib]"))])) new_modules = {} for name, stats in self.modules.items(): if name.startswith("[lib]"): new_modules[name] = stats elif name.endswith(".o"): - new_modules[os.path.relpath(name, common_prefix)] = stats + new_modules[relpath(name, common_prefix)] = stats else: new_modules[name] = stats - self.modules = new_modules + return new_modules + - def parse_object_name_armcc(self, line): +class _ArmccParser(_Parser): + RE = re.compile( + r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$') + RE_OBJECT = re.compile(r'(.+\.(l|ar))\((.+\.o)\)') + + def parse_object_name(self, line): """ Parse object file Positional arguments: line - the line containing the object or library """ - - # simple object (not library) - if line[-2] == '.' and line[-1] == 'o': + if line.endswith(".o"): return line else: - is_obj = re.match(RE_OBJECT_ARMCC, line) + is_obj = re.match(self.RE_OBJECT, line) if is_obj: - object_name = os.path.basename(is_obj.group(1)) + '/' + is_obj.group(3) - return '[lib]/' + object_name + return join('[lib]', basename(is_obj.group(1)), is_obj.group(3)) else: print "Malformed input found when parsing ARMCC map: %s" % line return '[misc]' - - - def parse_section_armcc(self, line): + def parse_section(self, line): """ Parse data from an armcc map file Examples of armcc map file: Base_Addr Size Type Attr Idx E Section Name Object - 0x00000000 0x00000400 Data RO 11222 RESET startup_MK64F12.o + 0x00000000 0x00000400 Data RO 11222 self.RESET startup_MK64F12.o 0x00000410 0x00000008 Code RO 49364 * !!!main c_w.l(__main.o) Positional arguments: line - the line to parse the section data from """ + test_re = re.match(self.RE, line) - test_re_armcc = re.match(RE_ARMCC, line) - - if test_re_armcc: + if test_re: + size = int(test_re.group(2), 16) - size = int(test_re_armcc.group(2), 16) - - if test_re_armcc.group(4) == 'RO': + if test_re.group(4) == 'RO': section = '.text' else: - if test_re_armcc.group(3) == 'Data': + if test_re.group(3) == 'Data': section = '.data' - elif test_re_armcc.group(3) == 'Zero': + elif test_re.group(3) == 'Zero': section = '.bss' + elif test_re.group(3) == 'Code': + section = '.text' else: - print "Malformed input found when parsing armcc map: %s" %\ - line + print "Malformed input found when parsing armcc map: %s, %r" %\ + (line, test_re.groups()) + + return ["", 0, ""] # check name of object or library - object_name = self.parse_object_name_armcc(\ - test_re_armcc.group(6)) + object_name = self.parse_object_name( + test_re.group(6)) return [object_name, size, section] else: return ["", 0, ""] - def parse_object_name_iar(self, object_name): + def parse_mapfile(self, file_desc): + """ Main logic to decode armc5 map files + + Positional arguments: + file_desc - a file like object to parse as an armc5 map file + """ + with file_desc as infile: + # Search area to parse + for line in infile: + if line.startswith(' Base Addr Size'): + break + + # Start decoding the map file + for line in infile: + self.module_add(*self.parse_section(line)) + + common_prefix = dirname(commonprefix([ + o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))])) + new_modules = {} + for name, stats in self.modules.items(): + if name == "anon$$obj.o" or name.startswith("[lib]"): + new_modules[name] = stats + elif name.endswith(".o"): + new_modules[relpath(name, common_prefix)] = stats + else: + new_modules[name] = stats + return new_modules + + +class _IarParser(_Parser): + RE = re.compile( + r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s' + r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$') + + RE_CMDLINE_FILE = re.compile(r'^#\s+(.+\.o)') + RE_LIBRARY = re.compile(r'^(.+\.a)\:.+$') + RE_OBJECT_LIBRARY = re.compile(r'^\s+(.+\.o)\s.*') + + def __init__(self): + _Parser.__init__(self) + # Modules passed to the linker on the command line + # this is a dict because modules are looked up by their basename + self.cmd_modules = {} + + def parse_object_name(self, object_name): """ Parse object file Positional arguments: line - the line containing the object or library """ - - # simple object (not library) if object_name.endswith(".o"): try: return self.cmd_modules[object_name] @@ -303,8 +316,7 @@ def parse_object_name_iar(self, object_name): else: return '[misc]' - - def parse_section_iar(self, line): + def parse_section(self, line): """ Parse data from an IAR map file Examples of IAR map file: @@ -321,86 +333,48 @@ def parse_section_iar(self, line): Positional_arguments: line - the line to parse section data from """ - - test_re_iar = re.match(RE_IAR, line) - - if test_re_iar: - - size = int(test_re_iar.group(4), 16) - - if (test_re_iar.group(2) == 'const' or - test_re_iar.group(2) == 'ro code'): + test_re = re.match(self.RE, line) + if test_re: + if (test_re.group(2) == 'const' or + test_re.group(2) == 'ro code'): section = '.text' - elif (test_re_iar.group(2) == 'zero' or - test_re_iar.group(2) == 'uninit'): - if test_re_iar.group(1)[0:4] == 'HEAP': + elif (test_re.group(2) == 'zero' or + test_re.group(2) == 'uninit'): + if test_re.group(1)[0:4] == 'HEAP': section = '.heap' - elif test_re_iar.group(1)[0:6] == 'CSTACK': + elif test_re.group(1)[0:6] == 'CSTACK': section = '.stack' else: section = '.bss' # default section - elif test_re_iar.group(2) == 'inited': + elif test_re.group(2) == 'inited': section = '.data' else: print "Malformed input found when parsing IAR map: %s" % line + return ["", 0, ""] # lookup object in dictionary and return module name - object_name = self.parse_object_name_iar(test_re_iar.group(5)) + object_name = self.parse_object_name(test_re.group(5)) + size = int(test_re.group(4), 16) return [object_name, size, section] else: - return ["", 0, ""] # no valid entry - - def parse_map_file_armcc(self, file_desc): - """ Main logic to decode armc5 map files - - Positional arguments: - file_desc - a file like object to parse as an armc5 map file - """ - - with file_desc as infile: - - # Search area to parse - for line in infile: - if line.startswith(' Base Addr Size'): - break - - # Start decoding the map file - for line in infile: - self.module_add(*self.parse_section_armcc(line)) - - common_prefix = os.path.dirname(os.path.commonprefix([ - o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))])) - new_modules = {} - for name, stats in self.modules.items(): - if name == "anon$$obj.o" or name.startswith("[lib]"): - new_modules[name] = stats - elif name.endswith(".o"): - new_modules[os.path.relpath(name, common_prefix)] = stats - else: - new_modules[name] = stats - self.modules = new_modules - - + return ["", 0, ""] - def check_new_library_iar(self, line): + def check_new_library(self, line): """ Searches for libraries and returns name. Example: m7M_tls.a: [43] """ - - - test_address_line = re.match(RE_LIBRARY_IAR, line) - + test_address_line = re.match(self.RE_LIBRARY, line) if test_address_line: return test_address_line.group(1) else: return "" - def check_new_object_lib_iar(self, line): + def check_new_object_lib(self, line): """ Searches for objects within a library section and returns name. Example: rt7M_tl.a: [44] @@ -411,15 +385,13 @@ def check_new_object_lib_iar(self, line): I64DivZer.o 2 """ - - test_address_line = re.match(RE_OBJECT_LIBRARY_IAR, line) - + test_address_line = re.match(self.RE_OBJECT_LIBRARY, line) if test_address_line: return test_address_line.group(1) else: return "" - def parse_iar_command_line(self, lines): + def parse_command_line(self, lines): """Parse the files passed on the command line to the iar linker Positional arguments: @@ -428,51 +400,82 @@ def parse_iar_command_line(self, lines): for line in lines: if line.startswith("*"): break - is_cmdline_file = RE_CMDLINE_FILE_IAR.match(line) - if is_cmdline_file: - full_path = is_cmdline_file.group(1) - self.cmd_modules[os.path.basename(full_path)] = full_path + for arg in line.split(" "): + arg = arg.rstrip(" \n") + if (not arg.startswith("-")) and arg.endswith(".o"): + self.cmd_modules[basename(arg)] = arg - common_prefix = os.path.dirname(os.path.commonprefix(self.cmd_modules.values())) - self.cmd_modules = {s: os.path.relpath(f, common_prefix) + common_prefix = dirname(commonprefix(self.cmd_modules.values())) + self.cmd_modules = {s: relpath(f, common_prefix) for s, f in self.cmd_modules.items()} - - def parse_map_file_iar(self, file_desc): + def parse_mapfile(self, file_desc): """ Main logic to decode IAR map files Positional arguments: file_desc - a file like object to parse as an IAR map file """ - with file_desc as infile: - self.parse_iar_command_line(infile) + self.parse_command_line(infile) for line in infile: if line.startswith(' Section '): break for line in infile: - self.module_add(*self.parse_section_iar(line)) + self.module_add(*self.parse_section(line)) if line.startswith('*** MODULE SUMMARY'): # finish section break current_library = "" for line in infile: - - library = self.check_new_library_iar(line) + library = self.check_new_library(line) if library: current_library = library - object_name = self.check_new_object_lib_iar(line) + object_name = self.check_new_object_lib(line) if object_name and current_library: - temp = '[lib]' + '/'+ current_library + '/'+ object_name + temp = join('[lib]', current_library, object_name) self.module_replace(object_name, temp) + return self.modules + + +class MemapParser(object): + """An object that represents parsed results, parses the memory map files, + and writes out different file types of memory results + """ + + print_sections = ('.text', '.data', '.bss') + + + # sections to print info (generic for all toolchains) + sections = _Parser.SECTIONS + misc_flash_sections = _Parser.MISC_FLASH_SECTIONS + other_sections = _Parser.OTHER_SECTIONS + + def __init__(self): + # list of all modules and their sections + # full list - doesn't change with depth + self.modules = dict() + # short version with specific depth + self.short_modules = dict() + # Memory report (sections + summary) + self.mem_report = [] + + # Memory summary + self.mem_summary = dict() + + # Totals of ".text", ".data" and ".bss" + self.subtotal = dict() + + # Flash no associated with a module + self.misc_flash_mem = 0 + def reduce_depth(self, depth): """ populates the short_modules attribute with a truncated module list @@ -492,16 +495,15 @@ def reduce_depth(self, depth): else: self.short_modules = dict() for module_name, v in self.modules.items(): - split_name = module_name.split('/') + split_name = module_name.split(sep) if split_name[0] == '': split_name = split_name[1:] - new_name = "/".join(split_name[:depth]) + new_name = join(*split_name[:depth]) self.short_modules.setdefault(new_name, {}) for section_idx, value in v.items(): self.short_modules[new_name].setdefault(section_idx, 0) self.short_modules[new_name][section_idx] += self.modules[module_name][section_idx] - export_formats = ["json", "csv-ci", "table"] def generate_output(self, export_format, depth, file_output=None): @@ -516,15 +518,13 @@ def generate_output(self, export_format, depth, file_output=None): Returns: generated string for the 'table' format, otherwise None """ - self.reduce_depth(depth) self.compute_report() - try: if file_output: file_desc = open(file_output, 'wb') else: - file_desc = sys.stdout + file_desc = stdout except IOError as error: print "I/O error({0}): {1}".format(error.errno, error.strerror) return False @@ -534,7 +534,7 @@ def generate_output(self, export_format, depth, file_output=None): 'table': self.generate_table}[export_format] output = to_call(file_desc) - if file_desc is not sys.stdout: + if file_desc is not stdout: file_desc.close() return output @@ -547,7 +547,6 @@ def generate_json(self, file_desc): """ file_desc.write(json.dumps(self.mem_report, indent=4)) file_desc.write('\n') - return None def generate_csv(self, file_desc): @@ -574,7 +573,6 @@ def generate_csv(self, file_desc): csv_writer.writerow(csv_module_section) csv_writer.writerow(csv_sizes) - return None def generate_table(self, file_desc): @@ -656,31 +654,29 @@ def parse(self, mapfile, toolchain): mapfile - the file name of the memory map file toolchain - the toolchain used to create the file """ - - result = True + if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"): + parser = _ArmccParser() + elif toolchain == "GCC_ARM" or toolchain == "GCC_CR": + parser = _GccParser() + elif toolchain == "IAR": + parser = _IarParser() + else: + return False try: with open(mapfile, 'r') as file_input: - if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"): - self.parse_map_file_armcc(file_input) - elif toolchain == "GCC_ARM" or toolchain == "GCC_CR": - self.parse_map_file_gcc(file_input) - elif toolchain == "IAR": - self.parse_map_file_iar(file_input) - else: - result = False + self.modules = parser.parse_mapfile(file_input) + return True except IOError as error: print "I/O error({0}): {1}".format(error.errno, error.strerror) - result = False - return result + return False def main(): """Entry Point""" - version = '0.4.0' # Parser handling - parser = argparse.ArgumentParser( + parser = ArgumentParser( description="Memory Map File Analyser for ARM mbed\nversion %s" % version) @@ -711,9 +707,9 @@ def main(): parser.add_argument('-v', '--version', action='version', version=version) # Parse/run command - if len(sys.argv) <= 1: + if len(argv) <= 1: parser.print_help() - sys.exit(1) + exit(1) args = parser.parse_args() @@ -723,7 +719,7 @@ def main(): # Parse and decode a map file if args.file and args.toolchain: if memap.parse(args.file, args.toolchain) is False: - sys.exit(0) + exit(0) if args.depth is None: depth = 2 # default depth level @@ -741,7 +737,7 @@ def main(): if args.export == 'table' and returned_string: print returned_string - sys.exit(0) + exit(0) if __name__ == "__main__": main() diff --git a/tools/options.py b/tools/options.py index 8cfec663ac3..d5d590b3e69 100644 --- a/tools/options.py +++ b/tools/options.py @@ -117,16 +117,6 @@ def extract_profile(parser, options, toolchain, fallback="develop"): profiles.append(contents) return profiles - -def mcu_is_enabled(parser, mcu): - if "Cortex-A" in TARGET_MAP[mcu].core: - args_error( - parser, - ("%s Will be supported in mbed OS 5.6. " - "To use the %s, please checkout the mbed OS 5.4 release branch. " - "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice " - "for more information") % (mcu, mcu)) - return True def extract_mcus(parser, options): try: diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 465a1853f80..8bf0db68a7b 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-fno-builtin", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os"], + "-fomit-frame-pointer", "-Os", "-g1"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], diff --git a/tools/profiles/release.json b/tools/profiles/release.json index 11207322d66..1fa503836d3 100644 --- a/tools/profiles/release.json +++ b/tools/profiles/release.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-fno-builtin", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os", "-DNDEBUG"], + "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g1"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu99"], "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"], diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py index 24e9b79ceb1..c5670df4820 100644 --- a/tools/targets/REALTEK_RTL8195AM.py +++ b/tools/targets/REALTEK_RTL8195AM.py @@ -255,7 +255,9 @@ def create_daplink(image_bin, ram1_bin, ram2_bin): output = open(image_bin, "wb") append_image_file(ram1_bin, output) + append_image_file(ram2_bin, output) + output.seek(0xb000) line = "" for key in ['tag', 'ver', 'timestamp', 'size', 'hash', 'campaign']: line += RAM2_HEADER[key] @@ -264,7 +266,6 @@ def create_daplink(image_bin, ram1_bin, ram2_bin): RAM2_HEADER['crc32'] = format_number(crc32_checksum(line), 8) output.write(RAM2_HEADER['crc32']) - append_image_file(ram2_bin, output) output.close() # ---------------------------- diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index fc4b221a283..020fe5ca198 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -458,6 +458,11 @@ def combine_bins_mts_dragonfly(t_self, resources, elf, binf): """A hoof for the MTS Dragonfly""" MTSCode._combine_bins_helper("MTS_DRAGONFLY_F411RE", binf) + @staticmethod + def combine_bins_mtb_mts_dragonfly(t_self, resources, elf, binf): + """A hook for the MTB MTS Dragonfly""" + MTSCode._combine_bins_helper("MTB_MTS_DRAGONFLY", binf) + class MCU_NRF51Code(object): """NRF51 Hooks""" @staticmethod diff --git a/tools/test.py b/tools/test.py index 7b4f631b3f2..8e43274f628 100644 --- a/tools/test.py +++ b/tools/test.py @@ -144,7 +144,7 @@ if not config: args_error(parser, "argument --test-config contains invalid path or identifier") elif not options.app_config: - config = TestConfig.get_default_config(mcu) + config = TestConfig.get_default_config(options.source_dir or ['.'], mcu) else: config = options.app_config diff --git a/tools/test/detect_targets_test.py b/tools/test/detect_targets_test.py index be21a32956b..20917719fee 100644 --- a/tools/test/detect_targets_test.py +++ b/tools/test/detect_targets_test.py @@ -28,42 +28,60 @@ class MbedLsToolsMock(): def __init__(self, test_type): self.interface_test_type = test_type - def get_details_txt(self, mount_point): - return self.details_txt_types[self.interface_test_type]; + def list_mbeds(self, unique_names=False, read_details_txt=False): + return self.mbed_types[self.interface_test_type]; # Static details.txt types. - details_txt_types = { - 'details_valid_interface_version' : { - 'Unique ID': '0226000029164e45002f0012706e0006f301000097969900', - 'HIF ID': '97969900', - 'Auto Reset': '0', - 'Automation allowed': '0', - 'Daplink Mode': 'Interface', - 'Interface Version': '0240', - 'Git SHA': 'c765cbb590f57598756683254ca38b211693ae5e', - 'Local Mods': '0', - 'USB Interfaces': 'MSD, CDC, HID', - 'Interface CRC': '0x26764ebf' - }, - 'details_valid_version' : { - 'Version': '0226', - 'Build': 'Aug 24 2015 17:06:30', - 'Git Commit SHA': '27a236b9fe39c674a703c5c89655fbd26b8e27e1', - 'Git Local mods': 'Yes' - }, - 'details_missing_interface_version' : { - 'Unique ID': '0226000033514e450044500585d4001de981000097969900', - 'HIC ID': '97969900', - 'Auto Reset': '0', - 'Automation allowed': '0', - 'Overflow detection': '0', - 'Daplink Mode': 'Interface', - 'Git SHA': 'b403a07e3696cee1e116d44cbdd64446e056ce38', - 'Local Mods': '0', - 'USB Interfaces': 'MSD, CDC, HID', - 'Interface CRC': '0x4d98bf7e', - 'Remount count': '0' - }, + mbed_types = { + 'details_valid_interface_version' : [{ + 'daplink_hic_id': u'97969900', + 'daplink_version': u'0244', + 'target_id': u'0240000034544e45001500048e41001b8321000097969900', + 'serial_port': u'COM3', + 'target_id_usb_id': u'0240000034544e45001500048e41001b8321000097969900', + 'daplink_auto_reset': u'0', + 'daplink_git_sha': u'392f85aa88a41125dec0b963ce73c6795b8bdd0d', + 'daplink_interface_version': u'0244', + 'daplink_overflow_detection': u'0', + 'daplink_daplink_mode': u'Interface', + 'target_id_mbed_htm': u'0240000034544e45001500048e41001b8321000097969900', + 'mount_point': 'D:', + 'daplink_automation_allowed': u'0', + 'daplink_interface_crc': u'0xc525d856', + 'daplink_local_mods': u'0', + 'daplink_unique_id': u'0240000034544e45001500048e41001b8321000097969900', + 'daplink_remount_count': u'0', + 'daplink_bootloader_crc': u'0xc4ebf65c', + 'platform_name': u'K64F', + 'platform_name_unique': u'K64F[0]', + 'daplink_bootloader_version': u'0244', + 'daplink_usb_interfaces': u'MSD, CDC, HID' + + }], + 'details_missing_interface_version' : [{ + 'daplink_hic_id': u'97969900', + 'target_id': u'0240000034544e45001500048e41001b8321000097969900', + 'serial_port': u'COM3', + 'target_id_usb_id': u'0240000034544e45001500048e41001b8321000097969900', + 'daplink_auto_reset': u'0', + 'daplink_git_sha': u'392f85aa88a41125dec0b963ce73c6795b8bdd0d', + 'daplink_interface_version': u'0244', + 'daplink_overflow_detection': u'0', + 'daplink_daplink_mode': u'Interface', + 'target_id_mbed_htm': u'0240000034544e45001500048e41001b8321000097969900', + 'mount_point': 'D:', + 'daplink_automation_allowed': u'0', + 'daplink_interface_crc': u'0xc525d856', + 'daplink_local_mods': u'0', + 'daplink_unique_id': u'0240000034544e45001500048e41001b8321000097969900', + 'daplink_remount_count': u'0', + 'daplink_bootloader_crc': u'0xc4ebf65c', + 'platform_name': u'K64F', + 'platform_name_unique': u'K64F[0]', + 'daplink_bootloader_version': u'0244', + 'daplink_usb_interfaces': u'MSD, CDC, HID' + + }], 'details_invalid_none' : None } @@ -84,6 +102,7 @@ def setUp(self): """ self.missing_mount_point = None self.mount_point = "D:" + self.invalid_mount_point = "F:" def tearDown(self): """ @@ -102,21 +121,9 @@ def test_interface_version_valid(self, mbed_lstools_mock): :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock :return """ - - interface_version = get_interface_version(self.mount_point) - assert interface_version == '0240' - @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_version')) - def test_version_valid(self, mbed_lstools_mock): - """ - Test that checks function returns correctly when given a valid Version - - :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock - :return - """ - interface_version = get_interface_version(self.mount_point) - assert interface_version == '0226' + assert interface_version == '0244' @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_missing_interface_version')) def test_interface_version_missing_interface_version(self, mbed_lstools_mock): @@ -143,7 +150,19 @@ def test_version_none(self, mbed_lstools_mock): interface_version = get_interface_version(self.mount_point) assert interface_version == 'unknown' - + + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_interface_version')) + def test_interface_version_wrong_mount_point(self, mbed_lstools_mock): + """ + Test that checks function returns correctly when there is no board attached to supplied mount point. + + :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock + :return + """ + + interface_version = get_interface_version(self.invalid_mount_point) + assert interface_version == 'unknown' + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none')) def test_interface_version_missing_mount_point(self, mbed_lstools_mock): """ diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index 23f17c1ff80..af369e4b5cb 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -198,6 +198,21 @@ "export": true, "auto-update" : true }, + { + "name": "mbed-os-example-filesystem", + "github":"https://github.com/ARMmbed/mbed-os-example-filesystem", + "mbed": [ + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-filesystem" + ], + "test-repo-source": "github", + "features" : [], + "targets" : ["K64F"], + "toolchains" : [], + "exporters": [], + "compile" : true, + "export": true, + "auto-update" : true + }, { "name": "nanostack-border-router", "github":"https://github.com/ARMmbed/nanostack-border-router", diff --git a/tools/test/memap/gcc.map b/tools/test/memap/gcc.map index 58ff289e973..01e16cb868d 100644 --- a/tools/test/memap/gcc.map +++ b/tools/test/memap/gcc.map @@ -8,6 +8,7 @@ Linker script and memory map 0x000000000001b200 0xc0 /common/path/startup/startup.o 0x000000000001b200 startup() 0x0000000000024020 0x8 /usr/lib/gcc/arm-none-eabi/7.1.0/../../../../arm-none-eabi/lib/armv6-m/libd16M_tlf.a(__main.o) + 0x0000000000024020 0x8 /usr/lib/gcc/arm-none-eabi/7.1.0/../../../../arm-none-eabi/lib/armv6-m/foo.o .data 0x0000000020002ef8 0xac8 load address 0x000000000002ca38 0x0000000020002ef8 __data_start__ = . diff --git a/tools/test/memap/iar.map b/tools/test/memap/iar.map index 0fc3aae55d3..ba3112a12fe 100644 --- a/tools/test/memap/iar.map +++ b/tools/test/memap/iar.map @@ -10,12 +10,9 @@ # Command line = # -f # /common/path/.link_files.txt -# (-o -# --map=/common/path/project.map -# /common/path/project.elf -# /common/path/main.o -# /common/path/startup/startup.o -# /common/path/irqs/irqs.o +# (-o /common/path/project.elf +# --map=/common/path/project.map /common/path/main.o +# /common/path/startup/startup.o /common/path/irqs/irqs.o # /common/path/data/data.o # ############################################################################### diff --git a/tools/test/memap/memap_test.py b/tools/test/memap/memap_test.py index a0c84dda51d..77259a721b0 100644 --- a/tools/test/memap/memap_test.py +++ b/tools/test/memap/memap_test.py @@ -20,6 +20,7 @@ import pytest +import tools.memap from tools.memap import MemapParser from copy import deepcopy @@ -137,7 +138,7 @@ def memap_parser(): return memap_parser -def generate_test_helper(memap_parser, format, depth, file_output=None): +def generate_test_helper(memap_parser, format, depth, sep, file_output=None): """ Helper that tests that the member variables "modules" is unchanged after calling "generate_output" @@ -147,17 +148,21 @@ def generate_test_helper(memap_parser, format, depth, file_output=None): :param format: the file type to output :param file_output: the file to output to """ - old_modules = deepcopy(memap_parser.modules) + tools.memap.sep = sep memap_parser.generate_output(format, depth, file_output=file_output) assert memap_parser.modules == old_modules,\ "generate_output modified the 'modules' property" + for file_name in memap_parser.short_modules: + assert(len(file_name.split(tools.memap.sep)) <= depth) + @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_report_computed(memap_parser, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_report_computed(memap_parser, depth, sep): """ Test that a report and summary are computed @@ -165,7 +170,7 @@ def test_report_computed(memap_parser, depth): :param depth: the detail of the output """ - memap_parser.generate_output('table', depth) + memap_parser.generate_output('table', depth, sep) # Report is created after generating output assert memap_parser.mem_summary @@ -173,17 +178,19 @@ def test_report_computed(memap_parser, depth): @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_generate_output_table(memap_parser, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_generate_output_table(memap_parser, depth, sep): """ Test that an output of type "table" can be generated correctly :param memap_parser: Mocked parser :param depth: the detail of the output """ - generate_test_helper(memap_parser, 'table', depth) + generate_test_helper(memap_parser, 'table', depth, sep) @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_generate_output_json(memap_parser, tmpdir, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_generate_output_json(memap_parser, tmpdir, depth, sep): """ Test that an output of type "json" can be generated correctly :param memap_parser: Mocked parser @@ -191,13 +198,14 @@ def test_generate_output_json(memap_parser, tmpdir, depth): :param depth: the detail of the output """ file_name = str(tmpdir.join('output.json').realpath()) - generate_test_helper(memap_parser, 'json', depth, file_name) + generate_test_helper(memap_parser, 'json', depth, sep, file_name) assert isfile(file_name), "Failed to create json file" json.load(open(file_name)) @pytest.mark.parametrize("depth", [1, 2, 20]) -def test_generate_output_csv_ci(memap_parser, tmpdir, depth): +@pytest.mark.parametrize("sep", ["\\", "/"]) +def test_generate_output_csv_ci(memap_parser, tmpdir, depth, sep): """ Test ensures that an output of type "csv-ci" can be generated correctly @@ -206,5 +214,5 @@ def test_generate_output_csv_ci(memap_parser, tmpdir, depth): :param depth: the detail of the output """ file_name = str(tmpdir.join('output.csv').realpath()) - generate_test_helper(memap_parser, 'csv-ci', depth, file_name) + generate_test_helper(memap_parser, 'csv-ci', depth, sep, file_name) assert isfile(file_name), "Failed to create csv-ci file" diff --git a/tools/test/memap/parse_test.py b/tools/test/memap/parse_test.py index 51eb9cae05a..210a6fa9e27 100644 --- a/tools/test/memap/parse_test.py +++ b/tools/test/memap/parse_test.py @@ -5,7 +5,7 @@ import pytest -from tools.memap import MemapParser +from tools.memap import MemapParser, _ArmccParser from copy import deepcopy @@ -19,10 +19,12 @@ def test_parse_armcc(): memap = MemapParser() - memap.parse_map_file_armcc(open(join(dirname(__file__), "arm.map"))) + memap.parse(join(dirname(__file__), "arm.map"), "ARM") + assert memap.modules == PARSED_ARM_DATA + memap.parse(join(dirname(__file__), "arm.map"), "UARM") assert memap.modules == PARSED_ARM_DATA -PARSED_IAR_GCC_DATA = { +PARSED_IAR_DATA = { "startup/startup.o": {".text": 0xc0}, "[lib]/d16M_tlf.a/__main.o": {".text": 8}, "irqs/irqs.o": {".text": 0x98}, @@ -32,17 +34,28 @@ def test_parse_armcc(): def test_parse_iar(): memap = MemapParser() - memap.parse_map_file_iar(open(join(dirname(__file__), "iar.map"))) - assert memap.modules == PARSED_IAR_GCC_DATA + memap.parse(join(dirname(__file__), "iar.map"), "IAR") + assert memap.modules == PARSED_IAR_DATA + +PARSED_GCC_DATA = { + "startup/startup.o": {".text": 0xc0}, + "[lib]/d16M_tlf.a/__main.o": {".text": 8}, + "[lib]/misc/foo.o": {".text": 8}, + "irqs/irqs.o": {".text": 0x98}, + "data/data.o": {".data": 0x18, ".bss": 0x198}, + "main.o": {".text": 0x36}, +} def test_parse_gcc(): memap = MemapParser() - memap.parse_map_file_gcc(open(join(dirname(__file__), "gcc.map"))) - assert memap.modules == PARSED_IAR_GCC_DATA + memap.parse(join(dirname(__file__), "gcc.map"), "GCC_ARM") + assert memap.modules == PARSED_GCC_DATA + memap.parse(join(dirname(__file__), "gcc.map"), "GCC_CR") + assert memap.modules == PARSED_GCC_DATA def test_add_empty_module(): - memap = MemapParser() + memap = _ArmccParser() old_modules = deepcopy(memap.modules) memap.module_add("", 8, ".data") assert(old_modules == memap.modules) @@ -52,7 +65,7 @@ def test_add_empty_module(): assert(old_modules == memap.modules) def test_add_full_module(): - memap = MemapParser() + memap = _ArmccParser() old_modules = deepcopy(memap.modules) memap.module_add("main.o", 8, ".data") assert(old_modules != memap.modules) diff --git a/tools/test_api.py b/tools/test_api.py index 2e7d60a275f..4569ea35972 100644 --- a/tools/test_api.py +++ b/tools/test_api.py @@ -28,6 +28,7 @@ import datetime import threading import ctypes +import functools from types import ListType from colorama import Fore, Back, Style from prettytable import PrettyTable @@ -71,7 +72,6 @@ from tools.utils import argparse_uppercase_type from tools.utils import argparse_lowercase_type from tools.utils import argparse_many -from tools.utils import get_path_depth import tools.host_tests.host_tests_plugins as host_tests_plugins @@ -2019,9 +2019,15 @@ def find_tests(base_dir, target_name, toolchain_name, app_config=None): toolchain_name: name of the toolchain to use for scanning (ex. 'GCC_ARM') options: Compile options to pass to the toolchain (ex. ['debug-info']) app_config - location of a chosen mbed_app.json file + + returns a dictionary where keys are the test name, and the values are + lists of paths needed to biuld the test. """ + # Temporary structure: tests referenced by (name, base, group, case) tuple tests = {} + # List of common folders: (predicate function, path) tuple + commons = [] # Prepare the toolchain toolchain = prepare_toolchain([base_dir], None, target_name, toolchain_name, @@ -2042,32 +2048,52 @@ def find_tests(base_dir, target_name, toolchain_name, app_config=None): # Loop through all subdirectories for d in test_resources.inc_dirs: - # If the test case folder is not called 'host_tests' and it is + # If the test case folder is not called 'host_tests' or 'COMMON' and it is # located two folders down from the main 'TESTS' folder (ex. TESTS/testgroup/testcase) # then add it to the tests - path_depth = get_path_depth(relpath(d, walk_base_dir)) - if path_depth == 2: + relative_path = relpath(d, walk_base_dir) + relative_path_parts = os.path.normpath(relative_path).split(os.sep) + if len(relative_path_parts) == 2: test_group_directory_path, test_case_directory = os.path.split(d) test_group_directory = os.path.basename(test_group_directory_path) - # Check to make sure discoverd folder is not in a host test directory - if test_case_directory != 'host_tests' and test_group_directory != 'host_tests': + # Check to make sure discoverd folder is not in a host test directory or common directory + special_dirs = ['host_tests', 'COMMON'] + if test_group_directory not in special_dirs and test_case_directory not in special_dirs: test_name = test_path_to_name(d, base_dir) - tests[test_name] = d + tests[(test_name, walk_base_dir, test_group_directory, test_case_directory)] = [d] + + # Also find any COMMON paths, we'll add these later once we find all the base tests + if 'COMMON' in relative_path_parts: + if relative_path_parts[0] != 'COMMON': + def predicate(base_pred, group_pred, (name, base, group, case)): + return base == base_pred and group == group_pred + commons.append((functools.partial(predicate, walk_base_dir, relative_path_parts[0]), d)) + else: + def predicate(base_pred, (name, base, group, case)): + return base == base_pred + commons.append((functools.partial(predicate, walk_base_dir), d)) - return tests + # Apply common directories + for pred, path in commons: + for test_identity, test_paths in tests.iteritems(): + if pred(test_identity): + test_paths.append(path) + + # Drop identity besides name + return {name: paths for (name, _, _, _), paths in tests.iteritems()} def print_tests(tests, format="list", sort=True): """Given a dictionary of tests (as returned from "find_tests"), print them in the specified format""" if format == "list": for test_name in sorted(tests.keys()): - test_path = tests[test_name] + test_path = tests[test_name][0] print "Test Case:" print " Name: %s" % test_name print " Path: %s" % test_path elif format == "json": - print json.dumps(tests, indent=2) + print json.dumps({test_name: test_path[0] for test_name, test_paths in tests}, indent=2) else: print "Unknown format '%s'" % format sys.exit(1) @@ -2164,13 +2190,16 @@ def build_tests(tests, base_source_paths, build_path, target, toolchain_name, jobs_count = int(jobs if jobs else cpu_count()) p = Pool(processes=jobs_count) results = [] - for test_name, test_path in tests.iteritems(): - test_build_path = os.path.join(build_path, test_path) - src_path = base_source_paths + [test_path] + for test_name, test_paths in tests.iteritems(): + if type(test_paths) != ListType: + test_paths = [test_paths] + + test_build_path = os.path.join(build_path, test_paths[0]) + src_paths = base_source_paths + test_paths bin_file = None - test_case_folder_name = os.path.basename(test_path) + test_case_folder_name = os.path.basename(test_paths[0]) - args = (src_path, test_build_path, target, toolchain_name) + args = (src_paths, test_build_path, target, toolchain_name) kwargs = { 'jobs': 1, 'clean': clean, diff --git a/tools/test_configs/ESP8266Interface.json b/tools/test_configs/ESP8266Interface.json new file mode 100644 index 00000000000..eba1c0cb4ae --- /dev/null +++ b/tools/test_configs/ESP8266Interface.json @@ -0,0 +1,37 @@ +{ + "config": { + "header-file": { + "help" : "String for including your driver header file", + "value" : "\"ESP8266Interface.h\"" + }, + "object-construction" : { + "value" : "new ESP8266Interface( D1, D0, false )" + }, + "connect-statement" : { + "help" : "Must use 'net' variable name, replace WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL with your WiFi settings", + "value" : "((ESP8266Interface *)net)->connect(WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL)" + }, + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"195.34.89.241\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + }, + "tcp-echo-prefix" : { + "help" : "Some servers send a prefix before echoed message", + "value" : "\"u-blox AG TCP/UDP test service\\n\"" + }, + "tcp-client-echo-buffer-size" : { + "help" : "Number of bytes to be send to echo server", + "value" : "200" + }, + "ESP8266-TX": { + "value":"D1" + }, + "ESP8266-RX": { + "value":"D0" + } + } +} diff --git a/tools/test_configs/__init__.py b/tools/test_configs/__init__.py index 90666baf248..4f884465e76 100644 --- a/tools/test_configs/__init__.py +++ b/tools/test_configs/__init__.py @@ -1,7 +1,8 @@ -from os.path import dirname, abspath, join +from os.path import dirname, abspath, join, exists from tools.utils import json_file_to_dict from tools.targets import TARGET_MAP +from tools.config import Config CONFIG_DIR = dirname(abspath(__file__)) CONFIG_MAP = json_file_to_dict(join(CONFIG_DIR, "config_paths.json")) @@ -28,12 +29,14 @@ def get_config_path(conf_name, target_name): else: return None -def get_default_config(target_name): +def get_default_config(source_dir, target_name): if target_name in TARGET_CONFIGS: config_name = TARGET_CONFIGS[target_name]['default_test_configuration'] if config_name == "NONE": return None return join(CONFIG_DIR, CONFIG_MAP[config_name]) + elif Config.find_app_config(source_dir): + return None elif (target_name in TARGET_MAP and 'LWIP' in TARGET_MAP[target_name].features): return join(CONFIG_DIR, CONFIG_MAP["ETHERNET"]) else: diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json index 3b85ad608ee..17937fa28fe 100644 --- a/tools/test_configs/config_paths.json +++ b/tools/test_configs/config_paths.json @@ -4,5 +4,6 @@ "HEAPBLOCKDEVICE_AND_ETHERNET": "HeapBlockDeviceAndEthernetInterface.json", "ODIN_WIFI" : "OdinInterface.json", "ODIN_ETHERNET" : "Odin_EthernetInterface.json", - "REALTEK_WIFI" : "RealtekInterface.json" + "REALTEK_WIFI" : "RealtekInterface.json", + "ESP8266_WIFI" : "ESP8266Interface.json" } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index a48e6e16fe3..c25c546faaf 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -9,7 +9,7 @@ }, "K64F": { "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET", - "test_configurations": ["HEAPBLOCKDEVICE_AND_ETHERNET"] + "test_configurations": ["HEAPBLOCKDEVICE_AND_ETHERNET", "ESP8266_WIFI", "ETHERNET"] }, "NUCLEO_F429ZI": { "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET", diff --git a/tools/tests.py b/tools/tests.py index 4b31665d34a..0c238758645 100644 --- a/tools/tests.py +++ b/tools/tests.py @@ -320,7 +320,7 @@ "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_A28", "description": "CAN loopback test", @@ -334,7 +334,7 @@ "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_A29", "description": "i2c_master_slave_asynch", @@ -589,7 +589,7 @@ "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "NUCLEO_F207ZG", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_30", "description": "CAN network test using interrupts", @@ -600,7 +600,7 @@ "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE", "NUCLEO_F446ZE", "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG", "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG", - "DISCO_F413ZH"] + "DISCO_F413ZH", "NUCLEO_F413ZH"] }, { "id": "MBED_31", "description": "PWM LED test", diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index 0df502303f0..e8f7549eaa8 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -819,7 +819,7 @@ def copy_files(self, files_paths, trg_path, resources=None, rel_path=None): def relative_object_path(self, build_path, base_dir, source): source_dir, name, _ = split_path(source) - obj_dir = join(build_path, relpath(source_dir, base_dir)) + obj_dir = relpath(join(build_path, relpath(source_dir, base_dir))) if obj_dir is not self.prev_dir: self.prev_dir = obj_dir mkdir(obj_dir) diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 4cc46aa0c2b..173b6af36b0 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -34,7 +34,7 @@ class ARM(mbedToolchain): DEP_PATTERN = re.compile('\S+:\s(?P.+)\n') SHEBANG = "#! armcc -E" SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", - "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"] + "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD", "Cortex-A9"] @staticmethod def check_executable(): @@ -293,7 +293,7 @@ class ARMC6(ARM_STD): SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD", "Cortex-M23", "Cortex-M23-NS", "Cortex-M33", - "CortexM33-NS"] + "CortexM33-NS", "Cortex-A9"] @staticmethod def check_executable(): return mbedToolchain.generic_check_executable("ARMC6", "armclang", 1)