Update to v6.2.0

.github/workflows/core.yml

@@ -16,7 +16,7 @@ concurrency:
 
 jobs:
   lit:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
 
     env:
       ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }}

.github/workflows/corevalidation.yml

@@ -23,7 +23,7 @@ jobs:
       matrix:
         compiler: [AC6, GCC, Clang]
 
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
 
     env:
       ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }}

CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h

@@ -67,8 +67,8 @@ __IAR_FT uint32_t __get_SP_usr(void)
     "MRS     %0, cpsr   \n"
     "CPS     #0x1F      \n" // no effect in USR mode
     "MOV     %1, sp     \n"
-    "MSR     cpsr_c, %2 \n" // no effect in USR mode
-    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+    "MSR     cpsr_c, %0 \n" // no effect in USR mode
+    "ISB" :  "+r"(cpsr), "=r"(result) :: "memory"
    );
   return result;
 }
@@ -80,8 +80,8 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
     "MRS     %0, cpsr   \n"
     "CPS     #0x1F      \n" // no effect in USR mode
     "MOV     sp, %1     \n"
-    "MSR     cpsr_c, %2 \n" // no effect in USR mode
-    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+    "MSR     cpsr_c, %0 \n" // no effect in USR mode
+    "ISB" : "+r"(cpsr) : "r" (topOfProcStack) : "memory"
    );
 }
 

CMSIS/Core/Include/cmsis_iccarm.h

@@ -348,21 +348,21 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
 {
   uint32_t res;
-  __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+  __ASM volatile ("LDRBT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory");
   return ((uint8_t)res);
 }
 
 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
 {
   uint32_t res;
-  __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+  __ASM volatile ("LDRHT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory");
   return ((uint16_t)res);
 }
 
 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
 {
   uint32_t res;
-  __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+  __ASM volatile ("LDRT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory");
   return res;
 }
 

CMSIS/Core/Include/core_ca.h

@@ -641,13 +641,13 @@ typedef union
   uint32_t w;                            /*!< \brief Type      used for word access */
 } ISR_Type;
 
-#define ISR_A_Pos                        13U                                    /*!< \brief ISR: A Position */
+#define ISR_A_Pos                        8U                                     /*!< \brief ISR: A Position */
 #define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \brief ISR: A Mask */
 
-#define ISR_I_Pos                        12U                                    /*!< \brief ISR: I Position */
+#define ISR_I_Pos                        7U                                     /*!< \brief ISR: I Position */
 #define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \brief ISR: I Mask */
 
-#define ISR_F_Pos                        11U                                    /*!< \brief ISR: F Position */
+#define ISR_F_Pos                        6U                                     /*!< \brief ISR: F Position */
 #define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \brief ISR: F Mask */
 
 /* DACR Register */
@@ -918,7 +918,7 @@ typedef struct
 
 /* GICDistributor SGIR Register */
 #define GICDistributor_SGIR_INTID_Pos         0U                                                   /*!< GICDistributor SGIR: INTID Position */
-#define GICDistributor_SGIR_INTID_Msk         (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/)          /*!< GICDistributor SGIR: INTID Mask */
+#define GICDistributor_SGIR_INTID_Msk         (0xFU /*<< GICDistributor_SGIR_INTID_Pos*/)          /*!< GICDistributor SGIR: INTID Mask */
 #define GICDistributor_SGIR_INTID(x)          (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk)
 
 #define GICDistributor_SGIR_NSATT_Pos         15U                                                  /*!< GICDistributor SGIR: NSATT Position */
@@ -1015,7 +1015,7 @@ typedef struct
 
 /* GICInterface HPPIR Register */
 #define GICInterface_HPPIR_INTID_Pos        0U                                               /*!< PTIM HPPIR: INTID Position */
-#define GICInterface_HPPIR_INTID_Msk        (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/)  /*!< PTIM HPPIR: INTID Mask */
+#define GICInterface_HPPIR_INTID_Msk        (0x3FFU /*<< GICInterface_HPPIR_INTID_Pos*/)  /*!< PTIM HPPIR: INTID Mask */
 #define GICInterface_HPPIR_INTID(x)         (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk)
 
 /* GICInterface ABPR Register */
@@ -1077,8 +1077,8 @@ typedef struct
 #define GICInterface_IIDR_ProductID(x)      (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk)
 
 /* GICInterface DIR Register */
-#define GICInterface_DIR_INTID_Pos          0U                                              /*!< PTIM DIR: INTID Position */
-#define GICInterface_DIR_INTID_Msk          (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/)   /*!< PTIM DIR: INTID Mask */
+#define GICInterface_DIR_INTID_Pos          0U                                              /*!< GICInterface DIR: INTID Position */
+#define GICInterface_DIR_INTID_Msk          (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/)   /*!< GICInterface DIR: INTID Mask */
 #define GICInterface_DIR_INTID(x)           (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk)
 #endif /*  (__GIC_PRESENT == 1U) || defined(DOXYGEN) */
 
@@ -1645,7 +1645,7 @@ __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
 */
 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
 {
-  return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
+  return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) << 1U)) & 3UL;
 }
 
 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
@@ -2700,7 +2700,7 @@ __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type m
         *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
         break;
       case WB_NO_WA:
-        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT) | (1 << SECTION_TEX0_SHIFT);
         break;
     }
   }
@@ -2768,7 +2768,7 @@ __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem,
           *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
           break;
         case WB_NO_WA:
-          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+          *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
           break;
       }
     }

CMSIS/Core/Include/m-profile/armv8m_mpu.h

@@ -188,7 +188,7 @@ typedef struct {
   \brief  Read MPU Type Register
   \return Number of MPU regions
 */
-__STATIC_INLINE uint32_t ARM_MPU_TYPE()
+__STATIC_INLINE uint32_t ARM_MPU_TYPE(void)
 {
   return ((MPU->TYPE) >> 8);
 }

CMSIS/Core/Include/r-profile/cmsis_iccarm_r.h

@@ -69,10 +69,10 @@ __IAR_FT uint32_t __get_SP_usr(void) {
   __ASM volatile("MRS     %0, cpsr   \n"
                  "CPS     #0x1F      \n" // no effect in USR mode
                  "MOV     %1, sp     \n"
-                 "MSR     cpsr_c, %2 \n" // no effect in USR mode
+                 "MSR     cpsr_c, %0 \n" // no effect in USR mode
                  "ISB"
-                 : "=r"(cpsr), "=r"(result)
-                 : "r"(cpsr)
+                 : "+r"(cpsr), "=r"(result)
+                 : 
                  : "memory");
   return result;
 }
@@ -84,8 +84,8 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack) {
                  "MOV     sp, %1     \n"
                  "MSR     cpsr_c, %2 \n" // no effect in USR mode
                  "ISB"
-                 : "=r"(cpsr)
-                 : "r"(topOfProcStack), "r"(cpsr)
+                 : "+r"(cpsr)
+                 : "r"(topOfProcStack)
                  : "memory");
 }
 

CMSIS/Core/Source/irq_ctrl_gic.c

@@ -24,7 +24,12 @@
 
 #include <stddef.h>
 
+#if defined(_RTE_)
 #include "RTE_Components.h"
+#elif !defined(CMSIS_device_header)
+#error "CMSIS_device_header must be defined to point to CMSIS device header"
+#endif
+
 #include CMSIS_device_header
 
 #include "irq_ctrl.h"

CMSIS/Core/Test/README.md

@@ -71,19 +71,16 @@ Currently, the following build configurations are provided:
 
 ## Prerequisites
 
-The following tools are required to build and run the CoreValidation tests:
-
-- [CMSIS-Toolbox 2.1.0](https://artifacts.keil.arm.com/cmsis-toolbox/2.1.0/)*
-- [CMake 3.25.2](https://cmake.org/download/)*
-- [Ninja 1.10.2](https://github.com/ninja-build/ninja/releases)*
-- [Arm Compiler 6.22](https://artifacts.tools.arm.com/arm-compiler/6.22/45/)*
-- [GCC Compiler 13.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/13.2.1/)*
-- [Clang Compiler 18.1.3](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-18.1.3)*
-- [Arm Virtual Hardware for Cortex-M based on FastModels 11.22.39](https://artifacts.keil.arm.com/avh/11.22.39/)*
+The following tools are required to build and run the Core tests:
+
+- [Arm Compiler 6.23](https://artifacts.tools.arm.com/arm-compiler/6.23/32/)*
+- [GCC Compiler 14.2.1](https://artifacts.keil.arm.com/arm-none-eabi-gcc/14.2.1/)*
+- [Clang Compiler 19.1.5](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-19.1.5)*
 - [Python 3.9](https://www.python.org/downloads/)
 - [LLVM FileCheck](https://github.com/llvm/llvm-project/releases/)
   - Ubuntu package `llvm-<version>-tools`
   - MacOS Homebrew formula `llvm`
+    Symlink FileCheck binary `ln -s /opt/homebrew/opt/llvm/bin/FileCheck /opt/homebrew/bin`
 
 The executables need to be present on the `PATH`.
 For tools distributed via vcpkg (*) this can be achieved automatically:
@@ -126,7 +123,7 @@ GCC         Cortex-M3  none        33/33
 
 The summary lists the amount of test cases executed and passed.
 
-## Analyse failing test cases
+## Analyze failing test cases
 
 In case of failing test cases, one can run a single test case with verbose output like this:
 
@@ -146,7 +143,7 @@ Testing Time: 0.10s
   Passed: 1
 ```
 
-The output reveales wich commands are chained and their error output if any.
+The output reveals which commands are chained and their error output if any.
 
 Failing FileCheck requires in detail analysis of the `// CHECK` annotations in the test source file
 against the `llvm-objdump` output of the test compilation.

CMSIS/Core/Test/lit.cfg.py

@@ -791,38 +791,38 @@ def get_ccflags(self):
 
 class Toolchain_Clang(Toolchain):
     TARGET = {
-        'CM0': 'thumbv6m-none-unknown-eabi',
-        'CM0plus': 'thumbv6m-none-unknown-eabi',
-        'CM3': 'thumbv7m-none-unknown-eabi',
-        'CM4': 'thumbv7em-none-unknown-eabi',
-        'CM4FP': 'thumbv7em-none-unknown-eabihf',
-        'CM7': 'thumbv7em-none-unknown-eabi',
-        'CM7SP': 'thumbv7em-none-unknown-eabihf',
-        'CM7DP': 'thumbv7em-none-unknown-eabihf',
-        'CM23': 'thumbv8m.base-none-unknown-eabi',
-        'CM23S': 'thumbv8m.base-none-unknown-eabi',
-        'CM23NS': 'thumbv8m.base-none-unknown-eabi',
-        'CM33': 'thumbv8m.main-none-unknown-eabihf',
-        'CM33S': 'thumbv8m.main-none-unknown-eabihf',
-        'CM33NS': 'thumbv8m.main-none-unknown-eabihf',
-        'CM35P': 'thumbv8m.main-none-unknown-eabihf',
-        'CM35PS': 'thumbv8m.main-none-unknown-eabihf',
-        'CM35PNS': 'thumbv8m.main-none-unknown-eabihf',
-        'CM52': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM52S': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM52NS': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM55': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM55S': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM55NS': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM85': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM85S': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CM85NS': 'thumbv8.1m.main-none-unknown-eabihf',
-        'CA5': 'armv7-none-unknown-eabi',
-        'CA5neon': 'armv7-none-unknown-eabihf',
-        'CA7': 'armv7-none-unknown-eabi',
-        'CA7neon': 'armv7-none-unknown-eabihf',
-        'CA9': 'armv7-none-unknown-eabi',
-        'CA9neon': 'armv7-none-unknown-eabihf'
+        'CM0': 'thumbv6m-none-eabi',
+        'CM0plus': 'thumbv6m-none-eabi',
+        'CM3': 'thumbv7m-none-eabi',
+        'CM4': 'thumbv7em-none-eabi',
+        'CM4FP': 'thumbv7em-none-eabihf',
+        'CM7': 'thumbv7em-none-eabi',
+        'CM7SP': 'thumbv7em-none-eabihf',
+        'CM7DP': 'thumbv7em-none-eabihf',
+        'CM23': 'thumbv8m.base-none-eabi',
+        'CM23S': 'thumbv8m.base-none-eabi',
+        'CM23NS': 'thumbv8m.base-none-eabi',
+        'CM33': 'thumbv8m.main-none-eabihf',
+        'CM33S': 'thumbv8m.main-none-eabihf',
+        'CM33NS': 'thumbv8m.main-none-eabihf',
+        'CM35P': 'thumbv8m.main-none-eabihf',
+        'CM35PS': 'thumbv8m.main-none-eabihf',
+        'CM35PNS': 'thumbv8m.main-none-eabihf',
+        'CM52': 'thumbv8.1m.main-none-eabihf',
+        'CM52S': 'thumbv8.1m.main-none-eabihf',
+        'CM52NS': 'thumbv8.1m.main-none-eabihf',
+        'CM55': 'thumbv8.1m.main-none-eabihf',
+        'CM55S': 'thumbv8.1m.main-none-eabihf',
+        'CM55NS': 'thumbv8.1m.main-none-eabihf',
+        'CM85': 'thumbv8.1m.main-none-eabihf',
+        'CM85S': 'thumbv8.1m.main-none-eabihf',
+        'CM85NS': 'thumbv8.1m.main-none-eabihf',
+        'CA5': 'armv7-none-eabi',
+        'CA5neon': 'armv7-none-eabihf',
+        'CA7': 'armv7-none-eabi',
+        'CA7neon': 'armv7-none-eabihf',
+        'CA9': 'armv7-none-eabi',
+        'CA9neon': 'armv7-none-eabihf'
     }
     OPTIMIZE = {
         'none': '-O1',

CMSIS/Core/Test/src/ror.c

@@ -7,8 +7,8 @@ static volatile uint32_t b = 2u;
 
 void ror() {
     // CHECK-LABEL: <ror>:
-    // CHECK-THUMB: ror{{s|.w}} {{r[0-9]+}}, {{r[0-9]+}}
-    // CHECK-ARM: ror {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-THUMB: ror{{ne|s|.w}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: {{ror|rorne}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
     volatile uint32_t c = __ROR(a, b);
     // CHECK: {{(bx lr)|(pop {.*pc})}}
 }

CMSIS/Core/Test/vcpkg-configuration.json

@@ -1,15 +1,14 @@
 {
     "registries": [
-      {
-        "kind": "artifact",
-        "location": "https://artifacts.tools.arm.com/vcpkg-registry",
-        "name": "arm"
-      }
+        {
+            "name": "arm",
+            "kind": "artifact",
+            "location": "https://artifacts.tools.arm.com/vcpkg-registry"
+        }
     ],
     "requires": {
-      "arm:compilers/arm/armclang":"^6.22.0",
-      "arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1",
-      "arm:compilers/arm/llvm-embedded": "^18.1.3"
+        "arm:compilers/arm/armclang": "6.23.0",
+        "arm:compilers/arm/arm-none-eabi-gcc": "14.2.1",
+        "arm:compilers/arm/llvm-embedded": "19.1.5"
     }
-  }
-
+}

CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml

@@ -5,7 +5,7 @@ layer:
   components:
     # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
     - component: ARM::CMSIS:CORE
-    - component: Device:Startup
+    - component: Device:Startup&C Startup
     - component: Device:IRQ Controller:GIC
 
   misc:

CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml

@@ -5,7 +5,7 @@ layer:
   components:
     # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
     - component: ARM::CMSIS:CORE
-    - component: Device:Startup
+    - component: Device:Startup&C Startup
     - component: Device:IRQ Controller:GIC
 
   misc:

CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml

@@ -5,7 +5,7 @@ layer:
   components:
     # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
     - component: ARM::CMSIS:CORE
-    - component: Device:Startup
+    - component: Device:Startup&C Startup
     - component: Device:IRQ Controller:GIC
 
   misc:

CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt

@@ -14,8 +14,6 @@ armcortexm7ct.semihosting-cwd=""                      # (string, init-time) defa
 armcortexm7ct.DP_FLOAT=1                              # (bool  , init-time) default = '1'      : Support 8-byte floats
 armcortexm7ct.dcache-size=32768                       # (int   , init-time) default = '0x8000' : L1 D-cache size in bytes
 armcortexm7ct.dcache-state_modelled=1                 # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation
-armcortexm7ct.dcache-ways=4                           # (int   , init-time) default = '0x4'    : L1 D-cache ways (sets are implicit from size)
 armcortexm7ct.icache-size=32768                       # (int   , init-time) default = '0x8000' : L1 I-cache size in bytes
 armcortexm7ct.icache-state_modelled=1                 # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation
-armcortexm7ct.icache-ways=2                           # (int   , init-time) default = '0x2'    : L1 I-cache ways (sets are implicit from size)
 #----------------------------------------------------------------------------------------------

CMSIS/CoreValidation/Layer/Target/CM85/model_config.txt

@@ -5,8 +5,7 @@ fvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) defa
 fvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic
 cpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support
 cpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
-cpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI
-# cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
+cpu0.CFGPACBTI=1                                      # (bool  , init-time) default = '0'      : Enables support for the Pointer Authentication and Branch Target Identification (PACBTI) Extension. FALSE: Disabled, TRUE:PAC implemented using the QARMA5 algorithm with BTI
 cpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
 cpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
 cpu0.semihosting-cmd_line=""                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls