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boards: qemu: combine riscv boards
combine riscv boards and use the dt props to configure qemu with the right riscv isa and extensions Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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‎boards/qemu/riscv/Kconfig‎

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# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_QEMU_RISCV
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select QEMU_TARGET
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select HAS_COVERAGE_SUPPORT

‎boards/qemu/riscv/Kconfig.defconfig‎

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# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_QEMU_RISCV
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# Use thread local storage by default so that this feature gets more CI coverage.
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configdefault THREAD_LOCAL_STORAGE
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default y
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configdefault BUILD_OUTPUT_BIN
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default n
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configdefault QEMU_ICOUNT_SHIFT
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default 6
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endif # BOARD_QEMU_RISCV

‎boards/qemu/riscv/Kconfig.qemu_riscv‎

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# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_QEMU_RISCV
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select SOC_QEMU_VIRT_RISCV32 if BOARD_QEMU_RISCV_QEMU_VIRT_RISCV32 || BOARD_QEMU_RISCV_QEMU_VIRT_RISCV32_SMP
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select SOC_QEMU_VIRT_RISCV32E if BOARD_QEMU_RISCV_QEMU_VIRT_RISCV32E
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select SOC_QEMU_VIRT_RISCV64 if BOARD_QEMU_RISCV_QEMU_VIRT_RISCV64 || BOARD_QEMU_RISCV_QEMU_VIRT_RISCV64_SMP

‎boards/qemu/riscv/board.cmake‎

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# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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# SPDX-License-Identifier: Apache-2.0
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set(SUPPORTED_EMU_PLATFORMS qemu)
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set(riscv_isa_extensions)
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set(riscv_isa_base)
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dt_prop(riscv_isa_extensions PATH "/cpus/cpu@0" PROPERTY "riscv,isa-extensions" REQUIRED)
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dt_prop(riscv_isa_base PATH "/cpus/cpu@0" PROPERTY "riscv,isa-base" REQUIRED)
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set(qemu_riscv_cpu "${riscv_isa_base}")
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foreach(ext IN LISTS riscv_isa_extensions)
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if(ext)
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string(APPEND qemu_riscv_cpu ",${ext}=on")
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endif()
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endforeach()
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if(CONFIG_RISCV_PMP)
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string(APPEND qemu_riscv_cpu ",pmp=on,u=on")
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endif()
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if(CONFIG_64BIT)
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set(QEMU_binary_suffix riscv64)
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else()
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set(QEMU_binary_suffix riscv32)
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endif()
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set(QEMU_CPU_TYPE_${ARCH} "${qemu_riscv_cpu}")
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set(QEMU_FLAGS_${ARCH}
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-nographic
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-machine virt
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-bios none
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-m 256
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-cpu ${qemu_riscv_cpu}
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)
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board_set_debugger_ifnset(qemu)

‎boards/qemu/riscv/board.yml‎

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board:
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name: qemu_riscv
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full_name: QEMU Emulation for RISCV
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vendor: qemu
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socs:
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- name: qemu_virt_riscv32
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variants:
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- name: smp
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- name: qemu_virt_riscv32e
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- name: qemu_virt_riscv64
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variants:
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- name: smp

‎boards/qemu/riscv/doc/index.rst‎

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.. zephyr:board:: qemu_riscv
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Overview
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********
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The RISCV QEMU board configuration is used to emulate the RISCV architecture.
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Get the Toolchain and QEMU
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**************************
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The minimum version of the `Zephyr SDK tools
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<https://github.com/zephyrproject-rtos/sdk-ng/releases>`_
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with toolchain and QEMU support for the RISCV64 architecture is v0.10.2.
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Please see the :ref:`installation instructions <install-required-tools>`
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for more details.
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Applications for the ``qemu_riscv`` board configuration can be built and run in
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the usual way for emulated boards (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Flashing
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========
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While this board is emulated and you can't "flash" it, you can use this
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configuration to run basic Zephyr applications and kernel tests in the QEMU
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emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample:
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: qemu_riscv/qemu_virt_riscv32
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:goals: run
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: qemu_riscv/qemu_virt_riscv32e
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:goals: run
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: qemu_riscv/qemu_virt_riscv64
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:goals: run
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This will build an image with the synchronization sample app, boot it using
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QEMU, and display the following console output:
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.. code-block:: console
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***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
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threadA: Hello World from riscv64!
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threadB: Hello World from riscv64!
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threadA: Hello World from riscv64!
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threadB: Hello World from riscv64!
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threadA: Hello World from riscv64!
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threadB: Hello World from riscv64!
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threadA: Hello World from riscv64!
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threadB: Hello World from riscv64!
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threadA: Hello World from riscv64!
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threadB: Hello World from riscv64!
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Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
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Debugging
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=========
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Refer to the detailed overview about :ref:`application_debugging`.

‎boards/qemu/riscv/qemu_riscv_qemu_virt_riscv.dtsi‎

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/*
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* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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/ {
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &ram0;
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};
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};
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&uart0 {
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status = "okay";
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};

‎boards/qemu/riscv/qemu_riscv_qemu_virt_riscv32.dts‎

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/*
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* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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/dts-v1/;
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#include <qemu/virt-riscv32.dtsi>
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#include "qemu_riscv_qemu_virt_riscv.dtsi"

‎boards/qemu/riscv/qemu_riscv_qemu_virt_riscv32.yaml‎

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identifier: qemu_riscv/qemu_virt_riscv32
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name: QEMU Emulation for RISC-V 32-bit
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type: qemu
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simulation:
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- name: qemu
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arch: riscv
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toolchain:
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- zephyr
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supported:
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- netif
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ram: 262144
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flash: 32768
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testing:
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default: true
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ignore_tags:
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- net
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- bluetooth

‎boards/qemu/riscv/qemu_riscv_qemu_virt_riscv32_defconfig‎

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# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_STACK_SENTINEL=y
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CONFIG_XIP=n
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CONFIG_RISCV_PMP=y

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