@@ -282,11 +282,14 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
282282 return ret ;
283283 }
284284
285- #if defined(CONFIG_SOC_SERIES_STM32H7X )
285+ hdma -> Instance = STM32_DMA_GET_INSTANCE (stream -> reg , stream -> dma_channel );
286+ hdma -> Init .Request = dma_cfg .dma_slot ;
287+ hdma -> Init .Mode = DMA_NORMAL ;
288+
289+ #if defined(CONFIG_SOC_SERIES_STM32H7X ) || defined(CONFIG_SOC_SERIES_STM32L4X )
286290 hdma -> Init .PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD ;
287291 hdma -> Init .MemDataAlignment = DMA_MDATAALIGN_HALFWORD ;
288292 hdma -> Init .Priority = DMA_PRIORITY_HIGH ;
289- hdma -> Init .FIFOMode = DMA_FIFOMODE_DISABLE ;
290293 hdma -> Init .PeriphInc = DMA_PINC_DISABLE ;
291294 hdma -> Init .MemInc = DMA_MINC_ENABLE ;
292295#else
@@ -299,14 +302,15 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
299302 hdma -> Init .TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT0 ;
300303 hdma -> Init .TransferEventMode = DMA_TCEM_BLOCK_TRANSFER ;
301304#endif
302- hdma -> Instance = STM32_DMA_GET_INSTANCE (stream -> reg , stream -> dma_channel );
303- hdma -> Init .Request = dma_cfg .dma_slot ;
304- hdma -> Init .Mode = DMA_NORMAL ;
305+
306+ #if defined(CONFIG_SOC_SERIES_STM32H7X )
307+ hdma -> Init .FIFOMode = DMA_FIFOMODE_DISABLE ;
308+ #endif
305309
306310 if (stream -> dma_cfg .channel_direction == (enum dma_channel_direction )MEMORY_TO_PERIPHERAL ) {
307311 hdma -> Init .Direction = DMA_MEMORY_TO_PERIPH ;
308312
309- #if !defined(CONFIG_SOC_SERIES_STM32H7X )
313+ #if !defined(CONFIG_SOC_SERIES_STM32H7X ) && !defined( CONFIG_SOC_SERIES_STM32L4X )
310314 hdma -> Init .SrcInc = DMA_SINC_INCREMENTED ;
311315 hdma -> Init .DestInc = DMA_DINC_FIXED ;
312316#endif
@@ -315,7 +319,7 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
315319 } else {
316320 hdma -> Init .Direction = DMA_PERIPH_TO_MEMORY ;
317321
318- #if !defined(CONFIG_SOC_SERIES_STM32H7X )
322+ #if !defined(CONFIG_SOC_SERIES_STM32H7X ) && !defined( CONFIG_SOC_SERIES_STM32L4X )
319323 hdma -> Init .SrcInc = DMA_SINC_FIXED ;
320324 hdma -> Init .DestInc = DMA_DINC_INCREMENTED ;
321325#endif
@@ -334,7 +338,7 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
334338 LOG_ERR ("HAL_DMA_ConfigChannelAttributes: <Failed>" );
335339 return - EIO ;
336340 }
337- #elif !defined(CONFIG_SOC_SERIES_STM32H7X )
341+ #elif !defined(CONFIG_SOC_SERIES_STM32H7X ) && !defined( CONFIG_SOC_SERIES_STM32L4X )
338342 if (HAL_DMA_ConfigChannelAttributes (& dev_data -> hdma , DMA_CHANNEL_NPRIV ) != HAL_OK ) {
339343 LOG_ERR ("HAL_DMA_ConfigChannelAttributes: <Failed>" );
340344 return - EIO ;
@@ -449,21 +453,28 @@ static int i2s_stm32_sai_configure(const struct device *dev, enum i2s_dir dir,
449453 return - EINVAL ;
450454 }
451455
456+ /* STM32L4xx not possible to control MCLK output from SAI configuration */
457+ #if !defined(CONFIG_SOC_SERIES_STM32L4X )
452458 if (cfg -> mclk_enable && stream -> master ) {
453459 hsai -> Init .MckOutput = SAI_MCK_OUTPUT_ENABLE ;
454460 } else {
455461 hsai -> Init .MckOutput = SAI_MCK_OUTPUT_DISABLE ;
456462 }
463+ #endif
457464
458465 if (cfg -> mclk_div == (enum mclk_divider )MCLK_NO_DIV ) {
459466 hsai -> Init .NoDivider = SAI_MASTERDIVIDER_DISABLED ;
460467 } else {
461468 hsai -> Init .NoDivider = SAI_MASTERDIVIDER_ENABLE ;
469+
470+ /* MckOverSampling is not supported by all STM32L4xx MCUs */
471+ #if !defined(CONFIG_SOC_SERIES_STM32L4X )
462472 if (cfg -> mclk_div == (enum mclk_divider )MCLK_DIV_256 ) {
463473 hsai -> Init .MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE ;
464474 } else {
465475 hsai -> Init .MckOverSampling = SAI_MCK_OVERSAMPLING_ENABLE ;
466476 }
477+ #endif
467478 }
468479
469480 /* AudioFrequency */
@@ -849,4 +860,4 @@ static DEVICE_API(i2s, i2s_stm32_driver_api) = {
849860 K_MSGQ_DEFINE(queue_##index, sizeof(struct queue_item), CONFIG_I2S_STM32_SAI_BLOCK_COUNT, \
850861 4);
851862
852- DT_INST_FOREACH_STATUS_OKAY (I2S_STM32_SAI_INIT )
863+ DT_INST_FOREACH_STATUS_OKAY (I2S_STM32_SAI_INIT )
0 commit comments