diff --git a/boards/arm/nucleo_l152re/doc/index.rst b/boards/arm/nucleo_l152re/doc/index.rst index d17cd466f4b9..c42fef2e4a1a 100644 --- a/boards/arm/nucleo_l152re/doc/index.rst +++ b/boards/arm/nucleo_l152re/doc/index.rst @@ -96,13 +96,6 @@ Other hardware features are not yet supported in this Zephyr port. The default configuration can be found in the defconfig file: ``boards/arm/nucleo_l152re/nucleo_l152re_defconfig`` -System Clock -============ - -Nucleo L152RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. It should theoretically support running at 32MHz, -but a bug (under investigation) limits operations to 16MHz. - Connections and IOs =================== diff --git a/boards/arm/nucleo_l152re/nucleo_l152re_defconfig b/boards/arm/nucleo_l152re/nucleo_l152re_defconfig index 298ece5b935a..46aa0f070628 100644 --- a/boards/arm/nucleo_l152re/nucleo_l152re_defconfig +++ b/boards/arm/nucleo_l152re/nucleo_l152re_defconfig @@ -4,7 +4,7 @@ CONFIG_SOC_SERIES_STM32L1X=y CONFIG_SOC_STM32L152XE=y CONFIG_CORTEX_M_SYSTICK=y # 32MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=16000000 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000 # enable uart driver CONFIG_SERIAL=y @@ -24,7 +24,7 @@ CONFIG_CLOCK_CONTROL=y CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y # Use HSI source CONFIG_CLOCK_STM32_PLL_SRC_HSI=y -CONFIG_CLOCK_STM32_PLL_DIVISOR=4 +CONFIG_CLOCK_STM32_PLL_DIVISOR=2 # produce 32Mhz clock at PLL output CONFIG_CLOCK_STM32_PLL_MULTIPLIER=4 CONFIG_CLOCK_STM32_AHB_PRESCALER=1