diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c index a4e4b999e5514..8340d50001e06 100644 --- a/drivers/ethernet/eth_stm32_hal.c +++ b/drivers/ethernet/eth_stm32_hal.c @@ -67,24 +67,27 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #if defined(CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER) && \ DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) -#define ETH_DMA_MEM __dtcm_noinit_section +#define __eth_stm32_desc __dtcm_noinit_section +#define __eth_stm32_buf __dtcm_noinit_section +#elif defined(CONFIG_SOC_SERIES_STM32H7X) && \ + DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay) +#define __eth_stm32_desc __attribute__((section(".eth_stm32_desc"))) +#define __eth_stm32_buf __attribute__((section(".eth_stm32_buf"))) +#elif defined(CONFIG_NOCACHE_MEMORY) +#define __eth_stm32_desc __nocache __aligned(4) +#define __eth_stm32_buf __nocache __aligned(4) #else -#define ETH_DMA_MEM __aligned(4) -#endif /* CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER */ - -#if defined(CONFIG_NOCACHE_MEMORY) -#define CACHE __nocache -#else -#define CACHE +#define __eth_stm32_desc __aligned(4) +#define __eth_stm32_buf __aligned(4) #endif -static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] CACHE ETH_DMA_MEM; -static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] CACHE ETH_DMA_MEM; -static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] CACHE ETH_DMA_MEM; -static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] CACHE ETH_DMA_MEM; +static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc; +static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc; +static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __eth_stm32_buf; +static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __eth_stm32_buf; #if defined(CONFIG_SOC_SERIES_STM32H7X) -static ETH_TxPacketConfig tx_config CACHE; +static ETH_TxPacketConfig tx_config; #endif #if defined(CONFIG_NET_L2_CANBUS_ETH_TRANSLATOR) diff --git a/dts/arm/st/h7/stm32h743.dtsi b/dts/arm/st/h7/stm32h743.dtsi index 73d9f35c3b90c..9bf64acb5b2f4 100644 --- a/dts/arm/st/h7/stm32h743.dtsi +++ b/dts/arm/st/h7/stm32h743.dtsi @@ -34,10 +34,34 @@ }; }; - /* system data RAM accessible over over AXI bus */ + /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */ sram0: memory@24000000 { - compatible = "mmio-sram"; reg = <0x24000000 DT_SIZE_K(512)>; + compatible = "mmio-sram"; + }; + + /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ + sram1: memory@30000000 { + reg = <0x30000000 DT_SIZE_K(128)>; + compatible = "mmio-sram"; + }; + + /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ + sram2: memory@30020000 { + compatible = "mmio-sram"; + reg = <0x30020000 DT_SIZE_K(128)>; + }; + + /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */ + sram3: memory@30040000 { + compatible = "mmio-sram"; + reg = <0x30040000 DT_SIZE_K(32)>; + }; + + /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */ + sram4: memory@38000000 { + reg = <0x38000000 DT_SIZE_K(64)>; + compatible = "mmio-sram"; }; dtcm: memory@20000000 { diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi index 5df3d4346c39f..571f4c0ecb646 100644 --- a/dts/arm/st/h7/stm32h745.dtsi +++ b/dts/arm/st/h7/stm32h745.dtsi @@ -39,11 +39,23 @@ /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ sram1: memory@30000000 { - reg = <0x30000000 DT_SIZE_K(288)>; + reg = <0x30000000 DT_SIZE_K(128)>; compatible = "mmio-sram"; }; - /* System data RAM accessible over AHB bus: SRAM4 in D2 domain */ + /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ + sram2: memory@30020000 { + compatible = "mmio-sram"; + reg = <0x30020000 DT_SIZE_K(128)>; + }; + + /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */ + sram3: memory@30040000 { + compatible = "mmio-sram"; + reg = <0x30040000 DT_SIZE_K(32)>; + }; + + /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */ sram4: memory@38000000 { reg = <0x38000000 DT_SIZE_K(64)>; compatible = "mmio-sram"; diff --git a/dts/arm/st/h7/stm32h750.dtsi b/dts/arm/st/h7/stm32h750.dtsi index eca74ab4f065d..42f1dc37cdf95 100644 --- a/dts/arm/st/h7/stm32h750.dtsi +++ b/dts/arm/st/h7/stm32h750.dtsi @@ -13,10 +13,34 @@ }; }; - /* system data RAM accessible over over AXI bus */ + /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */ sram0: memory@24000000 { - compatible = "mmio-sram"; reg = <0x24000000 DT_SIZE_K(512)>; + compatible = "mmio-sram"; + }; + + /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ + sram1: memory@30000000 { + reg = <0x30000000 DT_SIZE_K(128)>; + compatible = "mmio-sram"; + }; + + /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ + sram2: memory@30020000 { + compatible = "mmio-sram"; + reg = <0x30020000 DT_SIZE_K(128)>; + }; + + /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */ + sram3: memory@30040000 { + compatible = "mmio-sram"; + reg = <0x30040000 DT_SIZE_K(32)>; + }; + + /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */ + sram4: memory@38000000 { + reg = <0x38000000 DT_SIZE_K(64)>; + compatible = "mmio-sram"; }; dtcm: memory@20000000 { diff --git a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h index fbfd3d028e80e..50cacb8f95f17 100644 --- a/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h +++ b/include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h @@ -115,6 +115,11 @@ (NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \ MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ } +#define REGION_RAM_NOCACHE_ATTR(size) \ +{ \ + (NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \ + MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ +} #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE) #define REGION_FLASH_ATTR(size) \ { \ diff --git a/include/arch/arm/aarch32/cortex_m/scripts/linker.ld b/include/arch/arm/aarch32/cortex_m/scripts/linker.ld index 820585de79d1b..d07b7b12617c3 100644 --- a/include/arch/arm/aarch32/cortex_m/scripts/linker.ld +++ b/include/arch/arm/aarch32/cortex_m/scripts/linker.ld @@ -98,6 +98,8 @@ MEMORY DT_REGION_FROM_NODE_STATUS_OKAY(SRAM1, rw, DT_NODELABEL(sram1)) DT_REGION_FROM_NODE_STATUS_OKAY(SRAM2, rw, DT_NODELABEL(sram2)) /* STM32 alternate RAM configurations */ + DT_REGION_FROM_NODE_STATUS_OKAY(SRAM3, rw, DT_NODELABEL(sram3)) + DT_REGION_FROM_NODE_STATUS_OKAY(SRAM4, rw, DT_NODELABEL(sram4)) DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM1, rw, DT_NODELABEL(sdram1)) DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM2, rw, DT_NODELABEL(sdram2)) DT_REGION_FROM_NODE_STATUS_OKAY(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram)) diff --git a/soc/arm/st_stm32/stm32h7/CMakeLists.txt b/soc/arm/st_stm32/stm32h7/CMakeLists.txt index 399a487569c61..24f6f90e6e445 100644 --- a/soc/arm/st_stm32/stm32h7/CMakeLists.txt +++ b/soc/arm/st_stm32/stm32h7/CMakeLists.txt @@ -4,3 +4,6 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers) zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c) zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c) + +zephyr_sources(mpu_regions.c) +zephyr_linker_sources(SECTIONS sections.ld) diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.series b/soc/arm/st_stm32/stm32h7/Kconfig.series index 3dd7ab0f1d97a..7a94e34f80fe1 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.series +++ b/soc/arm/st_stm32/stm32h7/Kconfig.series @@ -13,6 +13,7 @@ config SOC_SERIES_STM32H7X select CPU_HAS_ARM_MPU select HAS_SWO select USE_STM32_HAL_CORTEX + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS help Enable support for STM32H7 MCU series diff --git a/soc/arm/st_stm32/stm32h7/mpu_regions.c b/soc/arm/st_stm32/stm32h7/mpu_regions.c new file mode 100644 index 0000000000000..0b098f48c6a80 --- /dev/null +++ b/soc/arm/st_stm32/stm32h7/mpu_regions.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Mario Jaun + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "../../common/cortex_m/arm_mpu_mem_cfg.h" + +static const struct arm_mpu_region mpu_regions[] = { + MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_ATTR(REGION_FLASH_SIZE)), + MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS, + REGION_RAM_ATTR(REGION_SRAM_SIZE)), +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay) && \ + DT_NODE_HAS_STATUS(DT_NODELABEL(mac), okay) + MPU_REGION_ENTRY("SRAM3_ETH_BUF", + DT_REG_ADDR(DT_NODELABEL(sram3)), + REGION_RAM_NOCACHE_ATTR(REGION_16K)), + MPU_REGION_ENTRY("SRAM3_ETH_DESC", + DT_REG_ADDR(DT_NODELABEL(sram3)), + REGION_PPB_ATTR(REGION_256B)), +#endif +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/arm/st_stm32/stm32h7/sections.ld b/soc/arm/st_stm32/stm32h7/sections.ld new file mode 100644 index 0000000000000..45092f2284a8f --- /dev/null +++ b/soc/arm/st_stm32/stm32h7/sections.ld @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020 Mario Jaun + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay) && DT_NODE_HAS_STATUS(DT_NODELABEL(mac), okay) + +SECTION_DATA_PROLOGUE(eth_stm32,(NOLOAD),) +{ + . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))); + *(.eth_stm32_desc) + . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 256; + *(.eth_stm32_buf) + . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K; +} GROUP_DATA_LINK_IN(SRAM3, SRAM3) + +#endif