diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1.dts b/boards/arm/arty/arty_a7_arm_designstart_m1.dts
index d198b2c758aee..0869925223aad 100644
--- a/boards/arm/arty/arty_a7_arm_designstart_m1.dts
+++ b/boards/arm/arty/arty_a7_arm_designstart_m1.dts
@@ -28,11 +28,13 @@
 		itcm: memory@0 {
 			compatible = "arm,itcm";
 			reg = <0x00000000 DT_SIZE_K(64)>;
+			zephyr,memory-region = "ITCM";
 		};
 
 		dtcm: memory@20000000 {
 			compatible = "arm,dtcm";
 			reg = <0x20000000 DT_SIZE_K(32)>;
+			zephyr,memory-region = "DTCM";
 		};
 
 		bram0: memory@60000000 {
diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3.dts b/boards/arm/arty/arty_a7_arm_designstart_m3.dts
index cd6ec1c6b20b7..d19e84028a775 100644
--- a/boards/arm/arty/arty_a7_arm_designstart_m3.dts
+++ b/boards/arm/arty/arty_a7_arm_designstart_m3.dts
@@ -34,11 +34,13 @@
 		itcm: memory@0 {
 			compatible = "arm,itcm";
 			reg = <0x00000000 DT_SIZE_K(32)>;
+			zephyr,memory-region = "ITCM";
 		};
 
 		dtcm: memory@20000000 {
 			compatible = "arm,dtcm";
 			reg = <0x20000000 DT_SIZE_K(32)>;
+			zephyr,memory-region = "DTCM";
 		};
 
 		bram0: memory@60000000 {
diff --git a/boards/arm/mps2_an521/mps2_an521.dts b/boards/arm/mps2_an521/mps2_an521.dts
index 2c677811e3adf..b4f0f248592b4 100644
--- a/boards/arm/mps2_an521/mps2_an521.dts
+++ b/boards/arm/mps2_an521/mps2_an521.dts
@@ -82,11 +82,13 @@
 	sram1: memory@10000000 {
 		compatible = "mmio-sram";
 		reg = <0x10000000 DT_SIZE_M(4)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2_3: memory@38000000 {
 		compatible = "mmio-sram";
 		reg = <0x38000000 DT_SIZE_M(4)>;
+		zephyr,memory-region = "SRAM2_3";
 	};
 
 	psram: memory@80000000 {
diff --git a/boards/arm/mps2_an521/mps2_an521_ns.dts b/boards/arm/mps2_an521/mps2_an521_ns.dts
index 7dc64c369005c..997f7bb07b668 100644
--- a/boards/arm/mps2_an521/mps2_an521_ns.dts
+++ b/boards/arm/mps2_an521/mps2_an521_ns.dts
@@ -82,11 +82,13 @@
 	sram1: memory@0 {
 		compatible = "mmio-sram";
 		reg = <0x0 DT_SIZE_M(4)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2_3: memory@28000000 {
 		compatible = "mmio-sram";
 		reg = <0x28000000 DT_SIZE_M(4)>;
+		zephyr,memory-region = "SRAM2_3";
 	};
 
 	psram: memory@80000000 {
diff --git a/boards/arm/mps2_an521/mps2_an521_remote.dts b/boards/arm/mps2_an521/mps2_an521_remote.dts
index 16a60511810f7..13a2d329bfc9b 100644
--- a/boards/arm/mps2_an521/mps2_an521_remote.dts
+++ b/boards/arm/mps2_an521/mps2_an521_remote.dts
@@ -82,11 +82,13 @@
 	sram1: memory@0 {
 		compatible = "mmio-sram";
 		reg = <0x0 DT_SIZE_M(4)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2_3: memory@28000000 {
 		compatible = "mmio-sram";
 		reg = <0x28000000 DT_SIZE_M(4)>;
+		zephyr,memory-region = "SRAM2_3";
 	};
 
 	psram: memory@80000000 {
diff --git a/boards/arm/mps3_an547/mps3_an547.dts b/boards/arm/mps3_an547/mps3_an547.dts
index c3071cd1abab5..5e9ad3464e7b4 100644
--- a/boards/arm/mps3_an547/mps3_an547.dts
+++ b/boards/arm/mps3_an547/mps3_an547.dts
@@ -109,6 +109,7 @@
 	 */
 	itcm: itcm@10000000 {	/* alias @ 0x0 */
 		reg = <0x10000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "ITCM";
 	};
 
 	sram: sram@11000000 {	/* alias @ 0x01000000 */
@@ -118,6 +119,7 @@
 
 	dtcm: dtcm@30000000 {	/* alias @ 0x20000000 */
 		reg = <0x30000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	isram: sram@31000000 {/* alias @ 0x21000000 */
diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts b/boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts
index 91e4b2cd99d7e..a9fbf6fc01ef4 100644
--- a/boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts
+++ b/boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts
@@ -23,6 +23,7 @@
 	sdram2: sdram@d0000000 {
 		device_type = "memory";
 		reg = <0xd0000000 DT_SIZE_M(8)>;
+		zephyr,memory-region = "SDRAM2";
 	};
 
 	leds {
diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
index 066c672128373..51caf20b2a965 100644
--- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
+++ b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
@@ -24,6 +24,7 @@
 	sdram2: sdram@d0000000 {
 		device_type = "memory";
 		reg = <0xd0000000 DT_SIZE_M(32)>;
+		zephyr,memory-region = "SDRAM2";
 	};
 
 	leds {
diff --git a/cmake/extensions.cmake b/cmake/extensions.cmake
index fd51effdd09fc..a05cb67ec2838 100644
--- a/cmake/extensions.cmake
+++ b/cmake/extensions.cmake
@@ -3316,9 +3316,9 @@ macro(zephyr_linker_memory_ifdef feature_toggle)
 endmacro()
 
 # Usage:
-#   zephyr_linker_dts_memory(NAME <name> PATH <path> FLAGS <flags>)
-#   zephyr_linker_dts_memory(NAME <name> NODELABEL <nodelabel> FLAGS <flags>)
-#   zephyr_linker_dts_memory(NAME <name> CHOSEN <prop> FLAGS <flags>)
+#   zephyr_linker_dts_memory(PATH <path> FLAGS <flags>)
+#   zephyr_linker_dts_memory(NODELABEL <nodelabel> FLAGS <flags>)
+#   zephyr_linker_dts_memory(CHOSEN <prop> FLAGS <flags>)
 #
 # Zephyr linker devicetree memory.
 # This function specifies a memory region for the platform in use based on its
@@ -3329,7 +3329,6 @@ endmacro()
 #
 # Only one of PATH, NODELABEL, and CHOSEN parameters may be given.
 #
-# NAME <name>      : Name of the memory region, for example FLASH.
 # PATH <path>      : Devicetree node identifier.
 # NODELABEL <label>: Node label
 # CHOSEN <prop>    : Chosen property, add memory section described by the
@@ -3342,7 +3341,7 @@ endmacro()
 #                  The flags r and x, or w and x may be combined like: rx, wx.
 #
 function(zephyr_linker_dts_memory)
-  set(single_args "CHOSEN;FLAGS;NAME;PATH;NODELABEL")
+  set(single_args "CHOSEN;FLAGS;PATH;NODELABEL")
   cmake_parse_arguments(DTS_MEMORY "" "${single_args}" "" ${ARGN})
 
   if(DTS_MEMORY_UNPARSED_ARGUMENTS)
@@ -3377,9 +3376,14 @@ function(zephyr_linker_dts_memory)
 
   dt_reg_addr(addr PATH ${DTS_MEMORY_PATH})
   dt_reg_size(size PATH ${DTS_MEMORY_PATH})
+  dt_prop(name PATH ${DTS_MEMORY_PATH} PROPERTY "memory-region")
+  if (NOT DEFINED name)
+    # Fallback to the node path
+    set(name ${DTS_MEMORY_PATH})
+  endif()
 
   zephyr_linker_memory(
-    NAME  ${DTS_MEMORY_NAME}
+    NAME  ${name}
     START ${addr}
     SIZE  ${size}
     FLAGS ${DTS_MEMORY_FLAGS}
diff --git a/cmake/linker_script/arm/linker.cmake b/cmake/linker_script/arm/linker.cmake
index c75696fe5d65b..8f091a271a289 100644
--- a/cmake/linker_script/arm/linker.cmake
+++ b/cmake/linker_script/arm/linker.cmake
@@ -35,19 +35,19 @@ zephyr_linker_memory(NAME RAM      FLAGS wx START ${RAM_ADDR}   SIZE ${RAM_SIZE}
 zephyr_linker_memory(NAME IDT_LIST FLAGS wx START ${IDT_ADDR}   SIZE 2K)
 
 # TI CCFG Registers
-zephyr_linker_dts_memory(NAME FLASH_CCFG FLAGS rwx NODELABEL ti_ccfg_partition)
+zephyr_linker_dts_memory(NODELABEL ti_ccfg_partition FLAGS rwx)
 
 # Data & Instruction Tightly Coupled Memory
-zephyr_linker_dts_memory(NAME ITCM        FLAGS rw CHOSEN "zephyr,itcm")
-zephyr_linker_dts_memory(NAME DTCM        FLAGS rw CHOSEN "zephyr,dtcm")
-
-zephyr_linker_dts_memory(NAME SRAM1       FLAGS rw NODELABEL sram1)
-zephyr_linker_dts_memory(NAME SRAM2       FLAGS rw NODELABEL sram2)
-zephyr_linker_dts_memory(NAME SRAM3       FLAGS rw NODELABEL sram3)
-zephyr_linker_dts_memory(NAME SRAM4       FLAGS rw NODELABEL sram4)
-zephyr_linker_dts_memory(NAME SDRAM1      FLAGS rw NODELABEL sdram1)
-zephyr_linker_dts_memory(NAME SDRAM2      FLAGS rw NODELABEL sdram2)
-zephyr_linker_dts_memory(NAME BACKUP_SRAM FLAGS rw NODELABEL backup_sram)
+zephyr_linker_dts_memory(CHOSEN "zephyr,itcm"  FLAGS rw)
+zephyr_linker_dts_memory(CHOSEN "zephyr,dtcm"  FLAGS rw)
+
+zephyr_linker_dts_memory(NODELABEL sram1       FLAGS rw)
+zephyr_linker_dts_memory(NODELABEL sram2       FLAGS rw)
+zephyr_linker_dts_memory(NODELABEL sram3       FLAGS rw)
+zephyr_linker_dts_memory(NODELABEL sram4       FLAGS rw)
+zephyr_linker_dts_memory(NODELABEL sdram1      FLAGS rw)
+zephyr_linker_dts_memory(NODELABEL sdram2      FLAGS rw)
+zephyr_linker_dts_memory(NODELABEL backup_sram FLAGS rw)
 
 if(CONFIG_XIP)
   zephyr_linker_group(NAME ROM_REGION LMA FLASH)
diff --git a/dts/arm/atmel/sam4l.dtsi b/dts/arm/atmel/sam4l.dtsi
index e8365ceb0cd93..7118ba32b2862 100644
--- a/dts/arm/atmel/sam4l.dtsi
+++ b/dts/arm/atmel/sam4l.dtsi
@@ -48,6 +48,7 @@
 	sram1: memory@21000000 {
 		compatible = "mmio-sram";
 		reg = <0x21000000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	soc {
diff --git a/dts/arm/cypress/psoc6.dtsi b/dts/arm/cypress/psoc6.dtsi
index 06d09db29cba1..d94469799aaed 100644
--- a/dts/arm/cypress/psoc6.dtsi
+++ b/dts/arm/cypress/psoc6.dtsi
@@ -59,11 +59,13 @@
 	sram1: memory@8023000 {
 		compatible = "mmio-sram";
 		reg = <0x08023000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2: memory@8024000 {
 		compatible = "mmio-sram";
 		reg = <0x08024000 DT_SIZE_K(112)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	soc {
diff --git a/dts/arm/nordic/nrf5340_cpunet.dtsi b/dts/arm/nordic/nrf5340_cpunet.dtsi
index cc6a5911d02b1..2484e86dbdfdd 100644
--- a/dts/arm/nordic/nrf5340_cpunet.dtsi
+++ b/dts/arm/nordic/nrf5340_cpunet.dtsi
@@ -50,6 +50,7 @@
 
 		sram1: memory@21000000 {
 			compatible = "mmio-sram";
+			zephyr,memory-region = "SRAM1";
 		};
 
 		clock: clock@41005000 {
diff --git a/dts/arm/nxp/nxp_lpc11u6x.dtsi b/dts/arm/nxp/nxp_lpc11u6x.dtsi
index 116a65fd5f702..23ce97850409a 100644
--- a/dts/arm/nxp/nxp_lpc11u6x.dtsi
+++ b/dts/arm/nxp/nxp_lpc11u6x.dtsi
@@ -26,11 +26,13 @@
 	sram1:memory@20000000 {
 		compatible = "mmio-sram";
 		reg = <0x20000000 0x800>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2:memory@20004000 {
 		compatible = "mmio-sram";
 		reg = <0x20004000 0x800>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	soc {
diff --git a/dts/arm/nxp/nxp_lpc54xxx.dtsi b/dts/arm/nxp/nxp_lpc54xxx.dtsi
index 42dd7a2fb299c..342e52c48cbed 100644
--- a/dts/arm/nxp/nxp_lpc54xxx.dtsi
+++ b/dts/arm/nxp/nxp_lpc54xxx.dtsi
@@ -52,11 +52,13 @@
 		sram1:memory@20010000 {
 			compatible = "mmio-sram";
 			reg = <0x20010000 DT_SIZE_K(64)>;
+			zephyr,memory-region = "SRAM1";
 		};
 
 		sram2:memory@20020000 {
 			compatible = "mmio-sram";
 			reg = <0x20020000 DT_SIZE_K(32)>;
+			zephyr,memory-region = "SRAM2";
 		};
 
 		sramx:memory@4000000{
diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi
index 7edc1da821cae..de2bc66a1c3bc 100644
--- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi
@@ -47,17 +47,20 @@
 	sram1: memory@20008000 {
 		compatible = "mmio-sram";
 		reg = <0x20008000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2: memory@2000c000 {
 		compatible = "mmio-sram";
 		reg = <0x2000c000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	sram4: memory@20010000 {
 		/* Conencted to USB bus*/
 		compatible = "mmio-sram";
 		reg = <0x20010000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "SRAM4";
 	};
 };
 
diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
index bd61e2766bb5e..65ef3966bc6df 100644
--- a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
@@ -55,16 +55,19 @@
 	sram1: memory@20010000 {
 		compatible = "mmio-sram";
 		reg = <0x20010000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2: memory@20020000 {
 		compatible = "mmio-sram";
 		reg = <0x20020000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	sram4: memory@20040000 {
 		compatible = "mmio-sram";
 		reg = <0x20040000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "SRAM4";
 	};
 };
 
diff --git a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi
index a33aca343f56e..6ba0043aba88c 100644
--- a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi
@@ -59,21 +59,25 @@
 	sram1: memory@20010000 {
 		compatible = "mmio-sram";
 		reg = <0x20010000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2: memory@20018000 {
 		compatible = "mmio-sram";
 		reg = <0x20018000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	sram3: memory@20020000 {
 		compatible = "mmio-sram";
 		reg = <0x20020000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
 	};
 
 	sram4: memory@40100000 {
 		compatible = "mmio-sram";
 		reg = <0x40100000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "SRAM4";
 	};
 };
 
diff --git a/dts/arm/nxp/nxp_rt.dtsi b/dts/arm/nxp/nxp_rt.dtsi
index 174e78b60189c..905938c64916e 100644
--- a/dts/arm/nxp/nxp_rt.dtsi
+++ b/dts/arm/nxp/nxp_rt.dtsi
@@ -52,11 +52,13 @@
 			itcm: itcm@0 {
 				compatible = "nxp,imx-itcm";
 				reg = <0x00000000 DT_SIZE_K(128)>;
+				zephyr,memory-region = "ITCM";
 			};
 
 			dtcm: dtcm@20000000 {
 				compatible = "nxp,imx-dtcm";
 				reg = <0x20000000 DT_SIZE_K(128)>;
+				zephyr,memory-region = "DTCM";
 			};
 
 			ocram: ocram@20200000 {
diff --git a/dts/arm/nxp/nxp_rt1170_cm4.dtsi b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
index 46f25c2d78da5..ab131cf8b8102 100644
--- a/dts/arm/nxp/nxp_rt1170_cm4.dtsi
+++ b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
@@ -28,6 +28,7 @@
 		sram1: memory@20000000 {
 			compatible = "mmio-sram";
 			reg = <0x20000000 DT_SIZE_K(128)>;
+			zephyr,memory-region = "SRAM1";
 		};
 
 		/*
diff --git a/dts/arm/nxp/nxp_rt1170_cm7.dtsi b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
index d9ae10bc79fd1..33e794450f03d 100644
--- a/dts/arm/nxp/nxp_rt1170_cm7.dtsi
+++ b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
@@ -29,11 +29,13 @@
 			itcm: itcm@0 {
 				compatible = "nxp,imx-itcm";
 				reg = <0x00000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "ITCM";
 			};
 
 			dtcm: dtcm@20000000 {
 				compatible = "nxp,imx-dtcm";
 				reg = <0x20000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "DTCM";
 			};
 		};
 
diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi
index f171a5730df16..c30eeef0fccbd 100644
--- a/dts/arm/st/f2/stm32f2.dtsi
+++ b/dts/arm/st/f2/stm32f2.dtsi
@@ -553,6 +553,7 @@
 			reg = <0x40024000 DT_SIZE_K(4)>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
 			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
 	};
diff --git a/dts/arm/st/f4/stm32f405.dtsi b/dts/arm/st/f4/stm32f405.dtsi
index 3f4ae25615dcd..035975fce8d2c 100644
--- a/dts/arm/st/f4/stm32f405.dtsi
+++ b/dts/arm/st/f4/stm32f405.dtsi
@@ -227,6 +227,7 @@
 			reg = <0x40024000 DT_SIZE_K(4)>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
 			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi
index b1637cc92afcb..1c0a1c49c68f9 100644
--- a/dts/arm/st/f4/stm32f446.dtsi
+++ b/dts/arm/st/f4/stm32f446.dtsi
@@ -108,6 +108,7 @@
 			reg = <0x40024000 DT_SIZE_K(4)>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
 			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
index d99c1b855bc22..08b7644673d64 100644
--- a/dts/arm/st/f7/stm32f7.dtsi
+++ b/dts/arm/st/f7/stm32f7.dtsi
@@ -743,6 +743,7 @@
 			reg = <0x40024000 DT_SIZE_K(4)>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
 			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/f7/stm32f723.dtsi b/dts/arm/st/f7/stm32f723.dtsi
index af2b99ca50bc8..c6baaffd70f75 100644
--- a/dts/arm/st/f7/stm32f723.dtsi
+++ b/dts/arm/st/f7/stm32f723.dtsi
@@ -17,6 +17,7 @@
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	soc {
diff --git a/dts/arm/st/f7/stm32f745.dtsi b/dts/arm/st/f7/stm32f745.dtsi
index e7ec4b730927a..d9fc926bd5c75 100644
--- a/dts/arm/st/f7/stm32f745.dtsi
+++ b/dts/arm/st/f7/stm32f745.dtsi
@@ -17,6 +17,7 @@
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	soc {
diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi
index db0f49378c3b7..0e5879f253ea0 100644
--- a/dts/arm/st/f7/stm32f767.dtsi
+++ b/dts/arm/st/f7/stm32f767.dtsi
@@ -19,6 +19,7 @@
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	soc {
diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi
index 78784a26e8be9..9872dadb52ecf 100644
--- a/dts/arm/st/h7/stm32h7.dtsi
+++ b/dts/arm/st/h7/stm32h7.dtsi
@@ -837,6 +837,7 @@
 			reg = <0x38800000 DT_SIZE_K(4)>;
 			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>;
 			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
 	};
diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi
index 082c0e9797927..d6d2e07f87658 100644
--- a/dts/arm/st/h7/stm32h723.dtsi
+++ b/dts/arm/st/h7/stm32h723.dtsi
@@ -41,6 +41,7 @@
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	/* AXI SRAM in D1 domain (AXI bus) */
diff --git a/dts/arm/st/h7/stm32h735.dtsi b/dts/arm/st/h7/stm32h735.dtsi
index 22d27e926c70c..941cfd9816895 100644
--- a/dts/arm/st/h7/stm32h735.dtsi
+++ b/dts/arm/st/h7/stm32h735.dtsi
@@ -56,22 +56,26 @@
 	sram1: memory@30000000 {
 		reg = <0x30000000 DT_SIZE_K(16)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
 	sram2: memory@30040000 {
 		reg = <0x30040000 DT_SIZE_K(16)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM2";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
 	sram4: memory@38000000 {
 		reg = <0x38000000 DT_SIZE_K(16)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
 	};
 
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
 	};
 };
diff --git a/dts/arm/st/h7/stm32h743.dtsi b/dts/arm/st/h7/stm32h743.dtsi
index 9bf64acb5b2f4..a66326619e4df 100644
--- a/dts/arm/st/h7/stm32h743.dtsi
+++ b/dts/arm/st/h7/stm32h743.dtsi
@@ -44,29 +44,34 @@
 	sram1: memory@30000000 {
 		reg = <0x30000000 DT_SIZE_K(128)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
 	sram2: memory@30020000 {
 		compatible = "mmio-sram";
 		reg = <0x30020000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
 	sram3: memory@30040000 {
 		compatible = "mmio-sram";
 		reg = <0x30040000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
 	sram4: memory@38000000 {
 		reg = <0x38000000 DT_SIZE_K(64)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
 	};
 
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	otghs_fs_phy: otghs_fs_phy {
diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi
index 571f4c0ecb646..76aa2ca2a9f58 100644
--- a/dts/arm/st/h7/stm32h745.dtsi
+++ b/dts/arm/st/h7/stm32h745.dtsi
@@ -41,23 +41,27 @@
 	sram1: memory@30000000 {
 		reg = <0x30000000 DT_SIZE_K(128)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
 	sram2: memory@30020000 {
 		compatible = "mmio-sram";
 		reg = <0x30020000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
 	sram3: memory@30040000 {
 		compatible = "mmio-sram";
 		reg = <0x30040000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
 	sram4: memory@38000000 {
 		reg = <0x38000000 DT_SIZE_K(64)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
 	};
 };
diff --git a/dts/arm/st/h7/stm32h745Xi_m7.dtsi b/dts/arm/st/h7/stm32h745Xi_m7.dtsi
index 75740b507581b..cb75c1f1b6e2f 100644
--- a/dts/arm/st/h7/stm32h745Xi_m7.dtsi
+++ b/dts/arm/st/h7/stm32h745Xi_m7.dtsi
@@ -17,6 +17,7 @@
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
 	};
 
 	soc {
diff --git a/dts/arm/st/h7/stm32h750.dtsi b/dts/arm/st/h7/stm32h750.dtsi
index 42f1dc37cdf95..8e215c9eee319 100644
--- a/dts/arm/st/h7/stm32h750.dtsi
+++ b/dts/arm/st/h7/stm32h750.dtsi
@@ -23,28 +23,33 @@
 	sram1: memory@30000000 {
 		reg = <0x30000000 DT_SIZE_K(128)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
 	sram2: memory@30020000 {
 		compatible = "mmio-sram";
 		reg = <0x30020000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
 	sram3: memory@30040000 {
 		compatible = "mmio-sram";
 		reg = <0x30040000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
 	};
 
 	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
 	sram4: memory@38000000 {
 		reg = <0x38000000 DT_SIZE_K(64)>;
 		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
 	};
 
 	dtcm: memory@20000000 {
 		compatible = "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
 	};
 };
diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi
index 2f98c68d86cef..1927163c1b6fd 100644
--- a/dts/arm/st/wb/stm32wb.dtsi
+++ b/dts/arm/st/wb/stm32wb.dtsi
@@ -36,11 +36,13 @@
 	sram1: memory@20030000 {
 		compatible = "mmio-sram";
 		reg = <0x20030000 0x2800>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2: memory@20038000 {
 		compatible = "mmio-sram";
 		reg = <0x20038000 0x5000>;
+		zephyr,memory-region = "SRAM2";
 	};
 
 	clocks {
diff --git a/dts/arm/ti/cc1352r.dtsi b/dts/arm/ti/cc1352r.dtsi
index 81dc682b4cd31..2df436b2d0006 100644
--- a/dts/arm/ti/cc1352r.dtsi
+++ b/dts/arm/ti/cc1352r.dtsi
@@ -24,6 +24,7 @@
 			ti_ccfg_partition: partition@57fa8 {
 				label = "ti_ccfg";
 				reg = <0x57fa8 88>;
+				zephyr,memory-region = "FLASH_CCFG";
 			};
 		};
 	};
diff --git a/dts/arm/ti/cc13x2_cc26x2.dtsi b/dts/arm/ti/cc13x2_cc26x2.dtsi
index e944360ae8001..1d581fc186164 100644
--- a/dts/arm/ti/cc13x2_cc26x2.dtsi
+++ b/dts/arm/ti/cc13x2_cc26x2.dtsi
@@ -32,6 +32,7 @@
 	sram1: memory@11000000 {
 		compatible = "mmio-sram";
 		reg = <0x11000000 0x2000>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	flash0: serial-flash@0 {
diff --git a/dts/arm/ti/cc2652r.dtsi b/dts/arm/ti/cc2652r.dtsi
index 81dc682b4cd31..2df436b2d0006 100644
--- a/dts/arm/ti/cc2652r.dtsi
+++ b/dts/arm/ti/cc2652r.dtsi
@@ -24,6 +24,7 @@
 			ti_ccfg_partition: partition@57fa8 {
 				label = "ti_ccfg";
 				reg = <0x57fa8 88>;
+				zephyr,memory-region = "FLASH_CCFG";
 			};
 		};
 	};
diff --git a/dts/arm/xilinx/zynq7000.dtsi b/dts/arm/xilinx/zynq7000.dtsi
index 18cf4ec029ddf..803578ea60530 100644
--- a/dts/arm/xilinx/zynq7000.dtsi
+++ b/dts/arm/xilinx/zynq7000.dtsi
@@ -26,6 +26,7 @@
 		ocm_low: memory@1000 {
 			compatible = "xlnx,zynq-ocm";
 			reg = <0x00001000 DT_SIZE_K(188)>;
+			zephyr,memory-region = "OCM";
 		};
 
 		ocm_high: memory@fffc0000 {
diff --git a/dts/bindings/arm/arm,dtcm.yaml b/dts/bindings/arm/arm,dtcm.yaml
index a638085abbe77..8622b9845a7f4 100644
--- a/dts/bindings/arm/arm,dtcm.yaml
+++ b/dts/bindings/arm/arm,dtcm.yaml
@@ -4,7 +4,7 @@ description: Cortex-M DTCM (Data Tightly Coupled Memory)
 
 compatible: "arm,dtcm"
 
-include: base.yaml
+include: [base.yaml, mem-region.yaml]
 
 properties:
     reg:
diff --git a/dts/bindings/arm/arm,itcm.yaml b/dts/bindings/arm/arm,itcm.yaml
index 4b0b34799cc93..455947dbb3662 100644
--- a/dts/bindings/arm/arm,itcm.yaml
+++ b/dts/bindings/arm/arm,itcm.yaml
@@ -4,7 +4,7 @@ description: Cortex-M ITCM (Instruction Tightly Coupled Memory)
 
 compatible: "arm,itcm"
 
-include: base.yaml
+include: [base.yaml, mem-region.yaml]
 
 properties:
     reg:
diff --git a/dts/bindings/arm/nxp,imx-dtcm.yaml b/dts/bindings/arm/nxp,imx-dtcm.yaml
index 8c76d6bfdac2b..8b16228913dcd 100644
--- a/dts/bindings/arm/nxp,imx-dtcm.yaml
+++ b/dts/bindings/arm/nxp,imx-dtcm.yaml
@@ -5,7 +5,7 @@ description: i.MX DTCM (Data Tightly Coupled Memory)
 
 compatible: "nxp,imx-dtcm"
 
-include: base.yaml
+include: [base.yaml, mem-region.yaml]
 
 properties:
     reg:
diff --git a/dts/bindings/arm/nxp,imx-itcm.yaml b/dts/bindings/arm/nxp,imx-itcm.yaml
index c0919e7b14155..755093ae301ae 100644
--- a/dts/bindings/arm/nxp,imx-itcm.yaml
+++ b/dts/bindings/arm/nxp,imx-itcm.yaml
@@ -5,7 +5,7 @@ description: i.MX ITCM (Instruction Tightly Coupled Memory)
 
 compatible: "nxp,imx-itcm"
 
-include: base.yaml
+include: [base.yaml, mem-region.yaml]
 
 properties:
     reg:
diff --git a/dts/bindings/base/mem-region.yaml b/dts/bindings/base/mem-region.yaml
new file mode 100644
index 0000000000000..a555faf508798
--- /dev/null
+++ b/dts/bindings/base/mem-region.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2021, CSIRO
+# SPDX-License-Identifier: Apache-2.0
+# Common fields for devices resulting in linker memory regions
+
+properties:
+  zephyr,memory-region:
+    type: string
+    required: false
+    description: |
+      Signify that this node should result in a dedicated linker script
+      memory region in the final executable. The region address and size
+      is taken from the <reg> property, while the name is the value of
+      this property.
diff --git a/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml b/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml
index 7dc5c963ad51f..04bcab041bc2c 100644
--- a/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml
+++ b/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml
@@ -9,7 +9,7 @@ description: |
 
 compatible: "st,stm32-backup-sram"
 
-include: base.yaml
+include: [base.yaml, mem-region.yaml]
 
 properties:
   label:
diff --git a/dts/bindings/mtd/fixed-partitions.yaml b/dts/bindings/mtd/fixed-partitions.yaml
index 4ad4642f86fd6..8c086a0304a8f 100644
--- a/dts/bindings/mtd/fixed-partitions.yaml
+++ b/dts/bindings/mtd/fixed-partitions.yaml
@@ -28,3 +28,12 @@ child-binding:
           type: array
           description: register space
           required: true
+       zephyr,memory-region:
+          type: string
+          required: false
+          description: |
+            Signify that this node should result in a dedicated linker script
+            memory region in the final executable. The region address and size
+            is taken from the <reg> property, while the name is the value of
+            this property. This must only be added to memory-mapped partitions,
+            not partitions on external flash.
diff --git a/dts/bindings/sram/mmio-sram.yaml b/dts/bindings/sram/mmio-sram.yaml
index e9919806ea1c8..98361916a27c4 100644
--- a/dts/bindings/sram/mmio-sram.yaml
+++ b/dts/bindings/sram/mmio-sram.yaml
@@ -5,7 +5,7 @@ description: Generic on-chip SRAM description
 
 compatible: "mmio-sram"
 
-include: base.yaml
+include: [base.yaml, mem-region.yaml]
 
 properties:
     reg:
diff --git a/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld b/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld
index 2ed81f197bfbf..1e19eb3d6d96b 100644
--- a/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld
+++ b/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld
@@ -81,7 +81,7 @@ MEMORY
 {
     FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
     SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
-    LINKER_DT_REGION_FROM_NODE(OCM, rw, DT_CHOSEN(zephyr_ocm))
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
 }
diff --git a/include/arch/arm/aarch32/cortex_m/scripts/linker.ld b/include/arch/arm/aarch32/cortex_m/scripts/linker.ld
index da045f7b90f3e..6ccb15dbc75e9 100644
--- a/include/arch/arm/aarch32/cortex_m/scripts/linker.ld
+++ b/include/arch/arm/aarch32/cortex_m/scripts/linker.ld
@@ -82,21 +82,21 @@ MEMORY
     FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
     SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
     /* TI CCFG Registers */
-    LINKER_DT_REGION_FROM_NODE(FLASH_CCFG, rwx, DT_NODELABEL(ti_ccfg_partition))
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(ti_ccfg_partition), rwx)
     /* Data & Instruction Tightly Coupled Memory */
-    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))
-    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
     /* STM32 Core Coupled Memory */
-    LINKER_DT_REGION_FROM_NODE(CCM, rw, DT_CHOSEN(zephyr_ccm))
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ccm), rw)
     /* STM32WB IPC RAM */
-    LINKER_DT_REGION_FROM_NODE(SRAM1, rw, DT_NODELABEL(sram1))
-    LINKER_DT_REGION_FROM_NODE(SRAM2, rw, DT_NODELABEL(sram2))
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram1), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram2), rw)
     /* STM32 alternate RAM configurations */
-    LINKER_DT_REGION_FROM_NODE(SRAM3, rw, DT_NODELABEL(sram3))
-    LINKER_DT_REGION_FROM_NODE(SRAM4, rw, DT_NODELABEL(sram4))
-    LINKER_DT_REGION_FROM_NODE(SDRAM1, rw, DT_NODELABEL(sdram1))
-    LINKER_DT_REGION_FROM_NODE(SDRAM2, rw, DT_NODELABEL(sdram2))
-    LINKER_DT_REGION_FROM_NODE(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram))
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram3), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram4), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sdram1), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sdram2), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(backup_sram), rw)
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
     }
diff --git a/include/arch/riscv/common/linker.ld b/include/arch/riscv/common/linker.ld
index 8ae7e0c038141..7ef6b2903fc96 100644
--- a/include/arch/riscv/common/linker.ld
+++ b/include/arch/riscv/common/linker.ld
@@ -82,8 +82,8 @@ MEMORY
     RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
 
     /* Data & Instruction Tightly Coupled Memory */
-    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))
-    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
 
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
diff --git a/include/linker/devicetree_regions.h b/include/linker/devicetree_regions.h
index 8fec70cc5330e..667bb51dc10bf 100644
--- a/include/linker/devicetree_regions.h
+++ b/include/linker/devicetree_regions.h
@@ -7,25 +7,57 @@
  * Generate memory regions from devicetree nodes.
  */
 
-/* Declare a memory region */
-#define _REGION_DECLARE(name, attr, node) name(attr) : \
-	ORIGIN = DT_REG_ADDR(node),		       \
-	LENGTH = DT_REG_SIZE(node)
-
 /**
- * @brief Generate a linker memory region from a devicetree node
+ * @brief Get the linker memory-region name
+ *
+ * This attempts to use the zephyr,memory-region property, falling back
+ * to the node path if it doesn't exist.
+ *
+ * Example devicetree fragment:
  *
- * If @p node_id refers to a node with status "okay", then this declares
- * a linker memory region named @p name with attributes from @p attr.
+ *     / {
+ *             soc {
+ *                     sram1: memory@2000000 {
+ *                         zephyr,memory-region = "MY_NAME";
+ *                     };
+ *                     sram2: memory@2001000 { ... };
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *    LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram1)) // "MY_NAME"
+ *    LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram2)) // "/soc/memory@2001000"
+ *
+ * @param node_id node identifier
+ * @return the name of the memory memory region the node will generate
+ */
+#define LINKER_DT_NODE_REGION_NAME(node_id) \
+	DT_PROP_OR(node_id, zephyr_memory_region, DT_NODE_PATH(node_id))
+
+/** @cond INTERNAL_HIDDEN */
+
+/**
+ * @brief Declare a memory region
  *
- * Otherwise, it doesn't expand to anything.
+ * @param node_id devicetree node identifier
+ * @param attr region attributes
+ */
+#define _REGION_DECLARE(node_id, attr)		    \
+	LINKER_DT_NODE_REGION_NAME(node_id)(attr) : \
+	ORIGIN = DT_REG_ADDR(node_id),		    \
+	LENGTH = DT_REG_SIZE(node_id)
+
+/** @endcond */
+
+/**
+ * @brief Generate a linker memory region from a devicetree node
  *
- * @param name name of the generated memory region
+ * @param node_id devicetree node identifier with a \<reg\> property defining
+ *                region location and size
  * @param attr region attributes to use (rx, rw, ...)
- * @param node_id devicetree node identifier with a \<reg\> property
- *                defining region location and size.
  */
-#define LINKER_DT_REGION_FROM_NODE(name, attr, node_id)		\
-	COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay),		\
-		    (_REGION_DECLARE(name, attr, node_id)),	\
+#define LINKER_DT_REGION_FROM_NODE(node_id, attr)      \
+	COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
+		    (_REGION_DECLARE(node_id, attr)),  \
 		    ())
diff --git a/scripts/dts/gen_defines.py b/scripts/dts/gen_defines.py
index 86e61987c3882..7cff885edfa70 100755
--- a/scripts/dts/gen_defines.py
+++ b/scripts/dts/gen_defines.py
@@ -107,6 +107,16 @@ def main():
         for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
             node.z_path_id = node_z_path_id(node)
 
+        # Check to see if we have duplicate "zephyr,memory-region" property values.
+        regions = dict()
+        for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
+            if 'zephyr,memory-region' in node.props:
+                region = node.props['zephyr,memory-region'].val
+                if region in regions:
+                    sys.exit(f"ERROR: Duplicate 'zephyr,memory-region' ({region}) properties "
+                             f"between {regions[region].path} and {node.path}")
+                regions[region] = node
+
         for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
             write_node_comment(node)
 
diff --git a/soc/arm/st_stm32/common/ccm.ld b/soc/arm/st_stm32/common/ccm.ld
index 4804cc75f9b03..ee2396b3c7900 100644
--- a/soc/arm/st_stm32/common/ccm.ld
+++ b/soc/arm/st_stm32/common/ccm.ld
@@ -9,7 +9,7 @@ GROUP_START(CCM)
 		*(.ccm_bss)
 		*(".ccm_bss.*")
 		__ccm_bss_end = .;
-	} GROUP_LINK_IN(CCM)
+	} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
 
 	SECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
 	{
@@ -17,7 +17,7 @@ GROUP_START(CCM)
 		*(.ccm_noinit)
 		*(".ccm_noinit.*")
 		__ccm_noinit_end = .;
-	} GROUP_LINK_IN(CCM)
+	} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
 
 	SECTION_PROLOGUE(_CCM_DATA_SECTION_NAME,,SUBALIGN(4))
 	{
@@ -25,10 +25,10 @@ GROUP_START(CCM)
 		*(.ccm_data)
 		*(".ccm_data.*")
 		__ccm_data_end = .;
-	} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)
+	} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION)
 
 	__ccm_end = .;
 
 	__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);
 
-GROUP_END(CCM)
\ No newline at end of file
+GROUP_END(CCM)
diff --git a/soc/arm/st_stm32/stm32h7/sections.ld b/soc/arm/st_stm32/stm32h7/sections.ld
index 45092f2284a8f..7dc2204988022 100644
--- a/soc/arm/st_stm32/stm32h7/sections.ld
+++ b/soc/arm/st_stm32/stm32h7/sections.ld
@@ -13,6 +13,6 @@ SECTION_DATA_PROLOGUE(eth_stm32,(NOLOAD),)
     . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 256;
     *(.eth_stm32_buf)
     . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K;
-} GROUP_DATA_LINK_IN(SRAM3, SRAM3)
+} GROUP_DATA_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram3)), LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram3)))
 
 #endif
diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld b/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld
index 8821bd4947111..e0e7edbaa0b6e 100644
--- a/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld
+++ b/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld
@@ -10,6 +10,6 @@ GROUP_START(FLASH_CCFG)
 SECTION_PROLOGUE(.ti_ccfg,,)
 {
     KEEP(*(_TI_CCFG_SECTION_NAME))
-} GROUP_LINK_IN(FLASH_CCFG)
+} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(ti_ccfg_partition)))
 
 GROUP_END(FLASH_CCFG)
diff --git a/soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld b/soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld
index f69e1329838e8..9f57775ceca9d 100644
--- a/soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld
+++ b/soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld
@@ -88,8 +88,8 @@ MEMORY
     RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
 
     /* Data & Instruction Tightly Coupled Memory */
-    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))
-    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
+    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
 
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
diff --git a/tests/lib/devicetree/api_ext/CMakeLists.txt b/tests/lib/devicetree/api_ext/CMakeLists.txt
new file mode 100644
index 0000000000000..4a9425bab7f68
--- /dev/null
+++ b/tests/lib/devicetree/api_ext/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(devicetree_extensions)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/lib/devicetree/api_ext/README b/tests/lib/devicetree/api_ext/README
new file mode 100644
index 0000000000000..48cd28c25a74f
--- /dev/null
+++ b/tests/lib/devicetree/api_ext/README
@@ -0,0 +1 @@
+Test cases for the devicetree.h extensions (GPIO, SPI, etc).
diff --git a/tests/lib/devicetree/api_ext/app.overlay b/tests/lib/devicetree/api_ext/app.overlay
new file mode 100644
index 0000000000000..e1b19a5e2f769
--- /dev/null
+++ b/tests/lib/devicetree/api_ext/app.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2021, Commonwealth Scientific and Industrial Research
+ * Organisation (CSIRO) ABN 41 687 119 230.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Application overlay for testing the devicetree.h extension API's.
+ *
+ * Names in this file should be chosen in a way that won't conflict
+ * with real-world devicetree nodes, to allow these tests to run on
+ * (and be extended to test) real hardware.
+ */
+
+ / {
+	test {
+		#address-cells = < 0x1 >;
+		#size-cells = < 0x1 >;
+
+		test_sram1: sram@20000000 {
+			compatible = "mmio-sram";
+			reg = < 0x20000000 0x1000 >;
+			zephyr,memory-region = "SRAM_REGION";
+		};
+		test_sram2: sram@20001000 {
+			compatible = "mmio-sram";
+			reg = < 0x20001000 0x1000 >;
+		};
+	};
+};
diff --git a/tests/lib/devicetree/api_ext/prj.conf b/tests/lib/devicetree/api_ext/prj.conf
new file mode 100644
index 0000000000000..9467c2926896d
--- /dev/null
+++ b/tests/lib/devicetree/api_ext/prj.conf
@@ -0,0 +1 @@
+CONFIG_ZTEST=y
diff --git a/tests/lib/devicetree/api_ext/src/main.c b/tests/lib/devicetree/api_ext/src/main.c
new file mode 100644
index 0000000000000..501727b5843f4
--- /dev/null
+++ b/tests/lib/devicetree/api_ext/src/main.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, Commonwealth Scientific and Industrial Research
+ * Organisation (CSIRO) ABN 41 687 119 230.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <ztest.h>
+#include <devicetree.h>
+#include <device.h>
+#include <drivers/gpio.h>
+
+#include <linker/devicetree_regions.h>
+
+#define TEST_SRAM1      DT_NODELABEL(test_sram1)
+#define TEST_SRAM2      DT_NODELABEL(test_sram2)
+
+static void test_linker_regions(void)
+{
+	zassert_true(!strcmp(LINKER_DT_NODE_REGION_NAME(TEST_SRAM1), "SRAM_REGION"), "");
+	zassert_true(!strcmp(LINKER_DT_NODE_REGION_NAME(TEST_SRAM2), "/test/sram@20001000"), "");
+}
+
+void test_main(void)
+{
+	ztest_test_suite(devicetree_api_ext,
+			 ztest_unit_test(test_linker_regions)
+			 );
+	ztest_run_test_suite(devicetree_api_ext);
+}
diff --git a/tests/lib/devicetree/api_ext/testcase.yaml b/tests/lib/devicetree/api_ext/testcase.yaml
new file mode 100644
index 0000000000000..3ac22dea78c8b
--- /dev/null
+++ b/tests/lib/devicetree/api_ext/testcase.yaml
@@ -0,0 +1,7 @@
+tests:
+  libraries.devicetree_ext:
+    tags: devicetree
+    # We only need this to run on one platform so use native_posix as it
+    # will mostly likely be the fastest.
+    integration_platforms:
+      - native_posix