diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml
index f8b5f1fecca89..34e6d2bfef54a 100644
--- a/MAINTAINERS.yml
+++ b/MAINTAINERS.yml
@@ -421,7 +421,7 @@ CMSIS-DSP integration:
   collaborators:
     - galak
   files:
-    - modules/Kconfig.cmsis_dsp
+    - modules/cmsis/Kconfig.cmsis_dsp
     - tests/benchmarks/cmsis_dsp/
     - tests/lib/cmsis_dsp/
   labels:
@@ -434,7 +434,7 @@ CMSIS-NN integration:
   collaborators:
     - stephanosio
   files:
-    - modules/Kconfig.cmsis_nn
+    - modules/cmsis/Kconfig.cmsis_nn
     - tests/lib/cmsis_nn/
   labels:
     - "area: CMSIS-NN"
@@ -2854,9 +2854,9 @@ West:
     - microbuilder
     - povergoing
   files:
-    - modules/Kconfig.cmsis
-    - modules/Kconfig.cmsis_dsp
-    - modules/Kconfig.cmsis_nn
+    - modules/cmsis/Kconfig
+    - modules/cmsis/Kconfig.cmsis_dsp
+    - modules/cmsis/Kconfig.cmsis_nn
   labels:
     - manifest-cmsis
 
diff --git a/arch/arm/core/aarch32/cortex_a_r/cache.c b/arch/arm/core/aarch32/cortex_a_r/cache.c
index fa921d2c0925c..164021a27d6df 100644
--- a/arch/arm/core/aarch32/cortex_a_r/cache.c
+++ b/arch/arm/core/aarch32/cortex_a_r/cache.c
@@ -14,7 +14,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 /* Cache Type Register */
diff --git a/arch/arm/core/aarch32/cortex_a_r/tcm.c b/arch/arm/core/aarch32/cortex_a_r/tcm.c
index 05f4046c198d1..6e966d181a2f1 100644
--- a/arch/arm/core/aarch32/cortex_a_r/tcm.c
+++ b/arch/arm/core/aarch32/cortex_a_r/tcm.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 void z_arm_tcm_disable_ecc(void)
 {
diff --git a/arch/arm/core/aarch32/cortex_a_r/thread.c b/arch/arm/core/aarch32/cortex_a_r/thread.c
index 904e9c113784c..736797f401144 100644
--- a/arch/arm/core/aarch32/cortex_a_r/thread.c
+++ b/arch/arm/core/aarch32/cortex_a_r/thread.c
@@ -5,7 +5,7 @@
  */
 
 #include <stdbool.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 bool z_arm_thread_is_in_user_mode(void)
 {
diff --git a/arch/arm/core/aarch32/cortex_m/cache.c b/arch/arm/core/aarch32/cortex_m/cache.c
index e0bd78ff186c7..df746eb0474df 100644
--- a/arch/arm/core/aarch32/cortex_m/cache.c
+++ b/arch/arm/core/aarch32/cortex_m/cache.c
@@ -13,7 +13,7 @@
 
 #include <zephyr/arch/cpu.h>
 #include <zephyr/cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 void arch_dcache_enable(void)
 {
diff --git a/arch/arm/core/aarch32/cortex_m/fpu.c b/arch/arm/core/aarch32/cortex_m/fpu.c
index 19921795b79ea..0e6084470e9fc 100644
--- a/arch/arm/core/aarch32/cortex_m/fpu.c
+++ b/arch/arm/core/aarch32/cortex_m/fpu.c
@@ -6,7 +6,7 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/fpu.h>
 
 /**
diff --git a/arch/arm/core/aarch32/cortex_m/irq_init.c b/arch/arm/core/aarch32/cortex_m/irq_init.c
index d579337da3559..b6b128e3368ff 100644
--- a/arch/arm/core/aarch32/cortex_m/irq_init.c
+++ b/arch/arm/core/aarch32/cortex_m/irq_init.c
@@ -11,7 +11,7 @@
  */
 
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /**
  *
diff --git a/arch/arm/core/aarch32/cortex_m/scb.c b/arch/arm/core/aarch32/cortex_m/scb.c
index 3e19db8b43bde..472c82424658c 100644
--- a/arch/arm/core/aarch32/cortex_m/scb.c
+++ b/arch/arm/core/aarch32/cortex_m/scb.c
@@ -18,7 +18,7 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/barrier.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/cache.h>
 
diff --git a/arch/arm/core/aarch32/cortex_m/thread.c b/arch/arm/core/aarch32/cortex_m/thread.c
index 74426821314cc..6ada938f6e1b9 100644
--- a/arch/arm/core/aarch32/cortex_m/thread.c
+++ b/arch/arm/core/aarch32/cortex_m/thread.c
@@ -5,7 +5,7 @@
  */
 
 #include <stdbool.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 bool z_arm_thread_is_in_user_mode(void)
 {
diff --git a/arch/arm/core/aarch32/cortex_m/timing.c b/arch/arm/core/aarch32/cortex_m/timing.c
index 5bf6e80dd6107..2e2912487f88c 100644
--- a/arch/arm/core/aarch32/cortex_m/timing.c
+++ b/arch/arm/core/aarch32/cortex_m/timing.c
@@ -15,7 +15,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/timing/timing.h>
 #include <aarch32/cortex_m/dwt.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys_clock.h>
 
 /**
diff --git a/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c b/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c
index cea69bbe607a5..1a316be7265d7 100644
--- a/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c
+++ b/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <aarch32/cortex_m/tz.h>
 #include <aarch32/cortex_m/exc.h>
 
diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c
index 29050524e0db2..6ad5adf7cdab0 100644
--- a/arch/arm/core/aarch32/irq_manage.c
+++ b/arch/arm/core/aarch32/irq_manage.c
@@ -17,7 +17,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
 	|| defined(CONFIG_CPU_AARCH32_CORTEX_R)
 #include <zephyr/drivers/interrupt_controller/gic.h>
diff --git a/arch/arm/core/aarch32/mmu/arm_mmu.c b/arch/arm/core/aarch32/mmu/arm_mmu.c
index 53f56591e356d..3658b2df639c2 100644
--- a/arch/arm/core/aarch32/mmu/arm_mmu.c
+++ b/arch/arm/core/aarch32/mmu/arm_mmu.c
@@ -29,7 +29,7 @@
 #include <zephyr/sys/mem_manage.h>
 #include <zephyr/sys/barrier.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "arm_mmu_priv.h"
diff --git a/arch/arm/include/aarch32/cortex_m/dwt.h b/arch/arm/include/aarch32/cortex_m/dwt.h
index 08a3d4c8fdd66..ed0df44dfde56 100644
--- a/arch/arm/include/aarch32/cortex_m/dwt.h
+++ b/arch/arm/include/aarch32/cortex_m/dwt.h
@@ -20,7 +20,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/__assert.h>
 
 #ifdef __cplusplus
diff --git a/arch/arm/include/aarch32/cortex_m/exc.h b/arch/arm/include/aarch32/cortex_m/exc.h
index b4f1b6cd8f7d1..13fc08f178d60 100644
--- a/arch/arm/include/aarch32/cortex_m/exc.h
+++ b/arch/arm/include/aarch32/cortex_m/exc.h
@@ -22,7 +22,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/exc.h>
 #include <zephyr/irq_offload.h>
 
diff --git a/arch/arm/include/aarch32/cortex_m/stack.h b/arch/arm/include/aarch32/cortex_m/stack.h
index 2dc69f93264ab..f5c4de5902af3 100644
--- a/arch/arm/include/aarch32/cortex_m/stack.h
+++ b/arch/arm/include/aarch32/cortex_m/stack.h
@@ -20,7 +20,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/boards/arm/arty/board.c b/boards/arm/arty/board.c
index b2539d7aedd47..c87f3249649c3 100644
--- a/boards/arm/arty/board.c
+++ b/boards/arm/arty/board.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/gpio.h>
diff --git a/drivers/cache/cache_aspeed.c b/drivers/cache/cache_aspeed.c
index 77fbe17309a27..400795a25047a 100644
--- a/drivers/cache/cache_aspeed.c
+++ b/drivers/cache/cache_aspeed.c
@@ -5,7 +5,6 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/drivers/syscon.h>
 #include <zephyr/sys/barrier.h>
 
diff --git a/drivers/clock_control/clock_control_mchp_xec.c b/drivers/clock_control/clock_control_mchp_xec.c
index f9da6c2a00b40..ae79ae1b41655 100644
--- a/drivers/clock_control/clock_control_mchp_xec.c
+++ b/drivers/clock_control/clock_control_mchp_xec.c
@@ -8,7 +8,7 @@
 
 #include <soc.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c
index b9f14b8c91f10..81ca122ed2272 100644
--- a/drivers/display/display_stm32_ltdc.c
+++ b/drivers/display/display_stm32_ltdc.c
@@ -55,7 +55,7 @@ LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
 #endif
 
 #if defined(CONFIG_HAS_CMSIS_CORE_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #if __DCACHE_PRESENT == 1
 #define CACHE_INVALIDATE(addr, size)	SCB_InvalidateDCache_by_Addr((addr), (size))
diff --git a/drivers/gpio/gpio_mchp_xec_v2.c b/drivers/gpio/gpio_mchp_xec_v2.c
index d24e944970846..3c89ed79c5ba6 100644
--- a/drivers/gpio/gpio_mchp_xec_v2.c
+++ b/drivers/gpio/gpio_mchp_xec_v2.c
@@ -13,7 +13,6 @@
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/irq.h>
 
 #include <zephyr/drivers/gpio/gpio_utils.h>
diff --git a/drivers/interrupt_controller/intc_mchp_ecia_xec.c b/drivers/interrupt_controller/intc_mchp_ecia_xec.c
index 29692c9dbd77e..64a8fa2b97b6a 100644
--- a/drivers/interrupt_controller/intc_mchp_ecia_xec.c
+++ b/drivers/interrupt_controller/intc_mchp_ecia_xec.c
@@ -13,7 +13,7 @@
 #define DT_DRV_COMPAT microchip_xec_ecia
 
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/device.h>
 #include <soc.h>
 #include <zephyr/sys/__assert.h>
diff --git a/drivers/kscan/kscan_mchp_xec.c b/drivers/kscan/kscan_mchp_xec.c
index 8b9231ba2d3d0..d3a39868c284f 100644
--- a/drivers/kscan/kscan_mchp_xec.c
+++ b/drivers/kscan/kscan_mchp_xec.c
@@ -6,7 +6,7 @@
 
 #define DT_DRV_COMPAT microchip_xec_kscan
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <errno.h>
 #include <zephyr/device.h>
 #ifdef CONFIG_SOC_SERIES_MEC172X
diff --git a/drivers/ps2/ps2_mchp_xec.c b/drivers/ps2/ps2_mchp_xec.c
index f2dd97d273811..ccd2957982e0f 100644
--- a/drivers/ps2/ps2_mchp_xec.c
+++ b/drivers/ps2/ps2_mchp_xec.c
@@ -7,7 +7,7 @@
 
 #define DT_DRV_COMPAT microchip_xec_ps2
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <errno.h>
 #include <zephyr/device.h>
 #include <zephyr/kernel.h>
diff --git a/drivers/serial/uart_lpc11u6x.c b/drivers/serial/uart_lpc11u6x.c
index 47a687c1618b9..23a65f5b34d46 100644
--- a/drivers/serial/uart_lpc11u6x.c
+++ b/drivers/serial/uart_lpc11u6x.c
@@ -5,7 +5,7 @@
  */
 #define DT_DRV_COMPAT nxp_lpc11u6x_uart
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #include <zephyr/drivers/uart.h>
 #include <zephyr/drivers/clock_control.h>
diff --git a/drivers/timer/cortex_m_systick.c b/drivers/timer/cortex_m_systick.c
index 53d85aa23e454..24c1457472c12 100644
--- a/drivers/timer/cortex_m_systick.c
+++ b/drivers/timer/cortex_m_systick.c
@@ -7,7 +7,7 @@
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/spinlock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
 
diff --git a/drivers/timer/mchp_xec_rtos_timer.c b/drivers/timer/mchp_xec_rtos_timer.c
index 65d11a2cfd53f..223c61e470bfc 100644
--- a/drivers/timer/mchp_xec_rtos_timer.c
+++ b/drivers/timer/mchp_xec_rtos_timer.c
@@ -12,7 +12,7 @@
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/spinlock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 
 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");
diff --git a/include/zephyr/arch/arm/aarch32/barrier.h b/include/zephyr/arch/arm/aarch32/barrier.h
index 60b60f84b6ee5..3b874c6bbd9b6 100644
--- a/include/zephyr/arch/arm/aarch32/barrier.h
+++ b/include/zephyr/arch/arm/aarch32/barrier.h
@@ -10,11 +10,7 @@
 #error Please include <zephyr/sys/barrier.h>
 #endif
 
-#if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#else
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
-#endif
+#include <cmsis_core.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h b/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h
index 38de02ab15ccf..e1e7071ef4729 100644
--- a/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h
+++ b/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h
@@ -1,66 +1,13 @@
 /*
- * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
- *
+ * Copyright (c) 2023 Nordic Semiconductor ASA
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/**
- * @file
- * @brief CMSIS interface file
- *
- * This header contains the interface to the ARM CMSIS Core headers.
- */
-
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
-
-#include <soc.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __CR_REV
-#define __CR_REV                0U
-#endif
-
-#ifndef __CA_REV
-#define __CA_REV                0U
-#endif
+#ifndef ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
+#define ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
 
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT           CONFIG_CPU_HAS_FPU
-#endif
-
-#ifndef __MMU_PRESENT
-#define __MMU_PRESENT           CONFIG_CPU_HAS_MMU
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#if defined(CONFIG_CPU_CORTEX_R4)
-#include <core_cr4.h>
-#elif defined(CONFIG_CPU_CORTEX_R5)
-#include <core_cr5.h>
-#elif defined(CONFIG_CPU_CORTEX_R7)
-#include <core_cr7.h>
-#elif defined(CONFIG_CPU_CORTEX_R52)
-#include <core_cr52.h>
-#elif defined(CONFIG_CPU_AARCH32_CORTEX_A)
-/*
- * Any defines relevant for the proper inclusion of CMSIS' Cortex-A
- * Common Peripheral Access Layer (such as __CORTEX_A) which are not
- * covered by the Kconfig-based default assignments above must be
- * provided by each aarch32 Cortex-A SoC's header file (already in-
- * cluded above).
- */
-#include <core_ca.h>
-#else
-#error "Unknown device"
-#endif
+#include <cmsis_core.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis_ext.h>
+#warning This header is deprecated, please include <cmsis_core.h>
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_ */
+#endif /* ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_ */
diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h b/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h
index c1615c7a15651..c4598302aaef3 100644
--- a/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h
+++ b/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h
@@ -16,7 +16,6 @@
 
 #include <zephyr/types.h>
 #include <zephyr/sys/sys_io.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 #include <zephyr/sys/barrier.h>
 
 #ifdef __cplusplus
diff --git a/include/zephyr/arch/arm/aarch32/cortex_m/cmsis.h b/include/zephyr/arch/arm/aarch32/cortex_m/cmsis.h
index 541f12a73e95b..c16b008c7a61e 100644
--- a/include/zephyr/arch/arm/aarch32/cortex_m/cmsis.h
+++ b/include/zephyr/arch/arm/aarch32/cortex_m/cmsis.h
@@ -1,108 +1,13 @@
 /*
- * Copyright (c) 2017 Nordic Semiconductor ASA
- *
+ * Copyright (c) 2023 Nordic Semiconductor ASA
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/**
- * @file
- * @brief CMSIS interface file
- *
- * This header contains the interface to the ARM CMSIS Core headers.
- */
-
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
-
-#include <zephyr/arch/arm/aarch32/cortex_m/nvic.h>
-
-#include <soc.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
- * Use __NVIC_PRIO_BITS as it is required and simple to check, but
- * ultimately all SoCs will define their own CMSIS types and constants.
- */
-#ifndef __NVIC_PRIO_BITS
-typedef enum {
-	Reset_IRQn                    = -15,
-	NonMaskableInt_IRQn           = -14,
-	HardFault_IRQn                = -13,
-#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	MemoryManagement_IRQn         = -12,
-	BusFault_IRQn                 = -11,
-	UsageFault_IRQn               = -10,
-#if defined(CONFIG_ARM_SECURE_FIRMWARE)
-	SecureFault_IRQn              = -9,
-#endif /* CONFIG_ARM_SECURE_FIRMWARE */
-#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
-	SVCall_IRQn                   =  -5,
-	DebugMonitor_IRQn             =  -4,
-	PendSV_IRQn                   =  -2,
-	SysTick_IRQn                  =  -1,
-	Max_IRQn                      =  CONFIG_NUM_IRQS,
-} IRQn_Type;
-
-#if defined(CONFIG_CPU_CORTEX_M0)
-#define __CM0_REV        0
-#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
-#define __CM0PLUS_REV    0
-#elif defined(CONFIG_CPU_CORTEX_M1)
-#define __CM1_REV        0
-#elif defined(CONFIG_CPU_CORTEX_M3)
-#define __CM3_REV        0
-#elif defined(CONFIG_CPU_CORTEX_M4)
-#define __CM4_REV        0
-#elif defined(CONFIG_CPU_CORTEX_M7)
-#define __CM7_REV        0
-#elif defined(CONFIG_CPU_CORTEX_M23)
-#define __CM23_REV       0
-#elif defined(CONFIG_CPU_CORTEX_M33)
-#define __CM33_REV       0
-#elif defined(CONFIG_CPU_CORTEX_M55)
-#define __CM55_REV       0
-#else
-#error "Unknown Cortex-M device"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#endif
-#define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
-#define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
-#endif /* __NVIC_PRIO_BITS */
-
-#if __NVIC_PRIO_BITS != NUM_IRQ_PRIO_BITS
-#error "NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
-#endif
+#ifndef ZEPHYR_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
+#define ZEPHYR_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
 
-#ifdef __cplusplus
-}
-#endif
+#include <cmsis_core.h>
 
-#if defined(CONFIG_CPU_CORTEX_M0)
-#include <core_cm0.h>
-#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
-#include <core_cm0plus.h>
-#elif defined(CONFIG_CPU_CORTEX_M1)
-#include <core_cm1.h>
-#elif defined(CONFIG_CPU_CORTEX_M3)
-#include <core_cm3.h>
-#elif defined(CONFIG_CPU_CORTEX_M4)
-#include <core_cm4.h>
-#elif defined(CONFIG_CPU_CORTEX_M7)
-#include <core_cm7.h>
-#elif defined(CONFIG_CPU_CORTEX_M23)
-#include <core_cm23.h>
-#elif defined(CONFIG_CPU_CORTEX_M33)
-#include <core_cm33.h>
-#elif defined(CONFIG_CPU_CORTEX_M55)
-#include <core_cm55.h>
-#else
-#error "Unknown Cortex-M device"
-#endif
+#warning This header is deprecated, please include <cmsis_core.h>
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_ */
+#endif /* ZEPHYR_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_ */
diff --git a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h b/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h
index 963a1dd6e0e3a..e1b4ed9d19b3e 100644
--- a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h
+++ b/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h
@@ -7,9 +7,7 @@
 
 #ifndef _ASMLANGUAGE
 
-#if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#endif
+#include <cmsis_core.h>
 
 /* Convenience macros to represent the ARMv7-M-specific
  * configuration for memory access permission and
diff --git a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h b/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h
index 67a5a365993ff..0f919c70a3337 100644
--- a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h
+++ b/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h
@@ -32,7 +32,7 @@
 #define MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)
 #define MPU_RLAR_EN_Msk         (0x1UL)
 #else
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #endif
 
 /* Privileged No Access, Unprivileged No Access */
diff --git a/modules/Kconfig b/modules/Kconfig
index f8fa95538d665..a2dad7e9c4afb 100644
--- a/modules/Kconfig
+++ b/modules/Kconfig
@@ -17,7 +17,7 @@ comment "Optional modules. Make sure they're installed, via the project manifest
 source "modules/Kconfig.altera"
 source "modules/Kconfig.atmel"
 source "modules/Kconfig.chre"
-source "modules/Kconfig.cmsis"
+source "modules/cmsis/Kconfig"
 source "modules/Kconfig.cypress"
 source "modules/Kconfig.eos_s3"
 source "modules/Kconfig.esp32"
diff --git a/modules/cmsis/CMakeLists.txt b/modules/cmsis/CMakeLists.txt
new file mode 100644
index 0000000000000..59a8307a8fb5a
--- /dev/null
+++ b/modules/cmsis/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} cmsis)
+
+if(CONFIG_CPU_CORTEX_M OR CONFIG_CPU_AARCH32_CORTEX_A OR CONFIG_CPU_AARCH32_CORTEX_R)
+  zephyr_include_directories(.)
+endif()
diff --git a/modules/Kconfig.cmsis b/modules/cmsis/Kconfig
similarity index 88%
rename from modules/Kconfig.cmsis
rename to modules/cmsis/Kconfig
index 4802ddf239763..0bbcddd55e78c 100644
--- a/modules/Kconfig.cmsis
+++ b/modules/cmsis/Kconfig
@@ -25,7 +25,7 @@ menuconfig CMSIS_DSP
 	select REQUIRES_FULL_LIBC if !ARCH_POSIX
 
 if CMSIS_DSP
-source "modules/Kconfig.cmsis_dsp"
+source "modules/cmsis/Kconfig.cmsis_dsp"
 endif
 
 menuconfig CMSIS_NN
@@ -34,5 +34,5 @@ menuconfig CMSIS_NN
 	select CMSIS_DSP
 
 if CMSIS_NN
-source "modules/Kconfig.cmsis_nn"
+source "modules/cmsis/Kconfig.cmsis_nn"
 endif
diff --git a/modules/Kconfig.cmsis_dsp b/modules/cmsis/Kconfig.cmsis_dsp
similarity index 100%
rename from modules/Kconfig.cmsis_dsp
rename to modules/cmsis/Kconfig.cmsis_dsp
diff --git a/modules/Kconfig.cmsis_nn b/modules/cmsis/Kconfig.cmsis_nn
similarity index 100%
rename from modules/Kconfig.cmsis_nn
rename to modules/cmsis/Kconfig.cmsis_nn
diff --git a/modules/cmsis/cmsis_core.h b/modules/cmsis/cmsis_core.h
new file mode 100644
index 0000000000000..04e5566cc0a98
--- /dev/null
+++ b/modules/cmsis/cmsis_core.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_H_
+
+#if defined(CONFIG_CPU_CORTEX_M)
+#include "cmsis_core_m.h"
+#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
+#include "cmsis_core_a_r.h"
+#endif
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_ */
diff --git a/modules/cmsis/cmsis_core_a_r.h b/modules/cmsis/cmsis_core_a_r.h
new file mode 100644
index 0000000000000..9f4514edb474e
--- /dev/null
+++ b/modules/cmsis/cmsis_core_a_r.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief CMSIS interface file
+ *
+ * This header contains the interface to the ARM CMSIS Core headers.
+ */
+
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_
+
+#include <soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CR_REV
+#define __CR_REV                0U
+#endif
+
+#ifndef __CA_REV
+#define __CA_REV                0U
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT           CONFIG_CPU_HAS_FPU
+#endif
+
+#ifndef __MMU_PRESENT
+#define __MMU_PRESENT           CONFIG_CPU_HAS_MMU
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#if defined(CONFIG_CPU_CORTEX_R4)
+#include <core_cr4.h>
+#elif defined(CONFIG_CPU_CORTEX_R5)
+#include <core_cr5.h>
+#elif defined(CONFIG_CPU_CORTEX_R7)
+#include <core_cr7.h>
+#elif defined(CONFIG_CPU_CORTEX_R52)
+#include <core_cr52.h>
+#elif defined(CONFIG_CPU_AARCH32_CORTEX_A)
+/*
+ * Any defines relevant for the proper inclusion of CMSIS' Cortex-A
+ * Common Peripheral Access Layer (such as __CORTEX_A) which are not
+ * covered by the Kconfig-based default assignments above must be
+ * provided by each aarch32 Cortex-A SoC's header file (already in-
+ * cluded above).
+ */
+#include <core_ca.h>
+#else
+#error "Unknown device"
+#endif
+
+#include "cmsis_core_a_r_ext.h"
+
+#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_ */
diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis_ext.h b/modules/cmsis/cmsis_core_a_r_ext.h
similarity index 90%
rename from include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis_ext.h
rename to modules/cmsis/cmsis_core_a_r_ext.h
index 911885d0bf2a1..0752b1474fa2b 100644
--- a/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis_ext.h
+++ b/modules/cmsis/cmsis_core_a_r_ext.h
@@ -15,8 +15,8 @@
  * NOTE: cmsis.h includes this file; do not manually include this file.
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_EXT_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_EXT_H_
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_A_R_EXT_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_A_R_EXT_H_
 
 /* FSR Register Definitions */
 #if defined(CONFIG_AARCH32_ARMV8_R)
@@ -74,4 +74,4 @@ __STATIC_FORCEINLINE uint32_t __get_DBGDSCR(void)
 	return result;
 }
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_EXT_H_ */
+#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_A_R_EXT_H_ */
diff --git a/modules/cmsis/cmsis_core_m.h b/modules/cmsis/cmsis_core_m.h
new file mode 100644
index 0000000000000..849c496a9bde4
--- /dev/null
+++ b/modules/cmsis/cmsis_core_m.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2017 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief CMSIS interface file
+ *
+ * This header contains the interface to the ARM CMSIS Core headers.
+ */
+
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
+
+#include <zephyr/arch/arm/aarch32/cortex_m/nvic.h>
+
+#include <soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
+ * Use __NVIC_PRIO_BITS as it is required and simple to check, but
+ * ultimately all SoCs will define their own CMSIS types and constants.
+ */
+#ifndef __NVIC_PRIO_BITS
+typedef enum {
+	Reset_IRQn                    = -15,
+	NonMaskableInt_IRQn           = -14,
+	HardFault_IRQn                = -13,
+#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	MemoryManagement_IRQn         = -12,
+	BusFault_IRQn                 = -11,
+	UsageFault_IRQn               = -10,
+#if defined(CONFIG_ARM_SECURE_FIRMWARE)
+	SecureFault_IRQn              = -9,
+#endif /* CONFIG_ARM_SECURE_FIRMWARE */
+#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
+	SVCall_IRQn                   =  -5,
+	DebugMonitor_IRQn             =  -4,
+	PendSV_IRQn                   =  -2,
+	SysTick_IRQn                  =  -1,
+	Max_IRQn                      =  CONFIG_NUM_IRQS,
+} IRQn_Type;
+
+#if defined(CONFIG_CPU_CORTEX_M0)
+#define __CM0_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
+#define __CM0PLUS_REV    0
+#elif defined(CONFIG_CPU_CORTEX_M1)
+#define __CM1_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M3)
+#define __CM3_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M4)
+#define __CM4_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M7)
+#define __CM7_REV        0
+#elif defined(CONFIG_CPU_CORTEX_M23)
+#define __CM23_REV       0
+#elif defined(CONFIG_CPU_CORTEX_M33)
+#define __CM33_REV       0
+#elif defined(CONFIG_CPU_CORTEX_M55)
+#define __CM55_REV       0
+#else
+#error "Unknown Cortex-M device"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#endif
+#define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
+#define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
+#endif /* __NVIC_PRIO_BITS */
+
+#if __NVIC_PRIO_BITS != NUM_IRQ_PRIO_BITS
+#error "NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#if defined(CONFIG_CPU_CORTEX_M0)
+#include <core_cm0.h>
+#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
+#include <core_cm0plus.h>
+#elif defined(CONFIG_CPU_CORTEX_M1)
+#include <core_cm1.h>
+#elif defined(CONFIG_CPU_CORTEX_M3)
+#include <core_cm3.h>
+#elif defined(CONFIG_CPU_CORTEX_M4)
+#include <core_cm4.h>
+#elif defined(CONFIG_CPU_CORTEX_M7)
+#include <core_cm7.h>
+#elif defined(CONFIG_CPU_CORTEX_M23)
+#include <core_cm23.h>
+#elif defined(CONFIG_CPU_CORTEX_M33)
+#include <core_cm33.h>
+#elif defined(CONFIG_CPU_CORTEX_M55)
+#include <core_cm55.h>
+#else
+#error "Unknown Cortex-M device"
+#endif
+
+#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_H_ */
diff --git a/modules/trusted-firmware-m/interface/interface.c b/modules/trusted-firmware-m/interface/interface.c
index 9cbcf5636c654..c89a572a788c6 100644
--- a/modules/trusted-firmware-m/interface/interface.c
+++ b/modules/trusted-firmware-m/interface/interface.c
@@ -8,7 +8,6 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/fpu.h>
 
 #include <tfm_ns_interface.h>
diff --git a/samples/application_development/code_relocation_nocopy/src/main.c b/samples/application_development/code_relocation_nocopy/src/main.c
index 402634b27189f..025fec384c8bb 100644
--- a/samples/application_development/code_relocation_nocopy/src/main.c
+++ b/samples/application_development/code_relocation_nocopy/src/main.c
@@ -15,7 +15,7 @@
  * to configure the region appropriately in arm_mpu_regions.c.
  */
 #ifdef CONFIG_ARM_MPU
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 void disable_mpu_rasr_xn(void)
 {
 	uint32_t index;
diff --git a/samples/subsys/debug/debugmon/src/main.c b/samples/subsys/debug/debugmon/src/main.c
index a1554e629636c..afb5320ff13af 100644
--- a/samples/subsys/debug/debugmon/src/main.c
+++ b/samples/subsys/debug/debugmon/src/main.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/sys/printk.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/exc.h>
 
 #define LED0_NODE DT_ALIAS(led0)
diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/soc.c b/soc/arm/arm/fvp_aemv8r_aarch32/soc.c
index cca6d2622cccc..56532ce9a9f94 100644
--- a/soc/arm/arm/fvp_aemv8r_aarch32/soc.c
+++ b/soc/arm/arm/fvp_aemv8r_aarch32/soc.c
@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 void z_arm_platform_init(void)
diff --git a/soc/arm/atmel_sam/sam3x/soc.c b/soc/arm/atmel_sam/sam3x/soc.c
index 7e9e997910f8e..6f85c2c69d7df 100644
--- a/soc/arm/atmel_sam/sam3x/soc.c
+++ b/soc/arm/atmel_sam/sam3x/soc.c
@@ -18,7 +18,6 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 /*
  * PLL clock = Main * (MULA + 1) / DIVA
diff --git a/soc/arm/atmel_sam/sam4e/soc.c b/soc/arm/atmel_sam/sam4e/soc.c
index 2b374da455630..33a8dd0d25fd5 100644
--- a/soc/arm/atmel_sam/sam4e/soc.c
+++ b/soc/arm/atmel_sam/sam4e/soc.c
@@ -18,7 +18,6 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  * @brief Setup various clock on SoC at boot time.
diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c
index 9937fcd6c80e9..e1041f8a2fcf3 100644
--- a/soc/arm/atmel_sam/sam4s/soc.c
+++ b/soc/arm/atmel_sam/sam4s/soc.c
@@ -18,7 +18,6 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  * @brief Setup various clock on SoC at boot time.
diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index a20632e6ede4a..79d7c9fa830ee 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c
@@ -15,7 +15,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c
index 53f4dfd3795ee..7571ce46dc710 100644
--- a/soc/arm/atmel_sam/samv71/soc.c
+++ b/soc/arm/atmel_sam/samv71/soc.c
@@ -15,7 +15,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
diff --git a/soc/arm/atmel_sam0/common/soc_samd2x.c b/soc/arm/atmel_sam0/common/soc_samd2x.c
index d5ff7cd162632..bc488ab724c87 100644
--- a/soc/arm/atmel_sam0/common/soc_samd2x.c
+++ b/soc/arm/atmel_sam0/common/soc_samd2x.c
@@ -22,12 +22,12 @@
  * GCLK Gen 3 -> ADC @ 8 MHz
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 
 #include <soc.h>
+#include <cmsis_core.h>
 
 /**
  * Fix different naming conventions for SAMD20
diff --git a/soc/arm/atmel_sam0/common/soc_saml2x.c b/soc/arm/atmel_sam0/common/soc_saml2x.c
index 3045c4dc24cf7..c4c1a659dd668 100644
--- a/soc/arm/atmel_sam0/common/soc_saml2x.c
+++ b/soc/arm/atmel_sam0/common/soc_saml2x.c
@@ -10,11 +10,11 @@
  * @brief Atmel SAML MCU series initialization code
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <soc.h>
+#include <cmsis_core.h>
 
 /* the SAML21 currently operates only in Performance Level 2... sleep
  * and low-power operation are not currently supported by the BSP
diff --git a/soc/arm/cypress/psoc6/soc.c b/soc/arm/cypress/psoc6/soc.c
index 9a5baefea106c..d75693744e4ac 100644
--- a/soc/arm/cypress/psoc6/soc.c
+++ b/soc/arm/cypress/psoc6/soc.c
@@ -7,7 +7,6 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/irq.h>
 
 #include "cy_syslib.h"
diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.c b/soc/arm/intel_socfpga_std/cyclonev/soc.c
index c00964600a40e..70e697dd62baa 100644
--- a/soc/arm/intel_socfpga_std/cyclonev/soc.c
+++ b/soc/arm/intel_socfpga_std/cyclonev/soc.c
@@ -12,9 +12,10 @@
 #include <zephyr/sys/util.h>
 #include <mmu.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 #include "soc.h"
 
+#include <cmsis_core.h>
+
 void arch_reserved_pages_update(void)
 {
 /* Function created to reserve the vector table  */
diff --git a/soc/arm/microchip_mec/mec1501/soc.c b/soc/arm/microchip_mec/mec1501/soc.c
index 11960427ae6ed..27fd059c339f2 100644
--- a/soc/arm/microchip_mec/mec1501/soc.c
+++ b/soc/arm/microchip_mec/mec1501/soc.c
@@ -10,7 +10,7 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /*
  * Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC
diff --git a/soc/arm/microchip_mec/mec172x/power.c b/soc/arm/microchip_mec/mec172x/power.c
index 0f31cca31288f..6c56ea62850e0 100644
--- a/soc/arm/microchip_mec/mec172x/power.c
+++ b/soc/arm/microchip_mec/mec172x/power.c
@@ -11,7 +11,7 @@
 #include <zephyr/pm/pm.h>
 #include <soc.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include "device_power.h"
 
 #include "soc_power_debug.h"
diff --git a/soc/arm/microchip_mec/mec172x/soc.c b/soc/arm/microchip_mec/mec172x/soc.c
index e8edd7e7aaef9..9de2f7ce552bd 100644
--- a/soc/arm/microchip_mec/mec172x/soc.c
+++ b/soc/arm/microchip_mec/mec172x/soc.c
@@ -10,7 +10,7 @@
 #include <soc.h>
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /* Enable SWD and ETM debug interface and pins.
  * NOTE: ETM TRACE pins exposed on MEC172x EVB J30 12,14,16,18,20.
diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/arm/nordic_nrf/nrf52/soc.c
index fe610a1aa45f7..52b97164e72bd 100644
--- a/soc/arm/nordic_nrf/nrf52/soc.c
+++ b/soc/arm/nordic_nrf/nrf52/soc.c
@@ -14,11 +14,12 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <hal/nrf_power.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/nordic_nrf/nrf53/soc.c b/soc/arm/nordic_nrf/nrf53/soc.c
index be2c36c3bbe29..6552f9d4bb160 100644
--- a/soc/arm/nordic_nrf/nrf53/soc.c
+++ b/soc/arm/nordic_nrf/nrf53/soc.c
@@ -14,7 +14,6 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 #include <nrf_erratas.h>
@@ -34,6 +33,8 @@
 #endif
 #include <soc_secure.h>
 
+#include <cmsis_core.h>
+
 #define PIN_XL1 0
 #define PIN_XL2 1
 
diff --git a/soc/arm/nordic_nrf/nrf91/soc.c b/soc/arm/nordic_nrf/nrf91/soc.c
index 500d26ee76b6e..5eb6342e6909b 100644
--- a/soc/arm/nordic_nrf/nrf91/soc.c
+++ b/soc/arm/nordic_nrf/nrf91/soc.c
@@ -14,10 +14,11 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/nuvoton_npcx/common/power.c b/soc/arm/nuvoton_npcx/common/power.c
index e7fe036f7669e..ea36d4b37f7d6 100644
--- a/soc/arm/nuvoton_npcx/common/power.c
+++ b/soc/arm/nuvoton_npcx/common/power.c
@@ -45,7 +45,7 @@
  * INCLUDE FILES: soc_clock.h
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/espi.h>
diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
index e9a3b1d4df61d..cccff03125ecf 100644
--- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c
+++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
@@ -8,9 +8,10 @@
 #include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include "wdog_imx.h"
 
+#include <cmsis_core.h>
+
 /* Initialize Resource Domain Controller. */
 static void SOC_RdcInit(void)
 {
diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c
index 914d568563f18..e61eb87144120 100644
--- a/soc/arm/nxp_imx/rt/soc_rt10xx.c
+++ b/soc/arm/nxp_imx/rt/soc_rt10xx.c
@@ -11,7 +11,6 @@
 #include <zephyr/linker/sections.h>
 #include <zephyr/linker/linker-defs.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
 #include <fsl_flexspi_nor_boot.h>
 #endif
@@ -22,6 +21,8 @@
 #include "usb.h"
 #endif
 
+#include <cmsis_core.h>
+
 #define CCM_NODE	DT_INST(0, nxp_imx_ccm)
 
 #define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b)				\
diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c
index 6efa7a3aada18..5e1b34476e87d 100644
--- a/soc/arm/nxp_imx/rt/soc_rt11xx.c
+++ b/soc/arm/nxp_imx/rt/soc_rt11xx.c
@@ -14,7 +14,6 @@
 #include <fsl_gpc.h>
 #include <fsl_pmu.h>
 #include <fsl_dcdc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
 #include <fsl_flexspi_nor_boot.h>
 #endif
@@ -35,6 +34,8 @@
 #include "usb.h"
 #endif
 
+#include <cmsis_core.h>
+
 #define DUAL_CORE_MU_ENABLED \
 	(CONFIG_SECOND_CORE_MCUX && CONFIG_IPM && CONFIG_IPM_IMX_REV2)
 
diff --git a/soc/arm/nxp_kinetis/k2x/soc.c b/soc/arm/nxp_kinetis/k2x/soc.c
index dedb1367060a7..67ea1183401de 100644
--- a/soc/arm/nxp_kinetis/k2x/soc.c
+++ b/soc/arm/nxp_kinetis/k2x/soc.c
@@ -23,7 +23,7 @@
 #include <fsl_common.h>
 #include <fsl_clock.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #define TIMESRC_OSCERCLK        (2)
 
diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/arm/nxp_kinetis/k6x/soc.c
index 1464df9a3276e..083f695db32c7 100644
--- a/soc/arm/nxp_kinetis/k6x/soc.c
+++ b/soc/arm/nxp_kinetis/k6x/soc.c
@@ -20,7 +20,8 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 #define LPUART0SRC_OSCERCLK     (1)
 
diff --git a/soc/arm/nxp_kinetis/ke1xf/soc.c b/soc/arm/nxp_kinetis/ke1xf/soc.c
index b48ed1a888638..b2c0ce95c5600 100644
--- a/soc/arm/nxp_kinetis/ke1xf/soc.c
+++ b/soc/arm/nxp_kinetis/ke1xf/soc.c
@@ -13,7 +13,7 @@
 #include <zephyr/init.h>
 #include <fsl_clock.h>
 #include <fsl_cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #define ASSERT_WITHIN_RANGE(val, min, max, str) \
 	BUILD_ASSERT(val >= min && val <= max, str)
diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
index eaecced4ae1bc..8a6b0f8045b78 100644
--- a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
+++ b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
@@ -13,7 +13,8 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 #define PLLFLLSEL_MCGFLLCLK	(0)
 #define PLLFLLSEL_MCGPLLCLK	(1)
diff --git a/soc/arm/nxp_s32/s32k/soc.c b/soc/arm/nxp_s32/s32k/soc.c
index 502a411ac4b3d..5db4204a89ca5 100644
--- a/soc/arm/nxp_s32/s32k/soc.c
+++ b/soc/arm/nxp_s32/s32k/soc.c
@@ -7,8 +7,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
+#include <cmsis_core.h>
 #include <OsIf.h>
 
 #ifdef CONFIG_XIP
diff --git a/soc/arm/nxp_s32/s32ze/soc.c b/soc/arm/nxp_s32/s32ze/soc.c
index 5e242d413ae07..4a1837f9dca09 100644
--- a/soc/arm/nxp_s32/s32ze/soc.c
+++ b/soc/arm/nxp_s32/s32ze/soc.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 #include <OsIf.h>
diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/arm/quicklogic_eos_s3/soc.c
index ed2cdb70ef964..ff18c3727408f 100644
--- a/soc/arm/quicklogic_eos_s3/soc.c
+++ b/soc/arm/quicklogic_eos_s3/soc.c
@@ -8,7 +8,7 @@
 #include <zephyr/init.h>
 #include <soc.h>
 #include <soc_pinmap.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 void eos_s3_lock_enable(void)
 {
diff --git a/soc/arm/renesas_smartbond/da1469x/soc.c b/soc/arm/renesas_smartbond/da1469x/soc.c
index 531bd4b1146f3..5fc566748c6c1 100644
--- a/soc/arm/renesas_smartbond/da1469x/soc.c
+++ b/soc/arm/renesas_smartbond/da1469x/soc.c
@@ -5,7 +5,6 @@
  */
 
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <DA1469xAB.h>
@@ -14,6 +13,7 @@
 #include <da1469x_pd.h>
 #include <da1469x_pdc.h>
 #include <da1469x_trimv.h>
+#include <cmsis_core.h>
 
 #define REMAP_ADR0_QSPI           0x2
 
diff --git a/soc/arm/silabs_exx32/common/soc.c b/soc/arm/silabs_exx32/common/soc.c
index c2e152aec0805..0aab80ea06b4d 100644
--- a/soc/arm/silabs_exx32/common/soc.c
+++ b/soc/arm/silabs_exx32/common/soc.c
@@ -9,7 +9,6 @@
  * @brief Common SoC initialization for the EXX32
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
@@ -18,6 +17,7 @@
 #include <em_cmu.h>
 #include <em_emu.h>
 #include <soc.h>
+#include <cmsis_core.h>
 
 #ifdef CONFIG_SOC_GECKO_DEV_INIT
 #include <sl_device_init_dcdc.h>
diff --git a/soc/arm/st_stm32/stm32c0/soc.c b/soc/arm/st_stm32/stm32c0/soc.c
index 14ad99a278dbc..65a7c518a0f64 100644
--- a/soc/arm/st_stm32/stm32c0/soc.c
+++ b/soc/arm/st_stm32/stm32c0/soc.c
@@ -11,10 +11,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
diff --git a/soc/arm/st_stm32/stm32f0/soc.c b/soc/arm/st_stm32/stm32f0/soc.c
index a59e9214203cc..c50512cc389f7 100644
--- a/soc/arm/st_stm32/stm32f0/soc.c
+++ b/soc/arm/st_stm32/stm32f0/soc.c
@@ -12,10 +12,11 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <cmsis_core.h>
+
 #if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
 extern void *_vector_table_pointer;
 #endif
diff --git a/soc/arm/st_stm32/stm32f1/soc.c b/soc/arm/st_stm32/stm32f1/soc.c
index b4f034dbc257b..69492f2340289 100644
--- a/soc/arm/st_stm32/stm32f1/soc.c
+++ b/soc/arm/st_stm32/stm32f1/soc.c
@@ -11,7 +11,8 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
diff --git a/soc/arm/st_stm32/stm32f2/soc.c b/soc/arm/st_stm32/stm32f2/soc.c
index 89e711b62c42f..fee0be753bd03 100644
--- a/soc/arm/st_stm32/stm32f2/soc.c
+++ b/soc/arm/st_stm32/stm32f2/soc.c
@@ -13,11 +13,12 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <stm32_ll_system.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
diff --git a/soc/arm/st_stm32/stm32f3/soc.c b/soc/arm/st_stm32/stm32f3/soc.c
index 97a29e35a8d2b..74a5bc40b40f6 100644
--- a/soc/arm/st_stm32/stm32f3/soc.c
+++ b/soc/arm/st_stm32/stm32f3/soc.c
@@ -12,7 +12,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
diff --git a/soc/arm/st_stm32/stm32f4/soc.c b/soc/arm/st_stm32/stm32f4/soc.c
index 66f1bb7e7959a..3583615a09705 100644
--- a/soc/arm/st_stm32/stm32f4/soc.c
+++ b/soc/arm/st_stm32/stm32f4/soc.c
@@ -12,8 +12,8 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
+#include <cmsis_core.h>
 #include <stm32_ll_system.h>
 
 /**
diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/arm/st_stm32/stm32f7/soc.c
index 2f42610403c23..b06a894197aaa 100644
--- a/soc/arm/st_stm32/stm32f7/soc.c
+++ b/soc/arm/st_stm32/stm32f7/soc.c
@@ -13,7 +13,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 #include <stm32_ll_system.h>
 
 /**
diff --git a/soc/arm/st_stm32/stm32g0/soc.c b/soc/arm/st_stm32/stm32g0/soc.c
index 15a3f9b27fc76..77c66858a2f77 100644
--- a/soc/arm/st_stm32/stm32g0/soc.c
+++ b/soc/arm/st_stm32/stm32g0/soc.c
@@ -12,9 +12,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
+
+#include <cmsis_core.h>
 #if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
 #include <stm32_ll_system.h>
 #include <stm32_ll_bus.h>
diff --git a/soc/arm/st_stm32/stm32g4/soc.c b/soc/arm/st_stm32/stm32g4/soc.c
index ddc48c801f4d2..94600c48327dd 100644
--- a/soc/arm/st_stm32/stm32g4/soc.c
+++ b/soc/arm/st_stm32/stm32g4/soc.c
@@ -12,8 +12,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
+#include <cmsis_core.h>
 #if defined(PWR_CR3_UCPD_DBDIS)
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
diff --git a/soc/arm/st_stm32/stm32h5/soc.c b/soc/arm/st_stm32/stm32h5/soc.c
index 67a5075024e23..206e4deae234b 100644
--- a/soc/arm/st_stm32/stm32h5/soc.c
+++ b/soc/arm/st_stm32/stm32h5/soc.c
@@ -14,9 +14,10 @@
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_icache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/st_stm32/stm32h7/soc_m4.c b/soc/arm/st_stm32/stm32h7/soc_m4.c
index 7bd4a9ec0ecc6..e2fe8955119a0 100644
--- a/soc/arm/st_stm32/stm32h7/soc_m4.c
+++ b/soc/arm/st_stm32/stm32h7/soc_m4.c
@@ -18,9 +18,10 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include "stm32_hsem.h"
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
diff --git a/soc/arm/st_stm32/stm32h7/soc_m7.c b/soc/arm/st_stm32/stm32h7/soc_m7.c
index 46b871dfb9073..8e72b3ee390c1 100644
--- a/soc/arm/st_stm32/stm32h7/soc_m7.c
+++ b/soc/arm/st_stm32/stm32h7/soc_m7.c
@@ -17,9 +17,10 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include "stm32_hsem.h"
 
+#include <cmsis_core.h>
+
 #if defined(CONFIG_STM32H7_DUAL_CORE)
 static int stm32h7_m4_wakeup(void)
 {
diff --git a/soc/arm/st_stm32/stm32l0/soc.c b/soc/arm/st_stm32/stm32l0/soc.c
index 247a61d13333b..06157dda097c3 100644
--- a/soc/arm/st_stm32/stm32l0/soc.c
+++ b/soc/arm/st_stm32/stm32l0/soc.c
@@ -11,13 +11,14 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_bus.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
diff --git a/soc/arm/st_stm32/stm32l1/soc.c b/soc/arm/st_stm32/stm32l1/soc.c
index 20b3af7f3d7da..aee0b089dce5c 100644
--- a/soc/arm/st_stm32/stm32l1/soc.c
+++ b/soc/arm/st_stm32/stm32l1/soc.c
@@ -11,12 +11,13 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
diff --git a/soc/arm/st_stm32/stm32l4/soc.c b/soc/arm/st_stm32/stm32l4/soc.c
index 61cf5e6d36acb..48cd59b901276 100644
--- a/soc/arm/st_stm32/stm32l4/soc.c
+++ b/soc/arm/st_stm32/stm32l4/soc.c
@@ -12,9 +12,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/st_stm32/stm32l5/soc.c b/soc/arm/st_stm32/stm32l5/soc.c
index fb7b956d72d45..349868e2edaf7 100644
--- a/soc/arm/st_stm32/stm32l5/soc.c
+++ b/soc/arm/st_stm32/stm32l5/soc.c
@@ -13,10 +13,11 @@
 #include <zephyr/init.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <stm32l5xx_ll_icache.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/st_stm32/stm32mp1/soc.c b/soc/arm/st_stm32/stm32mp1/soc.c
index fc95eab56ad7e..c1bedf8e20955 100644
--- a/soc/arm/st_stm32/stm32mp1/soc.c
+++ b/soc/arm/st_stm32/stm32mp1/soc.c
@@ -14,7 +14,8 @@
 #include <zephyr/init.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
diff --git a/soc/arm/st_stm32/stm32u5/soc.c b/soc/arm/st_stm32/stm32u5/soc.c
index a775a1d200031..d25fec9c680d5 100644
--- a/soc/arm/st_stm32/stm32u5/soc.c
+++ b/soc/arm/st_stm32/stm32u5/soc.c
@@ -14,9 +14,10 @@
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_icache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/st_stm32/stm32wb/soc.c b/soc/arm/st_stm32/stm32wb/soc.c
index 3fd07aefb9752..01364c241e109 100644
--- a/soc/arm/st_stm32/stm32wb/soc.c
+++ b/soc/arm/st_stm32/stm32wb/soc.c
@@ -11,9 +11,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/st_stm32/stm32wba/soc.c b/soc/arm/st_stm32/stm32wba/soc.c
index c5eb75a3454bc..9d027af604ff9 100644
--- a/soc/arm/st_stm32/stm32wba/soc.c
+++ b/soc/arm/st_stm32/stm32wba/soc.c
@@ -16,10 +16,10 @@
 #include <stm32_ll_icache.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/irq.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/st_stm32/stm32wl/soc.c b/soc/arm/st_stm32/stm32wl/soc.c
index 928f97429c559..3fec4bc3c56c2 100644
--- a/soc/arm/st_stm32/stm32wl/soc.c
+++ b/soc/arm/st_stm32/stm32wl/soc.c
@@ -11,12 +11,13 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 #include <stm32wlxx_ll_system.h>
 
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
diff --git a/soc/arm/ti_lm3s6965/sys_arch_reboot.c b/soc/arm/ti_lm3s6965/sys_arch_reboot.c
index 341f26218ed3c..244abf4c3098a 100644
--- a/soc/arm/ti_lm3s6965/sys_arch_reboot.c
+++ b/soc/arm/ti_lm3s6965/sys_arch_reboot.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /**
  *
diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c
index 253bd31c83cba..5c7317ac3f748 100644
--- a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c
+++ b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c
@@ -9,7 +9,7 @@
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "soc.h"
 
diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c
index f3b1137cb28de..7f794c5e9f7d2 100644
--- a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c
+++ b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c
@@ -9,7 +9,7 @@
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "soc.h"
 
diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/arm/xilinx_zynqmp/soc.c
index f84dc48f74e5d..242557ed7256d 100644
--- a/soc/arm/xilinx_zynqmp/soc.c
+++ b/soc/arm/xilinx_zynqmp/soc.c
@@ -7,7 +7,8 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+
+#include <cmsis_core.h>
 
 void z_arm_platform_init(void)
 {
diff --git a/subsys/testsuite/include/zephyr/interrupt_util.h b/subsys/testsuite/include/zephyr/interrupt_util.h
index 68f2632235f8c..e5dbf8b91acd4 100644
--- a/subsys/testsuite/include/zephyr/interrupt_util.h
+++ b/subsys/testsuite/include/zephyr/interrupt_util.h
@@ -10,7 +10,7 @@
 #define MS_TO_US(ms)  (ms * USEC_PER_MSEC)
 
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 static inline uint32_t get_available_nvic_line(uint32_t initial_offset)
 {
diff --git a/tests/application_development/code_relocation/src/main.c b/tests/application_development/code_relocation/src/main.c
index 6816938165c4a..4a7d903cc4625 100644
--- a/tests/application_development/code_relocation/src/main.c
+++ b/tests/application_development/code_relocation/src/main.c
@@ -17,7 +17,7 @@
  */
 
 #if (defined(CONFIG_ARM_MPU) && !defined(CONFIG_CPU_HAS_NXP_MPU))
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 void disable_mpu_rasr_xn(void)
 {
 	uint32_t index;
diff --git a/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c b/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c
index eb3ace8a00abc..1e7ac1ef71f84 100644
--- a/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c
+++ b/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/reboot.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/ztest.h>
 #include <zephyr/tc_util.h>
 
diff --git a/tests/arch/arm/arm_interrupt/src/arm_interrupt.c b/tests/arch/arm/arm_interrupt/src/arm_interrupt.c
index 011a151f25fba..6ef95fb01852c 100644
--- a/tests/arch/arm/arm_interrupt/src/arm_interrupt.c
+++ b/tests/arch/arm/arm_interrupt/src/arm_interrupt.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 static volatile int test_flag;
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c
index 14a93158bf8e6..4d46851faef0b 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 /* Offset for the Direct interrupt used in this test. */
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c
index 0f0cb2573453c..802385fa0e530 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #if defined(CONFIG_ARM_SECURE_FIRMWARE) && \
 	defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
index 70538ee2b6405..67adbc7e9c2a3 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 static volatile int test_flag;
diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
index f51291cd958f2..7d7930661099f 100644
--- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
+++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/linker/sections.h>
 
 
diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c b/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c
index 74a30858073d2..8a145884b747b 100644
--- a/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c
+++ b/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 
diff --git a/tests/arch/arm/arm_no_multithreading/src/main.c b/tests/arch/arm/arm_no_multithreading/src/main.c
index 1765b3d64ddd7..d525470edeca9 100644
--- a/tests/arch/arm/arm_no_multithreading/src/main.c
+++ b/tests/arch/arm/arm_no_multithreading/src/main.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/__assert.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 #if !defined(CONFIG_CPU_CORTEX_M)
diff --git a/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c b/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c
index 55c2cbae27439..870993c59e710 100644
--- a/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c
+++ b/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c
@@ -8,7 +8,7 @@
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/reboot.h>
 #include <zephyr/sys/barrier.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/nmi.h>
 #include <zephyr/ztest.h>
 #include <zephyr/tc_util.h>
diff --git a/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c b/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c
index 80f722795e748..c728864c05f88 100644
--- a/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c
+++ b/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c
@@ -9,7 +9,7 @@
 #include <zephyr/syscall_handler.h>
 #include <zephyr/toolchain.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 extern uint32_t _vector_table;
 extern uint32_t __vector_relay_handler;
diff --git a/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c b/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c
index 1498788ae3829..ec642909573c6 100644
--- a/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c
+++ b/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/kernel_structs.h>
 #include <zephyr/sys/barrier.h>
 #include <offsets_short_arch.h>
diff --git a/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c b/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
index a5a3faedc4d82..0c98869bbed4b 100644
--- a/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
+++ b/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/kernel_structs.h>
 #include <zephyr/sys/barrier.h>
 #include <offsets_short_arch.h>
diff --git a/tests/arch/arm/arm_tz_wrap_func/src/main.c b/tests/arch/arm/arm_tz_wrap_func/src/main.c
index cbbbf559f3d4a..0323bd5061768 100644
--- a/tests/arch/arm/arm_tz_wrap_func/src/main.c
+++ b/tests/arch/arm/arm_tz_wrap_func/src/main.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <aarch32/cortex_m/tz_ns.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 static bool expect_preface;
 static bool expect_postface;
diff --git a/tests/benchmarks/cmsis_dsp/common/benchmark_common.h b/tests/benchmarks/cmsis_dsp/common/benchmark_common.h
index e2f65b88f5dc1..6862064bd810c 100644
--- a/tests/benchmarks/cmsis_dsp/common/benchmark_common.h
+++ b/tests/benchmarks/cmsis_dsp/common/benchmark_common.h
@@ -13,7 +13,7 @@
 #if defined(CONFIG_CPU_CORTEX_M_HAS_DWT)
 /* Use cycle counting on the Cortex-M devices that support DWT */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 static ALWAYS_INLINE void benchmark_begin(uint32_t *irq_key, uint32_t *timestamp)
 {
diff --git a/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c b/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
index db91d09f11995..fbf02f2682b8f 100644
--- a/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
+++ b/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
@@ -151,7 +151,7 @@ ZTEST(k_float_disable, test_k_float_disable_syscall)
 
 #include <zephyr/arch/cpu.h>
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #else
 #include <zephyr/interrupt_util.h>
 #endif
diff --git a/tests/kernel/mem_protect/protection/src/main.c b/tests/kernel/mem_protect/protection/src/main.c
index fcd14e1eff4f2..328531f54af63 100644
--- a/tests/kernel/mem_protect/protection/src/main.c
+++ b/tests/kernel/mem_protect/protection/src/main.c
@@ -35,7 +35,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *pEsf)
 }
 
 #ifdef CONFIG_CPU_CORTEX_M
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 /* Must clear LSB of function address to access as data. */
 #define FUNC_TO_PTR(x) (void *)((uintptr_t)(x) & ~0x1)
 /* Must set LSB of function address to call in Thumb mode. */
diff --git a/west.yml b/west.yml
index b518c13b1bee4..6f13b52e900f6 100644
--- a/west.yml
+++ b/west.yml
@@ -122,7 +122,7 @@ manifest:
       revision: b7955c27e50485b7dafdc3888d7d6afdc2ac6d96
       path: modules/lib/chre
     - name: cmsis
-      revision: 74981bf893e8b10931464b9945e2143d99a3f0a3
+      revision: 1abf29132e608826752e2edd1f4799a065db4031
       path: modules/hal/cmsis
       groups:
         - hal
@@ -281,7 +281,7 @@ manifest:
       groups:
         - crypto
     - name: mcuboot
-      revision: fc658eb5a22b7b1721c3b7d0853a7115fae08939
+      revision: 010019e0f934d0d1288ad522c86600cd066920ae
       path: bootloader/mcuboot
     - name: mipi-sys-t
       path: modules/debug/mipi-sys-t