From fe83613ad569009d5c58181bb5862333bc20ccca Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 11:54:40 +0200 Subject: [PATCH 01/10] dts: bindings: flash controller size of the stm32 xspi nor This PR adds the size in Bits of the flash nor memory for the st,stm32-xspi-nor compatible Signed-off-by: Francois Ramu --- dts/bindings/flash_controller/st,stm32-xspi-nor.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dts/bindings/flash_controller/st,stm32-xspi-nor.yaml b/dts/bindings/flash_controller/st,stm32-xspi-nor.yaml index 7aee7040f6b08..03d4bc25622e7 100644 --- a/dts/bindings/flash_controller/st,stm32-xspi-nor.yaml +++ b/dts/bindings/flash_controller/st,stm32-xspi-nor.yaml @@ -23,6 +23,9 @@ include: - spi-bus-width - data-rate properties: + size: + required: true + description: Flash Memory size in bits spi-bus-width: type: int required: true From ed9abd7ecdf7b0c5465d375b56c5c712dc1363b9 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Thu, 24 Apr 2025 15:53:15 +0200 Subject: [PATCH 02/10] dts: bindings: memory controller size of the stm32 xspi psram This PR adds the size in Bits of the PSRAM memory for the st,stm32-xspi-psram compatible Signed-off-by: Francois Ramu --- dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml b/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml index a4514e536bc58..f9f8963715299 100644 --- a/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml +++ b/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml @@ -12,6 +12,11 @@ properties: reg: required: true + size: + type: int + required: true + description: Flash Memory size in bits + fixed-latency: type: boolean description: | From f86fabe57bd4d4dc6b93bf159b5ac2022cf7a7ca Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 11:59:08 +0200 Subject: [PATCH 03/10] dts: arm: stm32N6 reg definition for the st,stm32-xspi compatible The st,stm32-xspi compatible is defining the reg property with the register address and size at first index followed by the external memory base address and max allocated size. For the stm32N6 serie, xspi1 is addressing max 256 MBytes from 0x90000000 xspi2 is addressing max 256 MBytes from 0x70000000 Signed-off-by: Francois Ramu --- dts/arm/st/n6/stm32n6.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/dts/arm/st/n6/stm32n6.dtsi b/dts/arm/st/n6/stm32n6.dtsi index 698acda6c2d82..e779082794c92 100644 --- a/dts/arm/st/n6/stm32n6.dtsi +++ b/dts/arm/st/n6/stm32n6.dtsi @@ -687,27 +687,27 @@ xspi1: xspi@58025000 { compatible = "st,stm32-xspi"; - reg = <0x58025000 0x1000>; + reg = <0x58025000 0x1000>, <0x90000000 DT_SIZE_M(256)>; interrupts = <170 0>; clock-names = "xspix", "xspi-ker", "xspi-mgr"; clocks = <&rcc STM32_CLOCK(AHB5, 5)>, <&rcc STM32_SRC_HCLK5 XSPI1_SEL(0)>, <&rcc STM32_CLOCK(AHB5, 13)>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; status = "disabled"; }; xspi2: spi@5802a000 { compatible = "st,stm32-xspi"; - reg = <0x5802A000 0x1000>; + reg = <0x5802A000 0x1000>, <0x70000000 DT_SIZE_M(256)>; interrupts = <171 0>; clock-names = "xspix", "xspi-ker", "xspi-mgr"; clocks = <&rcc STM32_CLOCK(AHB5, 12)>, <&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>, <&rcc STM32_CLOCK(AHB5, 13)>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; status = "disabled"; }; From 20b6f8bb15be15c53e2b70857db1594c3e5231d1 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 12:00:10 +0200 Subject: [PATCH 04/10] dts: arm: stm32H5 reg definition for the st,stm32-xspi compatible The st,stm32-xspi compatible is defining the reg property with the register address and size at first index followed by the external memory base address and max allocated xspi1 is addressing max 256 MBytes from 0x90000000 Signed-off-by: Francois Ramu --- dts/arm/st/h5/stm32h562.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index a8fe1bce5e223..b7be9daa77538 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -260,13 +260,13 @@ xspi1: spi@47001400 { compatible = "st,stm32-xspi"; - reg = <0x47001400 0x400>; + reg = <0x47001400 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <78 0>; clock-names = "xspix", "xspi-ker"; clocks = <&rcc STM32_CLOCK(AHB4, 20U)>, <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; status = "disabled"; }; From bbf47d75cdf6ec8de644529fe89c35acbbcf7637 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 12:04:15 +0200 Subject: [PATCH 05/10] drivers: flash: stm32 xspi driver size and address of the external NOR New property of the st,stm32-xspi-nor compatible gives the external NOR flash in bits. The property of the st,stm32-xspi compatible gives the external NOR flash base address Signed-off-by: Francois Ramu --- drivers/flash/flash_stm32_xspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 29b352dee6b48..fa3ae20602ba5 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -37,8 +37,8 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL); (_CONCAT(HAL_XSPIM_, DT_STRING_TOKEN(STM32_XSPI_NODE, prop))), \ ((default_value))) -/* Get the base address of the flash from the DTS node */ -#define STM32_XSPI_BASE_ADDRESS DT_INST_REG_ADDR(0) +/* Get the base address of the flash from the DTS st,stm32-xspi node */ +#define STM32_XSPI_BASE_ADDRESS DT_REG_ADDR_BY_IDX(STM32_XSPI_NODE, 1) #define STM32_XSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios) @@ -2413,7 +2413,7 @@ static const struct flash_stm32_xspi_config flash_stm32_xspi_cfg = { .pclken = pclken, .pclk_len = DT_NUM_CLOCKS(STM32_XSPI_NODE), .irq_config = flash_stm32_xspi_irq_config_func, - .flash_size = DT_INST_REG_SIZE(0), + .flash_size = DT_INST_PROP(0, size) / 8, /* In Bytes */ .max_frequency = DT_INST_PROP(0, ospi_max_frequency), .data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */ .data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */ From 7a096bfc163860d8d6d3ae1ea778d50365ba678b Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Thu, 24 Apr 2025 15:41:31 +0200 Subject: [PATCH 06/10] drivers: memc: stm32 xspi driver size and address of the external PSRAM New property of the st,stm32-xspi-psram compatible gives the external PSRAM memory in bits. The property of the st,stm32-xspi compatible gives the external PSRAM memory base address Signed-off-by: Francois Ramu --- drivers/memc/memc_stm32_xspi_psram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memc/memc_stm32_xspi_psram.c b/drivers/memc/memc_stm32_xspi_psram.c index 676ec8c7f27fc..7e21c4e3c7645 100644 --- a/drivers/memc/memc_stm32_xspi_psram.c +++ b/drivers/memc/memc_stm32_xspi_psram.c @@ -338,7 +338,7 @@ static const struct memc_stm32_xspi_psram_config memc_stm32_xspi_cfg = { .pclken_mgr = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bus), .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bits)}, #endif - .memory_size = DT_INST_REG_ADDR_BY_IDX(0, 1), + .memory_size = DT_INST_PROP(0, size) / 8, /* In Bytes */ }; static struct memc_stm32_xspi_psram_data memc_stm32_xspi_data = { From 0faa0f94e37fc7a699789aa0d7d7bd5abd339d30 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 12:07:15 +0200 Subject: [PATCH 07/10] boards: st: stm32N6 boards xspi-nor-flash DTS configuration This PR defines the "st,stm32-xspi-nor" compatible Node and the "st,stm32-xspi-psram" compatible Node in conformance to the DTS specifications Includes the size property (in Bits) of the external memory device Signed-off-by: Francois Ramu --- boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi | 5 +++-- boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi | 10 ++++++---- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi index b249d2ab84772..4232538817fdb 100644 --- a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi +++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi @@ -235,9 +235,10 @@ zephyr_udc0: &usbotg_hs1 { <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; - mx25um51245g: ospi-nor-flash@70000000 { + mx25um51245g: ospi-nor-flash@0 { compatible = "st,stm32-xspi-nor"; - reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */ + reg = <0>; + size = ; /* 512 Mbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi index 9acf019f84f6b..9b275c460b8c5 100644 --- a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi +++ b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi @@ -250,9 +250,10 @@ zephyr_udc0: &usbotg_hs1 { <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; - memc: aps256xxn_obr: memory@90000000 { + memc: aps256xxn_obr: memory@0 { compatible = "st,stm32-xspi-psram"; - reg = <0x90000000 DT_SIZE_M(32)>; /* 256 Mbits */ + reg = <0>; + size = ; /* 256 Mbits */ fixed-latency; io-x16-mode; read-latency = <4>; @@ -273,9 +274,10 @@ zephyr_udc0: &usbotg_hs1 { <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; - mx66uw1g45g: ospi-nor-flash@70000000 { + mx66uw1g45g: ospi-nor-flash@0 { compatible = "st,stm32-xspi-nor"; - reg = <0x70000000 DT_SIZE_M(128)>; /* 1 Gbits */ + reg = <0>; + size = ; /* 1Gbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; From 5588e7abf3956575b0fc8c0aa8997d2c48627c45 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 12:07:56 +0200 Subject: [PATCH 08/10] boards: st: stm32H573 disco kit xspi-nor-flash DTS configuration This PR defines the "st,stm32-xspi-nor" compatible Node in conformance to the DTS specifications Includes the size property (in Bits) of the external NOR device Signed-off-by: Francois Ramu --- boards/st/stm32h573i_dk/stm32h573i_dk.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index 057423631743c..8776bcef00a77 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -273,9 +273,10 @@ status = "okay"; - mx25lm51245: ospi-nor-flash@90000000 { + mx25lm51245: ospi-nor-flash@0 { compatible = "st,stm32-xspi-nor"; - reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */ + reg = <0>; + size = ; /* 512 Mbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; From 3e358a97a9e6f6d4b8f8d15531778261afc96b2d Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 15 Apr 2025 12:10:32 +0200 Subject: [PATCH 09/10] samples: code_relocation_nocopy: update macro for flash size and address In case of the st,stm32-xspi-nor compatible new property and node definitions will requires new macro to get the external NOR flash base address and size Signed-off-by: Francois Ramu --- .../code_relocation_nocopy/linker_arm_nocopy.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld b/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld index 699a044373b4c..1abfbc87bb6c0 100644 --- a/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld +++ b/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld @@ -44,8 +44,8 @@ /* On stm32 XSPI, external flash is mapped in XIP region at address given by the reg property. */ #define EXTFLASH_NODE DT_INST(0, st_stm32_xspi_nor) -#define EXTFLASH_ADDR DT_REG_ADDR(DT_INST(0, st_stm32_xspi_nor)) -#define EXTFLASH_SIZE DT_REG_SIZE(DT_INST(0, st_stm32_xspi_nor)) +#define EXTFLASH_ADDR DT_REG_ADDR_BY_IDX(DT_PARENT(EXTFLASH_NODE), 1) +#define EXTFLASH_SIZE DT_PROP(EXTFLASH_NODE, size) / 8 #elif defined(CONFIG_FLASH_MSPI_NOR) && defined(CONFIG_SOC_NRF54H20_CPUAPP) From b331ada33570a50b261b4a2c4fe2b11d9a1c5c56 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Wed, 16 Apr 2025 09:35:57 +0200 Subject: [PATCH 10/10] doc: release-notes-4-2: new DTS properties for the xSPI of STM32 devices Change to apply on the DTS of STM32 soc and boards with xSPI nodes Signed-off-by: Francois Ramu --- doc/releases/migration-guide-4.2.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/doc/releases/migration-guide-4.2.rst b/doc/releases/migration-guide-4.2.rst index 7468848941346..9f907c1452e33 100644 --- a/doc/releases/migration-guide-4.2.rst +++ b/doc/releases/migration-guide-4.2.rst @@ -360,6 +360,19 @@ SPI * Renamed the device tree property ``port_sel`` to ``port-sel``. * Renamed the device tree property ``chip_select`` to ``chip-select``. +xSPI +==== + +* On STM32 devices, external memories device tree descriptions for size and address are now split + in two separate properties to comply with specification recommendations. + + For instance, following external flash description ``reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits /`` + is changed to ``reg = <0>;`` ``size = ; / 512 Mbits */``. + + Note that the property gives the actual size of the memory device in bits. + Previous mapping address information is now described in xspi node at SoC dtsi level. + + Other subsystems ****************