diff --git a/drivers/i2s/Kconfig.stm32 b/drivers/i2s/Kconfig.stm32 index e6b35e8561bd2..697aee3b08462 100644 --- a/drivers/i2s/Kconfig.stm32 +++ b/drivers/i2s/Kconfig.stm32 @@ -36,7 +36,7 @@ menuconfig I2S_STM32_SAI select USE_STM32_HAL_DMA_EX select USE_STM32_HAL_SAI help - Enable SAI support on the STM32U5 family of processors. + Enable SAI support on the STM32 family of processors. if I2S_STM32_SAI diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index 3fcd51acff019..f577fa0f2ddd6 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -633,6 +633,28 @@ status = "disabled"; }; + sai1_a: sai1@40015404 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015404 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>, + <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; + dmas = <&gpdma1 1 53 0>; + status = "disabled"; + }; + + sai1_b: sai1@40015424 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015424 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>, + <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; + dmas = <&gpdma1 0 54 0>; + status = "disabled"; + }; + usb: usb@40016000 { compatible = "st,stm32-usb"; reg = <0x40016000 0x400>; diff --git a/samples/drivers/i2s/output/boards/nucleo_h563zi.conf b/samples/drivers/i2s/output/boards/nucleo_h563zi.conf new file mode 100644 index 0000000000000..4f3f73a1e06a5 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_h563zi.conf @@ -0,0 +1 @@ +CONFIG_HEAP_MEM_POOL_SIZE=4192 diff --git a/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay b/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay new file mode 100644 index 0000000000000..561db541c6ee2 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2025 ZAL Zentrum für Angewandte Luftfahrtforschung GmbH + * Copyright (c) 2025 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2s-tx = &sai1_a; + }; +}; + +&pll2 { + /* 44.1KHz (0.09% Error) */ + div-m = <2>; + mul-n = <113>; + div-q = <2>; + div-r = <2>; + div-p = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&sai1_a { + pinctrl-0 = <&sai1_mclk_a_pe2 &sai1_sd_a_pe6 + &sai1_fs_a_pe4 &sai1_sck_a_pe5>; + pinctrl-names = "default"; + status = "okay"; + mclk-enable; + mclk-divider = "div-256"; + dma-names = "tx"; +};