From ea87a1434699db941b19b6a1d1d9fb7a26dc1d0a Mon Sep 17 00:00:00 2001 From: Mario Paja Date: Thu, 17 Jul 2025 15:12:31 +0200 Subject: [PATCH 1/3] dts: st: h7rs: add gpdma1 node This PR adds gpdma node on stm32h7rs series Signed-off-by: Mario Paja --- dts/arm/st/h7rs/stm32h7rs.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index c1dd2a3540303..6452cc84300d1 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Mario Paja * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +17,7 @@ #include #include #include +#include #include /* @@ -814,6 +816,19 @@ <&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>; status = "disabled"; }; + + gpdma1: dma@40021000 { + compatible = "st,stm32u5-dma"; + #dma-cells = <3>; + reg = <0x40021000 0x1000>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; + interrupts = <39 0 40 0 41 0 42 0 43 0 44 0 45 0 46 0 + 133 0 134 0 135 0 136 0 137 0 138 0 139 0 140 0>; + dma-channels = <16>; + dma-requests = <109>; + dma-offset = <0>; + status = "disabled"; + }; }; otgfs_phy: otgfs_phy { From 6fa07830b2269ba679446bcdacfff7d3e0ad5f8c Mon Sep 17 00:00:00 2001 From: Mario Paja Date: Thu, 17 Jul 2025 15:22:07 +0200 Subject: [PATCH 2/3] dts: st: h7rs: add sai node for stm32h7rs Define SAI1 A & B nodes for STM32H7RS series Signed-off-by: Mario Paja --- dts/arm/st/h7rs/stm32h7rs.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index 6452cc84300d1..4427c32e769ba 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -829,6 +829,30 @@ dma-offset = <0>; status = "disabled"; }; + + sai1_a: sai1@42005804 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x42005804 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 22)>, + <&rcc STM32_SRC_PLL3_P SAI1_SEL(2)>; + dmas = <&gpdma1 1 63 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | + STM32_DMA_16BITS)>; + status = "disabled"; + }; + + sai1_b: sai1@42005824 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x42005824 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 22)>, + <&rcc STM32_SRC_PLL3_P SAI1_SEL(2)>; + dmas = <&gpdma1 0 64 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | + STM32_DMA_16BITS)>; + status = "disabled"; + }; }; otgfs_phy: otgfs_phy { From ce57f6b2a3ebb30241feecb74104593680c3047a Mon Sep 17 00:00:00 2001 From: Mario Paja Date: Thu, 17 Jul 2025 16:49:49 +0200 Subject: [PATCH 3/3] samples: i2s: output: add nucleo_h7s3l8 Add Nucleo H7S3L8 board in samples/drivers/i2s/output Signed-off-by: Mario Paja --- .../i2s/output/boards/nucleo_h7s3l8.conf | 1 + .../i2s/output/boards/nucleo_h7s3l8.overlay | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 samples/drivers/i2s/output/boards/nucleo_h7s3l8.conf create mode 100644 samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay diff --git a/samples/drivers/i2s/output/boards/nucleo_h7s3l8.conf b/samples/drivers/i2s/output/boards/nucleo_h7s3l8.conf new file mode 100644 index 0000000000000..4f3f73a1e06a5 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_h7s3l8.conf @@ -0,0 +1 @@ +CONFIG_HEAP_MEM_POOL_SIZE=4192 diff --git a/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay b/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay new file mode 100644 index 0000000000000..02547dcf5c8b2 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2s-tx = &sai1_a; + }; +}; + +/* PLL3 for clocking SAI1 peripheral */ +&pll3 { + /* 44.1KHz (-0.1% Error) */ + div-m = <12>; + mul-n = <203>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <2>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&sai1_a { + pinctrl-0 = <&sai1_mclk_a_pg7 &sai1_sd_a_pc1 + &sai1_fs_a_pe4 &sai1_sck_a_pe5>; + pinctrl-names = "default"; + status = "okay"; + mclk-enable; + mclk-divider = "div-256"; + dma-names = "tx"; +}; + +&gpdma1 { + status = "okay"; +};