From 05ba34f243e056c6067e1a53fe442582d119bd34 Mon Sep 17 00:00:00 2001 From: Tomas Galbicka Date: Fri, 1 Aug 2025 13:35:30 +0200 Subject: [PATCH 1/4] dts: NXP RT700 refactor common DTS entries This commit moves common DTS entries into common file dts/arm/nxp/nxp_rt7xx_common.dtsi. This way there is not duplication between cpu0 and cpu1. Signed-off-by: Tomas Galbicka --- dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi | 208 ++++-------------------- dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi | 183 ++++----------------- dts/arm/nxp/nxp_rt7xx_common.dtsi | 211 +++++++++++++++++++++++++ dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi | 3 +- 4 files changed, 275 insertions(+), 330 deletions(-) create mode 100644 dts/arm/nxp/nxp_rt7xx_common.dtsi diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi index f9b3c2200eeff..8c7781f3adc61 100644 --- a/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi +++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi @@ -4,15 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include -#include -#include -#include -#include +#include "nxp_rt7xx_common.dtsi" #include -#include -#include #include / { @@ -62,15 +55,6 @@ }; soc { - sram: memory@10000000 { - ranges = <0x0 0x10000000 0x780000 - 0x20000000 0x30000000 0x780000>; - }; - - peripheral: peripheral@50000000 { - ranges = <0x0 0x50000000 0x10000000>; - }; - xspi0: memory-controller@50184000 { reg = <0x50184000 0x1000>, <0x38000000 DT_SIZE_M(128)>; }; @@ -78,14 +62,6 @@ xspi1: memory-controller@50185000 { reg = <0x50185000 0x1000>, <0x18000000 DT_SIZE_M(128)>; }; - - xspi2: memory-controller@50411000 { - reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; - }; - }; - - pinctrl: pinctrl { - compatible = "nxp,rt-iocon-pinctrl"; }; /* USB PLL */ @@ -96,45 +72,6 @@ }; }; -&sram { - #address-cells = <1>; - #size-cells = <1>; - - /* RT7XX SRAM partitions are shared between code and data. Boards can override - * the reg properties of either sram0 or sram_code nodes to change the balance - * of SRAM allocation. - * - * The SRAM region [0x000000-0x017FFF] is reserved for ROM bootloader execution. - * Can be reused after boot. - * The SRAM region [0x018000-0x17FFFF] is reserved for Non-cached shared memory - * or application data. - * The SRAM region [0x180000-0x1FFFFF] is reserved for CPU0 application, last - * 2MB non-cacheable data for NPU/GPU/Display etc. - * The SRAM region [0x200000-0x400000] is reserved for HiFi4 application. - */ - - sram4rom: memory@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 DT_SIZE_K(96)>; - }; - - /* This partition is shared with code in RAM */ - sram_shared_code: memory@20018000 { - compatible = "mmio-sram"; - reg = <0x20018000 DT_SIZE_K(1024+512-96)>; - }; - - sram0: memory@20180000 { - compatible = "mmio-sram"; - reg = <0x20180000 DT_SIZE_K(512)>; - }; - - sram1: memory@20200000 { - compatible = "mmio-sram"; - reg = <0x20200000 DT_SIZE_K(2048)>; - }; -}; - &peripheral { #address-cells = <1>; #size-cells = <1>; @@ -145,53 +82,12 @@ * and secure modes (0x50000000). */ - lpadc0: adc@20c000 { - compatible = "nxp,lpc-lpadc"; - reg = <0x20c000 0x304>; - interrupts = <15 0>; - status = "disabled"; - clk-divider = <1>; - clk-source = <0>; - voltage-ref = <1>; - calibration-average = <128>; - power-level = <0>; - offset-value-a = <10>; - offset-value-b = <10>; - #io-channel-cells = <1>; - clocks = <&clkctl3 MCUX_LPADC1_CLK>; - }; - rstctl0: reset-controller@0 { compatible = "nxp,rstctl"; reg = <0x0 0x1000>; #reset-cells = <1>; }; - rstctl2: reset-controller@67000 { - compatible = "nxp,rstctl"; - reg = <0x67000 0x1000>; - #reset-cells = <1>; - }; - - rstctl3: reset-controller@60000 { - compatible = "nxp,rstctl"; - reg = <0x60000 0x1000>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - - sysrststat: hwinfo@60000 { - compatible = "nxp,rstctl-hwinfo"; - reg = <0x60000 0x4>; - }; - }; - - rstctl4: reset-controller@a0000 { - compatible = "nxp,rstctl"; - reg = <0xa0000 0x1000>; - #reset-cells = <1>; - }; - rtc0: rtc@68000 { compatible = "nxp,irtc"; reg = <0x68000 0x1000>; @@ -208,24 +104,6 @@ #clock-cells = <1>; }; - clkctl2: clock-controller@65000 { - compatible = "nxp,lpc-syscon"; - reg = <0x65000 0x1000>; - #clock-cells = <1>; - }; - - clkctl3: clock-controller@61000 { - compatible = "nxp,lpc-syscon"; - reg = <0x61000 0x1000>; - #clock-cells = <1>; - }; - - clkctl4: clock-controller@a1000 { - compatible = "nxp,lpc-syscon"; - reg = <0xa1000 0x1000>; - #clock-cells = <1>; - }; - ctimer0: timer@28000 { compatible = "nxp,lpc-ctimer"; reg = <0x28000 0x1000>; @@ -323,42 +201,12 @@ #pinmux-cells = <2>; }; - syscon2: syscon@66000 { - compatible = "nxp,lpc-syscon"; - reg = <0x66000 0x1000>; - #clock-cells = <1>; - }; - - syscon3: syscon@62000 { - compatible = "nxp,lpc-syscon"; - reg = <0x62000 0x1000>; - #clock-cells = <1>; - }; - - syscon4: syscon@a2000 { - compatible = "nxp,lpc-syscon"; - reg = <0xa2000 0x1000>; - #clock-cells = <1>; - }; - iocon: pinctrl@4000 { compatible = "nxp,lpc-iocon"; reg = <0x4000 0x1000>; status = "okay"; }; - iocon1: pinctrl@64000 { - compatible = "nxp,lpc-iocon"; - reg = <0x64000 0x1000>; - status = "okay"; - }; - - iocon2: pinctrl@a5000 { - compatible = "nxp,lpc-iocon"; - reg = <0xa5000 0x1000>; - status = "okay"; - }; - gpio0: gpio@100000 { compatible = "nxp,kinetis-gpio"; status = "disabled"; @@ -985,6 +833,36 @@ }; }; + /* MU0: MUA, CPU0 to HiFi1 */ + mbox0_a: mbox@200000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x200000 0x1000>; + interrupts = <29 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "disabled"; + }; + + /* MU1: MUA, CPU0 to CPU1 */ + mbox1_a: mbox@202000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x202000 0x1000>; + interrupts = <30 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "disabled"; + }; + + /* MU4: MUA, CPU0 to HiFi4 */ + mbox4_a: mbox@189000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x189000 0x1000>; + interrupts = <31 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "disabled"; + }; + /* LPFlexcomm14/16 only support LPSPI function */ lpspi14: spi@484000 { compatible = "nxp,lpspi"; @@ -1227,26 +1105,6 @@ interrupts = <17 0>; status = "disabled"; }; - - mbox4: mailbox@189000 { - #mbox-cells = <1>; - - compatible = "nxp,mbox-imx-mu"; - reg = <0x189000 0x1000>; - - interrupts = <31 0>; - rx-channels = <4>; - - status = "disabled"; - }; -}; - -&systick { - /* - * RT700 cm33_cpu0 relies by default on the OS Timer for system - * clock implementation, so the SysTick node is not to be enabled. - */ - status = "disabled"; }; &xspi0 { @@ -1257,7 +1115,3 @@ #size-cells = <0>; clocks = <&clkctl0 MCUX_XSPI_CLK>; }; - -&nvic { - arm,num-irq-priority-bits = <3>; -}; diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi index 448aa590e57ce..6d7a8aef3115e 100644 --- a/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi +++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi @@ -4,14 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include -#include -#include -#include -#include -#include -#include +#include "nxp_rt7xx_common.dtsi" / { cpus { @@ -30,56 +23,6 @@ }; }; }; - - soc { - sram: memory@10000000 { - ranges = <0x0 0x10000000 0x780000 - 0x20000000 0x30000000 0x780000>; - }; - - peripheral: peripheral@50000000 { - ranges = <0x0 0x50000000 0x10000000>; - }; - - xspi2: memory@50411000 { - reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; - }; - }; - - pinctrl: pinctrl { - compatible = "nxp,rt-iocon-pinctrl"; - }; -}; - -&sram { - #address-cells = <1>; - #size-cells = <1>; - - /* RT7XX SRAM partitions are shared between code and data. Boards can - * override the reg properties of either sram0 or sram_code nodes to - * change the balance of SRAM allocation. - * - * The SRAM region [0x580000-0x5BFFFF] is reserved for shared memory or application data. - * The SRAM region [0x5C0000-0x67FFFF] is reserved for CPU1 application. - * The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application. - */ - - sram_code: memory@600000 { - compatible = "mmio-sram"; - reg = <0x600000 DT_SIZE_K(512)>; - }; - - /* This partition is shared with code in RAM */ - sram_shared_code: memory@20058000 { - compatible = "mmio-sram"; - reg = <0x20058000 DT_SIZE_K(256)>; - }; - - sram0: memory@205C0000 { - compatible = "mmio-sram"; - /* Only use 256K, align with SDK */ - reg = <0x205C0000 DT_SIZE_K(256)>; - }; }; &peripheral { @@ -92,46 +35,12 @@ * and secure modes (0x50000000). */ - lpadc0: adc@20c000 { - compatible = "nxp,lpc-lpadc"; - reg = <0x20c000 0x304>; - interrupts = <15 0>; - status = "disabled"; - clk-divider = <1>; - clk-source = <0>; - voltage-ref = <1>; - calibration-average = <128>; - power-level = <0>; - offset-value-a = <10>; - offset-value-b = <10>; - #io-channel-cells = <1>; - clocks = <&clkctl3 MCUX_LPADC1_CLK>; - }; - rstctl1: reset-controller@40000 { compatible = "nxp,rstctl"; reg = <0x40000 0x1000>; #reset-cells = <1>; }; - rstctl2: reset-controller@67000 { - compatible = "nxp,rstctl"; - reg = <0x67000 0x1000>; - #reset-cells = <1>; - }; - - rstctl3: reset-controller@60000 { - compatible = "nxp,rstctl"; - reg = <0x60000 0x1000>; - #reset-cells = <1>; - }; - - rstctl4: reset-controller@a0000 { - compatible = "nxp,rstctl"; - reg = <0xa0000 0x1000>; - #reset-cells = <1>; - }; - rtc1: rtc@69000 { compatible = "nxp,irtc"; reg = <0x69000 0x1000>; @@ -149,24 +58,6 @@ #clock-cells = <1>; }; - clkctl2: clock-controller@65000 { - compatible = "nxp,lpc-syscon"; - reg = <0x65000 0x1000>; - #clock-cells = <1>; - }; - - clkctl3: clock-controller@61000 { - compatible = "nxp,lpc-syscon"; - reg = <0x61000 0x1000>; - #clock-cells = <1>; - }; - - clkctl4: clock-controller@a1000 { - compatible = "nxp,lpc-syscon"; - reg = <0xa1000 0x1000>; - #clock-cells = <1>; - }; - ctimer5: timer@48000 { compatible = "nxp,lpc-ctimer"; reg = <0x48000 0x1000>; @@ -209,36 +100,6 @@ #clock-cells = <1>; }; - syscon2: syscon@66000 { - compatible = "nxp,lpc-syscon"; - reg = <0x66000 0x1000>; - #clock-cells = <1>; - }; - - syscon3: syscon@62000 { - compatible = "nxp,lpc-syscon"; - reg = <0x62000 0x1000>; - #clock-cells = <1>; - }; - - syscon4: syscon@a2000 { - compatible = "nxp,lpc-syscon"; - reg = <0xa2000 0x1000>; - #clock-cells = <1>; - }; - - iocon1: pinctrl@64000 { - compatible = "nxp,lpc-iocon"; - reg = <0x64000 0x1000>; - status = "okay"; - }; - - iocon2: pinctrl@a5000 { - compatible = "nxp,lpc-iocon"; - reg = <0xa5000 0x1000>; - status = "okay"; - }; - i3c2: i3c@56000 { compatible = "nxp,mcux-i3c"; reg = <0x56000 0x1000>; @@ -454,6 +315,36 @@ }; }; + /* MU1: MUB, CPU1 to CPU0 */ + mbox1_b: mbox@203000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x203000 0x1000>; + interrupts = <26 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "disabled"; + }; + + /* MU2: MUB, CPU1 to HiFi4 */ + mbox2_b: mbox@205000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x205000 0x1000>; + interrupts = <27 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "disabled"; + }; + + /* MU3: MUA, CPU1 to HiFi1 */ + mbox3_a: mbox@319000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x319000 0x1000>; + interrupts = <28 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "disabled"; + }; + /* LPFlexcomm15 only support LPI2C function. */ lpi2c15: i2c@213000 { compatible = "nxp,lpi2c"; @@ -479,15 +370,3 @@ status = "disabled"; }; }; - -&nvic { - arm,num-irq-priority-bits = <3>; -}; - -&systick { - /* - * RT700 cm33_cpu1 relies by default on the OS Timer for system - * clock implementation, so the SysTick node is not to be enabled. - */ - status = "disabled"; -}; diff --git a/dts/arm/nxp/nxp_rt7xx_common.dtsi b/dts/arm/nxp/nxp_rt7xx_common.dtsi new file mode 100644 index 0000000000000..ce1537050a369 --- /dev/null +++ b/dts/arm/nxp/nxp_rt7xx_common.dtsi @@ -0,0 +1,211 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + soc { + sram: memory@10000000 { + ranges = <0x0 0x10000000 0x780000 + 0x20000000 0x30000000 0x780000>; + }; + + peripheral: peripheral@50000000 { + ranges = <0x0 0x50000000 0x10000000>; + }; + + xspi2: memory-controller@50411000 { + reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; + }; + }; + + pinctrl: pinctrl { + compatible = "nxp,rt-iocon-pinctrl"; + }; +}; + +&sram { + #address-cells = <1>; + #size-cells = <1>; + + /* RT7XX SRAM partitions are shared between code and data. Boards can + * override the reg properties of either sram0 or sram_code nodes to + * change the balance of SRAM allocation. + * + * The SRAM region [0x000000-0x017FFF] is reserved for ROM bootloader execution. + * Can be reused after boot. + * The SRAM region [0x018000-0x17FFFF] is reserved for Non-cached shared memory + * or application data. + * The SRAM region [0x180000-0x1FFFFF] is reserved for CPU0 application, last + * 2MB non-cacheable data for NPU/GPU/Display etc. + * The SRAM region [0x200000-0x400000] is reserved for HiFi4 application. + * + * The SRAM region [0x580000-0x5BFFFF] is reserved for shared memory or application data. + * The SRAM region [0x5C0000-0x67FFFF] is reserved for CPU1 application. + * The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application. + */ + + sram4rom: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(96)>; + }; + + /* This partition is shared with code in RAM */ + sram_shared_code0: memory@20018000 { + compatible = "mmio-sram"; + reg = <0x20018000 DT_SIZE_K(1024+512-96)>; + }; + + sram_code: memory@600000 { + compatible = "mmio-sram"; + reg = <0x600000 DT_SIZE_K(512)>; + }; + + /* This partition is shared with code in RAM */ + sram_shared_code1: memory@20058000 { + compatible = "mmio-sram"; + reg = <0x20058000 DT_SIZE_K(256)>; + }; + + sram0: memory@20180000 { + compatible = "mmio-sram"; + reg = <0x20180000 DT_SIZE_K(512)>; + }; + + sram1: memory@20200000 { + compatible = "mmio-sram"; + reg = <0x20200000 DT_SIZE_K(2048)>; + }; + + sram3: memory@205C0000 { + compatible = "mmio-sram"; + /* Only use 256K, align with SDK */ + reg = <0x205C0000 DT_SIZE_K(256)>; + }; + + sram4: memory@20600000 { + compatible = "mmio-sram"; + reg = <0x20600000 DT_SIZE_K(256)>; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + /* + * Note that the offsets here are relative to the base address. + * The base addresses differ between non-secure (0x40000000) + * and secure modes (0x50000000). + */ + + lpadc0: adc@20c000 { + compatible = "nxp,lpc-lpadc"; + reg = <0x20c000 0x304>; + interrupts = <15 0>; + status = "disabled"; + clk-divider = <1>; + clk-source = <0>; + voltage-ref = <1>; + calibration-average = <128>; + power-level = <0>; + offset-value-a = <10>; + offset-value-b = <10>; + #io-channel-cells = <1>; + clocks = <&clkctl3 MCUX_LPADC1_CLK>; + }; + + rstctl2: reset-controller@67000 { + compatible = "nxp,rstctl"; + reg = <0x67000 0x1000>; + #reset-cells = <1>; + }; + + rstctl3: reset-controller@60000 { + compatible = "nxp,rstctl"; + reg = <0x60000 0x1000>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + + sysrststat: hwinfo@60000 { + compatible = "nxp,rstctl-hwinfo"; + reg = <0x60000 0x4>; + }; + }; + + rstctl4: reset-controller@a0000 { + compatible = "nxp,rstctl"; + reg = <0xa0000 0x1000>; + #reset-cells = <1>; + }; + + clkctl2: clock-controller@65000 { + compatible = "nxp,lpc-syscon"; + reg = <0x65000 0x1000>; + #clock-cells = <1>; + }; + + clkctl3: clock-controller@61000 { + compatible = "nxp,lpc-syscon"; + reg = <0x61000 0x1000>; + #clock-cells = <1>; + }; + + clkctl4: clock-controller@a1000 { + compatible = "nxp,lpc-syscon"; + reg = <0xa1000 0x1000>; + #clock-cells = <1>; + }; + + syscon2: syscon@66000 { + compatible = "nxp,lpc-syscon"; + reg = <0x66000 0x1000>; + #clock-cells = <1>; + }; + + syscon3: syscon@62000 { + compatible = "nxp,lpc-syscon"; + reg = <0x62000 0x1000>; + #clock-cells = <1>; + }; + + syscon4: syscon@a2000 { + compatible = "nxp,lpc-syscon"; + reg = <0xa2000 0x1000>; + #clock-cells = <1>; + }; + + iocon1: pinctrl@64000 { + compatible = "nxp,lpc-iocon"; + reg = <0x64000 0x1000>; + status = "okay"; + }; + + iocon2: pinctrl@a5000 { + compatible = "nxp,lpc-iocon"; + reg = <0xa5000 0x1000>; + status = "okay"; + }; +}; + +&systick { + /* + * RT700 cm33 cores relies by default on the OS Timer for system + * clock implementation, so the SysTick node is not to be enabled. + */ + status = "disabled"; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi b/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi index a5b8659875dd3..f519934c4c968 100644 --- a/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi +++ b/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi @@ -302,7 +302,8 @@ status = "disabled"; }; - mbox4: mbox@188000 { + /* MU4: MUB, Hifi4 to CPU0 */ + mbox4_b: mbox@188000 { #mbox-cells = <1>; reg = <0x188000 0x1000>; From f062e6b1e779555e4637b3a82ace227034936ce9 Mon Sep 17 00:00:00 2001 From: Tomas Galbicka Date: Fri, 1 Aug 2025 13:42:28 +0200 Subject: [PATCH 2/4] soc: NXP RT700 add support to boot CM33 CPU1 This commit adds multicore support to copy CM33 CPU1 image from flash to RAM where it will boot from. Also added NXP_IMXRT_BOOT_HEADER=y for CPU0 so it can be booted from FlexSPI Flash. Signed-off-by: Tomas Galbicka --- .../mcux/mcux-sdk-ng/drivers/drivers.cmake | 2 +- soc/nxp/imxrt/Kconfig | 2 +- soc/nxp/imxrt/imxrt7xx/cm33/Kconfig.defconfig | 9 +++++++ soc/nxp/imxrt/imxrt7xx/cm33/display_if.c | 9 +++---- soc/nxp/imxrt/imxrt7xx/cm33/init.c | 25 +++++++++++++++++++ 5 files changed, 40 insertions(+), 7 deletions(-) diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake index 368a250891ccb..c3337eb817f76 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake @@ -199,7 +199,7 @@ elseif(CONFIG_CPU_CORTEX_A) endif() set_variable_ifdef(CONFIG_HAS_MCUX_XCACHE CONFIG_MCUX_COMPONENT_driver.cache_xcache) -if((${MCUX_DEVICE} MATCHES "MIMX9596") OR (${MCUX_DEVICE} MATCHES "MIMX8UD7") OR (${MCUX_DEVICE} MATCHES "MIMXRT118") OR (CONFIG_SOC_MIMX94398) OR (CONFIG_SOC_MIMXRT798S)) +if((${MCUX_DEVICE} MATCHES "MIMX9596") OR (${MCUX_DEVICE} MATCHES "MIMX8UD7") OR (${MCUX_DEVICE} MATCHES "MIMXRT118") OR (${MCUX_DEVICE} MATCHES "MIMXRT798") OR (CONFIG_SOC_MIMX94398)) if(CONFIG_SOC_MIMX94398_M33) set(CONFIG_MCUX_COMPONENT_driver.irqsteer_1 ON) diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig index b6e4885d6a898..3f95930cb7c21 100644 --- a/soc/nxp/imxrt/Kconfig +++ b/soc/nxp/imxrt/Kconfig @@ -148,7 +148,7 @@ config NXP_IMX_EXTERNAL_HYPERRAM config SECOND_CORE_MCUX bool "Dual core operation on the RT11xx series" - depends on SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X + depends on SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X || SOC_SERIES_IMXRT7XX help Indicates the second core will be enabled, and the part will run in dual core mode. Enables dual core operation on the RT11xx series, diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig.defconfig b/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig.defconfig index 98a754278e8ce..e1db2840b7b46 100644 --- a/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig.defconfig +++ b/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig.defconfig @@ -23,6 +23,15 @@ endchoice config I2S_HAS_PLL_SETTING default n +if SECOND_CORE_MCUX + +# RT Boot header is only needed on primary core +config NXP_IMXRT_BOOT_HEADER + default y + depends on !BOOTLOADER_MCUBOOT + +endif + endif # SOC_MIMXRT798S_CM33_CPU0 diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/display_if.c b/soc/nxp/imxrt/imxrt7xx/cm33/display_if.c index 35d0cbce07d54..b2da91cb75605 100644 --- a/soc/nxp/imxrt/imxrt7xx/cm33/display_if.c +++ b/soc/nxp/imxrt/imxrt7xx/cm33/display_if.c @@ -40,10 +40,9 @@ void __weak imxrt_pre_init_display_interface(void) * source, the frequency is 532.48 * 18 / 30 = 319.49MHz, which meets the * requirement. */ - uint32_t mipiDsiDphyBitClkFreq_Hz = - DT_PROP(DT_NODELABEL(lcdif), clock_frequency) / - DT_PROP_OR(DT_NODELABEL(lcdif), divider, 1) / - DT_PROP(DT_NODELABEL(lcdif), wr_period) * 16U; + uint32_t mipiDsiDphyBitClkFreq_Hz = DT_PROP(DT_NODELABEL(lcdif), clock_frequency) / + DT_PROP_OR(DT_NODELABEL(lcdif), divider, 1) / + DT_PROP(DT_NODELABEL(lcdif), wr_period) * 16U; #else /* The DPHY bit clock must be fast enough to send out the pixels, it should be * larger than: @@ -54,7 +53,7 @@ void __weak imxrt_pre_init_display_interface(void) uint32_t mipiDsiDphyBitClkFreq_Hz = DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock); #endif uint8_t clockDiv = (uint8_t)((uint64_t)CLOCK_GetAudioPllFreq() * 18U / - (uint64_t)mipiDsiDphyBitClkFreq_Hz); + (uint64_t)mipiDsiDphyBitClkFreq_Hz); CLOCK_InitAudioPfd(kCLOCK_Pfd2, clockDiv); diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/init.c b/soc/nxp/imxrt/imxrt7xx/cm33/init.c index fc078b6c06d4f..f1fb8716b75b1 100644 --- a/soc/nxp/imxrt/imxrt7xx/cm33/init.c +++ b/soc/nxp/imxrt/imxrt7xx/cm33/init.c @@ -17,8 +17,33 @@ #include #include + +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) +#include +/* Memcpy macro to copy segments from secondary core image stored in flash + * to RAM section that secondary core boots from. + * n is the segment number, as defined in zephyr_image_info.h + */ +#define MEMCPY_SEGMENT(n, _) \ + memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA), \ + (uint32_t *)(SEGMENT_LMA_ADDRESS_##n), (SEGMENT_SIZE_##n)) +#endif + void soc_early_init_hook(void) { +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) + /** + * Copy CM33 CPU1 core from flash to memory. Note that depending on where the + * user decided to store CPU1 code, this is likely going to read from the + * XSPI while using XIP. Provided we DO NOT WRITE TO THE XSPI, + * this operation is safe. + * + * Note that this copy MUST occur before enabling the CPU0 caching to + * ensure the data is written directly to RAM (since the CPU1 core will use it) + */ + LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;)); +#endif + /* Enable data cache */ sys_cache_data_enable(); From b93c5e5fd35003dd5b58cf93bf0a14a6b6ed6d41 Mon Sep 17 00:00:00 2001 From: Tomas Galbicka Date: Fri, 1 Aug 2025 13:46:41 +0200 Subject: [PATCH 3/4] boards: NXP RT700 Add support for CM33 multicore This commit adds multicore support to boot secondary CM33 CPU1 core. - Adds Flash partition for CM33 CPU0 - Boots secondary core Signed-off-by: Tomas Galbicka --- boards/nxp/mimxrt700_evk/Kconfig.defconfig | 26 ++++++++++ boards/nxp/mimxrt700_evk/board.c | 52 +++++++++++++++++++ boards/nxp/mimxrt700_evk/board.cmake | 4 +- boards/nxp/mimxrt700_evk/doc/index.rst | 12 +++++ .../mimxrt700_evk_mimxrt798s_cm33_cpu0.dts | 33 +++++++++++- .../mimxrt700_evk_mimxrt798s_cm33_cpu1.dts | 6 ++- .../mimxrt700_evk_mimxrt798s_hifi4.dts | 2 +- ...mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay | 2 +- .../mimxrt700_evk_mimxrt798s_hifi4.overlay | 2 +- samples/drivers/mbox/CMakeLists.txt | 1 + samples/drivers/mbox/Kconfig.sysbuild | 1 + .../mimxrt700_evk_mimxrt798s_cm33_cpu0.conf | 2 + ...mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay | 13 +++++ samples/drivers/mbox/remote/CMakeLists.txt | 1 + .../mimxrt700_evk_mimxrt798s_cm33_cpu1.conf | 4 ++ ...mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay | 13 +++++ samples/drivers/mbox/sysbuild.cmake | 1 + samples/drivers/mbox_data/CMakeLists.txt | 1 + samples/drivers/mbox_data/Kconfig.sysbuild | 1 + .../mimxrt700_evk_mimxrt798s_cm33_cpu0.conf | 2 + ...mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay | 13 +++++ .../drivers/mbox_data/remote/CMakeLists.txt | 1 + .../mimxrt700_evk_mimxrt798s_cm33_cpu1.conf | 3 ++ ...mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay | 13 +++++ samples/drivers/mbox_data/sysbuild.cmake | 1 + .../ipc_service/static_vrings/CMakeLists.txt | 1 + .../static_vrings/Kconfig.sysbuild | 1 + .../mimxrt700_evk_mimxrt798s_cm33_cpu0.conf | 9 ++++ ...mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay | 49 +++++++++++++++++ .../mimxrt700_evk_mimxrt798s_cm33_cpu1.conf | 8 +++ ...mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay | 49 +++++++++++++++++ samples/subsys/ipc/openamp/Kconfig.sysbuild | 2 + .../mimxrt700_evk_mimxrt798s_cm33_cpu0.conf | 8 +++ ...mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay | 20 +++++++ .../mimxrt700_evk_mimxrt798s_cm33_cpu1.conf | 9 ++++ ...mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay | 20 +++++++ 36 files changed, 379 insertions(+), 7 deletions(-) create mode 100644 boards/nxp/mimxrt700_evk/Kconfig.defconfig create mode 100644 samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf create mode 100644 samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay create mode 100644 samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf create mode 100644 samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay create mode 100644 samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf create mode 100644 samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay create mode 100644 samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf create mode 100644 samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay create mode 100644 samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf create mode 100644 samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay create mode 100644 samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf create mode 100644 samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay diff --git a/boards/nxp/mimxrt700_evk/Kconfig.defconfig b/boards/nxp/mimxrt700_evk/Kconfig.defconfig new file mode 100644 index 0000000000000..81e1b74b9c41d --- /dev/null +++ b/boards/nxp/mimxrt700_evk/Kconfig.defconfig @@ -0,0 +1,26 @@ +# MIMXRT700-EVK board + +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT700_EVK + +if SECOND_CORE_MCUX && SOC_MIMXRT798S_CM33_CPU1 + +config BUILD_OUTPUT_INFO_HEADER + default y + +# RT700 CPU1 LMA offset calculation: +# CPU1 doesn't have access to flash partitions, so we use known values: +# - CPU0 will store CPU1 image at flash offset 0x720000 (slot1_partition) +# - Flash is memory-mapped at 0x28000000 (RT700 XSPI0 base) +# - CPU1 executes from 0x600000 (CPU1 alias space) +# +# LMA = flash_base + partition_offset = 0x28000000 + 0x720000 = 0x28720000 +# Adjustment = LMA - VMA = 0x28720000 - 0x600000 = 0x28120000 +config BUILD_OUTPUT_ADJUST_LMA + default "0x28720000 - 0x00600000" + +endif + +endif diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c index f3cafb10383b8..a4b75c20d55de 100644 --- a/boards/nxp/mimxrt700_evk/board.c +++ b/boards/nxp/mimxrt700_evk/board.c @@ -147,6 +147,9 @@ void board_early_init_hook(void) CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable); CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable); + /* Enable clock for Hifi4 access RAM arbiter1 (for SRAM start from 0x2058000000) */ + CLOCK_EnableClock(kCLOCK_Hifi4AccessRamArbiter1); + #if CONFIG_FLASH_MCUX_XSPI_XIP /* Call function xspi_setup_clock() to set user configured clock for XSPI. */ xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */ @@ -172,10 +175,17 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE); CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1); CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN); + + CLOCK_EnableClock(kCLOCK_SenseAccessRamArbiter0); #endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */ BOARD_InitAHBSC(); +#if defined(CONFIG_SECOND_CORE_MCUX) + POWER_DisablePD(kPDRUNCFG_SHUT_SENSEP_MAINCLK); + POWER_ApplyPD(); +#endif + #if DT_NODE_HAS_STATUS(DT_NODELABEL(edma0), okay) CLOCK_EnableClock(kCLOCK_Dma0); RESET_ClearPeripheralReset(kDMA0_RST_SHIFT_RSTn); @@ -615,3 +625,45 @@ static void edma_enable_all_request(uint8_t instance) } } #endif + +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) +/** + * @brief Kickoff secondary core (CPU1). + * + * Kick the secondary core out of reset and wait for it to indicate boot. The + * core image was already copied to RAM in soc_early_init_hook() + * + * @return 0 + */ +static int second_core_boot(void) +{ + /* Get the boot address for the second core */ + uint32_t boot_address = (uint32_t)(DT_REG_ADDR(DT_NODELABEL(sram_code))); + + PMC0->PDRUNCFG2 &= ~0x3FFC0000; + PMC0->PDRUNCFG3 &= ~0x3FFC0000; + + /* RT700 specific CPU1 boot sequence */ + /* Glikey write enable, GLIKEY4 */ + GlikeyWriteEnable(GLIKEY4, 1U); + + /* Boot source for Core 1 from RAM. */ + SYSCON3->CPU1_NSVTOR = ((uint32_t)(void *)boot_address >> 7U); + SYSCON3->CPU1_SVTOR = ((uint32_t)(void *)boot_address >> 7U); + + GlikeyClearConfig(GLIKEY4); + + /* Enable cpu1 clock. */ + CLOCK_EnableClock(kCLOCK_Cpu1); + + /* Clear reset*/ + RESET_ClearPeripheralReset(kCPU1_RST_SHIFT_RSTn); + + /* Release cpu wait*/ + SYSCON3->CPU_STATUS &= ~SYSCON3_CPU_STATUS_CPU_WAIT_MASK; + + return 0; +} + +SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/boards/nxp/mimxrt700_evk/board.cmake b/boards/nxp/mimxrt700_evk/board.cmake index 77a08ce25091c..6ac1b08d33787 100644 --- a/boards/nxp/mimxrt700_evk/board.cmake +++ b/boards/nxp/mimxrt700_evk/board.cmake @@ -1,10 +1,10 @@ # -# Copyright 2024, 2025 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # -if(CONFIG_SOC_MIMXRT798S_CM33_CPU0) +if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SECOND_CORE_MCUX) board_runner_args(jlink "--device=MIMXRT798S_M33_0" "--reset-after-load") board_runner_args(linkserver "--device=MIMXRT798S:MIMXRT700-EVK") board_runner_args(linkserver "--override=/device/memory/4=") diff --git a/boards/nxp/mimxrt700_evk/doc/index.rst b/boards/nxp/mimxrt700_evk/doc/index.rst index 3d2ddb0d978ea..860b3d669c65b 100644 --- a/boards/nxp/mimxrt700_evk/doc/index.rst +++ b/boards/nxp/mimxrt700_evk/doc/index.rst @@ -128,6 +128,18 @@ To build the hello_world sample for the i.MX RT700 HiFi 4 DSP core: :board: mimxrt700_evk/mimxrt798s/hifi4 :goals: build +Multicore Core Operation +************************ + +The MIMXRT700-EVK supports multicore core operation with all cores, the Cortex-M33 CPU0, Cortex-M33 CPU1, +HiFi1 DSP and HiFi4 DSP. +By default, the CM33 CPU0 core is the boot core and is responsible for initializing the system and +starting the CM33 CPU1 core and/or HiFi4 DSP. +The CM33 CPU1 is responsible to boot the HiFi1 DSP. + +Usually boot process is that core responsible for booting the secondary core(s) will copy its firmware/image +to the designated memory location and then release the secondary core from reset. + Programming and Debugging ************************* diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts index 72d3e3444ea77..d35762b53e52f 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts @@ -336,6 +336,33 @@ zephyr_lcdif: &lcdif {}; jedec-id = [c2 81 3a]; erase-block-size = ; write-block-size = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_M(7)>; + }; + slot1_partition: partition@720000 { + label = "image-1"; + reg = <0x00720000 DT_SIZE_M(7)>; + }; + storage_partition: partition@E20000 { + label = "storage"; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + }; + }; }; }; @@ -386,7 +413,11 @@ p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {}; status = "okay"; }; -&mbox4 { +&mbox1_a { + status = "okay"; +}; + +&mbox4_a { status = "okay"; }; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts index 6004ba46a9329..da52780a04fba 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts @@ -24,7 +24,7 @@ chosen { zephyr,flash = &sram_code; - zephyr,sram = &sram0; + zephyr,sram = &sram3; zephyr,console = &flexcomm19_lpuart19; zephyr,shell-uart = &flexcomm19_lpuart19; }; @@ -110,3 +110,7 @@ &rtc1 { status = "okay"; }; + +&mbox1_b { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts index 2c44fb7c76157..fbcdc2f9b6cba 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts @@ -73,6 +73,6 @@ mclk-output; }; -&mbox4 { +&mbox4_b { status = "okay"; }; diff --git a/samples/boards/nxp/adsp/rtxxx/amp_mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/samples/boards/nxp/adsp/rtxxx/amp_mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay index 2ddad4272b196..e8d58f68c0f09 100644 --- a/samples/boards/nxp/adsp/rtxxx/amp_mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay +++ b/samples/boards/nxp/adsp/rtxxx/amp_mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay @@ -6,6 +6,6 @@ / { aliases { - mbox = &mbox4; + mbox = &mbox4_a; }; }; diff --git a/samples/boards/nxp/adsp/rtxxx/amp_mbox/remote/boards/mimxrt700_evk_mimxrt798s_hifi4.overlay b/samples/boards/nxp/adsp/rtxxx/amp_mbox/remote/boards/mimxrt700_evk_mimxrt798s_hifi4.overlay index 2ddad4272b196..8db09783df1b1 100644 --- a/samples/boards/nxp/adsp/rtxxx/amp_mbox/remote/boards/mimxrt700_evk_mimxrt798s_hifi4.overlay +++ b/samples/boards/nxp/adsp/rtxxx/amp_mbox/remote/boards/mimxrt700_evk_mimxrt798s_hifi4.overlay @@ -6,6 +6,6 @@ / { aliases { - mbox = &mbox4; + mbox = &mbox4_b; }; }; diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index 069b8f1a6e0dd..8e8a3e1aecc5b 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -18,6 +18,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR + CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index 7ca010a039aa2..078c97b39eb58 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -15,6 +15,7 @@ config REMOTE_BOARD default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk" + default "mimxrt700_evk/mimxrt798s/cm33_cpu1" if $(BOARD) = "mimxrt700_evk" default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947" default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk" diff --git a/samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf new file mode 100644 index 0000000000000..60eead5a076e4 --- /dev/null +++ b/samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf @@ -0,0 +1,2 @@ +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay new file mode 100644 index 0000000000000..9836b08ebe3d3 --- /dev/null +++ b/samples/drivers/mbox/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox1_a 1>, <&mbox1_a 0>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index 0cf947cee7aeb..3f46ef6b8d1b2 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -16,6 +16,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET OR CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 OR CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 OR CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 OR + CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1 OR CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 OR CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU1 OR CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU1 OR diff --git a/samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf b/samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf new file mode 100644 index 0000000000000..24080dbba791c --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf @@ -0,0 +1,4 @@ +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_GLIKEY_MCUX_GLIKEY=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay b/samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay new file mode 100644 index 0000000000000..db51f5184fd5a --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox1_b 0>, <&mbox1_b 1>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/sysbuild.cmake b/samples/drivers/mbox/sysbuild.cmake index 0644500ca4866..cd5625533c3cd 100644 --- a/samples/drivers/mbox/sysbuild.cmake +++ b/samples/drivers/mbox/sysbuild.cmake @@ -24,6 +24,7 @@ native_simulator_set_final_executable(${DEFAULT_IMAGE}) if(SB_CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR SB_CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR SB_CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR + SB_CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR SB_CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) # For these NXP boards the main core application is dependent on # 'zephyr_image_info.h' generated by remote application. diff --git a/samples/drivers/mbox_data/CMakeLists.txt b/samples/drivers/mbox_data/CMakeLists.txt index 52192878048ed..4d45835e59326 100644 --- a/samples/drivers/mbox_data/CMakeLists.txt +++ b/samples/drivers/mbox_data/CMakeLists.txt @@ -11,6 +11,7 @@ set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR + CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR diff --git a/samples/drivers/mbox_data/Kconfig.sysbuild b/samples/drivers/mbox_data/Kconfig.sysbuild index d6388b3aa54a2..e68384343a654 100644 --- a/samples/drivers/mbox_data/Kconfig.sysbuild +++ b/samples/drivers/mbox_data/Kconfig.sysbuild @@ -10,6 +10,7 @@ string default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk" + default "mimxrt700_evk/mimxrt798s/cm33_cpu1" if $(BOARD) = "mimxrt700_evk" default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947" default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk" diff --git a/samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf new file mode 100644 index 0000000000000..60eead5a076e4 --- /dev/null +++ b/samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf @@ -0,0 +1,2 @@ +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay new file mode 100644 index 0000000000000..c85d52225ba05 --- /dev/null +++ b/samples/drivers/mbox_data/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox1_a 3>, <&mbox1_a 2>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox_data/remote/CMakeLists.txt b/samples/drivers/mbox_data/remote/CMakeLists.txt index efb3e573dce12..86e4eecce5629 100644 --- a/samples/drivers/mbox_data/remote/CMakeLists.txt +++ b/samples/drivers/mbox_data/remote/CMakeLists.txt @@ -9,6 +9,7 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 OR CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 OR + CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1 OR CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU1 OR CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU1 OR CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 OR diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf b/samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf new file mode 100644 index 0000000000000..3c0d59c603fec --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf @@ -0,0 +1,3 @@ +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay new file mode 100644 index 0000000000000..3fbee3cfc8dad --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox1_b 2>, <&mbox1_b 3>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox_data/sysbuild.cmake b/samples/drivers/mbox_data/sysbuild.cmake index dcb2509a05d57..866206b6a6813 100644 --- a/samples/drivers/mbox_data/sysbuild.cmake +++ b/samples/drivers/mbox_data/sysbuild.cmake @@ -19,6 +19,7 @@ ExternalZephyrProject_Add( if(SB_CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR SB_CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR SB_CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR + SB_CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR SB_CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) # For these NXP boards the main core application is dependent on # 'zephyr_image_info.h' generated by remote application. diff --git a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt index 33ee890f8f8f9..3acc4b71b633c 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt @@ -18,6 +18,7 @@ if(NOT (CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR + CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 diff --git a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild index 4f6465f0e43c0..7d611fe0187a4 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild @@ -13,6 +13,7 @@ string default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt700_evk/mimxrt798s/cm33_cpu1" if $(BOARD) = "mimxrt700_evk" default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947" default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk" default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk" diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf new file mode 100644 index 0000000000000..88c8f9d0fa506 --- /dev/null +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf @@ -0,0 +1,9 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_DCACHE=n diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay new file mode 100644 index 0000000000000..dbb8005130d40 --- /dev/null +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay @@ -0,0 +1,49 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + /* Define memory regions for IPC */ + sram1_ipc0: memory@20200000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20200000 DT_SIZE_K(16)>; + zephyr,memory-region="SRAM1_IPC0"; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + }; + + sram1_ipc1: memory@20204000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20204000 DT_SIZE_K(16)>; + zephyr,memory-region="SRAM1_IPC1"; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + }; + + ipc { + /delete-node/ ipc0; + + ipc0: ipc0 { + compatible = "zephyr,ipc-openamp-static-vrings"; + memory-region = <&sram1_ipc0>; + mboxes = <&mbox1_a 0>, <&mbox1_a 1>; + mbox-names = "tx", "rx"; + role = "host"; + status = "okay"; + }; + + ipc1: ipc1 { + compatible = "zephyr,ipc-openamp-static-vrings"; + memory-region = <&sram1_ipc1>; + mboxes = <&mbox1_a 2>, <&mbox1_a 3>; + mbox-names = "tx", "rx"; + role = "host"; + zephyr,priority = <1 PRIO_COOP>; + zephyr,buffer-size = <128>; + status = "okay"; + }; + }; +}; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf new file mode 100644 index 0000000000000..eee6d29ed184c --- /dev/null +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf @@ -0,0 +1,8 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay new file mode 100644 index 0000000000000..89da4297239de --- /dev/null +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay @@ -0,0 +1,49 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + /* Define memory regions for IPC */ + sram1_ipc0: memory@20200000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20200000 DT_SIZE_K(16)>; + zephyr,memory-region="SRAM1_IPC0"; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + }; + + sram1_ipc1: memory@20204000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20204000 DT_SIZE_K(16)>; + zephyr,memory-region="SRAM1_IPC1"; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + }; + + ipc { + /delete-node/ ipc0; + + ipc0: ipc0 { + compatible = "zephyr,ipc-openamp-static-vrings"; + memory-region = <&sram1_ipc0>; + mboxes = <&mbox1_b 0>, <&mbox1_b 1>; + mbox-names = "rx", "tx"; + role = "remote"; + status = "okay"; + }; + + ipc1: ipc1 { + compatible = "zephyr,ipc-openamp-static-vrings"; + memory-region = <&sram1_ipc1>; + mboxes = <&mbox1_b 2>, <&mbox1_b 3>; + mbox-names = "rx", "tx"; + role = "remote"; + zephyr,priority = <1 PRIO_COOP>; + zephyr,buffer-size = <128>; + status = "okay"; + }; + }; +}; diff --git a/samples/subsys/ipc/openamp/Kconfig.sysbuild b/samples/subsys/ipc/openamp/Kconfig.sysbuild index b0548a0a0cf09..b94d70254e156 100644 --- a/samples/subsys/ipc/openamp/Kconfig.sysbuild +++ b/samples/subsys/ipc/openamp/Kconfig.sysbuild @@ -16,5 +16,7 @@ string default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947" default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk" default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk" + default "mimxrt700_evk/mimxrt798s/cm33_cpu1" if $(BOARD) = "mimxrt700_evk" + default "esp32s3_devkitm/esp32s3/appcpu" if $(BOARD) = "esp32s3_devkitm" default "esp32s3_devkitc/esp32s3/appcpu" if $(BOARD) = "esp32s3_devkitc" default "esp32_devkitc/esp32/appcpu" if $(BOARD) = "esp32_devkitc" diff --git a/samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf new file mode 100644 index 0000000000000..b191313b58e11 --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf @@ -0,0 +1,8 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay new file mode 100644 index 0000000000000..5339497a202a4 --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay @@ -0,0 +1,20 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,ipc_shm = &sram1; + zephyr,ipc = &mailbox_a; + }; + + mailbox_a: ipm-mbox { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox1_a 1>, <&mbox1_a 0>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf new file mode 100644 index 0000000000000..e0cd3022c81e6 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.conf @@ -0,0 +1,9 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay new file mode 100644 index 0000000000000..039deeecf2f0c --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay @@ -0,0 +1,20 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,ipc_shm = &sram1; + zephyr,ipc = &mailbox_b; + }; + + mailbox_b: ipm-mbox { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox1_b 0>, <&mbox1_b 1>; + mbox-names = "tx", "rx"; + }; +}; From 68238d6377d260533751d3480fa44db7b846862c Mon Sep 17 00:00:00 2001 From: Tomas Galbicka Date: Tue, 12 Aug 2025 09:19:46 +0200 Subject: [PATCH 4/4] soc: RT700 add custom MPU regions for non-cache memory This commit adds custom MPU regions for RT700 CM33 CPU0 to define non-cachable region for SRAM. Signed-off-by: Tomas Galbicka --- soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt | 4 ++++ soc/nxp/imxrt/imxrt7xx/cm33/Kconfig | 1 + soc/nxp/imxrt/imxrt7xx/cm33/mpu_regions.c | 22 ++++++++++++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 soc/nxp/imxrt/imxrt7xx/cm33/mpu_regions.c diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt index 6e6f2a42fb24b..3596a099e2eb2 100644 --- a/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt +++ b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt @@ -17,6 +17,10 @@ zephyr_sources_ifdef(CONFIG_MIPI_DSI display_if.c) zephyr_sources_ifdef(CONFIG_MFD_PCA9422 pmic_int.c) +if(CONFIG_SOC_MIMXRT798S_CM33_CPU0) + zephyr_sources(mpu_regions.c) +endif() + if(CONFIG_FLASH_MCUX_XSPI_XIP) zephyr_sources(flash_clock_setup.c) zephyr_code_relocate(FILES flash_clock_setup.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_TEXT) diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig b/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig index f90e6446033b0..34d1d8da87f37 100644 --- a/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig +++ b/soc/nxp/imxrt/imxrt7xx/cm33/Kconfig @@ -8,6 +8,7 @@ config SOC_MIMXRT798S_CM33_CPU0 select ARM select CPU_HAS_ARM_SAU select CPU_HAS_ARM_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS select CPU_HAS_FPU select ARMV8_M_DSP select ARM_TRUSTZONE_M diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/mpu_regions.c b/soc/nxp/imxrt/imxrt7xx/cm33/mpu_regions.c new file mode 100644 index 0000000000000..3ee65720201f2 --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/mpu_regions.c @@ -0,0 +1,22 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define REGION_SRAM1_SHM_BASE_ADDRESS 0x30200000 +#define REGION_SRAM1_SHM_SIZE 0x00200000 + +static const struct arm_mpu_region mpu_regions[] = { + MPU_REGION_ENTRY( + "SRAM2_SHM", REGION_SRAM1_SHM_BASE_ADDRESS, + REGION_RAM_NOCACHE_ATTR(REGION_SRAM1_SHM_BASE_ADDRESS, REGION_SRAM1_SHM_SIZE)), +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +};