diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a768151bf389a..c3e771cc1688b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,8 +13,11 @@ config FLOAT_HARD bool "Hard-float calling convention" default y depends on FPU + depends on !RISCV_ISA_RV32E + depends on RISCV_ISA_EXT_F help This option enables the hard-float calling convention. + Adds eight floating-point argument registers. choice RISCV_GP_PURPOSE prompt "Purpose of the global pointer (GP) register" diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index c109e99b69e6d..2e582ab36736d 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -1,29 +1,37 @@ # Copyright (c) 2022 Carlo Caione # SPDX-License-Identifier: Apache-2.0 +RISCV_ISA_BASE_PROP := riscv,isa-base +RISCV_ISA_EXT_PROP := riscv,isa-extensions + config RISCV_ISA_RV32I bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv32i) help RV32I Base Integer Instruction Set - 32bit config RISCV_ISA_RV32E bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv32e) help RV32E Base Integer Instruction Set (Embedded) - 32bit config RISCV_ISA_RV64I bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv64i) select 64BIT help RV64I Base Integer Instruction Set - 64bit config RISCV_ISA_RV128I bool + default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv128i) help RV128I Base Integer Instruction Set - 128bit config RISCV_ISA_EXT_M bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),m) help (M) - Standard Extension for Integer Multiplication and Division @@ -33,6 +41,7 @@ config RISCV_ISA_EXT_M config RISCV_ISA_EXT_A bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),a) imply RISCV_ISA_EXT_ZAAMO imply RISCV_ISA_EXT_ZALRSC help @@ -45,6 +54,7 @@ config RISCV_ISA_EXT_A config RISCV_ISA_EXT_F bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),f) select CPU_HAS_FPU help (F) - Standard Extension for Single-Precision Floating-Point @@ -56,6 +66,7 @@ config RISCV_ISA_EXT_F config RISCV_ISA_EXT_D bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),d) depends on RISCV_ISA_EXT_F select CPU_HAS_FPU_DOUBLE_PRECISION help @@ -68,6 +79,7 @@ config RISCV_ISA_EXT_D config RISCV_ISA_EXT_G bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),g) select RISCV_ISA_EXT_M select RISCV_ISA_EXT_A select RISCV_ISA_EXT_F @@ -79,6 +91,7 @@ config RISCV_ISA_EXT_G config RISCV_ISA_EXT_Q bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),q) depends on RISCV_ISA_RV64I depends on RISCV_ISA_EXT_F depends on RISCV_ISA_EXT_D @@ -91,6 +104,7 @@ config RISCV_ISA_EXT_Q config RISCV_ISA_EXT_C bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),c) select RISCV_ISA_EXT_ZCA select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E) @@ -103,6 +117,7 @@ config RISCV_ISA_EXT_C config RISCV_ISA_EXT_ZICNTR bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zicntr) depends on RISCV_ISA_EXT_ZICSR help (Zicntr) - Standard Extension for Base Counters and Timers @@ -113,6 +128,7 @@ config RISCV_ISA_EXT_ZICNTR config RISCV_ISA_EXT_ZICSR bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zicsr) help (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions @@ -121,6 +137,7 @@ config RISCV_ISA_EXT_ZICSR config RISCV_ISA_EXT_ZIFENCEI bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zifencei) help (Zifencei) - Standard Extension for Instruction-Fetch Fence @@ -130,6 +147,7 @@ config RISCV_ISA_EXT_ZIFENCEI config RISCV_ISA_EXT_ZAAMO bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zaamo) help (Zaamo) - Atomic memory operation subset of the A extension @@ -137,6 +155,7 @@ config RISCV_ISA_EXT_ZAAMO config RISCV_ISA_EXT_ZALRSC bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zalrsc) help (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension @@ -144,6 +163,7 @@ config RISCV_ISA_EXT_ZALRSC config RISCV_ISA_EXT_ZCA bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zca) help (Zca) - Zba Extension for Compressed Instructions @@ -152,6 +172,7 @@ config RISCV_ISA_EXT_ZCA config RISCV_ISA_EXT_ZCB bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcb) depends on RISCV_ISA_EXT_ZCA help (Zcb) - Zcb Extension for Simple Compressed Instructions @@ -161,6 +182,7 @@ config RISCV_ISA_EXT_ZCB config RISCV_ISA_EXT_ZCD bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcd) depends on RISCV_ISA_EXT_D depends on RISCV_ISA_EXT_ZCA help @@ -171,6 +193,7 @@ config RISCV_ISA_EXT_ZCD config RISCV_ISA_EXT_ZCF bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcf) depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E depends on RISCV_ISA_EXT_F depends on RISCV_ISA_EXT_ZCA @@ -182,6 +205,7 @@ config RISCV_ISA_EXT_ZCF config RISCV_ISA_EXT_ZCMP bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcmp) depends on RISCV_ISA_EXT_ZCA depends on !RISCV_ISA_EXT_ZCD help @@ -192,6 +216,7 @@ config RISCV_ISA_EXT_ZCMP config RISCV_ISA_EXT_ZCMT bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcmt) depends on RISCV_ISA_EXT_ZICSR depends on RISCV_ISA_EXT_ZCA depends on !RISCV_ISA_EXT_ZCD @@ -203,6 +228,7 @@ config RISCV_ISA_EXT_ZCMT config RISCV_ISA_EXT_ZBA bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zba) help (Zba) - Zba BitManip Extension @@ -213,6 +239,7 @@ config RISCV_ISA_EXT_ZBA config RISCV_ISA_EXT_ZBB bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbb) help (Zbb) - Zbb BitManip Extension (Basic bit-manipulation) @@ -222,6 +249,7 @@ config RISCV_ISA_EXT_ZBB config RISCV_ISA_EXT_ZBC bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbc) help (Zbc) - Zbc BitManip Extension (Carry-less multiplication) @@ -230,6 +258,7 @@ config RISCV_ISA_EXT_ZBC config RISCV_ISA_EXT_ZBS bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbs) help (Zbs) - Zbs BitManip Extension (Single-bit instructions) @@ -239,6 +268,7 @@ config RISCV_ISA_EXT_ZBS config RISCV_ISA_EXT_ZMMUL bool + default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zmmul) help (Zmmul) - Zmmul Extension for Integer Multiplication diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 871cd600f8053..30552a400f618 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -70,3 +70,18 @@ set(scobc_module1_DEPRECATED set(raytac_an54l15q_db/nrf54l15/cpuapp_DEPRECATED raytac_an54lq_db_15/nrf54l15/cpuapp ) +set(qemu_riscv32_DEPRECATED + qemu_riscv/qemu_virt_riscv/rv32 +) +set(qemu_riscv32/qemu_virt_riscv32/smp_DEPRECATED + qemu_riscv/qemu_virt_riscv/rv32/smp +) +set(qemu_riscv32e_DEPRECATED + qemu_riscv/qemu_virt_riscv/rv32e +) +set(qemu_riscv64_DEPRECATED + qemu_riscv/qemu_virt_riscv/rv64 +) +set(qemu_riscv64/qemu_virt_riscv64/smp_DEPRECATED + qemu_riscv/qemu_virt_riscv/rv64/smp +) diff --git a/boards/qemu/riscv/Kconfig b/boards/qemu/riscv/Kconfig new file mode 100644 index 0000000000000..4d582ac08bb54 --- /dev/null +++ b/boards/qemu/riscv/Kconfig @@ -0,0 +1,6 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV + select QEMU_TARGET + select HAS_COVERAGE_SUPPORT diff --git a/boards/qemu/riscv/Kconfig.defconfig b/boards/qemu/riscv/Kconfig.defconfig new file mode 100644 index 0000000000000..e1e0ebd4c83ab --- /dev/null +++ b/boards/qemu/riscv/Kconfig.defconfig @@ -0,0 +1,16 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV + +# Use thread local storage by default so that this feature gets more CI coverage. +configdefault THREAD_LOCAL_STORAGE + default y + +configdefault BUILD_OUTPUT_BIN + default n + +configdefault QEMU_ICOUNT_SHIFT + default 6 + +endif # BOARD_QEMU_RISCV diff --git a/boards/qemu/riscv/Kconfig.qemu_riscv b/boards/qemu/riscv/Kconfig.qemu_riscv new file mode 100644 index 0000000000000..c8755042826ae --- /dev/null +++ b/boards/qemu/riscv/Kconfig.qemu_riscv @@ -0,0 +1,5 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV + select SOC_QEMU_VIRT_RISCV diff --git a/boards/qemu/riscv/board.cmake b/boards/qemu/riscv/board.cmake new file mode 100644 index 0000000000000..fd4f645968036 --- /dev/null +++ b/boards/qemu/riscv/board.cmake @@ -0,0 +1,37 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(riscv_isa_extensions) +set(riscv_isa_base) +dt_prop(riscv_isa_extensions PATH "/cpus/cpu@0" PROPERTY "riscv,isa-extensions" REQUIRED) +dt_prop(riscv_isa_base PATH "/cpus/cpu@0" PROPERTY "riscv,isa-base" REQUIRED) + +set(qemu_riscv_cpu "${riscv_isa_base}") +foreach(ext IN LISTS riscv_isa_extensions) + if(ext) + string(APPEND qemu_riscv_cpu ",${ext}=on") + endif() +endforeach() + +if(CONFIG_RISCV_PMP) + string(APPEND qemu_riscv_cpu ",pmp=on,u=on") +endif() + +if(CONFIG_64BIT) + set(QEMU_binary_suffix riscv64) +else() + set(QEMU_binary_suffix riscv32) +endif() + +set(QEMU_CPU_TYPE_${ARCH} "${qemu_riscv_cpu}") + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine virt + -bios none + -m 256 + -cpu ${qemu_riscv_cpu} + ) +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv/board.yml b/boards/qemu/riscv/board.yml new file mode 100644 index 0000000000000..94f83274dcf71 --- /dev/null +++ b/boards/qemu/riscv/board.yml @@ -0,0 +1,11 @@ +board: + name: qemu_riscv + full_name: QEMU Emulation for RISCV + vendor: qemu + socs: + - name: qemu_virt_riscv + variants: + - name: smp + cpucluster: rv32 + - name: smp + cpucluster: rv64 diff --git a/boards/qemu/riscv64/doc/index.rst b/boards/qemu/riscv/doc/index.rst similarity index 55% rename from boards/qemu/riscv64/doc/index.rst rename to boards/qemu/riscv/doc/index.rst index 884efce1f72ec..0e28806f461c8 100644 --- a/boards/qemu/riscv64/doc/index.rst +++ b/boards/qemu/riscv/doc/index.rst @@ -1,16 +1,16 @@ -.. zephyr:board:: qemu_riscv64 +.. zephyr:board:: qemu_riscv Overview ******** -The RISCV64 QEMU board configuration is used to emulate the RISCV64 architecture. +The RISCV QEMU board configuration is used to emulate the RISCV architecture. Get the Toolchain and QEMU ************************** The minimum version of the `Zephyr SDK tools `_ -with toolchain and QEMU support for the RISCV64 architecture is v0.10.2. +with toolchain and QEMU support for the RISCV architecture is v0.10.2. Please see the :ref:`installation instructions ` for more details. @@ -19,7 +19,7 @@ Programming and Debugging .. zephyr:board-supported-runners:: -Applications for the ``qemu_riscv64`` board configuration can be built and run in +Applications for the ``qemu_riscv`` board configuration can be built and run in the usual way for emulated boards (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -33,7 +33,21 @@ emulated environment. For example, with the :zephyr:code-sample:`synchronization .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix - :board: qemu_riscv64 + :board: qemu_riscv//rv32 + :goals: run + + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_riscv//rv32e + :goals: run + + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_riscv//rv64 :goals: run This will build an image with the synchronization sample app, boot it using @@ -42,16 +56,16 @@ QEMU, and display the following console output: .. code-block:: console ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 ***** - threadA: Hello World from riscv64! - threadB: Hello World from riscv64! - threadA: Hello World from riscv64! - threadB: Hello World from riscv64! - threadA: Hello World from riscv64! - threadB: Hello World from riscv64! - threadA: Hello World from riscv64! - threadB: Hello World from riscv64! - threadA: Hello World from riscv64! - threadB: Hello World from riscv64! + threadA: Hello World from riscv! + threadB: Hello World from riscv! + threadA: Hello World from riscv! + threadB: Hello World from riscv! + threadA: Hello World from riscv! + threadB: Hello World from riscv! + threadA: Hello World from riscv! + threadB: Hello World from riscv! + threadA: Hello World from riscv! + threadB: Hello World from riscv! Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. diff --git a/boards/qemu/riscv32e/qemu_riscv32e.dts b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv.dtsi similarity index 64% rename from boards/qemu/riscv32e/qemu_riscv32e.dts rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv.dtsi index 403d75cb74206..8e6cc5e242754 100644 --- a/boards/qemu/riscv32e/qemu_riscv32e.dts +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv.dtsi @@ -1,14 +1,10 @@ /* - * Copyright (c) 2022 Carlo Caione + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors * * SPDX-License-Identifier: Apache-2.0 * */ -/dts-v1/; - -#include - / { chosen { zephyr,console = &uart0; diff --git a/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32.dts b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32.dts new file mode 100644 index 0000000000000..7cd7177f82a4c --- /dev/null +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32.dts @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; + +#include +#include "qemu_riscv_qemu_virt_riscv.dtsi" diff --git a/boards/qemu/riscv32/qemu_riscv32.yaml b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32.yaml similarity index 83% rename from boards/qemu/riscv32/qemu_riscv32.yaml rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32.yaml index b6f258878a743..8dd848a1938cd 100644 --- a/boards/qemu/riscv32/qemu_riscv32.yaml +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32.yaml @@ -1,4 +1,4 @@ -identifier: qemu_riscv32 +identifier: qemu_riscv/qemu_virt_riscv/rv32 name: QEMU Emulation for RISC-V 32-bit type: qemu simulation: diff --git a/boards/qemu/riscv32/qemu_riscv32_defconfig b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_defconfig similarity index 68% rename from boards/qemu/riscv32/qemu_riscv32_defconfig rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_defconfig index 7a822571bb3c3..6dc4db61ee776 100644 --- a/boards/qemu/riscv32/qemu_riscv32_defconfig +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_defconfig @@ -1,3 +1,4 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_CONSOLE=y diff --git a/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp.dts b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp.dts new file mode 100644 index 0000000000000..7cd7177f82a4c --- /dev/null +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp.dts @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; + +#include +#include "qemu_riscv_qemu_virt_riscv.dtsi" diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp.yaml similarity index 83% rename from boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp.yaml index ab001b71df14a..cbe37bf3db250 100644 --- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp.yaml @@ -1,4 +1,4 @@ -identifier: qemu_riscv32/qemu_virt_riscv32/smp +identifier: qemu_riscv/qemu_virt_riscv/rv32/smp name: QEMU Emulation for RISC-V 32-bit SMP type: qemu simulation: diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp_defconfig similarity index 77% rename from boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp_defconfig index f52d8927f0c9b..9761bfe7dcb75 100644 --- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32_smp_defconfig @@ -1,3 +1,4 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_CONSOLE=y diff --git a/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e.dts b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e.dts new file mode 100644 index 0000000000000..e0f121d6f0e36 --- /dev/null +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e.dts @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; + +#include +#include "qemu_riscv_qemu_virt_riscv.dtsi" diff --git a/boards/qemu/riscv32e/qemu_riscv32e.yaml b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e.yaml similarity index 83% rename from boards/qemu/riscv32e/qemu_riscv32e.yaml rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e.yaml index 89fdcc478f75b..5385b91105979 100644 --- a/boards/qemu/riscv32e/qemu_riscv32e.yaml +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e.yaml @@ -1,4 +1,4 @@ -identifier: qemu_riscv32e +identifier: qemu_riscv/qemu_virt_riscv/rv32e name: QEMU Emulation for RISC-V (RV32E) 32-bit type: qemu simulation: diff --git a/boards/qemu/riscv32e/qemu_riscv32e_defconfig b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e_defconfig similarity index 72% rename from boards/qemu/riscv32e/qemu_riscv32e_defconfig rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e_defconfig index affc1eeffb740..c815598154e5c 100644 --- a/boards/qemu/riscv32e/qemu_riscv32e_defconfig +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv32e_defconfig @@ -1,3 +1,4 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_CONSOLE=y diff --git a/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64.dts b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64.dts new file mode 100644 index 0000000000000..51f6dc4761862 --- /dev/null +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64.dts @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; + +#include +#include "qemu_riscv_qemu_virt_riscv.dtsi" diff --git a/boards/qemu/riscv64/qemu_riscv64.yaml b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64.yaml similarity index 83% rename from boards/qemu/riscv64/qemu_riscv64.yaml rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64.yaml index 240ebcdbde92d..517bf14e67821 100644 --- a/boards/qemu/riscv64/qemu_riscv64.yaml +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64.yaml @@ -1,4 +1,4 @@ -identifier: qemu_riscv64 +identifier: qemu_riscv/qemu_virt_riscv/rv64 name: QEMU Emulation for RISC-V 64-bit type: qemu simulation: diff --git a/boards/qemu/riscv64/qemu_riscv64_defconfig b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_defconfig similarity index 73% rename from boards/qemu/riscv64/qemu_riscv64_defconfig rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_defconfig index 18dbae0da7755..8e3071546f0ad 100644 --- a/boards/qemu/riscv64/qemu_riscv64_defconfig +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_defconfig @@ -1,3 +1,4 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_PRIVILEGED_STACK_SIZE=2048 diff --git a/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp.dts b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp.dts new file mode 100644 index 0000000000000..51f6dc4761862 --- /dev/null +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp.dts @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; + +#include +#include "qemu_riscv_qemu_virt_riscv.dtsi" diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp.yaml similarity index 83% rename from boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp.yaml index ebcfb42e1f003..2106f70a5038d 100644 --- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp.yaml @@ -1,4 +1,4 @@ -identifier: qemu_riscv64/qemu_virt_riscv64/smp +identifier: qemu_riscv/qemu_virt_riscv/rv64/smp name: QEMU Emulation for RISC-V 64-bit SMP type: qemu simulation: diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp_defconfig similarity index 79% rename from boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig rename to boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp_defconfig index 948e0bad3631d..fc0c4290312ef 100644 --- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig +++ b/boards/qemu/riscv/qemu_riscv_qemu_virt_riscv_rv64_smp_defconfig @@ -1,3 +1,4 @@ +# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_PRIVILEGED_STACK_SIZE=2048 diff --git a/boards/qemu/riscv32/Kconfig b/boards/qemu/riscv32/Kconfig deleted file mode 100644 index 96de9ecb50734..0000000000000 --- a/boards/qemu/riscv32/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32 - select QEMU_TARGET diff --git a/boards/qemu/riscv32/Kconfig.defconfig b/boards/qemu/riscv32/Kconfig.defconfig deleted file mode 100644 index 8564054e21de5..0000000000000 --- a/boards/qemu/riscv32/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_RISCV32 - -# Use thread local storage by default so that this feature gets more CI coverage. -config THREAD_LOCAL_STORAGE - default y - -config BUILD_OUTPUT_BIN - default n - -config HAS_COVERAGE_SUPPORT - default y - -config QEMU_ICOUNT_SHIFT - default 6 if QEMU_ICOUNT - -endif # BOARD_QEMU_RISCV32 diff --git a/boards/qemu/riscv32/Kconfig.qemu_riscv32 b/boards/qemu/riscv32/Kconfig.qemu_riscv32 deleted file mode 100644 index 39f614e955b09..0000000000000 --- a/boards/qemu/riscv32/Kconfig.qemu_riscv32 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32 - select SOC_QEMU_VIRT_RISCV32 diff --git a/boards/qemu/riscv32/board.cmake b/boards/qemu/riscv32/board.cmake deleted file mode 100644 index 1e13b4b5176cb..0000000000000 --- a/boards/qemu/riscv32/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_binary_suffix riscv32) -set(QEMU_CPU_TYPE_${ARCH} riscv32) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine virt - -bios none - -m 256 -) - -board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv32/board.yml b/boards/qemu/riscv32/board.yml deleted file mode 100644 index 00b7b794e24e5..0000000000000 --- a/boards/qemu/riscv32/board.yml +++ /dev/null @@ -1,8 +0,0 @@ -board: - name: qemu_riscv32 - full_name: QEMU Emulation for RISCV32 - vendor: qemu - socs: - - name: qemu_virt_riscv32 - variants: - - name: smp diff --git a/boards/qemu/riscv32/doc/index.rst b/boards/qemu/riscv32/doc/index.rst deleted file mode 100644 index 69e003c21f80c..0000000000000 --- a/boards/qemu/riscv32/doc/index.rst +++ /dev/null @@ -1,52 +0,0 @@ -.. zephyr:board:: qemu_riscv32 - -Overview -******** - -The RISCV32 QEMU board configuration is used to emulate the RISCV32 architecture. - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``qemu_riscv32`` board configuration can be built and run in -the usual way for emulated boards (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -While this board is emulated and you can't "flash" it, you can use this -configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_riscv32 - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 ***** - threadA: Hello World from riscv32! - threadB: Hello World from riscv32! - threadA: Hello World from riscv32! - threadB: Hello World from riscv32! - threadA: Hello World from riscv32! - threadB: Hello World from riscv32! - threadA: Hello World from riscv32! - threadB: Hello World from riscv32! - threadA: Hello World from riscv32! - threadB: Hello World from riscv32! - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/qemu/riscv32/qemu_riscv32.dts b/boards/qemu/riscv32/qemu_riscv32.dts deleted file mode 100644 index 2c38ca1da1d7c..0000000000000 --- a/boards/qemu/riscv32/qemu_riscv32.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts deleted file mode 100644 index 2c38ca1da1d7c..0000000000000 --- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/qemu/riscv32e/Kconfig b/boards/qemu/riscv32e/Kconfig deleted file mode 100644 index 515c3d7287ab0..0000000000000 --- a/boards/qemu/riscv32e/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32E - select QEMU_TARGET diff --git a/boards/qemu/riscv32e/Kconfig.defconfig b/boards/qemu/riscv32e/Kconfig.defconfig deleted file mode 100644 index c3424c8722a92..0000000000000 --- a/boards/qemu/riscv32e/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_RISCV32E - -# Use thread local storage by default so that this feature gets more CI coverage. -config THREAD_LOCAL_STORAGE - default y - -config BUILD_OUTPUT_BIN - default n - -config HAS_COVERAGE_SUPPORT - default y - -endif # BOARD_QEMU_RISCV32E diff --git a/boards/qemu/riscv32e/Kconfig.qemu_riscv32e b/boards/qemu/riscv32e/Kconfig.qemu_riscv32e deleted file mode 100644 index f1256088e617c..0000000000000 --- a/boards/qemu/riscv32e/Kconfig.qemu_riscv32e +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32E - select SOC_QEMU_VIRT_RISCV32E diff --git a/boards/qemu/riscv32e/board.cmake b/boards/qemu/riscv32e/board.cmake deleted file mode 100644 index 82ca0617c99fb..0000000000000 --- a/boards/qemu/riscv32e/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2022 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_binary_suffix riscv32) -set(QEMU_CPU_TYPE_${ARCH} riscv32) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine virt - -bios none - -m 256 - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv32e/board.yml b/boards/qemu/riscv32e/board.yml deleted file mode 100644 index e720485ff439c..0000000000000 --- a/boards/qemu/riscv32e/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: qemu_riscv32e - full_name: QEMU Emulation for RISCV32E - vendor: qemu - socs: - - name: qemu_virt_riscv32e diff --git a/boards/qemu/riscv32e/doc/index.rst b/boards/qemu/riscv32e/doc/index.rst deleted file mode 100644 index a45687eeb7d13..0000000000000 --- a/boards/qemu/riscv32e/doc/index.rst +++ /dev/null @@ -1,54 +0,0 @@ -.. zephyr:board:: qemu_riscv32e - -Overview -******** - -The RISCV32E QEMU board configuration is used to emulate the RISCV32 (RV32E) architecture. - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``qemu_riscv32e`` board configuration can be built and run in -the usual way for emulated boards (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -While this board is emulated and you can't "flash" it, you can use this -configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_riscv32e - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build v3.1.0-rc1-59-g0d66cc1f6645 *** - thread_a: Hello World from cpu 0 on qemu_riscv32e! - thread_b: Hello World from cpu 0 on qemu_riscv32e! - thread_a: Hello World from cpu 0 on qemu_riscv32e! - thread_b: Hello World from cpu 0 on qemu_riscv32e! - thread_a: Hello World from cpu 0 on qemu_riscv32e! - thread_b: Hello World from cpu 0 on qemu_riscv32e! - thread_a: Hello World from cpu 0 on qemu_riscv32e! - thread_b: Hello World from cpu 0 on qemu_riscv32e! - thread_a: Hello World from cpu 0 on qemu_riscv32e! - thread_b: Hello World from cpu 0 on qemu_riscv32e! - thread_a: Hello World from cpu 0 on qemu_riscv32e! - thread_b: Hello World from cpu 0 on qemu_riscv32e! - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/qemu/riscv64/Kconfig b/boards/qemu/riscv64/Kconfig deleted file mode 100644 index 6adb7c150323a..0000000000000 --- a/boards/qemu/riscv64/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV64 - select QEMU_TARGET diff --git a/boards/qemu/riscv64/Kconfig.defconfig b/boards/qemu/riscv64/Kconfig.defconfig deleted file mode 100644 index 90a501d002d0f..0000000000000 --- a/boards/qemu/riscv64/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_RISCV64 - -config BUILD_OUTPUT_BIN - default n - -config HAS_COVERAGE_SUPPORT - default y - -config QEMU_ICOUNT_SHIFT - default 6 if QEMU_ICOUNT - -endif # BOARD_QEMU_RISCV64 diff --git a/boards/qemu/riscv64/Kconfig.qemu_riscv64 b/boards/qemu/riscv64/Kconfig.qemu_riscv64 deleted file mode 100644 index 7d136aebb2271..0000000000000 --- a/boards/qemu/riscv64/Kconfig.qemu_riscv64 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV64 - select SOC_QEMU_VIRT_RISCV64 diff --git a/boards/qemu/riscv64/board.cmake b/boards/qemu/riscv64/board.cmake deleted file mode 100644 index 05c75a5b8a429..0000000000000 --- a/boards/qemu/riscv64/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_binary_suffix riscv64) -set(QEMU_CPU_TYPE_${ARCH} riscv64) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine virt - -bios none - -m 256 - ) -board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv64/board.yml b/boards/qemu/riscv64/board.yml deleted file mode 100644 index eeab9480a24a1..0000000000000 --- a/boards/qemu/riscv64/board.yml +++ /dev/null @@ -1,8 +0,0 @@ -board: - name: qemu_riscv64 - full_name: QEMU Emulation for RISCV64 - vendor: qemu - socs: - - name: qemu_virt_riscv64 - variants: - - name: smp diff --git a/boards/qemu/riscv64/qemu_riscv64.dts b/boards/qemu/riscv64/qemu_riscv64.dts deleted file mode 100644 index 673d46680192f..0000000000000 --- a/boards/qemu/riscv64/qemu_riscv64.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2019 BayLibre SAS */ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts deleted file mode 100644 index 673d46680192f..0000000000000 --- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2019 BayLibre SAS */ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake index e440d4e2b1587..e4f46b2665e53 100644 --- a/cmake/compiler/gcc/target_riscv.cmake +++ b/cmake/compiler/gcc/target_riscv.cmake @@ -12,121 +12,124 @@ elseif(CONFIG_RISCV_CMODEL_LARGE) endif() if(CONFIG_64BIT) - string(CONCAT riscv_mabi ${riscv_mabi} "64") - string(CONCAT riscv_march ${riscv_march} "64") + string(APPEND riscv_mabi "64") + string(APPEND riscv_march "64") else() string(CONCAT riscv_mabi "i" ${riscv_mabi} "32") - string(CONCAT riscv_march ${riscv_march} "32") + string(APPEND riscv_march "32") endif() if(CONFIG_RISCV_ISA_RV32E) - string(CONCAT riscv_mabi ${riscv_mabi} "e") - string(CONCAT riscv_march ${riscv_march} "e") + string(APPEND riscv_mabi "e") + string(APPEND riscv_march "e") else() - string(CONCAT riscv_march ${riscv_march} "i") + string(APPEND riscv_march "i") endif() if(CONFIG_RISCV_ISA_EXT_M) - string(CONCAT riscv_march ${riscv_march} "m") + string(APPEND riscv_march "m") endif() if(CONFIG_RISCV_ISA_EXT_A) - string(CONCAT riscv_march ${riscv_march} "a") + string(APPEND riscv_march "a") endif() -if(CONFIG_FPU) +if(CONFIG_FLOAT_HARD) if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION) - if(CONFIG_FLOAT_HARD) - string(CONCAT riscv_mabi ${riscv_mabi} "d") - endif() - string(CONCAT riscv_march ${riscv_march} "fd") + string(APPEND riscv_mabi "d") else() - if(CONFIG_FLOAT_HARD) - string(CONCAT riscv_mabi ${riscv_mabi} "f") - endif() - string(CONCAT riscv_march ${riscv_march} "f") + string(APPEND riscv_mabi "f") + endif() +endif() + +if(CONFIG_FPU) + if(CONFIG_RISCV_ISA_EXT_F) + string(APPEND riscv_march "f") + endif() + if(CONFIG_RISCV_ISA_EXT_D) + string(APPEND riscv_march "d") endif() endif() if(CONFIG_RISCV_ISA_EXT_C) - string(CONCAT riscv_march ${riscv_march} "c") + string(APPEND riscv_march "c") endif() if(CONFIG_RISCV_ISA_EXT_ZICNTR) - string(CONCAT riscv_march ${riscv_march} "_zicntr") + string(APPEND riscv_march "_zicntr") endif() if(CONFIG_RISCV_ISA_EXT_ZICSR) - string(CONCAT riscv_march ${riscv_march} "_zicsr") + string(APPEND riscv_march "_zicsr") endif() if(CONFIG_RISCV_ISA_EXT_ZIFENCEI) - string(CONCAT riscv_march ${riscv_march} "_zifencei") + string(APPEND riscv_march "_zifencei") endif() # Check whether we already imply Zaamo/Zalrsc by selecting the A extension; if not - check them # individually and enable them as needed if(NOT CONFIG_RISCV_ISA_EXT_A) if(CONFIG_RISCV_ISA_EXT_ZAAMO) - string(CONCAT riscv_march ${riscv_march} "_zaamo") + string(APPEND riscv_march "_zaamo") endif() if(CONFIG_RISCV_ISA_EXT_ZALRSC) - string(CONCAT riscv_march ${riscv_march} "_zalrsc") + string(APPEND riscv_march "_zalrsc") endif() endif() # Zca is implied by C if(CONFIG_RISCV_ISA_EXT_ZCA AND NOT CONFIG_RISCV_ISA_EXT_C) - string(CONCAT riscv_march ${riscv_march} "_zca") + string(APPEND riscv_march "_zca") endif() if(CONFIG_RISCV_ISA_EXT_ZCB) - string(CONCAT riscv_march ${riscv_march} "_zcb") + string(APPEND riscv_march "_zcb") endif() # Zcd is implied by C+D if(CONFIG_RISCV_ISA_EXT_ZCD AND NOT (CONFIG_RISCV_ISA_EXT_C AND CONFIG_RISCV_ISA_EXT_D)) - string(CONCAT riscv_march ${riscv_march} "_zcd") + string(APPEND riscv_march "_zcd") endif() # Zcf is implied by C+F if(CONFIG_RISCV_ISA_EXT_ZCF AND NOT (CONFIG_RISCV_ISA_EXT_C AND CONFIG_RISCV_ISA_EXT_F)) - string(CONCAT riscv_march ${riscv_march} "_zcf") + string(APPEND riscv_march "_zcf") endif() if(CONFIG_RISCV_ISA_EXT_ZCMP) - string(CONCAT riscv_march ${riscv_march} "_zcmp") + string(APPEND riscv_march "_zcmp") endif() if(CONFIG_RISCV_ISA_EXT_ZCMT) - string(CONCAT riscv_march ${riscv_march} "_zcmt") + string(APPEND riscv_march "_zcmt") endif() if(CONFIG_RISCV_ISA_EXT_ZBA) - string(CONCAT riscv_march ${riscv_march} "_zba") + string(APPEND riscv_march "_zba") endif() if(CONFIG_RISCV_ISA_EXT_ZBB) - string(CONCAT riscv_march ${riscv_march} "_zbb") + string(APPEND riscv_march "_zbb") endif() if(CONFIG_RISCV_ISA_EXT_ZBC) - string(CONCAT riscv_march ${riscv_march} "_zbc") + string(APPEND riscv_march "_zbc") endif() if(CONFIG_RISCV_ISA_EXT_ZBS) - string(CONCAT riscv_march ${riscv_march} "_zbs") + string(APPEND riscv_march "_zbs") endif() # Check whether we already imply Zmmul by selecting the M extension; if not - enable it if(NOT CONFIG_RISCV_ISA_EXT_M AND CONFIG_RISCV_ISA_EXT_ZMMUL AND "${GCC_COMPILER_VERSION}" VERSION_GREATER_EQUAL 13.0.0) - string(CONCAT riscv_march ${riscv_march} "_zmmul") + string(APPEND riscv_march "_zmmul") endif() list(APPEND RISCV_C_FLAGS diff --git a/doc/build/kconfig/preprocessor-functions.rst b/doc/build/kconfig/preprocessor-functions.rst index ab7429963409b..e4e3e33e74057 100644 --- a/doc/build/kconfig/preprocessor-functions.rst +++ b/doc/build/kconfig/preprocessor-functions.rst @@ -46,6 +46,7 @@ while the ``*_hex`` version returns a hexadecimal value starting with ``0x``. $(dt_compat_on_bus,,) $(dt_gpio_hogs_enabled) $(dt_has_compat,) + $(dt_node_array_prop_has_val,,,) $(dt_node_array_prop_hex,,,[,]) $(dt_node_array_prop_int,,,[,]) $(dt_node_bool_prop,,) diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index d70d062719633..f3461bd067081 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -1848,4 +1848,4 @@ To run a single testsuite instead of a whole group of test you can run: .. code-block:: bash - $ twister -p qemu_riscv32 -s tests/kernel/interrupt/arch.shared_interrupt + $ twister -p qemu_riscv/qemu_virt_riscv/rv32 -s tests/kernel/interrupt/arch.shared_interrupt diff --git a/doc/hardware/arch/risc-v.rst b/doc/hardware/arch/risc-v.rst index 473b614b44b20..f6b7af45eff6d 100644 --- a/doc/hardware/arch/risc-v.rst +++ b/doc/hardware/arch/risc-v.rst @@ -34,6 +34,6 @@ SMP support SMP is supported on RISC-V for both QEMU-virtualized and hardware-based platforms. In order to test the SMP support, one can use -:zephyr:board:`qemu_riscv32` or :zephyr:board:`qemu_riscv64` for QEMU-based +:zephyr:board:`qemu_riscv` for QEMU-based platforms, or :zephyr:board:`beaglev_fire` or :zephyr:board:`mpfs_icicle` for hardware-based platforms. diff --git a/dts/bindings/cpu/riscv,cpus.yaml b/dts/bindings/cpu/riscv,cpus.yaml index 883146d76b2ae..402ddfa160959 100644 --- a/dts/bindings/cpu/riscv,cpus.yaml +++ b/dts/bindings/cpu/riscv,cpus.yaml @@ -15,5 +15,22 @@ properties: riscv,isa: description: RISC-V instruction set architecture - required: true type: string + + riscv,isa-base: + description: The base ISA implemented by the hart. + type: string + enum: + - rv32i + - rv32e + - rv64i + - rv128i + + riscv,isa-extensions: + description: | + Extensions supported by the hart. Take a look at + https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml + and https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html + for a list of possible extensions. Not all options listed there are + necessarily supported by Zephyr. + type: string-array diff --git a/dts/riscv/qemu/virt-riscv32.dtsi b/dts/riscv/qemu/virt-riscv32.dtsi index 25d769d5183a9..c3271f60c2227 100644 --- a/dts/riscv/qemu/virt-riscv32.dtsi +++ b/dts/riscv/qemu/virt-riscv32.dtsi @@ -11,35 +11,43 @@ / { cpus { cpu@0 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@1 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@2 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@3 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@4 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@5 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@6 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; cpu@7 { - riscv,isa = "rv32gc"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "g", "c"; }; }; }; diff --git a/dts/riscv/qemu/virt-riscv32e.dtsi b/dts/riscv/qemu/virt-riscv32e.dtsi new file mode 100644 index 0000000000000..e7f79639739ec --- /dev/null +++ b/dts/riscv/qemu/virt-riscv32e.dtsi @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + cpus { + cpu@0 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@1 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@2 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@3 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@4 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@5 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@6 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + + cpu@7 { + riscv,isa-base = "rv32e"; + riscv,isa-extensions = "e", "m", "a", "c", "zicsr", "zifencei"; + }; + }; +}; diff --git a/dts/riscv/qemu/virt-riscv64.dtsi b/dts/riscv/qemu/virt-riscv64.dtsi index 936f0a1881526..50406e677dd09 100644 --- a/dts/riscv/qemu/virt-riscv64.dtsi +++ b/dts/riscv/qemu/virt-riscv64.dtsi @@ -11,35 +11,43 @@ / { cpus { cpu@0 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@1 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@2 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@3 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@4 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@5 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@6 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; cpu@7 { - riscv,isa = "rv64gc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "g", "c"; }; }; }; diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi index c51803ed5ab84..fff9b2c4518b7 100644 --- a/dts/riscv/riscv32-litex-vexriscv.dtsi +++ b/dts/riscv/riscv32-litex-vexriscv.dtsi @@ -20,6 +20,8 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv32im_zicsr_zifencei"; + riscv,isa-base = "rv32i"; + riscv,isa-extensions = "i", "m", "zicsr", "zifencei"; status = "okay"; }; }; diff --git a/samples/basic/minimal/sample.yaml b/samples/basic/minimal/sample.yaml index 3330ea4af2a36..305054ba42dd9 100644 --- a/samples/basic/minimal/sample.yaml +++ b/samples/basic/minimal/sample.yaml @@ -100,11 +100,11 @@ tests: sample.minimal.riscv.runtime: extra_args: - CONF_FILE='common-runtime.conf;no-timers.conf;no-mt.conf;riscv.conf' - platform_allow: qemu_riscv32 + platform_allow: qemu_riscv/qemu_virt_riscv/rv32 tags: - kernel integration_platforms: - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv32 sample.minimal.no-mt-no-sw-isr-table.arm: extra_args: EXTRA_CONF_FILE='common.conf;no-mt.conf;no-sw-isr-table.conf;arm.conf' build_only: true diff --git a/samples/cpp/hello_world/README.rst b/samples/cpp/hello_world/README.rst index 1d09d8a977f8e..69c6f637a746b 100644 --- a/samples/cpp/hello_world/README.rst +++ b/samples/cpp/hello_world/README.rst @@ -17,17 +17,17 @@ This configuration can be built and executed on QEMU as follows: .. zephyr-app-commands:: :zephyr-app: samples/cpp/hello_world :host-os: unix - :board: qemu_riscv32 + :board: qemu_riscv//rv32 :goals: run :compact: -To build for another board, change "qemu_riscv32" above to that board's name. +To build for another board, change "qemu_riscv//rv32" above to that board's name. Sample Output ============= .. code-block:: console - Hello C++, world! qemu_riscv32 + Hello C++, world! qemu_riscv Exit QEMU by pressing :kbd:`CTRL+C` diff --git a/samples/cpp/hello_world/sample.yaml b/samples/cpp/hello_world/sample.yaml index 98ae71ebe8345..d80be8c77e8b7 100644 --- a/samples/cpp/hello_world/sample.yaml +++ b/samples/cpp/hello_world/sample.yaml @@ -6,7 +6,7 @@ common: - introduction - cpp integration_platforms: - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv32 harness: console harness_config: type: one_line diff --git a/samples/modules/compression/lz4/sample.yaml b/samples/modules/compression/lz4/sample.yaml index a5c36ff7a8e28..d355aae751369 100644 --- a/samples/modules/compression/lz4/sample.yaml +++ b/samples/modules/compression/lz4/sample.yaml @@ -18,7 +18,7 @@ tests: sample.compression.lz4: integration_platforms: - mps2/an385 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tags: - compression - lz4 diff --git a/samples/posix/env/README.rst b/samples/posix/env/README.rst index 2f020ba6b88d1..8a5eb9c501b72 100644 --- a/samples/posix/env/README.rst +++ b/samples/posix/env/README.rst @@ -20,7 +20,7 @@ This project outputs to the console. It can be built and executed on QEMU as fol .. zephyr-app-commands:: :zephyr-app: samples/posix/env :host-os: unix - :board: qemu_riscv32 + :board: qemu_riscv//rv32 :goals: run :compact: @@ -31,7 +31,7 @@ The program below shows sample output for a specific Zephyr build. .. code-block:: console - BOARD=qemu_riscv32 + BOARD=qemu_riscv BUILD_VERSION=zephyr-v3.5.0-5372-g3a46f2d052c7 ALERT= @@ -60,7 +60,7 @@ The shell command below may be used to display the value associated with one env .. code-block:: console uart:~$ posix env get BOARD - qemu_riscv32 + qemu_riscv The shell command below may be used to display all environment variables and their associated values. @@ -68,7 +68,7 @@ values. .. code-block:: console uart:~$ posix env get - BOARD=qemu_riscv32 + BOARD=qemu_riscv BUILD_VERSION=zephyr-v3.5.0-5372-g3a46f2d052c7 ALERT= diff --git a/samples/posix/philosophers/README.rst b/samples/posix/philosophers/README.rst index 6cd73ee637f15..6167afe103b65 100644 --- a/samples/posix/philosophers/README.rst +++ b/samples/posix/philosophers/README.rst @@ -18,7 +18,7 @@ This project outputs to the console. It can be built and executed on QEMU as fol .. zephyr-app-commands:: :zephyr-app: samples/posix/philosophers :host-os: unix - :board: qemu_riscv64 + :board: qemu_riscv//rv64 :goals: run :compact: diff --git a/samples/posix/uname/sample.yaml b/samples/posix/uname/sample.yaml index d65596b72a316..7159dc13cf6fd 100644 --- a/samples/posix/uname/sample.yaml +++ b/samples/posix/uname/sample.yaml @@ -5,7 +5,7 @@ common: tags: posix integration_platforms: - native_sim - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 harness: console harness_config: type: multi_line diff --git a/samples/sensor/sensor_shell/README.rst b/samples/sensor/sensor_shell/README.rst index 65653741bc216..166823a54f5fd 100644 --- a/samples/sensor/sensor_shell/README.rst +++ b/samples/sensor/sensor_shell/README.rst @@ -24,7 +24,7 @@ adding the following overlay: .. zephyr-app-commands:: :zephyr-app: samples/sensor/sensor_shell - :board: qemu_riscv64 + :board: qemu_riscv//rv64 :goals: run :gen-args: -DEXTRA_DTC_OVERLAY_FILE=fake_sensor.overlay diff --git a/samples/subsys/profiling/perf/README.rst b/samples/subsys/profiling/perf/README.rst index a50a2433a0eb4..ea8ad476005cb 100644 --- a/samples/subsys/profiling/perf/README.rst +++ b/samples/subsys/profiling/perf/README.rst @@ -18,7 +18,7 @@ Usage example .. zephyr-app-commands:: :zephyr-app: samples/subsys/profiling/perf - :board: qemu_riscv64 + :board: qemu_riscv//rv64 :goals: run :compact: diff --git a/samples/subsys/profiling/perf/sample.yaml b/samples/subsys/profiling/perf/sample.yaml index 261c2f957bb50..1eea49cb1615d 100644 --- a/samples/subsys/profiling/perf/sample.yaml +++ b/samples/subsys/profiling/perf/sample.yaml @@ -11,8 +11,8 @@ tests: - CONFIG_PROFILING_PERF_BUFFER_SIZE=128 filter: CONFIG_RISCV or CONFIG_X86 integration_platforms: - - qemu_riscv64 - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv64 + - qemu_riscv/qemu_virt_riscv/rv32 - qemu_x86_64 - qemu_x86 harness: pytest diff --git a/samples/userspace/hello_world_user/README.rst b/samples/userspace/hello_world_user/README.rst index 22ece4becea61..dd4c4eca57725 100644 --- a/samples/userspace/hello_world_user/README.rst +++ b/samples/userspace/hello_world_user/README.rst @@ -24,7 +24,7 @@ It can be built and executed on QEMU as follows: .. zephyr-app-commands:: :zephyr-app: samples/userspace/hello_world_user :host-os: unix - :board: qemu_riscv32 + :board: qemu_riscv//rv32 :goals: run :compact: @@ -33,6 +33,6 @@ Sample Output .. code-block:: console - Hello World from UserSpace! qemu_riscv32 + Hello World from UserSpace! qemu_riscv Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. diff --git a/scripts/kconfig/kconfigfunctions.py b/scripts/kconfig/kconfigfunctions.py index d92017853a674..8e078c1418e87 100644 --- a/scripts/kconfig/kconfigfunctions.py +++ b/scripts/kconfig/kconfigfunctions.py @@ -940,25 +940,64 @@ def dt_nodelabel_enabled_with_compat(kconf, _, label, compat): return "n" +def _dt_node_array_prop_has_val_generic(node_search_function, search_arg, prop, val): + """ + This function takes the 'node_search_function' and uses it to search for + a node with 'search_arg' and it checks if the node node has a property + 'prop' with type "array". If so, and the property contains + an element equal to the integer 'val', it returns "y". + If the property is of type "string-array", it checks if 'val' is + one of the strings in the array, returning "y" if so. + Otherwise, it returns "n". + """ + try: + node = node_search_function(search_arg) + except edtlib.EDTError: + return "n" -def dt_nodelabel_array_prop_has_val(kconf, _, label, prop, val): + if node is None: + return "n" + + if prop not in node.props: + return "n" + + if node.props[prop].type == "array": + return "y" if int(val, base=0) in node.props[prop].val else "n" + + if node.props[prop].type == "string-array": + return "y" if val in node.props[prop].val else "n" + + return "n" + +def dt_node_array_prop_has_val(kconf, _, path, prop, val): """ - This function looks for a node with node label 'label'. - If the node exists, it checks if the node node has a property + This function looks for a node at 'path'. + If the node exists, it checks if the node has a property 'prop' with type "array". If so, and the property contains an element equal to the integer 'val', it returns "y". + If the property is of type "string-array", it checks if 'val' is + one of the strings in the array, returning "y" if so. Otherwise, it returns "n". """ if doc_mode or edt is None: return "n" - node = edt.label2node.get(label) + return _dt_node_array_prop_has_val_generic(edt.get_node, path, prop, val) - if not node or (prop not in node.props) or (node.props[prop].type != "array"): +def dt_nodelabel_array_prop_has_val(kconf, _, label, prop, val): + """ + This function looks for a node with node label 'label'. + If the node exists, it checks if the node node has a property + 'prop' with type "array". If so, and the property contains + an element equal to the integer 'val', it returns "y". + If the property is of type "string-array", it checks if 'val' is + one of the strings in the array, returning "y" if so. + Otherwise, it returns "n". + """ + if doc_mode or edt is None: return "n" - else: - return "y" if int(val, base=0) in node.props[prop].val else "n" + return _dt_node_array_prop_has_val_generic(edt.label2node.get, label, prop, val) def dt_nodelabel_path(kconf, _, label): """ @@ -1183,6 +1222,7 @@ def inc_dec(kconf, name, *args): "dt_nodelabel_path": (dt_nodelabel_path, 1, 1), "dt_node_parent": (dt_node_parent, 1, 1), "dt_nodelabel_array_prop_has_val": (dt_nodelabel_array_prop_has_val, 3, 3), + "dt_node_array_prop_has_val": (dt_node_array_prop_has_val, 3, 3), "dt_gpio_hogs_enabled": (dt_gpio_hogs_enabled, 0, 0), "dt_chosen_partition_addr_int": (dt_chosen_partition_addr, 1, 3), "dt_chosen_partition_addr_hex": (dt_chosen_partition_addr, 1, 3), diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig index 6a684f5c4ca9a..8750f724f2169 100644 --- a/soc/litex/litex_vexriscv/Kconfig +++ b/soc/litex/litex_vexriscv/Kconfig @@ -4,10 +4,6 @@ config SOC_LITEX_VEXRISCV select RISCV select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI imply XIP if SOC_LITEX_VEXRISCV diff --git a/soc/qemu/virt_riscv/Kconfig b/soc/qemu/virt_riscv/Kconfig index d17ac3296a12a..cb4f4dc8bcc95 100644 --- a/soc/qemu/virt_riscv/Kconfig +++ b/soc/qemu/virt_riscv/Kconfig @@ -1,18 +1,10 @@ # Copyright (c) 2024 Antmicro # SPDX-License-Identifier: Apache-2.0 -config SOC_FAMILY_QEMU_VIRT_RISCV +config SOC_QEMU_VIRT_RISCV select INCLUDE_RESET_VECTOR - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C select RISCV select RISCV_PRIVILEGED + select RISCV_HAS_PLIC select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP - -if SOC_FAMILY_QEMU_VIRT_RISCV - -rsource "*/Kconfig" - -endif # SOC_FAMILY_QEMU_VIRT_RISCV diff --git a/soc/qemu/virt_riscv/Kconfig.defconfig b/soc/qemu/virt_riscv/Kconfig.defconfig index 599c62a1acd3a..6e0b78170701f 100644 --- a/soc/qemu/virt_riscv/Kconfig.defconfig +++ b/soc/qemu/virt_riscv/Kconfig.defconfig @@ -2,7 +2,7 @@ # Copyright (c) 2024 Antmicro # SPDX-License-Identifier: Apache-2.0 -if SOC_FAMILY_QEMU_VIRT_RISCV +if SOC_QEMU_VIRT_RISCV config SYS_CLOCK_HW_CYCLES_PER_SEC default 10000000 @@ -28,4 +28,4 @@ config NUM_IRQS config PMP_SLOTS default 16 -endif # SOC_FAMILY_QEMU_VIRT_RISCV +endif # SOC_QEMU_VIRT_RISCV diff --git a/soc/qemu/virt_riscv/Kconfig.soc b/soc/qemu/virt_riscv/Kconfig.soc index ba3a1bd596124..7ec6c07648236 100644 --- a/soc/qemu/virt_riscv/Kconfig.soc +++ b/soc/qemu/virt_riscv/Kconfig.soc @@ -1,10 +1,8 @@ # Copyright (c) 2024 Antmicro # SPDX-License-Identifier: Apache-2.0 -config SOC_FAMILY_QEMU_VIRT_RISCV +config SOC_QEMU_VIRT_RISCV bool -config SOC_FAMILY - default "qemu_virt_riscv" if SOC_FAMILY_QEMU_VIRT_RISCV - -rsource "*/Kconfig.soc" +config SOC + default "qemu_virt_riscv" if SOC_QEMU_VIRT_RISCV diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig b/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig deleted file mode 100644 index f8f1157f247b5..0000000000000 --- a/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_RISCV32 - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_F - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_HAS_PLIC diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig.soc b/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig.soc deleted file mode 100644 index 4b1ee59adc1c9..0000000000000 --- a/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_RISCV32 - bool - select SOC_FAMILY_QEMU_VIRT_RISCV - -config SOC - default "qemu_virt_riscv32" if SOC_QEMU_VIRT_RISCV32 diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig b/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig deleted file mode 100644 index 973992ece9bfa..0000000000000 --- a/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Cobham Gaisler AB -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_RISCV32E - select RISCV_ISA_RV32E - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_HAS_PLIC diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig.soc b/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig.soc deleted file mode 100644 index 38b51ee58ffcf..0000000000000 --- a/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_RISCV32E - bool - select SOC_FAMILY_QEMU_VIRT_RISCV - -config SOC - default "qemu_virt_riscv32e" if SOC_QEMU_VIRT_RISCV32E diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig b/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig deleted file mode 100644 index b78e2bf5a9802..0000000000000 --- a/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_RISCV64 - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_F - select RISCV_ISA_EXT_D - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_HAS_PLIC diff --git a/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig.soc b/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig.soc deleted file mode 100644 index cfcf51103de24..0000000000000 --- a/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_RISCV64 - bool - select SOC_FAMILY_QEMU_VIRT_RISCV - -config SOC - default "qemu_virt_riscv64" if SOC_QEMU_VIRT_RISCV64 diff --git a/soc/qemu/virt_riscv/soc.yml b/soc/qemu/virt_riscv/soc.yml index 746051f76a902..b46cb53626a5a 100644 --- a/soc/qemu/virt_riscv/soc.yml +++ b/soc/qemu/virt_riscv/soc.yml @@ -1,6 +1,6 @@ -family: +socs: - name: qemu_virt_riscv - socs: - - name: qemu_virt_riscv32 - - name: qemu_virt_riscv32e - - name: qemu_virt_riscv64 + cpuclusters: + - name: rv32 + - name: rv32e + - name: rv64 diff --git a/tests/application_development/code_relocation/testcase.yaml b/tests/application_development/code_relocation/testcase.yaml index 99ca2107abf35..70755c0786a21 100644 --- a/tests/application_development/code_relocation/testcase.yaml +++ b/tests/application_development/code_relocation/testcase.yaml @@ -34,8 +34,8 @@ tests: buildsystem.app_dev.code_relocation.riscv: extra_args: CONF_FILE="prj_riscv.conf" platform_allow: - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 buildsystem.app_dev.code_relocation.xtensa: extra_args: CONF_FILE="prj_xtensa.conf" platform_allow: qemu_xtensa/dc233c diff --git a/tests/arch/common/gen_isr_table/testcase.yaml b/tests/arch/common/gen_isr_table/testcase.yaml index efd2050a1db33..d46942bfd732e 100644 --- a/tests/arch/common/gen_isr_table/testcase.yaml +++ b/tests/arch/common/gen_isr_table/testcase.yaml @@ -90,13 +90,13 @@ tests: extra_configs: - CONFIG_GEN_IRQ_VECTOR_TABLE=n arch.interrupt.gen_isr_table.bit_shift_2nd_level: - platform_allow: qemu_riscv32 + platform_allow: qemu_riscv/qemu_virt_riscv/rv32 extra_configs: - CONFIG_MAX_IRQ_PER_AGGREGATOR=52 - CONFIG_1ST_LEVEL_INTERRUPT_BITS=7 - CONFIG_2ND_LEVEL_INTERRUPT_BITS=9 arch.interrupt.gen_isr_table.bit_shift_3rd_level: - platform_allow: qemu_riscv32 + platform_allow: qemu_riscv/qemu_virt_riscv/rv32 extra_configs: - CONFIG_MAX_IRQ_PER_AGGREGATOR=52 - CONFIG_3RD_LEVEL_INTERRUPTS=y diff --git a/tests/arch/common/stack_unwind/testcase.yaml b/tests/arch/common/stack_unwind/testcase.yaml index 69696b31a3884..33fd7db76bfcc 100644 --- a/tests/arch/common/stack_unwind/testcase.yaml +++ b/tests/arch/common/stack_unwind/testcase.yaml @@ -7,9 +7,9 @@ tests: arch.common.stack_unwind.riscv_fp: arch_allow: riscv integration_platforms: - - qemu_riscv32e - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 extra_configs: - CONFIG_FRAME_POINTER=y harness_config: @@ -21,9 +21,9 @@ tests: arch.common.stack_unwind.riscv_sp: arch_allow: riscv integration_platforms: - - qemu_riscv32e - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 harness_config: type: multi_line regex: @@ -62,9 +62,9 @@ tests: - riscv - arm64 integration_platforms: - - qemu_riscv32e - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_cortex_a53 platform_exclude: # these platforms disabled here since CONFIG_ARM_MMU=n by default diff --git a/tests/arch/riscv/fatal/testcase.yaml b/tests/arch/riscv/fatal/testcase.yaml index f84c614578d96..1e0e77ca37f63 100644 --- a/tests/arch/riscv/fatal/testcase.yaml +++ b/tests/arch/riscv/fatal/testcase.yaml @@ -6,7 +6,7 @@ common: - kernel - riscv platform_allow: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tests: arch.riscv64.fatal.panic_sp: extra_configs: diff --git a/tests/arch/riscv/pmp/isr-stack-guard/testcase.yaml b/tests/arch/riscv/pmp/isr-stack-guard/testcase.yaml index de2f8b8363486..3e5e8f5833438 100644 --- a/tests/arch/riscv/pmp/isr-stack-guard/testcase.yaml +++ b/tests/arch/riscv/pmp/isr-stack-guard/testcase.yaml @@ -1,8 +1,8 @@ common: platform_allow: - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 filter: CONFIG_RISCV_PMP ignore_faults: true diff --git a/tests/arch/riscv/userspace/riscv_gp/testcase.yaml b/tests/arch/riscv/userspace/riscv_gp/testcase.yaml index ae311f60634a4..ce3cee037f67d 100644 --- a/tests/arch/riscv/userspace/riscv_gp/testcase.yaml +++ b/tests/arch/riscv/userspace/riscv_gp/testcase.yaml @@ -5,7 +5,7 @@ common: - kernel - riscv platform_allow: - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv64/smp tests: arch.riscv64.riscv_gp.relative_addressing: extra_configs: diff --git a/tests/benchmarks/latency_measure/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/benchmarks/latency_measure/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/benchmarks/latency_measure/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/benchmarks/latency_measure/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/benchmarks/latency_measure/testcase.yaml b/tests/benchmarks/latency_measure/testcase.yaml index e2efb4e3978d7..c1edd9634c925 100644 --- a/tests/benchmarks/latency_measure/testcase.yaml +++ b/tests/benchmarks/latency_measure/testcase.yaml @@ -15,7 +15,7 @@ tests: integration_platforms: - qemu_x86 - qemu_arc/qemu_arc_em - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv64/smp harness_config: type: one_line record: @@ -74,7 +74,7 @@ tests: integration_platforms: - qemu_x86 - qemu_arc/qemu_arc_em - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv64/smp harness_config: type: one_line record: diff --git a/tests/benchmarks/posix/threads/README.rst b/tests/benchmarks/posix/threads/README.rst index 8c084d1d240c8..364afb9e41de5 100644 --- a/tests/benchmarks/posix/threads/README.rst +++ b/tests/benchmarks/posix/threads/README.rst @@ -13,7 +13,7 @@ Sample output of the benchmark:: *** Booting Zephyr OS build v4.0.0-1410-gfca33facee37 *** ASSERT: y - BOARD: qemu_riscv64 + BOARD: qemu_riscv NUM_CPUS: 1 TEST_DELAY_US: 0 TEST_DURATION_S: 5 diff --git a/tests/benchmarks/posix/threads/testcase.yaml b/tests/benchmarks/posix/threads/testcase.yaml index e9798b76a86af..94ba6f537aa4e 100644 --- a/tests/benchmarks/posix/threads/testcase.yaml +++ b/tests/benchmarks/posix/threads/testcase.yaml @@ -7,8 +7,8 @@ common: - posix integration_platforms: - qemu_cortex_a53/qemu_cortex_a53/smp - - qemu_riscv64/qemu_virt_riscv64/smp - - qemu_riscv32/qemu_virt_riscv32/smp + - qemu_riscv/qemu_virt_riscv/rv64/smp + - qemu_riscv/qemu_virt_riscv/rv32/smp - qemu_x86_64 harness: console harness_config: diff --git a/tests/benchmarks/sched/testcase.yaml b/tests/benchmarks/sched/testcase.yaml index 3372e4476845b..5f781429e7b17 100644 --- a/tests/benchmarks/sched/testcase.yaml +++ b/tests/benchmarks/sched/testcase.yaml @@ -8,7 +8,7 @@ tests: integration_platforms: - mps2/an385 - qemu_x86 - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv64/smp slow: true harness: console harness_config: diff --git a/tests/drivers/build_all/interrupt_controller/intc_plic/testcase.yaml b/tests/drivers/build_all/interrupt_controller/intc_plic/testcase.yaml index dcfa5d7708bc9..83274da2dadf2 100644 --- a/tests/drivers/build_all/interrupt_controller/intc_plic/testcase.yaml +++ b/tests/drivers/build_all/interrupt_controller/intc_plic/testcase.yaml @@ -2,13 +2,13 @@ common: build_only: true filter: CONFIG_PLIC platform_allow: - - qemu_riscv32 - - qemu_riscv32/qemu_virt_riscv32/smp - - qemu_riscv64 - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32/smp + - qemu_riscv/qemu_virt_riscv/rv64 + - qemu_riscv/qemu_virt_riscv/rv64/smp integration_platforms: - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 tags: - drivers - interrupt diff --git a/tests/drivers/console_switching/boards/qemu_riscv64.overlay b/tests/drivers/console_switching/boards/qemu_riscv_qemu_virt_riscv_rv64.overlay similarity index 100% rename from tests/drivers/console_switching/boards/qemu_riscv64.overlay rename to tests/drivers/console_switching/boards/qemu_riscv_qemu_virt_riscv_rv64.overlay diff --git a/tests/drivers/console_switching/testcase.yaml b/tests/drivers/console_switching/testcase.yaml index 99189c19dd1a8..20951b0b318c9 100644 --- a/tests/drivers/console_switching/testcase.yaml +++ b/tests/drivers/console_switching/testcase.yaml @@ -5,9 +5,9 @@ common: - emul - devmux platform_allow: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tests: drivers.devmux.console_switching: {} diff --git a/tests/drivers/coredump/coredump_api/boards/qemu_riscv32.overlay b/tests/drivers/coredump/coredump_api/boards/qemu_riscv_qemu_virt_riscv_rv32.overlay similarity index 100% rename from tests/drivers/coredump/coredump_api/boards/qemu_riscv32.overlay rename to tests/drivers/coredump/coredump_api/boards/qemu_riscv_qemu_virt_riscv_rv32.overlay diff --git a/tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay b/tests/drivers/coredump/coredump_api/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.overlay similarity index 66% rename from tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay rename to tests/drivers/coredump/coredump_api/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.overlay index ce40ceadeb881..639d39c4c8082 100644 --- a/tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay +++ b/tests/drivers/coredump/coredump_api/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.overlay @@ -3,4 +3,4 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "qemu_riscv32.overlay" +#include "qemu_riscv_qemu_virt_riscv_rv32.overlay" diff --git a/tests/drivers/coredump/coredump_api/src/main.c b/tests/drivers/coredump/coredump_api/src/main.c index 66797add42b28..a85863c4bd50c 100644 --- a/tests/drivers/coredump/coredump_api/src/main.c +++ b/tests/drivers/coredump/coredump_api/src/main.c @@ -12,7 +12,7 @@ #define TEST_MEMORY_VALUE_1 0xcdcdcdcd #define TEST_MEMORY_VALUE_2 0xefefefef -#if defined(CONFIG_BOARD_QEMU_RISCV32) +#if defined(CONFIG_BOARD_QEMU_RISCV_QEMU_VIRT_RISCV_RV32) #define TEST_MEMORY_VALUE_3 0x12121212 #define TEST_MEMORY_VALUE_4 0x34343434 #define TEST_MEMORY_VALUE_5 0x56565656 @@ -58,7 +58,7 @@ static void test_coredump_callback(uintptr_t dump_area, size_t dump_area_size) static void *coredump_tests_suite_setup(void) { -#if defined(CONFIG_BOARD_QEMU_RISCV32) +#if defined(CONFIG_BOARD_QEMU_RISCV_QEMU_VIRT_RISCV_RV32) /* Get addresses of memory regions specified in device tree to fill with test data */ uint32_t *mem0 = (uint32_t *)DT_PROP_BY_IDX(DT_NODELABEL(coredump_device0), memory_regions, 0); diff --git a/tests/drivers/coredump/coredump_api/testcase.yaml b/tests/drivers/coredump/coredump_api/testcase.yaml index bece8efb2b26c..100c9b67bb304 100644 --- a/tests/drivers/coredump/coredump_api/testcase.yaml +++ b/tests/drivers/coredump/coredump_api/testcase.yaml @@ -9,7 +9,7 @@ common: tests: debug.coredump.drivers.api.qemu_riscv32: filter: CONFIG_ARCH_SUPPORTS_COREDUMP - platform_allow: qemu_riscv32 + platform_allow: qemu_riscv/qemu_virt_riscv/rv32 harness: console harness_config: type: multi_line @@ -32,7 +32,7 @@ tests: - "E: #CD:END#" debug.coredump.drivers.api: filter: CONFIG_ARCH_SUPPORTS_COREDUMP - platform_exclude: qemu_riscv32 + platform_exclude: qemu_riscv/qemu_virt_riscv/rv32 arch_exclude: - posix harness: console diff --git a/tests/drivers/interrupt_controller/intc_plic/src/main.c b/tests/drivers/interrupt_controller/intc_plic/src/main.c index de22642e787b8..16c29b5ff967c 100644 --- a/tests/drivers/interrupt_controller/intc_plic/src/main.c +++ b/tests/drivers/interrupt_controller/intc_plic/src/main.c @@ -35,7 +35,7 @@ ZTEST(intc_plic, test_hart_context_mapping) extern const uint32_t plic_hart_contexts_0[]; if (!IS_ENABLED(CONFIG_TEST_INTC_PLIC_ALT_MAPPING)) { - /* Based on the default qemu_riscv64 devicetree */ + /* Based on the default qemu_riscv/qemu_virt_riscv/rv64 devicetree */ zassert_equal(plic_hart_contexts_0[0], 0); zassert_equal(plic_hart_contexts_0[1], 2); zassert_equal(plic_hart_contexts_0[2], 4); diff --git a/tests/drivers/interrupt_controller/intc_plic/testcase.yaml b/tests/drivers/interrupt_controller/intc_plic/testcase.yaml index a798cd76f8fa7..9e02a3ccbd77f 100644 --- a/tests/drivers/interrupt_controller/intc_plic/testcase.yaml +++ b/tests/drivers/interrupt_controller/intc_plic/testcase.yaml @@ -1,5 +1,5 @@ common: - platform_allow: qemu_riscv64 + platform_allow: qemu_riscv/qemu_virt_riscv/rv64 tags: - drivers - interrupt diff --git a/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml b/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml index 18c6ee7326862..6da4c27ad38b9 100644 --- a/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml +++ b/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml @@ -8,11 +8,11 @@ common: filter: CONFIG_MULTI_LEVEL_INTERRUPTS platform_allow: - m2gl025_miv/miv - - qemu_riscv32/qemu_virt_riscv32 - - qemu_riscv32/qemu_virt_riscv32/smp - - qemu_riscv64/qemu_virt_riscv64 - - qemu_riscv64/qemu_virt_riscv64/smp - - qemu_riscv32e/qemu_virt_riscv32e + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32/smp + - qemu_riscv/qemu_virt_riscv/rv64 + - qemu_riscv/qemu_virt_riscv/rv64/smp + - qemu_riscv/qemu_virt_riscv/rv32e tests: interrupt_controller.intc_multi_level_backend.default: {} interrupt_controller.intc_multi_level_backend.no_assert: diff --git a/tests/drivers/uart/uart_async_rx/testcase.yaml b/tests/drivers/uart/uart_async_rx/testcase.yaml index 2f59b90c851eb..d368e764de069 100644 --- a/tests/drivers/uart/uart_async_rx/testcase.yaml +++ b/tests/drivers/uart/uart_async_rx/testcase.yaml @@ -14,7 +14,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - qemu_x86_64 - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv32 integration_platforms: - qemu_x86 extra_configs: diff --git a/tests/kernel/fatal/no-multithreading/testcase.yaml b/tests/kernel/fatal/no-multithreading/testcase.yaml index ef0b24a79f5fb..acfdd22c30192 100644 --- a/tests/kernel/fatal/no-multithreading/testcase.yaml +++ b/tests/kernel/fatal/no-multithreading/testcase.yaml @@ -4,9 +4,9 @@ common: - qemu_arc/qemu_arc_em - qemu_arc/qemu_arc_hs - qemu_arc/qemu_arc_hs6x - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 - nsim/nsim_em - nsim/nsim_em7d_v22 - nsim/nsim_hs diff --git a/tests/kernel/mem_slab/mslab_api/testcase.yaml b/tests/kernel/mem_slab/mslab_api/testcase.yaml index 40021091d0126..0f653cce63cc8 100644 --- a/tests/kernel/mem_slab/mslab_api/testcase.yaml +++ b/tests/kernel/mem_slab/mslab_api/testcase.yaml @@ -19,9 +19,9 @@ tests: - qemu_arc/qemu_arc_em - qemu_arc/qemu_arc_hs - qemu_arc/qemu_arc_hs6x - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_leon3 integration_platforms: - qemu_cortex_m3 diff --git a/tests/kernel/smp/testcase.yaml b/tests/kernel/smp/testcase.yaml index 4cf799373cd38..89b1da2ea5eaa 100644 --- a/tests/kernel/smp/testcase.yaml +++ b/tests/kernel/smp/testcase.yaml @@ -32,8 +32,8 @@ tests: ignore_faults: true filter: (CONFIG_MP_MAX_NUM_CPUS > 1) platform_exclude: - - qemu_riscv64/qemu_virt_riscv64/smp # qemu_riscv64 doesn't support custom ROM offset - - qemu_riscv32/qemu_virt_riscv32/smp # qemu_riscv32 doesn't support custom ROM offset + - qemu_riscv/qemu_virt_riscv/rv64/smp # qemu_riscv64 doesn't support custom ROM offset + - qemu_riscv/qemu_virt_riscv/rv32/smp # qemu_riscv32 doesn't support custom ROM offset extra_configs: - CONFIG_SCHED_CPU_MASK=y - CONFIG_ROM_START_OFFSET=0x80 diff --git a/tests/kernel/threads/dynamic_thread_stack/testcase.yaml b/tests/kernel/threads/dynamic_thread_stack/testcase.yaml index 85516540630a3..d9df33acf32f2 100644 --- a/tests/kernel/threads/dynamic_thread_stack/testcase.yaml +++ b/tests/kernel/threads/dynamic_thread_stack/testcase.yaml @@ -10,10 +10,10 @@ common: - qemu_cortex_a53 - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_cortex_m3 - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 + - qemu_riscv/qemu_virt_riscv/rv64/smp # Permutations of (pool | alloc | user) tests: diff --git a/tests/kernel/threads/no-multithreading/testcase.yaml b/tests/kernel/threads/no-multithreading/testcase.yaml index 93f7757c86152..695da4abb3217 100644 --- a/tests/kernel/threads/no-multithreading/testcase.yaml +++ b/tests/kernel/threads/no-multithreading/testcase.yaml @@ -20,9 +20,9 @@ tests: - qemu_arc/qemu_arc_em - qemu_arc/qemu_arc_hs - qemu_arc/qemu_arc_hs6x - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_leon3 integration_platforms: - qemu_cortex_m0 diff --git a/tests/kernel/timer/cycle64/testcase.yaml b/tests/kernel/timer/cycle64/testcase.yaml index 1598c07337be5..29742792c7a6c 100644 --- a/tests/kernel/timer/cycle64/testcase.yaml +++ b/tests/kernel/timer/cycle64/testcase.yaml @@ -1,6 +1,6 @@ # Note: Re: slow vs fast # -# Some platforms such as native_sim, qemu_riscv32, qemu_riscv64 +# Some platforms such as native_sim and qemu_riscv # complete these tests almost instantaneously because of qemu timer # quirks ("time warp") even though the test reports that it completes # in e.g. 14 s. We can take advantage of that for fast tests on each PR diff --git a/tests/lib/devicetree/api/testcase.yaml b/tests/lib/devicetree/api/testcase.yaml index ded886833ac87..4e6b8ce5c1fba 100644 --- a/tests/lib/devicetree/api/testcase.yaml +++ b/tests/lib/devicetree/api/testcase.yaml @@ -8,6 +8,6 @@ tests: - qemu_x86 - qemu_x86_64 - qemu_cortex_m3 - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv32 integration_platforms: - native_sim diff --git a/tests/lib/mpsc_pbuf/testcase.yaml b/tests/lib/mpsc_pbuf/testcase.yaml index 9c2d8c107460b..753516c668cb0 100644 --- a/tests/lib/mpsc_pbuf/testcase.yaml +++ b/tests/lib/mpsc_pbuf/testcase.yaml @@ -9,8 +9,8 @@ tests: - qemu_cortex_m3 - qemu_cortex_r5 - qemu_leon3 - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_x86 - qemu_x86_64 - qemu_xtensa/dc233c diff --git a/tests/lib/multi_heap/testcase.yaml b/tests/lib/multi_heap/testcase.yaml index f327881614f19..4e46813c4946e 100644 --- a/tests/lib/multi_heap/testcase.yaml +++ b/tests/lib/multi_heap/testcase.yaml @@ -19,9 +19,9 @@ tests: - qemu_arc/qemu_arc_em - qemu_arc/qemu_arc_hs - qemu_arc/qemu_arc_hs6x - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_leon3 integration_platforms: - qemu_cortex_m3 diff --git a/tests/modules/thrift/ThriftTest/testcase.yaml b/tests/modules/thrift/ThriftTest/testcase.yaml index f5d71ff961cd6..a1a64c0831c16 100644 --- a/tests/modules/thrift/ThriftTest/testcase.yaml +++ b/tests/modules/thrift/ThriftTest/testcase.yaml @@ -11,11 +11,11 @@ common: platform_allow: - mps2/an385 - qemu_cortex_a53 - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_x86_64 integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tests: thrift.ThriftTest.binaryProtocol: {} thrift.ThriftTest.compactProtocol: diff --git a/tests/net/pm/testcase.yaml b/tests/net/pm/testcase.yaml index 142200eac9d28..c80dd48b6585d 100644 --- a/tests/net/pm/testcase.yaml +++ b/tests/net/pm/testcase.yaml @@ -4,8 +4,8 @@ common: platform_allow: - qemu_x86 - qemu_leon3 - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 integration_platforms: - qemu_x86 depends_on: netif diff --git a/tests/posix/clock_selection/testcase.yaml b/tests/posix/clock_selection/testcase.yaml index e58bdfdf42638..2da1738d61498 100644 --- a/tests/posix/clock_selection/testcase.yaml +++ b/tests/posix/clock_selection/testcase.yaml @@ -8,7 +8,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 min_flash: 64 min_ram: 32 tests: diff --git a/tests/posix/eventfd/testcase.yaml b/tests/posix/eventfd/testcase.yaml index 6646036067c4c..e3ef2aa402ffd 100644 --- a/tests/posix/eventfd/testcase.yaml +++ b/tests/posix/eventfd/testcase.yaml @@ -8,7 +8,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tests: portability.posix.eventfd: {} portability.posix.eventfd.minimal: diff --git a/tests/posix/fs/testcase.yaml b/tests/posix/fs/testcase.yaml index f5fb98269b9a8..455a5709a7758 100644 --- a/tests/posix/fs/testcase.yaml +++ b/tests/posix/fs/testcase.yaml @@ -13,7 +13,7 @@ common: - simulation integration_platforms: - qemu_x86 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tests: portability.posix.fs: {} portability.posix.fs.minimal: diff --git a/tests/posix/multi_process/testcase.yaml b/tests/posix/multi_process/testcase.yaml index c3d77f932d607..8742781be69d5 100644 --- a/tests/posix/multi_process/testcase.yaml +++ b/tests/posix/multi_process/testcase.yaml @@ -8,7 +8,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 min_flash: 64 min_ram: 32 tests: diff --git a/tests/posix/rwlocks/testcase.yaml b/tests/posix/rwlocks/testcase.yaml index 9e31cbc07d07b..2d97eacd05f44 100644 --- a/tests/posix/rwlocks/testcase.yaml +++ b/tests/posix/rwlocks/testcase.yaml @@ -8,7 +8,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 min_flash: 64 min_ram: 32 tests: diff --git a/tests/posix/signals/testcase.yaml b/tests/posix/signals/testcase.yaml index eb2e02bb6ecde..200e03d37025a 100644 --- a/tests/posix/signals/testcase.yaml +++ b/tests/posix/signals/testcase.yaml @@ -18,33 +18,33 @@ common: tests: portability.posix.signals: integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 portability.posix.signals.minimal: integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 extra_configs: - CONFIG_MINIMAL_LIBC=y portability.posix.signals.newlib: integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 filter: TOOLCHAIN_HAS_NEWLIB == 1 extra_configs: - CONFIG_NEWLIB_LIBC=y portability.posix.signals.picolibc: integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 tags: picolibc filter: CONFIG_PICOLIBC_SUPPORTED extra_configs: - CONFIG_PICOLIBC=y portability.posix.signals.strginal_no_desc: integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 extra_configs: - CONFIG_POSIX_SIGNAL_STRING_DESC=n portability.posix.signals.big_nsig: integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 extra_configs: - CONFIG_POSIX_RTSIG_MAX=1024 portability.posix.signals.native: diff --git a/tests/posix/single_process/testcase.yaml b/tests/posix/single_process/testcase.yaml index e4d31eaa3e3c1..9f01ce9daf6f1 100644 --- a/tests/posix/single_process/testcase.yaml +++ b/tests/posix/single_process/testcase.yaml @@ -8,7 +8,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 min_flash: 64 min_ram: 32 tests: diff --git a/tests/posix/xsi_realtime/testcase.yaml b/tests/posix/xsi_realtime/testcase.yaml index c7bf8ff6465f1..2724e5cef42c2 100644 --- a/tests/posix/xsi_realtime/testcase.yaml +++ b/tests/posix/xsi_realtime/testcase.yaml @@ -12,7 +12,7 @@ common: integration_platforms: - qemu_x86 - qemu_cortex_a53 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 platform_exclude: # linker_zephyr_pre0.cmd:140: syntax error (??) - qemu_xtensa/dc233c diff --git a/tests/posix/xsi_streams/testcase.yaml b/tests/posix/xsi_streams/testcase.yaml index 06b40f1c2e8d0..040cb21692970 100644 --- a/tests/posix/xsi_streams/testcase.yaml +++ b/tests/posix/xsi_streams/testcase.yaml @@ -8,7 +8,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 min_flash: 64 min_ram: 32 tests: diff --git a/tests/posix/xsi_system_logging/testcase.yaml b/tests/posix/xsi_system_logging/testcase.yaml index 54d6790ae75b0..46766f0756c78 100644 --- a/tests/posix/xsi_system_logging/testcase.yaml +++ b/tests/posix/xsi_system_logging/testcase.yaml @@ -7,7 +7,7 @@ common: - arch - simulation integration_platforms: - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv64 min_flash: 64 min_ram: 32 tests: diff --git a/tests/subsys/bindesc/definition/testcase.yaml b/tests/subsys/bindesc/definition/testcase.yaml index 3e92b2982f253..7df8f7094da8c 100644 --- a/tests/subsys/bindesc/definition/testcase.yaml +++ b/tests/subsys/bindesc/definition/testcase.yaml @@ -16,9 +16,9 @@ tests: - qemu_arc/qemu_arc_hs - qemu_arc/qemu_arc_hs5x - qemu_arc/qemu_arc_hs6x - - qemu_riscv32 - - qemu_riscv32e - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv64 bindesc.define.c99: extra_configs: - CONFIG_STD_C99=y diff --git a/tests/subsys/debug/coredump/testcase.yaml b/tests/subsys/debug/coredump/testcase.yaml index 673382bf455cb..3ce81b83dc891 100644 --- a/tests/subsys/debug/coredump/testcase.yaml +++ b/tests/subsys/debug/coredump/testcase.yaml @@ -32,8 +32,8 @@ tests: integration_platforms: - qemu_x86 platform_allow: - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_x86 - qemu_x86_64 - qemu_xtensa/dc233c/mmu diff --git a/tests/subsys/debug/symtab/testcase.yaml b/tests/subsys/debug/symtab/testcase.yaml index 43d4c54a2e4af..c132f262955f9 100644 --- a/tests/subsys/debug/symtab/testcase.yaml +++ b/tests/subsys/debug/symtab/testcase.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: Apache-2.0 common: platform_allow: - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_cortex_a53 - qemu_cortex_m3 - qemu_xtensa/dc233c diff --git a/tests/subsys/debug/thread_analyzer/testcase.yaml b/tests/subsys/debug/thread_analyzer/testcase.yaml index 9ae49081889cd..cc6767f175a69 100644 --- a/tests/subsys/debug/thread_analyzer/testcase.yaml +++ b/tests/subsys/debug/thread_analyzer/testcase.yaml @@ -9,8 +9,8 @@ common: - qemu_cortex_a53 - qemu_x86 - qemu_x86_64 - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_xtensa/dc233c/mmu extra_configs: - CONFIG_QEMU_ICOUNT=n diff --git a/tests/subsys/fs/fat_fs_dual_drive/testcase.yaml b/tests/subsys/fs/fat_fs_dual_drive/testcase.yaml index 7b32bcc125638..773309cdde915 100644 --- a/tests/subsys/fs/fat_fs_dual_drive/testcase.yaml +++ b/tests/subsys/fs/fat_fs_dual_drive/testcase.yaml @@ -4,8 +4,8 @@ tests: - qemu_x86 - native_sim - qemu_leon3 - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 tags: filesystem integration_platforms: - native_sim diff --git a/tests/subsys/logging/dictionary/testcase.yaml b/tests/subsys/logging/dictionary/testcase.yaml index e47890624d87b..b5ce390e42d95 100644 --- a/tests/subsys/logging/dictionary/testcase.yaml +++ b/tests/subsys/logging/dictionary/testcase.yaml @@ -5,8 +5,8 @@ common: platform_allow: - mps2/an385 - qemu_cortex_a53 - - qemu_riscv32 - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv64 - qemu_x86 - qemu_x86_64 integration_platforms: diff --git a/tests/subsys/logging/log_blocking/src/main.c b/tests/subsys/logging/log_blocking/src/main.c index 8ce30a5c5f5d0..55d35d4f9569e 100644 --- a/tests/subsys/logging/log_blocking/src/main.c +++ b/tests/subsys/logging/log_blocking/src/main.c @@ -177,12 +177,12 @@ ZTEST(log_blocking, test_blocking) * This is a workaround for a possible bug in the testing subsys: * - comment-out ztest_test_fail() below * - run with: - * west build -p auto -b qemu_riscv64 -t run \ + * west build -p auto -b qemu_riscv/qemu_virt_riscv/rv64 -t run \ * -T tests/subsys/logging/log_blocking/logging.blocking.rate.stalled * - observe "Assertion failed at..." * - technically, testsuite should pass. Since ZTEST_EXPECT_FAIL() is set. Never gets there. * - run with: - * twister -i -p qemu_riscv64 -T tests/subsys/logging/log_blocking/ + * twister -i -p qemu_riscv/qemu_virt_riscv/rv64 -T tests/subsys/logging/log_blocking/ * - observe "..FAILED : Timeout" * - possible conclusions: * - test thread has not properly longjumped? diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv_qemu_virt_riscv_rv64.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv_qemu_virt_riscv_rv64.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml index 67002bdf91492..81758a11c25e0 100644 --- a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml @@ -9,8 +9,8 @@ tests: - qemu_cortex_m3 - native_sim - native_sim/native/64 - - qemu_riscv32/qemu_virt_riscv32/smp - - qemu_riscv64 + - qemu_riscv/qemu_virt_riscv/rv32/smp + - qemu_riscv/qemu_virt_riscv/rv64 integration_platforms: - native_sim tags: diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv_qemu_virt_riscv_rv64.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv_qemu_virt_riscv_rv64.conf diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64.overlay b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64.overlay similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64.overlay rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64.overlay diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.overlay b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.overlay similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.overlay rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.overlay diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml index a2708f3040298..e794d079767ce 100644 --- a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml @@ -10,8 +10,8 @@ common: platform_allow: - native_sim - qemu_cortex_m0 - - qemu_riscv64 - - qemu_riscv64/qemu_virt_riscv64/smp + - qemu_riscv/qemu_virt_riscv/rv64 + - qemu_riscv/qemu_virt_riscv/rv64/smp - qemu_malta - qemu_arc/qemu_arc_hs6x - qemu_leon3 diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv_qemu_virt_riscv_rv64.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv_qemu_virt_riscv_rv64.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv_qemu_virt_riscv_rv64.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv_qemu_virt_riscv_rv64.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml b/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml index b6a71d596ba9f..2f433bcdef7f0 100644 --- a/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml @@ -32,11 +32,11 @@ tests: platform_exclude: - qemu_cortex_a9 - qemu_x86 - - qemu_riscv64/qemu_virt_riscv64/smp - - qemu_riscv64 - - qemu_riscv32e - - qemu_riscv32 - - qemu_riscv32/qemu_virt_riscv32/smp + - qemu_riscv/qemu_virt_riscv/rv64/smp + - qemu_riscv/qemu_virt_riscv/rv64 + - qemu_riscv/qemu_virt_riscv/rv32e + - qemu_riscv/qemu_virt_riscv/rv32 + - qemu_riscv/qemu_virt_riscv/rv32/smp - qemu_cortex_m3 - mps2/an385 extra_configs: diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv_qemu_virt_riscv_rv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv_qemu_virt_riscv_rv64.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv_qemu_virt_riscv_rv64.conf diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv_qemu_virt_riscv_rv64_smp.conf diff --git a/tests/subsys/shell/shell_backend/testcase.yaml b/tests/subsys/shell/shell_backend/testcase.yaml index eb9e9d2a314d4..eaf86ce512775 100644 --- a/tests/subsys/shell/shell_backend/testcase.yaml +++ b/tests/subsys/shell/shell_backend/testcase.yaml @@ -7,4 +7,4 @@ tests: filter: ( CONFIG_SHELL ) platform_allow: - qemu_x86 - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv32 diff --git a/tests/subsys/shell/shell_backend_uart/testcase.yaml b/tests/subsys/shell/shell_backend_uart/testcase.yaml index 64a9323ce4d45..be1ee86db300c 100644 --- a/tests/subsys/shell/shell_backend_uart/testcase.yaml +++ b/tests/subsys/shell/shell_backend_uart/testcase.yaml @@ -8,4 +8,4 @@ tests: - uart platform_allow: - qemu_x86 - - qemu_riscv32 + - qemu_riscv/qemu_virt_riscv/rv32