zephyrproject-rtos · maass-hamburg · Oct 14, 2025 · Oct 14, 2025 · Oct 14, 2025 · Oct 14, 2025
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
@@ -13,8 +13,11 @@ config FLOAT_HARD
 	bool "Hard-float calling convention"
 	default y
 	depends on FPU
+	depends on !RISCV_ISA_RV32E
+	depends on RISCV_ISA_EXT_F
 	help
 	  This option enables the hard-float calling convention.
+	  Adds eight floating-point argument registers.
 
 choice RISCV_GP_PURPOSE
 	prompt "Purpose of the global pointer (GP) register"

diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa
@@ -1,29 +1,37 @@
 # Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
 # SPDX-License-Identifier: Apache-2.0
 
+RISCV_ISA_BASE_PROP := riscv,isa-base
+RISCV_ISA_EXT_PROP  := riscv,isa-extensions
+
 config RISCV_ISA_RV32I
 	bool
+	default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv32i)
 	help
 	  RV32I Base Integer Instruction Set - 32bit
 
 config RISCV_ISA_RV32E
 	bool
+	default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv32e)
 	help
 	  RV32E Base Integer Instruction Set (Embedded) - 32bit
 
 config RISCV_ISA_RV64I
 	bool
+	default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv64i)
 	select 64BIT
 	help
 	  RV64I Base Integer Instruction Set - 64bit
 
 config RISCV_ISA_RV128I
 	bool
+	default y if $(dt_node_str_prop_equals,/cpus/cpu@0,$(RISCV_ISA_BASE_PROP),rv128i)
 	help
 	  RV128I Base Integer Instruction Set - 128bit
 
 config RISCV_ISA_EXT_M
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),m)
 	help
 	  (M) - Standard Extension for Integer Multiplication and Division
 
@@ -33,6 +41,7 @@ config RISCV_ISA_EXT_M
 
 config RISCV_ISA_EXT_A
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),a)
 	imply RISCV_ISA_EXT_ZAAMO
 	imply RISCV_ISA_EXT_ZALRSC
 	help
@@ -45,6 +54,7 @@ config RISCV_ISA_EXT_A
 
 config RISCV_ISA_EXT_F
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),f)
 	select CPU_HAS_FPU
 	help
 	  (F) - Standard Extension for Single-Precision Floating-Point
@@ -56,6 +66,7 @@ config RISCV_ISA_EXT_F
 
 config RISCV_ISA_EXT_D
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),d)
 	depends on RISCV_ISA_EXT_F
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	help
@@ -68,6 +79,7 @@ config RISCV_ISA_EXT_D
 
 config RISCV_ISA_EXT_G
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),g)
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_F
@@ -79,6 +91,7 @@ config RISCV_ISA_EXT_G
 
 config RISCV_ISA_EXT_Q
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),q)
 	depends on RISCV_ISA_RV64I
 	depends on RISCV_ISA_EXT_F
 	depends on RISCV_ISA_EXT_D
@@ -91,6 +104,7 @@ config RISCV_ISA_EXT_Q
 
 config RISCV_ISA_EXT_C
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),c)
 	select RISCV_ISA_EXT_ZCA
 	select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D
 	select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E)
@@ -103,6 +117,7 @@ config RISCV_ISA_EXT_C
 
 config RISCV_ISA_EXT_ZICNTR
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zicntr)
 	depends on RISCV_ISA_EXT_ZICSR
 	help
 	  (Zicntr) - Standard Extension for Base Counters and Timers
@@ -113,6 +128,7 @@ config RISCV_ISA_EXT_ZICNTR
 
 config RISCV_ISA_EXT_ZICSR
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zicsr)
 	help
 	  (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions
 
@@ -121,6 +137,7 @@ config RISCV_ISA_EXT_ZICSR
 
 config RISCV_ISA_EXT_ZIFENCEI
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zifencei)
 	help
 	  (Zifencei) - Standard Extension for Instruction-Fetch Fence
 
@@ -130,20 +147,23 @@ config RISCV_ISA_EXT_ZIFENCEI
 
 config RISCV_ISA_EXT_ZAAMO
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zaamo)
 	help
 	  (Zaamo) - Atomic memory operation subset of the A extension
 
 	  The Zaamo extension enables support for AMO*.W/D-style instructions.
 
 config RISCV_ISA_EXT_ZALRSC
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zalrsc)
 	help
 	  (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension
 
 	  The Zalrsc extension enables support for LR.W/D and SC.W/D-style instructions.
 
 config RISCV_ISA_EXT_ZCA
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zca)
 	help
 	  (Zca) - Zba Extension for Compressed Instructions
 
@@ -152,6 +172,7 @@ config RISCV_ISA_EXT_ZCA
 
 config RISCV_ISA_EXT_ZCB
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcb)
 	depends on RISCV_ISA_EXT_ZCA
 	help
 	  (Zcb) - Zcb Extension for Simple Compressed Instructions
@@ -161,6 +182,7 @@ config RISCV_ISA_EXT_ZCB
 
 config RISCV_ISA_EXT_ZCD
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcd)
 	depends on RISCV_ISA_EXT_D
 	depends on RISCV_ISA_EXT_ZCA
 	help
@@ -171,6 +193,7 @@ config RISCV_ISA_EXT_ZCD
 
 config RISCV_ISA_EXT_ZCF
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcf)
 	depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E
 	depends on RISCV_ISA_EXT_F
 	depends on RISCV_ISA_EXT_ZCA
@@ -182,6 +205,7 @@ config RISCV_ISA_EXT_ZCF
 
 config RISCV_ISA_EXT_ZCMP
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcmp)
 	depends on RISCV_ISA_EXT_ZCA
 	depends on !RISCV_ISA_EXT_ZCD
 	help
@@ -192,6 +216,7 @@ config RISCV_ISA_EXT_ZCMP
 
 config RISCV_ISA_EXT_ZCMT
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zcmt)
 	depends on RISCV_ISA_EXT_ZICSR
 	depends on RISCV_ISA_EXT_ZCA
 	depends on !RISCV_ISA_EXT_ZCD
@@ -203,6 +228,7 @@ config RISCV_ISA_EXT_ZCMT
 
 config RISCV_ISA_EXT_ZBA
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zba)
 	help
 	  (Zba) - Zba BitManip Extension
 
@@ -213,6 +239,7 @@ config RISCV_ISA_EXT_ZBA
 
 config RISCV_ISA_EXT_ZBB
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbb)
 	help
 	  (Zbb) - Zbb BitManip Extension (Basic bit-manipulation)
 
@@ -222,6 +249,7 @@ config RISCV_ISA_EXT_ZBB
 
 config RISCV_ISA_EXT_ZBC
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbc)
 	help
 	  (Zbc) - Zbc BitManip Extension (Carry-less multiplication)
 
@@ -230,6 +258,7 @@ config RISCV_ISA_EXT_ZBC
 
 config RISCV_ISA_EXT_ZBS
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zbs)
 	help
 	  (Zbs) - Zbs BitManip Extension (Single-bit instructions)
 
@@ -239,6 +268,7 @@ config RISCV_ISA_EXT_ZBS
 
 config RISCV_ISA_EXT_ZMMUL
 	bool
+	default y if $(dt_node_array_prop_has_val,/cpus/cpu@0,$(RISCV_ISA_EXT_PROP),zmmul)
 	help
 	  (Zmmul) - Zmmul Extension for Integer Multiplication
 

diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake
@@ -70,3 +70,18 @@ set(scobc_module1_DEPRECATED
 set(raytac_an54l15q_db/nrf54l15/cpuapp_DEPRECATED
     raytac_an54lq_db_15/nrf54l15/cpuapp
 )
+set(qemu_riscv32_DEPRECATED
+    qemu_riscv/qemu_virt_riscv/rv32
+)
+set(qemu_riscv32/qemu_virt_riscv32/smp_DEPRECATED
+    qemu_riscv/qemu_virt_riscv/rv32/smp
+)
+set(qemu_riscv32e_DEPRECATED
+    qemu_riscv/qemu_virt_riscv/rv32e
+)
+set(qemu_riscv64_DEPRECATED
+    qemu_riscv/qemu_virt_riscv/rv64
+)
+set(qemu_riscv64/qemu_virt_riscv64/smp_DEPRECATED
+    qemu_riscv/qemu_virt_riscv/rv64/smp
+)
diff --git a/boards/qemu/riscv/Kconfig b/boards/qemu/riscv/Kconfig
@@ -0,0 +1,6 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV
+	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
diff --git a/boards/qemu/riscv/Kconfig.defconfig b/boards/qemu/riscv/Kconfig.defconfig
@@ -0,0 +1,16 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_QEMU_RISCV
+
+# Use thread local storage by default so that this feature gets more CI coverage.
+configdefault THREAD_LOCAL_STORAGE
+	default y
+
+configdefault BUILD_OUTPUT_BIN
+	default n
+
+configdefault QEMU_ICOUNT_SHIFT
+	default 6
+
+endif # BOARD_QEMU_RISCV
diff --git a/boards/qemu/riscv/Kconfig.qemu_riscv b/boards/qemu/riscv/Kconfig.qemu_riscv
@@ -0,0 +1,5 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QEMU_RISCV
+	select SOC_QEMU_VIRT_RISCV
diff --git a/boards/qemu/riscv/board.cmake b/boards/qemu/riscv/board.cmake
@@ -0,0 +1,37 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS qemu)
+
+set(riscv_isa_extensions)
+set(riscv_isa_base)
+dt_prop(riscv_isa_extensions PATH "/cpus/cpu@0" PROPERTY "riscv,isa-extensions" REQUIRED)
+dt_prop(riscv_isa_base PATH "/cpus/cpu@0" PROPERTY "riscv,isa-base" REQUIRED)
+
+set(qemu_riscv_cpu "${riscv_isa_base}")
+foreach(ext IN LISTS riscv_isa_extensions)
+  if(ext)
+    string(APPEND qemu_riscv_cpu ",${ext}=on")
+  endif()
+endforeach()
+
+if(CONFIG_RISCV_PMP)
+  string(APPEND qemu_riscv_cpu ",pmp=on,u=on")
+endif()
+
+if(CONFIG_64BIT)
+  set(QEMU_binary_suffix riscv64)
+else()
+  set(QEMU_binary_suffix riscv32)
+endif()
+
+set(QEMU_CPU_TYPE_${ARCH} "${qemu_riscv_cpu}")
+
+set(QEMU_FLAGS_${ARCH}
+  -nographic
+  -machine virt
+  -bios none
+  -m 256
+  -cpu ${qemu_riscv_cpu}
+  )
+board_set_debugger_ifnset(qemu)
diff --git a/boards/qemu/riscv/board.yml b/boards/qemu/riscv/board.yml
@@ -0,0 +1,11 @@
+board:
+  name: qemu_riscv
+  full_name: QEMU Emulation for RISCV
+  vendor: qemu
+  socs:
+    - name: qemu_virt_riscv
+      variants:
+        - name: smp
+          cpucluster: rv32
+        - name: smp
+          cpucluster: rv64