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Update (2023.07.11)
31106: sun/net/InetAddress/nameservice/simple/DefaultCaching.java fail with -Xcomp 29329: LA port of 8295257: Remove implicit noreg temp register arguments in aarch64 MacroAssembler 29198: LA port of 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at 31364: [LoongArch64] zero build failed after openjdk#25064 28984: 8309778: java/nio/file/Files/CopyAndMove.java fails when using second test directory
1 parent 4d10bd7 commit 3906467

20 files changed

+153
-164
lines changed

‎src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp‎

Lines changed: 44 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -101,12 +101,12 @@ void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* mas
101101
}
102102

103103
void G1BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
104-
Register dst, Address src, Register tmp1, Register tmp_thread) {
104+
Register dst, Address src, Register tmp1, Register tmp2) {
105105
bool on_oop = is_reference_type(type);
106106
bool on_weak = (decorators & ON_WEAK_OOP_REF) != 0;
107107
bool on_phantom = (decorators & ON_PHANTOM_OOP_REF) != 0;
108108
bool on_reference = on_weak || on_phantom;
109-
ModRefBarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread);
109+
ModRefBarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp2);
110110
if (on_oop && on_reference) {
111111
// RA is live. It must be saved around calls.
112112
__ enter(); // barrier may call runtime
@@ -116,7 +116,8 @@ void G1BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorator
116116
noreg /* obj */,
117117
dst /* pre_val */,
118118
TREG /* thread */,
119-
tmp1 /* tmp */,
119+
tmp1 /* tmp1 */,
120+
tmp2 /* tmp2 */,
120121
true /* tosca_live */,
121122
true /* expand_call */);
122123
__ leave();
@@ -127,7 +128,8 @@ void G1BarrierSetAssembler::g1_write_barrier_pre(MacroAssembler* masm,
127128
Register obj,
128129
Register pre_val,
129130
Register thread,
130-
Register tmp,
131+
Register tmp1,
132+
Register tmp2,
131133
bool tosca_live,
132134
bool expand_call) {
133135
// If expand_call is true then we expand the call_VM_leaf macro
@@ -139,29 +141,25 @@ void G1BarrierSetAssembler::g1_write_barrier_pre(MacroAssembler* masm,
139141
Label done;
140142
Label runtime;
141143

142-
assert(pre_val != noreg, "check this code");
143-
144-
if (obj != noreg) {
145-
assert_different_registers(obj, pre_val, tmp);
146-
assert(pre_val != V0, "check this code");
147-
}
144+
assert_different_registers(obj, pre_val, tmp1, tmp2);
145+
assert(pre_val != noreg && tmp1 != noreg && tmp2 != noreg, "expecting a register");
148146

149147
Address in_progress(thread, in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset()));
150148
Address index(thread, in_bytes(G1ThreadLocalData::satb_mark_queue_index_offset()));
151149
Address buffer(thread, in_bytes(G1ThreadLocalData::satb_mark_queue_buffer_offset()));
152150

153151
// Is marking active?
154152
if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
155-
__ ld_w(AT, in_progress);
153+
__ ld_w(tmp1, in_progress);
156154
} else {
157155
assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
158-
__ ld_b(AT, in_progress);
156+
__ ld_b(tmp1, in_progress);
159157
}
160-
__ beqz(AT, done);
158+
__ beqz(tmp1, done);
161159

162160
// Do we need to load the previous value?
163161
if (obj != noreg) {
164-
__ load_heap_oop(pre_val, Address(obj, 0), tmp);
162+
__ load_heap_oop(pre_val, Address(obj, 0), noreg, noreg, AS_RAW);
165163
}
166164

167165
// Is the previous value null?
@@ -171,18 +169,19 @@ void G1BarrierSetAssembler::g1_write_barrier_pre(MacroAssembler* masm,
171169
// Is index == 0?
172170
// (The index field is typed as size_t.)
173171

174-
__ ld_d(tmp, index);
175-
__ beqz(tmp, runtime);
172+
__ ld_d(tmp1, index);
173+
__ beqz(tmp1, runtime);
176174

177-
__ addi_d(tmp, tmp, -1 * wordSize);
178-
__ st_d(tmp, index);
179-
__ ld_d(AT, buffer);
175+
__ addi_d(tmp1, tmp1, -1 * wordSize);
176+
__ st_d(tmp1, index);
177+
__ ld_d(tmp2, buffer);
180178

181179
// Record the previous value
182-
__ stx_d(pre_val, tmp, AT);
180+
__ stx_d(pre_val, tmp1, tmp2);
183181
__ b(done);
184182

185183
__ bind(runtime);
184+
186185
__ push_call_clobbered_registers();
187186

188187
// Calling the runtime using the regular call_VM_leaf mechanism generates
@@ -199,8 +198,6 @@ void G1BarrierSetAssembler::g1_write_barrier_pre(MacroAssembler* masm,
199198

200199
if (expand_call) {
201200
assert(pre_val != A1, "smashed arg");
202-
if (thread != A1) __ move(A1, thread);
203-
if (pre_val != A0) __ move(A0, pre_val);
204201
__ super_call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_pre_entry), pre_val, thread);
205202
} else {
206203
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_pre_entry), pre_val, thread);
@@ -215,10 +212,12 @@ void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
215212
Register store_addr,
216213
Register new_val,
217214
Register thread,
218-
Register tmp,
215+
Register tmp1,
219216
Register tmp2) {
220-
assert_different_registers(tmp, tmp2, AT);
221217
assert(thread == TREG, "must be");
218+
assert_different_registers(store_addr, thread, tmp1, tmp2, SCR1);
219+
assert(store_addr != noreg && new_val != noreg && tmp1 != noreg
220+
&& tmp2 != noreg, "expecting a register");
222221

223222
Address queue_index(thread, in_bytes(G1ThreadLocalData::dirty_card_queue_index_offset()));
224223
Address buffer(thread, in_bytes(G1ThreadLocalData::dirty_card_queue_buffer_offset()));
@@ -230,53 +229,49 @@ void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
230229
Label runtime;
231230

232231
// Does store cross heap regions?
233-
__ xorr(AT, store_addr, new_val);
234-
__ srli_d(AT, AT, HeapRegion::LogOfHRGrainBytes);
235-
__ beqz(AT, done);
232+
__ xorr(tmp1, store_addr, new_val);
233+
__ srli_d(tmp1, tmp1, HeapRegion::LogOfHRGrainBytes);
234+
__ beqz(tmp1, done);
236235

237236
// crosses regions, storing null?
238237
__ beqz(new_val, done);
239238

240239
// storing region crossing non-null, is card already dirty?
241-
const Register card_addr = tmp;
242-
const Register cardtable = tmp2;
240+
const Register card_addr = tmp1;
243241

244-
__ move(card_addr, store_addr);
245-
__ srli_d(card_addr, card_addr, CardTable::card_shift());
242+
__ srli_d(card_addr, store_addr, CardTable::card_shift());
246243
// Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
247244
// a valid address and therefore is not properly handled by the relocation code.
248-
__ li(cardtable, (intptr_t)ct->card_table()->byte_map_base());
249-
__ add_d(card_addr, card_addr, cardtable);
245+
__ li(tmp2, (intptr_t)ct->card_table()->byte_map_base());
246+
__ add_d(card_addr, card_addr, tmp2);
250247

251-
__ ld_bu(AT, card_addr, 0);
252-
__ addi_d(AT, AT, -1 * (int)G1CardTable::g1_young_card_val());
253-
__ beqz(AT, done);
248+
__ ld_bu(tmp2, card_addr, 0);
249+
__ addi_d(tmp2, tmp2, -1 * (int)G1CardTable::g1_young_card_val());
250+
__ beqz(tmp2, done);
254251

255252
assert((int)CardTable::dirty_card_val() == 0, "must be 0");
256253

257254
__ membar(__ StoreLoad);
258-
__ ld_bu(AT, card_addr, 0);
259-
__ beqz(AT, done);
255+
__ ld_bu(tmp2, card_addr, 0);
256+
__ beqz(tmp2, done);
260257

261258
// storing a region crossing, non-null oop, card is clean.
262259
// dirty card and log.
263260
__ st_b(R0, card_addr, 0);
264261

265-
__ ld_d(AT, queue_index);
266-
__ beqz(AT, runtime);
267-
__ addi_d(AT, AT, -1 * wordSize);
268-
__ st_d(AT, queue_index);
262+
__ ld_d(SCR1, queue_index);
263+
__ beqz(SCR1, runtime);
264+
__ addi_d(SCR1, SCR1, -1 * wordSize);
265+
__ st_d(SCR1, queue_index);
269266
__ ld_d(tmp2, buffer);
270-
__ ld_d(AT, queue_index);
271-
__ stx_d(card_addr, tmp2, AT);
267+
__ ld_d(SCR1, queue_index);
268+
__ stx_d(card_addr, tmp2, SCR1);
272269
__ b(done);
273270

274271
__ bind(runtime);
275272
// save the live input values
276273
__ push(store_addr);
277-
__ push(new_val);
278274
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_post_entry), card_addr, TREG);
279-
__ pop(new_val);
280275
__ pop(store_addr);
281276

282277
__ bind(done);
@@ -306,7 +301,8 @@ void G1BarrierSetAssembler::oop_store_at(MacroAssembler* masm, DecoratorSet deco
306301
tmp3 /* obj */,
307302
tmp2 /* pre_val */,
308303
TREG /* thread */,
309-
tmp1 /* tmp */,
304+
tmp1 /* tmp1 */,
305+
SCR1 /* tmp2 */,
310306
val != noreg /* tosca_live */,
311307
false /* expand_call */);
312308
}
@@ -327,7 +323,7 @@ void G1BarrierSetAssembler::oop_store_at(MacroAssembler* masm, DecoratorSet deco
327323
tmp3 /* store_adr */,
328324
new_val /* new_val */,
329325
TREG /* thread */,
330-
tmp1 /* tmp */,
326+
tmp1 /* tmp1 */,
331327
tmp2 /* tmp2 */);
332328
}
333329
}

‎src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -43,15 +43,16 @@ class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
4343
Register obj,
4444
Register pre_val,
4545
Register thread,
46-
Register tmp,
46+
Register tmp1,
47+
Register tmp2,
4748
bool tosca_live,
4849
bool expand_call);
4950

5051
void g1_write_barrier_post(MacroAssembler* masm,
5152
Register store_addr,
5253
Register new_val,
5354
Register thread,
54-
Register tmp,
55+
Register tmp1,
5556
Register tmp2);
5657

5758
virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
@@ -65,7 +66,7 @@ class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
6566
void generate_c1_post_barrier_runtime_stub(StubAssembler* sasm);
6667

6768
virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
68-
Register dst, Address src, Register tmp1, Register tmp_thread);
69+
Register dst, Address src, Register tmp1, Register tmp2);
6970
};
7071

7172
#endif // CPU_LOONGARCH_GC_G1_G1BARRIERSETASSEMBLER_LOONGARCH_HPP

‎src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@
3838
#define __ masm->
3939

4040
void BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
41-
Register dst, Address src, Register tmp1, Register tmp_thread) {
41+
Register dst, Address src, Register tmp1, Register tmp2) {
4242
// RA is live. It must be saved around calls.
4343

4444
bool in_heap = (decorators & IN_HEAP) != 0;
@@ -333,7 +333,7 @@ void BarrierSetAssembler::c2i_entry_barrier(MacroAssembler* masm) {
333333
// Is it a weak but alive CLD?
334334
__ push2(T2, T8);
335335
__ ld_d(T8, Address(SCR2, ClassLoaderData::holder_offset()));
336-
__ resolve_weak_handle(T8, T2); // Assembler occupies SCR1.
336+
__ resolve_weak_handle(T8, T2, SCR2); // Assembler occupies SCR1.
337337
__ move(SCR1, T8);
338338
__ pop2(T2, T8);
339339
__ bnez(SCR1, method_live);

‎src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ class BarrierSetAssembler: public CHeapObj<mtGC> {
5454
Register dst, Register count, Register scratch, RegSet saved_regs) {}
5555

5656
virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
57-
Register dst, Address src, Register tmp1, Register tmp_thread);
57+
Register dst, Address src, Register tmp1, Register tmp2);
5858
virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
5959
Address dst, Register val, Register tmp1, Register tmp2, Register tmp3);
6060

‎src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp‎

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -85,15 +85,16 @@ void ShenandoahBarrierSetAssembler::shenandoah_write_barrier_pre(MacroAssembler*
8585
bool tosca_live,
8686
bool expand_call) {
8787
if (ShenandoahSATBBarrier) {
88-
satb_write_barrier_pre(masm, obj, pre_val, thread, tmp, tosca_live, expand_call);
88+
satb_write_barrier_pre(masm, obj, pre_val, thread, tmp, SCR1, tosca_live, expand_call);
8989
}
9090
}
9191

9292
void ShenandoahBarrierSetAssembler::satb_write_barrier_pre(MacroAssembler* masm,
9393
Register obj,
9494
Register pre_val,
9595
Register thread,
96-
Register tmp,
96+
Register tmp1,
97+
Register tmp2,
9798
bool tosca_live,
9899
bool expand_call) {
99100
// If expand_call is true then we expand the call_VM_leaf macro
@@ -105,21 +106,21 @@ void ShenandoahBarrierSetAssembler::satb_write_barrier_pre(MacroAssembler* masm,
105106
Label done;
106107
Label runtime;
107108

108-
assert_different_registers(obj, pre_val, tmp, SCR1);
109-
assert(pre_val != noreg && tmp != noreg, "expecting a register");
109+
assert_different_registers(obj, pre_val, tmp1, tmp2);
110+
assert(pre_val != noreg && tmp1 != noreg && tmp2 != noreg, "expecting a register");
110111

111112
Address in_progress(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_active_offset()));
112113
Address index(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_index_offset()));
113114
Address buffer(thread, in_bytes(ShenandoahThreadLocalData::satb_mark_queue_buffer_offset()));
114115

115116
// Is marking active?
116117
if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
117-
__ ld_w(tmp, in_progress);
118+
__ ld_w(tmp1, in_progress);
118119
} else {
119120
assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
120-
__ ld_b(tmp, in_progress);
121+
__ ld_b(tmp1, in_progress);
121122
}
122-
__ beqz(tmp, done);
123+
__ beqz(tmp1, done);
123124

124125
// Do we need to load the previous value?
125126
if (obj != noreg) {
@@ -133,17 +134,17 @@ void ShenandoahBarrierSetAssembler::satb_write_barrier_pre(MacroAssembler* masm,
133134
// Is index == 0?
134135
// (The index field is typed as size_t.)
135136

136-
__ ld_d(tmp, index); // tmp := *index_adr
137-
__ beqz(tmp, runtime); // tmp == 0?
137+
__ ld_d(tmp1, index); // tmp := *index_adr
138+
__ beqz(tmp1, runtime); // tmp == 0?
138139
// If yes, goto runtime
139140

140-
__ addi_d(tmp, tmp, -wordSize); // tmp := tmp - wordSize
141-
__ st_d(tmp, index); // *index_adr := tmp
142-
__ ld_d(SCR1, buffer);
143-
__ add_d(tmp, tmp, SCR1); // tmp := tmp + *buffer_adr
141+
__ addi_d(tmp1, tmp1, -wordSize); // tmp := tmp - wordSize
142+
__ st_d(tmp1, index); // *index_adr := tmp
143+
__ ld_d(tmp2, buffer);
144+
// tmp := tmp + *buffer_adr
144145

145146
// Record the previous value
146-
__ st_d(pre_val, Address(tmp, 0));
147+
__ stx_d(pre_val, tmp1, tmp2);
147148
__ b(done);
148149

149150
__ bind(runtime);
@@ -317,7 +318,7 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
317318
void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register dst, Register tmp) {
318319
if (ShenandoahIUBarrier) {
319320
__ push_call_clobbered_registers();
320-
satb_write_barrier_pre(masm, noreg, dst, TREG, tmp, true, false);
321+
satb_write_barrier_pre(masm, noreg, dst, TREG, tmp, SCR1, true, false);
321322
__ pop_call_clobbered_registers();
322323
}
323324
}
@@ -338,10 +339,10 @@ void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register ds
338339
// dst: SCR1 (might use SCR1 as temporary output register to avoid clobbering src)
339340
//
340341
void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
341-
Register dst, Address src, Register tmp1, Register tmp_thread) {
342+
Register dst, Address src, Register tmp1, Register tmp2) {
342343
// 1: non-reference load, no additional barrier is needed
343344
if (!is_reference_type(type)) {
344-
BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread);
345+
BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp2);
345346
return;
346347
}
347348

@@ -355,7 +356,7 @@ void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet d
355356
}
356357
assert_different_registers(dst, src.base(), src.index());
357358

358-
BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread);
359+
BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp2);
359360

360361
load_reference_barrier(masm, dst, src, decorators);
361362

@@ -364,7 +365,7 @@ void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet d
364365
dst = result_dst;
365366
}
366367
} else {
367-
BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp_thread);
368+
BarrierSetAssembler::load_at(masm, decorators, type, dst, src, tmp1, tmp2);
368369
}
369370

370371
// 3: apply keep-alive barrier if needed
@@ -375,7 +376,8 @@ void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet d
375376
noreg /* obj */,
376377
dst /* pre_val */,
377378
TREG /* thread */,
378-
tmp1 /* tmp */,
379+
tmp1 /* tmp1 */,
380+
tmp2 /* tmp2 */,
379381
true /* tosca_live */,
380382
true /* expand_call */);
381383
__ pop_call_clobbered_registers();

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