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‎make/autoconf/build-performance.m4

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626
AC_DEFUN([BPERF_CHECK_CORES],
2727
[
2828
AC_MSG_CHECKING([for number of cores])
29-
NUM_CORES=0
3029
3130
if test -f /proc/cpuinfo; then
3231
# Looks like a Linux (or cygwin) system
@@ -38,10 +37,7 @@ AC_DEFUN([BPERF_CHECK_CORES],
3837
# Looks like a MacOSX system
3938
NUM_CORES=`/usr/sbin/sysctl -n hw.ncpu`
4039
elif test "x$OPENJDK_BUILD_OS" = xaix ; then
41-
NUM_LCPU=`lparstat -m 2> /dev/null | $GREP -o "lcpu=[[0-9]]*" | $CUT -d "=" -f 2`
42-
if test -n "$NUM_LCPU"; then
43-
NUM_CORES=$NUM_LCPU
44-
fi
40+
NUM_CORES=`lparstat -m 2> /dev/null | $GREP -o "lcpu=[[0-9]]*" | $CUT -d "=" -f 2`
4541
elif test -n "$NUMBER_OF_PROCESSORS"; then
4642
# On windows, look in the env
4743
NUM_CORES=$NUMBER_OF_PROCESSORS

‎make/conf/jib-profiles.js

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -813,24 +813,6 @@ var getJibProfilesProfiles = function (input, common, data) {
813813
}
814814
});
815815

816-
// Define the reference implementation profiles. These are basically the same
817-
// as the open profiles, but upload artifacts to a different location.
818-
common.main_profile_names.forEach(function (name) {
819-
var riName = name + "-ri";
820-
var riDebugName = riName + common.debug_suffix;
821-
var openName = name + common.open_suffix;
822-
var openDebugName = openName + common.debug_suffix;
823-
profiles[riName] = clone(profiles[openName]);
824-
profiles[riDebugName] = clone(profiles[openDebugName]);
825-
// Rewrite all remote dirs to "bundles/openjdk/BCL/..."
826-
for (artifactName in profiles[riName].artifacts) {
827-
var artifact = profiles[riName].artifacts[artifactName];
828-
artifact.remote = replaceAll(
829-
"\/GPL\/", "/BCL/",
830-
(artifact.remote != null ? artifact.remote : artifact.local));
831-
}
832-
});
833-
834816
// For open profiles, the non-debug jdk bundles, need an "open" prefix on the
835817
// remote bundle names, forming the word "openjdk". See JDK-8188789.
836818
common.main_profile_names.forEach(function (name) {

‎src/hotspot/cpu/aarch64/aarch64.ad

Lines changed: 157 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2301,6 +2301,12 @@ const bool Matcher::match_rule_supported(int opcode) {
23012301
ret_value = false;
23022302
}
23032303
break;
2304+
case Op_ExpandBits:
2305+
case Op_CompressBits:
2306+
if (!(UseSVE > 1 && VM_Version::supports_svebitperm())) {
2307+
ret_value = false;
2308+
}
2309+
break;
23042310
}
23052311

23062312
return ret_value; // Per default match rules are supported.
@@ -17350,6 +17356,157 @@ instruct encode_ascii_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
1735017356
ins_pipe(pipe_class_memory);
1735117357
%}
1735217358

17359+
//----------------------------- CompressBits/ExpandBits ------------------------
17360+
17361+
instruct compressBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
17362+
vRegF tdst, vRegF tsrc, vRegF tmask) %{
17363+
match(Set dst (CompressBits src mask));
17364+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17365+
format %{ "mov $tsrc, $src\n\t"
17366+
"mov $tmask, $mask\n\t"
17367+
"bext $tdst, $tsrc, $tmask\n\t"
17368+
"mov $dst, $tdst"
17369+
%}
17370+
ins_encode %{
17371+
__ mov($tsrc$$FloatRegister, __ S, 0, $src$$Register);
17372+
__ mov($tmask$$FloatRegister, __ S, 0, $mask$$Register);
17373+
__ sve_bext($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17374+
__ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17375+
%}
17376+
ins_pipe(pipe_slow);
17377+
%}
17378+
17379+
instruct compressBitsI_memcon(iRegINoSp dst, memory4 mem, immI mask,
17380+
vRegF tdst, vRegF tsrc, vRegF tmask) %{
17381+
match(Set dst (CompressBits (LoadI mem) mask));
17382+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17383+
format %{ "ldrs $tsrc, $mem\n\t"
17384+
"ldrs $tmask, $mask\n\t"
17385+
"bext $tdst, $tsrc, $tmask\n\t"
17386+
"mov $dst, $tdst"
17387+
%}
17388+
ins_encode %{
17389+
loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrs, $tsrc$$FloatRegister, $mem->opcode(),
17390+
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
17391+
__ ldrs($tmask$$FloatRegister, $constantaddress($mask));
17392+
__ sve_bext($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17393+
__ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17394+
%}
17395+
ins_pipe(pipe_slow);
17396+
%}
17397+
17398+
instruct compressBitsL_reg(iRegLNoSp dst, iRegL src, iRegL mask,
17399+
vRegD tdst, vRegD tsrc, vRegD tmask) %{
17400+
match(Set dst (CompressBits src mask));
17401+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17402+
format %{ "mov $tsrc, $src\n\t"
17403+
"mov $tmask, $mask\n\t"
17404+
"bext $tdst, $tsrc, $tmask\n\t"
17405+
"mov $dst, $tdst"
17406+
%}
17407+
ins_encode %{
17408+
__ mov($tsrc$$FloatRegister, __ D, 0, $src$$Register);
17409+
__ mov($tmask$$FloatRegister, __ D, 0, $mask$$Register);
17410+
__ sve_bext($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17411+
__ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17412+
%}
17413+
ins_pipe(pipe_slow);
17414+
%}
17415+
17416+
instruct compressBitsL_memcon(iRegLNoSp dst, memory8 mem, immL mask,
17417+
vRegF tdst, vRegF tsrc, vRegF tmask) %{
17418+
match(Set dst (CompressBits (LoadL mem) mask));
17419+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17420+
format %{ "ldrd $tsrc, $mem\n\t"
17421+
"ldrd $tmask, $mask\n\t"
17422+
"bext $tdst, $tsrc, $tmask\n\t"
17423+
"mov $dst, $tdst"
17424+
%}
17425+
ins_encode %{
17426+
loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrd, $tsrc$$FloatRegister, $mem->opcode(),
17427+
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
17428+
__ ldrd($tmask$$FloatRegister, $constantaddress($mask));
17429+
__ sve_bext($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17430+
__ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17431+
%}
17432+
ins_pipe(pipe_slow);
17433+
%}
17434+
17435+
instruct expandBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
17436+
vRegF tdst, vRegF tsrc, vRegF tmask) %{
17437+
match(Set dst (ExpandBits src mask));
17438+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17439+
format %{ "mov $tsrc, $src\n\t"
17440+
"mov $tmask, $mask\n\t"
17441+
"bdep $tdst, $tsrc, $tmask\n\t"
17442+
"mov $dst, $tdst"
17443+
%}
17444+
ins_encode %{
17445+
__ mov($tsrc$$FloatRegister, __ S, 0, $src$$Register);
17446+
__ mov($tmask$$FloatRegister, __ S, 0, $mask$$Register);
17447+
__ sve_bdep($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17448+
__ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17449+
%}
17450+
ins_pipe(pipe_slow);
17451+
%}
17452+
17453+
instruct expandBitsI_memcon(iRegINoSp dst, memory4 mem, immI mask,
17454+
vRegF tdst, vRegF tsrc, vRegF tmask) %{
17455+
match(Set dst (ExpandBits (LoadI mem) mask));
17456+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17457+
format %{ "ldrs $tsrc, $mem\n\t"
17458+
"ldrs $tmask, $mask\n\t"
17459+
"bdep $tdst, $tsrc, $tmask\n\t"
17460+
"mov $dst, $tdst"
17461+
%}
17462+
ins_encode %{
17463+
loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrs, $tsrc$$FloatRegister, $mem->opcode(),
17464+
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
17465+
__ ldrs($tmask$$FloatRegister, $constantaddress($mask));
17466+
__ sve_bdep($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17467+
__ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
17468+
%}
17469+
ins_pipe(pipe_slow);
17470+
%}
17471+
17472+
instruct expandBitsL_reg(iRegLNoSp dst, iRegL src, iRegL mask,
17473+
vRegD tdst, vRegD tsrc, vRegD tmask) %{
17474+
match(Set dst (ExpandBits src mask));
17475+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17476+
format %{ "mov $tsrc, $src\n\t"
17477+
"mov $tmask, $mask\n\t"
17478+
"bdep $tdst, $tsrc, $tmask\n\t"
17479+
"mov $dst, $tdst"
17480+
%}
17481+
ins_encode %{
17482+
__ mov($tsrc$$FloatRegister, __ D, 0, $src$$Register);
17483+
__ mov($tmask$$FloatRegister, __ D, 0, $mask$$Register);
17484+
__ sve_bdep($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17485+
__ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17486+
%}
17487+
ins_pipe(pipe_slow);
17488+
%}
17489+
17490+
17491+
instruct expandBitsL_memcon(iRegINoSp dst, memory8 mem, immL mask,
17492+
vRegF tdst, vRegF tsrc, vRegF tmask) %{
17493+
match(Set dst (ExpandBits (LoadL mem) mask));
17494+
effect(TEMP tdst, TEMP tsrc, TEMP tmask);
17495+
format %{ "ldrd $tsrc, $mem\n\t"
17496+
"ldrd $tmask, $mask\n\t"
17497+
"bdep $tdst, $tsrc, $tmask\n\t"
17498+
"mov $dst, $tdst"
17499+
%}
17500+
ins_encode %{
17501+
loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrd, $tsrc$$FloatRegister, $mem->opcode(),
17502+
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
17503+
__ ldrd($tmask$$FloatRegister, $constantaddress($mask));
17504+
__ sve_bdep($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
17505+
__ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
17506+
%}
17507+
ins_pipe(pipe_slow);
17508+
%}
17509+
1735317510
// ============================================================================
1735417511
// This name is KNOWN by the ADLC and cannot be changed.
1735517512
// The ADLC forces a 'TypeRawPtr::BOTTOM' output type

‎src/hotspot/cpu/aarch64/aarch64_vector.ad

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5689,6 +5689,18 @@ instruct vmask_gen_imm(pReg pd, immL con, rFlagsReg cr) %{
56895689
ins_pipe(pipe_slow);
56905690
%}
56915691

5692+
instruct vmask_gen_sub(pReg pd, iRegL src1, iRegL src2, rFlagsReg cr) %{
5693+
predicate(UseSVE > 0);
5694+
match(Set pd (VectorMaskGen (SubL src1 src2)));
5695+
effect(KILL cr);
5696+
format %{ "vmask_gen_sub $pd, $src2, $src1\t# KILL cr" %}
5697+
ins_encode %{
5698+
BasicType bt = Matcher::vector_element_basic_type(this);
5699+
__ sve_whilelo($pd$$PRegister, __ elemType_to_regVariant(bt), $src2$$Register, $src1$$Register);
5700+
%}
5701+
ins_pipe(pipe_slow);
5702+
%}
5703+
56925704
// ------------------------------ Popcount vector ------------------------------
56935705

56945706
// vector popcount - INT

‎src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4072,6 +4072,18 @@ instruct vmask_gen_imm(pReg pd, immL con, rFlagsReg cr) %{
40724072
ins_pipe(pipe_slow);
40734073
%}
40744074

4075+
instruct vmask_gen_sub(pReg pd, iRegL src1, iRegL src2, rFlagsReg cr) %{
4076+
predicate(UseSVE > 0);
4077+
match(Set pd (VectorMaskGen (SubL src1 src2)));
4078+
effect(KILL cr);
4079+
format %{ "vmask_gen_sub $pd, $src2, $src1\t# KILL cr" %}
4080+
ins_encode %{
4081+
BasicType bt = Matcher::vector_element_basic_type(this);
4082+
__ sve_whilelo($pd$$PRegister, __ elemType_to_regVariant(bt), $src2$$Register, $src1$$Register);
4083+
%}
4084+
ins_pipe(pipe_slow);
4085+
%}
4086+
40754087
// ------------------------------ Popcount vector ------------------------------
40764088

40774089
// vector popcount - INT

‎src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -299,3 +299,18 @@ void BarrierSetAssembler::c2i_entry_barrier(MacroAssembler* masm) {
299299
__ bind(method_live);
300300
}
301301

302+
void BarrierSetAssembler::check_oop(MacroAssembler* masm, Register obj, Register tmp1, Register tmp2, Label& error) {
303+
// Check if the oop is in the right area of memory
304+
__ mov(tmp2, (intptr_t) Universe::verify_oop_mask());
305+
__ andr(tmp1, obj, tmp2);
306+
__ mov(tmp2, (intptr_t) Universe::verify_oop_bits());
307+
308+
// Compare tmp1 and tmp2. We don't use a compare
309+
// instruction here because the flags register is live.
310+
__ eor(tmp1, tmp1, tmp2);
311+
__ cbnz(tmp1, error);
312+
313+
// make sure klass is 'reasonable', which is not zero.
314+
__ load_klass(obj, obj); // get klass
315+
__ cbz(obj, error); // if klass is NULL it is broken
316+
}

‎src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,8 @@ class BarrierSetAssembler: public CHeapObj<mtGC> {
7272
virtual void nmethod_entry_barrier(MacroAssembler* masm, Label* slow_path, Label* continuation, Label* guard);
7373
virtual void c2i_entry_barrier(MacroAssembler* masm);
7474

75+
virtual void check_oop(MacroAssembler* masm, Register obj, Register tmp1, Register tmp2, Label& error);
76+
7577
virtual bool supports_instruction_patching() {
7678
NMethodPatchingType patching_type = nmethod_patching_type();
7779
return patching_type == NMethodPatchingType::conc_instruction_and_data_patch ||

‎src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2019, 2022, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2019, 2023, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -444,6 +444,19 @@ void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, Z
444444
__ b(*stub->continuation());
445445
}
446446

447+
#endif // COMPILER2
448+
447449
#undef __
450+
#define __ masm->
448451

449-
#endif // COMPILER2
452+
void ZBarrierSetAssembler::check_oop(MacroAssembler* masm, Register obj, Register tmp1, Register tmp2, Label& error) {
453+
// Check if mask is good.
454+
// verifies that ZAddressBadMask & r0 == 0
455+
__ ldr(tmp2, Address(rthread, ZThreadLocalData::address_bad_mask_offset()));
456+
__ andr(tmp1, obj, tmp2);
457+
__ cbnz(tmp1, error);
458+
459+
BarrierSetAssembler::check_oop(masm, obj, tmp1, tmp2, error);
460+
}
461+
462+
#undef __

‎src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,8 @@ class ZBarrierSetAssembler : public ZBarrierSetAssemblerBase {
9797
void generate_c2_load_barrier_stub(MacroAssembler* masm,
9898
ZLoadBarrierStubC2* stub) const;
9999
#endif // COMPILER2
100+
101+
void check_oop(MacroAssembler* masm, Register obj, Register tmp1, Register tmp2, Label& error);
100102
};
101103

102104
#endif // CPU_AARCH64_GC_Z_ZBARRIERSETASSEMBLER_AARCH64_HPP

‎src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp

Lines changed: 2 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -568,29 +568,8 @@ class StubGenerator: public StubCodeGenerator {
568568
// make sure object is 'reasonable'
569569
__ cbz(r0, exit); // if obj is NULL it is OK
570570

571-
#if INCLUDE_ZGC
572-
if (UseZGC) {
573-
// Check if mask is good.
574-
// verifies that ZAddressBadMask & r0 == 0
575-
__ ldr(c_rarg3, Address(rthread, ZThreadLocalData::address_bad_mask_offset()));
576-
__ andr(c_rarg2, r0, c_rarg3);
577-
__ cbnz(c_rarg2, error);
578-
}
579-
#endif
580-
581-
// Check if the oop is in the right area of memory
582-
__ mov(c_rarg3, (intptr_t) Universe::verify_oop_mask());
583-
__ andr(c_rarg2, r0, c_rarg3);
584-
__ mov(c_rarg3, (intptr_t) Universe::verify_oop_bits());
585-
586-
// Compare c_rarg2 and c_rarg3. We don't use a compare
587-
// instruction here because the flags register is live.
588-
__ eor(c_rarg2, c_rarg2, c_rarg3);
589-
__ cbnz(c_rarg2, error);
590-
591-
// make sure klass is 'reasonable', which is not zero.
592-
__ load_klass(r0, r0); // get klass
593-
__ cbz(r0, error); // if klass is NULL it is broken
571+
BarrierSetAssembler* bs_asm = BarrierSet::barrier_set()->barrier_set_assembler();
572+
bs_asm->check_oop(_masm, r0, c_rarg2, c_rarg3, error);
594573

595574
// return if everything seems ok
596575
__ bind(exit);

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