Merge pull request #22 from matthewelse/anotherpullrequest

PWM Patch Pull Request

Author: emilmont

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/LPC11xx.h

@@ -345,7 +345,7 @@ typedef struct
   __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
   __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
   union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40014018) Match Register */
+  __IO uint32_t MR[4];                  /*!< Offset: Match Register base */
   struct{
   __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
   __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/objects.h

@@ -59,6 +59,10 @@ struct spi_s {
     LPC_SSP_TypeDef *spi;
 };
 
+struct can_s {
+    int index;
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11CXX/pwmout_api.c

@@ -54,11 +54,21 @@ typedef struct {
     uint8_t mr;
 } timer_mr;
 
-static timer_mr pwm_timer_map[4] = {
-    {0, 0},
-    {1, 0},
-    {2, 0},
-    {3, 0},
+static timer_mr pwm_timer_map[11] = {
+    {0, 0}, /* CT16B0, MR0 */
+    {0, 1}, /* CT16B0, MR1 */
+    {0, 2}, /* CT16B0, MR2 */
+
+    {1, 0}, /* CT16B1, MR0 */
+    {1, 1}, /* CT16B1, MR1 */
+
+    {2, 0}, /* CT32B0, MR0 */
+    {2, 1}, /* CT32B0, MR1 */
+    {2, 2}, /* CT32B0, MR2 */
+
+    {3, 0}, /* CT32B1, MR0 */
+    {3, 1}, /* CT32B1, MR1 */
+    {3, 2}  /* CT32B1, MR2 */
 };
 
 static LPC_TMR_TypeDef *Timers[4] = {

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX/pwmout_api.c

@@ -54,11 +54,21 @@ typedef struct {
     uint8_t mr;
 } timer_mr;
 
-static timer_mr pwm_timer_map[4] = {
-    {0, 0},
-    {1, 0},
-    {2, 0},
-    {3, 0},
+static timer_mr pwm_timer_map[11] = {
+    {0, 0}, /* CT16B0, MR0 */
+    {0, 1}, /* CT16B0, MR1 */
+    {0, 2}, /* CT16B0, MR2 */
+
+    {1, 0}, /* CT16B1, MR0 */
+    {1, 1}, /* CT16B1, MR1 */
+
+    {2, 0}, /* CT32B0, MR0 */
+    {2, 1}, /* CT32B0, MR1 */
+    {2, 2}, /* CT32B0, MR2 */
+
+    {3, 0}, /* CT32B1, MR0 */
+    {3, 1}, /* CT32B1, MR1 */
+    {3, 2}  /* CT32B1, MR2 */
 };
 
 static LPC_TMR_TypeDef *Timers[4] = {