File tree 10 files changed +99
-35
lines changed
TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F756xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO 10 files changed +99
-35
lines changed Original file line number Diff line number Diff line change 54
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; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
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#define VECTOR_SIZE 0x198
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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+
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+
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE+MBED_CRASH_REPORT_RAM_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -64,7 +70,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 37
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#define MBED_APP_SIZE 0x200000
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#endif
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- ;256 KB SRAM (0x40000 )
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+ ;256 KB SRAM (0x30000 + 0x10000 )
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x20000000
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#endif
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#if !defined(MBED_RAM_SIZE)
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- #define MBED_RAM_SIZE 0x20000 ; (?)
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+ #define MBED_RAM_SIZE 0x30000
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#endif
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; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
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#define VECTOR_SIZE 0x1B0
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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+
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -64,7 +68,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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@@ -74,4 +81,3 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
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}
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}
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-
Original file line number Diff line number Diff line change 58
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; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
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#define VECTOR_SIZE 0x1B0
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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+
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -67,16 +71,19 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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-
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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- RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE {
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+ RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE {
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.ANY (+RW +ZI)
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}
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- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
Original file line number Diff line number Diff line change 43
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#endif
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#if !defined(MBED_RAM_SIZE)
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- #define MBED_RAM_SIZE 0x50000
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+ #define MBED_RAM_SIZE 0x00050000
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#endif
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; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
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#define VECTOR_SIZE 0x1C8
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 32
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#define MBED_APP_START 0x08000000
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#endif
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- ; STM32F746xG : 1024 KB FLASH (0x100000)
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+ ; STM32F756xG : 1024 KB FLASH (0x100000)
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x100000
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#endif
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; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
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#define VECTOR_SIZE 0x1C8
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 53
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; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
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#define VECTOR_SIZE 0x1F8
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 32
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#define MBED_APP_START 0x08000000
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#endif
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- ; STM32F767ZI : 2048KB FLASH (0x200000)
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+ ; STM32F743xl : 2048KB FLASH (0x200000)
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x200000
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#endif
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; 166 vectors = 664 bytes (0x298) to be reserved in RAM
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#define VECTOR_SIZE 0x298
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 58
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; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
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#define VECTOR_SIZE 0x188
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -69,11 +72,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
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+ RW_m_crash_data MBED_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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-
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- RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START- MBED_RAM2_SIZE) {
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+
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+ RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE ) {
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 58
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; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
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#define VECTOR_SIZE 0x188
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -69,11 +72,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
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+ RW_m_crash_data MBED_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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-
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- RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START- MBED_RAM2_SIZE) {
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+
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+ RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE ) {
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.ANY (+RW +ZI)
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}
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Original file line number Diff line number Diff line change 58
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; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
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#define VECTOR_SIZE 0x188
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+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
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+ #define MBED_IRAM1_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
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+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE)
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+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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@@ -69,11 +72,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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.ANY (+RO)
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}
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- RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
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+ RW_m_crash_data MBED_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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+ }
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+
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+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
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.ANY (+RW +ZI)
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}
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-
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- RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START- MBED_RAM2_SIZE) {
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+
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+ RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE ) {
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.ANY (+RW +ZI)
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}
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