1+ ;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
2+ ;; The information contained herein is confidential property of Nordic
3+ ;; Semiconductor ASA.Terms and conditions of usage are described in detail
4+ ;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
5+ ;; Licensees are granted free, non-transferable use of the information. NO
6+ ;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
7+ ;; the file.
8+
9+ ;; Description message
10+
11+ MODULE ?cstartup
12+
13+ ;; Stack size default : 1024
14+ ;; Heap size default : 2048
15+
16+ ;; Forward declaration of sections.
17+ SECTION CSTACK:DATA:NOROOT( 3 )
18+
19+ SECTION .intvec:CODE:NOROOT( 2 )
20+
21+ EXTERN __iar_program_start
22+ EXTERN SystemInit
23+ EXTERN nrf_reloc_vector_table
24+ PUBLIC __vector_table
25+ PUBLIC __Vectors
26+ PUBLIC __Vectors_End
27+ PUBLIC __Vectors_Size
28+
29+ DATA
30+
31+ __vector_table
32+ DCD sfe(CSTACK)
33+ DCD Reset_Handler
34+ DCD NMI_Handler
35+ DCD HardFault_Handler
36+ DCD 0
37+ DCD 0
38+ DCD 0
39+ ;__vector_table_0x1c
40+ DCD 0
41+ DCD 0
42+ DCD 0
43+ DCD 0
44+ DCD SVC_Handler
45+ DCD 0
46+ DCD 0
47+ DCD PendSV_Handler
48+ DCD SysTick_Handler
49+
50+ ; External Interrupts
51+ DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
52+ DCD RADIO_IRQHandler ;RADIO
53+ DCD UART0_IRQHandler_v ;UART0
54+ DCD SPI0_TWI0_IRQHandler_v ;SPI0_TWI0
55+ DCD SPI1_TWI1_IRQHandler_v ;SPI1_TWI1
56+ DCD 0 ;Reserved
57+ DCD GPIOTE_IRQHandler_v ;GPIOTE
58+ DCD ADC_IRQHandler_v ;ADC
59+ DCD TIMER0_IRQHandler ;TIMER0
60+ DCD TIMER1_IRQHandler_v ;TIMER1
61+ DCD TIMER2_IRQHandler_v ;TIMER2
62+ DCD RTC0_IRQHandler ;RTC0
63+ DCD TEMP_IRQHandler ;TEMP
64+ DCD RNG_IRQHandler ;RNG
65+ DCD ECB_IRQHandler ;ECB
66+ DCD CCM_AAR_IRQHandler ;CCM_AAR
67+ DCD WDT_IRQHandler_v ;WDT
68+ DCD RTC1_IRQHandler_v ;RTC1
69+ DCD QDEC_IRQHandler_v ;QDEC
70+ DCD LPCOMP_COMP_IRQHandler_v ;LPCOMP_COMP
71+ DCD SWI0_IRQHandler ;SWI0
72+ DCD SWI1_IRQHandler_v ;SWI1
73+ DCD SWI2_IRQHandler_v ;SWI2
74+ DCD SWI3_IRQHandler_v ;SWI3
75+ DCD SWI4_IRQHandler ;SWI4
76+ DCD SWI5_IRQHandler ;SWI5
77+
78+
79+ __Vectors_End
80+ __Vectors EQU __vector_table
81+ __Vectors_Size EQU __Vectors_End - __Vectors
82+ NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
83+ NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
84+
85+ ; Default handlers.
86+ THUMB
87+
88+ PUBWEAK Reset_Handler
89+ SECTION .text:CODE:REORDER:NOROOT( 2 )
90+ Reset_Handler
91+ LDR R0 , =NRF_POWER_RAMON_ADDRESS
92+ LDR R2 , [ R0 ]
93+ MOVS R1 , #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
94+ ORRS R2 , R2 , R1
95+ STR R2 , [ R0 ]
96+ LDR R0 , =SystemInit
97+ BLX R0
98+ LDR R0 , =nrf_reloc_vector_table
99+ BLX R0
100+ LDR R0 , =__iar_program_start
101+ BX R0
102+
103+ ; Dummy exception handlers
104+
105+ PUBWEAK NMI_Handler
106+ SECTION .text:CODE:REORDER:NOROOT( 1 )
107+ NMI_Handler
108+ B .
109+
110+ PUBWEAK HardFault_Handler
111+ SECTION .text:CODE:REORDER:NOROOT( 1 )
112+ HardFault_Handler
113+ B .
114+
115+ PUBWEAK SVC_Handler
116+ SECTION .text:CODE:REORDER:NOROOT( 1 )
117+ SVC_Handler
118+ B .
119+
120+ PUBWEAK PendSV_Handler
121+ SECTION .text:CODE:REORDER:NOROOT( 1 )
122+ PendSV_Handler
123+ B .
124+
125+ PUBWEAK SysTick_Handler
126+ SECTION .text:CODE:REORDER:NOROOT( 1 )
127+ SysTick_Handler
128+ B .
129+
130+ ; Dummy interrupt handlers
131+
132+ PUBWEAK POWER_CLOCK_IRQHandler
133+ SECTION .text:CODE:REORDER:NOROOT( 1 )
134+ POWER_CLOCK_IRQHandler
135+ B .
136+ PUBWEAK RADIO_IRQHandler
137+ SECTION .text:CODE:REORDER:NOROOT( 1 )
138+ RADIO_IRQHandler
139+ B .
140+ PUBWEAK UART0_IRQHandler_v
141+ SECTION .text:CODE:REORDER:NOROOT( 1 )
142+ UART0_IRQHandler_v
143+ B .
144+ PUBWEAK SPI0_TWI0_IRQHandler_v
145+ SECTION .text:CODE:REORDER:NOROOT( 1 )
146+ SPI0_TWI0_IRQHandler_v
147+ B .
148+ PUBWEAK SPI1_TWI1_IRQHandler_v
149+ SECTION .text:CODE:REORDER:NOROOT( 1 )
150+ SPI1_TWI1_IRQHandler_v
151+ B .
152+ PUBWEAK GPIOTE_IRQHandler_v
153+ SECTION .text:CODE:REORDER:NOROOT( 1 )
154+ GPIOTE_IRQHandler_v
155+ B .
156+ PUBWEAK ADC_IRQHandler_v
157+ SECTION .text:CODE:REORDER:NOROOT( 1 )
158+ ADC_IRQHandler_v
159+ B .
160+ PUBWEAK TIMER0_IRQHandler
161+ SECTION .text:CODE:REORDER:NOROOT( 1 )
162+ TIMER0_IRQHandler
163+ B .
164+ PUBWEAK TIMER1_IRQHandler_v
165+ SECTION .text:CODE:REORDER:NOROOT( 1 )
166+ TIMER1_IRQHandler_v
167+ B .
168+ PUBWEAK TIMER2_IRQHandler_v
169+ SECTION .text:CODE:REORDER:NOROOT( 1 )
170+ TIMER2_IRQHandler_v
171+ B .
172+ PUBWEAK RTC0_IRQHandler
173+ SECTION .text:CODE:REORDER:NOROOT( 1 )
174+ RTC0_IRQHandler
175+ B .
176+ PUBWEAK TEMP_IRQHandler
177+ SECTION .text:CODE:REORDER:NOROOT( 1 )
178+ TEMP_IRQHandler
179+ B .
180+ PUBWEAK RNG_IRQHandler
181+ SECTION .text:CODE:REORDER:NOROOT( 1 )
182+ RNG_IRQHandler
183+ B .
184+ PUBWEAK ECB_IRQHandler
185+ SECTION .text:CODE:REORDER:NOROOT( 1 )
186+ ECB_IRQHandler
187+ B .
188+ PUBWEAK CCM_AAR_IRQHandler
189+ SECTION .text:CODE:REORDER:NOROOT( 1 )
190+ CCM_AAR_IRQHandler
191+ B .
192+ PUBWEAK WDT_IRQHandler_v
193+ SECTION .text:CODE:REORDER:NOROOT( 1 )
194+ WDT_IRQHandler_v
195+ B .
196+ PUBWEAK RTC1_IRQHandler_v
197+ SECTION .text:CODE:REORDER:NOROOT( 1 )
198+ RTC1_IRQHandler_v
199+ B .
200+ PUBWEAK QDEC_IRQHandler_v
201+ SECTION .text:CODE:REORDER:NOROOT( 1 )
202+ QDEC_IRQHandler_v
203+ B .
204+ PUBWEAK LPCOMP_COMP_IRQHandler_v
205+ SECTION .text:CODE:REORDER:NOROOT( 1 )
206+ LPCOMP_COMP_IRQHandler_v
207+ B .
208+ PUBWEAK SWI0_IRQHandler
209+ SECTION .text:CODE:REORDER:NOROOT( 1 )
210+ SWI0_IRQHandler
211+ B .
212+ PUBWEAK SWI1_IRQHandler_v
213+ SECTION .text:CODE:REORDER:NOROOT( 1 )
214+ SWI1_IRQHandler_v
215+ B .
216+ PUBWEAK SWI2_IRQHandler_v
217+ SECTION .text:CODE:REORDER:NOROOT( 1 )
218+ SWI2_IRQHandler_v
219+ B .
220+ PUBWEAK SWI3_IRQHandler_v
221+ SECTION .text:CODE:REORDER:NOROOT( 1 )
222+ SWI3_IRQHandler_v
223+ B .
224+ PUBWEAK SWI4_IRQHandler
225+ SECTION .text:CODE:REORDER:NOROOT( 1 )
226+ SWI4_IRQHandler
227+ B .
228+ PUBWEAK SWI5_IRQHandler
229+ SECTION .text:CODE:REORDER:NOROOT( 1 )
230+ SWI5_IRQHandler
231+ B .
232+
233+
234+ END
0 commit comments