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Merge pull request #4974 from ARMmbed/release-candidate
Release candidate for mbed-os-5.5.6
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‎.travis.yml

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@@ -28,10 +28,10 @@ script:
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- python tools/project.py -S
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- python tools/build_travis.py
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before_install:
31-
- sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded
31+
- sudo add-apt-repository -y ppa:team-gcc-arm-embedded/ppa
3232
- sudo add-apt-repository -y ppa:libreoffice/libreoffice-4-2
3333
- sudo apt-get update -qq
34-
- sudo apt-get install -qq gcc-arm-none-eabi doxygen --force-yes
34+
- sudo apt-get install -qq gcc-arm-embedded doxygen --force-yes
3535
# Print versions we use
3636
- arm-none-eabi-gcc --version
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- python --version

‎cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S

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/* Copyright (c) 2009 - 2012 ARM LIMITED
2+
3+
All rights reserved.
4+
Redistribution and use in source and binary forms, with or without
5+
modification, are permitted provided that the following conditions are met:
6+
- Redistributions of source code must retain the above copyright
7+
notice, this list of conditions and the following disclaimer.
8+
- Redistributions in binary form must reproduce the above copyright
9+
notice, this list of conditions and the following disclaimer in the
10+
documentation and/or other materials provided with the distribution.
11+
- Neither the name of ARM nor the names of its contributors may be used
12+
to endorse or promote products derived from this software without
13+
specific prior written permission.
14+
*
15+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17+
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18+
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
19+
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20+
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21+
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22+
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23+
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25+
POSSIBILITY OF SUCH DAMAGE.
26+
---------------------------------------------------------------------------*/
27+
28+
/*----------------------------------------------------------------------------
29+
* Functions
30+
*---------------------------------------------------------------------------*/
31+
.text
32+
.global __v7_all_cache
33+
/*
34+
* __STATIC_ASM void __v7_all_cache(uint32_t op) {
35+
*/
36+
__v7_all_cache:
37+
.arm
38+
39+
PUSH {R4-R11}
40+
41+
MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
42+
ANDS R3, R6, #0x07000000 /* Extract coherency level */
43+
MOV R3, R3, LSR #23 /* Total cache levels << 1 */
44+
BEQ Finished /* If 0, no need to clean */
45+
46+
MOV R10, #0 /* R10 holds current cache level << 1 */
47+
Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
48+
MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
49+
AND R1, R1, #7 /* Isolate those lower 3 bits */
50+
CMP R1, #2
51+
BLT Skip /* No cache or only instruction cache at this level */
52+
53+
MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
54+
ISB /* ISB to sync the change to the CacheSizeID reg */
55+
MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
56+
AND R2, R1, #7 /* Extract the line length field */
57+
ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
58+
LDR R4, =0x3FF
59+
ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
60+
CLZ R5, R4 /* R5 is the bit position of the way size increment */
61+
LDR R7, =0x7FFF
62+
ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
63+
64+
Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
65+
66+
Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
67+
ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
68+
CMP R0, #0
69+
BNE Dccsw
70+
MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
71+
B cont
72+
Dccsw: CMP R0, #1
73+
BNE Dccisw
74+
MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
75+
B cont
76+
Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
77+
cont: SUBS R9, R9, #1 /* Decrement the Way number */
78+
BGE Loop3
79+
SUBS R7, R7, #1 /* Decrement the Set number */
80+
BGE Loop2
81+
Skip: ADD R10, R10, #2 /* increment the cache number */
82+
CMP R3, R10
83+
BGT Loop1
84+
85+
Finished:
86+
DSB
87+
POP {R4-R11}
88+
BX lr
89+
90+
91+
.END
92+
/*----------------------------------------------------------------------------
93+
* end of file
94+
*---------------------------------------------------------------------------*/

‎cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S

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Original file line numberDiff line numberDiff line change
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/* Copyright (c) 2009 - 2012 ARM LIMITED
2+
3+
All rights reserved.
4+
Redistribution and use in source and binary forms, with or without
5+
modification, are permitted provided that the following conditions are met:
6+
- Redistributions of source code must retain the above copyright
7+
notice, this list of conditions and the following disclaimer.
8+
- Redistributions in binary form must reproduce the above copyright
9+
notice, this list of conditions and the following disclaimer in the
10+
documentation and/or other materials provided with the distribution.
11+
- Neither the name of ARM nor the names of its contributors may be used
12+
to endorse or promote products derived from this software without
13+
specific prior written permission.
14+
*
15+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17+
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18+
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
19+
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20+
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21+
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22+
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23+
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25+
POSSIBILITY OF SUCH DAMAGE.
26+
---------------------------------------------------------------------------*/
27+
28+
/*----------------------------------------------------------------------------
29+
* Functions
30+
*---------------------------------------------------------------------------*/
31+
SECTION `.text`:CODE:NOROOT(2)
32+
arm
33+
PUBLIC __v7_all_cache
34+
/*
35+
* __STATIC_ASM void __v7_all_cache(uint32_t op) {
36+
*/
37+
38+
__v7_all_cache:
39+
40+
41+
PUSH {R4-R11}
42+
43+
MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
44+
ANDS R3, R6, #0x07000000 /* Extract coherency level */
45+
MOV R3, R3, LSR #23 /* Total cache levels << 1 */
46+
BEQ Finished /* If 0, no need to clean */
47+
48+
MOV R10, #0 /* R10 holds current cache level << 1 */
49+
Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
50+
MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
51+
AND R1, R1, #7 /* Isolate those lower 3 bits */
52+
CMP R1, #2
53+
BLT Skip /* No cache or only instruction cache at this level */
54+
55+
MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
56+
ISB /* ISB to sync the change to the CacheSizeID reg */
57+
MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
58+
AND R2, R1, #7 /* Extract the line length field */
59+
ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
60+
LDR R4, =0x3FF
61+
ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
62+
CLZ R5, R4 /* R5 is the bit position of the way size increment */
63+
LDR R7, =0x7FFF
64+
ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
65+
66+
Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
67+
68+
Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
69+
ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
70+
CMP R0, #0
71+
BNE Dccsw
72+
MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
73+
B cont
74+
Dccsw: CMP R0, #1
75+
BNE Dccisw
76+
MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
77+
B cont
78+
Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
79+
cont: SUBS R9, R9, #1 /* Decrement the Way number */
80+
BGE Loop3
81+
SUBS R7, R7, #1 /* Decrement the Set number */
82+
BGE Loop2
83+
Skip: ADD R10, R10, #2 /* increment the cache number */
84+
CMP R3, R10
85+
BGT Loop1
86+
87+
Finished:
88+
DSB
89+
POP {R4-R11}
90+
BX lr
91+
92+
93+
END
94+
/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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‎doxyfile_options

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@@ -2056,7 +2056,32 @@ INCLUDE_FILE_PATTERNS =
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# recursively expanded use the := operator instead of the = operator.
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# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
20582058

2059-
PREDEFINED = DOXYGEN_ONLY \
2059+
PREDEFINED = DOXYGEN_ONLY \
2060+
DEVICE_ANALOGIN \
2061+
DEVICE_ANALOGOUT \
2062+
DEVICE_CAN \
2063+
DEVICE_ETHERNET \
2064+
DEVICE_EMAC \
2065+
DEVICE_FLASH \
2066+
DEVICE_I2C \
2067+
DEVICE_I2CSLAVE \
2068+
DEVICE_I2C_ASYNCH \
2069+
DEVICE_INTERRUPTIN \
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DEVICE_LOWPOWERTIMER \
2071+
DEVICE_PORTIN \
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DEVICE_PORTINOUT \
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DEVICE_PORTOUT \
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DEVICE_PWMOUT \
2075+
DEVICE_RTC \
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DEVICE_TRNG \
2077+
DEVICE_SERIAL \
2078+
DEVICE_SERIAL_ASYNCH \
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DEVICE_SERIAL_FC \
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DEVICE_SLEEP \
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DEVICE_SPI \
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DEVICE_SPI_ASYNCH \
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DEVICE_SPISLAVE \
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DEVICE_STORAGE \
20602085
"MBED_DEPRECATED_SINCE(d, m)=" \
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"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)="
20622087

‎doxygen_options.json

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"SEARCH_INCLUDES": "YES",
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"INCLUDE_PATH": "",
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"INCLUDE_FILE_PATTERNS": "",
8-
"PREDEFINED": "DOXYGEN_ONLY \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"",
8+
"PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"",
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"EXPAND_AS_DEFINED": "",
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"SKIP_FUNCTION_MACROS": "NO",
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"EXCLUDE_PATTERNS": "*/tools/* */TESTS/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */features/filesystem/* */BUILD/* */rtos/rtx*/* */cmsis/* */features/FEATURES_*"

‎features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md

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# Change Log
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3+
## [v4.0.9](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.9)
4+
5+
-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.8...v4.0.9)
6+
7+
**Closed issues:**
8+
- IOTCLT-1899 Maximum COAP message resending buffer size limited to 255 bytes
9+
- IOTCLT-1888 Problem with blockwise transfers that are even increments of block_size
10+
311
## [v4.0.8](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.8)
412

513
-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.4...v4.0.8)

‎features/FEATURE_COMMON_PAL/mbed-coap/module.json

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{
22
"name": "mbed-coap",
3-
"version": "4.0.8",
3+
"version": "4.0.9",
44
"description": "COAP library",
55
"keywords": [
66
"coap",

‎features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h

Lines changed: 1 addition & 1 deletion
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@@ -225,7 +225,7 @@ struct coap_s {
225225
uint32_t system_time; /* System time seconds */
226226
uint16_t sn_coap_block_data_size;
227227
uint8_t sn_coap_resending_queue_msgs;
228-
uint8_t sn_coap_resending_queue_bytes;
228+
uint32_t sn_coap_resending_queue_bytes;
229229
uint8_t sn_coap_resending_count;
230230
uint8_t sn_coap_resending_intervall;
231231
uint8_t sn_coap_duplication_buffer_size;

‎features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2027,7 +2027,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
20272027
original_payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len;
20282028
original_payload_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr;
20292029

2030-
if ((block_size * (block_number + 1)) > stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
2030+
if ((block_size * (block_number + 1)) >= stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
20312031
src_coap_blockwise_ack_msg_ptr->payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len - (block_size * block_number);
20322032
src_coap_blockwise_ack_msg_ptr->payload_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr + (block_size * block_number);
20332033
}
@@ -2080,7 +2080,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
20802080
stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len = original_payload_len;
20812081
stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr = original_payload_ptr;
20822082

2083-
if ((block_size * (block_number + 1)) > stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
2083+
if ((block_size * (block_number + 1)) >= stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
20842084
sn_coap_protocol_linked_list_blockwise_msg_remove(handle, stored_blockwise_msg_temp_ptr);
20852085
}
20862086

‎features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/lwipopts_conf.h

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1+
/*
2+
* Copyright (c) 2012-2015, ARM Limited, All Rights Reserved
3+
* SPDX-License-Identifier: Apache-2.0
4+
*
5+
* Licensed under the Apache License, Version 2.0 (the "License"); you may
6+
* not use this file except in compliance with the License.
7+
* You may obtain a copy of the License at
8+
*
9+
* http://www.apache.org/licenses/LICENSE-2.0
10+
*
11+
* Unless required by applicable law or agreed to in writing, software
12+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
13+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
* See the License for the specific language governing permissions and
15+
* limitations under the License.
16+
*/
17+
18+
#ifndef LWIPOPTS_CONF_H
19+
#define LWIPOPTS_CONF_H
20+
21+
#define LWIP_TRANSPORT_ETHERNET 1
22+
#define ETH_PAD_SIZE 2
23+
24+
#define MEM_SIZE (16*1024)//(8*1024)//(16*1024)
25+
26+
#endif

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