Skip to content

Commit b2ff2e9

Browse files
PrzemekWirkusPrzemekWirkus
committed
Merge pull request #6 from mbedmicro/master
Synd with master (11 March 2015)
2 parents 1bb14b7 + 0703a02 commit b2ff2e9

File tree

309 files changed

+113902
-38646
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

309 files changed

+113902
-38646
lines changed

‎libraries/mbed/api/rtc_time.h

+11
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,17 @@ extern "C" {
6969
*/
7070
void set_time(time_t t);
7171

72+
/** Attach an external RTC to be used for the C time functions
73+
*
74+
* Do not call this function from an interrupt while an RTC read/write operation may be occurring
75+
*
76+
* @param read_rtc pointer to function which returns current UNIX timestamp
77+
* @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
78+
* @param init_rtc pointer to funtion which initializes RTC, can be NULL
79+
* @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
80+
*/
81+
void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
82+
7283
#ifdef __cplusplus
7384
}
7485
#endif

‎libraries/mbed/common/rtc_time.c

+37-11
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,18 @@
1919
#include "rtc_time.h"
2020
#include "us_ticker_api.h"
2121

22+
#if DEVICE_RTC
23+
static void (*_rtc_init)(void) = rtc_init;
24+
static int (*_rtc_isenabled)(void) = rtc_isenabled;
25+
static time_t (*_rtc_read)(void) = rtc_read;
26+
static void (*_rtc_write)(time_t t) = rtc_write;
27+
#else
28+
static void (*_rtc_init)(void) = NULL;
29+
static int (*_rtc_isenabled)(void) = NULL;
30+
static time_t (*_rtc_read)(void) = NULL;
31+
static void (*_rtc_write)(time_t t) = NULL;
32+
#endif
33+
2234
#ifdef __cplusplus
2335
extern "C" {
2436
#endif
@@ -29,15 +41,16 @@ time_t time(time_t *timer)
2941
#endif
3042

3143
{
32-
#if DEVICE_RTC
33-
if (!(rtc_isenabled())) {
34-
set_time(0);
44+
if (_rtc_isenabled != NULL) {
45+
if (!(_rtc_isenabled())) {
46+
set_time(0);
47+
}
3548
}
36-
time_t t = rtc_read();
37-
38-
#else
49+
3950
time_t t = 0;
40-
#endif
51+
if (_rtc_read != NULL) {
52+
t = _rtc_read();
53+
}
4154

4255
if (timer != NULL) {
4356
*timer = t;
@@ -46,10 +59,12 @@ time_t time(time_t *timer)
4659
}
4760

4861
void set_time(time_t t) {
49-
#if DEVICE_RTC
50-
rtc_init();
51-
rtc_write(t);
52-
#endif
62+
if (_rtc_init != NULL) {
63+
_rtc_init();
64+
}
65+
if (_rtc_write != NULL) {
66+
_rtc_write(t);
67+
}
5368
}
5469

5570
clock_t clock() {
@@ -58,6 +73,17 @@ clock_t clock() {
5873
return t;
5974
}
6075

76+
void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
77+
__disable_irq();
78+
_rtc_read = read_rtc;
79+
_rtc_write = write_rtc;
80+
_rtc_init = init_rtc;
81+
_rtc_isenabled = isenabled_rtc;
82+
__enable_irq();
83+
}
84+
85+
86+
6187
#ifdef __cplusplus
6288
}
6389
#endif

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -145,8 +145,8 @@ void SystemInit (void) {
145145
/* Switch to FEE Mode */
146146
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
147147
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
148-
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
149-
OSC0->CR = OSC_CR_ERCLKEN_MASK;
148+
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=1,SC8P=1,SC16P=0 */
149+
OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC4P_MASK;
150150
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
151151
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
152152
/* MCG->C4: DMX32=1,DRST_DRS=1 */

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf

+36
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
/*###ICF### Section handled by ICF editor, don't touch! ****/
2+
/*-Editor annotation file-*/
3+
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
4+
/*-Specials-*/
5+
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
6+
/*-Memory Regions-*/
7+
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
8+
define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
9+
define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
10+
define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
11+
define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
12+
define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF;
13+
/*-Sizes-*/
14+
define symbol __ICFEDIT_size_cstack__ = 0x400;
15+
define symbol __ICFEDIT_size_heap__ = 0xA00;
16+
/**** End of ICF editor section. ###ICF###*/
17+
18+
define symbol __CRP_start__ = 0x000002FC;
19+
define symbol __CRP_end__ = 0x000002FF;
20+
21+
define memory mem with size = 4G;
22+
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
23+
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
24+
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
25+
26+
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
27+
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
28+
29+
initialize by copy { readwrite };
30+
do not initialize { section .noinit };
31+
32+
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
33+
place in ROM_region { readonly };
34+
place in RAM_region { readwrite,
35+
block HEAP, block CSTACK };
36+
place in CRP_region { section .crp };

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s

+216
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,216 @@
1+
/**************************************************
2+
*
3+
* Part one of the system initialization code, contains low-level
4+
* initialization, plain thumb variant.
5+
*
6+
* Copyright 2011 IAR Systems. All rights reserved.
7+
*
8+
* $Revision: 47876 $
9+
*
10+
**************************************************/
11+
12+
;
13+
; The modules in this file are included in the libraries, and may be replaced
14+
; by any user-defined modules that define the PUBLIC symbol _program_start or
15+
; a user defined start symbol.
16+
; To override the cstartup defined in the library, simply add your modified
17+
; version to the workbench project.
18+
;
19+
; The vector table is normally located at address 0.
20+
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
21+
; The name "__vector_table" has special meaning for C-SPY:
22+
; it is where the SP start value is found, and the NVIC vector
23+
; table register (VTOR) is initialized to this address if != 0.
24+
;
25+
; Cortex-M version
26+
;
27+
28+
29+
MODULE ?cstartup
30+
31+
;; Forward declaration of sections.
32+
SECTION CSTACK:DATA:NOROOT(3)
33+
34+
SECTION .intvec:CODE:NOROOT(2)
35+
36+
EXTERN __iar_program_start
37+
EXTERN SystemInit
38+
PUBLIC __vector_table
39+
PUBLIC __vector_table_0x1c
40+
PUBLIC __Vectors
41+
PUBLIC __Vectors_End
42+
PUBLIC __Vectors_Size
43+
44+
DATA
45+
46+
__vector_table
47+
DCD sfe(CSTACK)
48+
DCD Reset_Handler
49+
DCD NMI_Handler
50+
DCD HardFault_Handler
51+
DCD 0
52+
DCD 0
53+
DCD 0
54+
__vector_table_0x1c
55+
DCD 0
56+
DCD 0
57+
DCD 0
58+
DCD 0
59+
DCD SVC_Handler
60+
DCD 0
61+
DCD 0
62+
DCD PendSV_Handler
63+
DCD SysTick_Handler
64+
65+
; External Interrupts
66+
DCD SPI0_IRQHandler ; SPI0 controller
67+
DCD SPI1_IRQHandler ; SPI1 controller
68+
DCD 0 ; Reserved
69+
DCD UART0_IRQHandler ; UART0
70+
DCD UART1_IRQHandler ; UART1
71+
DCD UART2_IRQHandler ; UART2
72+
DCD 0 ; Reserved
73+
DCD I2C1_IRQHandler ; I2C1 controller
74+
DCD I2C0_IRQHandler ; I2C0 controller
75+
DCD SCT_IRQHandler ; Smart Counter Timer
76+
DCD MRT_IRQHandler ; Multi-Rate Timer
77+
DCD CMP_IRQHandler ; Comparator
78+
DCD WDT_IRQHandler ; PIO1 (0:11)
79+
DCD BOD_IRQHandler ; Brown Out Detect
80+
DCD Flash_IRQHandler ; Flash interrupt
81+
DCD WKT_IRQHandler ; Wakeup timer
82+
DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
83+
DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
84+
DCD ADC_THCMP_IRQHandler ; ADC threshold compare
85+
DCD ADC_OVR_IRQHandler ; ADC overrun
86+
DCD DMA__RQHandler ; DMA interrupt
87+
DCD I2C2_IRQHandler ; I2C2 controller
88+
DCD I2C3_IRQHandler ; I2C3 controller
89+
DCD 0 ; Reserved
90+
DCD PININT0_IRQHandler ; PIO INT0
91+
DCD PININT1_IRQHandler ; PIO INT1
92+
DCD PININT2_IRQHandler ; PIO INT2
93+
DCD PININT3_IRQHandler ; PIO INT3
94+
DCD PININT4_IRQHandler ; PIO INT4
95+
DCD PININT5_IRQHandler ; PIO INT5
96+
DCD PININT6_IRQHandler ; PIO INT6
97+
DCD PININT7_IRQHandler ; PIO INT7
98+
__Vectors_End
99+
100+
__Vectors EQU __vector_table
101+
__Vectors_Size EQU __Vectors_End - __Vectors
102+
103+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
104+
;;
105+
;; Default interrupt handlers.
106+
;;
107+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
108+
109+
THUMB
110+
PUBWEAK Reset_Handler
111+
SECTION .text:CODE:NOROOT:REORDER(2)
112+
Reset_Handler
113+
LDR R0, =SystemInit
114+
BLX R0
115+
LDR R0, =__iar_program_start
116+
BX R0
117+
118+
PUBWEAK NMI_Handler
119+
PUBWEAK HardFault_Handler
120+
PUBWEAK SVC_Handler
121+
PUBWEAK PendSV_Handler
122+
PUBWEAK SysTick_Handler
123+
PUBWEAK SPI0_IRQHandler
124+
PUBWEAK SPI1_IRQHandler
125+
PUBWEAK UART0_IRQHandler
126+
PUBWEAK UART1_IRQHandler
127+
PUBWEAK UART2_IRQHandler
128+
PUBWEAK I2C1_IRQHandler
129+
PUBWEAK I2C0_IRQHandler
130+
PUBWEAK SCT_IRQHandler
131+
PUBWEAK MRT_IRQHandler
132+
PUBWEAK CMP_IRQHandler
133+
PUBWEAK WDT_IRQHandler
134+
PUBWEAK BOD_IRQHandler
135+
PUBWEAK Flash_IRQHandler
136+
PUBWEAK WKT_IRQHandler
137+
PUBWEAK ADC_SEQA_IRQHandler
138+
PUBWEAK ADC_SEQB_IRQHandler
139+
PUBWEAK ADC_THCMP_IRQHandler
140+
PUBWEAK ADC_OVR_IRQHandler
141+
PUBWEAK DMA__RQHandler
142+
PUBWEAK I2C2_IRQHandler
143+
PUBWEAK I2C3_IRQHandler
144+
PUBWEAK PININT0_IRQHandler
145+
PUBWEAK PININT1_IRQHandler
146+
PUBWEAK PININT2_IRQHandler
147+
PUBWEAK PININT3_IRQHandler
148+
PUBWEAK PININT4_IRQHandler
149+
PUBWEAK PININT5_IRQHandler
150+
PUBWEAK PININT6_IRQHandler
151+
PUBWEAK PININT7_IRQHandler
152+
153+
SECTION .text:CODE:REORDER:NOROOT(1)
154+
THUMB
155+
156+
NMI_Handler
157+
HardFault_Handler
158+
SVC_Handler
159+
PendSV_Handler
160+
SysTick_Handler
161+
SPI0_IRQHandler
162+
SPI1_IRQHandler
163+
UART0_IRQHandler
164+
UART1_IRQHandler
165+
UART2_IRQHandler
166+
I2C1_IRQHandler
167+
I2C0_IRQHandler
168+
SCT_IRQHandler
169+
MRT_IRQHandler
170+
CMP_IRQHandler
171+
WDT_IRQHandler
172+
BOD_IRQHandler
173+
Flash_IRQHandler
174+
WKT_IRQHandler
175+
ADC_SEQA_IRQHandler
176+
ADC_SEQB_IRQHandler
177+
ADC_THCMP_IRQHandler
178+
ADC_OVR_IRQHandler
179+
DMA__RQHandler
180+
I2C2_IRQHandler
181+
I2C3_IRQHandler
182+
PININT0_IRQHandler
183+
PININT1_IRQHandler
184+
PININT2_IRQHandler
185+
PININT3_IRQHandler
186+
PININT4_IRQHandler
187+
PININT5_IRQHandler
188+
PININT6_IRQHandler
189+
PININT7_IRQHandler
190+
Default_IRQHandler
191+
B Default_IRQHandler
192+
193+
SECTION .crp:CODE:ROOT(2)
194+
DATA
195+
/* Code Read Protection
196+
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
197+
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
198+
- Copy RAM to flash command can not write to Sector 0.
199+
- Erase command can erase Sector 0 only when all sectors
200+
are selected for erase.
201+
- Compare command is disabled.
202+
- Read Memory command is disabled.
203+
CRP2 0x87654321 - Read Memory is disabled.
204+
- Write to RAM is disabled.
205+
- "Go" command is disabled.
206+
- Copy RAM to flash is disabled.
207+
- Compare is disabled.
208+
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
209+
by pulling PIO0_1 LOW is disabled if a valid user code is
210+
present in flash sector 0.
211+
Caution: If CRP3 is selected, no future factory testing can be
212+
performed on the device.
213+
*/
214+
DCD 0xFFFFFFFF
215+
216+
END

0 commit comments

Comments
 (0)