Skip to content

Commit c4ac78b

Browse files
cy-opmadbridge
cy-opm
authored and
adbridge
committed
Added CYW9P62S1_43012EVB_01 board Notes: - CRC and TRNG are disabled on this board since the MCU on this board does not have the required hardware. - QSPI and QSPIF are temporarily removed due to issues related to supporting the new S25FS512S flash chip we have on this board. These will be enabled as soon as we can get the issues resolved. #11722 
1 parent 586ce90 commit c4ac78b

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

41 files changed

+14376
-23
lines changed

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@
8282
#include "S25FL512S_config.h"
8383

8484
#elif defined(TARGET_CYW9P62S1_43012EVB_01)
85-
#include "S25FS128S_config.h"
85+
#include "S25FS512S_config.h"
8686

8787
#elif defined(TARGET_CY8CPROTO_064_SB)
8888
#include "S25FL128S_config.h"

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

+34
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
/*******************************************************************************
2+
* File Name: cycfg.c
3+
*
4+
* Description:
5+
* Wrapper function to initialize all generated code.
6+
* This file was automatically generated and should not be modified.
7+
*
8+
********************************************************************************
9+
* Copyright 2017-2019 Cypress Semiconductor Corporation
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the "License");
13+
* you may not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* http://www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an "AS IS" BASIS,
20+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
********************************************************************************/
24+
25+
#include "cycfg.h"
26+
27+
void init_cycfg_all(void)
28+
{
29+
init_cycfg_system();
30+
init_cycfg_clocks();
31+
init_cycfg_routing();
32+
init_cycfg_peripherals();
33+
init_cycfg_pins();
34+
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

+47
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
/*******************************************************************************
2+
* File Name: cycfg.h
3+
*
4+
* Description:
5+
* Simple wrapper header containing all generated files.
6+
* This file was automatically generated and should not be modified.
7+
*
8+
********************************************************************************
9+
* Copyright 2017-2019 Cypress Semiconductor Corporation
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the "License");
13+
* you may not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* http://www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an "AS IS" BASIS,
20+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
********************************************************************************/
24+
25+
#if !defined(CYCFG_H)
26+
#define CYCFG_H
27+
28+
#if defined(__cplusplus)
29+
extern "C" {
30+
#endif
31+
32+
#include "cycfg_notices.h"
33+
#include "cycfg_system.h"
34+
#include "cycfg_clocks.h"
35+
#include "cycfg_routing.h"
36+
#include "cycfg_peripherals.h"
37+
#include "cycfg_pins.h"
38+
39+
void init_cycfg_all(void);
40+
41+
42+
#if defined(__cplusplus)
43+
}
44+
#endif
45+
46+
47+
#endif /* CYCFG_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

+24
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/*******************************************************************************
2+
* File Name: cycfg.timestamp
3+
*
4+
* Description:
5+
* Sentinel file for determining if generated source is up to date.
6+
* This file was automatically generated and should not be modified.
7+
*
8+
********************************************************************************
9+
* Copyright 2017-2019 Cypress Semiconductor Corporation
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the "License");
13+
* you may not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* http://www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an "AS IS" BASIS,
20+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
********************************************************************************/
24+

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

+90
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,90 @@
1+
/*******************************************************************************
2+
* File Name: cycfg_clocks.c
3+
*
4+
* Description:
5+
* Clock configuration
6+
* This file was automatically generated and should not be modified.
7+
*
8+
********************************************************************************
9+
* Copyright 2017-2019 Cypress Semiconductor Corporation
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the "License");
13+
* you may not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* http://www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an "AS IS" BASIS,
20+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
********************************************************************************/
24+
25+
#include "cycfg_clocks.h"
26+
27+
#if defined (CY_USING_HAL)
28+
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
29+
{
30+
.type = CYHAL_RSC_CLOCK,
31+
.block_num = CYBSP_USB_CLK_DIV_HW,
32+
.channel_num = CYBSP_USB_CLK_DIV_NUM,
33+
};
34+
#endif //defined (CY_USING_HAL)
35+
#if defined (CY_USING_HAL)
36+
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
37+
{
38+
.type = CYHAL_RSC_CLOCK,
39+
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
40+
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
41+
};
42+
#endif //defined (CY_USING_HAL)
43+
#if defined (CY_USING_HAL)
44+
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
45+
{
46+
.type = CYHAL_RSC_CLOCK,
47+
.block_num = CYBSP_CSD_CLK_DIV_HW,
48+
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
49+
};
50+
#endif //defined (CY_USING_HAL)
51+
#if defined (CY_USING_HAL)
52+
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
53+
{
54+
.type = CYHAL_RSC_CLOCK,
55+
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
56+
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
57+
};
58+
#endif //defined (CY_USING_HAL)
59+
60+
61+
void init_cycfg_clocks(void)
62+
{
63+
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
64+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
65+
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
66+
#if defined (CY_USING_HAL)
67+
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
68+
#endif //defined (CY_USING_HAL)
69+
70+
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
71+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
72+
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
73+
#if defined (CY_USING_HAL)
74+
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
75+
#endif //defined (CY_USING_HAL)
76+
77+
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
78+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
79+
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
80+
#if defined (CY_USING_HAL)
81+
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
82+
#endif //defined (CY_USING_HAL)
83+
84+
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
85+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
86+
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
87+
#if defined (CY_USING_HAL)
88+
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
89+
#endif //defined (CY_USING_HAL)
90+
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

+71
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
/*******************************************************************************
2+
* File Name: cycfg_clocks.h
3+
*
4+
* Description:
5+
* Clock configuration
6+
* This file was automatically generated and should not be modified.
7+
*
8+
********************************************************************************
9+
* Copyright 2017-2019 Cypress Semiconductor Corporation
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the "License");
13+
* you may not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* http://www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an "AS IS" BASIS,
20+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
********************************************************************************/
24+
25+
#if !defined(CYCFG_CLOCKS_H)
26+
#define CYCFG_CLOCKS_H
27+
28+
#include "cycfg_notices.h"
29+
#include "cy_sysclk.h"
30+
#if defined (CY_USING_HAL)
31+
#include "cyhal_hwmgr.h"
32+
#endif //defined (CY_USING_HAL)
33+
34+
#if defined(__cplusplus)
35+
extern "C" {
36+
#endif
37+
38+
#define CYBSP_USB_CLK_DIV_ENABLED 1U
39+
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
40+
#define CYBSP_USB_CLK_DIV_NUM 0U
41+
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
42+
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
43+
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
44+
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
45+
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
46+
#define CYBSP_CSD_CLK_DIV_NUM 3U
47+
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
48+
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
49+
#define CYBSP_BT_UART_CLK_DIV_NUM 4U
50+
51+
#if defined (CY_USING_HAL)
52+
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
53+
#endif //defined (CY_USING_HAL)
54+
#if defined (CY_USING_HAL)
55+
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
56+
#endif //defined (CY_USING_HAL)
57+
#if defined (CY_USING_HAL)
58+
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
59+
#endif //defined (CY_USING_HAL)
60+
#if defined (CY_USING_HAL)
61+
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
62+
#endif //defined (CY_USING_HAL)
63+
64+
void init_cycfg_clocks(void);
65+
66+
#if defined(__cplusplus)
67+
}
68+
#endif
69+
70+
71+
#endif /* CYCFG_CLOCKS_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

+30
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
/*******************************************************************************
2+
* File Name: cycfg_notices.h
3+
*
4+
* Description:
5+
* Contains warnings and errors that occurred while generating code for the
6+
* design.
7+
* This file was automatically generated and should not be modified.
8+
*
9+
********************************************************************************
10+
* Copyright 2017-2019 Cypress Semiconductor Corporation
11+
* SPDX-License-Identifier: Apache-2.0
12+
*
13+
* Licensed under the Apache License, Version 2.0 (the "License");
14+
* you may not use this file except in compliance with the License.
15+
* You may obtain a copy of the License at
16+
*
17+
* http://www.apache.org/licenses/LICENSE-2.0
18+
*
19+
* Unless required by applicable law or agreed to in writing, software
20+
* distributed under the License is distributed on an "AS IS" BASIS,
21+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22+
* See the License for the specific language governing permissions and
23+
* limitations under the License.
24+
********************************************************************************/
25+
26+
#if !defined(CYCFG_NOTICES_H)
27+
#define CYCFG_NOTICES_H
28+
29+
30+
#endif /* CYCFG_NOTICES_H */

0 commit comments

Comments
 (0)