Make GDS workflow to include the correct files, inline readme.md

Author: cheyao

.github/workflows/docs.yaml

@@ -19,10 +19,8 @@ jobs:
       uses: actions/setup-python@v4
       with:
         python-version: '3.7.7'
-        cache: 'pip'
-    - run: pip install -r requirements.txt
+    - run: pip install requests PyYAML
 
     # fetch the Verilog from Wokwi API
     - name: fetch Verilog and build config
       run: ./configure.py --check-docs
-

.github/workflows/gds.yaml

@@ -34,8 +34,7 @@ jobs:
       uses: actions/setup-python@v4
       with:
         python-version: '3.7.7'
-        cache: 'pip'
-    - run: pip install -r requirements.txt
+    - run: pip install requests PyYAML
 
     # fetch the Verilog from Wokwi API
     - name: fetch Verilog and build config
@@ -59,7 +58,7 @@ jobs:
 
     - name: add summary
       run: ./configure.py --get-stats >> $GITHUB_STEP_SUMMARY
-  
+
     - name: populate src cache
       uses: actions/cache@v3
       with:
@@ -137,7 +136,7 @@ jobs:
 
     - name: gds2gltf
       run: |
-        python -m pip install -r requirements.txt
+        python -m pip install numpy gdspy triangle pygltflib
         cp runs/wokwi/results/final/gds/*.gds tinytapeout.gds
         python3 gds2gltf.py tinytapeout.gds
         cp tinytapeout.gds.gltf viewer/
@@ -173,7 +172,8 @@ jobs:
           path: |
             src/*
             runs/wokwi/results/final/*
-            runs/wokwi/reports/final_summary_report.csv
+            runs/wokwi/reports/metrics.csv
+            runs/wokwi/reports/synthesis/1-synthesis.AREA 0.stat.rpt
 
   pages:
     needs:

.gitignore

@@ -0,0 +1,4 @@
+.DS_Store
+.idea
+.vscode
+*.vcd

README.md

@@ -14,6 +14,13 @@ When you edit the info.yaml to choose a different ID, the [GitHub Action](.githu
 
 After that, the action uses the open source ASIC tool called [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/) to build the files needed to fabricate an ASIC.
 
+# Setup
+
+Due to Github limitations, you need to do some work to get everything to work.
+
+1. Go to Actons tab and press enable Github Actions
+2. Go to Settings tab and select Pages, then change Source from `Deploy from a branch` to `Github Actions`
+
 # What files get made?
 
 When the action is complete, you can click on the 'Actions' tab above, choose the 'gds' action and then click on the latest result.
@@ -26,8 +33,8 @@ You should see a page with the results of the build:
 
 You can also download a zipped artifact that contains:
 
-* runs/wokwi/reports/final_summary_report.csv  - CSV file with lots of details about the design
-* runs/wokwi/reports/synthesis/1-synthesis.stat.rpt.strategy4 - list of the [standard cells](https://www.zerotoasiccourse.com/terminology/standardcell/) used by your design
+* runs/wokwi/reports/metrics.csv  - CSV file with lots of details about the design
+* runs/wokwi/reports/synthesis/1-synthesis.AREA 0.stat.rpt - list of the [standard cells](https://www.zerotoasiccourse.com/terminology/standardcell/) used by your design
 * runs/wokwi/results/final/gds/user_module.gds - the final [GDS](https://www.zerotoasiccourse.com/terminology/gds2/) file needed to make your design
 
 # What next?

info.yaml

@@ -42,4 +42,3 @@ documentation:
     - segment f
     - segment g
     - none
-

requirements.txt

@@ -2,8 +2,8 @@
 // Remember to include your top module name in the info.yaml file
 `default_netname none
 
-module githubusername_top( //prepend your github username
-	input  [7:0] io_in,    //leave the port names unchanged
+module githubusername_top( // prepend your github username
+	input  [7:0] io_in,    // leave the port names unchanged
 	output [7:0] io_out);
 
 	//****Your Design Here****

src/template.v

@@ -1,3 +1,6 @@
+`include "template.v"
+`timescale 1ns/1ps
+
 module template_tb ();
     reg  [7:0] io_in;
     wire [7:0] io_out;
@@ -12,8 +15,9 @@ module template_tb ();
         #1 io_in = 8'b00000011;
         #1 io_in = 8'b00000010;
         #1 io_in = 8'b00000000;
+        $finish;
     end
 
     githubusername_top dut(.io_i(io_in),
                    .io_o(io_out));
-endmodule 
+endmodule