regs.conf

area 0x00000000 4K PRUSS
area 0x00700000 1024K DSP_L2_ROM_for_dsp
area 0x00800000 256K DSP_L2_RAM_for_dsp
area 0x00E00000 32K DSP_L1P_RAM_for_dsp
area 0x00F00000 32K DSP_L1D_RAM_for_dsp
area 0x01800000 64K DSP_Interrupt_Controller
area 0x01810000 4K DSP_Powerdown_Controller
area 0x01811000 4K DSP_Security_ID
area 0x01812000 4K DSP_Revision_ID
area 0x01820000 64K DSP_EMC
area 0x01840000 64K DSP_Memory_System
area 0x01BC0000 4K ARM_ETB_memory
area 0x01BC1000 2K ARM_ETB_reg
area 0x01BC1800 256 ARM_Ice_Crusher
area 0x01C00000 32K EDMA3_CC
area 0x01C08000 1K EDMA3_TC0
area 0x01C08400 1K EDMA3_TC1
area 0x01C10000 4K PSC 
area 0x01C11000 4K PLLC0
area 0x01C14000 4K SYSCFG0
area 0x01C20000 4K TIMER0
area 0x01C21000 4K TIMER1
area 0x01C22000 4K I2C0
area 0x01C23000 4K RTC
area 0x01C40000 4K MMC_SD0
area 0x01C41000 4K SPI0
area 0x01C42000 4K UART0
area 0x01D00000 4K McASP0_Control
area 0x01D01000 4K McASP0_AFIFO_Ctrl
area 0x01D02000 4K McASP0_Data
area 0x01D0C000 4K UART1
area 0x01D0D000 4K UART2
area 0x01D10000 2K McBSP0
area 0x01D10800 2K McBSP0_FIFO_Ctrl
area 0x01D11000 2K McBSP1
area 0x01D11800 2K McBSP1_FIFO_Ctrl
area 0x01E00000 64K USB0
area 0x01E10000 4K UHPI
area 0x01E13000 4K LCD_Controller
area 0x01E16000 4K UPP
area 0x01E17000 4K VPIF
area 0x01E18000 8K SATA
area 0x01E1A000 4K PLL1
area 0x01E1B000 4K MMCSD1
area 0x01E20000 8K EMAC_Control_Module_RAM
area 0x01E22000 4K EMAC_Control_Module_Registers
area 0x01E23000 4K EMAC_Control_Registers
area 0x01E24000 4K EMAC_MDIO_port
area 0x01E25000 4K USB1
area 0x01E26000 4K GPIO
area 0x01E27000 4K PSC1
area 0x01E28000 4K I2C1
area 0x01E2C000 4K SYSCFG1
area 0x01E30000 32K EDMA3_CC1
area 0x01E38000 1K EDMA3_TC2
area 0x01F00000 4K eHRPWM0
area 0x01F01000 4K HRPWM0
area 0x01F02000 4K eHRPWM1
area 0x01F03000 4K HRPWM1
area 0x01F06000 4K ECAP0
area 0x01F07000 4K ECAP1
area 0x01F08000 4K ECAP2
area 0x01F0C000 4K TIMER2
area 0x01F0D000 4K TIMER3
area 0x01F0E000 4K SPI1
area 0x01F10000 4K McBSP0_FIFO_Data
area 0x01F11000 4K McBSP1_FIFO_Data
area 0x11700000 1024K DSP_L2_ROM
area 0x11800000 256K DSP_L2_RAM
area 0x11E00000 32K DSP_L1P_RAM
area 0x11F00000 32K DSP_L1D_RAM
area 0x40000000 512M EMIFA_SDRAM_data_CS0
area 0x60000000 32M EMIFA_async_data_CS2
area 0x62000000 32M EMIFA_async_data_CS3
area 0x64000000 32M EMIFA_async_data_CS4
area 0x66000000 32M EMIFA_async_data_CS5
area 0x68000000 32K EMIFA_Control_Regs
area 0x80000000 128K Shared_RAM
area 0xB0000000 32K DDR2_Control_Regs
area 0xC0000000 512M DDR2_Data
area 0xFFFD0000 64K ARM_local_ROM
area 0xFFFEE000 8K ARM_Interrupt_Controller
area 0xFFFF0000 8K ARM_local_RAM

# omap-l138 data sheet table 3-2 "C674x Cache Registers"
reg 0x01840000 L2CFG L2 Cache configuration register
reg 0x01840020 L1PCFG L1P Size Cache configuration register
reg 0x01840024 L1PCC L1P Freeze Mode Cache configuration register
reg 0x01840040 L1DCFG L1D Size Cache configuration register
reg 0x01840044 L1DCC L1D Freeze Mode Cache configuration register
reg 0x01841000 EDMAWEIGHT L2 EDMA access control register
reg 0x01842000 L2ALLOC0 L2 allocation register 0
reg 0x01842004 L2ALLOC1 L2 allocation register 1
reg 0x01842008 L2ALLOC2 L2 allocation register 2
reg 0x0184200C L2ALLOC3 L2 allocation register 3
reg 0x01844000 L2WBAR L2 writeback base address register
reg 0x01844004 L2WWC L2 writeback word count register
reg 0x01844010 L2WIBAR L2 writeback invalidate base address register
reg 0x01844014 L2WIWC L2 writeback invalidate word count register
reg 0x01844018 L2IBAR L2 invalidate base address register
reg 0x0184401C L2IWC L2 invalidate word count register
reg 0x01844020 L1PIBAR L1P invalidate base address register
reg 0x01844024 L1PIWC L1P invalidate word count register
reg 0x01844030 L1DWIBAR L1D writeback invalidate base address register
reg 0x01844034 L1DWIWC L1D writeback invalidate word count register
reg 0x01844040 L1DWBAR L1D Block Writeback
reg 0x01844044 L1DWWC L1D Block Writeback
reg 0x01844048 L1DIBAR L1D invalidate base address register
reg 0x0184404C L1DIWC L1D invalidate word count register
reg 0x01845000 L2WB L2 writeback all register
reg 0x01845004 L2WBINV L2 writeback invalidate all register
reg 0x01845008 L2INV L2 Global Invalidate without writeback
reg 0x01845028 L1PINV L1P Global Invalidate
reg 0x01845040 L1DWB L1D Global Writeback
reg 0x01845044 L1DWBINV L1D Global Writeback with Invalidate
reg 0x01845048 L1DINV L1D Global Invalidate without writeback
reg 0x01848000 MAR0 Memory Attribute Registers


# from Megamodule reference guide, sect 7.5, table 7-3

reg 0x01800000 EVTFLAG0 Event flag register 0
reg 0x01800004 EVTFLAG1 Event flag register 1
reg 0x01800008 EVTFLAG2 Event flag register 2
reg 0x0180000C EVTFLAG3 Event flag register 3
reg 0x01800020 EVTSET0 Event set register 0
reg 0x01800024 EVTSET1 Event set register 1
reg 0x01800028 EVTSET2 Event set register 2
reg 0x0180002C EVTSET3 Event set register 3
reg 0x01800040 EVTCLR0 Event clear register 0
reg 0x01800044 EVTCLR1 Event clear register 1
reg 0x01800048 EVTCLR2 Event clear register 2
reg 0x0180004C EVTCLR3 Event clear register 3
reg 0x01800080 EVTMASK0 Event mask register 0
reg 0x01800084 EVTMASK1 Event mask register 1
reg 0x01800088 EVTMASK2 Event mask register 2
reg 0x0180008C EVTMASK3 Event mask register 3
reg 0x018000A0 MEVTFLAG0 Masked event flag register 0
reg 0x018000A4 MEVTFLAG1 Masked event flag register 1
reg 0x018000A8 MEVTFLAG2 Masked event flag register 2
reg 0x018000AC MEVTFLAG3 Masked event flag register 3
reg 0x01800100 INTMUX0 Interrupt mux register 0
reg 0x01800104 INTMUX1 Interrupt mux register 1
reg 0x01800108 INTMUX2 Interrupt mux register 2
reg 0x0180010C INTMUX3 Interrupt mux register 3
reg 0x01810140 AEGMUX0 Advanced event generator mux register 0
reg 0x01810144 AEGMUX1 Advanced event generator mux register 1
reg 0x01800180 INTXSTAT Interrupt exception status register
reg 0x01800184 INTXCLR Interrupt exception clear register
reg 0x01800188 INTDMASK Dropped interrupt mask register
reg 0x018000C0 EXPMASK0 Exception Mask register 0
reg 0x018000C4 EXPMASK1 Exception Mask register 1
reg 0x018000C8 EXPMASK2 Exception Mask register 2
reg 0x018000CC EXPMASK3 Exception Mask register 3
reg 0x018000E0 MEXPFLAG0 Masked Exception Flag register 0
reg 0x018000E4 MEXPFLAG1 Masked Exception Flag register 1
reg 0x018000E8 MEXPFLAG2 Masked Exception Flag register 2
reg 0x018000EC MEXPFLAG3 Masked Exception Flag register 3

# ================================================================
# PLLC0 register omap data sheet, section 7.3, table 7-2
area_regs PLLC0
areg 0 REVID PLLC0 Revision Identification Register
areg 0xE4 RSTYPE Reset Type Status Register
areg 0x100 PLLCTL PLLC0 Control Register
areg 0x104 OCSEL OBSCLK Select Register
areg 0x110 PLLM PLL Multiplier Control Register
areg 0x114 PREDIV PLLC0 Pre-Divider Control Register
areg 0x118 PLLDIV1 PLLC0 Divider 1 Register
areg 0x11C PLLDIV2 PLLC0 Divider 2 Register
areg 0x120 PLLDIV3 PLLC0 Divider 3 Register
areg 0x124 OSCDIV Oscillator Divider 1 Register (OBSCLK)
areg 0x128 POSTDIV PLL Post-Divider Control Register
areg 0x138 PLLCMD PLL Controller Command Register
areg 0x13C PLLSTAT PLL Controller Status Register
areg 0x140 ALNCTL PLLC0 Clock Align Control Register
areg 0x144 DCHANGE PLLC0 PLLDIV Ratio Change Status Register
areg 0x148 CKEN Clock Enable Control Register
areg 0x14C CKSTAT Clock Status Register
areg 0x150 SYSTAT PLLC0 SYSCLK Status Register
areg 0x160 PLLDIV4 PLLC0 Divider 4 Register
areg 0x164 PLLDIV5 PLLC0 Divider 5 Register
areg 0x168 PLLDIV6 PLLC0 Divider 6 Register
areg 0x16C PLLDIV7 PLLC0 Divider 7 Register
areg 0x1F0 EMUCNT0 Emulation Performance Counter 0 Register
areg 0x1F4 EMUCNT1 Emulation Performance Counter 1 Register


# ================================================================
# real time clock perpherial manual 
area_regs RTC
areg 0 SECOND Seconds Register                     
areg 0x4 MINUTE Minutes Register
areg 0x8 HOUR Hours Register
areg 0xC DAY Day of the Month Register
areg 0x10 MONTH Month Register
areg 0x14 YEAR Year Register
areg 0x18 DOTW Day of the Week Register
areg 0x20 ALARMSECOND Alarm Seconds Register
areg 0x24 ALARMMINUTE Alarm Minutes Register
areg 0x28 ALARMHOUR Alarm Hours Register
areg 0x2C ALARMDAY Alarm Days Register
areg 0x30 ALARMMONTH Alarm Months Register
areg 0x34 ALARMYEAR Alarm Years Register
areg 0x40 CTRL Control Register
areg 0x44 STATUS Status Register
areg 0x48 INTERRUPT Interrupt Enable Register
areg 0x4C COMPLSB Compensation (LSB) Register
areg 0x50 COMPMSB Compensation (MSB) Register
areg 0x54 OSC Oscillator Register
areg 0x60 SCRATCH0 Scratch 0 Register
areg 0x64 SCRATCH1 Scratch 1 Register
areg 0x68 SCRATCH2 Scratch 2 Register
areg 0x6C KICK0R Kick 0 Register
areg 0x70 KICK1R Kick 1 Register

# ================================================================
# timer0
area_regs TIMER0
areg 0x0 REVID Revision ID Register
areg 0x4 EMUMGT Emulation Management Register
areg 0x8 GPINTGPEN GPIO Interrupt and GPIO Enable Register
areg 0xC GPDATGPDIR GPIO Data and GPIO Direction Register
areg 0x10 TIM12 Timer Counter Register 12
areg 0x14 TIM34 Timer Counter Register 34
areg 0x18 PRD12 Timer Period Register 12
areg 0x1C PRD34 Timer Period Register 34
areg 0x20 TCR Timer Control Register
areg 0x24 TGCR Timer Global Control Register
areg 0x28 WDTCR Watchdog Timer Control Register
areg 0x34 REL12 Timer Reload Register 12
areg 0x38 REL34 Timer Reload Register 34
areg 0x3C CAP12 Timer Capture Register 12
areg 0x40 CAP34 Timer Capture Register 34
areg 0x44 INTCTLSTAT Timer Interrupt Control and Status Register
areg 0x60 CMP0 Compare Register 0
areg 0x64 CMP1 Compare Register 1
areg 0x68 CMP2 Compare Register 2
areg 0x6C CMP3 Compare Register 3
areg 0x70 CMP4 Compare Register 4
areg 0x74 CMP5 Compare Register 5
areg 0x78 CMP6 Compare Register 6
areg 0x7C CMP7 Compare Register 7

# timer1
area_regs TIMER1
areg 0x0 REVID Revision ID Register
areg 0x4 EMUMGT Emulation Management Register
areg 0x8 GPINTGPEN GPIO Interrupt and GPIO Enable Register
areg 0xC GPDATGPDIR GPIO Data and GPIO Direction Register
areg 0x10 TIM12 Timer Counter Register 12
areg 0x14 TIM34 Timer Counter Register 34
areg 0x18 PRD12 Timer Period Register 12
areg 0x1C PRD34 Timer Period Register 34
areg 0x20 TCR Timer Control Register
areg 0x24 TGCR Timer Global Control Register
areg 0x28 WDTCR Watchdog Timer Control Register
areg 0x34 REL12 Timer Reload Register 12
areg 0x38 REL34 Timer Reload Register 34
areg 0x3C CAP12 Timer Capture Register 12
areg 0x40 CAP34 Timer Capture Register 34
areg 0x44 INTCTLSTAT Timer Interrupt Control and Status Register
areg 0x60 CMP0 Compare Register 0
areg 0x64 CMP1 Compare Register 1
areg 0x68 CMP2 Compare Register 2
areg 0x6C CMP3 Compare Register 3
areg 0x70 CMP4 Compare Register 4
areg 0x74 CMP5 Compare Register 5
areg 0x78 CMP6 Compare Register 6
areg 0x7C CMP7 Compare Register 7

# timer2
area_regs TIMER2
areg 0x0 REVID Revision ID Register
areg 0x4 EMUMGT Emulation Management Register
areg 0x8 GPINTGPEN GPIO Interrupt and GPIO Enable Register
areg 0xC GPDATGPDIR GPIO Data and GPIO Direction Register
areg 0x10 TIM12 Timer Counter Register 12
areg 0x14 TIM34 Timer Counter Register 34
areg 0x18 PRD12 Timer Period Register 12
areg 0x1C PRD34 Timer Period Register 34
areg 0x20 TCR Timer Control Register
areg 0x24 TGCR Timer Global Control Register
areg 0x28 WDTCR Watchdog Timer Control Register
areg 0x34 REL12 Timer Reload Register 12
areg 0x38 REL34 Timer Reload Register 34
areg 0x3C CAP12 Timer Capture Register 12
areg 0x40 CAP34 Timer Capture Register 34
areg 0x44 INTCTLSTAT Timer Interrupt Control and Status Register
areg 0x60 CMP0 Compare Register 0
areg 0x64 CMP1 Compare Register 1
areg 0x68 CMP2 Compare Register 2
areg 0x6C CMP3 Compare Register 3
areg 0x70 CMP4 Compare Register 4
areg 0x74 CMP5 Compare Register 5
areg 0x78 CMP6 Compare Register 6
areg 0x7C CMP7 Compare Register 7

# timer3
area_regs TIMER3
areg 0x0 REVID Revision ID Register
areg 0x4 EMUMGT Emulation Management Register
areg 0x8 GPINTGPEN GPIO Interrupt and GPIO Enable Register
areg 0xC GPDATGPDIR GPIO Data and GPIO Direction Register
areg 0x10 TIM12 Timer Counter Register 12
areg 0x14 TIM34 Timer Counter Register 34
areg 0x18 PRD12 Timer Period Register 12
areg 0x1C PRD34 Timer Period Register 34
areg 0x20 TCR Timer Control Register
areg 0x24 TGCR Timer Global Control Register
areg 0x28 WDTCR Watchdog Timer Control Register
areg 0x34 REL12 Timer Reload Register 12
areg 0x38 REL34 Timer Reload Register 34
areg 0x3C CAP12 Timer Capture Register 12
areg 0x40 CAP34 Timer Capture Register 34
areg 0x44 INTCTLSTAT Timer Interrupt Control and Status Register
areg 0x60 CMP0 Compare Register 0
areg 0x64 CMP1 Compare Register 1
areg 0x68 CMP2 Compare Register 2
areg 0x6C CMP3 Compare Register 3
areg 0x70 CMP4 Compare Register 4
areg 0x74 CMP5 Compare Register 5
areg 0x78 CMP6 Compare Register 6
areg 0x7C CMP7 Compare Register 7


area_regs SYSCFG0
areg 0 REVID Revision Identification Register
areg 8 DIEIDR0 Die Identification Register 0
areg 0xc DIEIDR1 Die Identification Register 1
areg 0x10 DIEIDR2 Die Identification Register 2
areg 0x14 DIEIDR3 Die Identification Register 3
areg 0x18 DEVIDR0 Device Identification Register 0
areg 0x20 BOOTCFG Boot Configuration Register
areg 0x38 KICK0R Kick 0 Register  
areg 0x3C KICK1R Kick 1 Register
areg 0x40 HOST0CFG Host 0 Configuration Register
areg 0x44 HOST1CFG Host 1 Configuration Register
areg 0xE0 IRAWSTAT Interrupt Raw Status/Set Register
areg 0xE4 IENSTAT Interrupt Enable Status/Clear Register
areg 0xE8 IENSET Interrupt Enable Register
areg 0xEC IENCLR Interrupt Enable Clear Register
areg 0xF0 EOI End of Interrupt Register
areg 0xF4 FLTADDRR Fault Address Register
areg 0xF8 FLTSTAT Fault Status Register
areg 0x110 MSTPRI0 Master Priority 0 Register
areg 0x114 MSTPRI1 Master Priority 1 Register
areg 0x118 MSTPRI2 Master Priority 2 Register
areg 0x120 PINMUX0 Pin Multiplexing Control 0 Register
areg 0x124 PINMUX1 Pin Multiplexing Control 1 Register
areg 0x128 PINMUX2 Pin Multiplexing Control 2 Register
areg 0x12C PINMUX3 Pin Multiplexing Control 3 Register
areg 0x130 PINMUX4 Pin Multiplexing Control 4 Register
areg 0x134 PINMUX5 Pin Multiplexing Control 5 Register
areg 0x138 PINMUX6 Pin Multiplexing Control 6 Register
areg 0x13C PINMUX7 Pin Multiplexing Control 7 Register
areg 0x140 PINMUX8 Pin Multiplexing Control 8 Register
areg 0x144 PINMUX9 Pin Multiplexing Control 9 Register
areg 0x148 PINMUX10 Pin Multiplexing Control 10 Register
areg 0x14C PINMUX11 Pin Multiplexing Control 11 Register
areg 0x150 PINMUX12 Pin Multiplexing Control 12 Register
areg 0x154 PINMUX13 Pin Multiplexing Control 13 Register
areg 0x158 PINMUX14 Pin Multiplexing Control 14 Register
areg 0x15C PINMUX15 Pin Multiplexing Control 15 Register
areg 0x160 PINMUX16 Pin Multiplexing Control 16 Register
areg 0x164 PINMUX17 Pin Multiplexing Control 17 Register
areg 0x168 PINMUX18 Pin Multiplexing Control 18 Register
areg 0x16C PINMUX19 Pin Multiplexing Control 19 Register
areg 0x170 SUSPSRC Suspend Source Register
areg 0x174 CHIPSIG Chip Signal Register
areg 0x178 CHIPSIG_CLR Chip Signal Clear Register
areg 0x17C CFGCHIP0 Chip Configuration 0 Register
areg 0x180 CFGCHIP1 Chip Configuration 1 Register
areg 0x184 CFGCHIP2 Chip Configuration 2 Register
areg 0x188 CFGCHIP3 Chip Configuration 3 Register
areg 0x18C CFGCHIP4 Chip Configuration 4 Register

# ================================================================

area_regs GPIO
areg 0x00 REV Peripheral Revision
areg 0x04 RESERVED Reserved
areg 0x08 BINTEN GPIO Interrupt Per-Bank Enable
areg 0x10 DIR01 GPIO Banks 0 and 1 Direction
areg 0x14 OUT_DATA01 GPIO Banks 0 and 1 Output Data
areg 0x18 SET_DATA01 GPIO Banks 0 and 1 Set Data
areg 0x1C CLR_DATA01 GPIO Banks 0 and 1 Clear Data
areg 0x20 IN_DATA01 GPIO Banks 0 and 1 Input Data
areg 0x24 SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt
areg 0x28 CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt
areg 0x2C SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt
areg 0x30 CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt
areg 0x34 INTSTAT01 GPIO Banks 0 and 1 Interrupt Status
areg 0x38 DIR23 GPIO Banks 2 and 3 Direction
areg 0x3C OUT_DATA23 GPIO Banks 2 and 3 Output Data
areg 0x40 SET_DATA23 GPIO Banks 2 and 3 Set Data
areg 0x44 CLR_DATA23 GPIO Banks 2 and 3 Clear Data
areg 0x48 IN_DATA23 GPIO Banks 2 and 3 Input Data
areg 0x4C SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt
areg 0x50 CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt
areg 0x54 SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt
areg 0x58 CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt
areg 0x5C INTSTAT23 GPIO Banks 2 and 3 Interrupt Status
areg 0x60 DIR45 GPIO Banks 4 and 5 Direction
areg 0x64 OUT_DATA45 GPIO Banks 4 and 5 Output Data
areg 0x68 SET_DATA45 GPIO Banks 4 and 5 Set Data
areg 0x6C CLR_DATA45 GPIO Banks 4 and 5 Clear Data
areg 0x70 IN_DATA45 GPIO Banks 4 and 5 Input Data
areg 0x74 SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt
areg 0x78 CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt
areg 0x7C SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interrupt
areg 0x80 CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt
areg 0x84 INTSTAT45 GPIO Banks 4 and 5 Interrupt Status
areg 0x88 DIR67 GPIO Banks 6 and 7 Direction
areg 0x8C OUT_DATA67 GPIO Banks 6 and 7 Output Data
areg 0x90 SET_DATA67 GPIO Banks 6 and 7 Set Data
areg 0x94 CLR_DATA67 GPIO Banks 6 and 7 Clear Data
areg 0x98 IN_DATA67 GPIO Banks 6 and 7 Input Data
areg 0x9C SET_RIS_TRIG67 GPIO Banks 6 and 7 Set Rising Edge Interrupt
areg 0xA0 CLR_RIS_TRIG67 GPIO Banks 6 and 7 Clear Rising Edge Interrupt
areg 0xA4 SET_FAL_TRIG67 GPIO Banks 6 and 7 Set Falling Edge Interrupt
areg 0xA8 CLR_FAL_TRIG67 GPIO Banks 6 and 7 Clear Falling Edge Interrupt
areg 0xAC INTSTAT67 GPIO Banks 6 and 7 Interrupt Status
areg 0xB0 DIR8 GPIO Bank 8 Direction
areg 0xB4 OUT_DATA8 GPIO Bank 8 Output Data
areg 0xB8 SET_DATA8 GPIO Bank 8 Set Data
areg 0xBC CLR_DATA8 GPIO Bank 8 Clear Data
areg 0xC0 IN_DATA8 GPIO Bank 8 Input Data
areg 0xC4 SET_RIS_TRIG8 GPIO Bank 8 Set Rising Edge Interrupt
areg 0xC8 CLR_RIS_TRIG8 GPIO Bank 8 Clear Rising Edge Interrupt
areg 0xCC SET_FAL_TRIG8 GPIO Bank 8 Set Falling Edge Interrupt
areg 0xD0 CLR_FAL_TRIG8 GPIO Bank 8 Clear Falling Edge Interrupt
areg 0xD4 INTSTAT8 GPIO Bank 8 Interrupt Status

# ================================================================


fields L1PCFG mmref31
2-0 L1PMODE Defines the size of the L1P cache.

fields L1PCC mmref32
16 POPER Holds the previous value of the OPER bit.
0 OPER Controls the L1P freeze mode.

fields L1PIBAR mmref32
31-0 L1PIBAR 32-bit base address for block invalidation

fields L1PIWC mmref33
15-0 L1PIWC Word count for block invalidation.

fields L1PINV mmref33
0 I Controls the global invalidation of L1P cache

# ================================================================
fields L1DCFG mmref60
2-0 L1DMODE Defines the size of the L1D cache.

fields L1DCC mmref61
16 POPER Holds the previous value of the OPER field.
0 OPER Controls the L1D freeze mode.

fields L1DINV mmref62
0 I Controls the global invalidation of L1D cache.

fields L1DWB mmref63
0 C Controls the global writeback operation of L1D cache.

fields L1DWBINV mmref63
0 C Controls the global writeback-invalidate operation of L1D cache.

fields L1DIBAR mmref64
31-0 L1DIBAR Defines the base address for the L1D block invalidate operation.

fields L1DIWC mmref64
15-0 L1DIWC Word count for block invalidation

fields L1DWBAR mmref65
31-0 L1DWBAR Defines the base address for the L1D block writeback operation

fields L1DWIWC mmref65
15-0 L1DWIWC Word count for block invalidation

# ================================================================
fields L2CFG mmref96
27-24 NUM_MM Number of megamodules minus 1.
19-16 MMID Contains the megamodule ID number.
9 IP L1P global invalidate bit
8 ID L1D global invalidate bit
3 L2CC Controls the freeze mode
2-0 L2MODE Defines the size of L2 cache.