project created and all the essential files added to it

Author: Amirarsalan-sn

Report/Report_persian_language.pdf

@@ -0,0 +1,5 @@
+module adder (input [31:0] a, b, output [31:0] y);
+
+assign y = a+b;
+
+endmodule 

adder.sv

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+module alu (input logic [31:0] src1, src2, input logic [3:0] aluc, output logic [31:0] out, output logic zero,
+				output logic cout, overflow, sign);
+	
+	always_comb begin
+		case (aluc)
+		4'b0000: begin
+			{cout, out} = {1'b0, src1} + {1'b0, src2};
+			end
+		4'b0001: begin
+			{cout, out} = {1'b0, src1} + {1'b0, ~src2} + 9'b1;
+ 			end
+		4'b0010: begin 
+			out = src1 & src2;
+			cout = 0;
+			end
+		4'b0011: begin 
+			out = src1 | src2;
+			cout = 0;
+			end
+		4'b0100: begin // sra
+			out = $signed(src1) >>> $unsigned(src2[4:0]);
+			cout = 0;			
+			end
+		4'b0101: begin
+			if ($signed(src1) < $signed(src2))
+				out = 1;
+			else
+				out = 0;
+			cout = 0;				
+			end
+		4'b0110: begin // srl
+			out = src1 >> src2[4:0];
+			cout = 0;			
+			end
+		4'b0111: begin // sll
+			out = src1 << src2[4:0];
+			cout = 0;			
+			end
+		4'b1000: begin // sltu
+			if($unsigned(src1) < $unsigned(src2))
+				out = 1;
+			else
+				out = 0;
+			cout = 0;				
+			end
+		4'b1001: begin // xor
+			out = src1 ^ src2;
+			cout = 0;			
+		end
+		default: begin
+			out = 0;
+			cout = 0;			
+			end 
+		endcase
+		if (out==0)
+			zero = 1;
+		else
+			zero = 0;
+		sign = out[31];
+		overflow = (~((src1[31] ^ src2[31]) ^ aluc[0])) & (src1[31] ^ sign) & ~aluc[1]; 
+	end
+
+endmodule 

alu.sv

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+module aluDec (input logic [1:0] aluop,
+					input logic op5, funct7b5,
+					input logic [2:0] funct3,
+					output logic [3:0] alucontrol);
+
+	always_comb begin
+	
+		case(aluop)
+		2'b00: alucontrol = 4'b0000;
+		2'b01: alucontrol = 4'b0001;
+		2'b10: case (funct3)
+					3'b000: if({op5, funct7b5} == 2'b11)
+									alucontrol = 4'b0001;
+							  else
+									alucontrol = 4'b0000;
+					3'b001: // sll
+							  alucontrol = 4'b0111;
+					3'b010: alucontrol = 4'b0101;
+					3'b011:// sltu
+							  alucontrol = 4'b1000;
+					3'b100:// xor
+							  alucontrol = 4'b1001;
+					3'b101: if(funct7b5) // sra
+									alucontrol = 4'b0100;
+							  else // srl
+									alucontrol = 4'b0110;
+					3'b110: alucontrol = 4'b0011;
+					3'b111: alucontrol = 4'b0010;
+					default: alucontrol = 4'bx;
+				 endcase
+		default: alucontrol = 4'bx;
+		endcase
+	end
+
+endmodule 

aluDec.sv

@@ -0,0 +1,38 @@
+module auipcTb();
+
+logic clk; 
+logic reset;
+logic [31:0] WriteData, DataAdr;  
+logic MemWrite;
+
+// instantiate device to be tested 
+top dut(clk, reset, WriteData, DataAdr, MemWrite);
+
+// initialize test
+initial  
+  begin 
+	reset <= 1; # 22; reset <= 0;
+  end
+
+// generate clock to sequence tests
+always  
+  begin 
+	clk <= 1; # 5; clk <= 0; # 5;
+ end
+always @(negedge clk) begin
+	if(MemWrite) 
+  		begin 
+			if(DataAdr == 100 & WriteData == 4096)
+ 				begin
+
+					$display("Simulation succeeded"); 
+					$stop;
+				end 
+			else 
+				begin 
+					$display("Simulation failed"); 
+					$stop;
+				end
+		end
+end
+endmodule 

auipcTb.sv

@@ -0,0 +1,2 @@
+#0 auipc x2, 1		//x2 = 00000000000000000001000000000000 = 0x1000 = 4096 | 00000000000000000001-00010-0010111 | 0x00001117
+#4 sw x2, 100(x0)		//mem[100] = 0x1000 = 4096 | 0000011-00010-00000-010-00100-0100011 | 0x06202223

auipctest.s

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+00001117
+06202223

auipctest.txt

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+module branchDec(input logic [6:0] op,
+					  input logic [2:0] funct3,
+					  input logic branch,
+					  output logic beq, bne, blt, bge, bltu, bgeu);
+
+		assign beq = (op == 7'b1100011) & (funct3 == 3'b000) & branch ;
+		assign bne = (op == 7'b1100011) & (funct3 == 3'b001) & branch ;
+		assign blt = (op == 7'b1100011) & (funct3 == 3'b100) & branch ;
+		assign bge = (op == 7'b1100011) & (funct3 == 3'b101) & branch ;
+		assign bltu = (op == 7'b1100011) & (funct3 == 3'b110) & branch ;
+		assign bgeu = (op == 7'b1100011) & (funct3 == 3'b111) & branch ;
+					
+endmodule  

branchDec.sv

@@ -0,0 +1,29 @@
+module controller(input logic clk,
+						input logic reset,
+						input logic [6:0] op,
+						input logic [2:0] funct3,
+						input logic funct7b5,
+						input logic zero, cout, overflow, sign,
+						output logic [2:0] immsrc,
+						output logic [1:0] alusrca, alusrcb,
+						output logic [1:0] resultsrc,
+						output logic adrsrc,
+						output logic [3:0] alucontrol,
+						output logic irwrite, pcwrite,
+						output logic regwrite, memwrite);
+						
+	logic beq, bne, blt, bge, bltu, bgeu, branch, pcupdate;
+	logic [1:0] aluop;
+	
+	fsm MainFSM(clk, reset, op, branch, pcupdate, regwrite, 
+					memwrite, irwrite, resultsrc, alusrcb, alusrca, adrsrc, aluop);
+	aluDec AluDecoder(aluop, op[5], funct7b5, funct3, alucontrol);
+	instrDec InstrDecoder(op, immsrc);
+	branchDec BranchDecoder(op, funct3, branch, beq, bne, blt, bge, bltu, bgeu); 
+	
+	assign pcwrite = (beq & zero) | (bne & ~zero) | (bgeu & cout) | (bltu & ~cout) 
+	| (bge & (sign == overflow)) | (blt & (sign != overflow)) | pcupdate;
+	
+	
+	
+endmodule 

controller.sv

@@ -0,0 +1,104 @@
+// controller.tv
+
+// Place in same computer directory as controller.sv to test your multicycle controller.
+// Checks all supported instructions (add,sub,and,or,slt,lw,addi,sw,beq,jal).
+
+
+// ========== Test Vector Format ==========
+// Op[6:0] Funct3[2:0] Funct7b5 Zero _ ImmSrc[1:0] ALUSrcA[1:0] ALUSrcB[1:0] ResultSrc[1:0] AdrSrc ALUControl[2:0] IRWrite PCWrite RegWrite MemWrite
+
+
+// ========== Test R-type instructions (add,sub,or,and,slt) ==========
+// Each instruction takes four cycles to execute
+// Op[6:0] Funct3[2:0] Funct7b5 Zero _ ImmSrc[1:0] ALUSrcA[1:0] ALUSrcB[1:0] ResultSrc[1:0] AdrSrc ALUControl[2:0] IRWrite PCWrite RegWrite MemWrite
+//
+// add
+0110011_000_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 000)
+0110011_000_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 001)
+0110011_000_0_0__XX_10_00_XX_X_000_0_0_0_0 // ExecuteR (Vect 002)
+0110011_000_0_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 003)
+//
+// sub
+0110011_000_1_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 004)
+0110011_000_1_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 005)
+0110011_000_1_0__XX_10_00_XX_X_001_0_0_0_0 // ExecuteR (Vect 006)
+0110011_000_1_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 007)
+//
+// or
+0110011_110_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 008)
+0110011_110_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 009)
+0110011_110_0_0__XX_10_00_XX_X_011_0_0_0_0 // ExecuteR (Vect 010)
+0110011_110_0_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 011)
+//
+// and
+0110011_111_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 012)
+0110011_111_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 013)
+0110011_111_0_0__XX_10_00_XX_X_010_0_0_0_0 // ExecuteR (Vect 014)
+0110011_111_0_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 015)
+//
+// slt
+0110011_010_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 016)
+0110011_010_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 017)
+0110011_010_0_0__XX_10_00_XX_X_101_0_0_0_0 // ExecuteR (Vect 018)
+0110011_010_0_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 019)
+
+
+// ========== Test I-type instructions (lw, addi) ==========
+// lw takes five cycles to execute, addi takes four cycles
+// Op[6:0] Funct3[2:0] Funct7b5 Zero _ ImmSrc[1:0] ALUSrcA[1:0] ALUSrcB[1:0] ResultSrc[1:0] AdrSrc ALUControl[2:0] IRWrite PCWrite RegWrite MemWrite
+//
+// lw
+0000011_010_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 020)
+0000011_010_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 021)
+0000011_010_0_0__00_10_01_XX_X_000_0_0_0_0 // MemAdr   (Vect 022)
+0000011_010_0_0__XX_XX_XX_00_1_XXX_0_0_0_0 // MemRead  (Vect 023)
+0000011_010_0_0__XX_XX_XX_01_X_XXX_0_0_1_0 // MemWB    (Vect 024)
+//
+// addi
+0010011_000_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 025)
+0010011_000_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 026)
+0010011_000_0_0__00_10_01_XX_X_000_0_0_0_0 // ExecuteI (Vect 027)
+0010011_000_0_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 028)
+//
+// addi (funct7b5 is now just data and shouldn't affect execution)
+0010011_000_1_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 029)
+0010011_000_1_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 030)
+0010011_000_1_0__00_10_01_XX_X_000_0_0_0_0 // ExecuteI (Vect 031)
+0010011_000_1_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 032)
+
+
+// ========== Test S-type instructions (sw) ==========
+// sw takes four cycles to execute
+// Op[6:0] Funct3[2:0] Funct7b5 Zero _ ImmSrc[1:0] ALUSrcA[1:0] ALUSrcB[1:0] ResultSrc[1:0] AdrSrc ALUControl[2:0] IRWrite PCWrite RegWrite MemWrite
+//
+// sw
+0100011_010_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 033)
+0100011_010_0_0__XX_XX_XX_XX_X_XXX_0_0_0_0 // Decode   (Vect 034)
+0100011_010_0_0__01_10_01_XX_X_000_0_0_0_0 // MemAdr   (Vect 035)
+0100011_010_0_0__XX_XX_XX_00_1_XXX_0_0_0_1 // MemWrite (Vect 036)
+
+
+// ========== Test B-type instructions (beq) ==========
+// beq takes three cycles to execute
+// Op[6:0] Funct3[2:0] Funct7b5 Zero _ ImmSrc[1:0] ALUSrcA[1:0] ALUSrcB[1:0] ResultSrc[1:0] AdrSrc ALUControl[2:0] IRWrite PCWrite RegWrite MemWrite
+//
+// beq (branch not taken because ALU returns Zero=0 indicating inequality)
+1100011_000_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 037)
+1100011_000_0_0__10_01_01_XX_X_000_0_0_0_0 // Decode   (Vect 038)
+1100011_000_0_0__XX_10_00_00_X_001_0_0_0_0 // BEQ      (Vect 039)
+//
+// beq (branch taken because ALU returns Zero=1 indicating equality)
+1100011_000_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 040)
+1100011_000_0_0__10_01_01_XX_X_000_0_0_0_0 // Decode   (Vect 041)
+1100011_000_0_1__XX_10_00_00_X_001_0_1_0_0 // BEQ      (Vect 042)
+
+
+// ========== Test J-type instructions (jal) ==========
+// jal takes four cycles to execute
+// Op[6:0] Funct3[2:0] Funct7b5 Zero _ ImmSrc[1:0] ALUSrcA[1:0] ALUSrcB[1:0] ResultSrc[1:0] AdrSrc ALUControl[2:0] IRWrite PCWrite RegWrite MemWrite
+//
+// jal
+1101111_000_0_0__XX_00_10_10_0_000_1_1_0_0 // Fetch    (Vect 043)
+1101111_000_0_0__11_01_01_XX_X_000_0_0_0_0 // Decode   (Vect 044)
+1101111_000_0_0__XX_01_10_00_X_000_0_1_0_0 // JAL      (Vect 045)
+1101111_000_0_0__XX_XX_XX_00_X_XXX_0_0_1_0 // ALUWB    (Vect 046)

controller.tv

@@ -0,0 +1,47 @@
+module dataPath (input logic clk, reset,
+					  input logic [2:0] ImmSrc, 
+					  input logic [3:0] ALUControl, 
+					  input logic [1:0] ResultSrc, 
+					  input logic IRWrite,
+					  input logic RegWrite,
+					  input logic [1:0] ALUSrcA, ALUSrcB, 
+					  input logic AdrSrc, 
+					  input logic PCWrite,  
+					  input logic [31:0] ReadData,
+					  output logic Zero, cout, overflow, sign, 
+					  output logic [31:0] Adr, 
+					  output logic [31:0] WriteData,
+					  output logic [31:0] instr);
+
+		 
+logic [31:0] Result , ALUOut, ALUResult;
+logic [31:0] RD1, RD2, A , SrcA, SrcB, Data;
+logic [31:0] ImmExt;
+logic [31:0] PC, OldPC;
+
+
+//pc
+flopenr #(32) pcFlop(clk, reset, PCWrite, Result, PC);
+
+
+//regFile
+regFile rf(clk, RegWrite, instr[19:15], instr[24:20], instr[11:7], Result, RD1, RD2); 
+extend ext(instr[31:7], ImmSrc, ImmExt);
+flopr #(32) regF( clk, reset, RD1, A);
+flopr #(32) regF_2( clk, reset, RD2, WriteData);
+
+
+//alu
+mux3 #(32) srcAmux(PC, OldPC, A, ALUSrcA, SrcA);
+mux3 #(32) srcBmux(WriteData, ImmExt, 32'd4, ALUSrcB, SrcB);
+alu alu(SrcA, SrcB, ALUControl, ALUResult, Zero, cout, overflow, sign);
+flopr #(32) aluReg (clk, reset, ALUResult, ALUOut);
+mux4 #(32) resultMux(ALUOut, Data, ALUResult, ImmExt, ResultSrc, Result );
+
+//mem
+mux2 #(32) adrMux(PC, Result, AdrSrc, Adr);
+flopenr #(32) memFlop1(clk, reset, IRWrite, PC, OldPC); 
+flopenr #(32) memFlop2(clk, reset, IRWrite, ReadData, instr);
+flopr #(32) memDataFlop(clk, reset, ReadData, Data);
+
+endmodule

dataPath.sv

@@ -0,0 +1,22 @@
+module experiment(input logic [2:0] a, b);
+
+	always_comb begin
+		
+		if ($signed(a) < $signed(b))
+			$display("use $signed for signed values , signed a < signed b");
+		if ($signed(a) > $signed(b))
+			$display("use $signed for signed values , signed a > signed b");
+		if($unsigned(a) > $unsigned(b))
+			$display("use $unsigned for unsigned values, unsigned a > unsigned b");
+		if($unsigned(a) < $unsigned(b))
+			$display("use $unsigned for unsigned values, unsigned a < unsigned b");
+		if(a > b)
+			$display("a>b");
+		else
+			$display("a<b");
+		$display("go fuck yourself");
+		
+	end
+
+
+endmodule 

experimenting.sv

@@ -0,0 +1,17 @@
+module extend (input logic [31:7] instr, input logic [2:0] immsrc, output logic [31:0] immext);
+
+	always_comb
+		case(immsrc) //controller produces immsrc signal
+			//I
+			3'b000: immext = {{20{instr[31]}}, instr[31:20]};
+			//S
+			3'b001: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
+			//B
+			3'b010: immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
+			//J
+			3'b011: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+			//U
+			3'b100: immext = {instr[31:12], 12'b0};
+			default: immext = 32'bx; // undefined ? ?
+		endcase
+endmodule