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ArchfxArchfx
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Optimizations to the algorithm
1 parent d491c9f commit 9565dd4

10 files changed

+54
-42
lines changed

‎DepthMap.bit

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‎DepthMap_160x120.bit

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‎DepthMap_320x240_8bit_colour.bit

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‎DepthMap_Disparity+Avg.bit

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‎DepthMap_320x240_8bit_colour_AEC_0.bit ‎DepthMap_Exp_SSD_fixed.bit

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‎DepthMap_recti.bit

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‎depthMap.runs/impl_1/DepthMap.bit

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‎depthMap.srcs/sources_1/imports/disparity_generator.vhd

+42-39
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ end disparity_generator;
5656

5757
architecture Behavioral of disparity_generator is
5858

59-
type CacheArray is array(0 to WIDTH*fetchBlock-1) of std_logic_vector(3 downto 0);
59+
type CacheArray is array(0 to WIDTH*fetchBlock+1) of std_logic_vector(3 downto 0);
6060
signal org_L : CacheArray; --temporary storage for Left image
6161
signal org_R : CacheArray; --temporary storage for Right image
6262

@@ -80,39 +80,39 @@ begin
8080

8181
with cacheManager select
8282
left_right_addr <= readreg when "0000",
83-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock, readreg'length)) when "0001",
84-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2, readreg'length)) when "0010",
85-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3, readreg'length)) when "0011",
86-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*4, readreg'length)) when "0100",
87-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*5, readreg'length)) when "0101",
88-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*6, readreg'length)) when "0110",
89-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*7, readreg'length)) when "0111",
90-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*8, readreg'length)) when "1000",
91-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*9, readreg'length)) when "1001",
92-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*10, readreg'length)) when "1010",
93-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*11, readreg'length)) when "1011",
94-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*12, readreg'length)) when "1100",
95-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*13, readreg'length)) when "1101",
96-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*14, readreg'length)) when "1110",
97-
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*15, readreg'length)) when "1111";
83+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock-WIDTH, readreg'length)) when "0001",
84+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2-WIDTH, readreg'length)) when "0010",
85+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3-WIDTH, readreg'length)) when "0011",
86+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*4-WIDTH, readreg'length)) when "0100",
87+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*5-WIDTH, readreg'length)) when "0101",
88+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*6-WIDTH, readreg'length)) when "0110",
89+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*7-WIDTH, readreg'length)) when "0111",
90+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*8-WIDTH, readreg'length)) when "1000",
91+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*9-WIDTH, readreg'length)) when "1001",
92+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*10-WIDTH, readreg'length)) when "1010",
93+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*11-WIDTH, readreg'length)) when "1011",
94+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*12-WIDTH, readreg'length)) when "1100",
95+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*13-WIDTH, readreg'length)) when "1101",
96+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*14-WIDTH, readreg'length)) when "1110",
97+
readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*15-WIDTH, readreg'length)) when "1111";
9898

9999
with cacheManager select
100-
dOUT_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) when "000",
101-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock, dOUT_addr'length)) when "0001",
102-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2, dOUT_addr'length)) when "0010",
103-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3, dOUT_addr'length)) when "0011",
104-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*4, dOUT_addr'length)) when "0100",
105-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*5, dOUT_addr'length)) when "0101",
106-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*6, dOUT_addr'length)) when "0110",
107-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*7, dOUT_addr'length)) when "0111",
108-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*8, dOUT_addr'length)) when "1000",
109-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*9, dOUT_addr'length)) when "1001",
110-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*10, dOUT_addr'length)) when "1010",
111-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*11, dOUT_addr'length)) when "1011",
112-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*12, dOUT_addr'length)) when "1100",
113-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*13, dOUT_addr'length)) when "1101",
114-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*14, dOUT_addr'length)) when "1110",
115-
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*15, dOUT_addr'length)) when "1111";
100+
dOUT_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) when "000",
101+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock, dOUT_addr'length)) when "0001",
102+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2, dOUT_addr'length)) when "0010",
103+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3, dOUT_addr'length)) when "0011",
104+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*4, dOUT_addr'length)) when "0100",
105+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*5, dOUT_addr'length)) when "0101",
106+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*6, dOUT_addr'length)) when "0110",
107+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*7, dOUT_addr'length)) when "0111",
108+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*8, dOUT_addr'length)) when "1000",
109+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*9, dOUT_addr'length)) when "1001",
110+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*10, dOUT_addr'length)) when "1010",
111+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*11, dOUT_addr'length)) when "1011",
112+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*12, dOUT_addr'length)) when "1100",
113+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*13, dOUT_addr'length)) when "1101",
114+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*14, dOUT_addr'length)) when "1110",
115+
std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*15, dOUT_addr'length)) when "1111";
116116

117117
--with cacheManager select
118118
-- left_right_addr <= readreg when "00",
@@ -135,7 +135,7 @@ avg_reg_en <= not doneFetch;
135135
caching_process: process (HCLK) begin
136136
if rising_edge(HCLK) then
137137
if doneFetch='0' then
138-
if unsigned(readreg)<WIDTH*fetchBlock then -- replace fetchBlock with height if fetchBlock concept is removed
138+
if unsigned(readreg)<WIDTH*fetchBlock+2*WIDTH then -- replace fetchBlock with height if fetchBlock concept is removed
139139
org_L(to_integer(unsigned(readreg)))<= left_in;
140140
org_R(to_integer(unsigned(readreg)))<= right_in;
141141
avg_out<=std_logic_vector(unsigned(left_in) + unsigned(right_in)/2);
@@ -154,7 +154,7 @@ Image_process: process (CLK_MAIN) begin
154154
doneFetch <='1';
155155
end if;
156156
if doneFetch='1' then
157-
if unsigned(data_count)<WIDTH*fetchBlock then -- replace fetchBlock with height if fetchBlock concept is removed
157+
if unsigned(data_count)<WIDTH*fetchBlock+WIDTH then -- replace fetchBlock with height if fetchBlock concept is removed
158158
if (offsetfound='1') then
159159
if(col = WIDTH - 1) then
160160
col <= (others => '0');
@@ -186,9 +186,9 @@ Image_process: process (CLK_MAIN) begin
186186
-- end if;
187187
else
188188
cacheManager<=cacheManager+"1"; --Comment this if remove fetchBlock concept
189-
data_count <= (others => '0');
189+
data_count <= std_logic_vector(to_unsigned(WIDTH,data_count'length));
190190
doneFetch <='0';
191-
row<=(others => '0');
191+
row<=std_logic_vector(to_unsigned(1,row'length));
192192
end if;
193193

194194
end if;
@@ -200,8 +200,7 @@ SSD_calc_process: process (CLK_MAIN) begin
200200
if rising_edge(CLK_MAIN) then
201201
SSD_calc<='0';
202202
if (offsetping='1') then
203-
ssd <= std_logic_vector
204-
(to_unsigned(
203+
ssd <= std_logic_vector(to_unsigned(
205204
(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 -to_integer(unsigned(offset))))))
206205
+(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 -to_integer(unsigned(offset))))))
207206
+(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 -to_integer(unsigned(offset))))))
@@ -226,7 +225,11 @@ Image_write_process: process (offsetfound,HCLK) begin
226225
wr_en<='1';
227226
-- dOUT<=std_logic_vector(to_unsigned(to_integer((unsigned(best_offset)-minoffset)*4),dOUT'length));
228227
-- dOUT<=std_logic_vector(to_unsigned(to_integer(unsigned(best_offset)),dOUT'length));
229-
dOUT<=std_logic_vector(to_unsigned(to_integer((unsigned(best_offset))-minoffset)*(255/(maxoffset-minoffset)),dOUT'length));
228+
-- if to_integer(unsigned(best_offset)) > 10 then
229+
dOUT<=(std_logic_vector(to_unsigned(to_integer((unsigned(best_offset))-minoffset)*(255/(maxoffset-minoffset)),dOUT'length)));
230+
-- else
231+
-- dOUT<= "00000000";
232+
-- end if;
230233
-- dOUT<=std_logic_vector(unsigned(org_L((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))))+unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col))))/2);
231234
else
232235
wr_en<='0';

‎depthMap.srcs/sources_1/imports/ov7670_registers_left.vhd

+11-2
Original file line numberDiff line numberDiff line change
@@ -20,9 +20,16 @@ end ov7670_registers_left;
2020
architecture Behavioral of ov7670_registers_left is
2121
signal sreg : std_logic_vector(15 downto 0);
2222
signal address : std_logic_vector(7 downto 0) := (others => '0');
23+
signal AECH : std_logic_vector(7 downto 0);
24+
signal AECHH : std_logic_vector(5 downto 0);
25+
signal COM1 : std_logic_vector(1 downto 0);
26+
2327
begin
2428
command <= sreg;
2529
with sreg select finished <= '1' when x"FFFF", '0' when others;
30+
AECHH <= "000000";--exposure(15 downto 10);
31+
AECH <= "11110000";--exposure(9 downto 2); --8 was higher 1111 was too much
32+
COM1 <= (others => '0');--exposure(1 downto 0);
2633

2734
process(clk)
2835
begin
@@ -42,7 +49,7 @@ begin
4249
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
4350

4451
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
45-
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
52+
when x"07" => sreg <= "01000000000000" & COM1 ; -- COM1 no CCIR601
4653
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
4754
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
4855
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
@@ -108,8 +115,10 @@ begin
108115

109116
when x"36" => sreg <= x"b382";
110117
when x"37" => sreg <= x"b80a";
111-
when x"38" => sreg <= x"138e";--x"138f"; -- COM8 - AGC switched off 138f for default, White balance
118+
when x"38" => sreg <= x"138f";--x"138f"; -- COM8 - AGC switched off 138f for default, White balance
112119
when x"39" => sreg <= x"4200"; -- COM17 - Color bar removed
120+
when x"3A" => sreg <= x"10" & AECH;
121+
when x"3B" => sreg <= "0111000000" & AECHH;
113122
-- when x"10" => sreg <= x"703a"; -- SCALING_XSC
114123
-- when x"11" => sreg <= x"7135"; -- SCALING_YSC
115124
-- when x"12" => sreg <= x"7200"; -- SCALING_DCWCTR -- zzz was 11

‎depthMap.srcs/sources_1/imports/ov7670_registers_right.vhd

+1-1
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ begin
116116

117117
when x"36" => sreg <= x"b382";
118118
when x"37" => sreg <= x"b80a";
119-
when x"38" => sreg <= x"138e";--x"138f"; -- COM8 - AGC switched off 138f for default, White balance
119+
when x"38" => sreg <= x"138f";--x"138f"; -- COM8 - AGC switched off 138f for default, White balance
120120
when x"39" => sreg <= x"4200"; -- COM17 - Color bar removed
121121
when x"3A" => sreg <= x"10" & AECH;
122122
when x"3B" => sreg <= "0111000000" & AECHH;

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