compile to verilog, convert function to function, but not to modules.

[Yuecheng-CAM]

Hi,

I find when I compile bluespec to Verilog, I find the functions in bluespec got compiled to verilog modules, but not verilog functions. I'm wondering is there a flag/option to specify compile bluespec functions to verilog functions. Thanks

[rsnikhil]

No, there is no way to preserve a BSV function as a Verilog function.

All BSV functions are normally inlined, and disappear in the generated Verilog.

But see also "Section 14.1.1 noinline" in the BSV Language Reference Guide. This does not do exactly what you're asking, but it does create a single Verilog module with the function as its only method. The function is not inlined at the invocation sites; instead the Verilog module is instantiated and the method is invoked.