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ka10_pmp.c
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/* PMP disk controller interface for WAITS.
Copyright (c) 2017-2020, Richard Cornwell
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Structure of a disk. See Hercules CKD disks.
Numbers are stored least to most significant.
Devid = "CKD_P370"
uint8 devid[8] device header.
uint32 heads number of heads per cylinder
uint32 tracksize size of track
uint8 devtype Hex code of last two digits of device type.
uint8 fileseq always 0.
uint16 highcyl highest cylinder.
uint8 resv[492] pad to 512 byte block
Each Track has:
uint8 bin Track header.
uint16 cyl Cylinder number
uint16 head Head number.
Each Record has:
uint16 cyl Cylinder number <- tpos
uint16 head Head number
uint8 rec Record id.
uint8 klen Length of key
uint16 dlen Length of data
uint8 key[klen] Key data.
uint8 data[dlen] Data len.
cpos points to where data is actually read/written from
Pad to being track to multiple of 512 bytes.
Last record has cyl and head = 0xffffffff
*/
#include "kx10_defs.h"
#ifndef NUM_DEVS_PMP
#define NUM_DEVS_PMP 0
#endif
#if (NUM_DEVS_PMP > 0)
#define UNIT_V_TYPE (UNIT_V_UF + 0)
#define UNIT_TYPE (0xf << UNIT_V_TYPE)
#define GET_TYPE(x) ((UNIT_TYPE & (x)) >> UNIT_V_TYPE)
#define SET_TYPE(x) (UNIT_TYPE & ((x) << UNIT_V_TYPE))
#define UNIT_DASD UNIT_ATTABLE | UNIT_DISABLE | UNIT_ROABLE | \
UNIT_FIX | SET_TYPE(6)
#define UNIT_V_ADDR (UNIT_V_TYPE + 4)
#define UNIT_ADDR_MASK (0xff << UNIT_V_ADDR)
#define GET_UADDR(x) ((UNIT_ADDR_MASK & x) >> UNIT_V_ADDR)
#define UNIT_ADDR(x) ((x) << UNIT_V_ADDR)
#define NUM_UNITS_PMP 8
#define PMP_DEV 0500
#define CMD u3
/* u3 */
#define DK_NOP 0x03 /* Nop operation */
#define DK_RELEASE 0x17 /* Release from channel */
#define DK_RESTORE 0x13 /* Restore */
#define DK_SEEK 0x07 /* Seek */
#define DK_SEEKCYL 0x0B /* Seek Cylinder */
#define DK_SEEKHD 0x1B /* Seek Head */
#define DK_SETMSK 0x1f /* Set file mask */
#define DK_SPACE 0x0f /* Space record */
#define DK_SRCH_HAEQ 0x39 /* Search HA equal */
#define DK_SRCH_IDEQ 0x31 /* Search ID equal */
#define DK_SRCH_IDGT 0x51 /* Search ID greater */
#define DK_SRCH_IDGE 0x71 /* Search ID greater or equal */
#define DK_SRCH_KYEQ 0x29 /* Search Key equal */
#define DK_SRCH_KYGT 0x49 /* Search Key greater */
#define DK_SRCH_KYGE 0x69 /* Search Key greater or equal */
#define DK_RD_IPL 0x02 /* Read IPL record */
#define DK_RD_HA 0x1A /* Read home address */
#define DK_RD_CNT 0x12 /* Read count */
#define DK_RD_R0 0x16 /* Read R0 */
#define DK_RD_D 0x06 /* Read Data */
#define DK_RD_KD 0x0e /* Read key and data */
#define DK_RD_CKD 0x1e /* Read count, key and data */
#define DK_WR_HA 0x19 /* Write home address */
#define DK_WR_R0 0x15 /* Write R0 */
#define DK_WR_D 0x05 /* Write Data */
#define DK_WR_KD 0x0d /* Write key and data */
#define DK_WR_CKD 0x1d /* Write count, key and data */
#define DK_WR_SCKD 0x01 /* Write special count, key and data */
#define DK_ERASE 0x11 /* Erase to end of track */
#define DK_RD_SECT 0x22 /* Read sector counter */
#define DK_SETSECT 0x23 /* Set sector */
#define DK_MT 0x80 /* Multi track flag */
#define DK_INDEX 0x00100 /* Index seen in command */
#define DK_NOEQ 0x00200 /* Not equal compare */
#define DK_HIGH 0x00400 /* High compare */
#define DK_PARAM 0x00800 /* Parameter in u4 */
#define DK_MSET 0x01000 /* Mode set command already */
#define DK_SHORTSRC 0x02000 /* Last search was short */
#define DK_SRCOK 0x04000 /* Last search good */
#define DK_CYL_DIRTY 0x08000 /* Current cylinder dirty */
#define DK_DONE 0x10000 /* Write command done, zero fill */
#define DK_INDEX2 0x20000 /* Second index seen */
#define DK_ATTN 0x40000 /* Device has attention set */
#define DK_MSK_INHWR0 0x00 /* Inhbit writing of HA/R0 */
#define DK_MSK_INHWRT 0x40 /* Inhbit all writes */
#define DK_MSK_ALLWRU 0x80 /* Allow all updates */
#define DK_MSK_ALLWRT 0xc0 /* Allow all writes */
#define DK_MSK_WRT 0xc0 /* Write mask */
#define DK_MSK_SKALLSKR 0x00 /* Allow all seek/recal */
#define DK_MSK_SKALLCLY 0x08 /* Allow cyl/head only */
#define DK_MSK_SKALLHD 0x10 /* Allow head only */
#define DK_MSK_SKNONE 0x18 /* Allow no seeks */
#define DK_MSK_SK 0x18 /* Seek mask */
#define POS u4
/* u4 */
/* Holds the current track and head */
#define DK_V_TRACK 8
#define DK_M_TRACK 0x3ff00 /* Max 1024 cylinders */
#define DK_V_HEAD 0
#define DK_M_HEAD 0xff /* Max 256 heads */
#define SENSE u5
/* u5 */
/* Sense byte 0 */
#define SNS_CMDREJ 0x80 /* Command reject */
#define SNS_INTVENT 0x40 /* Unit intervention required */
#define SNS_BUSCHK 0x20 /* Parity error on bus */
#define SNS_EQUCHK 0x10 /* Equipment check */
#define SNS_DATCHK 0x08 /* Data Check */
#define SNS_OVRRUN 0x04 /* Data overrun */
#define SNS_TRKCND 0x02 /* Track Condition */
#define SNS_SEEKCK 0x01 /* Seek Check */
/* Sense byte 1 */
#define SNS_DCCNT 0x80 /* Data Check Count */
#define SNS_TRKOVR 0x40 /* Track Overrun */
#define SNS_ENDCYL 0x20 /* End of Cylinder */
#define SNS_INVSEQ 0x10 /* Invalid Sequence */
#define SNS_NOREC 0x08 /* No record found */
#define SNS_WRP 0x04 /* Write Protect */
#define SNS_ADDR 0x02 /* Missing Address Mark */
#define SNS_OVRINC 0x01 /* Overflow Incomplete */
/* Sense byte 2 */
#define SNS_BYTE2 0x00 /* Diags Use */
/* Sense byte 3 */
#define SNS_BYTE3 0x00 /* Diags Use */
/* saved in state field of data */
/* Record position, high 4 bits, low internal short count */
#define DK_POS_INDEX 0x0 /* At Index Mark */
#define DK_POS_HA 0x1 /* In home address (c) */
#define DK_POS_CNT 0x2 /* In count (c) */
#define DK_POS_KEY 0x3 /* In Key area */
#define DK_POS_DATA 0x4 /* In Data area */
#define DK_POS_AM 0x5 /* Address mark before record */
#define DK_POS_END 0x8 /* Past end of data */
#define DK_POS_SEEK 0xF /* In seek */
#define LASTCMD u6
/* u6 holds last command */
/* Held in ccyl entry */
#define DATAPTR up7
/* Pointer held in up7 */
struct pmp_t
{
uint8 *cbuf; /* Cylinder buffer */
uint32 cpos; /* Position of head of cylinder in file */
uint32 tstart; /* Location of start of track */
uint16 ccyl; /* Current Cylinder number */
uint16 cyl; /* Cylinder head at */
uint16 tpos; /* Track position */
uint16 rpos; /* Start of current record */
uint16 dlen; /* remaining in data */
uint32 tsize; /* Size of one track include rounding */
uint8 state; /* Current state */
uint8 klen; /* remaining in key */
uint8 filemsk; /* Current file mask */
uint8 rec; /* Current record number */
uint16 count; /* Remaining in current operation */
};
/* PDP10 CONO/CONI and DATA bits */
/* CONI 500 bits */
#define NXM_ERR 00200000000000LL /* Non-existent memory */
#define CHA_ERR 00100000000000LL /* Data chaining error */
#define SEL_ERR 00040000000000LL /* Selection error */
#define LST_ADDR 00037700000000LL /* Last address used */
#define PAR1_ERR 00000040000000LL /* Parity error control */
#define PAR2_ERR 00000020000000LL /* Parity error memory */
#define IDLE 00000010100000LL /* Channel idle */
#define INT_SEL 00000004000000LL /* Initial selection state */
#define REQ_SEL 00000002000000LL /* Device requestion select */
#define TRANS 00000001000000LL /* Transfer in progress */
#define PAR_ERR 00000000400000LL /* Parity error */
#define HOLD_EMPTY 00000000200000LL /* Command hold empty */
#define UNU_END 00000000040000LL /* Unusual end */
#define NEW_STS 00000000020000LL /* New status */
#define ATTN 00000000010000LL /* Attention */
#define ST_MOD 00000000004000LL /* Status modifier */
#define CTL_END 00000000002000LL /* Control unit end */
#define BSY 00000000001000LL /* Device is busy */
#define CHN_END 00000000000400LL /* Channel end */
#define DEV_END 00000000000200LL /* Device end */
#define UNIT_CHK 00000000000100LL /* Unit check */
#define UNIT_EXP 00000000000040LL /* Unit exception */
#define PI_ACT 00000000000020LL /* PI channel active */
#define PIA 00000000000007LL /* PI channel */
#define STS_MASK 00000000017740LL /* Status bits to clear */
/* CONO 500 bits */
#define IRQ_ERROR 00000000400000LL /* Disk or Core parity error */
#define IRQ_EMPTY 00000000200000LL /* Command hold empty */
#define IRQ_IDLE 00000000100000LL /* Channel is idle */
#define IRQ_UEND 00000000040000LL /* Unusual end */
#define IRQ_NSTS 00000000020000LL /* New Status */
#define IRQ_STS 00000000017740LL /* Status bits set */
/* DATAO 500 is -Word Count, Address */
/* DATAI 500 is Current Address */
/* CONI 504 */
#define OP1 000000010000LL /* Channel in operation */
#define DAT_CHAIN 000000004000LL /* Data Chaining enabled */
#define WCMA_LD 000000002000LL /* WCMA hold register full */
#define CMD_LD 000000001000LL /* Command hold loaded */
#define IDLE_CH 000000000400LL /* Channel is idle */
#define REQ_CH 000000000200LL /* Request for channel */
#define IS_CH 000000000100LL /* Initial select state */
#define TRANS_CH 000000000040LL /* Tranfer in progress */
#define CMD_EMP 000000000020LL /* Command hold empty */
#define CMD_FUL 000000000010LL /* Command hold full */
#define OPL 000000000004LL /* Operation out */
/* CONO 504 */
#define CLR_UEND 00000004000LL /* Clear Unusual end */
#define CLR_MUX 00000002000LL /* Clear memory multiplexer */
#define CLR_DATCH 00000001000LL /* Clear data chaining flag */
#define CLR_IRQ 00000000400LL /* Clear IRQs */
#define NSTS_CLR 00000000200LL /* Clear New status flag */
#define PWR_CLR 00000000100LL /* Power on clear */
#define STS_CLR 00000000040LL /* Clear device status */
#define CMD_CLR 00000000020LL /* Clear command hold */
#define CMD_HOLD 00000000010LL /* Set command hold loaded. */
#define DEV_RESET 00000000004LL /* Reset current device */
#define OPL_RESET 00000000002LL /* Reset all devices */
#define CHN_RESET 00000000001LL /* Reset the channel */
/* DATAO 504 */
#define CMD_MASK 0000000000377LL /* Command */
#define SKP_MOD_OFF 0000000000400LL /* Skip mod off */
#define SKP_MOD_ON 0000000001000LL /* Skip mod on */
#define CMDCH_ON 0000000002000LL /* Command chaining */
#define CNT_BYT 0000000004000LL /* Count in bytes */
#define BYTE_MODE 0000000010000LL /* Transfer bytes not words */
#define SET_HOLD 0000000020000LL /* Set command hold */
#define DEV_ADDR 0000017740000LL /* Device address */
#define DATCH_ON 0000020000000LL /* Data chaining on */
#define HOLD_MASK 0000037777777LL /* Bits in command */
/* Channel sense bytes */
#define SNS_ATTN 0x80 /* Unit attention */
#define SNS_SMS 0x40 /* Status modifier */
#define SNS_CTLEND 0x20 /* Control unit end */
#define SNS_BSY 0x10 /* Unit Busy */
#define SNS_CHNEND 0x08 /* Channel end */
#define SNS_DEVEND 0x04 /* Device end */
#define SNS_UNITCHK 0x02 /* Unit check */
#define SNS_UNITEXP 0x01 /* Unit exception */
/* Channel pmp_cnt values. */
#define BUFF_EMPTY 0x10 /* Buffer is empty */
#define BUFF_DIRTY 0x20 /* Buffer is dirty flag */
#define BUFF_CHNEND 0x40 /* Channel end */
struct disk_t
{
const char *name; /* Type Name */
int cyl; /* Number of cylinders */
uint32 heads; /* Number of heads/cylinder */
int bpt; /* Max bytes per track */
uint8 sen_cnt; /* Number of sense bytes */
uint8 dev_type; /* Device type code */
}
disk_type[] =
{
{"2301", 1, 200, 20483, 6, 0x01}, /* 4.1 M */
{"2302", 250, 46, 4984, 6, 0x02}, /* 57.32 M 50ms, 120ms/10, 180ms> 10 */
{"2303", 80, 10, 4984, 6, 0x03}, /* 4.00 M */
{"2305", 48, 8, 14568, 6, 0x05}, /* 5.43 M */
{"2305-2",96, 8, 14858, 6, 0x05}, /* 11.26 M */
{"2311", 202, 10, 3717, 6, 0x11}, /* 7.32 M 156k/s 30 ms 145 full */
{"2314", 203, 20, 7294, 6, 0x14}, /* 29.17 M */
{"3330", 411, 19, 13165, 24, 0x30}, /* 100.00 M */
{"3330-2",815, 19, 13165, 24, 0x30},
{0},
};
/* Header block */
struct pmp_header
{
uint8 devid[8]; /* device header. */
uint32 heads; /* number of heads per cylinder */
uint32 tracksize; /* size of track */
uint8 devtype; /* Hex code of last two digits of device type. */
uint8 fileseq; /* always 0. */
uint16 highcyl; /* highest cylinder. */
uint8 resv[492]; /* pad to 512 byte block */
};
int pmp_pia; /* PIA for PMP device */
uint64 pmp_status; /* CONI status for device 500 */
int pmp_statusb;
uint32 pmp_cmd_hold; /* Command hold register */
uint32 pmp_wc_hold; /* Word count hold */
t_addr pmp_addr_hold; /* Address register hold */
uint32 pmp_wc; /* Current word count register */
t_addr pmp_addr; /* Current address register */
uint64 pmp_data; /* Data assembly register */
int pmp_cnt; /* Character count in asm register */
int pmp_cmd; /* Current command */
uint32 pmp_irq; /* Irq enable flags */
UNIT *pmp_cur_unit; /* Currently addressed unit */
t_stat pmp_devio(uint32 dev, uint64 *data);
int pmp_checkirq();
int pmp_posterror(uint64);
int chan_read_byte(uint8 *data);
int chan_write_byte(uint8 *data);
void chan_end(uint8 flags);
void pmp_startcmd();
void pmp_adjpos(UNIT * uptr);
t_stat pmp_srv(UNIT *);
t_stat pmp_reset(DEVICE *);
t_stat pmp_attach(UNIT *, CONST char *);
t_stat pmp_detach(UNIT *);
t_stat pmp_set_type(UNIT * uptr, int32 val, CONST char *cptr,
void *desc);
t_stat pmp_get_type(FILE * st, UNIT * uptr, int32 v,
CONST void *desc);
t_stat pmp_set_dev_addr(UNIT * uptr, int32 val, CONST char *cptr,
void *desc);
t_stat pmp_get_dev_addr(FILE * st, UNIT * uptr, int32 v,
CONST void *desc);
t_stat pmp_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
const char *cptr);
const char *pmp_description (DEVICE *dptr);
DIB pmp_dib[] = {
{PMP_DEV, 2, &pmp_devio, NULL}};
MTAB pmp_mod[] = {
{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "TYPE", "TYPE",
&pmp_set_type, &pmp_get_type, NULL, "Type of disk"},
{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "DEV", "DEV", &pmp_set_dev_addr,
&pmp_get_dev_addr, NULL},
{0}
};
UNIT pmp_unit[] = {
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x60), 0)}, /* 0 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x61), 0)}, /* 1 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x62), 0)}, /* 2 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x63), 0)}, /* 3 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x64), 0)}, /* 4 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x65), 0)}, /* 5 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x66), 0)}, /* 6 */
{UDATA(&pmp_srv, UNIT_DASD|UNIT_ADDR(0x67), 0)}, /* 7 */
};
DEVICE pmp_dev = {
"PMP", pmp_unit, NULL, pmp_mod,
NUM_UNITS_PMP, 8, 15, 1, 8, 8,
NULL, NULL, &pmp_reset, NULL, &pmp_attach, &pmp_detach,
&pmp_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0, dev_debug,
NULL, NULL, &pmp_help, NULL, NULL, &pmp_description
};
/* IOT routines */
t_stat
pmp_devio(uint32 dev, uint64 *data) {
int i;
switch(dev & 07) {
case CONI:
*data = pmp_status | pmp_pia;
if (pmp_checkirq())
*data |= PI_ACT;
if (pmp_statusb & IS_CH)
*data |= INT_SEL;
if (pmp_statusb & REQ_CH)
*data |= REQ_SEL;
if (pmp_statusb & IDLE_CH)
*data |= IDLE;
if ((pmp_statusb & (WCMA_LD|CMD_LD)) != (WCMA_LD|CMD_LD))
*data |= HOLD_EMPTY;
if (pmp_cur_unit != NULL)
*data |= ((uint64)GET_UADDR(pmp_cur_unit->flags)) << 24;
if ((pmp_status & (NXM_ERR|CHA_ERR|SEL_ERR)) != 0)
*data |= UNU_END;
sim_debug(DEBUG_CONI, &pmp_dev, "PMP %03o CONI %012llo PC=%o\n",
dev, *data, PC);
break;
case CONO:
sim_debug(DEBUG_CONO, &pmp_dev, "PMP %03o CONO %012llo PC=%06o\n",
dev, *data, PC);
if (*data & 010)
pmp_pia = *data & 7;
pmp_irq = (uint32)(*data);
(void)pmp_checkirq();
break;
case DATAI:
sim_debug(DEBUG_DATAIO, &pmp_dev, "PMP %03o DATI %012llo PC=%06o\n",
dev, *data, PC);
*data = (uint64)(pmp_addr);
break;
case DATAO:
pmp_addr_hold = (*data) & RMASK;
pmp_wc_hold = (*data >> 18) & RMASK;
pmp_statusb |= WCMA_LD;
sim_debug(DEBUG_DATAIO, &pmp_dev, "PMP %03o DATO %012llo %d PC=%06o\n",
dev, *data, (int)(((RMASK ^ pmp_wc_hold) + 1) & RMASK), PC);
(void)pmp_checkirq();
break;
case CONI|04:
*data = pmp_statusb;
if ((pmp_statusb & WCMA_LD) != 0 && (pmp_statusb & CMD_LD) != 0)
*data |= CMD_FUL;
if ((*data & CMD_FUL) == 0)
*data |= CMD_EMP;
if ((pmp_statusb & (OP1|REQ_CH|IDLE_CH)) == IDLE_CH)
*data |= OPL;
sim_debug(DEBUG_CONI, &pmp_dev, "IBM %03o CONI %012llo PC=%o\n",
dev, *data, PC);
break;
case CONO|04:
sim_debug(DEBUG_CONO, &pmp_dev, "IBM %03o CONO %012llo PC=%06o\n",
dev, *data, PC);
if (*data & PWR_CLR) { /* Power on clear */
pmp_statusb = IDLE_CH;
pmp_status = 0;
pmp_pia = 0;
/* Clear command in each unit */
break;
}
if (*data & CHN_RESET) {
pmp_statusb = IDLE_CH;
pmp_status = 0;
break;
}
if (*data & STS_CLR) /* Clear status bits */
pmp_status &= ~STS_MASK;
if (*data & CLR_DATCH) /* Data chaining */
pmp_cmd &= ~DATCH_ON;
if (*data & CMD_CLR) /* Clear pending command */
pmp_statusb &= ~CMD_LD;
if (*data & CMD_HOLD) { /* Set command buffer full */
pmp_statusb |= CMD_LD;
}
if (*data & (CLR_UEND|CLR_IRQ)) /* Clear unusual end condtions */
pmp_status &= ~(UNU_END|NEW_STS|STS_MASK);
if (*data & NSTS_CLR) { /* Clear new status */
pmp_status &= ~NEW_STS;
if ((pmp_statusb & OP1) == 0) { /* Check if any device requesting attn */
for (i = 0; i < NUM_UNITS_PMP; i++) {
if ((pmp_dev.units[i].CMD & DK_ATTN) != 0) {
pmp_cur_unit = &pmp_dev.units[i];
pmp_status |= NEW_STS|DEV_END;
pmp_dev.units[i].CMD &= ~DK_ATTN;
break;
}
}
if ((pmp_statusb & NEW_STS) == 0) {
pmp_statusb &= ~REQ_CH;
if (pmp_statusb & CMD_LD)
pmp_startcmd();
}
}
}
(void)pmp_checkirq();
break;
case DATAI|4:
sim_debug(DEBUG_DATAIO, &pmp_dev, "IBM %03o DATI %012llo PC=%06o\n",
dev, *data, PC);
break;
case DATAO|4:
sim_debug(DEBUG_DATAIO, &pmp_dev, "IBM %03o DATO %012llo PC=%06o\n",
dev, *data, PC);
pmp_cmd_hold = (*data) & HOLD_MASK;
pmp_statusb |= CMD_LD;
pmp_startcmd();
(void)pmp_checkirq();
break;
}
return SCPE_OK;
}
/* Check if interrupt pending for device */
int
pmp_checkirq() {
int f = 0;
clr_interrupt(PMP_DEV);
if ((pmp_irq & IRQ_ERROR) != 0 && (pmp_status & (PAR1_ERR|PAR2_ERR|PAR_ERR)) != 0) {
sim_debug(DEBUG_DETAIL, &pmp_dev, "parity irq\n");
f = 1;
}
if ((pmp_irq & IRQ_EMPTY) != 0 &&
(pmp_statusb & (WCMA_LD|CMD_LD)) != (WCMA_LD|CMD_LD)) {
sim_debug(DEBUG_DETAIL, &pmp_dev, "load irq\n");
f = 1;
}
if ((pmp_irq & IRQ_IDLE) != 0 && (pmp_statusb & (OP1|IDLE_CH)) == IDLE_CH) {
sim_debug(DEBUG_DETAIL, &pmp_dev, "idle irq\n");
f = 1;
}
if ((pmp_irq & IRQ_UEND) != 0 &&
(pmp_status & (NXM_ERR|CHA_ERR|SEL_ERR|UNU_END)) != 0) {
sim_debug(DEBUG_DETAIL, &pmp_dev, "uend irq\n");
f = 1;
}
if ((pmp_status & pmp_irq & (IRQ_NSTS|IRQ_STS)) != 0) {
sim_debug(DEBUG_DETAIL, &pmp_dev, "mem sts %o\n",
(int)(pmp_status & pmp_irq & (IRQ_NSTS|IRQ_STS)));
f = 1;
}
if (f)
set_interrupt(PMP_DEV, pmp_pia);
return f;
}
/* Post and error message and clear channel */
int
pmp_posterror(uint64 err) {
pmp_status |= err;
pmp_statusb &= ~(OP1|IS_CH|TRANS_CH);
pmp_statusb |= IDLE_CH;
(void)pmp_checkirq();
return 1;
}
/* read byte from memory */
int
chan_read_byte(uint8 *data) {
int byte;
int xfer = 0;
if ((pmp_cmd & 0x1) == 0) {
return 1;
}
/* Check if finished transfer */
if (pmp_cnt & BUFF_CHNEND)
return 1;
pmp_statusb |= TRANS_CH; /* Tranfer in progress */
/* Read in next work if buffer is in empty status */
if (pmp_cnt & BUFF_EMPTY) {
if (Mem_read_word(pmp_addr, &pmp_data, 0))
return pmp_posterror(NXM_ERR);
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_read %06o %012llo\n",
pmp_addr, pmp_data);
pmp_addr++;
pmp_cnt = 0;
xfer = 1; /* Read in a word */
}
/* Handle word vs byte mode */
if (pmp_cmd & BYTE_MODE) {
byte = (pmp_data >> (4 + (8 * (3 - (pmp_cnt & 0x3))))) & 0xff;
pmp_cnt++;
*data = byte;
if ((pmp_cnt & 03) == 0)
pmp_cnt = BUFF_EMPTY;
} else {
if ((pmp_cnt & 0xf) > 0x3) {
if ((pmp_cnt & 0xf) == 0x4) { /* Split byte */
byte = (pmp_data << 4) & 0xf0;
if (Mem_read_word(pmp_addr, &pmp_data, 0))
return pmp_posterror(NXM_ERR);
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_read %06o %012llo\n",
pmp_addr, pmp_data);
pmp_addr++;
xfer = 1; /* Read in a word */
byte |= pmp_data & 0xf;
} else {
byte = (pmp_data >> (4 + (8 * (8 - (pmp_cnt & 0xf))))) & 0xff;
}
} else {
byte = (pmp_data >> (4 + (8 * (3 - (pmp_cnt & 0xf))))) & 0xff;
}
pmp_cnt++;
if ((pmp_cnt & 0xf) == 9)
pmp_cnt = BUFF_EMPTY;
}
*data = byte;
if (pmp_cmd & CNT_BYT) {
pmp_wc ++;
} else if (xfer) {
pmp_wc ++;
}
if (pmp_wc & 07000000)
pmp_cnt |= BUFF_CHNEND;
return 0;
}
/* write byte to memory */
int
chan_write_byte(uint8 *data) {
int xfer = 0;
if ((pmp_cmd & 0x1) != 0) {
return 1;
}
/* Check if at end of transfer */
if (pmp_cnt == BUFF_CHNEND) {
return 1;
}
pmp_statusb |= TRANS_CH; /* Tranfer in progress */
if (pmp_cnt == BUFF_EMPTY) {
pmp_data = 0;
pmp_cnt = 0;
}
/* Handle word vs byte mode */
if (pmp_cmd & BYTE_MODE) {
if (pmp_cnt & BUFF_CHNEND)
return 1;
pmp_data &= ~(0xff <<(4 + (8 * (3 - (pmp_cnt & 0x3)))));
pmp_data |= (uint64)(*data & 0xff) << (4 + (8 * (3 - (pmp_cnt & 0x3))));
pmp_cnt++;
pmp_cnt |= BUFF_DIRTY;
if ((pmp_cnt & 03) == 0) {
pmp_cnt &= ~(BUFF_DIRTY|7);
if (Mem_write_word(pmp_addr, &pmp_data, 0))
return pmp_posterror(NXM_ERR);
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_write %06o %012llo\n",
pmp_addr, pmp_data);
pmp_addr++;
xfer = 1;
}
} else {
if ((pmp_cnt & 0xf) > 0x3) {
if ((pmp_cnt & 0xf) == 0x4) { /* Split byte */
pmp_data &= ~0xf;
pmp_data |= (uint64)((*data >> 4) & 0xf);
if (Mem_write_word(pmp_addr, &pmp_data, 0))
return pmp_posterror(NXM_ERR);
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_write %06o %012llo %2x\n",
pmp_addr, pmp_data, pmp_cnt);
pmp_addr++;
xfer = 1; /* Read in a word */
pmp_data = *data & 0xf;
pmp_cnt |= BUFF_DIRTY;
} else {
pmp_data &= ~(0xff <<(4 + (8 * (8 - (pmp_cnt & 0xf)))));
pmp_data |= (uint64)(*data & 0xff) << (4 + (8 * (8 - (pmp_cnt & 0xf))));
pmp_cnt |= BUFF_DIRTY;
}
} else {
pmp_data &= ~(0xff <<(4 + (8 * (3 - (pmp_cnt & 0xf)))));
pmp_data |= (uint64)(*data & 0xff) << (4 + (8 * (3 - (pmp_cnt & 0xf))));
pmp_cnt |= BUFF_DIRTY;
}
pmp_cnt++;
if ((pmp_cnt & 0xf) == 9) {
pmp_cnt = BUFF_EMPTY;
if (Mem_write_word(pmp_addr, &pmp_data, 0))
return pmp_posterror(NXM_ERR);
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_write %06o %012llo %2x\n",
pmp_addr, pmp_data, pmp_cnt);
pmp_addr++;
xfer = 1; /* Read in a word */
}
}
if (pmp_cmd & CNT_BYT) {
pmp_wc ++;
} else if (xfer) {
pmp_wc ++;
}
if (pmp_wc & 07000000) {
/* If not data channing, let device know there will be no
* more data to come
*/
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_write_wc\n");
if ((pmp_cmd & DATCH_ON) == 0) {
pmp_cnt = BUFF_CHNEND;
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_write_end\n");
return 1;
} else {
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_write reload\n");
if (pmp_statusb & WCMA_LD) {
pmp_statusb &= ~(WCMA_LD);
pmp_addr = pmp_addr_hold;
pmp_wc = pmp_wc_hold;
pmp_data = 0;
} else {
return pmp_posterror(CHA_ERR);
}
}
}
return 0;
}
/*
* Signal end of transfer by device.
*/
void
chan_end(uint8 flags) {
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_end(%x) %x\n", flags, pmp_wc);
/* If PCI flag set, trigger interrupt */
/* Flush buffer if there was any change */
if (pmp_cnt & BUFF_DIRTY) {
pmp_cnt = BUFF_EMPTY;
if (Mem_write_word(pmp_addr, &pmp_data, 0)) {
(void) pmp_posterror(NXM_ERR);
return;
}
sim_debug(DEBUG_DATA, &pmp_dev, "chan_write %012llo\n", pmp_data);
pmp_addr++;
}
pmp_statusb &= ~TRANS_CH; /* Clear transfer in progress */
pmp_statusb |= IDLE_CH;
pmp_status |= NEW_STS | CHN_END | ((uint64)flags) << 5;
if (pmp_status & (BSY|UNIT_CHK))
pmp_status |= UNU_END;
/* If channel is also finished, then skip any more data commands. */
if (pmp_status & (CHN_END|DEV_END)) {
pmp_cnt = BUFF_CHNEND;
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_endc %012llo %06o\n",
pmp_status, pmp_cmd);
/* While command has chain data set, continue to skip */
if (pmp_cmd & DATCH_ON) {
(void) pmp_posterror(CHA_ERR);
return;
}
if (pmp_cmd & CMDCH_ON) {
pmp_startcmd();
(void)pmp_checkirq();
return;
}
/* Indicate that device is done */
pmp_statusb &= ~OP1;
}
sim_debug(DEBUG_DETAIL, &pmp_dev, "chan_endf %012llo %06o\n",
pmp_status, pmp_statusb);
(void)pmp_checkirq();
}
/* Issue command to device */
void
pmp_startcmd() {
uint16 addr;
int i;
int unit;
int cmd;
int old_cmd = pmp_cmd;
uint8 ch;
sim_debug(DEBUG_CMD, &pmp_dev, "start command %o\n", pmp_statusb);
if ((pmp_statusb & CMD_LD) == 0 || (pmp_statusb & IDLE_CH) == 0) {
sim_debug(DEBUG_CMD, &pmp_dev, "not ready %o\n", pmp_statusb);
return;
}
/* Idle, no device selected. */
if ((pmp_statusb & OP1) == 0) {
/* Set to initial selection. */
pmp_statusb |= IS_CH;
pmp_cur_unit = NULL;
/* Copy over command */
pmp_cmd = pmp_cmd_hold;
cmd = pmp_cmd & CMD_MASK;
pmp_statusb &= ~(CMD_LD);
if (pmp_statusb & WCMA_LD) {
pmp_statusb &= ~(WCMA_LD);
pmp_addr = pmp_addr_hold;
pmp_wc = pmp_wc_hold;
pmp_cnt = BUFF_EMPTY;
}
addr = (uint16)((pmp_cmd & DEV_ADDR) >> 14);
sim_debug(DEBUG_CMD, &pmp_dev, "initiate on %02x\n", addr);
/* scan units looking for matching device. */
for (i = 0; i < NUM_UNITS_PMP; i++) {
if (addr == GET_UADDR(pmp_dev.units[i].flags)) {
pmp_cur_unit = &pmp_dev.units[i];
break;
}
}
}
/* If no matching device found, report selection error */
if (pmp_cur_unit == NULL) {
sim_debug(DEBUG_CMD, &pmp_dev, "No device\n");
(void)pmp_posterror(SEL_ERR);
return;
}
/* Check if unit is busy */
unit = GET_UADDR(pmp_cur_unit->flags) & 0x7;
/* Check if device busy */
if ((pmp_cur_unit->CMD & 0xff) != 0) {
sim_debug(DEBUG_CMD, &pmp_dev, "busy %o\n", pmp_statusb);
if (pmp_statusb & IS_CH)
(void)pmp_posterror(SEL_ERR);
pmp_status |= UNU_END|BSY;
(void)pmp_checkirq();
return;
}
/* Copy over command */
if ((pmp_statusb & CMD_LD) != 0) {
pmp_cmd = pmp_cmd_hold;
sim_debug(DEBUG_CMD, &pmp_dev, "load %o\n", pmp_cmd);
pmp_statusb &= ~(CMD_LD);
if (pmp_statusb & WCMA_LD) {
pmp_statusb &= ~(WCMA_LD);
pmp_addr = pmp_addr_hold;
pmp_wc = pmp_wc_hold;
pmp_cnt = BUFF_EMPTY;
}
}
/* Otherwise if there is command chaining, try new command */
if (old_cmd & CMDCH_ON) {
/* Channel in operation, must be command chaining */
if (((old_cmd & SKP_MOD_OFF) != 0) && ((pmp_status & ST_MOD) == 0)) {
pmp_statusb &= ~(CMD_LD);
(void)pmp_checkirq();
return;
}
if (((old_cmd & SKP_MOD_ON) != 0) && ((pmp_status & ST_MOD) != 0)) {
pmp_statusb &= ~(CMD_LD);
(void)pmp_checkirq();
return;
}
}
sim_debug(DEBUG_CMD, &pmp_dev, "CMD unit=%d %02x %06o\n", unit, pmp_cmd, pmp_addr);
(void)pmp_checkirq();
cmd = pmp_cmd & CMD_MASK;
/* If device not attached, return error */
if ((pmp_cur_unit->flags & UNIT_ATT) == 0) {
if (cmd == 0x4) { /* Sense */
sim_debug(DEBUG_CMD, &pmp_dev, "CMD sense\n");
ch = pmp_cur_unit->SENSE & 0xff;
sim_debug(DEBUG_DETAIL, &pmp_dev, "sense unit=%d 1 %x\n", unit, ch);
chan_write_byte(&ch) ;
ch = (pmp_cur_unit->SENSE >> 8) & 0xff;
sim_debug(DEBUG_DETAIL, &pmp_dev, "sense unit=%d 2 %x\n", unit, ch);
chan_write_byte(&ch) ;
ch = 0;
sim_debug(DEBUG_DETAIL, &pmp_dev, "sense unit=%d 3 %x\n", unit, ch);
chan_write_byte(&ch) ;
ch = unit;
sim_debug(DEBUG_DETAIL, &pmp_dev, "sense unit=%d 4 %x\n", unit, ch);
chan_write_byte(&ch) ;
ch = 0;
chan_write_byte(&ch) ;
chan_write_byte(&ch) ;
pmp_cur_unit->SENSE = 0;
pmp_status |= NEW_STS|CHN_END|DEV_END;
(void)pmp_posterror(0);
return;
}
if (cmd == 0x0)
return;
pmp_cur_unit->SENSE = SNS_INTVENT|SNS_CMDREJ;
pmp_status |= UNU_END|NEW_STS|CHN_END|DEV_END|UNIT_CHK;
(void)pmp_posterror(0);
return;
}
/* Issue the actual command */
switch (cmd & 0x3) {
case 0x3: /* Control */
if (cmd == 0x3 || cmd == DK_RELEASE) {
pmp_status &= ~(STS_MASK);
pmp_status |= NEW_STS|CHN_END|DEV_END;
if ((pmp_cmd & CMDCH_ON) == 0)
/* Indicate that device is done */
pmp_statusb &= ~OP1;
(void)pmp_checkirq();
return;
}
/* Fall Through */
case 0x1: /* Write command */
case 0x2: /* Read command */
pmp_statusb &= ~IDLE_CH;
pmp_cur_unit->CMD &= ~(DK_PARAM);
pmp_cur_unit->CMD |= cmd;
sim_debug(DEBUG_CMD, &pmp_dev, "CMD unit=%d CMD=%02x\n", unit,
pmp_cur_unit->CMD);
return;
case 0x0: /* Status */
if (cmd == 0x4) { /* Sense */
pmp_statusb &= ~IDLE_CH;
pmp_cur_unit->CMD |= cmd;
return;
}
break;
}
pmp_status &= ~(STS_MASK);
if (pmp_cur_unit->SENSE & 0xff)
pmp_status |= UNU_END|UNIT_CHK;
pmp_status |= NEW_STS|CHN_END|DEV_END;
pmp_statusb |= IDLE_CH;
pmp_statusb &= ~OP1;
sim_debug(DEBUG_CMD, &pmp_dev, "CMD unit=%d finish\n", unit);
(void)pmp_checkirq();
}
/* Compute position on new track. */
void
pmp_adjpos(UNIT * uptr)
{
struct pmp_t *data = (struct pmp_t *)(uptr->DATAPTR);
uint8 *rec;
int pos;
/* Save current position */
pos = data->tpos;
/* Set ourselves to start of track */
data->state = DK_POS_HA;
data->rec = data->klen = 0;
data->rpos = data->count = data->dlen = 0;
data->tstart = (uptr->POS & 0xff) * data->tsize;
rec = &data->cbuf[data->rpos + data->tstart];
/* Skip forward until we reach pos */
for (data->tpos = 0; data->tpos < pos; data->tpos++) {
switch(data->state) {
case DK_POS_HA: /* In home address (c) */
if (data->count == 4) {
data->tpos = data->rpos = 5;
data->state = DK_POS_CNT;
rec = &data->cbuf[data->rpos + data->tstart];
/* Check for end of track */
if ((rec[0] & rec[1] & rec[2] & rec[3]) == 0xff)
data->state = DK_POS_END;
}
break;
case DK_POS_CNT: /* In count (c) */
if (data->count == 0) {
/* Check for end of track */
if ((rec[0] & rec[1] & rec[2] & rec[3]) == 0xff) {