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kx10_cpu.c
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/* kx10_cpu.c: PDP-10 CPU simulator
Copyright (c) 2011-2021, Richard Cornwell
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Richard Cornwell shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Richard Cornwell
cpu KA10/KI10/KL10/KS10 central processor
The 36b system family had six different implementions: PDP-6, KA10, KI10,
KL10, KL10 extended, and KS10.
The register state for the KA10 is:
AC[16] accumulators
PC program counter
flags<0:11> state flags
pi_enb<1:7> enabled PI levels
pi_act<1:7> active PI levels
pi_prq<1:7> program PI requests
apr_enb<0:7> enabled system flags
apr_flg<0:7> system flags
The PDP-10 had just two instruction formats: memory reference
and I/O.
000000000 0111 1 1111 112222222222333333
012345678 9012 3 4567 890123456789012345
+---------+----+-+----+------------------+
| opcode | ac |i| idx| address | memory reference
+---------+----+-+----+------------------+
000 0000000 111 1 1111 112222222222333333
012 3456789 012 3 4567 890123456789012345
+---+-------+---+-+----+------------------+
|111|device |iop|i| idx| address | I/O
+---+-------+---+-+----+------------------+
This routine is the instruction decode routine for the PDP-10.
It is called from the simulator control program to execute
instructions in simulated memory, starting at the simulated PC.
It runs until an abort occurs.
General notes:
1. Reasons to stop. The simulator can be stopped by:
HALT instruction
MUUO instruction in executive mode
pager error in interrupt sequence
invalid vector table in interrupt sequence
illegal instruction in interrupt sequence
breakpoint encountered
nested indirects exceeding limit
nested XCT's exceeding limit
I/O error in I/O simulator
2. Interrupts. PDP-10's have a seven level priority interrupt
system. Interrupt requests can come from internal sources,
such as APR program requests, or external sources, such as
I/O devices. The requests are stored in pi_prq for program
requests, pi_apr for other internal flags, and pi_ioq for
I/O device flags. Internal and device (but not program)
interrupts must be enabled on a level by level basis. When
an interrupt is granted on a level, interrupts at that level
and below are masked until the interrupt is dismissed.
3. Arithmetic. The PDP-10 is a 2's complement system.
4. Adding I/O devices. These modules must be modified:
ka10_defs.h add device address and interrupt definitions
ka10_sys.c add sim_devices table entry
*/
#include "kx10_defs.h"
#include "sim_timer.h"
#define HIST_PC 0x40000000
#define HIST_PC2 0x80000000
#define HIST_PCE 0x20000000
#define HIST_MIN 64
#define HIST_MAX 5000000
#define TMR_RTC 0
#define TMR_QUA 1
uint64 M[MAXMEMSIZE]; /* Memory */
#if KL | KS
uint64 FM[128]; /* Fast memory register */
#elif KI
uint64 FM[64]; /* Fast memory register */
#else
uint64 FM[16]; /* Fast memory register */
#endif
uint64 AR; /* Primary work register */
uint64 MQ; /* Extension to AR */
uint64 BR; /* Secondary operand */
uint64 AD; /* Address Data */
uint64 MB; /* Memory Bufer Register */
t_addr AB; /* Memory address buffer */
t_addr PC; /* Program counter */
uint32 IR; /* Instruction register */
uint64 MI; /* Monitor lights */
uint8 MI_flag; /* Monitor flags */
uint8 MI_disable; /* Monitor flag disable */
uint32 FLAGS; /* Flags */
uint32 AC; /* Operand accumulator */
uint64 SW; /* Switch register */
uint8 RUN; /* Run flag */
uint8 prog_stop; /* Programmed stop */
#if PIDP10
uint8 sing_inst_sw; /* Execute single inst */
uint8 examine_sw; /* Examine memory */
uint8 deposit_sw; /* Deposit memory */
uint8 xct_sw; /* Execute SW */
uint8 stop_sw; /* Stop simulation */
uint32 rdrin_dev; /* Read in device */
uint8 IX; /* Index register */
uint8 IND; /* Indirect flag */
#endif
#if PDP6 | KA | KI
t_addr AS; /* Address switches */
#endif
int BYF5; /* Flag for second half of LDB/DPB instruction */
int uuo_cycle; /* Uuo cycle in progress */
int SC; /* Shift count */
int SCAD; /* Shift count extension */
int FE; /* Exponent */
t_addr last_addr; /* Last addressed accessed */
#if KA | PDP6
t_addr Pl, Ph, Rl, Rh, Pflag; /* Protection registers */
int push_ovf; /* Push stack overflow */
int mem_prot; /* Memory protection flag */
#endif
int nxm_flag; /* Non-existant memory flag */
#if KA | KI
int nxm_stop; /* Non-existant memory stop flag */
int adr_flag; /* Address break flag */
int adr_cond; /* Address condition swiches */
#endif
int clk_flg; /* Clock flag */
int ov_irq; /* Trap overflow */
int fov_irq; /* Trap floating overflow */
#if PDP6
int pcchg_irq; /* PC Change flag */
int ill_op; /* Illegal opcode */
int user_io; /* User IO flag */
int ex_uuo_sync; /* Execute a UUO op */
#endif
uint16 IOB_PI; /* Input bus PI signals */
uint8 PIR; /* Current priority level */
uint8 PIH; /* Highest priority */
uint8 PIE; /* Priority enable mask */
int pi_cycle; /* Executing an interrupt */
int pi_enable; /* Interrupts enabled */
int parity_irq; /* Parity interupt */
int pi_pending; /* Interrupt pending. */
int pi_enc; /* Flag for pi */
int apr_irq; /* Apr Irq level */
int clk_en; /* Enable clock interrupts */
int clk_irq; /* Clock interrupt */
int pi_restore; /* Restore previous level */
int pi_hold; /* Hold onto interrupt */
int modify; /* Modify cycle */
int xct_flag; /* XCT flags */
int pi_vect; /* Last pi location used for IRQ */
#if KI | KL | KS
uint64 ARX; /* Extension to AR */
uint64 BRX; /* Extension to BR */
uint64 ADX; /* Extension to AD */
t_addr ub_ptr; /* User base pointer */
t_addr eb_ptr; /* Executive base pointer */
uint8 fm_sel; /* User fast memory block */
int32 apr_serial = -1; /* CPU Serial number */
int inout_fail; /* In out fail flag */
#if KS
int ext_ac; /* Extended instruction AC */
uint8 prev_ctx; /* Previous AC context */
uint16 irq_enable; /* Apr IRQ enable bits */
uint16 irq_flags; /* Apr IRQ bits */
uint64 tim_low; /* Low order timer word */
uint64 tim_high; /* High order timer word */
uint64 int_val; /* Interval timer */
uint64 int_cur; /* Current interval */
int t20_page; /* Tops 20 paging selected */
int ptr_flg; /* Access to pointer value */
int extend = 0; /* Process extended instruction */
int fe_xct = 0; /* Execute instruction at address */
#if KS_ITS
uint64 qua_time; /* Quantum clock value */
uint8 pi_act; /* Current active PI level */
#endif
#elif KL
int ext_ac; /* Extended instruction AC */
uint8 prev_ctx; /* Previous AC context */
uint16 irq_enable; /* Apr IRQ enable bits */
uint16 irq_flags; /* Apr IRQ bits */
int mtr_irq; /* Timer IRQ */
int mtr_enable; /* Enable Timer */
int mtr_flags; /* Flags for accounting */
int tim_per; /* Timer period */
int tim_val; /* Current timer value */
int rtc_tim; /* Time till next 60hz clock */
uint32 brk_addr; /* Address break */
int brk_flags; /* Break flags */
int t20_page; /* Tops 20 paging selected */
int ptr_flg; /* Access to pointer value */
int extend = 0; /* Process extended instruction */
int sect; /* Actual resolved section */
int cur_sect; /* Current section */
int prev_sect; /* Previous section */
int pc_sect; /* Program counter section */
int glb_sect; /* Global section access */
#elif KI
int small_user; /* Small user flag */
#endif
int user_addr_cmp; /* User address compare flag */
#endif
#if KI | KL | ITS | BBN | KS
uint32 e_tlb[512]; /* Executive TLB */
uint32 u_tlb[546]; /* User TLB */
int page_enable; /* Enable paging */
int page_fault; /* Page fail */
uint32 ac_stack; /* Register stack pointer */
uint32 pag_reload; /* Page reload pointer */
uint64 fault_data; /* Fault data from last fault */
int trap_flag; /* In trap cycle */
int last_page; /* Last page mapped */
#endif
#if BBN
int exec_map; /* Enable executive mapping */
int next_write; /* Clear next write mapping */
int mon_base_reg; /* Monitor base register */
int user_base_reg; /* User base register */
int user_limit; /* User limit register */
uint64 pur; /* Process use register */
#endif
#if MPX_DEV
int mpx_enable; /* Enable MPX device */
#endif
#if ITS
uint32 dbr1; /* User Low Page Table Address */
uint32 dbr2; /* User High Page Table Address */
uint32 dbr3; /* Exec High Page Table Address */
uint32 jpc; /* Jump program counter */
uint8 age; /* Age word */
uint32 fault_addr; /* Fault address */
uint64 opc; /* Saved PC and Flags */
uint64 mar; /* Memory address compare */
uint32 qua_time; /* Quantum clock value */
#if MAGIC_SWITCH
int MAGIC = 1; /* Magic switch. */
#endif /* MAGIC_SWITCH */
#endif /* ITS */
#if KL_ITS
#define dbr1 FM[(6<<4)|1]
#define dbr2 FM[(6<<4)|2]
#define dbr3 FM[(6<<4)|3]
#define dbr4 FM[(6<<4)|4]
#define jpc FM[(6<<4)|15]
#define mar brk_addr;
#endif
#if KL
#define spt FM[(06<<4)|3]
#define cst FM[(06<<4)|2]
#define cst_msk FM[(06<<4)|0]
#define cst_dat FM[(06<<4)|1]
#endif
#if KS
uint64 spt;
uint64 cst;
uint64 cst_msk;
uint64 cst_dat;
uint64 hsb;
#endif
#if KS_ITS
#define dbr1 spt
#define dbr2 cst
#define dbr3 cst_dat
#define dbr4 cst_msk
uint64 pcst;
#endif
int watch_stop; /* Stop at memory watch point */
int maoff = 0; /* Offset for traps */
uint16 dev_irq[128]; /* Pending irq by device */
t_stat (*dev_tab[128])(uint32 dev, uint64 *data);
t_addr (*dev_irqv[128])(uint32 dev, t_addr addr);
t_stat cpu_detach(UNIT *uptr);
t_stat rtc_srv(UNIT * uptr);
#if KS
int32 rtc_tps = 500;
#else
int32 rtc_tps = 60;
#endif
#if ITS
t_stat qua_srv(UNIT * uptr);
int32 qua_tps = 125000;
#endif
#if KL
t_stat tim_srv(UNIT * uptr);
#endif
int32 tmxr_poll = 10000;
/* Physical address range for Rubin 10-11 interface. */
#define T11RANGE(addr) ((addr) >= ten11_base && (addr) < ten11_end)
/* Physical address range for auxiliary PDP-6. */
#define AUXCPURANGE(addr) ((addr) >= auxcpu_base && (addr) < (auxcpu_base + 040000))
#if (NUM_DEVS_RP + NUM_DEVS_RS + NUM_DEVS_TU) > 0
#if KA | KI | KL
/* List of RH10 & RH20 devices */
DEVICE *rh_devs[] = {
#if (NUM_DEVS_RS > 0)
&rsa_dev,
#endif
#if (NUM_DEVS_RP > 0)
&rpa_dev,
#if (NUM_DEVS_RP > 1)
&rpb_dev,
#if (NUM_DEVS_RP > 2)
&rpc_dev,
#if (NUM_DEVS_RP > 3)
&rpd_dev,
#endif
#endif
#endif
#endif
#if (NUM_DEVS_TU > 0)
&tua_dev,
#endif
#if (NUM_DEVS_NIA > 0)
&nia_dev,
#endif
NULL,
};
/* RH10 device numbers */
int rh_nums[] = { 0270, 0274, 0360, 0364, 0370, 0374, 0};
/* Maps RH10 & RH20 device number to DEVICE structure */
struct rh_dev rh[8];
#endif
#endif
typedef struct {
uint32 pc;
uint32 ea;
uint64 ir;
uint64 ac;
uint32 flags;
uint64 mb;
uint64 fmb;
uint16 prev_sect;
} InstHistory;
int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
/* Forward and external declarations */
#if KL | KS
int do_extend(uint32 IA);
#endif
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
t_stat cpu_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
#if KI | KL | KS
t_stat cpu_set_serial (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_show_serial (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
#endif
t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
const char *cptr);
const char *cpu_description (DEVICE *dptr);
void set_ac_display (uint64 *acbase);
#if KA
int (*Mem_read)(int flag, int cur_context, int fetch, int mod);
int (*Mem_write)(int flag, int cur_context);
#else
int Mem_read(int flag, int cur_context, int fetch, int mod);
int Mem_write(int flag, int cur_context);
#endif
t_bool build_dev_tab (void);
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit
cpu_reg CPU register list
cpu_mod CPU modifier list
*/
#if KL
#define DEFMEM 4096
#elif KS
#define DEFMEM 512
#else
#define DEFMEM 256
#endif
#if KI_22BIT
#define DF_FLAG UNIT_DF10C
#else
#define DF_FLAG 0
#endif
UNIT cpu_unit[] = { { UDATA (&rtc_srv,
UNIT_IDLE|UNIT_FIX|UNIT_BINK|UNIT_TWOSEG|DF_FLAG, DEFMEM * 1024) },
#if ITS
{ UDATA (&qua_srv, UNIT_IDLE|UNIT_DIS, 0) }
#endif
#if KL
{ UDATA (&tim_srv, UNIT_IDLE|UNIT_DIS, 0) }
#endif
};
REG cpu_reg[] = {
{ ORDATAD (PC, PC, 18, "Program Counter") },
{ ORDATAD (FLAGS, FLAGS, 18, "Flags") },
{ ORDATAD (FM0, FM[00], 36, "Fast Memory") }, /* addr in memory */
{ ORDATA (FM1, FM[01], 36) }, /* modified at exit */
{ ORDATA (FM2, FM[02], 36) }, /* to SCP */
{ ORDATA (FM3, FM[03], 36) },
{ ORDATA (FM4, FM[04], 36) },
{ ORDATA (FM5, FM[05], 36) },
{ ORDATA (FM6, FM[06], 36) },
{ ORDATA (FM7, FM[07], 36) },
{ ORDATA (FM10, FM[010], 36) },
{ ORDATA (FM11, FM[011], 36) },
{ ORDATA (FM12, FM[012], 36) },
{ ORDATA (FM13, FM[013], 36) },
{ ORDATA (FM14, FM[014], 36) },
{ ORDATA (FM15, FM[015], 36) },
{ ORDATA (FM16, FM[016], 36) },
{ ORDATA (FM17, FM[017], 36) },
#if KL | KS
{ BRDATA (FM, FM, 8, 36, 128)},
#elif KI
{ BRDATA (FM, FM, 8, 36, 64)},
#else
{ BRDATA (FM, FM, 8, 36, 16)},
#endif
{ ORDATAD (PIR, PIR, 8, "Priority Interrupt Request") },
{ ORDATAD (PIH, PIH, 8, "Priority Interrupt Hold") },
{ ORDATAD (PIE, PIE, 8, "Priority Interrupt Enable") },
{ ORDATAD (PIENB, pi_enable, 7, "Enable Priority System") },
{ ORDATAD (SW, SW, 36, "Console SW Register"), REG_FIT},
{ ORDATAD (MI, MI, 36, "Memory Indicators"), REG_FIT},
{ FLDATAD (MIFLAG, MI_flag, 0, "Memory indicator flag") },
{ FLDATAD (MIDISABLE, MI_disable, 0, "Memory indicator disable") },
#if PDP6 | KA | KI
{ ORDATAD (AS, AS, 18, "Console AS Register"), REG_FIT},
#endif
{ FLDATAD (BYF5, BYF5, 0, "Byte Flag") },
{ FLDATAD (UUO, uuo_cycle, 0, "UUO Cycle") },
#if KA | PDP6
{ ORDATAD (PL, Pl, 18, "Program Limit Low") },
{ ORDATAD (PH, Ph, 18, "Program Limit High") },
{ ORDATAD (RL, Rl, 18, "Program Relation Low") },
{ ORDATAD (RH, Rh, 18, "Program Relation High") },
{ FLDATAD (PFLAG, Pflag, 0, "Relocation enable") },
{ FLDATAD (PUSHOVER, push_ovf, 0, "Push overflow flag") },
{ FLDATAD (MEMPROT, mem_prot, 0, "Memory protection flag") },
#endif
{ FLDATAD (NXM, nxm_flag, 0, "Non-existing memory access") },
#if KA | KI
{ FLDATAD (NXMSTOP, nxm_stop, 0, "Stop on non-existing memory") },
{ FLDATAD (ABRK, adr_flag, 0, "Address break") },
{ ORDATAD (ACOND, adr_cond, 5, "Address condition switches") },
#endif
{ FLDATAD (CLK, clk_flg, 0, "Clock interrupt") },
{ FLDATAD (OV, ov_irq, 0, "Overflow enable") },
#if PDP6
{ FLDATAD (PCCHG, pcchg_irq, 0, "PC Change interrupt") },
{ FLDATAD (USERIO, user_io, 0, "User I/O") },
{ FLDATAD (UUOSYNC, ex_uuo_sync, 0, "UUO Op") },
#else
{ FLDATAD (FOV, fov_irq, 0, "Floating overflow enable") },
#endif
{ FLDATA (PIPEND, pi_pending, 0), REG_HRO},
{ FLDATA (PARITY, parity_irq, 0) },
{ ORDATAD (APRIRQ, apr_irq, 3, "APR Interrupt number") },
{ ORDATAD (CLKIRQ, clk_irq, 3, "CLK Interrupt number") },
{ FLDATA (CLKEN, clk_en, 0), REG_HRO},
{ FLDATA (XCT, xct_flag, 0), REG_HRO},
{ BRDATA (IRQV, dev_irq, 8, 16, 128 ), REG_HRO},
{ ORDATA (PIEN, pi_enc, 8), REG_HRO},
{ FLDATA (PIHOLD, pi_hold, 0), REG_HRO},
{ FLDATA (PIREST, pi_restore, 0), REG_HRO},
{ FLDATA (PICYC, pi_cycle, 0), REG_HRO},
#if MPX_DEV
{ FLDATA (MPX, mpx_enable, 0), REG_HRO},
#endif
#if KI
{ ORDATAD (UB, ub_ptr, 18, "User Base Pointer") },
{ ORDATAD (EB, eb_ptr, 18, "Executive Base Pointer") },
#endif
#if KL | KS
{ ORDATAD (UB, ub_ptr, 22, "User Base Pointer") },
{ ORDATAD (EB, eb_ptr, 22, "Executive Base Pointer") },
#endif
#if KI | KL | KS
{ ORDATAD (FMSEL, fm_sel, 8, "Register set select") },
{ ORDATAD (SERIAL, apr_serial, 10, "System Serial Number") },
{ FLDATA (INOUT, inout_fail, 0), REG_RO},
#if KI
{ FLDATA (SMALL, small_user, 0), REG_RO},
#endif
{ FLDATA (ADRCMP, user_addr_cmp, 0), REG_HRO},
#endif
#if KL | KI | ITS | BBN | KS
{ FLDATAD (PAGE_ENABLE, page_enable, 0, "Paging enabled")},
{ FLDATAD (PAGE_FAULT, page_fault, 0, "Page fault"), REG_RO},
#if KI | ITS | BBN
{ ORDATAD (AC_STACK, ac_stack, 18, "AC Stack"), REG_RO},
#endif
{ ORDATAD (PAGE_RELOAD, pag_reload, 18, "Page reload"), REG_HRO},
{ ORDATAD (FAULT_DATA, fault_data, 36, "Page fault data"), REG_RO},
{ FLDATAD (TRP_FLG, trap_flag, 0, "Trap flag"), REG_HRO},
#if !(KL | KS)
{ ORDATAD (LST_PAGE, last_page, 9, "Last page"), REG_HRO},
#endif
#endif
#if BBN
{ FLDATAD (EXEC_MAP, exec_map, 0, "Executive mapping"), REG_RO},
{ FLDATAD (NXT_WR, next_write, 0, "Map next write"), REG_RO},
{ ORDATAD (MON_BASE, mon_base_reg, 8, "Monitor base"), REG_RO},
{ ORDATAD (USER_BASE, user_base_reg, 8, "User base"), REG_RO},
{ ORDATAD (USER_LIMIT, user_limit, 3, "User limit"), REG_RO},
{ ORDATAD (PER_USER, pur, 36, "Per user data"), REG_RO},
#endif
#if ITS
{ ORDATAD (DBR1, dbr1, 18, "DB register 1")},
{ ORDATAD (DBR2, dbr2, 18, "DB register 2")},
{ ORDATAD (DBR3, dbr3, 18, "DB register 3")},
{ ORDATAD (JPC, jpc, 18, "Last Jump PC")},
{ ORDATAD (AGE, age, 4, "Age")},
{ ORDATAD (FAULT_ADDR, fault_addr, 18, "Fault address"), REG_RO},
{ ORDATAD (OPC, opc, 36, "Saved PC and flags")},
{ ORDATAD (MAR, mar, 18, "Memory address register")},
{ ORDATAD (QUA_TIME, qua_time, 32, "Quantum timer"), REG_RO},
#if MAGIC_SWITCH
{ ORDATAD (MAGIC, MAGIC, 1, "Magic switch"), REG_FIT},
#endif /* MAGIC_SWITCH */
#endif /* ITS */
#if KS
{ ORDATAD (EXT_AC, ext_ac, 4, "Extended Instruction AC"), REG_HRO},
{ ORDATAD (PREV_CTX, prev_ctx, 5, "Previous context"), REG_HRO},
{ ORDATAD (ITQ_EN, irq_enable, 16, "Interrupt enable"), REG_HRO},
{ ORDATAD (ITQ_FLGS, irq_flags, 16, "Interrupt Flags"), REG_HRO},
{ ORDATAD (T20_PAGE, t20_page, 1, "TOPS20 paging"), REG_HRO},
{ ORDATAD (PTR_FLG, ptr_flg, 1, "Accessing pointer"), REG_HRO},
{ ORDATAD (EXTEND, extend, 1, "Execute Extend"), REG_HRO},
{ ORDATAD (SPT, spt, 18, "Special Page table"),},
{ ORDATAD (CST, cst, 18, "Memory status table"),},
{ ORDATAD (PU, cst_dat, 36, "User data"),},
{ ORDATAD (CSTM, cst_msk, 36, "Status mask"),},
#endif
#if KL
{ ORDATAD (EXT_AC, ext_ac, 4, "Extended Instruction AC"), REG_HRO},
{ ORDATAD (PREV_CTX, prev_ctx, 5, "Previous context"), REG_HRO},
{ ORDATAD (ITQ_EN, irq_enable, 16, "Interrupt enable"), REG_HRO},
{ ORDATAD (ITQ_FLGS, irq_flags, 16, "Interrupt Flags"), REG_HRO},
{ ORDATAD (MTR_IRQ, mtr_irq, 1, "Timer IRQ"), REG_HRO},
{ ORDATAD (MTR_EN, mtr_enable, 1, "Timer Enable"), REG_HRO},
{ ORDATAD (MTR_FLGS, mtr_flags, 3, "Timer Flags"), REG_HRO},
{ ORDATAD (TIM_PER, tim_per, 12, "Timer period"), REG_HRO},
{ ORDATAD (TIM_VAl, tim_val, 12, "Timer period"), REG_HRO},
{ ORDATAD (RTC_TIM, rtc_tim, 12, "RTC timer"), REG_HRO},
{ ORDATAD (BRK_ADDR, brk_addr, 18, "Break address"), REG_HRO},
{ ORDATAD (BRK_FLGS, brk_flags, 18, "Break address"), REG_HRO},
{ ORDATAD (T20_PAGE, t20_page, 1, "TOPS20 paging"), REG_HRO},
{ ORDATAD (PTR_FLG, ptr_flg, 1, "Accessing pointer"), REG_HRO},
{ ORDATAD (EXTEND, extend, 1, "Execute Extend"), REG_HRO},
{ ORDATAD (SECT, sect, 12, "access section"), REG_HRO},
{ ORDATAD (CUR_SECT, cur_sect, 12, "Current section"), REG_HRO},
{ ORDATAD (PREV_SECT, prev_sect, 12, "Previous section"), REG_HRO},
{ ORDATAD (PC_SECT, pc_sect, 12, "PC section"), REG_HRO},
{ ORDATAD (GLB_SECT, glb_sect, 1, "Global section"), REG_HRO},
#endif
#if !PDP6
{ BRDATA (ETLB, e_tlb, 8, 32, 512), REG_HRO},
{ BRDATA (UTLB, u_tlb, 8, 32, 546), REG_HRO},
#endif
#if PIDP10
{ ORDATAD (READIN, rdrin_dev, 9, "Readin device")},
#endif
{ NULL }
};
MTAB cpu_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_MSIZE, 1, "16K", "16K", &cpu_set_size },
{ UNIT_MSIZE, 2, "32K", "32K", &cpu_set_size },
{ UNIT_MSIZE, 3, "48K", "48K", &cpu_set_size },
{ UNIT_MSIZE, 4, "64K", "64K", &cpu_set_size },
{ UNIT_MSIZE, 6, "96K", "96K", &cpu_set_size },
{ UNIT_MSIZE, 8, "128K", "128K", &cpu_set_size },
{ UNIT_MSIZE, 12, "196K", "196K", &cpu_set_size },
{ UNIT_MSIZE, 16, "256K", "256K", &cpu_set_size },
#if KI_22BIT|KI|ITS|KS
{ UNIT_MSIZE, 32, "512K", "512K", &cpu_set_size },
{ UNIT_MSIZE, 48, "768K", "768K", &cpu_set_size },
{ UNIT_MSIZE, 64, "1024K", "1024K", &cpu_set_size },
#endif
#if KI_22BIT|KI|KL
{ UNIT_MSIZE, 128, "2048K", "2048K", &cpu_set_size },
{ UNIT_MSIZE, 256, "4096K", "4096K", &cpu_set_size },
#endif
#if KI|KL|KS
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "SERIAL", "SERIAL",
&cpu_set_serial, &cpu_show_serial, NULL, "CPU Serial Number" },
#if KL
{ UNIT_M_PAGE, 0, "KL10A", "KL10A", NULL, NULL, NULL,
"Base KL10"},
{ UNIT_M_PAGE, UNIT_KL10B, "KL10B", "KL10B", NULL, NULL, NULL,
"Extended addressing support for KL10"},
#endif
#endif
#if KA
{ UNIT_M_PAGE, 0, "ONESEG", "ONESEG", NULL, NULL, NULL,
"One Relocation Register"},
{ UNIT_M_PAGE, UNIT_TWOSEG, "TWOSEG", "TWOSEG", NULL, NULL,
NULL, "Two Relocation Registers"},
#endif
#if ITS | KL_ITS | KS_ITS
{ UNIT_M_PAGE, UNIT_ITSPAGE, "ITS", "ITS", NULL, NULL, NULL,
"Paging hardware for ITS"},
#endif
#if BBN
{ UNIT_M_PAGE, UNIT_BBNPAGE, "BBN", "BBN", NULL, NULL, NULL,
"Paging hardware for TENEX"},
#endif
#if WAITS
{ UNIT_M_WAITS, UNIT_WAITS, "WAITS", "WAITS", NULL, NULL, NULL,
"Support for WAITS XCTR"},
{ UNIT_M_WAITS, 0, NULL, "NOWAITS", NULL, NULL, NULL,
"No support for WAITS XCTR"},
#endif
#if MPX_DEV
{ UNIT_M_MPX, UNIT_MPX, "MPX", "MPX", NULL, NULL, NULL,
"MPX Device for ITS"},
{ UNIT_M_MPX, 0, NULL, "NOMPX", NULL, NULL, NULL,
"Disables the MPX device"},
#endif
#if KI | KL
{ UNIT_M_DF10, 0, "DF10", "DF10", NULL, NULL, NULL,
"18 bit DF10"},
{ UNIT_M_DF10, UNIT_DF10C, "DF10C", "DF10C", NULL, NULL, NULL,
"22 bit DF10C"},
#endif
#if PDP6 | KA | KI
{ UNIT_MAOFF, UNIT_MAOFF, "MAOFF", "MAOFF", NULL, NULL,
NULL, "Interrupts relocated to 140"},
{ UNIT_MAOFF, 0, NULL, "NOMAOFF", NULL, NULL, NULL,
"No interrupt relocation"},
#endif
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
&cpu_set_hist, &cpu_show_hist },
{ 0 }
};
/* Simulator debug controls */
DEBTAB cpu_debug[] = {
{"IRQ", DEBUG_IRQ, "Debug IRQ requests"},
{"CONI", DEBUG_CONI, "Show coni instructions"},
{"CONO", DEBUG_CONO, "Show cono instructions"},
{"DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"},
#if KS
{"DATA", DEBUG_DATA, "Show data transfers"},
{"DETAIL", DEBUG_DETAIL, "Show details about device"},
{"EXP", DEBUG_EXP, "Show exception information"},
#endif
{0, 0}
};
DEVICE cpu_dev = {
"CPU", &cpu_unit[0], cpu_reg, cpu_mod,
1+ITS+KL, 8, 22, 1, 8, 36,
&cpu_ex, &cpu_dep, &cpu_reset,
NULL, NULL, &cpu_detach, NULL, DEV_DEBUG, 0, cpu_debug,
NULL, NULL, &cpu_help, NULL, NULL, &cpu_description
};
/* Data arrays */
#define FCE 000001 /* Fetch memory into AR */
#define FCEPSE 000002 /* Fetch and store memory into AR */
#define SCE 000004 /* Save AR into memory */
#define FAC 000010 /* Copy AR to BR, then Fetch AC into AR */
#define FAC2 000020 /* Fetch AC+1 into MQ */
#define SAC 000040 /* Save AC into AR */
#define SACZ 000100 /* Save AC into AR if AC not 0 */
#define SAC2 000200 /* Save MQ into AC+1 */
#define SWAR 000400 /* Swap AR */
#define FBR 001000 /* Load AC into BR */
#if PDP6
#define P6(x) x
#define P10(x) 0
#else
#define P6(x) 0
#define P10(x) x
#endif
#if PDP6
#define PC_CHANGE FLAGS |= PCHNG; check_apr_irq();
#else
#define PC_CHANGE
#endif
#define SWAP_AR ((RMASK & AR) << 18) | ((AR >> 18) & RMASK)
#define SMEAR_SIGN(x) x = ((x) & SMASK) ? (x) | EXPO : (x) & MANT
#define GET_EXPO(x) ((((x) & SMASK) ? 0377 : 0 ) \
^ (((x) >> 27) & 0377))
#if KI | KL | KS
#define AOB(x) ((x + 1) & RMASK) | ((x + 01000000LL) & (C1|LMASK))
#define SOB(x) ((x + RMASK) & RMASK) | ((x + LMASK) & (C1|LMASK));
#else
#define AOB(x) (x + 01000001LL)
#define SOB(x) (x + 0777776777777LL)
#endif
#if ITS
#define QITS (cpu_unit[0].flags & UNIT_ITSPAGE)
#define QTEN11 (ten11_unit[0].flags & UNIT_ATT)
#define QAUXCPU (auxcpu_unit[0].flags & UNIT_ATT)
#else
#if KL_ITS | KS_ITS
#define QITS (cpu_unit[0].flags & UNIT_ITSPAGE)
#else
#define QITS 0
#endif
#endif
#if BBN
#define QBBN (cpu_unit[0].flags & UNIT_BBNPAGE)
#else
#define QBBN 0
#endif
#if WAITS
#define QWAITS (cpu_unit[0].flags & UNIT_WAITS)
#else
#define QWAITS 0
#endif
#if KL
#define QKLB (cpu_unit[0].flags & UNIT_KL10B)
#else
#define QKLB 0
#endif
#if PDP6
#define QSLAVE (slave_unit[0].flags & UNIT_ATT)
#else
#define QSLAVE 0
#endif
#define MAX_DEV 128
#if KL
struct _byte {
int p;
int s;
} _byte_adj[] = {
{ /* 37 */ 36, 6 }, /* 45 */
{ /* 38 */ 30, 6 }, /* 46 */
{ /* 39 */ 24, 6 }, /* 47 */
{ /* 40 */ 18, 6 }, /* 50 */
{ /* 41 */ 12, 6 }, /* 51 */
{ /* 42 */ 6, 6 }, /* 52 */
{ /* 43 */ 0, 6 }, /* 53 */
{ /* 44 */ 36, 8 }, /* 54 */
{ /* 45 */ 28, 8 }, /* 55 */
{ /* 46 */ 20, 8 }, /* 56 */
{ /* 47 */ 12, 8 }, /* 57 */
{ /* 48 */ 4, 8 }, /* 60 */
{ /* 49 */ 36, 7 }, /* 61 */
{ /* 50 */ 29, 7 }, /* 62 */
{ /* 51 */ 22, 7 }, /* 63 */
{ /* 52 */ 15, 7 }, /* 64 */
{ /* 53 */ 8, 7 }, /* 65 */
{ /* 54 */ 1, 7 }, /* 66 */
{ /* 55 */ 36, 9 }, /* 67 */
{ /* 56 */ 27, 9 }, /* 70 */
{ /* 57 */ 18, 9 }, /* 71 */
{ /* 58 */ 9, 9 }, /* 72 */
{ /* 59 */ 0, 9 }, /* 73 */
{ /* 60 */ 36,18 }, /* 74 */
{ /* 61 */ 18,18 }, /* 75 */
{ /* 62 */ 0,18 } /* 76 */
};
#endif
#if ITS
/*
* Set quantum clock to qua_time.
*/
void
set_quantum()
{
double us;
sim_cancel(&cpu_unit[1]);
if (qua_time & BIT17)
return;
us = (double)(BIT17 - qua_time);
(void)sim_activate_after_d(&cpu_unit[1], us);
}
/*
* Update the qua_time variable.
*/
void
load_quantum()
{
if (sim_is_active(&cpu_unit[1])) {
double us;
us = sim_activate_time_usecs (&cpu_unit[1]);
if ((uint32)us > BIT17)
qua_time = BIT17;
else
qua_time = (BIT17 - (uint32)us) & RMASK;
sim_cancel(&cpu_unit[1]);
}
}
/*
* Get the current quantum time.
*/
uint32
get_quantum()
{
uint32 t = qua_time;
if (sim_is_active(&cpu_unit[1])) {
double us;
us = sim_activate_time_usecs (&cpu_unit[1]);
t = (BIT17 - (uint32)us) & RMASK;
}
return t;
}
#endif
/*
* Set device to interrupt on a given level 1-7
* Level 0 means that device interrupt is not enabled
*/
void set_interrupt(int dev, int lvl) {
lvl &= 07;
if (lvl) {
dev_irq[dev>>2] = 0200 >> lvl;
pi_pending = 1;
IOB_PI |= 0200 >> lvl;
#if DEBUG
sim_debug(DEBUG_IRQ, &cpu_dev, "set irq %o %o %03o %03o %03o\n",
dev & 0774, lvl, PIE, PIR, PIH);
#endif
}
}
#if MPX_DEV
void set_interrupt_mpx(int dev, int lvl, int mpx) {
lvl &= 07;
if (lvl) {
dev_irq[dev>>2] = 0200 >> lvl;
if (lvl == 1 && mpx != 0)
dev_irq[dev>>2] |= mpx << 8;
pi_pending = 1;
IOB_PI |= 0200 >> lvl;
#if DEBUG
sim_debug(DEBUG_IRQ, &cpu_dev, "set mpx irq %o %o %o %03o %03o %03o\n",
dev & 0774, lvl, mpx, PIE, PIR, PIH);
#endif
}
}
#endif
/*
* Clear the interrupt flag for a device
*/
void clr_interrupt(int dev) {
uint16 lvl;
int i;
dev_irq[dev>>2] = 0;
/* Update bus PI flags */
for (lvl = i = 0; i < MAX_DEV; i++)
lvl |= dev_irq[i];
IOB_PI = lvl;
#if DEBUG
if (dev > 4)
sim_debug(DEBUG_IRQ, &cpu_dev, "clear irq %o\n", dev & 0774);
#endif
}
/*
* Check if there is any pending interrupts return 0 if none,
* else set pi_enc to highest level and return 1.
*/
int check_irq_level() {
int i, lvl;
int pi_req;
/* If PXCT don't check for interrupts */
if (xct_flag != 0)
return 0;
/* If not enabled, check if any pending Processor IRQ */
if (pi_enable == 0) {
#if !PDP6
if (PIR != 0) {
pi_enc = 1;
for(lvl = 0100; lvl != 0; lvl >>= 1) {
if (lvl & PIH)
break;
if (PIR & lvl)
return 1;
pi_enc++;
}
}
#endif
return 0;
}
lvl = IOB_PI;
if (lvl == 0)
pi_pending = 0;
pi_req = (lvl & PIE) | PIR;
#if MPX_DEV
/* Check if interrupt on PI channel 1 */
if (mpx_enable && cpu_unit[0].flags & UNIT_MPX &&
(pi_req & 0100) && (PIH & 0100) == 0) {
pi_enc = 010;
for(i = lvl = 0; i < MAX_DEV; i++) {
if (dev_irq[i] & 0100) {
int l = dev_irq[i] >> 8;
if (l != 0 && l < pi_enc)
pi_enc = l;
}
}
if (pi_enc != 010) {
pi_enc += 010;
return 1;
}
}
#endif
/* Handle held interrupt requests */
i = 1;
for(lvl = 0100; lvl != 0; lvl >>= 1, i++) {
if (lvl & PIH)
break;
if (pi_req & lvl) {
pi_enc = i;
return 1;
}
}
return 0;
}
/*
* Recover from held interrupt.
*/
void restore_pi_hold() {
int lvl;
if (!pi_enable)
return;
/* Clear HOLD flag for highest interrupt */
for(lvl = 0100; lvl != 0; lvl >>= 1) {
if (lvl & PIH) {
PIR &= ~lvl;
#if DEBUG
sim_debug(DEBUG_IRQ, &cpu_dev, "restore irq %o %03o\n", lvl, PIH);