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lr35902.c
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/*
* Special thanks to tpw_rules from #gbdev for helping spotting some bugs
*/
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#include <assert.h>
#include "lr35902.h"
#include "memory.h"
#include "string_fun.h"
#include "io_regs.h"
#define OP(n) ops[n].handler(ops[n].a, ops[n].b);
#define ADDR_INT_VBlank 0x0040
#define ADDR_INT_LCDSTAT_Int 0x0048
#define ADDR_INT_Timer_Overflow 0x0050
#define ADDR_INT_End_Serial_IO_Transfer 0x0058
#define ADDR_INT_High_to_Low_P10_P13 0x0060
static regs_t regs;
// Some constants used as parameters
static uint8_t C_00H = 0x00, C_08H = 0x08, C_10H = 0x10, C_18H = 0x18,
C_20H = 0x20, C_28H = 0x28, C_30H = 0x30, C_38H = 0x38;
static uint8_t C_0 = 0, C_1 = 1, C_2 = 2, C_3 = 3, C_4 = 4, C_5 = 5,
C_6 = 6, C_7 = 7;
static uint8_t C_NZ = COND_NZ, C_NC = COND_NC, C_Z = COND_Z, C_C = COND_C;
static uint16_t imm_val;
static uint16_t *imm_16 = (uint16_t*)&imm_val;
static uint8_t *imm_8 = (uint8_t*)&imm_val;
static uint8_t tmp_8;
static uint16_t tmp_16;
static uint8_t ext_cycles;
static uint8_t int_count;
static uint8_t int_opt;
static uint8_t halted;
static inst_t ops[256];
static inst_t ops_cb[256];
regs_t *cpu_get_regs() {
return ®s;
}
void init_regs() {
regs.SP = ®s.SP_val;
regs.AF = (uint16_t*)®s.r_data[0];
regs.BC = (uint16_t*)®s.r_data[2];
regs.DE = (uint16_t*)®s.r_data[4];
regs.HL = (uint16_t*)®s.r_data[6];
// This works on little endian
// It may not work on big endian!!!
#if __BYTE_ORDER == __LITTLE_ENDIAN
regs.F = (uint8_t*)®s.r_data[0];
regs.A = (uint8_t*)®s.r_data[1];
regs.C = (uint8_t*)®s.r_data[2];
regs.B = (uint8_t*)®s.r_data[3];
regs.E = (uint8_t*)®s.r_data[4];
regs.D = (uint8_t*)®s.r_data[5];
regs.L = (uint8_t*)®s.r_data[6];
regs.H = (uint8_t*)®s.r_data[7];
#else
#error "Big endian not supported yet"
#endif
}
void exec_op(uint8_t n) {
//printf("0x%04X : %02X -> %s\n", PC, n, ops[n].desc);
switch (ops[n].length) {
case 1: break;
case 2: *imm_8 = mem_read_8(regs.PC + 1); break;
case 3: *imm_16 = mem_read_16(regs.PC + 1); break;
}
regs.PC += ops[n].length;
switch (ops[n].opt) {
case MEM_R_8a:
tmp_8 = mem_read_8(*(uint8_t*)ops[n].b + 0xFF00);
ops[n].handler(ops[n].a, &tmp_8);
break;
case MEM_R_16a:
tmp_8 = mem_read_8(*(uint16_t*)ops[n].b);
ops[n].handler(ops[n].a, &tmp_8);
break;
case MEM_W_8a:
ops[n].handler(&tmp_8, ops[n].b);
mem_write_8(*(uint8_t*)ops[n].a + 0xFF00, tmp_8);
break;
case MEM_W_16a:
ops[n].handler(&tmp_8, ops[n].b);
mem_write_8(*(uint16_t*)ops[n].a, tmp_8);
break;
case MEM_W_16a_16d:
ops[n].handler(&tmp_16, ops[n].b);
mem_write_16(*(uint16_t*)ops[n].a, tmp_16);
break;
case MEM_RW_16a:
tmp_8 = mem_read_8(*(uint16_t*)ops[n].a);
//printf("op: %x\n", n);
//printf(">before: %x\n", tmp_8);
ops[n].handler(&tmp_8, ops[n].b);
//printf(">after: %x\n", tmp_8);
mem_write_8(*(uint16_t*)ops[n].a, tmp_8);
break;
case NONE:
ops[n].handler(ops[n].a, ops[n].b);
break;
}
}
void exec_op_cb(uint8_t n) {
//printf("0x%04X : %02X -> %s\n", PC - 1, n, ops_cb[n].desc);
switch (ops_cb[n].opt) {
case MEM_R_16a:
tmp_8 = mem_read_8(*(uint16_t*)ops_cb[n].b);
ops_cb[n].handler(ops_cb[n].a, &tmp_8);
break;
case MEM_W_16a:
ops_cb[n].handler(&tmp_8, ops_cb[n].b);
mem_write_8(*(uint16_t*)ops_cb[n].a, tmp_8);
break;
case MEM_RW_16a:
tmp_8 = mem_read_8(*(uint16_t*)ops_cb[n].a);
ops_cb[n].handler(&tmp_8, ops_cb[n].b);
mem_write_8(*(uint16_t*)ops_cb[n].a, tmp_8);
break;
case MEM_R_8a:
case MEM_W_8a:
case MEM_W_16a_16d:
case NONE:
ops_cb[n].handler(ops_cb[n].a, ops_cb[n].b);
break;
}
}
void set_flag(flag_t f, int v) {
if (v) {
*regs.F |= f;
} else {
*regs.F &= ~f;
}
}
void set_flag_Z(uint8_t *a) {
if (*a == 0) {
set_flag(Z_FLAG, 1);
} else {
set_flag(Z_FLAG, 0);
}
}
uint8_t get_flag(flag_t f) {
return (*regs.F & f) > 0 ? 1 : 0;
}
void op_ld_8(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
*a = *b;
}
void op_ld_16(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
uint16_t *b = (uint16_t*)_b;
*a = *b;
}
// BUG!!!, HL+ happens before the exec_op() stores the result
// Dirty fix
void op_ldi(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
//uint8_t *b = (uint8_t*)_b;
//*a = *b;
//(*regs.HL)++;
if (a == regs.A) {
exec_op(0x7E);
regs.PC -= ops[0x7E].length;
} else {
exec_op(0x77);
regs.PC -= ops[0x77].length;
}
exec_op(0x23);
regs.PC -= ops[0x23].length;
}
// BUG!!!, HL- happens before the exec_op() stores the result
// Dirty fix
void op_ldd(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
//uint8_t *b = (uint8_t*)_b;
//*a = *b;
//(*regs.HL)--;
if (a == regs.A) {
exec_op(0x7E);
regs.PC -= ops[0x7E].length;
} else {
exec_op(0x77);
regs.PC -= ops[0x77].length;
}
exec_op(0x2B);
regs.PC -= ops[0x2B].length;
}
void op_ldhl(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
int8_t *b = (int8_t*)_b;
uint8_t *b_tmp = (uint8_t*)_b;
set_flag(H_FLAG, ((*a & 0x0F) > (0x0F - (*b_tmp & 0x0F))) ? 1 : 0);
set_flag(C_FLAG, ((*a & 0xFF) > (0xFF - *b_tmp)) ? 1 : 0);
*regs.HL = *a + *b;
set_flag(Z_FLAG, 0);
set_flag(N_FLAG, 0);
}
void op_halt(void *_a, void *_b) {
halted = 1;
}
void op_add_8(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
set_flag(H_FLAG, ((*a & 0x0F) > (0x0F - (*b & 0x0F))) ? 1 : 0);
set_flag(C_FLAG, (*a > (0xFF - *b)) ? 1 : 0);
*a += *b;
set_flag_Z(a);
set_flag(N_FLAG, 0);
}
void op_add_16(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
uint16_t *b = (uint16_t*)_b;
set_flag(H_FLAG, ((*a & 0x0FFF) > (0x0FFF - (*b & 0x0FFF))) ? 1 : 0);
set_flag(C_FLAG, ((*a & 0xFFFF) > (0xFFFF - (*b & 0xFFFF))) ? 1 : 0);
*a += *b;
set_flag(N_FLAG, 0);
}
void op_addsp(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
int8_t *b = (int8_t*)_b;
uint8_t *b_tmp = (uint8_t*)_b;
set_flag(H_FLAG, ((*a & 0x0F) > (0x0F - (*b_tmp & 0x0F))) ? 1 : 0);
set_flag(C_FLAG, ((*a & 0xFF) > (0xFF - *b_tmp)) ? 1 : 0);
*a += *b;
set_flag(Z_FLAG, 0);
set_flag(N_FLAG, 0);
}
void op_adc(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
uint8_t c = get_flag(C_FLAG);
// CHECK THIS!!!
//set_flag(H_FLAG, ((*a & 0x0F) < (*b & 0x0F)) ? 1 : 0);
//set_flag(C_FLAG, (*a > (0xFF - *b)) ? 1 : 0);
set_flag(H_FLAG, ((*a & 0x0F) + (*b & 0x0F) +
get_flag(C_FLAG) > 0x0F) ? 1 : 0);
set_flag(C_FLAG, ((uint16_t)*a + (uint16_t)*b +
(uint16_t)get_flag(C_FLAG) > 0x00FF) ? 1 : 0);
*a += *b + c;
set_flag_Z(a);
set_flag(N_FLAG, 0);
}
void op_sub(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
set_flag(H_FLAG, ((*a & 0x0F) < (*b & 0x0F)) ? 1 : 0);
set_flag(C_FLAG, (*a < *b) ? 1 : 0);
*a -= *b;
set_flag_Z(a);
set_flag(N_FLAG, 1);
}
void op_sbc(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
uint8_t c = get_flag(C_FLAG);
// CHECK THIS!!!
//set_flag(H_FLAG, ((*a & 0x0F) < (*b & 0x0F)) ? 1 : 0);
//set_flag(C_FLAG, (*a < *b) ? 1 : 0);
set_flag(H_FLAG, ((*a & 0x0F) < (*b & 0x0F) +
get_flag(C_FLAG)) ? 1 : 0);
set_flag(C_FLAG, ((uint16_t)*a < (uint16_t)*b +
get_flag(C_FLAG)) ? 1 : 0);
*a -= *b + c;
set_flag_Z(a);
set_flag(N_FLAG, 1);
}
void op_and(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
*a &= *b;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 1);
set_flag(C_FLAG, 0);
}
void op_xor(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
*a ^= *b;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, 0);
}
void op_or(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
*a |= *b;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, 0);
}
void op_cp(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
set_flag(Z_FLAG, (*a == *b) ? 1 : 0);
set_flag(N_FLAG, 1);
set_flag(H_FLAG, ((*a & 0x0F) < (*b & 0x0F)) ? 1 : 0);
set_flag(C_FLAG, (*a < *b) ? 1 : 0);
}
void op_inc_8(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
//printf("before: %x\n", *a);
(*a)++;
//printf("after: %x\n", *a);
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, ((*a & 0x0F) == 0x00) ? 1 : 0);
}
void op_inc_16(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
(*a)++;
}
void op_dec_8(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
(*a)--;
set_flag_Z(a);
set_flag(N_FLAG, 1);
set_flag(H_FLAG, ((*a & 0x0F) == 0x0F) ? 1 : 0);
}
void op_dec_16(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
(*a)--;
}
void op_ccf(void *_a, void *_b) {
if (*regs.F & C_FLAG) {
set_flag(C_FLAG, 0);
} else {
set_flag(C_FLAG, 1);
}
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
}
void op_scf(void *_a, void *_b) {
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, 1);
}
void op_rlca(void *_a, void *_b) {
uint8_t b7 = *regs.A >> 7;
*regs.A = *regs.A << 1 | b7;
set_flag(Z_FLAG, 0);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b7);
}
void op_rla(void *_a, void *_b) {
uint8_t b7 = *regs.A >> 7;
*regs.A = *regs.A << 1 | get_flag(C_FLAG);
set_flag(Z_FLAG, 0);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b7);
}
void op_rrca(void *_a, void *_b) {
uint8_t b0 = *regs.A & 0x01;
*regs.A = *regs.A >> 1 | b0 << 7;
set_flag(Z_FLAG, 0);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b0);
}
void op_rra(void *_a, void *_b) {
uint8_t b0 = *regs.A & 0x01;
*regs.A = *regs.A >> 1 | get_flag(C_FLAG) << 7;
set_flag(Z_FLAG, 0);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b0);
}
// !! According to documentation, interrupts are enabled / disabled
// after the instruction next to di/ei is executed.
void op_di(void *_a, void *_b) {
int_count = 2;
int_opt = INT_DISABLE;
//regs.ime_flag = 0;
}
void op_ei(void *_a, void *_b) {
int_count = 2;
int_opt = INT_ENABLE;
//regs.ime_flag = 1;
}
void op_push(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
*regs.SP -= 2;
//mem_write_16(*regs.SP, *a);
// which one is the good one???
mem_write_8(*regs.SP, (uint8_t)(*a & 0x00FF));
mem_write_8(*regs.SP+1, (uint8_t)((*a & 0xFF00) >> 8));
}
void op_pop(void *_a, void *_b) {
uint16_t *a = (uint16_t*)_a;
//*a = mem_read_16(*regs.SP);
// which one is the good one???
*a = ((uint16_t)mem_read_8(*regs.SP+1) << 8) +
(uint16_t)mem_read_8(*regs.SP);
if (a == regs.AF) {
*regs.F &= 0xF0;
}
*regs.SP += 2;
}
void op_jp(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint16_t *b = (uint16_t*)_b;
uint8_t jump;
if (a == NULL) {
regs.PC = *b;
} else {
switch (*a) {
case COND_NZ: jump = (*regs.F & Z_FLAG) ? 0 : 1; break;
case COND_Z: jump = (*regs.F & Z_FLAG) ? 1 : 0; break;
case COND_NC: jump = (*regs.F & C_FLAG) ? 0 : 1; break;
case COND_C: jump = (*regs.F & C_FLAG) ? 1 : 0; break;
}
if (jump) {
regs.PC = *b;
ext_cycles = 1;
}
}
}
void op_jr(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
int8_t *b = (int8_t*)_b;
uint8_t jump;
if (a == NULL) {
regs.PC += *b;
} else {
switch (*a) {
case COND_NZ: jump = (*regs.F & Z_FLAG) ? 0 : 1; break;
case COND_Z: jump = (*regs.F & Z_FLAG) ? 1 : 0; break;
case COND_NC: jump = (*regs.F & C_FLAG) ? 0 : 1; break;
case COND_C: jump = (*regs.F & C_FLAG) ? 1 : 0; break;
}
if (jump) {
regs.PC += *b;
ext_cycles = 1;
}
}
}
void op_call(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint16_t *b = (uint16_t*)_b;
uint8_t jump;
if (a == NULL) {
op_push(®s.PC, NULL);
regs.PC = *b;
} else {
switch (*a) {
case COND_NZ: jump = (*regs.F & Z_FLAG) ? 0 : 1; break;
case COND_Z: jump = (*regs.F & Z_FLAG) ? 1 : 0; break;
case COND_NC: jump = (*regs.F & C_FLAG) ? 0 : 1; break;
case COND_C: jump = (*regs.F & C_FLAG) ? 1 : 0; break;
}
if (jump) {
op_push(®s.PC, NULL);
regs.PC = *b;
ext_cycles = 1;
}
}
}
void op_ret(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t jump;
if (a == NULL) {
op_pop(®s.PC, NULL);
} else {
switch (*a) {
case COND_NZ: jump = (*regs.F & Z_FLAG) ? 0 : 1; break;
case COND_Z: jump = (*regs.F & Z_FLAG) ? 1 : 0; break;
case COND_NC: jump = (*regs.F & C_FLAG) ? 0 : 1; break;
case COND_C: jump = (*regs.F & C_FLAG) ? 1 : 0; break;
}
if (jump) {
op_pop(®s.PC, NULL);
ext_cycles = 1;
}
}
}
void op_reti(void *_a, void *_b) {
op_pop(®s.PC, NULL);
// Delay the enable for one step???
op_ei(NULL, NULL);
}
void op_rst(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
op_push(®s.PC, NULL);
regs.PC = *a;
}
void op_cpl(void *_a, void *_b) {
*regs.A = ~(*regs.A);
set_flag(N_FLAG, 1);
set_flag(H_FLAG, 1);
}
// http://www.z80.info/z80syntx.htm#DAA
#define BCD_COND(c_flag, up_from, up_to, h_flag, lo_from, lo_to) \
(up >= up_from && up <= up_to && \
lo >= lo_from && lo <= lo_to && \
get_flag(C_FLAG) == c_flag && \
get_flag(H_FLAG) == h_flag)
void op_daa(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint16_t a_cpy = *a;
if (get_flag(N_FLAG)) {
if (get_flag(H_FLAG)) {
a_cpy = (a_cpy - 0x06) & 0xFF;
}
if (get_flag(C_FLAG)) {
a_cpy -= 0x60;
}
} else {
if (get_flag(H_FLAG) || (a_cpy & 0x0F) > 9) {
a_cpy += 0x06;
}
if (get_flag(C_FLAG) || a_cpy > 0x9F) {
a_cpy += 0x60;
}
}
if ((a_cpy & 0x100) == 0x100) {
set_flag(C_FLAG, 1);
}
set_flag(H_FLAG, 0);
*a = a_cpy;
set_flag_Z(a);
}
void op_stop(void *_a, void *_b) {
// TODO
// printf("Stopped: [%04X] %04X\n", regs.PC - 2, mem_read_16(regs.PC - 2));
}
void op_nop(void *_a, void *_b) {
}
void op_undef(void *_a, void *_b) {
// TODO
}
void op_pref_cb(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
exec_op_cb(*a);
}
// prefix CB opcodes
void op_rlc(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b7 = (*a & 0x80) >> 7;
*a = *a << 1;
*a += b7;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b7);
}
void op_rrc(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b0 = *a & 0x01;
*a = *a >> 1;
*a += b0 << 7;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b0);
}
void op_rl(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b7 = (*a & 0x80) >> 7;
*a = *a << 1;
*a += (*regs.F & C_FLAG) >> 4;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b7);
}
void op_rr(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b0 = *a & 0x01;
*a = *a >> 1;
*a += ((*regs.F & C_FLAG) >> 4) << 7;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b0);
}
void op_sla(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b7 = (*a & 0x80) >> 7;
*a = *a << 1;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b7);
}
void op_sra(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b0 = *a & 0x01;
uint8_t b7 = (*a & 0x80) >> 7;
*a = *a >> 1;
*a += b7 << 7;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b0);
}
void op_swap(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
*a = (*a << 4) + ((*a & 0xF0) >> 4);
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, 0);
}
void op_srl(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t b0 = *a & 0x01;
*a = *a >> 1;
set_flag_Z(a);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 0);
set_flag(C_FLAG, b0);
}
void op_bit(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
set_flag(Z_FLAG, (*a & (1 << *b)) ? 0 : 1);
set_flag(N_FLAG, 0);
set_flag(H_FLAG, 1);
}
void op_res(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
*a &= ~(1 << *b);
}
void op_set(void *_a, void *_b) {
uint8_t *a = (uint8_t*)_a;
uint8_t *b = (uint8_t*)_b;
*a |= 1 << *b;
}
/*
#define SET_OP(i, d, f, _a, _b, c) \
ops[i].desc = d; \
ops[i].handler = &f; \
ops[i].a = _a; \
ops[i].b = _b; \
ops[i].cycles = c;
*/
// (opcode, description, function handler, parameter a, parameter b,
// memory access, byte length, normal cycles, extra cycles)
#define SET_OP(i, d, f, _a, _b, o, l, c0, c1) \
ops[i].desc = d; \
ops[i].handler = &f; \
ops[i].a = _a; \
ops[i].b = _b; \
ops[i].opt = o; \
ops[i].length = l; \
ops[i].cycles[0] = c0; \
ops[i].cycles[1] = c1;
// !! The desc parameter is stored in the stack of set_opcodes function :S
void set_opcodes() {
SET_OP(0x00, "NOP", op_nop, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x01, "LD BC,d16", op_ld_16, regs.BC, imm_16, NONE, 3, 12, 0);
SET_OP(0x02, "LD (BC),A", op_ld_8, regs.BC, regs.A, MEM_W_16a, 1, 8, 0);
SET_OP(0x03, "INC BC", op_inc_16, regs.BC, NULL, NONE, 1, 8, 0);
SET_OP(0x04, "INC B", op_inc_8, regs.B, NULL, NONE, 1, 4, 0);
SET_OP(0x05, "DEC B", op_dec_8, regs.B, NULL, NONE, 1, 4, 0);
SET_OP(0x06, "LD B,d8", op_ld_8, regs.B, imm_8, NONE, 2, 8, 0);
SET_OP(0x07, "RLCA", op_rlca, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x08, "LD (a16),SP", op_ld_16, imm_16, regs.SP, MEM_W_16a_16d, 3, 20, 0);
SET_OP(0x09, "ADD HL,BC", op_add_16, regs.HL, regs.BC, NONE, 1, 8, 0);
SET_OP(0x0A, "LD A,(BC)", op_ld_8, regs.A, regs.BC, MEM_R_16a, 1, 8, 0);
SET_OP(0x0B, "DEC BC", op_dec_16, regs.BC, NULL, NONE, 1, 8, 0);
SET_OP(0x0C, "INC C", op_inc_8, regs.C, NULL, NONE, 1, 4, 0);
SET_OP(0x0D, "DEC C", op_dec_8, regs.C, NULL, NONE, 1, 4, 0);
SET_OP(0x0E, "LD C,d8", op_ld_8, regs.C, imm_8, NONE, 2, 8, 0);
SET_OP(0x0F, "RRCA", op_rrca, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x10, "STOP 0", op_stop, &C_0, NULL, NONE, 2, 4, 0);
SET_OP(0x11, "LD DE,d16", op_ld_16, regs.DE, imm_16, NONE, 3, 12, 0);
SET_OP(0x12, "LD (DE),A", op_ld_8, regs.DE, regs.A, MEM_W_16a, 1, 8, 0);
SET_OP(0x13, "INC DE", op_inc_16, regs.DE, NULL, NONE, 1, 8, 0);
SET_OP(0x14, "INC D", op_inc_8, regs.D, NULL, NONE, 1, 4, 0);
SET_OP(0x15, "DEC D", op_dec_8, regs.D, NULL, NONE, 1, 4, 0);
SET_OP(0x16, "LD D,d8", op_ld_8, regs.D, imm_8, NONE, 2, 8, 0);
SET_OP(0x17, "RLA", op_rla, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x18, "JR r8", op_jr, NULL, imm_8, NONE, 2, 12, 0);
SET_OP(0x19, "ADD HL,DE", op_add_16, regs.HL, regs.DE, NONE, 1, 8, 0);
SET_OP(0x1A, "LD A,(DE)", op_ld_8, regs.A, regs.DE, MEM_R_16a, 1, 8, 0);
SET_OP(0x1B, "DEC DE", op_dec_16, regs.DE, NULL, NONE, 1, 8, 0);
SET_OP(0x1C, "INC E", op_inc_8, regs.E, NULL, NONE, 1, 4, 0);
SET_OP(0x1D, "DEC E", op_dec_8, regs.E, NULL, NONE, 1, 4, 0);
SET_OP(0x1E, "LD E,d8", op_ld_8, regs.E, imm_8, NONE, 2, 8, 0);
SET_OP(0x1F, "RRA", op_rra, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x20, "JR NZ,r8", op_jr, &C_NZ, imm_8, NONE, 2, 8, 12);
SET_OP(0x21, "LD HL,d16", op_ld_16, regs.HL, imm_16, NONE, 3, 12, 0);
SET_OP(0x22, "LD (HL+),A", op_ldi, regs.HL, regs.A, NONE, 1, 8, 0);
SET_OP(0x23, "INC HL", op_inc_16, regs.HL, NULL, NONE, 1, 8, 0);
SET_OP(0x24, "INC H", op_inc_8, regs.H, NULL, NONE, 1, 4, 0);
SET_OP(0x25, "DEC H", op_dec_8, regs.H, NULL, NONE, 1, 4, 0);
SET_OP(0x26, "LD H,d8", op_ld_8, regs.H, imm_8, NONE, 2, 8, 0);
SET_OP(0x27, "DAA", op_daa, regs.A, NULL, NONE, 1, 4, 0);
SET_OP(0x28, "JR Z,r8", op_jr, &C_Z, imm_8, NONE, 2, 8, 12);
SET_OP(0x29, "ADD HL,HL", op_add_16, regs.HL, regs.HL, NONE, 1, 8, 0);
SET_OP(0x2A, "LD A,(HL+)", op_ldi, regs.A, regs.HL, NONE, 1, 8, 0);
SET_OP(0x2B, "DEC HL", op_dec_16, regs.HL, NULL, NONE, 1, 8, 0);
SET_OP(0x2C, "INC L", op_inc_8, regs.L, NULL, NONE, 1, 4, 0);
SET_OP(0x2D, "DEC L", op_dec_8, regs.L, NULL, NONE, 1, 4, 0);
SET_OP(0x2E, "LD L,d8", op_ld_8, regs.L, imm_8, NONE, 2, 8, 0);
SET_OP(0x2F, "CPL", op_cpl, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x30, "JR NC,r8", op_jr, &C_NC, imm_8, NONE, 2, 8, 12);
SET_OP(0x31, "LD SP,d16", op_ld_16, regs.SP, imm_16, NONE, 3, 12, 0);
SET_OP(0x32, "LD (HL-),A", op_ldd, regs.HL, regs.A, NONE, 1, 8, 0);
SET_OP(0x33, "INC SP", op_inc_16, regs.SP, NULL, NONE, 1, 8, 0);
SET_OP(0x34, "INC (HL)", op_inc_8, regs.HL, NULL, MEM_RW_16a, 1, 12, 0);
SET_OP(0x35, "DEC (HL)", op_dec_8, regs.HL, NULL, MEM_RW_16a, 1, 12, 0);
SET_OP(0x36, "LD (HL),d8", op_ld_8, regs.HL, imm_8, MEM_W_16a, 2, 12, 0);
SET_OP(0x37, "SCF", op_scf, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x38, "JR C,r8", op_jr, &C_C, imm_8, NONE, 2, 8, 12);
SET_OP(0x39, "ADD HL,SP", op_add_16, regs.HL, regs.SP, NONE, 1, 8, 0);
SET_OP(0x3A, "LD A,(HL-)", op_ldd, regs.A, regs.HL, NONE, 1, 8, 0);
SET_OP(0x3B, "DEC SP", op_dec_16, regs.SP, NULL, NONE, 1, 8, 0);
SET_OP(0x3C, "INC A", op_inc_8, regs.A, NULL, NONE, 1, 4, 0);
SET_OP(0x3D, "DEC A", op_dec_8, regs.A, NULL, NONE, 1, 4, 0);
SET_OP(0x3E, "LD A,d8", op_ld_8, regs.A, imm_8, NONE, 2, 8, 0);
SET_OP(0x3F, "CCF", op_ccf, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x40, "LD B,B", op_ld_8, regs.B, regs.B, NONE, 1, 4, 0);
SET_OP(0x41, "LD B,C", op_ld_8, regs.B, regs.C, NONE, 1, 4, 0);
SET_OP(0x42, "LD B,D", op_ld_8, regs.B, regs.D, NONE, 1, 4, 0);
SET_OP(0x43, "LD B,E", op_ld_8, regs.B, regs.E, NONE, 1, 4, 0);
SET_OP(0x44, "LD B,H", op_ld_8, regs.B, regs.H, NONE, 1, 4, 0);
SET_OP(0x45, "LD B,L", op_ld_8, regs.B, regs.L, NONE, 1, 4, 0);
SET_OP(0x46, "LD B,(HL)", op_ld_8, regs.B, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x47, "LD B,A", op_ld_8, regs.B, regs.A, NONE, 1, 4, 0);
SET_OP(0x48, "LD C,B", op_ld_8, regs.C, regs.B, NONE, 1, 4, 0);
SET_OP(0x49, "LD C,C", op_ld_8, regs.C, regs.C, NONE, 1, 4, 0);
SET_OP(0x4A, "LD C,D", op_ld_8, regs.C, regs.D, NONE, 1, 4, 0);
SET_OP(0x4B, "LD C,E", op_ld_8, regs.C, regs.E, NONE, 1, 4, 0);
SET_OP(0x4C, "LD C,H", op_ld_8, regs.C, regs.H, NONE, 1, 4, 0);
SET_OP(0x4D, "LD C,L", op_ld_8, regs.C, regs.L, NONE, 1, 4, 0);
SET_OP(0x4E, "LD C,(HL)", op_ld_8, regs.C, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x4F, "LD C,A", op_ld_8, regs.C, regs.A, NONE, 1, 4, 0);
SET_OP(0x50, "LD D,B", op_ld_8, regs.D, regs.B, NONE, 1, 4, 0);
SET_OP(0x51, "LD D,C", op_ld_8, regs.D, regs.C, NONE, 1, 4, 0);
SET_OP(0x52, "LD D,D", op_ld_8, regs.D, regs.D, NONE, 1, 4, 0);
SET_OP(0x53, "LD D,E", op_ld_8, regs.D, regs.E, NONE, 1, 4, 0);
SET_OP(0x54, "LD D,H", op_ld_8, regs.D, regs.H, NONE, 1, 4, 0);
SET_OP(0x55, "LD D,L", op_ld_8, regs.D, regs.L, NONE, 1, 4, 0);
SET_OP(0x56, "LD D,(HL)", op_ld_8, regs.D, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x57, "LD D,A", op_ld_8, regs.D, regs.A, NONE, 1, 4, 0);
SET_OP(0x58, "LD E,B", op_ld_8, regs.E, regs.B, NONE, 1, 4, 0);
SET_OP(0x59, "LD E,C", op_ld_8, regs.E, regs.C, NONE, 1, 4, 0);
SET_OP(0x5A, "LD E,D", op_ld_8, regs.E, regs.D, NONE, 1, 4, 0);
SET_OP(0x5B, "LD E,E", op_ld_8, regs.E, regs.E, NONE, 1, 4, 0);
SET_OP(0x5C, "LD E,H", op_ld_8, regs.E, regs.H, NONE, 1, 4, 0);
SET_OP(0x5D, "LD E,L", op_ld_8, regs.E, regs.L, NONE, 1, 4, 0);
SET_OP(0x5E, "LD E,(HL)", op_ld_8, regs.E, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x5F, "LD E,A", op_ld_8, regs.E, regs.A, NONE, 1, 4, 0);
SET_OP(0x60, "LD H,B", op_ld_8, regs.H, regs.B, NONE, 1, 4, 0);
SET_OP(0x61, "LD H,C", op_ld_8, regs.H, regs.C, NONE, 1, 4, 0);
SET_OP(0x62, "LD H,D", op_ld_8, regs.H, regs.D, NONE, 1, 4, 0);
SET_OP(0x63, "LD H,E", op_ld_8, regs.H, regs.E, NONE, 1, 4, 0);
SET_OP(0x64, "LD H,H", op_ld_8, regs.H, regs.H, NONE, 1, 4, 0);
SET_OP(0x65, "LD H,L", op_ld_8, regs.H, regs.L, NONE, 1, 4, 0);
SET_OP(0x66, "LD H,(HL)", op_ld_8, regs.H, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x67, "LD H,A", op_ld_8, regs.H, regs.A, NONE, 1, 4, 0);
SET_OP(0x68, "LD L,B", op_ld_8, regs.L, regs.B, NONE, 1, 4, 0);
SET_OP(0x69, "LD L,C", op_ld_8, regs.L, regs.C, NONE, 1, 4, 0);
SET_OP(0x6A, "LD L,D", op_ld_8, regs.L, regs.D, NONE, 1, 4, 0);
SET_OP(0x6B, "LD L,E", op_ld_8, regs.L, regs.E, NONE, 1, 4, 0);
SET_OP(0x6C, "LD L,H", op_ld_8, regs.L, regs.H, NONE, 1, 4, 0);
SET_OP(0x6D, "LD L,L", op_ld_8, regs.L, regs.L, NONE, 1, 4, 0);
SET_OP(0x6E, "LD L,(HL)", op_ld_8, regs.L, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x6F, "LD L,A", op_ld_8, regs.L, regs.A, NONE, 1, 4, 0);
SET_OP(0x70, "LD (HL),B", op_ld_8, regs.HL, regs.B, MEM_W_16a, 1, 8, 0);
SET_OP(0x71, "LD (HL),C", op_ld_8, regs.HL, regs.C, MEM_W_16a, 1, 8, 0);
SET_OP(0x72, "LD (HL),D", op_ld_8, regs.HL, regs.D, MEM_W_16a, 1, 8, 0);
SET_OP(0x73, "LD (HL),E", op_ld_8, regs.HL, regs.E, MEM_W_16a, 1, 8, 0);
SET_OP(0x74, "LD (HL),H", op_ld_8, regs.HL, regs.H, MEM_W_16a, 1, 8, 0);
SET_OP(0x75, "LD (HL),L", op_ld_8, regs.HL, regs.L, MEM_W_16a, 1, 8, 0);
SET_OP(0x76, "HALT", op_halt, NULL, NULL, NONE, 1, 4, 0);
SET_OP(0x77, "LD (HL),A", op_ld_8, regs.HL, regs.A, MEM_W_16a, 1, 8, 0);
SET_OP(0x78, "LD A,B", op_ld_8, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0x79, "LD A,C", op_ld_8, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0x7A, "LD A,D", op_ld_8, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0x7B, "LD A,E", op_ld_8, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0x7C, "LD A,H", op_ld_8, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0x7D, "LD A,L", op_ld_8, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0x7E, "LD A,(HL)", op_ld_8, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x7F, "LD A,A", op_ld_8, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0x80, "ADD A,B", op_add_8, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0x81, "ADD A,C", op_add_8, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0x82, "ADD A,D", op_add_8, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0x83, "ADD A,E", op_add_8, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0x84, "ADD A,H", op_add_8, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0x85, "ADD A,L", op_add_8, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0x86, "ADD A,(HL)", op_add_8, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x87, "ADD A,A", op_add_8, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0x88, "ADC A,B", op_adc, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0x89, "ADC A,C", op_adc, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0x8A, "ADC A,D", op_adc, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0x8B, "ADC A,E", op_adc, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0x8C, "ADC A,H", op_adc, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0x8D, "ADC A,L", op_adc, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0x8E, "ADC A,(HL)", op_adc, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x8F, "ADC A,A", op_adc, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0x90, "SUB B", op_sub, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0x91, "SUB C", op_sub, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0x92, "SUB D", op_sub, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0x93, "SUB E", op_sub, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0x94, "SUB H", op_sub, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0x95, "SUB L", op_sub, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0x96, "SUB (HL)", op_sub, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x97, "SUB A", op_sub, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0x98, "SBC A,B", op_sbc, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0x99, "SBC A,C", op_sbc, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0x9A, "SBC A,D", op_sbc, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0x9B, "SBC A,E", op_sbc, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0x9C, "SBC A,H", op_sbc, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0x9D, "SBC A,L", op_sbc, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0x9E, "SBC A,(HL)", op_sbc, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0x9F, "SBC A,A", op_sbc, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0xA0, "AND B", op_and, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0xA1, "AND C", op_and, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0xA2, "AND D", op_and, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0xA3, "AND E", op_and, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0xA4, "AND H", op_and, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0xA5, "AND L", op_and, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0xA6, "AND (HL)", op_and, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0xA7, "AND A", op_and, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0xA8, "XOR B", op_xor, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0xA9, "XOR C", op_xor, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0xAA, "XOR D", op_xor, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0xAB, "XOR E", op_xor, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0xAC, "XOR H", op_xor, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0xAD, "XOR L", op_xor, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0xAE, "XOR (HL)", op_xor, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0xAF, "XOR A", op_xor, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0xB0, "OR B", op_or, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0xB1, "OR C", op_or, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0xB2, "OR D", op_or, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0xB3, "OR E", op_or, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0xB4, "OR H", op_or, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0xB5, "OR L", op_or, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0xB6, "OR (HL)", op_or, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0xB7, "OR A", op_or, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0xB8, "CP B", op_cp, regs.A, regs.B, NONE, 1, 4, 0);
SET_OP(0xB9, "CP C", op_cp, regs.A, regs.C, NONE, 1, 4, 0);
SET_OP(0xBA, "CP D", op_cp, regs.A, regs.D, NONE, 1, 4, 0);
SET_OP(0xBB, "CP E", op_cp, regs.A, regs.E, NONE, 1, 4, 0);
SET_OP(0xBC, "CP H", op_cp, regs.A, regs.H, NONE, 1, 4, 0);
SET_OP(0xBD, "CP L", op_cp, regs.A, regs.L, NONE, 1, 4, 0);
SET_OP(0xBE, "CP (HL)", op_cp, regs.A, regs.HL, MEM_R_16a, 1, 8, 0);
SET_OP(0xBF, "CP A", op_cp, regs.A, regs.A, NONE, 1, 4, 0);
SET_OP(0xC0, "RET NZ", op_ret, &C_NZ, NULL, NONE, 1, 8, 20);
SET_OP(0xC1, "POP BC", op_pop, regs.BC, NULL, NONE, 1, 12, 0);
SET_OP(0xC2, "JP NZ,a16", op_jp, &C_NZ, imm_16, NONE, 3, 12, 16);
SET_OP(0xC3, "JP a16", op_jp, NULL, imm_16, NONE, 3, 16, 0);
SET_OP(0xC4, "CALL NZ,a16", op_call, &C_NZ, imm_16, NONE, 3, 12, 24);
SET_OP(0xC5, "PUSH BC", op_push, regs.BC, NULL, NONE, 1, 16, 0);
SET_OP(0xC6, "ADD A,d8", op_add_8, regs.A, imm_8, NONE, 2, 8, 0);
SET_OP(0xC7, "RST 00H", op_rst, &C_00H, NULL, NONE, 1, 16, 0);
SET_OP(0xC8, "RET Z", op_ret, &C_Z, NULL, NONE, 1, 8, 20);
SET_OP(0xC9, "RET", op_ret, NULL, NULL, NONE, 1, 16, 0);
SET_OP(0xCA, "JP Z,a16", op_jp, &C_Z, imm_16, NONE, 3, 12, 16);
SET_OP(0xCB, "PREFIX CB", op_pref_cb, imm_8, NULL, NONE, 2, 4, 0);
SET_OP(0xCC, "CALL Z,a16", op_call, &C_Z, imm_16, NONE, 3, 12, 24);
SET_OP(0xCD, "CALL a16", op_call, NULL, imm_16, NONE, 3, 24, 0);
SET_OP(0xCE, "ADC A,d8", op_adc, regs.A, imm_8, NONE, 2, 8, 0);
SET_OP(0xCF, "RST 08H", op_rst, &C_08H, NULL, NONE, 1, 16, 0);
SET_OP(0xD0, "RET NC", op_ret, &C_NC, NULL, NONE, 1, 8, 20);
SET_OP(0xD1, "POP DE", op_pop, regs.DE, NULL, NONE, 1, 12, 0);
SET_OP(0xD2, "JP NC,a16", op_jp, &C_NC, imm_16, NONE, 3, 12, 16);
SET_OP(0xD3, "-", op_undef, NULL, NULL, NONE, 1, 0, 0);
SET_OP(0xD4, "CALL NC,a16", op_call, &C_NC, imm_16, NONE, 3, 12, 24);
SET_OP(0xD5, "PUSH DE", op_push, regs.DE, NULL, NONE, 1, 16, 0);
SET_OP(0xD6, "SUB d8", op_sub, regs.A, imm_8, NONE, 2, 8, 0);
SET_OP(0xD7, "RST 10H", op_rst, &C_10H, NULL, NONE, 1, 16, 0);
SET_OP(0xD8, "RET C", op_ret, &C_C, NULL, NONE, 1, 8, 20);
SET_OP(0xD9, "RETI", op_reti, NULL, NULL, NONE, 1, 16, 0);