ip: dvi2rgb: Critical warnings when Debug disabled (low priority)

[sbobrowicz]

When you don't select the new option to include the debug module, there are several critical warnings that get generated during OoC synthesis due to the XDC not finding the ILA signals. I think the solution will be to figure out how to conditionally include the XDC constraints related to the debug core based on the users choice for the parameter. Here are the generated critical warnings:

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_refclk'. The XDC file /home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_refclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file /home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:1]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:2]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:3]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:4]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:5]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:6]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:7]

[elodg]

Xilinx:
"CR-983906 has already been placed for the similar issue which is slated to be fixed in 2018.3. The idea behind fix is to provide a flow to use the tcl to show the generic way of providing the constraints. "

Revisit the issue then