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Incorrect counter function when writing to SlaveCtl. #61

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elodg opened this issue Feb 1, 2022 · 0 comments

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elodg commented Feb 1, 2022

vivado-library/ip/dvi2rgb/src/TWI_SlaveCtl.vhd

Line 234 in 0722144

if ((state = stSAck and rd_wrn = '1') or

Counter bitCount is not being reset to 7 when exiting stSAck and entering stWrite (rd_wrn = '0'). Correct by removing condition "and rd_wrn = '1'".

elodg self-assigned this

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