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codec.txt
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# **********************************************************
# Copyright (c) 2016 ARM Limited. All rights reserved.
# **********************************************************
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# * Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# * Neither the name of ARM Limited nor the names of its contributors may be
# used to endorse or promote products derived from this software without
# specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGE.
# Data read by "codec.py" and used to generate some C source files.
# After changing this file, run "codec.py" in this directory.
# Text from '#' to the end of the line is a comment.
################################################################################
# Operand types
# The syntax here is: mask opndtype
# Each operand type is listed here with a mask, consisting of '-', '?' and 'x',
# showing how the bits are used by the encoder/decoder functions,
# {de,en}code_opnd_OPNDTYPE, in "codec.c". The operands are ordered by pattern.
#
# '-' : Bit is not handled by operand encoder or decoder.
# '?' : Bit is read by encoder and decoder but not generated by encoder.
# 'x' : Bit is read by decoder and generated by encoder.
#
# Thus an operand encoder may generate a bit that is read by another operand
# encoder, but it is an error if there is a cyclic dependency.
# Hints for understanding the operand type names:
# In register operands (e.g. w10) the number refers to the position of the lowest bit.
# In memory operands (e.g. mem7) the number refers to the number of offset bits.
-------------------------------- impx30 # implicit X30 operand
-------------------------------- lsl # implicit LSL for ADD/MOV (immediate)
-------------------------------- h_sz # element width of FP vector reg, used to
# distinguish FP16 and float/double encs
----------------------------xxxx nzcv # flag bit specifier for CCMN, CCMP
---------------------------xxxxx w0 # W register (or WZR)
---------------------------xxxxx w0p0 # even-numbered W register (or WZR)
---------------------------xxxxx w0p1 # ... add 1
---------------------------xxxxx x0 # X register (or XZR)
---------------------------xxxxx memx0 # X register used as memref for SYS
---------------------------xxxxx x0p0 # even-numbered X register (or XZR)
---------------------------xxxxx x0p1 # ... add 1
---------------------------xxxxx b0 # B register
---------------------------xxxxx h0 # H register
---------------------------xxxxx s0 # S register
---------------------------xxxxx d0 # D register
---------------------------xxxxx q0 # Q register
---------------------------xxxxx z0 # Z register
---------------------------xxxxx q0p1 # Q register, add 1
---------------------------xxxxx q0p2 # Q register, add 2
---------------------------xxxxx q0p3 # Q register, add 3
---------------------------xxxxx prfop # prefetch operation
----------------------xxxxx----- w5 # W register (or WZR)
----------------------xxxxx----- x5 # X register (or XZR)
----------------------xxxxx----- x5sp # X register or XSP
----------------------xxxxx----- h5 # H register
----------------------xxxxx----- s5 # S register
----------------------xxxxx----- d5 # D register
----------------------xxxxx----- q5 # Q register
----------------------xxxxx----- z5 # Z register
----------------------xxxxx----- mem9qpost # size is 16 bytes; post-index
--------------------xx---------- vmsz # B/H/S/D for load/store multiple structures
--------------------xxxx-------- imm4 # option for CLREX, DSB, DMB, ISB
-------------------xxx---------- extam # extend amount
------------------xxxx---------- p10_low # SVE predicate registers p0-p7
-----------------xxxxx---------- ign10 # ignored reg field in load/store exclusive
-----------------xxxxx---------- w10 # W register (or WZR)
-----------------xxxxx---------- x10 # X register (or XZR)
-----------------xxxxx---------- s10 # S register
-----------------xxxxx---------- d10 # D register
-----------------xxxxx---------- q10 # Q register
----------------xxx------------- ext # extend type
----------------xxxx------------ cond # condition for CCMN, CCMP
-------------xxxxxxxxxxxxxx----- sysops # immediate operands for SYS
------------xxxxxxxxxxxxxxx----- sysreg # operand of MRS
-----------xxxxx---------------- ign16 # ignored reg field in load/store exclusive
-----------xxxxx---------------- imm5 # immediate for CCMN, CCMP
-----------xxxxx---------------- w16 # W register (or WZR)
-----------xxxxx---------------- w16p0 # even-numbered W register (or WZR)
-----------xxxxx---------------- w16p1 # ... add 1
-----------xxxxx---------------- x16 # X register (or XZR)
-----------xxxxx---------------- x16p0 # even-numbered X register (or XZR)
-----------xxxxx---------------- x16p1 # ... add 1
-----------xxxxx---------------- d16 # D register
-----------xxxxx---------------- q16 # Q register
-----------xxxxx---------------- z16 # Z register
-----------xxxxxxxxx------------ mem9off # immed offset for mem9/mem9post
-----------xxxxxxxxx--xxxxx----- mem9q # size is 16 bytes
-----------xxxxxxxxx--xxxxx----- prf9 # size is 0 bytes (prefetch variant of mem9)
-----------xxxxxxxxx--xxxxx----- memregq # register offset, size is 16 bytes
-----------xxxxxxxxx--xxxxx----- prfreg # register offset, size is 0 (prefetch)
-----------xxxxxxxxxxxxxxxx----- imm16 # immediate for MOVK/MOVN/MOVZ/SVC
----------?-------?-xxxxxxx----- memvr # gets size from 21, 13 and 11:10
----------?-----???-??xxxxx----- memvs # gets size from 21, 15:13 and 11:10
----------?xxxxx--?-??---------- x16immvr # computes immed from 21, 13 and 11:10
----------?xxxxx???-??---------- x16immvs # computes immed from 21, 15:13 and 11:10
----------xx--------x----------- vindex_H # Index for vector with half elements (0-7)
----------xxxxxxxxxxxx---------- imm12 # immediate for ADD/SUB
----------xxxxxxxxxxxxxxxxx----- mem12q # size is 16 bytes
----------xxxxxxxxxxxxxxxxx----- prf12 # size is 0 bytes (prefetch variant of mem12)
---------?x---------x----------- vindex_SD # Index for vector with single or double
---------x---------------------- imm12sh # shift for ADD/SUB (immediate); '0x'
# elements, depending on bit 22 (sz)
---------x---------------------- sd_sz # element width of FP vector reg for single
--------xx---------------------- b_sz # element width of a vector (8<<b_sz)
--------xx---------------------- hs_sz # element width of a vector (8<<hs_sz)
--------xx---------------------- bhs_sz # element width of a vector (8<<bhs_sz)
--------xx---------------------- bhsd_sz # element width of a vector (8<<bhsd_sz)
--------xx---------------------- bd_sz # element width of a vector (8<<bd_sz)
--------xx---------------------- shift3 # shift type for add/sub (shifted register)
--------xx---------------------- shift4 # shift type for logical (shifted register)
--------xx-----------------xxxxx float_reg0 # H, S or D register
--------xx------------xxxxx----- float_reg5 # H, S or D register
--------xx-------xxxxx---------- float_reg10 # H, S or D register
--------xx-xxxxx---------------- float_reg16 # H, S or D register
-?--------------------xxxxx----- mem0p # gets size from 30; no offset, pair
-?---------xxxxx????------------ x16imm # computes immed from 30 and 15:12
-x------------------------------ index3 # index of D subreg in Q: 0-1
-x-------------------------xxxxx dq0 # Q register if bit 30 is set, else D
-x-------------------------xxxxx dq0p1 # ... add 1
-x-------------------------xxxxx dq0p2 # ... add 2
-x-------------------------xxxxx dq0p3 # ... add 3
-x-------------------------xxxxx vt0 # checks (30, 11:10) != (0, 0b11)
-x-------------------------xxxxx vt1 # ... add 1
-x-------------------------xxxxx vt2 # ... add 2
-x-------------------------xxxxx vt3 # ... add 3
-x--------------------xxxxx----- dq5 # Q register if bit 30 is set, else D
-x-----------------x------------ index2 # index of S subreg in Q: 0-3
-x-----------------xx----------- index1 # index of H subreg in Q: 0-7
-x-----------------xxx---------- index0 # index of B subreg in Q: 0-15
-x--------------????--xxxxx----- memvm # computes multiplier from 15:12
-x----------xxxx---------------- dq16_h_sz # Q register (0-15) if bit 30 is set, else D
-x---------xxxxx---------------- dq16 # Q register if bit 30 is set, else D
?---------------xxxxxx---------- imm6 # shift amount
?---------------xxxxxx---------- imms # bitfield immediate, checks 31
?---------xxxxxx---------------- immr # bitfield immediate, checks 31
?--------xx--------------------- imm16sh # shift for MOVK/... (immediate); checks 31
??--------------------xxxxx----- mem0 # gets size from 31:30; no offset
??--------------------xxxxx----- mem9post # gets size from 31:30; post-index
??---------xxxxxxxxx--xxxxx----- mem9 # gets size from 31:30
??---------xxxxxxxxx--xxxxx----- memreg # register offset, gets size from 31:30
??--------xxxxxxxxxxxxxxxxx----- mem12 # gets size from 31:30
??---?----------------xxxxx----- mem7post # gets size from 31:30 and 26; post-index
??---?----xxxxxxx--------------- mem7off # gets size from 31:30 and 26
??---?----xxxxxxx-----xxxxx----- mem7 # gets size from 31:30 and 26
??---?--xxxxxxxxxxxxxxxxxxx----- memlit # load literal, gets size from 31:30 and 26
x--------------------------xxxxx wx0 # W/X register (or WZR/XZR)
x--------------------------xxxxx wx0sp # W/X register or WSP/XSP
x---------------------xxxxx----- wx5 # W/X register (or WZR/XZR)
x---------------------xxxxx----- wx5sp # W/X register or WSP/XSP
x----------------xxxxx---------- wx10 # W/X register (or WZR/XZR)
x----------xxxxx---------------- wx16 # W/X register (or WZR/XZR)
################################################################################
# Instruction patterns
# The syntax here is: pattern opcode opndtype* : opndtype*
# Each pattern consists of '0', '1' and 'x'. Patterns must not overlap.
# The opndtypes before/after the ':' correspond to destination/source operands.
# Each 'x' bit must be handled by at least one of the listed opndtypes.
# If several operands handle the same 'x' bit then the automatically generated
# encoder will check that consistent bit patterns are generated.
# Alternative syntax: pattern opcode opndset
# This alternative is used when there is a pair of encoder/decoder functions,
# {de,en}code_opnds_OPNDSET in "codec.c", that handles all the operands together.
# This is used, for example, when the number of operands varies.
# Data Processing - Immediate
## PC-relative addressing
0xx10000xxxxxxxxxxxxxxxxxxxxxxxx adr adr
1xx10000xxxxxxxxxxxxxxxxxxxxxxxx adrp adr
## Add/subtract (immediate)
x00100010xxxxxxxxxxxxxxxxxxxxxxx add wx0sp : wx5sp imm12 lsl imm12sh
x01100010xxxxxxxxxxxxxxxxxxxxxxx adds wx0 : wx5sp imm12 lsl imm12sh
x10100010xxxxxxxxxxxxxxxxxxxxxxx sub wx0sp : wx5sp imm12 lsl imm12sh
x11100010xxxxxxxxxxxxxxxxxxxxxxx subs wx0 : wx5sp imm12 lsl imm12sh
## Logical (immediate)
x00100100xxxxxxxxxxxxxxxxxxxxxxx and logic_imm
x01100100xxxxxxxxxxxxxxxxxxxxxxx orr logic_imm
x10100100xxxxxxxxxxxxxxxxxxxxxxx eor logic_imm
x11100100xxxxxxxxxxxxxxxxxxxxxxx ands logic_imm
## Move wide (immediate)
000100101xxxxxxxxxxxxxxxxxxxxxxx movn w0 : imm16 lsl imm16sh
010100101xxxxxxxxxxxxxxxxxxxxxxx movz w0 : imm16 lsl imm16sh
011100101xxxxxxxxxxxxxxxxxxxxxxx movk w0 : w0 imm16 lsl imm16sh
100100101xxxxxxxxxxxxxxxxxxxxxxx movn x0 : imm16 lsl imm16sh
110100101xxxxxxxxxxxxxxxxxxxxxxx movz x0 : imm16 lsl imm16sh
111100101xxxxxxxxxxxxxxxxxxxxxxx movk x0 : x0 imm16 lsl imm16sh
## Bitfield
0001001100xxxxxxxxxxxxxxxxxxxxxx sbfm w0 : w5 immr imms
0011001100xxxxxxxxxxxxxxxxxxxxxx bfm w0 : w0 w5 immr imms
0101001100xxxxxxxxxxxxxxxxxxxxxx ubfm w0 : w5 immr imms
1001001101xxxxxxxxxxxxxxxxxxxxxx sbfm x0 : x5 immr imms
1011001101xxxxxxxxxxxxxxxxxxxxxx bfm x0 : x0 x5 immr imms
1101001101xxxxxxxxxxxxxxxxxxxxxx ubfm x0 : x5 immr imms
## Extract
00010011100xxxxxxxxxxxxxxxxxxxxx extr w0 : w5 w16 imms
10010011110xxxxxxxxxxxxxxxxxxxxx extr x0 : x5 x16 imms
# Branches, Exception Generating and System instructions
## Unconditional branch (immediate)
000101xxxxxxxxxxxxxxxxxxxxxxxxxx b b
100101xxxxxxxxxxxxxxxxxxxxxxxxxx bl b
## Compare and branch (immediate)
x0110100xxxxxxxxxxxxxxxxxxxxxxxx cbz cbz
x0110101xxxxxxxxxxxxxxxxxxxxxxxx cbnz cbz
## Test and branch (immediate)
x0110110xxxxxxxxxxxxxxxxxxxxxxxx tbz tbz
x0110111xxxxxxxxxxxxxxxxxxxxxxxx tbnz tbz
## Conditional branch (immediate)
01010100xxxxxxxxxxxxxxxxxxx0xxxx bcond bcond
## Exception generation
11010100000xxxxxxxxxxxxxxxx00001 svc : imm16
11010100000xxxxxxxxxxxxxxxx00010 hvc : imm16
11010100000xxxxxxxxxxxxxxxx00011 smc : imm16
11010100001xxxxxxxxxxxxxxxx00000 brk : imm16
11010100010xxxxxxxxxxxxxxxx00000 hlt : imm16
## System
# FIXME i#1569: Add: MSR (immediate), HINT
11010101000000110010000000011111 nop :
11010101000000110010000000111111 yield :
11010101000000110010000001011111 wfe :
11010101000000110010000001111111 wfi :
11010101000000110010000010011111 sev :
11010101000000110010000010111111 sevl :
11010101000000110011xxxx01011111 clrex : imm4
11010101000000110011xxxx10011111 dsb : imm4
11010101000000110011xxxx10111111 dmb : imm4
11010101000000110011xxxx11011111 isb : imm4
1101010100001xxxxxxxxxxxxxxxxxxx sys : sysops memx0
110101010001xxxxxxxxxxxxxxxxxxxx msr msr
# FIXME i#1569: Add: SYSL
110101010011xxxxxxxxxxxxxxxxxxxx mrs x0 : sysreg
## Unconditional branch (register)
1101011000011111000000xxxxx00000 br : x5
1101011000111111000000xxxxx00000 blr impx30 : x5
1101011001011111000000xxxxx00000 ret : x5
# Loads and Stores
## Load/store exclusive
00001000000xxxxx0xxxxxxxxxxxxxxx stxrb mem0 w16 : w0 ign10
00001000000xxxxx1xxxxxxxxxxxxxxx stlxrb mem0 w16 : w0 ign10
00001000010xxxxx0xxxxxxxxxxxxxxx ldxrb w0 : mem0 ign10 ign16
00001000010xxxxx1xxxxxxxxxxxxxxx ldaxrb w0 : mem0 ign10 ign16
00001000100xxxxx1xxxxxxxxxxxxxxx stlrb mem0 : w0 ign10 ign16
0000100011011111111111xxxxxxxxxx ldarb w0 : mem0
01001000000xxxxx0xxxxxxxxxxxxxxx stxrh mem0 w16 : w0 ign10
01001000000xxxxx1xxxxxxxxxxxxxxx stlxrh mem0 w16 : w0 ign10
01001000010xxxxx0xxxxxxxxxxxxxxx ldxrh w0 : mem0 ign10 ign16
01001000010xxxxx1xxxxxxxxxxxxxxx ldaxrh w0 : mem0 ign10 ign16
01001000100xxxxx1xxxxxxxxxxxxxxx stlrh mem0 : w0 ign10 ign16
0100100011011111111111xxxxxxxxxx ldarh w0 : mem0
10001000000xxxxx0xxxxxxxxxxxxxxx stxr mem0 w16 : w0 ign10
10001000000xxxxx1xxxxxxxxxxxxxxx stlxr mem0 w16 : w0 ign10
10001000001xxxxx0xxxxxxxxxxxxxxx stxp mem0p w16 : w0 w10
10001000001xxxxx1xxxxxxxxxxxxxxx stlxp mem0p w16 : w0 w10
10001000010xxxxx0xxxxxxxxxxxxxxx ldxr w0 : mem0 ign10 ign16
10001000010xxxxx1xxxxxxxxxxxxxxx ldaxr w0 : mem0 ign10 ign16
10001000011xxxxx0xxxxxxxxxxxxxxx ldxp w0 w10 : mem0p ign16
10001000011xxxxx1xxxxxxxxxxxxxxx ldaxp w0 w10 : mem0p ign16
10001000100xxxxx1xxxxxxxxxxxxxxx stlr mem0 : w0 ign10 ign16
1000100011011111111111xxxxxxxxxx ldar w0 : mem0
11001000000xxxxx0xxxxxxxxxxxxxxx stxr mem0 w16 : x0 ign10
11001000000xxxxx1xxxxxxxxxxxxxxx stlxr mem0 w16 : x0 ign10
11001000001xxxxx0xxxxxxxxxxxxxxx stxp mem0p w16 : x0 x10
11001000001xxxxx1xxxxxxxxxxxxxxx stlxp mem0p w16 : x0 x10
11001000010xxxxx0xxxxxxxxxxxxxxx ldxr x0 : mem0 ign10 ign16
11001000010xxxxx1xxxxxxxxxxxxxxx ldaxr x0 : mem0 ign10 ign16
11001000011xxxxx0xxxxxxxxxxxxxxx ldxp x0 x10 : mem0p ign16
11001000011xxxxx1xxxxxxxxxxxxxxx ldaxp x0 x10 : mem0p ign16
11001000100xxxxx1xxxxxxxxxxxxxxx stlr mem0 : x0 ign10 ign16
1100100011011111111111xxxxxxxxxx ldar x0 : mem0
### ARMv8.1 atomic instructions
00001000101xxxxx011111xxxxxxxxxx casb w16 mem0 : w16 w0 mem0
00001000101xxxxx111111xxxxxxxxxx caslb w16 mem0 : w16 w0 mem0
00001000111xxxxx011111xxxxxxxxxx casab w16 mem0 : w16 w0 mem0
00001000111xxxxx111111xxxxxxxxxx casalb w16 mem0 : w16 w0 mem0
01001000101xxxxx011111xxxxxxxxxx cash w16 mem0 : w16 w0 mem0
01001000101xxxxx111111xxxxxxxxxx caslh w16 mem0 : w16 w0 mem0
01001000111xxxxx011111xxxxxxxxxx casah w16 mem0 : w16 w0 mem0
01001000111xxxxx111111xxxxxxxxxx casalh w16 mem0 : w16 w0 mem0
10001000101xxxxx011111xxxxxxxxxx cas w16 mem0 : w16 w0 mem0
10001000101xxxxx111111xxxxxxxxxx casl w16 mem0 : w16 w0 mem0
10001000111xxxxx011111xxxxxxxxxx casa w16 mem0 : w16 w0 mem0
10001000111xxxxx111111xxxxxxxxxx casal w16 mem0 : w16 w0 mem0
11001000101xxxxx011111xxxxxxxxxx cas x16 mem0 : x16 x0 mem0
11001000101xxxxx111111xxxxxxxxxx casl x16 mem0 : x16 x0 mem0
11001000111xxxxx011111xxxxxxxxxx casa x16 mem0 : x16 x0 mem0
11001000111xxxxx111111xxxxxxxxxx casal x16 mem0 : x16 x0 mem0
00001000001xxxxx011111xxxxxxxxxx casp w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p
00001000001xxxxx111111xxxxxxxxxx caspl w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p
00001000011xxxxx011111xxxxxxxxxx caspa w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p
00001000011xxxxx111111xxxxxxxxxx caspal w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p
01001000001xxxxx011111xxxxxxxxxx casp x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p
01001000001xxxxx111111xxxxxxxxxx caspl x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p
01001000011xxxxx011111xxxxxxxxxx caspa x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p
01001000011xxxxx111111xxxxxxxxxx caspal x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p
## Load register (literal)
00011000xxxxxxxxxxxxxxxxxxxxxxxx ldr w0 : memlit
00011100xxxxxxxxxxxxxxxxxxxxxxxx ldr s0 : memlit
01011000xxxxxxxxxxxxxxxxxxxxxxxx ldr x0 : memlit
01011100xxxxxxxxxxxxxxxxxxxxxxxx ldr d0 : memlit
10011000xxxxxxxxxxxxxxxxxxxxxxxx ldrsw x0 : memlit
10011100xxxxxxxxxxxxxxxxxxxxxxxx ldr q0 : memlit
11011000xxxxxxxxxxxxxxxxxxxxxxxx prfm : prfop memlit
## Load/store no-allocate pair (offset)
0010100000xxxxxxxxxxxxxxxxxxxxxx stnp mem7 : w0 w10
0010100001xxxxxxxxxxxxxxxxxxxxxx ldnp w0 w10 : mem7
0010110000xxxxxxxxxxxxxxxxxxxxxx stnp mem7 : s0 s10
0010110001xxxxxxxxxxxxxxxxxxxxxx ldnp s0 s10 : mem7
0110110000xxxxxxxxxxxxxxxxxxxxxx stnp mem7 : d0 d10
0110110001xxxxxxxxxxxxxxxxxxxxxx ldnp d0 d10 : mem7
1010100000xxxxxxxxxxxxxxxxxxxxxx stnp mem7 : x0 x10
1010100001xxxxxxxxxxxxxxxxxxxxxx ldnp x0 x10 : mem7
1010110000xxxxxxxxxxxxxxxxxxxxxx stnp mem7 : q0 q10
1010110001xxxxxxxxxxxxxxxxxxxxxx ldnp q0 q10 : mem7
## Load/store register pair (post-indexed)
0010100010xxxxxxxxxxxxxxxxxxxxxx stp mem7post x5sp : w0 w10 x5sp mem7off
0010100011xxxxxxxxxxxxxxxxxxxxxx ldp w0 w10 x5sp : mem7post x5sp mem7off
0010110010xxxxxxxxxxxxxxxxxxxxxx stp mem7post x5sp : s0 s10 x5sp mem7off
0010110011xxxxxxxxxxxxxxxxxxxxxx ldp s0 s10 x5sp : mem7post x5sp mem7off
0110100011xxxxxxxxxxxxxxxxxxxxxx ldpsw x0 x10 x5sp : mem7post x5sp mem7off
0110110010xxxxxxxxxxxxxxxxxxxxxx stp mem7post x5sp : d0 d10 x5sp mem7off
0110110011xxxxxxxxxxxxxxxxxxxxxx ldp d0 d10 x5sp : mem7post x5sp mem7off
1010100010xxxxxxxxxxxxxxxxxxxxxx stp mem7post x5sp : x0 x10 x5sp mem7off
1010100011xxxxxxxxxxxxxxxxxxxxxx ldp x0 x10 x5sp : mem7post x5sp mem7off
1010110010xxxxxxxxxxxxxxxxxxxxxx stp mem7post x5sp : q0 q10 x5sp mem7off
1010110011xxxxxxxxxxxxxxxxxxxxxx ldp q0 q10 x5sp : mem7post x5sp mem7off
## Load/store register pair (offset)
0010100100xxxxxxxxxxxxxxxxxxxxxx stp mem7 : w0 w10
0010100101xxxxxxxxxxxxxxxxxxxxxx ldp w0 w10 : mem7
0010110100xxxxxxxxxxxxxxxxxxxxxx stp mem7 : s0 s10
0010110101xxxxxxxxxxxxxxxxxxxxxx ldp s0 s10 : mem7
0110100101xxxxxxxxxxxxxxxxxxxxxx ldpsw x0 x10 : mem7
0110110100xxxxxxxxxxxxxxxxxxxxxx stp mem7 : d0 d10
0110110101xxxxxxxxxxxxxxxxxxxxxx ldp d0 d10 : mem7
1010100100xxxxxxxxxxxxxxxxxxxxxx stp mem7 : x0 x10
1010100101xxxxxxxxxxxxxxxxxxxxxx ldp x0 x10 : mem7
1010110100xxxxxxxxxxxxxxxxxxxxxx stp mem7 : q0 q10
1010110101xxxxxxxxxxxxxxxxxxxxxx ldp q0 q10 : mem7
## Load/store register pair (pre-indexed)
0010100110xxxxxxxxxxxxxxxxxxxxxx stp mem7 x5sp : w0 w10 x5sp mem7off
0010100111xxxxxxxxxxxxxxxxxxxxxx ldp w0 w10 x5sp : mem7 x5sp mem7off
0010110110xxxxxxxxxxxxxxxxxxxxxx stp mem7 x5sp : s0 s10 x5sp mem7off
0010110111xxxxxxxxxxxxxxxxxxxxxx ldp s0 s10 x5sp : mem7 x5sp mem7off
0110100111xxxxxxxxxxxxxxxxxxxxxx ldpsw x0 x10 x5sp : mem7 x5sp mem7off
0110110110xxxxxxxxxxxxxxxxxxxxxx stp mem7 x5sp : d0 d10 x5sp mem7off
0110110111xxxxxxxxxxxxxxxxxxxxxx ldp d0 d10 x5sp : mem7 x5sp mem7off
1010100110xxxxxxxxxxxxxxxxxxxxxx stp mem7 x5sp : x0 x10 x5sp mem7off
1010100111xxxxxxxxxxxxxxxxxxxxxx ldp x0 x10 x5sp : mem7 x5sp mem7off
1010110110xxxxxxxxxxxxxxxxxxxxxx stp mem7 x5sp : q0 q10 x5sp mem7off
1010110111xxxxxxxxxxxxxxxxxxxxxx ldp q0 q10 x5sp : mem7 x5sp mem7off
## Load/store register (unscaled immediate)
# Base
10111000000xxxxxxxxx00xxxxxxxxxx stur mem9 : w0
11111000000xxxxxxxxx00xxxxxxxxxx stur mem9 : x0
00111000000xxxxxxxxx00xxxxxxxxxx sturb mem9 : w0
01111000000xxxxxxxxx00xxxxxxxxxx sturh mem9 : w0
# SIMD
00111100000xxxxxxxxx00xxxxxxxxxx stur mem9 : b0
01111100000xxxxxxxxx00xxxxxxxxxx stur mem9 : h0
10111100000xxxxxxxxx00xxxxxxxxxx stur mem9 : s0
11111100000xxxxxxxxx00xxxxxxxxxx stur mem9 : d0
00111100100xxxxxxxxx00xxxxxxxxxx stur mem9q : q0
# Base
10111000010xxxxxxxxx00xxxxxxxxxx ldur w0 : mem9
11111000010xxxxxxxxx00xxxxxxxxxx ldur x0 : mem9
00111000010xxxxxxxxx00xxxxxxxxxx ldurb w0 : mem9
01111000010xxxxxxxxx00xxxxxxxxxx ldurh w0 : mem9
00111000100xxxxxxxxx00xxxxxxxxxx ldursb x0 : mem9
00111000110xxxxxxxxx00xxxxxxxxxx ldursb w0 : mem9
01111000100xxxxxxxxx00xxxxxxxxxx ldursh x0 : mem9
01111000110xxxxxxxxx00xxxxxxxxxx ldursh w0 : mem9
10111000100xxxxxxxxx00xxxxxxxxxx ldursw x0 : mem9
# SIMD
00111100010xxxxxxxxx00xxxxxxxxxx ldur b0 : mem9
01111100010xxxxxxxxx00xxxxxxxxxx ldur h0 : mem9
10111100010xxxxxxxxx00xxxxxxxxxx ldur s0 : mem9
11111100010xxxxxxxxx00xxxxxxxxxx ldur d0 : mem9
00111100110xxxxxxxxx00xxxxxxxxxx ldur q0 : mem9q
11111000100xxxxxxxxx00xxxxxxxxxx prfum : prfop prf9 # PRFUM #imm5,[Xn,#simm]
## Load/store register (immediate post-indexed)
00111000000xxxxxxxxx01xxxxxxxxxx strb mem9post x5sp : w0 x5sp mem9off # STRB Wt,[Xn],#simm
00111000010xxxxxxxxx01xxxxxxxxxx ldrb w0 x5sp : mem9post x5sp mem9off
00111000100xxxxxxxxx01xxxxxxxxxx ldrsb x0 x5sp : mem9post x5sp mem9off
00111000110xxxxxxxxx01xxxxxxxxxx ldrsb w0 x5sp : mem9post x5sp mem9off
00111100000xxxxxxxxx01xxxxxxxxxx str mem9post x5sp : b0 x5sp mem9off
00111100010xxxxxxxxx01xxxxxxxxxx ldr b0 x5sp : mem9post x5sp mem9off
00111100100xxxxxxxxx01xxxxxxxxxx str mem9qpost x5sp : q0 x5sp mem9off
00111100110xxxxxxxxx01xxxxxxxxxx ldr q0 x5sp : mem9qpost x5sp mem9off
01111000000xxxxxxxxx01xxxxxxxxxx strh mem9post x5sp : w0 x5sp mem9off
01111000010xxxxxxxxx01xxxxxxxxxx ldrh w0 x5sp : mem9post x5sp mem9off
01111000100xxxxxxxxx01xxxxxxxxxx ldrsh x0 x5sp : mem9post x5sp mem9off
01111000110xxxxxxxxx01xxxxxxxxxx ldrsh w0 x5sp : mem9post x5sp mem9off
01111100000xxxxxxxxx01xxxxxxxxxx str mem9post x5sp : h0 x5sp mem9off
01111100010xxxxxxxxx01xxxxxxxxxx ldr h0 x5sp : mem9post x5sp mem9off
10111000000xxxxxxxxx01xxxxxxxxxx str mem9post x5sp : w0 x5sp mem9off
10111000010xxxxxxxxx01xxxxxxxxxx ldr w0 x5sp : mem9post x5sp mem9off
10111000100xxxxxxxxx01xxxxxxxxxx ldrsw x0 x5sp : mem9post x5sp mem9off
10111100000xxxxxxxxx01xxxxxxxxxx str mem9post x5sp : s0 x5sp mem9off
10111100010xxxxxxxxx01xxxxxxxxxx ldr s0 x5sp : mem9post x5sp mem9off
11111000000xxxxxxxxx01xxxxxxxxxx str mem9post x5sp : x0 x5sp mem9off
11111000010xxxxxxxxx01xxxxxxxxxx ldr x0 x5sp : mem9post x5sp mem9off
11111100000xxxxxxxxx01xxxxxxxxxx str mem9post x5sp : d0 x5sp mem9off
11111100010xxxxxxxxx01xxxxxxxxxx ldr d0 x5sp : mem9post x5sp mem9off
## Load/store register (unprivileged)
00111000000xxxxxxxxx10xxxxxxxxxx sttrb mem9 : w0
00111000010xxxxxxxxx10xxxxxxxxxx ldtrb w0 : mem9
00111000100xxxxxxxxx10xxxxxxxxxx ldtrsb x0 : mem9
00111000110xxxxxxxxx10xxxxxxxxxx ldtrsb w0 : mem9
01111000000xxxxxxxxx10xxxxxxxxxx sttrh mem9 : w0
01111000010xxxxxxxxx10xxxxxxxxxx ldtrh w0 : mem9
01111000100xxxxxxxxx10xxxxxxxxxx ldtrsh x0 : mem9
01111000110xxxxxxxxx10xxxxxxxxxx ldtrsh w0 : mem9
10111000000xxxxxxxxx10xxxxxxxxxx sttr mem9 : w0
10111000010xxxxxxxxx10xxxxxxxxxx ldtr w0 : mem9
10111000100xxxxxxxxx10xxxxxxxxxx ldtrsw x0 : mem9
11111000000xxxxxxxxx10xxxxxxxxxx sttr mem9 : x0
11111000010xxxxxxxxx10xxxxxxxxxx ldtr x0 : mem9
## Load/store register (immediate pre-indexed)
00111000000xxxxxxxxx11xxxxxxxxxx strb mem9 x5sp : w0 x5sp mem9off # STRB Wt,[Xn,#simm]!
00111000010xxxxxxxxx11xxxxxxxxxx ldrb w0 x5sp : mem9 x5sp mem9off
00111000100xxxxxxxxx11xxxxxxxxxx ldrsb x0 x5sp : mem9 x5sp mem9off
00111000110xxxxxxxxx11xxxxxxxxxx ldrsb w0 x5sp : mem9 x5sp mem9off
00111100000xxxxxxxxx11xxxxxxxxxx str mem9 x5sp : b0 x5sp mem9off
00111100010xxxxxxxxx11xxxxxxxxxx ldr b0 x5sp : mem9 x5sp mem9off
00111100100xxxxxxxxx11xxxxxxxxxx str mem9q x5sp : q0 x5sp mem9off
00111100110xxxxxxxxx11xxxxxxxxxx ldr q0 x5sp : mem9q x5sp mem9off
01111000000xxxxxxxxx11xxxxxxxxxx strh mem9 x5sp : w0 x5sp mem9off
01111000010xxxxxxxxx11xxxxxxxxxx ldrh w0 x5sp : mem9 x5sp mem9off
01111000100xxxxxxxxx11xxxxxxxxxx ldrsh x0 x5sp : mem9 x5sp mem9off
01111000110xxxxxxxxx11xxxxxxxxxx ldrsh w0 x5sp : mem9 x5sp mem9off
01111100000xxxxxxxxx11xxxxxxxxxx str mem9 x5sp : h0 x5sp mem9off
01111100010xxxxxxxxx11xxxxxxxxxx ldr h0 x5sp : mem9 x5sp mem9off
10111000000xxxxxxxxx11xxxxxxxxxx str mem9 x5sp : w0 x5sp mem9off
10111000010xxxxxxxxx11xxxxxxxxxx ldr w0 x5sp : mem9 x5sp mem9off
10111000100xxxxxxxxx11xxxxxxxxxx ldrsw x0 x5sp : mem9 x5sp mem9off
10111100000xxxxxxxxx11xxxxxxxxxx str mem9 x5sp : s0 x5sp mem9off
10111100010xxxxxxxxx11xxxxxxxxxx ldr s0 x5sp : mem9 x5sp mem9off
11111000000xxxxxxxxx11xxxxxxxxxx str mem9 x5sp : x0 x5sp mem9off
11111000010xxxxxxxxx11xxxxxxxxxx ldr x0 x5sp : mem9 x5sp mem9off
11111100000xxxxxxxxx11xxxxxxxxxx str mem9 x5sp : d0 x5sp mem9off
11111100010xxxxxxxxx11xxxxxxxxxx ldr d0 x5sp : mem9 x5sp mem9off
## Atomic memory operations (ARMv8.1)
00111000001xxxxx000000xxxxxxxxxx ldaddb w0 mem0 : w16 mem0
00111000001xxxxx000100xxxxxxxxxx ldclrb w0 mem0 : w16 mem0
00111000001xxxxx001000xxxxxxxxxx ldeorb w0 mem0 : w16 mem0
00111000001xxxxx001100xxxxxxxxxx ldsetb w0 mem0 : w16 mem0
00111000001xxxxx010000xxxxxxxxxx ldsmaxb w0 mem0 : w16 mem0
00111000001xxxxx010100xxxxxxxxxx ldsminb w0 mem0 : w16 mem0
00111000001xxxxx011000xxxxxxxxxx ldumaxb w0 mem0 : w16 mem0
00111000001xxxxx011100xxxxxxxxxx lduminb w0 mem0 : w16 mem0
00111000011xxxxx000000xxxxxxxxxx ldaddlb w0 mem0 : w16 mem0
00111000011xxxxx000100xxxxxxxxxx ldclrlb w0 mem0 : w16 mem0
00111000011xxxxx001000xxxxxxxxxx ldeorlb w0 mem0 : w16 mem0
00111000011xxxxx001100xxxxxxxxxx ldsetlb w0 mem0 : w16 mem0
00111000011xxxxx010000xxxxxxxxxx ldsmaxlb w0 mem0 : w16 mem0
00111000011xxxxx010100xxxxxxxxxx ldsminlb w0 mem0 : w16 mem0
00111000011xxxxx011000xxxxxxxxxx ldumaxlb w0 mem0 : w16 mem0
00111000011xxxxx011100xxxxxxxxxx lduminlb w0 mem0 : w16 mem0
00111000101xxxxx000000xxxxxxxxxx ldaddab w0 mem0 : w16 mem0
00111000101xxxxx000100xxxxxxxxxx ldclrab w0 mem0 : w16 mem0
00111000101xxxxx001000xxxxxxxxxx ldeorab w0 mem0 : w16 mem0
00111000101xxxxx001100xxxxxxxxxx ldsetab w0 mem0 : w16 mem0
00111000101xxxxx010000xxxxxxxxxx ldsmaxab w0 mem0 : w16 mem0
00111000101xxxxx010100xxxxxxxxxx ldsminab w0 mem0 : w16 mem0
00111000101xxxxx011000xxxxxxxxxx ldumaxab w0 mem0 : w16 mem0
00111000101xxxxx011100xxxxxxxxxx lduminab w0 mem0 : w16 mem0
00111000111xxxxx000000xxxxxxxxxx ldaddalb w0 mem0 : w16 mem0
00111000111xxxxx000100xxxxxxxxxx ldclralb w0 mem0 : w16 mem0
00111000111xxxxx001000xxxxxxxxxx ldeoralb w0 mem0 : w16 mem0
00111000111xxxxx001100xxxxxxxxxx ldsetalb w0 mem0 : w16 mem0
00111000111xxxxx010000xxxxxxxxxx ldsmaxalb w0 mem0 : w16 mem0
00111000111xxxxx010100xxxxxxxxxx ldsminalb w0 mem0 : w16 mem0
00111000111xxxxx011000xxxxxxxxxx ldumaxalb w0 mem0 : w16 mem0
00111000111xxxxx011100xxxxxxxxxx lduminalb w0 mem0 : w16 mem0
01111000001xxxxx000000xxxxxxxxxx ldaddh w0 mem0 : w16 mem0
01111000001xxxxx000100xxxxxxxxxx ldclrh w0 mem0 : w16 mem0
01111000001xxxxx001000xxxxxxxxxx ldeorh w0 mem0 : w16 mem0
01111000001xxxxx001100xxxxxxxxxx ldseth w0 mem0 : w16 mem0
01111000001xxxxx010000xxxxxxxxxx ldsmaxh w0 mem0 : w16 mem0
01111000001xxxxx010100xxxxxxxxxx ldsminh w0 mem0 : w16 mem0
01111000001xxxxx011000xxxxxxxxxx ldumaxh w0 mem0 : w16 mem0
01111000001xxxxx011100xxxxxxxxxx lduminh w0 mem0 : w16 mem0
01111000011xxxxx000000xxxxxxxxxx ldaddlh w0 mem0 : w16 mem0
01111000011xxxxx000100xxxxxxxxxx ldclrlh w0 mem0 : w16 mem0
01111000011xxxxx001000xxxxxxxxxx ldeorlh w0 mem0 : w16 mem0
01111000011xxxxx001100xxxxxxxxxx ldsetlh w0 mem0 : w16 mem0
01111000011xxxxx010000xxxxxxxxxx ldsmaxlh w0 mem0 : w16 mem0
01111000011xxxxx010100xxxxxxxxxx ldsminlh w0 mem0 : w16 mem0
01111000011xxxxx011000xxxxxxxxxx ldumaxlh w0 mem0 : w16 mem0
01111000011xxxxx011100xxxxxxxxxx lduminlh w0 mem0 : w16 mem0
01111000101xxxxx000000xxxxxxxxxx ldaddah w0 mem0 : w16 mem0
01111000101xxxxx000100xxxxxxxxxx ldclrah w0 mem0 : w16 mem0
01111000101xxxxx001000xxxxxxxxxx ldeorah w0 mem0 : w16 mem0
01111000101xxxxx001100xxxxxxxxxx ldsetah w0 mem0 : w16 mem0
01111000101xxxxx010000xxxxxxxxxx ldsmaxah w0 mem0 : w16 mem0
01111000101xxxxx010100xxxxxxxxxx ldsminah w0 mem0 : w16 mem0
01111000101xxxxx011000xxxxxxxxxx ldumaxah w0 mem0 : w16 mem0
01111000101xxxxx011100xxxxxxxxxx lduminah w0 mem0 : w16 mem0
01111000111xxxxx000000xxxxxxxxxx ldaddalh w0 mem0 : w16 mem0
01111000111xxxxx000100xxxxxxxxxx ldclralh w0 mem0 : w16 mem0
01111000111xxxxx001000xxxxxxxxxx ldeoralh w0 mem0 : w16 mem0
01111000111xxxxx001100xxxxxxxxxx ldsetalh w0 mem0 : w16 mem0
01111000111xxxxx010000xxxxxxxxxx ldsmaxalh w0 mem0 : w16 mem0
01111000111xxxxx010100xxxxxxxxxx ldsminalh w0 mem0 : w16 mem0
01111000111xxxxx011000xxxxxxxxxx ldumaxalh w0 mem0 : w16 mem0
01111000111xxxxx011100xxxxxxxxxx lduminalh w0 mem0 : w16 mem0
10111000001xxxxx000000xxxxxxxxxx ldadd w0 mem0 : w16 mem0
10111000001xxxxx000100xxxxxxxxxx ldclr w0 mem0 : w16 mem0
10111000001xxxxx001000xxxxxxxxxx ldeor w0 mem0 : w16 mem0
10111000001xxxxx001100xxxxxxxxxx ldset w0 mem0 : w16 mem0
10111000001xxxxx010000xxxxxxxxxx ldsmax w0 mem0 : w16 mem0
10111000001xxxxx010100xxxxxxxxxx ldsmin w0 mem0 : w16 mem0
10111000001xxxxx011000xxxxxxxxxx ldumax w0 mem0 : w16 mem0
10111000001xxxxx011100xxxxxxxxxx ldumin w0 mem0 : w16 mem0
10111000011xxxxx000000xxxxxxxxxx ldaddl w0 mem0 : w16 mem0
10111000011xxxxx000100xxxxxxxxxx ldclrl w0 mem0 : w16 mem0
10111000011xxxxx001000xxxxxxxxxx ldeorl w0 mem0 : w16 mem0
10111000011xxxxx001100xxxxxxxxxx ldsetl w0 mem0 : w16 mem0
10111000011xxxxx010000xxxxxxxxxx ldsmaxl w0 mem0 : w16 mem0
10111000011xxxxx010100xxxxxxxxxx ldsminl w0 mem0 : w16 mem0
10111000011xxxxx011000xxxxxxxxxx ldumaxl w0 mem0 : w16 mem0
10111000011xxxxx011100xxxxxxxxxx lduminl w0 mem0 : w16 mem0
10111000101xxxxx000000xxxxxxxxxx ldadda w0 mem0 : w16 mem0
10111000101xxxxx000100xxxxxxxxxx ldclra w0 mem0 : w16 mem0
10111000101xxxxx001000xxxxxxxxxx ldeora w0 mem0 : w16 mem0
10111000101xxxxx001100xxxxxxxxxx ldseta w0 mem0 : w16 mem0
10111000101xxxxx010000xxxxxxxxxx ldsmaxa w0 mem0 : w16 mem0
10111000101xxxxx010100xxxxxxxxxx ldsmina w0 mem0 : w16 mem0
10111000101xxxxx011000xxxxxxxxxx ldumaxa w0 mem0 : w16 mem0
10111000101xxxxx011100xxxxxxxxxx ldumina w0 mem0 : w16 mem0
10111000111xxxxx000000xxxxxxxxxx ldaddal w0 mem0 : w16 mem0
10111000111xxxxx000100xxxxxxxxxx ldclral w0 mem0 : w16 mem0
10111000111xxxxx001000xxxxxxxxxx ldeoral w0 mem0 : w16 mem0
10111000111xxxxx001100xxxxxxxxxx ldsetal w0 mem0 : w16 mem0
10111000111xxxxx010000xxxxxxxxxx ldsmaxal w0 mem0 : w16 mem0
10111000111xxxxx010100xxxxxxxxxx ldsminal w0 mem0 : w16 mem0
10111000111xxxxx011000xxxxxxxxxx ldumaxal w0 mem0 : w16 mem0
10111000111xxxxx011100xxxxxxxxxx lduminal w0 mem0 : w16 mem0
11111000001xxxxx000000xxxxxxxxxx ldadd x0 mem0 : x16 mem0
11111000001xxxxx000100xxxxxxxxxx ldclr x0 mem0 : x16 mem0
11111000001xxxxx001000xxxxxxxxxx ldeor x0 mem0 : x16 mem0
11111000001xxxxx001100xxxxxxxxxx ldset x0 mem0 : x16 mem0
11111000001xxxxx010000xxxxxxxxxx ldsmax x0 mem0 : x16 mem0
11111000001xxxxx010100xxxxxxxxxx ldsmin x0 mem0 : x16 mem0
11111000001xxxxx011000xxxxxxxxxx ldumax x0 mem0 : x16 mem0
11111000001xxxxx011100xxxxxxxxxx ldumin x0 mem0 : x16 mem0
11111000011xxxxx000000xxxxxxxxxx ldaddl x0 mem0 : x16 mem0
11111000011xxxxx000100xxxxxxxxxx ldclrl x0 mem0 : x16 mem0
11111000011xxxxx001000xxxxxxxxxx ldeorl x0 mem0 : x16 mem0
11111000011xxxxx001100xxxxxxxxxx ldsetl x0 mem0 : x16 mem0
11111000011xxxxx010000xxxxxxxxxx ldsmaxl x0 mem0 : x16 mem0
11111000011xxxxx010100xxxxxxxxxx ldsminl x0 mem0 : x16 mem0
11111000011xxxxx011000xxxxxxxxxx ldumaxl x0 mem0 : x16 mem0
11111000011xxxxx011100xxxxxxxxxx lduminl x0 mem0 : x16 mem0
11111000101xxxxx000000xxxxxxxxxx ldadda x0 mem0 : x16 mem0
11111000101xxxxx000100xxxxxxxxxx ldclra x0 mem0 : x16 mem0
11111000101xxxxx001000xxxxxxxxxx ldeora x0 mem0 : x16 mem0
11111000101xxxxx001100xxxxxxxxxx ldseta x0 mem0 : x16 mem0
11111000101xxxxx010000xxxxxxxxxx ldsmaxa x0 mem0 : x16 mem0
11111000101xxxxx010100xxxxxxxxxx ldsmina x0 mem0 : x16 mem0
11111000101xxxxx011000xxxxxxxxxx ldumaxa x0 mem0 : x16 mem0
11111000101xxxxx011100xxxxxxxxxx ldumina x0 mem0 : x16 mem0
11111000111xxxxx000000xxxxxxxxxx ldaddal x0 mem0 : x16 mem0
11111000111xxxxx000100xxxxxxxxxx ldclral x0 mem0 : x16 mem0
11111000111xxxxx001000xxxxxxxxxx ldeoral x0 mem0 : x16 mem0
11111000111xxxxx001100xxxxxxxxxx ldsetal x0 mem0 : x16 mem0
11111000111xxxxx010000xxxxxxxxxx ldsmaxal x0 mem0 : x16 mem0
11111000111xxxxx010100xxxxxxxxxx ldsminal x0 mem0 : x16 mem0
11111000111xxxxx011000xxxxxxxxxx ldumaxal x0 mem0 : x16 mem0
11111000111xxxxx011100xxxxxxxxxx lduminal x0 mem0 : x16 mem0
00111000001xxxxx100000xxxxxxxxxx swpb w0 mem0 : w16 mem0
00111000011xxxxx100000xxxxxxxxxx swplb w0 mem0 : w16 mem0
00111000101xxxxx100000xxxxxxxxxx swpab w0 mem0 : w16 mem0
00111000111xxxxx100000xxxxxxxxxx swpalb w0 mem0 : w16 mem0
01111000001xxxxx100000xxxxxxxxxx swph w0 mem0 : w16 mem0
01111000011xxxxx100000xxxxxxxxxx swplh w0 mem0 : w16 mem0
01111000101xxxxx100000xxxxxxxxxx swpah w0 mem0 : w16 mem0
01111000111xxxxx100000xxxxxxxxxx swpalh w0 mem0 : w16 mem0
10111000001xxxxx100000xxxxxxxxxx swp w0 mem0 : w16 mem0
10111000011xxxxx100000xxxxxxxxxx swpl w0 mem0 : w16 mem0
10111000101xxxxx100000xxxxxxxxxx swpa w0 mem0 : w16 mem0
10111000111xxxxx100000xxxxxxxxxx swpal w0 mem0 : w16 mem0
11111000001xxxxx100000xxxxxxxxxx swp x0 mem0 : x16 mem0
11111000011xxxxx100000xxxxxxxxxx swpl x0 mem0 : x16 mem0
11111000101xxxxx100000xxxxxxxxxx swpa x0 mem0 : x16 mem0
11111000111xxxxx100000xxxxxxxxxx swpal x0 mem0 : x16 mem0
## Load/store register (register offset)
00111000001xxxxxxxxx10xxxxxxxxxx strb memreg : w0
00111000011xxxxxxxxx10xxxxxxxxxx ldrb w0 : memreg
00111000101xxxxxxxxx10xxxxxxxxxx ldrsb x0 : memreg
00111000111xxxxxxxxx10xxxxxxxxxx ldrsb w0 : memreg
00111100001xxxxxxxxx10xxxxxxxxxx str memreg : b0
00111100011xxxxxxxxx10xxxxxxxxxx ldr b0 : memreg
00111100101xxxxxxxxx10xxxxxxxxxx str memregq : b0
00111100111xxxxxxxxx10xxxxxxxxxx ldr q0 : memregq
01111000001xxxxxxxxx10xxxxxxxxxx strh memreg : w0
01111000011xxxxxxxxx10xxxxxxxxxx ldrh w0 : memreg
01111000101xxxxxxxxx10xxxxxxxxxx ldrsh x0 : memreg
01111000111xxxxxxxxx10xxxxxxxxxx ldrsh w0 : memreg
01111100001xxxxxxxxx10xxxxxxxxxx str memreg : h0
01111100011xxxxxxxxx10xxxxxxxxxx ldr h0 : memreg
10111000001xxxxxxxxx10xxxxxxxxxx str memreg : w0
10111000011xxxxxxxxx10xxxxxxxxxx ldr w0 : memreg
10111000101xxxxxxxxx10xxxxxxxxxx ldrsw x0 : memreg
10111100001xxxxxxxxx10xxxxxxxxxx str memreg : s0
10111100011xxxxxxxxx10xxxxxxxxxx ldr s0 : memreg
11111000001xxxxxxxxx10xxxxxxxxxx str memreg : x0
11111000011xxxxxxxxx10xxxxxxxxxx ldr x0 : memreg
11111000101xxxxxxxxx10xxxxxxxxxx prfm : prfop prfreg
11111100001xxxxxxxxx10xxxxxxxxxx str memreg : d0
11111100011xxxxxxxxx10xxxxxxxxxx ldr d0 : memreg
## Load/store register (unsigned immediate)
0011100100xxxxxxxxxxxxxxxxxxxxxx strb mem12 : w0 # STRB Wt,[Xn,#simm]
0011100101xxxxxxxxxxxxxxxxxxxxxx ldrb w0 : mem12
0011100110xxxxxxxxxxxxxxxxxxxxxx ldrsb x0 : mem12
0011100111xxxxxxxxxxxxxxxxxxxxxx ldrsb w0 : mem12
0011110100xxxxxxxxxxxxxxxxxxxxxx str mem12 : b0
0011110101xxxxxxxxxxxxxxxxxxxxxx ldr b0 : mem12
0011110110xxxxxxxxxxxxxxxxxxxxxx str mem12q : q0
0011110111xxxxxxxxxxxxxxxxxxxxxx ldr q0 : mem12q
0111100100xxxxxxxxxxxxxxxxxxxxxx strh mem12 : w0
0111100101xxxxxxxxxxxxxxxxxxxxxx ldrh w0 : mem12
0111100110xxxxxxxxxxxxxxxxxxxxxx ldrsh x0 : mem12
0111100111xxxxxxxxxxxxxxxxxxxxxx ldrsh w0 : mem12
0111110100xxxxxxxxxxxxxxxxxxxxxx str mem12 : h0
0111110101xxxxxxxxxxxxxxxxxxxxxx ldr h0 : mem12
1011100100xxxxxxxxxxxxxxxxxxxxxx str mem12 : w0
1011100101xxxxxxxxxxxxxxxxxxxxxx ldr w0 : mem12
1011100110xxxxxxxxxxxxxxxxxxxxxx ldrsw x0 : mem12
1011110100xxxxxxxxxxxxxxxxxxxxxx str mem12 : s0
1011110101xxxxxxxxxxxxxxxxxxxxxx ldr s0 : mem12
1111100100xxxxxxxxxxxxxxxxxxxxxx str mem12 : x0
1111100101xxxxxxxxxxxxxxxxxxxxxx ldr x0 : mem12
1111100110xxxxxxxxxxxxxxxxxxxxxx prfm : prfop prf12 # PRFM #imm5,[Xn,#simm]
1111110100xxxxxxxxxxxxxxxxxxxxxx str mem12 : d0
1111110101xxxxxxxxxxxxxxxxxxxxxx ldr d0 : mem12
## Advanced SIMD load/store multiple structures
0x001100000000000000xxxxxxxxxxxx st4 memvm : vmsz vt0 vt1 vt2 vt3
0x001100000000000010xxxxxxxxxxxx st1 memvm : vmsz vt0 vt1 vt2 vt3
0x001100000000000100xxxxxxxxxxxx st3 memvm : vmsz vt0 vt1 vt2
0x001100000000000110xxxxxxxxxxxx st1 memvm : vmsz vt0 vt1 vt2
0x001100000000000111xxxxxxxxxxxx st1 memvm : vt0 vmsz
0x001100000000001000xxxxxxxxxxxx st2 memvm : vmsz vt0 vt1
0x001100000000001010xxxxxxxxxxxx st1 memvm : vmsz vt0 vt1
0x001100010000000000xxxxxxxxxxxx ld4 vt0 vt1 vt2 vt3 : memvm vmsz
0x001100010000000010xxxxxxxxxxxx ld1 vt0 vt1 vt2 vt3 : memvm vmsz
0x001100010000000100xxxxxxxxxxxx ld3 vt0 vt1 vt2 : memvm vmsz
0x001100010000000110xxxxxxxxxxxx ld1 vt0 vt1 vt2 : memvm vmsz
0x001100010000000111xxxxxxxxxxxx ld1 vt0 : memvm vmsz
0x001100010000001000xxxxxxxxxxxx ld2 vt0 vt1 : memvm vmsz
0x001100010000001010xxxxxxxxxxxx ld1 vt0 vt1 : memvm vmsz
## Advanced SIMD load/store multiple structures (post-indexed)
0x001100100xxxxx0000xxxxxxxxxxxx st4 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
0x001100100xxxxx0010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
0x001100100xxxxx0100xxxxxxxxxxxx st3 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
0x001100100xxxxx0110xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
0x001100100xxxxx0111xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 x5sp x16imm
0x001100100xxxxx1000xxxxxxxxxxxx st2 memvm x5sp : vmsz vt0 vt1 x5sp x16imm
0x001100100xxxxx1010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 x5sp x16imm
0x001100110xxxxx0000xxxxxxxxxxxx ld4 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0010xxxxxxxxxxxx ld1 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0100xxxxxxxxxxxx ld3 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0110xxxxxxxxxxxx ld1 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0111xxxxxxxxxxxx ld1 vt0 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx1000xxxxxxxxxxxx ld2 vt0 vt1 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx1010xxxxxxxxxxxx ld1 vt0 vt1 x5sp : memvm vmsz x5sp x16imm
## Advanced SIMD load/store single structure
0x00110100000000000xxxxxxxxxxxxx st1 memvs : q0 index0
0x00110100000000001xxxxxxxxxxxxx st3 memvs : q0 q0p1 q0p2 index0
0x00110100000000010xx0xxxxxxxxxx st1 memvs : q0 index1
0x00110100000000011xx0xxxxxxxxxx st3 memvs : q0 q0p1 q0p2 index1
0x00110100000000100x00xxxxxxxxxx st1 memvs : q0 index2
0x00110100000000100001xxxxxxxxxx st1 memvs : q0 index3
0x00110100000000101x00xxxxxxxxxx st3 memvs : q0 q0p1 q0p2 index2
0x00110100000000101001xxxxxxxxxx st3 memvs : q0 q0p1 q0p2 index3
0x00110100100000000xxxxxxxxxxxxx st2 memvs : q0 q0p1 index0
0x00110100100000001xxxxxxxxxxxxx st4 memvs : q0 q0p1 q0p2 q0p3 index0
0x00110100100000010xx0xxxxxxxxxx st2 memvs : q0 q0p1 index1
0x00110100100000011xx0xxxxxxxxxx st4 memvs : q0 q0p1 q0p2 q0p3 index1
0x00110100100000100x00xxxxxxxxxx st2 memvs : q0 q0p1 index2
0x00110100100000100001xxxxxxxxxx st2 memvs : q0 q0p1 index3
0x00110100100000101x00xxxxxxxxxx st4 memvs : q0 q0p1 q0p2 q0p3 index2
0x00110100100000101001xxxxxxxxxx st4 memvs : q0 q0p1 q0p2 q0p3 index3
0x00110101000000000xxxxxxxxxxxxx ld1 q0 : memvs index0
0x00110101000000001xxxxxxxxxxxxx ld3 q0 q0p1 q0p2 : memvs index0
0x00110101000000010xx0xxxxxxxxxx ld1 q0 : memvs index1
0x00110101000000011xx0xxxxxxxxxx ld3 q0 q0p1 q0p2 : memvs index1
0x00110101000000100x00xxxxxxxxxx ld1 q0 : memvs index2
0x00110101000000100001xxxxxxxxxx ld1 q0 : memvs index3
0x00110101000000101x00xxxxxxxxxx ld3 q0 q0p1 q0p2 : memvs index2
0x00110101000000101001xxxxxxxxxx ld3 q0 q0p1 q0p2 : memvs index3
0x001101010000001100xxxxxxxxxxxx ld1r dq0 : memvr
0x001101010000001110xxxxxxxxxxxx ld3r dq0 dq0p1 dq0p2 : memvr
0x00110101100000000xxxxxxxxxxxxx ld2 q0 q0p1 : memvs index0
0x00110101100000001xxxxxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 : memvs index0
0x00110101100000010xx0xxxxxxxxxx ld2 q0 q0p1 : memvs index1
0x00110101100000011xx0xxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 : memvs index1
0x00110101100000100x00xxxxxxxxxx ld2 q0 q0p1 : memvs index2
0x00110101100000100001xxxxxxxxxx ld2 q0 q0p1 : memvs index3
0x00110101100000101x00xxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 : memvs index2
0x00110101100000101001xxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 : memvs index3
0x001101011000001100xxxxxxxxxxxx ld2r dq0 dq0p1 : memvr
0x001101011000001110xxxxxxxxxxxx ld4r dq0 dq0p1 dq0p2 dq0p3 : memvr
## Advanced SIMD load/store single structure (post-indexed)
0x001101100xxxxx000xxxxxxxxxxxxx st1 memvs x5sp : q0 index0 x5sp x16immvs
0x001101100xxxxx001xxxxxxxxxxxxx st3 memvs x5sp : q0 q0p1 q0p2 index0 x5sp x16immvs
0x001101100xxxxx010xx0xxxxxxxxxx st1 memvs x5sp : q0 index1 x5sp x16immvs
0x001101100xxxxx011xx0xxxxxxxxxx st3 memvs x5sp : q0 q0p1 q0p2 index1 x5sp x16immvs
0x001101100xxxxx100x00xxxxxxxxxx st1 memvs x5sp : q0 index2 x5sp x16immvs
0x001101100xxxxx100001xxxxxxxxxx st1 memvs x5sp : q0 index3 x5sp x16immvs
0x001101100xxxxx101x00xxxxxxxxxx st3 memvs x5sp : q0 q0p1 q0p2 index2 x5sp x16immvs
0x001101100xxxxx101001xxxxxxxxxx st3 memvs x5sp : q0 q0p1 q0p2 index3 x5sp x16immvs
0x001101101xxxxx000xxxxxxxxxxxxx st2 memvs x5sp : q0 q0p1 index0 x5sp x16immvs
0x001101101xxxxx001xxxxxxxxxxxxx st4 memvs x5sp : q0 q0p1 q0p2 q0p3 index0 x5sp x16immvs
0x001101101xxxxx010xx0xxxxxxxxxx st2 memvs x5sp : q0 q0p1 index1 x5sp x16immvs
0x001101101xxxxx011xx0xxxxxxxxxx st4 memvs x5sp : q0 q0p1 q0p2 q0p3 index1 x5sp x16immvs
0x001101101xxxxx100x00xxxxxxxxxx st2 memvs x5sp : q0 q0p1 index2 x5sp x16immvs
0x001101101xxxxx100001xxxxxxxxxx st2 memvs x5sp : q0 q0p1 index3 x5sp x16immvs
0x001101101xxxxx101x00xxxxxxxxxx st4 memvs x5sp : q0 q0p1 q0p2 q0p3 index2 x5sp x16immvs
0x001101101xxxxx101001xxxxxxxxxx st4 memvs x5sp : q0 q0p1 q0p2 q0p3 index3 x5sp x16immvs
0x001101110xxxxx000xxxxxxxxxxxxx ld1 q0 x5sp : q0 memvs index0 x5sp x16immvs
0x001101110xxxxx001xxxxxxxxxxxxx ld3 q0 q0p1 q0p2 x5sp : q0 q0p1 q0p2 memvs index0 x5sp x16immvs
0x001101110xxxxx010xx0xxxxxxxxxx ld1 q0 x5sp : q0 memvs index1 x5sp x16immvs
0x001101110xxxxx011xx0xxxxxxxxxx ld3 q0 q0p1 q0p2 x5sp : q0 q0p1 q0p2 memvs index1 x5sp x16immvs
0x001101110xxxxx100x00xxxxxxxxxx ld1 q0 x5sp : q0 memvs index2 x5sp x16immvs
0x001101110xxxxx100001xxxxxxxxxx ld1 q0 x5sp : q0 memvs index3 x5sp x16immvs
0x001101110xxxxx101x00xxxxxxxxxx ld3 q0 q0p1 q0p2 x5sp : q0 q0p1 q0p2 memvs index2 x5sp x16immvs
0x001101110xxxxx101001xxxxxxxxxx ld3 q0 q0p1 q0p2 x5sp : q0 q0p1 q0p2 memvs index3 x5sp x16immvs
0x001101110xxxxx1100xxxxxxxxxxxx ld1r dq0 x5sp : memvr x5sp x16immvr
0x001101110xxxxx1110xxxxxxxxxxxx ld3r dq0 dq0p1 dq0p2 x5sp : memvr x5sp x16immvr
0x001101111xxxxx000xxxxxxxxxxxxx ld2 q0 q0p1 x5sp : q0 q0p1 memvs index0 x5sp x16immvs
0x001101111xxxxx001xxxxxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 x5sp : q0 q0p1 q0p2 q0p3 memvs index0 x5sp x16immvs
0x001101111xxxxx010xx0xxxxxxxxxx ld2 q0 q0p1 x5sp : q0 q0p1 memvs index1 x5sp x16immvs
0x001101111xxxxx011xx0xxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 x5sp : q0 q0p1 q0p2 q0p3 memvs index1 x5sp x16immvs
0x001101111xxxxx100x00xxxxxxxxxx ld2 q0 q0p1 x5sp : q0 q0p1 memvs index2 x5sp x16immvs
0x001101111xxxxx100001xxxxxxxxxx ld2 q0 q0p1 x5sp : q0 q0p1 memvs index3 x5sp x16immvs
0x001101111xxxxx101x00xxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 x5sp : q0 q0p1 q0p2 q0p3 memvs index2 x5sp x16immvs
0x001101111xxxxx101001xxxxxxxxxx ld4 q0 q0p1 q0p2 q0p3 x5sp : q0 q0p1 q0p2 q0p3 memvs index3 x5sp x16immvs
0x001101111xxxxx1100xxxxxxxxxxxx ld2r dq0 dq0p1 x5sp : memvr x5sp x16immvr
0x001101111xxxxx1110xxxxxxxxxxxx ld4r dq0 dq0p1 dq0p2 dq0p3 x5sp : memvr x5sp x16immvr
# Data Processing - Register
## Logical (shifted register)
x0001010xx0xxxxxxxxxxxxxxxxxxxxx and wx0 : wx5 wx16 shift4 imm6
x0001010xx1xxxxxxxxxxxxxxxxxxxxx bic wx0 : wx5 wx16 shift4 imm6
x0101010xx0xxxxxxxxxxxxxxxxxxxxx orr wx0 : wx5 wx16 shift4 imm6
x0101010xx1xxxxxxxxxxxxxxxxxxxxx orn wx0 : wx5 wx16 shift4 imm6
x1001010xx0xxxxxxxxxxxxxxxxxxxxx eor wx0 : wx5 wx16 shift4 imm6
x1001010xx1xxxxxxxxxxxxxxxxxxxxx eon wx0 : wx5 wx16 shift4 imm6
x1101010xx0xxxxxxxxxxxxxxxxxxxxx ands wx0 : wx5 wx16 shift4 imm6
x1101010xx1xxxxxxxxxxxxxxxxxxxxx bics wx0 : wx5 wx16 shift4 imm6
## Add/subtract (shifted register)
x0001011xx0xxxxxxxxxxxxxxxxxxxxx add wx0 : wx5 wx16 shift3 imm6
x0101011xx0xxxxxxxxxxxxxxxxxxxxx adds wx0 : wx5 wx16 shift3 imm6
x1001011xx0xxxxxxxxxxxxxxxxxxxxx sub wx0 : wx5 wx16 shift3 imm6
x1101011xx0xxxxxxxxxxxxxxxxxxxxx subs wx0 : wx5 wx16 shift3 imm6
## Add/subtract (extended register)
x0001011001xxxxxxxxxxxxxxxxxxxxx add wx0sp : wx5sp wx16 ext extam
x0101011001xxxxxxxxxxxxxxxxxxxxx adds wx0 : wx5sp wx16 ext extam
x1001011001xxxxxxxxxxxxxxxxxxxxx sub wx0sp : wx5sp wx16 ext extam
x1101011001xxxxxxxxxxxxxxxxxxxxx subs wx0 : wx5sp wx16 ext extam
## Add/subtract (with carry)
x0011010000xxxxx000000xxxxxxxxxx adc wx0 : wx5 wx16
x0111010000xxxxx000000xxxxxxxxxx adcs wx0 : wx5 wx16
x1011010000xxxxx000000xxxxxxxxxx sbc wx0 : wx5 wx16
x1111010000xxxxx000000xxxxxxxxxx sbcs wx0 : wx5 wx16
## Conditional compare (register)
x0111010010xxxxxxxxx00xxxxx0xxxx ccmn : wx5 wx16 nzcv cond
x1111010010xxxxxxxxx00xxxxx0xxxx ccmp : wx5 wx16 nzcv cond
## Conditional compare (immediate)
x0111010010xxxxxxxxx10xxxxx0xxxx ccmn : wx5 imm5 nzcv cond
x1111010010xxxxxxxxx10xxxxx0xxxx ccmp : wx5 imm5 nzcv cond
## Conditional select
x0011010100xxxxxxxxx00xxxxxxxxxx csel wx0 : wx5 wx16 cond
x0011010100xxxxxxxxx01xxxxxxxxxx csinc wx0 : wx5 wx16 cond
x1011010100xxxxxxxxx00xxxxxxxxxx csinv wx0 : wx5 wx16 cond
x1011010100xxxxxxxxx01xxxxxxxxxx csneg wx0 : wx5 wx16 cond
# Data-processing (3 source)
x0011011000xxxxx0xxxxxxxxxxxxxxx madd wx0 : wx5 wx16 wx10
x0011011000xxxxx1xxxxxxxxxxxxxxx msub wx0 : wx5 wx16 wx10
10011011001xxxxx0xxxxxxxxxxxxxxx smaddl x0 : w5 w16 x10
10011011001xxxxx1xxxxxxxxxxxxxxx smsubl x0 : w5 w16 x10
10011011010xxxxx0xxxxxxxxxxxxxxx smulh x0 : x5 x16 ign10
10011011101xxxxx0xxxxxxxxxxxxxxx umaddl x0 : w5 w16 x10
10011011101xxxxx1xxxxxxxxxxxxxxx umsubl x0 : w5 w16 x10
10011011110xxxxx0xxxxxxxxxxxxxxx umulh x0 : x5 x16 ign10
# Data-processing (2 source)
x0011010110xxxxx000010xxxxxxxxxx udiv wx0 : wx5 wx16
x0011010110xxxxx000011xxxxxxxxxx sdiv wx0 : wx5 wx16
x0011010110xxxxx001000xxxxxxxxxx lslv wx0 : wx5 wx16
x0011010110xxxxx001001xxxxxxxxxx lsrv wx0 : wx5 wx16
x0011010110xxxxx001010xxxxxxxxxx asrv wx0 : wx5 wx16
x0011010110xxxxx001011xxxxxxxxxx rorv wx0 : wx5 wx16
00011010110xxxxx010000xxxxxxxxxx crc32b w0 : w5 w16
00011010110xxxxx010001xxxxxxxxxx crc32h w0 : w5 w16
00011010110xxxxx010010xxxxxxxxxx crc32w w0 : w5 w16
00011010110xxxxx010100xxxxxxxxxx crc32cb w0 : w5 w16
00011010110xxxxx010101xxxxxxxxxx crc32ch w0 : w5 w16
00011010110xxxxx010110xxxxxxxxxx crc32cw w0 : w5 w16
10011010110xxxxx010011xxxxxxxxxx crc32x w0 : w5 x16
10011010110xxxxx010111xxxxxxxxxx crc32cx w0 : w5 x16
# Data-processing (1 source)
x101101011000000000000xxxxxxxxxx rbit wx0 : wx5
x101101011000000000001xxxxxxxxxx rev16 wx0 : wx5
0101101011000000000010xxxxxxxxxx rev w0 : w5
x101101011000000000100xxxxxxxxxx clz wx0 : wx5
x101101011000000000101xxxxxxxxxx cls wx0 : wx5
1101101011000000000010xxxxxxxxxx rev32 x0 : x5
1101101011000000000011xxxxxxxxxx rev x0 : x5
# Data Processing - Scalar Floating-Point and Advanced SIMD
# FMOV (general) GPR to FP reg
0001111011100111000000xxxxxxxxxx fmov h0 : w5 # Armv8.2
0001111000100111000000xxxxxxxxxx fmov s0 : w5
1001111011100111000000xxxxxxxxxx fmov h0 : x5 # Armv8.2
1001111001100111000000xxxxxxxxxx fmov d0 : x5
1001111010101111000000xxxxxxxxxx fmov q0 : x5 # only sets the bit top half of q0
# Advanced SIMD three same (FP16)
0x001110010xxxxx000001xxxxxxxxxx fmaxnm dq0 : dq5 dq16 h_sz
0x001110010xxxxx000011xxxxxxxxxx fmla dq0 : dq0 dq5 dq16 h_sz
0x001110010xxxxx000101xxxxxxxxxx fadd dq0 : dq5 dq16 h_sz
0x001110010xxxxx000111xxxxxxxxxx fmulx dq0 : dq5 dq16 h_sz
0x001110010xxxxx001001xxxxxxxxxx fcmeq dq0 : dq5 dq16 h_sz
0x001110010xxxxx001101xxxxxxxxxx fmax dq0 : dq5 dq16 h_sz
0x001110010xxxxx001111xxxxxxxxxx frecps dq0 : dq5 dq16 h_sz
0x001110110xxxxx000001xxxxxxxxxx fminnm dq0 : dq5 dq16 h_sz
0x001110110xxxxx000011xxxxxxxxxx fmls dq0 : dq0 dq5 dq16 h_sz
0x001110110xxxxx000101xxxxxxxxxx fsub dq0 : dq5 dq16 h_sz
0x001110110xxxxx001101xxxxxxxxxx fmin dq0 : dq5 dq16 h_sz
0x001110110xxxxx001111xxxxxxxxxx frsqrts dq0 : dq5 dq16 h_sz
0x101110010xxxxx000001xxxxxxxxxx fmaxnmp dq0 : dq5 dq16 h_sz
0x101110010xxxxx000101xxxxxxxxxx faddp dq0 : dq5 dq16 h_sz
0x101110010xxxxx000111xxxxxxxxxx fmul dq0 : dq5 dq16 h_sz
0x101110010xxxxx001001xxxxxxxxxx fcmge dq0 : dq5 dq16 h_sz