instr_get_opcode(ins) doesn't support NEON and VFP instructions

[yuhao]

Instructions like fmul (vector version) or vmla.f32 are not supported. Is there a plan?

[egrimley]

FMUL is AArch64 and currently not handled by the decoder. Of the AArch64 instructions that operate on FP/SIMD registers only load/store instructions are decoded, though it should still be possible to execute any instruction. I don't seem to be able to find a specific issue for completing the AArch64 decoder, though there are related issues, such as #2440 and #2443, and there's #1569, of course.

VMLA.F32 is AArch32 and should work, I think.

If "fmul" is a typo for "vmul", please label this issue with OpSys-ARM and explain what doesn't work.

[derekbruening]

Right, please clarify which architecture you are looking at. All Advanced SIMD and floating point instructions for AArch32 in ARMv8, including vmla.f32, are supported in DR's IR.

[yuhao]

I meant FMUL in AArch64. I suppose this is not a bug, but I was curious if the support for AArch64 will be extended to non load/store instructions?

[egrimley]

I've created #2626; I hope it's not a duplicate. I'll close this one for now. It can be reopened if there is a problem with vmla.f32.