AP9.sta.rpt

TimeQuest Timing Analyzer report for AP9
Tue Nov  8 13:34:45 2016
Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1100mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1100mV 85C Model Setup Summary
  8. Slow 1100mV 85C Model Hold Summary
  9. Slow 1100mV 85C Model Recovery Summary
 10. Slow 1100mV 85C Model Removal Summary
 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
 12. Setup Times
 13. Hold Times
 14. Clock to Output Times
 15. Minimum Clock to Output Times
 16. Slow 1100mV 85C Model Metastability Report
 17. Slow 1100mV 0C Model Fmax Summary
 18. Slow 1100mV 0C Model Setup Summary
 19. Slow 1100mV 0C Model Hold Summary
 20. Slow 1100mV 0C Model Recovery Summary
 21. Slow 1100mV 0C Model Removal Summary
 22. Slow 1100mV 0C Model Minimum Pulse Width Summary
 23. Setup Times
 24. Hold Times
 25. Clock to Output Times
 26. Minimum Clock to Output Times
 27. Slow 1100mV 0C Model Metastability Report
 28. Fast 1100mV 85C Model Setup Summary
 29. Fast 1100mV 85C Model Hold Summary
 30. Fast 1100mV 85C Model Recovery Summary
 31. Fast 1100mV 85C Model Removal Summary
 32. Fast 1100mV 85C Model Minimum Pulse Width Summary
 33. Setup Times
 34. Hold Times
 35. Clock to Output Times
 36. Minimum Clock to Output Times
 37. Fast 1100mV 85C Model Metastability Report
 38. Fast 1100mV 0C Model Setup Summary
 39. Fast 1100mV 0C Model Hold Summary
 40. Fast 1100mV 0C Model Recovery Summary
 41. Fast 1100mV 0C Model Removal Summary
 42. Fast 1100mV 0C Model Minimum Pulse Width Summary
 43. Setup Times
 44. Hold Times
 45. Clock to Output Times
 46. Minimum Clock to Output Times
 47. Fast 1100mV 0C Model Metastability Report
 48. Multicorner Timing Analysis Summary
 49. Setup Times
 50. Hold Times
 51. Clock to Output Times
 52. Minimum Clock to Output Times
 53. Board Trace Model Assignments
 54. Input Transition Times
 55. Signal Integrity Metrics (Slow 1100mv 0c Model)
 56. Signal Integrity Metrics (Slow 1100mv 85c Model)
 57. Signal Integrity Metrics (Fast 1100mv 0c Model)
 58. Signal Integrity Metrics (Fast 1100mv 85c Model)
 59. Setup Transfers
 60. Hold Transfers
 61. Recovery Transfers
 62. Removal Transfers
 63. Report TCCS
 64. Report RSKM
 65. Unconstrained Paths
 66. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 14.1.0 Build 186 12/03/2014 SJ Full Version ;
; Revision Name      ; AP9                                                 ;
; Device Family      ; Cyclone V                                           ;
; Device Name        ; 5CEBA4F23C7                                         ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.45        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  45.5%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                         ;
+------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------------+
; Clock Name                                     ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                            ;
+------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------------+
; clk_div:inst25|clock_1KHz                      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_1KHz }                      ;
; clk_div:inst25|clock_1Khz_int                  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_1Khz_int }                  ;
; clk_div:inst25|clock_1Mhz_int                  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_1Mhz_int }                  ;
; clk_div:inst25|clock_10Hz_int                  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_10Hz_int }                  ;
; clk_div:inst25|clock_10Khz_int                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_10Khz_int }                 ;
; clk_div:inst25|clock_100hz_int                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_100hz_int }                 ;
; clk_div:inst25|clock_100KHz                    ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_100KHz }                    ;
; clk_div:inst25|clock_100Khz_int                ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:inst25|clock_100Khz_int }                ;
; CLOCK_50                                       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                                       ;
; dec_keyboard:inst11|f3                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { dec_keyboard:inst11|f3 }                         ;
; keyboard:inst14|ready_set                      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { keyboard:inst14|ready_set }                      ;
; keyboard:inst14|scan_ready                     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { keyboard:inst14|scan_ready }                     ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] } ;
; PS2_CLK                                        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PS2_CLK }                                        ;
; SW[8]                                          ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { SW[8] }                                          ;
+------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------------+


+--------------------------------------------------------------------------------------+
; Slow 1100mV 85C Model Fmax Summary                                                   ;
+------------+-----------------+------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                     ; Note ;
+------------+-----------------+------------------------------------------------+------+
; 81.17 MHz  ; 81.17 MHz       ; CLOCK_50                                       ;      ;
; 155.62 MHz ; 155.62 MHz      ; PS2_CLK                                        ;      ;
; 195.16 MHz ; 195.16 MHz      ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;      ;
; 321.13 MHz ; 321.13 MHz      ; SW[8]                                          ;      ;
; 329.38 MHz ; 329.38 MHz      ; clk_div:inst25|clock_1Mhz_int                  ;      ;
; 346.02 MHz ; 346.02 MHz      ; clk_div:inst25|clock_1Khz_int                  ;      ;
; 359.32 MHz ; 359.32 MHz      ; clk_div:inst25|clock_100Khz_int                ;      ;
; 364.83 MHz ; 364.83 MHz      ; clk_div:inst25|clock_100hz_int                 ;      ;
; 395.26 MHz ; 395.26 MHz      ; clk_div:inst25|clock_10Khz_int                 ;      ;
; 396.04 MHz ; 396.04 MHz      ; dec_keyboard:inst11|f3                         ;      ;
; 446.43 MHz ; 446.43 MHz      ; clk_div:inst25|clock_10Hz_int                  ;      ;
; 448.03 MHz ; 448.03 MHz      ; clk_div:inst25|clock_1KHz                      ;      ;
; 497.02 MHz ; 497.02 MHz      ; clk_div:inst25|clock_100KHz                    ;      ;
+------------+-----------------+------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------------------------------------------+
; Slow 1100mV 85C Model Setup Summary                                     ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; dec_keyboard:inst11|f3                         ; -9.856 ; -89.366       ;
; CLOCK_50                                       ; -5.820 ; -6190.159     ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -5.627 ; -386.934      ;
; PS2_CLK                                        ; -5.426 ; -56.974       ;
; SW[8]                                          ; -3.716 ; -28.115       ;
; clk_div:inst25|clock_1Mhz_int                  ; -2.036 ; -6.358        ;
; clk_div:inst25|clock_1Khz_int                  ; -1.890 ; -8.643        ;
; clk_div:inst25|clock_100Khz_int                ; -1.783 ; -7.738        ;
; clk_div:inst25|clock_100hz_int                 ; -1.741 ; -7.578        ;
; clk_div:inst25|clock_10Khz_int                 ; -1.530 ; -7.243        ;
; clk_div:inst25|clock_1KHz                      ; -1.459 ; -4.165        ;
; clk_div:inst25|clock_10Hz_int                  ; -1.240 ; -7.189        ;
; clk_div:inst25|clock_100KHz                    ; -1.012 ; -3.581        ;
+------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------+
; Slow 1100mV 85C Model Hold Summary                                     ;
+------------------------------------------------+-------+---------------+
; Clock                                          ; Slack ; End Point TNS ;
+------------------------------------------------+-------+---------------+
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 0.022 ; 0.000         ;
; clk_div:inst25|clock_10Khz_int                 ; 0.084 ; 0.000         ;
; CLOCK_50                                       ; 0.101 ; 0.000         ;
; PS2_CLK                                        ; 0.114 ; 0.000         ;
; clk_div:inst25|clock_100Khz_int                ; 0.141 ; 0.000         ;
; clk_div:inst25|clock_100hz_int                 ; 0.184 ; 0.000         ;
; clk_div:inst25|clock_1Khz_int                  ; 0.220 ; 0.000         ;
; clk_div:inst25|clock_1Mhz_int                  ; 0.226 ; 0.000         ;
; clk_div:inst25|clock_1KHz                      ; 0.316 ; 0.000         ;
; clk_div:inst25|clock_100KHz                    ; 0.647 ; 0.000         ;
; dec_keyboard:inst11|f3                         ; 0.703 ; 0.000         ;
; clk_div:inst25|clock_10Hz_int                  ; 0.742 ; 0.000         ;
; SW[8]                                          ; 0.797 ; 0.000         ;
+------------------------------------------------+-------+---------------+


+-----------------------------------------------------+
; Slow 1100mV 85C Model Recovery Summary              ;
+----------------------------+--------+---------------+
; Clock                      ; Slack  ; End Point TNS ;
+----------------------------+--------+---------------+
; keyboard:inst14|ready_set  ; -1.233 ; -1.233        ;
; keyboard:inst14|scan_ready ; -1.220 ; -1.220        ;
+----------------------------+--------+---------------+


+----------------------------------------------------+
; Slow 1100mV 85C Model Removal Summary              ;
+----------------------------+-------+---------------+
; Clock                      ; Slack ; End Point TNS ;
+----------------------------+-------+---------------+
; keyboard:inst14|ready_set  ; 0.187 ; 0.000         ;
; keyboard:inst14|scan_ready ; 0.533 ; 0.000         ;
+----------------------------+-------+---------------+


+-------------------------------------------------------------------------+
; Slow 1100mV 85C Model Minimum Pulse Width Summary                       ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -2.636 ; -7142.670     ;
; PS2_CLK                                        ; -0.595 ; -21.720       ;
; SW[8]                                          ; -0.589 ; -8.273        ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.538 ; -109.064      ;
; dec_keyboard:inst11|f3                         ; -0.538 ; -8.187        ;
; clk_div:inst25|clock_1Khz_int                  ; -0.538 ; -4.858        ;
; clk_div:inst25|clock_10Khz_int                 ; -0.538 ; -4.767        ;
; clk_div:inst25|clock_10Hz_int                  ; -0.538 ; -4.620        ;
; clk_div:inst25|clock_100KHz                    ; -0.538 ; -3.964        ;
; clk_div:inst25|clock_100Khz_int                ; -0.538 ; -3.846        ;
; clk_div:inst25|clock_100hz_int                 ; -0.538 ; -3.844        ;
; clk_div:inst25|clock_1Mhz_int                  ; -0.538 ; -3.402        ;
; clk_div:inst25|clock_1KHz                      ; -0.538 ; -2.880        ;
; keyboard:inst14|scan_ready                     ; -0.538 ; -0.825        ;
; keyboard:inst14|ready_set                      ; -0.538 ; -0.805        ;
+------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; 5.688 ; 5.880 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 0.651 ; 1.646 ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 0.651 ; 1.646 ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 1.989 ; 2.804 ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; 2.227 ; 3.395 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; 2.227 ; 3.395 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; 3.197 ; 3.882 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; 3.197 ; 3.882 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.544 ; 5.562 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.544 ; 5.562 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.372 ; 5.023 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.123 ; 4.522 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.372 ; 5.023 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.272 ; 3.743 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; -1.945 ; -2.146 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 3.961  ; 3.628  ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 3.961  ; 3.628  ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 3.836  ; 3.284  ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; -0.680 ; -1.567 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; -0.680 ; -1.567 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; -2.213 ; -2.750 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; -2.213 ; -2.750 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.560 ; -2.073 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.560 ; -2.073 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.665 ; -2.059 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.665 ; -2.059 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.736 ; -2.217 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -2.197 ; -2.601 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 8.090  ; 8.679  ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 8.090  ; 8.679  ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 8.090  ; 8.679  ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 8.090  ; 8.679  ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.817 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.393 ; 11.330 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.546 ; 11.450 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.817 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.062 ; 12.090 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.684 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.392 ; 11.311 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.684 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.976  ; 10.764 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.744 ; 11.811 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.185 ; 11.079 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.185 ; 12.484 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.185 ; 12.484 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.237 ; 11.082 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.291 ; 11.146 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.284  ; 9.685  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.742 ; 11.759 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------+------------------------------------------------+-------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+--------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 7.493 ; 7.975  ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 7.493 ; 7.975  ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 7.493 ; 7.975  ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 7.493 ; 7.975  ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.326 ; 9.116  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.326 ; 9.116  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.484 ; 9.268  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.159 ; 10.412 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.909 ; 9.758  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.958 ; 8.657  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.345 ; 9.145  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.217 ; 10.372 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.958 ; 8.657  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.658 ; 9.589  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.169 ; 8.973  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.343 ; 7.659  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.060 ; 10.229 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.189 ; 8.948  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.239 ; 9.005  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.343 ; 7.659  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.641 ; 9.512  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+--------+------------+------------------------------------------------+


----------------------------------------------
; Slow 1100mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------+
; Slow 1100mV 0C Model Fmax Summary                                                    ;
+------------+-----------------+------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                     ; Note ;
+------------+-----------------+------------------------------------------------+------+
; 84.18 MHz  ; 84.18 MHz       ; CLOCK_50                                       ;      ;
; 153.61 MHz ; 153.61 MHz      ; PS2_CLK                                        ;      ;
; 200.32 MHz ; 200.32 MHz      ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;      ;
; 326.26 MHz ; 326.26 MHz      ; clk_div:inst25|clock_1Mhz_int                  ;      ;
; 328.19 MHz ; 328.19 MHz      ; SW[8]                                          ;      ;
; 344.95 MHz ; 344.95 MHz      ; clk_div:inst25|clock_1Khz_int                  ;      ;
; 349.9 MHz  ; 349.9 MHz       ; clk_div:inst25|clock_100Khz_int                ;      ;
; 358.04 MHz ; 358.04 MHz      ; clk_div:inst25|clock_100hz_int                 ;      ;
; 387.3 MHz  ; 387.3 MHz       ; clk_div:inst25|clock_10Khz_int                 ;      ;
; 403.71 MHz ; 403.71 MHz      ; dec_keyboard:inst11|f3                         ;      ;
; 445.83 MHz ; 445.83 MHz      ; clk_div:inst25|clock_1KHz                      ;      ;
; 446.23 MHz ; 446.23 MHz      ; clk_div:inst25|clock_10Hz_int                  ;      ;
; 486.85 MHz ; 486.85 MHz      ; clk_div:inst25|clock_100KHz                    ;      ;
+------------+-----------------+------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-------------------------------------------------------------------------+
; Slow 1100mV 0C Model Setup Summary                                      ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; dec_keyboard:inst11|f3                         ; -9.957 ; -89.885       ;
; CLOCK_50                                       ; -5.740 ; -5890.449     ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -5.556 ; -383.930      ;
; PS2_CLK                                        ; -5.510 ; -55.367       ;
; SW[8]                                          ; -3.726 ; -26.975       ;
; clk_div:inst25|clock_1Mhz_int                  ; -2.065 ; -6.535        ;
; clk_div:inst25|clock_1Khz_int                  ; -1.899 ; -8.782        ;
; clk_div:inst25|clock_100Khz_int                ; -1.858 ; -7.926        ;
; clk_div:inst25|clock_100hz_int                 ; -1.793 ; -7.800        ;
; clk_div:inst25|clock_10Khz_int                 ; -1.582 ; -7.315        ;
; clk_div:inst25|clock_1KHz                      ; -1.326 ; -3.932        ;
; clk_div:inst25|clock_10Hz_int                  ; -1.241 ; -7.322        ;
; clk_div:inst25|clock_100KHz                    ; -1.054 ; -3.713        ;
+------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------+
; Slow 1100mV 0C Model Hold Summary                                       ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -0.093 ; -1.036        ;
; PS2_CLK                                        ; -0.022 ; -0.022        ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.012 ; -0.017        ;
; clk_div:inst25|clock_100Khz_int                ; 0.156  ; 0.000         ;
; clk_div:inst25|clock_10Khz_int                 ; 0.173  ; 0.000         ;
; clk_div:inst25|clock_1Khz_int                  ; 0.268  ; 0.000         ;
; clk_div:inst25|clock_100hz_int                 ; 0.279  ; 0.000         ;
; clk_div:inst25|clock_1Mhz_int                  ; 0.299  ; 0.000         ;
; clk_div:inst25|clock_1KHz                      ; 0.341  ; 0.000         ;
; clk_div:inst25|clock_100KHz                    ; 0.644  ; 0.000         ;
; SW[8]                                          ; 0.648  ; 0.000         ;
; dec_keyboard:inst11|f3                         ; 0.673  ; 0.000         ;
; clk_div:inst25|clock_10Hz_int                  ; 0.684  ; 0.000         ;
+------------------------------------------------+--------+---------------+


+-----------------------------------------------------+
; Slow 1100mV 0C Model Recovery Summary               ;
+----------------------------+--------+---------------+
; Clock                      ; Slack  ; End Point TNS ;
+----------------------------+--------+---------------+
; keyboard:inst14|ready_set  ; -1.260 ; -1.260        ;
; keyboard:inst14|scan_ready ; -1.091 ; -1.091        ;
+----------------------------+--------+---------------+


+----------------------------------------------------+
; Slow 1100mV 0C Model Removal Summary               ;
+----------------------------+-------+---------------+
; Clock                      ; Slack ; End Point TNS ;
+----------------------------+-------+---------------+
; keyboard:inst14|ready_set  ; 0.170 ; 0.000         ;
; keyboard:inst14|scan_ready ; 0.479 ; 0.000         ;
+----------------------------+-------+---------------+


+-------------------------------------------------------------------------+
; Slow 1100mV 0C Model Minimum Pulse Width Summary                        ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -2.636 ; -7139.908     ;
; SW[8]                                          ; -0.663 ; -8.672        ;
; PS2_CLK                                        ; -0.651 ; -19.638       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.538 ; -107.126      ;
; dec_keyboard:inst11|f3                         ; -0.538 ; -8.097        ;
; clk_div:inst25|clock_1Khz_int                  ; -0.538 ; -4.806        ;
; clk_div:inst25|clock_10Khz_int                 ; -0.538 ; -4.738        ;
; clk_div:inst25|clock_10Hz_int                  ; -0.538 ; -4.621        ;
; clk_div:inst25|clock_100KHz                    ; -0.538 ; -3.927        ;
; clk_div:inst25|clock_100Khz_int                ; -0.538 ; -3.874        ;
; clk_div:inst25|clock_100hz_int                 ; -0.538 ; -3.858        ;
; clk_div:inst25|clock_1Mhz_int                  ; -0.538 ; -3.376        ;
; clk_div:inst25|clock_1KHz                      ; -0.538 ; -2.825        ;
; keyboard:inst14|scan_ready                     ; -0.538 ; -0.816        ;
; keyboard:inst14|ready_set                      ; -0.538 ; -0.796        ;
+------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; 5.419 ; 5.660 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 0.633 ; 1.455 ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 0.633 ; 1.455 ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 2.013 ; 2.906 ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; 2.208 ; 3.438 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; 2.208 ; 3.438 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; 3.208 ; 3.935 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; 3.208 ; 3.935 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.426 ; 5.476 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.426 ; 5.476 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.420 ; 5.093 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.198 ; 4.666 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.420 ; 5.093 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.365 ; 3.865 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; -1.699 ; -1.895 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 4.052  ; 3.599  ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 4.052  ; 3.599  ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 3.868  ; 3.253  ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; -0.652 ; -1.588 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; -0.652 ; -1.588 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; -2.223 ; -2.818 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; -2.223 ; -2.818 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.566 ; -2.117 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.566 ; -2.117 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.684 ; -2.113 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.684 ; -2.113 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.708 ; -2.232 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -2.271 ; -2.702 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 7.676  ; 8.323  ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 7.676  ; 8.323  ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 7.676  ; 8.323  ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 7.676  ; 8.323  ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.819 ; 12.186 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.849  ; 10.747 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.001 ; 10.891 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.819 ; 12.186 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.476 ; 11.493 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.844 ; 12.090 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.859  ; 10.749 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.844 ; 12.090 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.446  ; 10.214 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.208 ; 11.243 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.693  ; 10.547 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.705 ; 11.906 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.705 ; 11.906 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.707  ; 10.527 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.766  ; 10.593 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.776  ; 9.184  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.161 ; 11.161 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                            ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 7.083 ; 7.625 ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 7.083 ; 7.625 ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 7.083 ; 7.625 ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 7.083 ; 7.625 ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.810 ; 8.581 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.810 ; 8.581 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.971 ; 8.750 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.653 ; 9.835 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.354 ; 9.218 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.460 ; 8.146 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.842 ; 8.623 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.735 ; 9.824 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.460 ; 8.146 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.143 ; 9.048 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.708 ; 8.476 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.842 ; 7.162 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.608 ; 9.686 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.691 ; 8.426 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 7.746 ; 8.486 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.842 ; 7.162 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 8.095 ; 8.962 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


---------------------------------------------
; Slow 1100mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------+
; Fast 1100mV 85C Model Setup Summary                                     ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; dec_keyboard:inst11|f3                         ; -4.332 ; -39.743       ;
; CLOCK_50                                       ; -3.208 ; -3247.507     ;
; SW[8]                                          ; -2.613 ; -19.445       ;
; PS2_CLK                                        ; -2.532 ; -18.279       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -2.150 ; -160.422      ;
; clk_div:inst25|clock_1Mhz_int                  ; -1.007 ; -2.161        ;
; clk_div:inst25|clock_1Khz_int                  ; -0.785 ; -2.585        ;
; clk_div:inst25|clock_100Khz_int                ; -0.709 ; -2.413        ;
; clk_div:inst25|clock_10Khz_int                 ; -0.637 ; -2.005        ;
; clk_div:inst25|clock_100hz_int                 ; -0.554 ; -2.127        ;
; clk_div:inst25|clock_1KHz                      ; -0.417 ; -1.227        ;
; clk_div:inst25|clock_10Hz_int                  ; -0.335 ; -1.773        ;
; clk_div:inst25|clock_100KHz                    ; -0.278 ; -0.660        ;
+------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------+
; Fast 1100mV 85C Model Hold Summary                                      ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -0.282 ; -12.576       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.275 ; -0.680        ;
; clk_div:inst25|clock_1KHz                      ; -0.228 ; -0.387        ;
; clk_div:inst25|clock_10Khz_int                 ; -0.154 ; -0.154        ;
; clk_div:inst25|clock_100hz_int                 ; -0.124 ; -0.124        ;
; clk_div:inst25|clock_1Khz_int                  ; -0.109 ; -0.109        ;
; clk_div:inst25|clock_100Khz_int                ; -0.103 ; -0.103        ;
; clk_div:inst25|clock_1Mhz_int                  ; -0.097 ; -0.097        ;
; PS2_CLK                                        ; 0.181  ; 0.000         ;
; clk_div:inst25|clock_100KHz                    ; 0.210  ; 0.000         ;
; dec_keyboard:inst11|f3                         ; 0.252  ; 0.000         ;
; clk_div:inst25|clock_10Hz_int                  ; 0.317  ; 0.000         ;
; SW[8]                                          ; 0.623  ; 0.000         ;
+------------------------------------------------+--------+---------------+


+-----------------------------------------------------+
; Fast 1100mV 85C Model Recovery Summary              ;
+----------------------------+--------+---------------+
; Clock                      ; Slack  ; End Point TNS ;
+----------------------------+--------+---------------+
; keyboard:inst14|ready_set  ; -0.733 ; -0.733        ;
; keyboard:inst14|scan_ready ; -0.326 ; -0.326        ;
+----------------------------+--------+---------------+


+-----------------------------------------------------+
; Fast 1100mV 85C Model Removal Summary               ;
+----------------------------+--------+---------------+
; Clock                      ; Slack  ; End Point TNS ;
+----------------------------+--------+---------------+
; keyboard:inst14|ready_set  ; -0.138 ; -0.138        ;
; keyboard:inst14|scan_ready ; 0.065  ; 0.000         ;
+----------------------------+--------+---------------+


+-------------------------------------------------------------------------+
; Fast 1100mV 85C Model Minimum Pulse Width Summary                       ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -2.174 ; -5855.688     ;
; SW[8]                                          ; -0.746 ; -8.560        ;
; PS2_CLK                                        ; -0.692 ; -15.529       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.119 ; -4.786        ;
; clk_div:inst25|clock_1KHz                      ; -0.079 ; -0.235        ;
; clk_div:inst25|clock_1Mhz_int                  ; 0.014  ; 0.000         ;
; keyboard:inst14|scan_ready                     ; 0.027  ; 0.000         ;
; dec_keyboard:inst11|f3                         ; 0.043  ; 0.000         ;
; clk_div:inst25|clock_1Khz_int                  ; 0.085  ; 0.000         ;
; clk_div:inst25|clock_100KHz                    ; 0.105  ; 0.000         ;
; keyboard:inst14|ready_set                      ; 0.109  ; 0.000         ;
; clk_div:inst25|clock_100hz_int                 ; 0.131  ; 0.000         ;
; clk_div:inst25|clock_10Khz_int                 ; 0.138  ; 0.000         ;
; clk_div:inst25|clock_100Khz_int                ; 0.148  ; 0.000         ;
; clk_div:inst25|clock_10Hz_int                  ; 0.151  ; 0.000         ;
+------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; 2.984 ; 3.428 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 0.392 ; 1.504 ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 0.392 ; 1.504 ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 1.153 ; 2.363 ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; 1.217 ; 2.657 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; 1.217 ; 2.657 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; 1.600 ; 2.647 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; 1.600 ; 2.647 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2.194 ; 3.534 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2.194 ; 3.534 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2.092 ; 3.128 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1.851 ; 2.692 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2.092 ; 3.128 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1.485 ; 2.394 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; -0.917 ; -1.502 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 1.935  ; 1.056  ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 1.935  ; 1.056  ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 1.804  ; 0.852  ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; -0.469 ; -1.701 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; -0.469 ; -1.701 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; -1.092 ; -2.031 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; -1.092 ; -2.031 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.559 ; -1.481 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.559 ; -1.481 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.659 ; -1.468 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.659 ; -1.468 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.804 ; -1.704 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.932 ; -1.793 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                    ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 4.337 ; 5.338 ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 4.337 ; 5.338 ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 4.337 ; 5.338 ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 4.337 ; 5.338 ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.583 ; 7.820 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.866 ; 6.692 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.979 ; 6.795 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.583 ; 7.820 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.290 ; 7.203 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.587 ; 7.727 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.906 ; 6.720 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.587 ; 7.727 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.673 ; 6.380 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.127 ; 7.046 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.778 ; 6.553 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.531 ; 7.642 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.531 ; 7.642 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.806 ; 6.550 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.876 ; 6.626 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.056 ; 5.410 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.095 ; 6.995 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                            ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 4.069 ; 5.007 ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 4.069 ; 5.007 ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 4.069 ; 5.007 ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 4.069 ; 5.007 ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.859 ; 5.587 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.859 ; 5.587 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.981 ; 5.721 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.492 ; 6.591 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.240 ; 6.032 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.695 ; 5.345 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.911 ; 5.647 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.540 ; 6.565 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.695 ; 5.345 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.110 ; 5.940 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.804 ; 5.521 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.120 ; 4.418 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.484 ; 6.512 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.816 ; 5.503 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.881 ; 5.573 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.120 ; 4.418 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.075 ; 5.876 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


----------------------------------------------
; Fast 1100mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------+
; Fast 1100mV 0C Model Setup Summary                                      ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; dec_keyboard:inst11|f3                         ; -4.167 ; -38.227       ;
; CLOCK_50                                       ; -2.889 ; -2816.620     ;
; PS2_CLK                                        ; -2.452 ; -14.781       ;
; SW[8]                                          ; -2.152 ; -16.044       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -1.959 ; -141.925      ;
; clk_div:inst25|clock_1Mhz_int                  ; -0.921 ; -1.911        ;
; clk_div:inst25|clock_1Khz_int                  ; -0.731 ; -2.249        ;
; clk_div:inst25|clock_100Khz_int                ; -0.671 ; -2.109        ;
; clk_div:inst25|clock_10Khz_int                 ; -0.609 ; -1.681        ;
; clk_div:inst25|clock_100hz_int                 ; -0.531 ; -1.883        ;
; clk_div:inst25|clock_1KHz                      ; -0.304 ; -0.903        ;
; clk_div:inst25|clock_10Hz_int                  ; -0.274 ; -1.447        ;
; clk_div:inst25|clock_100KHz                    ; -0.190 ; -0.439        ;
+------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------+
; Fast 1100mV 0C Model Hold Summary                                       ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -0.366 ; -81.938       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.259 ; -0.964        ;
; clk_div:inst25|clock_1KHz                      ; -0.235 ; -0.499        ;
; clk_div:inst25|clock_10Khz_int                 ; -0.151 ; -0.151        ;
; clk_div:inst25|clock_100Khz_int                ; -0.123 ; -0.123        ;
; clk_div:inst25|clock_100hz_int                 ; -0.121 ; -0.121        ;
; clk_div:inst25|clock_1Khz_int                  ; -0.115 ; -0.115        ;
; clk_div:inst25|clock_1Mhz_int                  ; -0.093 ; -0.093        ;
; PS2_CLK                                        ; 0.162  ; 0.000         ;
; clk_div:inst25|clock_100KHz                    ; 0.195  ; 0.000         ;
; dec_keyboard:inst11|f3                         ; 0.233  ; 0.000         ;
; clk_div:inst25|clock_10Hz_int                  ; 0.270  ; 0.000         ;
; SW[8]                                          ; 0.432  ; 0.000         ;
+------------------------------------------------+--------+---------------+


+-----------------------------------------------------+
; Fast 1100mV 0C Model Recovery Summary               ;
+----------------------------+--------+---------------+
; Clock                      ; Slack  ; End Point TNS ;
+----------------------------+--------+---------------+
; keyboard:inst14|ready_set  ; -0.643 ; -0.643        ;
; keyboard:inst14|scan_ready ; -0.244 ; -0.244        ;
+----------------------------+--------+---------------+


+-----------------------------------------------------+
; Fast 1100mV 0C Model Removal Summary                ;
+----------------------------+--------+---------------+
; Clock                      ; Slack  ; End Point TNS ;
+----------------------------+--------+---------------+
; keyboard:inst14|ready_set  ; -0.164 ; -0.164        ;
; keyboard:inst14|scan_ready ; 0.005  ; 0.000         ;
+----------------------------+--------+---------------+


+-------------------------------------------------------------------------+
; Fast 1100mV 0C Model Minimum Pulse Width Summary                        ;
+------------------------------------------------+--------+---------------+
; Clock                                          ; Slack  ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; CLOCK_50                                       ; -2.174 ; -5959.134     ;
; SW[8]                                          ; -0.785 ; -9.543        ;
; PS2_CLK                                        ; -0.738 ; -17.221       ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.050 ; -1.207        ;
; clk_div:inst25|clock_1KHz                      ; -0.024 ; -0.070        ;
; clk_div:inst25|clock_1Mhz_int                  ; 0.045  ; 0.000         ;
; keyboard:inst14|scan_ready                     ; 0.064  ; 0.000         ;
; dec_keyboard:inst11|f3                         ; 0.066  ; 0.000         ;
; clk_div:inst25|clock_1Khz_int                  ; 0.106  ; 0.000         ;
; clk_div:inst25|clock_100KHz                    ; 0.112  ; 0.000         ;
; keyboard:inst14|ready_set                      ; 0.129  ; 0.000         ;
; clk_div:inst25|clock_100hz_int                 ; 0.131  ; 0.000         ;
; clk_div:inst25|clock_100Khz_int                ; 0.142  ; 0.000         ;
; clk_div:inst25|clock_10Khz_int                 ; 0.147  ; 0.000         ;
; clk_div:inst25|clock_10Hz_int                  ; 0.149  ; 0.000         ;
+------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; 2.549 ; 3.109 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 0.386 ; 1.471 ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 0.386 ; 1.471 ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 1.080 ; 2.265 ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; 1.142 ; 2.505 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; 1.142 ; 2.505 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; 1.534 ; 2.570 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; 1.534 ; 2.570 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2.052 ; 3.321 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2.052 ; 3.321 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1.975 ; 2.994 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1.770 ; 2.656 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1.975 ; 2.994 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1.442 ; 2.370 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; -0.735 ; -1.364 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 1.976  ; 1.065  ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 1.976  ; 1.065  ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 1.848  ; 0.880  ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; -0.424 ; -1.614 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; -0.424 ; -1.614 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; -1.053 ; -2.011 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; -1.053 ; -2.011 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.559 ; -1.490 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.559 ; -1.490 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.638 ; -1.493 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.638 ; -1.493 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.752 ; -1.677 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.907 ; -1.791 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                    ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 3.962 ; 4.983 ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 3.962 ; 4.983 ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 3.962 ; 4.983 ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 3.962 ; 4.983 ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.007 ; 6.964 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.378 ; 6.020 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.459 ; 6.104 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.007 ; 6.964 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.730 ; 6.438 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.038 ; 6.917 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.420 ; 6.053 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 6.038 ; 6.917 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.180 ; 5.724 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.576 ; 6.293 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.311 ; 5.910 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.984 ; 6.827 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.984 ; 6.827 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.297 ; 5.874 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.361 ; 5.940 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.598 ; 4.897 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.572 ; 6.269 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                            ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 3.711 ; 4.672 ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 3.711 ; 4.672 ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 3.711 ; 4.672 ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 3.711 ; 4.672 ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.399 ; 4.956 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.399 ; 4.956 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.487 ; 5.056 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.954 ; 5.787 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.712 ; 5.320 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.226 ; 4.710 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.452 ; 5.009 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.021 ; 5.792 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.226 ; 4.710 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.588 ; 5.215 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.361 ; 4.896 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.685 ; 3.929 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.967 ; 5.719 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.330 ; 4.844 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.390 ; 4.905 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.685 ; 3.929 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.582 ; 5.190 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


---------------------------------------------
; Fast 1100mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                              ;
+-------------------------------------------------+-----------+---------+----------+---------+---------------------+
; Clock                                           ; Setup     ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------+-----------+---------+----------+---------+---------------------+
; Worst-case Slack                                ; -9.957    ; -0.366  ; -1.260   ; -0.164  ; -2.636              ;
;  CLOCK_50                                       ; -5.820    ; -0.366  ; N/A      ; N/A     ; -2.636              ;
;  PS2_CLK                                        ; -5.510    ; -0.022  ; N/A      ; N/A     ; -0.738              ;
;  SW[8]                                          ; -3.726    ; 0.432   ; N/A      ; N/A     ; -0.785              ;
;  clk_div:inst25|clock_100KHz                    ; -1.054    ; 0.195   ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_100Khz_int                ; -1.858    ; -0.123  ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_100hz_int                 ; -1.793    ; -0.124  ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_10Hz_int                  ; -1.241    ; 0.270   ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_10Khz_int                 ; -1.582    ; -0.154  ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_1KHz                      ; -1.459    ; -0.235  ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_1Khz_int                  ; -1.899    ; -0.115  ; N/A      ; N/A     ; -0.538              ;
;  clk_div:inst25|clock_1Mhz_int                  ; -2.065    ; -0.097  ; N/A      ; N/A     ; -0.538              ;
;  dec_keyboard:inst11|f3                         ; -9.957    ; 0.233   ; N/A      ; N/A     ; -0.538              ;
;  keyboard:inst14|ready_set                      ; N/A       ; N/A     ; -1.260   ; -0.164  ; -0.538              ;
;  keyboard:inst14|scan_ready                     ; N/A       ; N/A     ; -1.220   ; 0.005   ; -0.538              ;
;  lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -5.627    ; -0.275  ; N/A      ; N/A     ; -0.538              ;
; Design-wide TNS                                 ; -6804.043 ; -84.004 ; -2.453   ; -0.164  ; -7323.725           ;
;  CLOCK_50                                       ; -6190.159 ; -81.938 ; N/A      ; N/A     ; -7142.670           ;
;  PS2_CLK                                        ; -56.974   ; -0.022  ; N/A      ; N/A     ; -21.720             ;
;  SW[8]                                          ; -28.115   ; 0.000   ; N/A      ; N/A     ; -9.543              ;
;  clk_div:inst25|clock_100KHz                    ; -3.713    ; 0.000   ; N/A      ; N/A     ; -3.964              ;
;  clk_div:inst25|clock_100Khz_int                ; -7.926    ; -0.123  ; N/A      ; N/A     ; -3.874              ;
;  clk_div:inst25|clock_100hz_int                 ; -7.800    ; -0.124  ; N/A      ; N/A     ; -3.858              ;
;  clk_div:inst25|clock_10Hz_int                  ; -7.322    ; 0.000   ; N/A      ; N/A     ; -4.621              ;
;  clk_div:inst25|clock_10Khz_int                 ; -7.315    ; -0.154  ; N/A      ; N/A     ; -4.767              ;
;  clk_div:inst25|clock_1KHz                      ; -4.165    ; -0.499  ; N/A      ; N/A     ; -2.880              ;
;  clk_div:inst25|clock_1Khz_int                  ; -8.782    ; -0.115  ; N/A      ; N/A     ; -4.858              ;
;  clk_div:inst25|clock_1Mhz_int                  ; -6.535    ; -0.097  ; N/A      ; N/A     ; -3.402              ;
;  dec_keyboard:inst11|f3                         ; -89.885   ; 0.000   ; N/A      ; N/A     ; -8.187              ;
;  keyboard:inst14|ready_set                      ; N/A       ; N/A     ; -1.260   ; -0.164  ; -0.805              ;
;  keyboard:inst14|scan_ready                     ; N/A       ; N/A     ; -1.220   ; 0.000   ; -0.825              ;
;  lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -386.934  ; -0.964  ; N/A      ; N/A     ; -109.064            ;
+-------------------------------------------------+-----------+---------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; 5.688 ; 5.880 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 0.651 ; 1.646 ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 0.651 ; 1.646 ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 2.013 ; 2.906 ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; 2.227 ; 3.438 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; 2.227 ; 3.438 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; 3.208 ; 3.935 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; 3.208 ; 3.935 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.544 ; 5.562 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.544 ; 5.562 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.420 ; 5.093 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.198 ; 4.666 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.420 ; 5.093 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.365 ; 3.865 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; CLOCK_50  ; CLOCK_50                                       ; -0.735 ; -1.364 ; Rise       ; CLOCK_50                                       ;
; KEY[*]    ; PS2_CLK                                        ; 4.052  ; 3.628  ; Rise       ; PS2_CLK                                        ;
;  KEY[0]   ; PS2_CLK                                        ; 4.052  ; 3.628  ; Rise       ; PS2_CLK                                        ;
; PS2_DAT   ; PS2_CLK                                        ; 3.868  ; 3.284  ; Rise       ; PS2_CLK                                        ;
; KEY[*]    ; SW[8]                                          ; -0.424 ; -1.567 ; Rise       ; SW[8]                                          ;
;  KEY[0]   ; SW[8]                                          ; -0.424 ; -1.567 ; Rise       ; SW[8]                                          ;
; SW[*]     ; clk_div:inst25|clock_100KHz                    ; -1.053 ; -2.011 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
;  SW[9]    ; clk_div:inst25|clock_100KHz                    ; -1.053 ; -2.011 ; Rise       ; clk_div:inst25|clock_100KHz                    ;
; KEY[*]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.559 ; -1.481 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  KEY[0]   ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.559 ; -1.481 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; SW[*]     ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.638 ; -1.468 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[0]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.638 ; -1.468 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[1]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.752 ; -1.677 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  SW[2]    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; -0.907 ; -1.791 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 8.090  ; 8.679  ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 8.090  ; 8.679  ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 8.090  ; 8.679  ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 8.090  ; 8.679  ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.817 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.393 ; 11.330 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.546 ; 11.450 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.817 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.062 ; 12.090 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.684 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.392 ; 11.311 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.353 ; 12.684 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.976  ; 10.764 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.744 ; 11.811 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.185 ; 11.079 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.185 ; 12.484 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 11.185 ; 12.484 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.237 ; 11.082 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.291 ; 11.146 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 9.284  ; 9.685  ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 10.742 ; 11.759 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+--------+--------+------------+------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                            ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; Data Port ; Clock Port                                     ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+
; LEDR[*]   ; SW[8]                                          ; 3.711 ; 4.672 ; Rise       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 3.711 ; 4.672 ; Rise       ; SW[8]                                          ;
; LEDR[*]   ; SW[8]                                          ; 3.711 ; 4.672 ; Fall       ; SW[8]                                          ;
;  LEDR[8]  ; SW[8]                                          ; 3.711 ; 4.672 ; Fall       ; SW[8]                                          ;
; VGA_B[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.399 ; 4.956 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.399 ; 4.956 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.487 ; 5.056 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.954 ; 5.787 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_B[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.712 ; 5.320 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_G[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.226 ; 4.710 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.452 ; 5.009 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 5.021 ; 5.792 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.226 ; 4.710 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_G[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.588 ; 5.215 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_HS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.361 ; 4.896 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_R[*]  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.685 ; 3.929 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.967 ; 5.719 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[1] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.330 ; 4.844 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[2] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.390 ; 4.905 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
;  VGA_R[3] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 3.685 ; 3.929 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
; VGA_VS    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 4.582 ; 5.190 ; Rise       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ;
+-----------+------------------------------------------------+-------+-------+------------+------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                               ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin      ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LEDR[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-------------------------------------------------------------+
; Input Transition Times                                      ;
+----------+--------------+-----------------+-----------------+
; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------+--------------+-----------------+-----------------+
; SW[6]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[7]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[8]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; PS2_CLK  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; PS2_DAT  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[2]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[0]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[1]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SW[9]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+----------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin      ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.132 V                              ; 0.377 V                              ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.132 V                             ; 0.377 V                             ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_HS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.131 V                              ; 0.38 V                               ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.131 V                             ; 0.38 V                              ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; LEDR[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.131 V                              ; 0.38 V                               ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.131 V                             ; 0.38 V                              ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-07 V                   ; 3.09 V              ; -0.13 V             ; 0.032 V                              ; 0.298 V                              ; 4.39e-10 s                  ; 1.69e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-07 V                  ; 3.09 V             ; -0.13 V            ; 0.032 V                             ; 0.298 V                             ; 4.39e-10 s                 ; 1.69e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.1e-07 V                    ; 3.12 V              ; -0.169 V            ; 0.165 V                              ; 0.384 V                              ; 4.57e-10 s                  ; 1.75e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.1e-07 V                   ; 3.12 V             ; -0.169 V           ; 0.165 V                             ; 0.384 V                             ; 4.57e-10 s                 ; 1.75e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.132 V                              ; 0.377 V                              ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.132 V                             ; 0.377 V                             ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_B[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.131 V                              ; 0.38 V                               ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.131 V                             ; 0.38 V                              ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-07 V                   ; 3.09 V              ; -0.13 V             ; 0.032 V                              ; 0.298 V                              ; 4.39e-10 s                  ; 1.69e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-07 V                  ; 3.09 V             ; -0.13 V            ; 0.032 V                             ; 0.298 V                             ; 4.39e-10 s                 ; 1.69e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.1e-07 V                    ; 3.12 V              ; -0.169 V            ; 0.165 V                              ; 0.384 V                              ; 4.57e-10 s                  ; 1.75e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.1e-07 V                   ; 3.12 V             ; -0.169 V           ; 0.165 V                             ; 0.384 V                             ; 4.57e-10 s                 ; 1.75e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.132 V                              ; 0.377 V                              ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.132 V                             ; 0.377 V                             ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.131 V                              ; 0.38 V                               ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.131 V                             ; 0.38 V                              ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.131 V                              ; 0.38 V                               ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.131 V                             ; 0.38 V                              ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.58e-07 V                   ; 3.09 V              ; -0.13 V             ; 0.032 V                              ; 0.298 V                              ; 4.39e-10 s                  ; 1.69e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.58e-07 V                  ; 3.09 V             ; -0.13 V            ; 0.032 V                             ; 0.298 V                             ; 4.39e-10 s                 ; 1.69e-10 s                 ; Yes                       ; Yes                       ;
; VGA_R[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.1e-07 V                    ; 3.12 V              ; -0.169 V            ; 0.165 V                              ; 0.384 V                              ; 4.57e-10 s                  ; 1.75e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.1e-07 V                   ; 3.12 V             ; -0.169 V           ; 0.165 V                             ; 0.384 V                             ; 4.57e-10 s                 ; 1.75e-10 s                 ; Yes                       ; No                        ;
; VGA_R[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.01e-07 V                   ; 3.13 V              ; -0.229 V            ; 0.132 V                              ; 0.377 V                              ; 4.37e-10 s                  ; 1.58e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.01e-07 V                  ; 3.13 V             ; -0.229 V           ; 0.132 V                             ; 0.377 V                             ; 4.37e-10 s                 ; 1.58e-10 s                 ; Yes                       ; No                        ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin      ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.148 V                              ; 5.31e-10 s                  ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.148 V                             ; 5.31e-10 s                 ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_HS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.147 V                              ; 5.3e-10 s                   ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.147 V                             ; 5.3e-10 s                  ; 3.14e-10 s                 ; Yes                       ; No                        ;
; LEDR[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.147 V                              ; 5.3e-10 s                   ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.147 V                             ; 5.3e-10 s                  ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.66e-05 V                   ; 3.09 V              ; -0.0542 V           ; 0.04 V                               ; 0.089 V                              ; 5.35e-10 s                  ; 3.01e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.66e-05 V                  ; 3.09 V             ; -0.0542 V          ; 0.04 V                              ; 0.089 V                             ; 5.35e-10 s                 ; 3.01e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.1e-05 V                    ; 3.11 V              ; -0.0931 V           ; 0.115 V                              ; 0.142 V                              ; 5.74e-10 s                  ; 3.17e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.1e-05 V                   ; 3.11 V             ; -0.0931 V          ; 0.115 V                             ; 0.142 V                             ; 5.74e-10 s                 ; 3.17e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.148 V                              ; 5.31e-10 s                  ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.148 V                             ; 5.31e-10 s                 ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_B[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.147 V                              ; 5.3e-10 s                   ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.147 V                             ; 5.3e-10 s                  ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.66e-05 V                   ; 3.09 V              ; -0.0542 V           ; 0.04 V                               ; 0.089 V                              ; 5.35e-10 s                  ; 3.01e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.66e-05 V                  ; 3.09 V             ; -0.0542 V          ; 0.04 V                              ; 0.089 V                             ; 5.35e-10 s                 ; 3.01e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.1e-05 V                    ; 3.11 V              ; -0.0931 V           ; 0.115 V                              ; 0.142 V                              ; 5.74e-10 s                  ; 3.17e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.1e-05 V                   ; 3.11 V             ; -0.0931 V          ; 0.115 V                             ; 0.142 V                             ; 5.74e-10 s                 ; 3.17e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.148 V                              ; 5.31e-10 s                  ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.148 V                             ; 5.31e-10 s                 ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.147 V                              ; 5.3e-10 s                   ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.147 V                             ; 5.3e-10 s                  ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.147 V                              ; 5.3e-10 s                   ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.147 V                             ; 5.3e-10 s                  ; 3.14e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.66e-05 V                   ; 3.09 V              ; -0.0542 V           ; 0.04 V                               ; 0.089 V                              ; 5.35e-10 s                  ; 3.01e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.66e-05 V                  ; 3.09 V             ; -0.0542 V          ; 0.04 V                              ; 0.089 V                             ; 5.35e-10 s                 ; 3.01e-10 s                 ; Yes                       ; Yes                       ;
; VGA_R[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.1e-05 V                    ; 3.11 V              ; -0.0931 V           ; 0.115 V                              ; 0.142 V                              ; 5.74e-10 s                  ; 3.17e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.1e-05 V                   ; 3.11 V             ; -0.0931 V          ; 0.115 V                             ; 0.142 V                             ; 5.74e-10 s                 ; 3.17e-10 s                 ; Yes                       ; Yes                       ;
; VGA_R[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.02e-05 V                   ; 3.11 V              ; -0.117 V            ; 0.087 V                              ; 0.148 V                              ; 5.31e-10 s                  ; 3.14e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.02e-05 V                  ; 3.11 V             ; -0.117 V           ; 0.087 V                             ; 0.148 V                             ; 5.31e-10 s                 ; 3.14e-10 s                 ; Yes                       ; No                        ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin      ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_HS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; LEDR[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
; VGA_B[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_B[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
; VGA_G[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
; VGA_R[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
; VGA_R[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin      ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_HS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; LEDR[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
; VGA_B[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_R[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
; VGA_R[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
; VGA_R[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
; VGA_R[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                             ;
+------------------------------------------------+------------------------------------------------+----------+----------+----------+----------+
; From Clock                                     ; To Clock                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------+------------------------------------------------+----------+----------+----------+----------+
; clk_div:inst25|clock_1KHz                      ; clk_div:inst25|clock_1KHz                      ; 4        ; 0        ; 0        ; 0        ;
; keyboard:inst14|scan_ready                     ; clk_div:inst25|clock_1KHz                      ; 3        ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_1Khz_int                  ; clk_div:inst25|clock_1Khz_int                  ; 16       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_100hz_int                 ; clk_div:inst25|clock_1Khz_int                  ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1Mhz_int                  ; clk_div:inst25|clock_1Mhz_int                  ; 11       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_100Khz_int                ; clk_div:inst25|clock_1Mhz_int                  ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Hz_int                  ; clk_div:inst25|clock_10Hz_int                  ; 18       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_1Khz_int                  ; clk_div:inst25|clock_10Khz_int                 ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Khz_int                 ; clk_div:inst25|clock_10Khz_int                 ; 16       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_10Hz_int                  ; clk_div:inst25|clock_100hz_int                 ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100hz_int                 ; clk_div:inst25|clock_100hz_int                 ; 14       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_100KHz                    ; clk_div:inst25|clock_100KHz                    ; 7        ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_10Khz_int                 ; clk_div:inst25|clock_100Khz_int                ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100Khz_int                ; clk_div:inst25|clock_100Khz_int                ; 14       ; 0        ; 0        ; 0        ;
; CLOCK_50                                       ; CLOCK_50                                       ; 6965     ; 981      ; 0        ; 0        ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; CLOCK_50                                       ; 54904    ; 982      ; 0        ; 0        ;
; dec_keyboard:inst11|f3                         ; dec_keyboard:inst11|f3                         ; 12       ; 0        ; 0        ; 0        ;
; PS2_CLK                                        ; dec_keyboard:inst11|f3                         ; 304      ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_1KHz                      ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1Khz_int                  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1Mhz_int                  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Hz_int                  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Khz_int                 ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100hz_int                 ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100KHz                    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100Khz_int                ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; CLOCK_50                                       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 28       ; 0        ; 0        ; 0        ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1469     ; 0        ; 0        ; 0        ;
; SW[8]                                          ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 111      ; 0        ; 0        ; 0        ;
; keyboard:inst14|ready_set                      ; PS2_CLK                                        ; 1        ; 1        ; 0        ; 0        ;
; PS2_CLK                                        ; PS2_CLK                                        ; 130      ; 0        ; 0        ; 0        ;
; dec_keyboard:inst11|f3                         ; SW[8]                                          ; 71       ; 0        ; 0        ; 0        ;
; SW[8]                                          ; SW[8]                                          ; 1        ; 0        ; 0        ; 0        ;
+------------------------------------------------+------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                              ;
+------------------------------------------------+------------------------------------------------+----------+----------+----------+----------+
; From Clock                                     ; To Clock                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------+------------------------------------------------+----------+----------+----------+----------+
; clk_div:inst25|clock_1KHz                      ; clk_div:inst25|clock_1KHz                      ; 4        ; 0        ; 0        ; 0        ;
; keyboard:inst14|scan_ready                     ; clk_div:inst25|clock_1KHz                      ; 3        ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_1Khz_int                  ; clk_div:inst25|clock_1Khz_int                  ; 16       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_100hz_int                 ; clk_div:inst25|clock_1Khz_int                  ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1Mhz_int                  ; clk_div:inst25|clock_1Mhz_int                  ; 11       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_100Khz_int                ; clk_div:inst25|clock_1Mhz_int                  ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Hz_int                  ; clk_div:inst25|clock_10Hz_int                  ; 18       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_1Khz_int                  ; clk_div:inst25|clock_10Khz_int                 ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Khz_int                 ; clk_div:inst25|clock_10Khz_int                 ; 16       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_10Hz_int                  ; clk_div:inst25|clock_100hz_int                 ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100hz_int                 ; clk_div:inst25|clock_100hz_int                 ; 14       ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_100KHz                    ; clk_div:inst25|clock_100KHz                    ; 7        ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_10Khz_int                 ; clk_div:inst25|clock_100Khz_int                ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100Khz_int                ; clk_div:inst25|clock_100Khz_int                ; 14       ; 0        ; 0        ; 0        ;
; CLOCK_50                                       ; CLOCK_50                                       ; 6965     ; 981      ; 0        ; 0        ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; CLOCK_50                                       ; 54904    ; 982      ; 0        ; 0        ;
; dec_keyboard:inst11|f3                         ; dec_keyboard:inst11|f3                         ; 12       ; 0        ; 0        ; 0        ;
; PS2_CLK                                        ; dec_keyboard:inst11|f3                         ; 304      ; 0        ; 0        ; 0        ;
; clk_div:inst25|clock_1KHz                      ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1Khz_int                  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1Mhz_int                  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Hz_int                  ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 2        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_10Khz_int                 ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100hz_int                 ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100KHz                    ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_100Khz_int                ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1        ; 1        ; 0        ; 0        ;
; CLOCK_50                                       ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 28       ; 0        ; 0        ; 0        ;
; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 1469     ; 0        ; 0        ; 0        ;
; SW[8]                                          ; lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 111      ; 0        ; 0        ; 0        ;
; keyboard:inst14|ready_set                      ; PS2_CLK                                        ; 1        ; 1        ; 0        ; 0        ;
; PS2_CLK                                        ; PS2_CLK                                        ; 130      ; 0        ; 0        ; 0        ;
; dec_keyboard:inst11|f3                         ; SW[8]                                          ; 71       ; 0        ; 0        ; 0        ;
; SW[8]                                          ; SW[8]                                          ; 1        ; 0        ; 0        ; 0        ;
+------------------------------------------------+------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                  ;
+----------------------------+----------------------------+----------+----------+----------+----------+
; From Clock                 ; To Clock                   ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------+----------------------------+----------+----------+----------+----------+
; keyboard:inst14|scan_ready ; keyboard:inst14|ready_set  ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1KHz  ; keyboard:inst14|scan_ready ; 1        ; 0        ; 0        ; 0        ;
+----------------------------+----------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                   ;
+----------------------------+----------------------------+----------+----------+----------+----------+
; From Clock                 ; To Clock                   ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------+----------------------------+----------+----------+----------+----------+
; keyboard:inst14|scan_ready ; keyboard:inst14|ready_set  ; 1        ; 1        ; 0        ; 0        ;
; clk_div:inst25|clock_1KHz  ; keyboard:inst14|scan_ready ; 1        ; 0        ; 0        ; 0        ;
+----------------------------+----------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 7     ; 7    ;
; Unconstrained Input Port Paths  ; 195   ; 195  ;
; Unconstrained Output Ports      ; 15    ; 15   ;
; Unconstrained Output Port Paths ; 15    ; 15   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 14.1.0 Build 186 12/03/2014 SJ Full Version
    Info: Processing started: Tue Nov  8 13:34:33 2016
Info: Command: quartus_sta AP9 -c AP9
Info: qsta_default_script.tcl version: #3
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'AP9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
    Info (332105): create_clock -period 1.000 -name lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0]
    Info (332105): create_clock -period 1.000 -name SW[8] SW[8]
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_100KHz clk_div:inst25|clock_100KHz
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_1Mhz_int clk_div:inst25|clock_1Mhz_int
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_100Khz_int clk_div:inst25|clock_100Khz_int
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_10Hz_int clk_div:inst25|clock_10Hz_int
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_100hz_int clk_div:inst25|clock_100hz_int
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_1Khz_int clk_div:inst25|clock_1Khz_int
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_10Khz_int clk_div:inst25|clock_10Khz_int
    Info (332105): create_clock -period 1.000 -name dec_keyboard:inst11|f3 dec_keyboard:inst11|f3
    Info (332105): create_clock -period 1.000 -name clk_div:inst25|clock_1KHz clk_div:inst25|clock_1KHz
    Info (332105): create_clock -period 1.000 -name keyboard:inst14|scan_ready keyboard:inst14|scan_ready
    Info (332105): create_clock -period 1.000 -name keyboard:inst14|ready_set keyboard:inst14|ready_set
    Info (332105): create_clock -period 1.000 -name PS2_CLK PS2_CLK
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: inst5  from: dataf  to: combout
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -9.856
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -9.856             -89.366 dec_keyboard:inst11|f3 
    Info (332119):    -5.820           -6190.159 CLOCK_50 
    Info (332119):    -5.627            -386.934 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -5.426             -56.974 PS2_CLK 
    Info (332119):    -3.716             -28.115 SW[8] 
    Info (332119):    -2.036              -6.358 clk_div:inst25|clock_1Mhz_int 
    Info (332119):    -1.890              -8.643 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -1.783              -7.738 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -1.741              -7.578 clk_div:inst25|clock_100hz_int 
    Info (332119):    -1.530              -7.243 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -1.459              -4.165 clk_div:inst25|clock_1KHz 
    Info (332119):    -1.240              -7.189 clk_div:inst25|clock_10Hz_int 
    Info (332119):    -1.012              -3.581 clk_div:inst25|clock_100KHz 
Info (332146): Worst-case hold slack is 0.022
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.022               0.000 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):     0.084               0.000 clk_div:inst25|clock_10Khz_int 
    Info (332119):     0.101               0.000 CLOCK_50 
    Info (332119):     0.114               0.000 PS2_CLK 
    Info (332119):     0.141               0.000 clk_div:inst25|clock_100Khz_int 
    Info (332119):     0.184               0.000 clk_div:inst25|clock_100hz_int 
    Info (332119):     0.220               0.000 clk_div:inst25|clock_1Khz_int 
    Info (332119):     0.226               0.000 clk_div:inst25|clock_1Mhz_int 
    Info (332119):     0.316               0.000 clk_div:inst25|clock_1KHz 
    Info (332119):     0.647               0.000 clk_div:inst25|clock_100KHz 
    Info (332119):     0.703               0.000 dec_keyboard:inst11|f3 
    Info (332119):     0.742               0.000 clk_div:inst25|clock_10Hz_int 
    Info (332119):     0.797               0.000 SW[8] 
Info (332146): Worst-case recovery slack is -1.233
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.233              -1.233 keyboard:inst14|ready_set 
    Info (332119):    -1.220              -1.220 keyboard:inst14|scan_ready 
Info (332146): Worst-case removal slack is 0.187
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.187               0.000 keyboard:inst14|ready_set 
    Info (332119):     0.533               0.000 keyboard:inst14|scan_ready 
Info (332146): Worst-case minimum pulse width slack is -2.636
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.636           -7142.670 CLOCK_50 
    Info (332119):    -0.595             -21.720 PS2_CLK 
    Info (332119):    -0.589              -8.273 SW[8] 
    Info (332119):    -0.538            -109.064 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.538              -8.187 dec_keyboard:inst11|f3 
    Info (332119):    -0.538              -4.858 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -0.538              -4.767 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -0.538              -4.620 clk_div:inst25|clock_10Hz_int 
    Info (332119):    -0.538              -3.964 clk_div:inst25|clock_100KHz 
    Info (332119):    -0.538              -3.846 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -0.538              -3.844 clk_div:inst25|clock_100hz_int 
    Info (332119):    -0.538              -3.402 clk_div:inst25|clock_1Mhz_int 
    Info (332119):    -0.538              -2.880 clk_div:inst25|clock_1KHz 
    Info (332119):    -0.538              -0.825 keyboard:inst14|scan_ready 
    Info (332119):    -0.538              -0.805 keyboard:inst14|ready_set 
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: inst5  from: dataf  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -9.957
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -9.957             -89.885 dec_keyboard:inst11|f3 
    Info (332119):    -5.740           -5890.449 CLOCK_50 
    Info (332119):    -5.556            -383.930 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -5.510             -55.367 PS2_CLK 
    Info (332119):    -3.726             -26.975 SW[8] 
    Info (332119):    -2.065              -6.535 clk_div:inst25|clock_1Mhz_int 
    Info (332119):    -1.899              -8.782 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -1.858              -7.926 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -1.793              -7.800 clk_div:inst25|clock_100hz_int 
    Info (332119):    -1.582              -7.315 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -1.326              -3.932 clk_div:inst25|clock_1KHz 
    Info (332119):    -1.241              -7.322 clk_div:inst25|clock_10Hz_int 
    Info (332119):    -1.054              -3.713 clk_div:inst25|clock_100KHz 
Info (332146): Worst-case hold slack is -0.093
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.093              -1.036 CLOCK_50 
    Info (332119):    -0.022              -0.022 PS2_CLK 
    Info (332119):    -0.012              -0.017 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):     0.156               0.000 clk_div:inst25|clock_100Khz_int 
    Info (332119):     0.173               0.000 clk_div:inst25|clock_10Khz_int 
    Info (332119):     0.268               0.000 clk_div:inst25|clock_1Khz_int 
    Info (332119):     0.279               0.000 clk_div:inst25|clock_100hz_int 
    Info (332119):     0.299               0.000 clk_div:inst25|clock_1Mhz_int 
    Info (332119):     0.341               0.000 clk_div:inst25|clock_1KHz 
    Info (332119):     0.644               0.000 clk_div:inst25|clock_100KHz 
    Info (332119):     0.648               0.000 SW[8] 
    Info (332119):     0.673               0.000 dec_keyboard:inst11|f3 
    Info (332119):     0.684               0.000 clk_div:inst25|clock_10Hz_int 
Info (332146): Worst-case recovery slack is -1.260
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.260              -1.260 keyboard:inst14|ready_set 
    Info (332119):    -1.091              -1.091 keyboard:inst14|scan_ready 
Info (332146): Worst-case removal slack is 0.170
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.170               0.000 keyboard:inst14|ready_set 
    Info (332119):     0.479               0.000 keyboard:inst14|scan_ready 
Info (332146): Worst-case minimum pulse width slack is -2.636
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.636           -7139.908 CLOCK_50 
    Info (332119):    -0.663              -8.672 SW[8] 
    Info (332119):    -0.651             -19.638 PS2_CLK 
    Info (332119):    -0.538            -107.126 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.538              -8.097 dec_keyboard:inst11|f3 
    Info (332119):    -0.538              -4.806 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -0.538              -4.738 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -0.538              -4.621 clk_div:inst25|clock_10Hz_int 
    Info (332119):    -0.538              -3.927 clk_div:inst25|clock_100KHz 
    Info (332119):    -0.538              -3.874 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -0.538              -3.858 clk_div:inst25|clock_100hz_int 
    Info (332119):    -0.538              -3.376 clk_div:inst25|clock_1Mhz_int 
    Info (332119):    -0.538              -2.825 clk_div:inst25|clock_1KHz 
    Info (332119):    -0.538              -0.816 keyboard:inst14|scan_ready 
    Info (332119):    -0.538              -0.796 keyboard:inst14|ready_set 
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: inst5  from: dataf  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.332
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -4.332             -39.743 dec_keyboard:inst11|f3 
    Info (332119):    -3.208           -3247.507 CLOCK_50 
    Info (332119):    -2.613             -19.445 SW[8] 
    Info (332119):    -2.532             -18.279 PS2_CLK 
    Info (332119):    -2.150            -160.422 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -1.007              -2.161 clk_div:inst25|clock_1Mhz_int 
    Info (332119):    -0.785              -2.585 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -0.709              -2.413 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -0.637              -2.005 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -0.554              -2.127 clk_div:inst25|clock_100hz_int 
    Info (332119):    -0.417              -1.227 clk_div:inst25|clock_1KHz 
    Info (332119):    -0.335              -1.773 clk_div:inst25|clock_10Hz_int 
    Info (332119):    -0.278              -0.660 clk_div:inst25|clock_100KHz 
Info (332146): Worst-case hold slack is -0.282
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.282             -12.576 CLOCK_50 
    Info (332119):    -0.275              -0.680 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.228              -0.387 clk_div:inst25|clock_1KHz 
    Info (332119):    -0.154              -0.154 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -0.124              -0.124 clk_div:inst25|clock_100hz_int 
    Info (332119):    -0.109              -0.109 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -0.103              -0.103 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -0.097              -0.097 clk_div:inst25|clock_1Mhz_int 
    Info (332119):     0.181               0.000 PS2_CLK 
    Info (332119):     0.210               0.000 clk_div:inst25|clock_100KHz 
    Info (332119):     0.252               0.000 dec_keyboard:inst11|f3 
    Info (332119):     0.317               0.000 clk_div:inst25|clock_10Hz_int 
    Info (332119):     0.623               0.000 SW[8] 
Info (332146): Worst-case recovery slack is -0.733
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.733              -0.733 keyboard:inst14|ready_set 
    Info (332119):    -0.326              -0.326 keyboard:inst14|scan_ready 
Info (332146): Worst-case removal slack is -0.138
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.138              -0.138 keyboard:inst14|ready_set 
    Info (332119):     0.065               0.000 keyboard:inst14|scan_ready 
Info (332146): Worst-case minimum pulse width slack is -2.174
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.174           -5855.688 CLOCK_50 
    Info (332119):    -0.746              -8.560 SW[8] 
    Info (332119):    -0.692             -15.529 PS2_CLK 
    Info (332119):    -0.119              -4.786 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.079              -0.235 clk_div:inst25|clock_1KHz 
    Info (332119):     0.014               0.000 clk_div:inst25|clock_1Mhz_int 
    Info (332119):     0.027               0.000 keyboard:inst14|scan_ready 
    Info (332119):     0.043               0.000 dec_keyboard:inst11|f3 
    Info (332119):     0.085               0.000 clk_div:inst25|clock_1Khz_int 
    Info (332119):     0.105               0.000 clk_div:inst25|clock_100KHz 
    Info (332119):     0.109               0.000 keyboard:inst14|ready_set 
    Info (332119):     0.131               0.000 clk_div:inst25|clock_100hz_int 
    Info (332119):     0.138               0.000 clk_div:inst25|clock_10Khz_int 
    Info (332119):     0.148               0.000 clk_div:inst25|clock_100Khz_int 
    Info (332119):     0.151               0.000 clk_div:inst25|clock_10Hz_int 
Info: Analyzing Fast 1100mV 0C Model
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: inst5  from: dataf  to: combout
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.167
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -4.167             -38.227 dec_keyboard:inst11|f3 
    Info (332119):    -2.889           -2816.620 CLOCK_50 
    Info (332119):    -2.452             -14.781 PS2_CLK 
    Info (332119):    -2.152             -16.044 SW[8] 
    Info (332119):    -1.959            -141.925 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.921              -1.911 clk_div:inst25|clock_1Mhz_int 
    Info (332119):    -0.731              -2.249 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -0.671              -2.109 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -0.609              -1.681 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -0.531              -1.883 clk_div:inst25|clock_100hz_int 
    Info (332119):    -0.304              -0.903 clk_div:inst25|clock_1KHz 
    Info (332119):    -0.274              -1.447 clk_div:inst25|clock_10Hz_int 
    Info (332119):    -0.190              -0.439 clk_div:inst25|clock_100KHz 
Info (332146): Worst-case hold slack is -0.366
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.366             -81.938 CLOCK_50 
    Info (332119):    -0.259              -0.964 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.235              -0.499 clk_div:inst25|clock_1KHz 
    Info (332119):    -0.151              -0.151 clk_div:inst25|clock_10Khz_int 
    Info (332119):    -0.123              -0.123 clk_div:inst25|clock_100Khz_int 
    Info (332119):    -0.121              -0.121 clk_div:inst25|clock_100hz_int 
    Info (332119):    -0.115              -0.115 clk_div:inst25|clock_1Khz_int 
    Info (332119):    -0.093              -0.093 clk_div:inst25|clock_1Mhz_int 
    Info (332119):     0.162               0.000 PS2_CLK 
    Info (332119):     0.195               0.000 clk_div:inst25|clock_100KHz 
    Info (332119):     0.233               0.000 dec_keyboard:inst11|f3 
    Info (332119):     0.270               0.000 clk_div:inst25|clock_10Hz_int 
    Info (332119):     0.432               0.000 SW[8] 
Info (332146): Worst-case recovery slack is -0.643
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.643              -0.643 keyboard:inst14|ready_set 
    Info (332119):    -0.244              -0.244 keyboard:inst14|scan_ready 
Info (332146): Worst-case removal slack is -0.164
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.164              -0.164 keyboard:inst14|ready_set 
    Info (332119):     0.005               0.000 keyboard:inst14|scan_ready 
Info (332146): Worst-case minimum pulse width slack is -2.174
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.174           -5959.134 CLOCK_50 
    Info (332119):    -0.785              -9.543 SW[8] 
    Info (332119):    -0.738             -17.221 PS2_CLK 
    Info (332119):    -0.050              -1.207 lpm_dff1:inst1|lpm_ff:lpm_ff_component|dffs[0] 
    Info (332119):    -0.024              -0.070 clk_div:inst25|clock_1KHz 
    Info (332119):     0.045               0.000 clk_div:inst25|clock_1Mhz_int 
    Info (332119):     0.064               0.000 keyboard:inst14|scan_ready 
    Info (332119):     0.066               0.000 dec_keyboard:inst11|f3 
    Info (332119):     0.106               0.000 clk_div:inst25|clock_1Khz_int 
    Info (332119):     0.112               0.000 clk_div:inst25|clock_100KHz 
    Info (332119):     0.129               0.000 keyboard:inst14|ready_set 
    Info (332119):     0.131               0.000 clk_div:inst25|clock_100hz_int 
    Info (332119):     0.142               0.000 clk_div:inst25|clock_100Khz_int 
    Info (332119):     0.147               0.000 clk_div:inst25|clock_10Khz_int 
    Info (332119):     0.149               0.000 clk_div:inst25|clock_10Hz_int 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 1112 megabytes
    Info: Processing ended: Tue Nov  8 13:34:44 2016
    Info: Elapsed time: 00:00:11
    Info: Total CPU time (on all processors): 00:00:14