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Merged main:34ee53c9e390 into amd-gfx:85bfd92dd479
Local branch amd-gfx 85bfd92 Merged main:11819a1031fc into amd-gfx:973615db91c7 Remote branch main 34ee53c [lldb][test] Fix TestCallBuiltinFunction.py
2 parents 85bfd92 + 34ee53c commit 5512cfe

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15 files changed

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15 files changed

+223
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‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1769,12 +1769,9 @@ Value *CodeGenFunction::EmitCheckedArgForBuiltin(const Expr *E,
17691769
}
17701770

17711771
static Value *EmitAbs(CodeGenFunction &CGF, Value *ArgValue, bool HasNSW) {
1772-
// X < 0 ? -X : X
1773-
// TODO: Use phi-node (for better SimplifyCFGPass)
1774-
Value *NegOp = CGF.Builder.CreateNeg(ArgValue, "neg", false, HasNSW);
1775-
Constant *Zero = llvm::Constant::getNullValue(ArgValue->getType());
1776-
Value *CmpResult = CGF.Builder.CreateICmpSLT(ArgValue, Zero, "abscond");
1777-
return CGF.Builder.CreateSelect(CmpResult, NegOp, ArgValue, "abs");
1772+
return CGF.Builder.CreateBinaryIntrinsic(
1773+
Intrinsic::abs, ArgValue,
1774+
ConstantInt::get(CGF.Builder.getInt1Ty(), HasNSW));
17781775
}
17791776

17801777
static Value *EmitOverflowCheckedAbs(CodeGenFunction &CGF, const CallExpr *E,

‎clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,7 @@ typedef __SIZE_TYPE__ size_t;
1717
// BOTH-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1818
// BOTH-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
1919
// BOTH-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
20-
// BOTH-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[TMP0]]
21-
// BOTH-NEXT: [[ABSCOND:%.*]] = icmp slt i32 [[TMP0]], 0
22-
// BOTH-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i32 [[NEG]], i32 [[TMP0]]
20+
// BOTH-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 %0, i1 true)
2321
// BOTH-NEXT: ret i32 [[ABS]]
2422
signed int testabs(signed int a) {
2523
return __abs(a);
@@ -30,19 +28,15 @@ signed int testabs(signed int a) {
3028
// 64BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3129
// 64BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
3230
// 64BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
33-
// 64BIT-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
34-
// 64BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
35-
// 64BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
31+
// 64BIT-NEXT: [[ABS:%.*]] = call i64 @llvm.abs.i64(i64 [[TMP0]], i1 true)
3632
// 64BIT-NEXT: ret i64 [[ABS]]
3733
//
3834
// 32BIT-LABEL: @testlabs(
3935
// 32BIT-NEXT: entry:
4036
// 32BIT-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4137
// 32BIT-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
4238
// 32BIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
43-
// 32BIT-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[TMP0]]
44-
// 32BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i32 [[TMP0]], 0
45-
// 32BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i32 [[NEG]], i32 [[TMP0]]
39+
// 32BIT-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[TMP0]], i1 true)
4640
// 32BIT-NEXT: ret i32 [[ABS]]
4741
//
4842
signed long testlabs(signed long a) {
@@ -54,19 +48,15 @@ signed long testlabs(signed long a) {
5448
// 64BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5549
// 64BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
5650
// 64BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
57-
// 64BIT-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
58-
// 64BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
59-
// 64BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
51+
// 64BIT-NEXT: [[ABS:%.*]] = call i64 @llvm.abs.i64(i64 [[TMP0]], i1 true)
6052
// 64BIT-NEXT: ret i64 [[ABS]]
6153
//
6254
// 32BIT-LABEL: @testllabs(
6355
// 32BIT-NEXT: entry:
6456
// 32BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
6557
// 32BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
6658
// 32BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
67-
// 32BIT-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
68-
// 32BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
69-
// 32BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
59+
// 32BIT-NEXT: [[ABS:%.*]] = call i64 @llvm.abs.i64(i64 [[TMP0]], i1 true)
7060
// 32BIT-NEXT: ret i64 [[ABS]]
7161
//
7262
signed long long testllabs(signed long long a) {

‎clang/test/CodeGen/abs-overflow.c

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,8 @@
66
extern int abs(int x);
77

88
int absi(int x) {
9-
// WRAPV: [[NEG:%.*]] = sub i32 0, [[X:%.*]]
10-
// WRAPV: [[CMP:%.*]] = icmp slt i32 [[X]], 0
11-
// WRAPV: [[SEL:%.*]] = select i1 [[CMP]], i32 [[NEG]], i32 [[X]]
9+
// WRAPV: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 %0, i1 false)
10+
// WRAPV-NEXT: ret i32 [[ABS]]
1211
//
1312
// BOTH-TRAP: [[NEG:%.*]] = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 0, i32 [[X:%.*]])
1413
// BOTH-TRAP: [[NEGV:%.*]] = extractvalue { i32, i1 } [[NEG]], 0
@@ -26,9 +25,8 @@ int absi(int x) {
2625
}
2726

2827
int babsi(int x) {
29-
// WRAPV: [[NEG:%.*]] = sub i32 0, [[X:%.*]]
30-
// WRAPV: [[CMP:%.*]] = icmp slt i32 [[X]], 0
31-
// WRAPV: [[SEL:%.*]] = select i1 [[CMP]], i32 [[NEG]], i32 [[X]]
28+
// WRAPV: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 %0, i1 false)
29+
// WRAPV-NEXT: ret i32 [[ABS]]
3230
//
3331
// BOTH-TRAP: [[NEG:%.*]] = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 0, i32 [[X:%.*]])
3432
// BOTH-TRAP: [[NEGV:%.*]] = extractvalue { i32, i1 } [[NEG]], 0

‎clang/test/CodeGen/builtin-abs.c

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,27 +2,24 @@
22

33
int absi(int x) {
44
// CHECK-LABEL: @absi(
5-
// CHECK: [[NEG:%.*]] = sub nsw i32 0, [[X:%.*]]
6-
// CHECK: [[CMP:%.*]] = icmp slt i32 [[X]], 0
7-
// CHECK: [[SEL:%.*]] = select i1 [[CMP]], i32 [[NEG]], i32 [[X]]
5+
// CHECK: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 %0, i1 true)
6+
// CHECK-NEXT: ret i32 [[ABS]]
87
//
98
return __builtin_abs(x);
109
}
1110

1211
long absl(long x) {
1312
// CHECK-LABEL: @absl(
14-
// CHECK: [[NEG:%.*]] = sub nsw i64 0, [[X:%.*]]
15-
// CHECK: [[CMP:%.*]] = icmp slt i64 [[X]], 0
16-
// CHECK: [[SEL:%.*]] = select i1 [[CMP]], i64 [[NEG]], i64 [[X]]
13+
// CHECK: [[ABS:%.*]] = call i64 @llvm.abs.i64(i64 %0, i1 true)
14+
// CHECK-NEXT: ret i64 [[ABS]]
1715
//
1816
return __builtin_labs(x);
1917
}
2018

2119
long long absll(long long x) {
2220
// CHECK-LABEL: @absll(
23-
// CHECK: [[NEG:%.*]] = sub nsw i64 0, [[X:%.*]]
24-
// CHECK: [[CMP:%.*]] = icmp slt i64 [[X]], 0
25-
// CHECK: [[SEL:%.*]] = select i1 [[CMP]], i64 [[NEG]], i64 [[X]]
21+
// CHECK: [[ABS:%.*]] = call i64 @llvm.abs.i64(i64 %0, i1 true)
22+
// CHECK-NEXT: ret i64 [[ABS]]
2623
//
2724
return __builtin_llabs(x);
2825
}

‎clang/test/CodeGenCXX/builtins.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,8 @@ long __builtin_abs(long); // #2
5353
extern "C" int __builtin_abs(int); // #3
5454

5555
int x = __builtin_abs(-2);
56-
// CHECK: store i32 2, ptr @x, align 4
56+
// CHECK: [[X:%.+]] = call i32 @llvm.abs.i32(i32 -2, i1 true)
57+
// CHECK-NEXT: store i32 [[X]], ptr @x, align 4
5758

5859
long y = __builtin_abs(-2l);
5960
// CHECK: [[Y:%.+]] = call noundef i64 @_Z13__builtin_absl(i64 noundef -2)

‎clang/tools/clang-repl/ClangRepl.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,14 @@
2424
#include "llvm/Support/TargetSelect.h"
2525
#include <optional>
2626

27+
// Disable LSan for this test.
28+
// FIXME: Re-enable once we can assume GCC 13.2 or higher.
29+
// https://llvm.org/github.com/llvm/llvm-project/issues/67586.
30+
#if LLVM_ADDRESS_SANITIZER_BUILD || LLVM_HWADDRESS_SANITIZER_BUILD
31+
#include <sanitizer/lsan_interface.h>
32+
LLVM_ATTRIBUTE_USED int __lsan_is_turned_off() { return 1; }
33+
#endif
34+
2735
static llvm::cl::opt<bool> CudaEnabled("cuda", llvm::cl::Hidden);
2836
static llvm::cl::opt<std::string> CudaPath("cuda-path", llvm::cl::Hidden);
2937
static llvm::cl::opt<std::string> OffloadArch("offload-arch", llvm::cl::Hidden);

‎lldb/test/API/commands/expression/call-function/TestCallBuiltinFunction.py

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,4 +23,3 @@ def test(self):
2323
"__builtin_isnormal(0.0f)", result_type="int", result_value="0"
2424
)
2525
self.expect_expr("__builtin_constant_p(1)", result_type="int", result_value="1")
26-
self.expect_expr("__builtin_abs(-14)", result_type="int", result_value="14")

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 476166
19+
#define LLVM_MAIN_REVISION 476172
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/lib/CodeGen/MachineLICM.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -601,7 +601,7 @@ void MachineLICMBase::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
601601
for (MachineOperand &MO : MI.all_uses()) {
602602
if (!MO.getReg())
603603
continue;
604-
if (TRI->isSuperRegisterEq(Reg, MO.getReg()))
604+
if (TRI->regsOverlap(Reg, MO.getReg()))
605605
MO.setIsKill(false);
606606
}
607607
}

‎llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ class PPCAIXAsmPrinter : public PPCAsmPrinter {
280280

281281
void emitFunctionBodyEnd() override;
282282

283-
void emitPGORefs();
283+
void emitPGORefs(Module &M);
284284

285285
void emitEndOfAsmFile(Module &) override;
286286

@@ -2652,10 +2652,28 @@ void PPCAIXAsmPrinter::emitFunctionEntryLabel() {
26522652
getObjFileLowering().getFunctionEntryPointSymbol(Alias, TM));
26532653
}
26542654

2655-
void PPCAIXAsmPrinter::emitPGORefs() {
2656-
if (OutContext.hasXCOFFSection(
2655+
void PPCAIXAsmPrinter::emitPGORefs(Module &M) {
2656+
if (!OutContext.hasXCOFFSection(
26572657
"__llvm_prf_cnts",
2658-
XCOFF::CsectProperties(XCOFF::XMC_RW, XCOFF::XTY_SD))) {
2658+
XCOFF::CsectProperties(XCOFF::XMC_RW, XCOFF::XTY_SD)))
2659+
return;
2660+
2661+
// When inside a csect `foo`, a .ref directive referring to a csect `bar`
2662+
// translates into a relocation entry from `foo` to` bar`. The referring
2663+
// csect, `foo`, is identified by its address. If multiple csects have the
2664+
// same address (because one or more of them are zero-length), the referring
2665+
// csect cannot be determined. Hence, we don't generate the .ref directives
2666+
// if `__llvm_prf_cnts` is an empty section.
2667+
bool HasNonZeroLengthPrfCntsSection = false;
2668+
const DataLayout &DL = M.getDataLayout();
2669+
for (GlobalVariable &GV : M.globals())
2670+
if (GV.hasSection() && GV.getSection().equals("__llvm_prf_cnts") &&
2671+
DL.getTypeAllocSize(GV.getValueType()) > 0) {
2672+
HasNonZeroLengthPrfCntsSection = true;
2673+
break;
2674+
}
2675+
2676+
if (HasNonZeroLengthPrfCntsSection) {
26592677
MCSection *CntsSection = OutContext.getXCOFFSection(
26602678
"__llvm_prf_cnts", SectionKind::getData(),
26612679
XCOFF::CsectProperties(XCOFF::XMC_RW, XCOFF::XTY_SD),
@@ -2689,7 +2707,7 @@ void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) {
26892707
if (M.empty() && TOCDataGlobalVars.empty())
26902708
return;
26912709

2692-
emitPGORefs();
2710+
emitPGORefs(M);
26932711

26942712
// Switch to section to emit TOC base.
26952713
OutStreamer->switchSection(getObjFileLowering().getTOCBaseSection());

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -257,10 +257,27 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
257257
assert(ActiveFeatures[RISCV::Feature64Bit] &&
258258
"Expected RV32 to only need 2 instructions");
259259

260+
// If the lower 13 bits are something like 0x17ff, try to add 1 to change the
261+
// lower 13 bits to 0x1800. We can restore this with an ADDI of -1 at the end
262+
// of the sequence. Call generateInstSeqImpl on the new constant which may
263+
// subtract 0xfffffffffffff800 to create another ADDI. This will leave a
264+
// constant with more than 12 trailing zeros for the next recursive step.
265+
if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
266+
int64_t Imm12 = -(0x800 - (Val & 0xfff));
267+
int64_t AdjustedVal = Val - Imm12;
268+
RISCVMatInt::InstSeq TmpSeq;
269+
generateInstSeqImpl(AdjustedVal, ActiveFeatures, TmpSeq);
270+
271+
// Keep the new sequence if it is an improvement.
272+
if ((TmpSeq.size() + 1) < Res.size()) {
273+
TmpSeq.emplace_back(RISCV::ADDI, Imm12);
274+
Res = TmpSeq;
275+
}
276+
}
277+
260278
// If the constant is positive we might be able to generate a shifted constant
261279
// with no leading zeros and use a final SRLI to restore them.
262-
if (Val > 0) {
263-
assert(Res.size() > 2 && "Expected longer sequence");
280+
if (Val > 0 && Res.size() > 2) {
264281
generateInstSeqLeadingZeros(Val, ActiveFeatures, Res);
265282
}
266283

‎llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir

Lines changed: 35 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,44 @@ body: |
1717
bb.1:
1818
; CHECK-LABEL: bb.1:
1919
; CHECK-NOT: $x2 = LDRXui %stack.0, 0
20+
; CHECK: $x0 = ADDXrr $x0, $x2
2021
liveins: $x0
2122
DBG_VALUE %stack.0, 0
2223
$x2 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
23-
$x0 = ADDXrr $x0, $x2
24-
$xzr = SUBSXri $x0, 1, 0, implicit-def $nzcv
24+
$x0 = ADDXrr $x0, killed $x2
25+
$xzr = SUBSXri killed $x0, 1, 0, implicit-def $nzcv
26+
Bcc 11, %bb.1, implicit $nzcv
27+
B %bb.2
28+
29+
bb.2:
30+
liveins: $x0
31+
%0 = COPY $x0
32+
%0 = COPY $x0 ; Force isSSA = false.
33+
...
34+
---
35+
name: test2
36+
tracksRegLiveness: true
37+
registers:
38+
- { id: 0, class: gpr64 }
39+
stack:
40+
- { id: 0, size: 8, type: spill-slot }
41+
body: |
42+
bb.0:
43+
; CHECK-LABEL: name: test2
44+
; CHECK-LABEL: bb.0:
45+
; CHECK: $x2 = LDRXui %stack.0, 0
46+
liveins: $x0, $x1, $x2
47+
B %bb.1
48+
49+
bb.1:
50+
; CHECK-LABEL: bb.1:
51+
; CHECK-NOT: $x2 = LDRXui %stack.0, 0
52+
; CHECK: $w0 = ADDWrr $w0, $w2
53+
liveins: $x0
54+
DBG_VALUE %stack.0, 0
55+
$x2 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
56+
$w0 = ADDWrr $w0, killed $w2
57+
$wzr = SUBSWri killed $w0, 1, 0, implicit-def $nzcv
2558
Bcc 11, %bb.1, implicit $nzcv
2659
B %bb.2
2760

‎llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,24 @@
1818
; RUN: -xcoff-traceback-table=false --filetype=obj < %t/with-vnds.ll -o %t/with-vnds.o
1919
; RUN: llvm-objdump %t/with-vnds.o -tr | FileCheck %s --check-prefix=WITHVNDS-OBJ
2020

21+
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
22+
; RUN: -xcoff-traceback-table=false < %t/zero-size-cnts-section.ll | FileCheck %s --check-prefixes=ZERO-SIZE-CNTS
23+
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
24+
; RUN: -xcoff-traceback-table=false --filetype=obj < %t/zero-size-cnts-section.ll -o %t/zero-size-cnts-section.o
25+
; RUN: llvm-objdump %t/zero-size-cnts-section.o -tr | FileCheck %s --check-prefix=ZERO-SIZE-CNTS-OBJ
26+
27+
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
28+
; RUN: -xcoff-traceback-table=false < %t/zero-size-other-section.ll | FileCheck %s --check-prefixes=ZERO-SIZE-OTHER
29+
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
30+
; RUN: -xcoff-traceback-table=false < %t/zero-size-other-section.ll | FileCheck %s --check-prefixes=ZERO-SIZE-OTHER
31+
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
32+
; RUN: -xcoff-traceback-table=false --filetype=obj < %t/zero-size-other-section.ll -o %t/zero-size-other-section.o
33+
; RUN: llvm-objdump %t/zero-size-other-section.o -tr | FileCheck %s --check-prefix=ZERO-SIZE-OTHER-OBJ
34+
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
35+
; RUN: -xcoff-traceback-table=false --filetype=obj < %t/zero-size-other-section.ll -o %t/zero-size-other-section.o
36+
; RUN: llvm-objdump %t/zero-size-other-section.o -tr | FileCheck %s --check-prefix=ZERO-SIZE-OTHER-OBJ
37+
38+
2139
;--- no-ref.ll
2240
; The absence of a __llvm_prf_cnts section should stop generating the .refs.
2341
;
@@ -120,3 +138,60 @@ entry:
120138
; WITHVNDS-OBJ-NEXT: 00000000 R_REF __llvm_prf_vnds
121139
; WITHVNDS-OBJ-NEXT: 00000100 R_POS .main
122140
; WITHVNDS-OBJ-NEXT: 00000104 R_POS TOC
141+
142+
;--- zero-size-cnts-section.ll
143+
; If __llvm_prf_cnts is of zero size, do not generate the .ref directive.
144+
; The size of the other sections does not matter.
145+
146+
@dummy_cnts = private global [0 x i32] zeroinitializer, section "__llvm_prf_cnts", align 4
147+
@dummy_data = private global [1 x i64] zeroinitializer, section "__llvm_prf_data", align 8
148+
@dummy_name = private constant [0 x i32] zeroinitializer, section "__llvm_prf_names", align 4
149+
150+
@llvm.used = appending global [3 x ptr]
151+
[ptr @dummy_cnts,
152+
ptr @dummy_data,
153+
ptr @dummy_name], section "llvm.metadata"
154+
155+
define i32 @main() #0 {
156+
entry:
157+
ret i32 1
158+
}
159+
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; ZERO-SIZE-CNTS-NOT: .ref __llvm_prf_data[RW]
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; ZERO-SIZE-CNTS-NOT: .ref __llvm_prf_names[RO]
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; ZERO-SIZE-CNTS-NOT: .ref __llvm_prf_vnds
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; ZERO-SIZE-CNTS-OBJ-NOT: R_REF __llvm_prf_data
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; ZERO-SIZE-CNTS-OBJ-NOT: R_REF __llvm_prf_names
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; ZERO-SIZE-CNTS-OBJ-NOT: R_REF __llvm_prf_vnds
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;--- zero-size-other-section.ll
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; If __llvm_prf_cnts is of non-zero size, generate the .ref directive even if other sections
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; are zero-sized;
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@__profc_main = private global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", align 8
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@__profd_main = private global [0 x i64] zeroinitializer, section "__llvm_prf_data", align 8
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@__llvm_prf_nm = private constant [0 x i8] zeroinitializer, section "__llvm_prf_names", align 1
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@__llvm_prf_vnodes = private global [0 x { i64, i64, ptr }] zeroinitializer, section "__llvm_prf_vnds"
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@llvm.used = appending global [4 x ptr]
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[ptr @__profc_main,
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ptr @__profd_main,
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ptr @__llvm_prf_nm,
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ptr @__llvm_prf_vnodes], section "llvm.metadata"
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define i32 @main() #0 {
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entry:
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ret i32 1
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}
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; ZERO-SIZE-OTHER: .csect __llvm_prf_cnts[RW],3
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; ZERO-SIZE-OTHER: .csect __llvm_prf_cnts[RW],3
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; ZERO-SIZE-OTHER-NEXT: .ref __llvm_prf_data[RW]
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; ZERO-SIZE-OTHER-NEXT: .ref __llvm_prf_names[RO]
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; ZERO-SIZE-OTHER-NEXT: .ref __llvm_prf_vnds[RW]
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; ZERO-SIZE-OTHER-OBJ: R_REF __llvm_prf_data
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; ZERO-SIZE-OTHER-OBJ-NEXT: R_REF __llvm_prf_names
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; ZERO-SIZE-OTHER-OBJ-NEXT: R_REF __llvm_prf_vnds
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