Merged main:f7b09516e466 into amd-gfx:e631f76db5ef

Local branch amd-gfx e631f76 Merged main:beb89e7fc002 into amd-gfx:71a26b8a604d
Remote branch main f7b0951 [LLVM] Add missing verifier checks for convergence control

Author: SC llvm team

clang/lib/CodeGen/CGBlocks.cpp

@@ -66,28 +66,6 @@ static llvm::Constant *buildDisposeHelper(CodeGenModule &CGM,
 
 namespace {
 
-/// Represents a captured entity that requires extra operations in order for
-/// this entity to be copied or destroyed correctly.
-struct BlockCaptureManagedEntity {
-  BlockCaptureEntityKind CopyKind, DisposeKind;
-  BlockFieldFlags CopyFlags, DisposeFlags;
-  const BlockDecl::Capture *CI;
-  const CGBlockInfo::Capture *Capture;
-
-  BlockCaptureManagedEntity(BlockCaptureEntityKind CopyType,
-                            BlockCaptureEntityKind DisposeType,
-                            BlockFieldFlags CopyFlags,
-                            BlockFieldFlags DisposeFlags,
-                            const BlockDecl::Capture &CI,
-                            const CGBlockInfo::Capture &Capture)
-      : CopyKind(CopyType), DisposeKind(DisposeType), CopyFlags(CopyFlags),
-        DisposeFlags(DisposeFlags), CI(&CI), Capture(&Capture) {}
-
-  bool operator<(const BlockCaptureManagedEntity &Other) const {
-    return Capture->getOffset() < Other.Capture->getOffset();
-  }
-};
-
 enum class CaptureStrKind {
   // String for the copy helper.
   CopyHelper,

llvm/include/llvm/CodeGen/LiveInterval.h

@@ -326,11 +326,11 @@ namespace llvm {
       return VNI && VNI->id < getNumValNums() && VNI == getValNumInfo(VNI->id);
     }
 
-    /// getNextValue - Create a new value number and return it.  MIIdx specifies
-    /// the instruction that defines the value number.
-    VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator) {
+    /// getNextValue - Create a new value number and return it.
+    /// @p Def is the index of instruction that defines the value number.
+    VNInfo *getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator) {
       VNInfo *VNI =
-        new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def);
+        new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), Def);
       valnos.push_back(VNI);
       return VNI;
     }

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 469633
+#define LLVM_MAIN_REVISION 469640
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/IR/Verifier.cpp

@@ -2535,6 +2535,23 @@ void Verifier::verifySiblingFuncletUnwinds() {
   }
 }
 
+static bool isConvergenceControlIntrinsic(const CallBase &Call) {
+  switch (Call.getIntrinsicID()) {
+  case Intrinsic::experimental_convergence_anchor:
+  case Intrinsic::experimental_convergence_entry:
+  case Intrinsic::experimental_convergence_loop:
+    return true;
+  default:
+    return false;
+  }
+}
+
+static bool isControlledConvergent(const CallBase &Call) {
+  if (Call.countOperandBundlesOfType(LLVMContext::OB_convergencectrl))
+    return true;
+  return isConvergenceControlIntrinsic(Call);
+}
+
 void Verifier::verifyConvergenceControl(Function &F) {
   DenseMap<BasicBlock *, SmallVector<CallBase *, 8>> LiveTokenMap;
   DenseMap<const Cycle *, const CallBase *> CycleHearts;
@@ -2552,10 +2569,10 @@ void Verifier::verifyConvergenceControl(Function &F) {
 
     Value *Token = Bundle.Inputs[0].get();
     auto *Def = dyn_cast<CallBase>(Token);
-    Check(Def != nullptr,
-          "Convergence control tokens can only be produced by call "
-          "instructions.",
-          Token);
+    Check(Def && isConvergenceControlIntrinsic(*Def),
+          "Convergence control tokens can only be produced by calls to the "
+          "convergence control intrinsics.",
+          Token, CB);
 
     Check(llvm::is_contained(LiveTokens, Token),
           "Convergence region is not well-nested.", Token, CB);
@@ -2615,6 +2632,9 @@ void Verifier::verifyConvergenceControl(Function &F) {
       if (!CB)
         continue;
 
+      Check(CB->countOperandBundlesOfType(LLVMContext::OB_convergencectrl) <= 1,
+            "The 'convergencetrl' bundle can occur at most once on a call", CB);
+
       auto Bundle = CB->getOperandBundle(LLVMContext::OB_convergencectrl);
       if (Bundle)
         checkBundle(*Bundle, CB, LiveTokens);
@@ -3375,20 +3395,6 @@ void Verifier::visitPHINode(PHINode &PN) {
   visitInstruction(PN);
 }
 
-static bool isControlledConvergent(const CallBase &Call) {
-  if (Call.getOperandBundle(LLVMContext::OB_convergencectrl))
-    return true;
-  if (const auto *F = dyn_cast<Function>(Call.getCalledOperand())) {
-    switch (F->getIntrinsicID()) {
-    case Intrinsic::experimental_convergence_anchor:
-    case Intrinsic::experimental_convergence_entry:
-    case Intrinsic::experimental_convergence_loop:
-      return true;
-    }
-  }
-  return false;
-}
-
 void Verifier::visitCallBase(CallBase &Call) {
   Check(Call.getCalledOperand()->getType()->isPointerTy(),
         "Called function must be a pointer!", Call);

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td

@@ -141,6 +141,16 @@ defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;
 
 defm FRECIP   : FT_MOV<0b011001, "frecip">;
 
+// multiplication
+let Predicates = [HasFPUv2_SF] in {
+  def : Pat<(f32 (fmul (fneg sFPR32Op:$vrx), sFPR32Op:$vry)),
+            (FNMUL_S sFPR32Op:$vrx, sFPR32Op:$vry)>;
+}
+let Predicates = [HasFPUv2_DF] in {
+  def : Pat<(f64 (fmul (fneg sFPR64Op:$vrx), sFPR64Op:$vry)),
+            (FNMUL_D sFPR64Op:$vrx, sFPR64Op:$vry)>;
+}
+
 //fmov, fmtvr, fmfvr
 defm FMOV : FT_MOV<0b000100, "fmov">;
 def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),

llvm/lib/Target/CSKY/CSKYInstrInfoF2.td

@@ -208,6 +208,16 @@ defm f2FNMULS : F2_XYZZ_T<0b010101, "fnmuls",
 defm f2FNMUL : F2_XYZ_T<0b010001, "fnmul",
   BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
 
+// multiplication
+let Predicates = [HasFPUv3_SF] in {
+  def : Pat<(f32 (fmul (fneg FPR32Op:$vrx), FPR32Op:$vry)),
+            (f2FNMUL_S FPR32Op:$vrx, FPR32Op:$vry)>;
+}
+let Predicates = [HasFPUv3_DF] in {
+  def : Pat<(f64 (fmul (fneg FPR64Op:$vrx), FPR64Op:$vry)),
+            (f2FNMUL_D FPR64Op:$vrx, FPR64Op:$vry)>;
+}
+
 // fcvt
 def f2FFTOS32_S  : F2_XZ_P<0b01000, 0b011011, "fftoi.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
 def f2FFTOU32_S  : F2_XZ_P<0b01000, 0b011010, "fftoi.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;

llvm/test/CodeGen/CSKY/fpu/base-d.ll

@@ -27,7 +27,7 @@ define double @FADD_DOUBLE_I(double %x) {
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
+; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI1_0:
 ; CHECK-DF-NEXT:    .quad 0xbff0000000000000 # double -1
 ;
@@ -38,7 +38,7 @@ define double @FADD_DOUBLE_I(double %x) {
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
 ; CHECK-DF2-NEXT:  .LCPI1_0:
 ; CHECK-DF2-NEXT:    .quad 0xbff0000000000000 # double -1
 entry:
@@ -72,7 +72,7 @@ define double @FSUB_DOUBLE_I(double %x) {
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
+; CHECK-DF-NEXT:    .p2align 2, 0x0
 ; CHECK-DF-NEXT:  .LCPI3_0:
 ; CHECK-DF-NEXT:    .quad 0x3ff0000000000000 # double 1
 ;
@@ -83,7 +83,7 @@ define double @FSUB_DOUBLE_I(double %x) {
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
 ; CHECK-DF2-NEXT:  .LCPI3_0:
 ; CHECK-DF2-NEXT:    .quad 0x3ff0000000000000 # double 1
 
@@ -108,29 +108,62 @@ entry:
   ret double %fmul
 }
 
+define double @FNMUL_DOUBLE_a(double %x, double %y) {
+;
+; CHECK-DF-LABEL: FNMUL_DOUBLE_a:
+; CHECK-DF:       # %bb.0: # %entry
+; CHECK-DF-NEXT:    fnmuld vr0, vr1, vr0
+; CHECK-DF-NEXT:    rts16
+;
+; CHECK-DF2-LABEL: FNMUL_DOUBLE_a:
+; CHECK-DF2:       # %bb.0: # %entry
+; CHECK-DF2-NEXT:    fnmul.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT:    rts16
+entry:
+  %z = fneg double %y
+  %fnmul = fmul double %z, %x
+  ret double %fnmul
+}
+
+define double @FNMUL_DOUBLE_b(double %x, double %y) {
+; CHECK-DF-LABEL: FNMUL_DOUBLE_b:
+; CHECK-DF:       # %bb.0: # %entry
+; CHECK-DF-NEXT:    fnmuld vr0, vr0, vr1
+; CHECK-DF-NEXT:    rts16
+;
+; CHECK-DF2-LABEL: FNMUL_DOUBLE_b:
+; CHECK-DF2:       # %bb.0: # %entry
+; CHECK-DF2-NEXT:    fnmul.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT:    rts16
+entry:
+  %z = fneg double %x
+  %fnmul = fmul double %y, %z
+  ret double %fnmul
+}
+
 define double @FMUL_DOUBLE_I(double %x) {
 ;
 ; CHECK-DF-LABEL: FMUL_DOUBLE_I:
 ; CHECK-DF:       # %bb.0: # %entry
-; CHECK-DF-NEXT:    grs32 a0, .LCPI5_0
+; CHECK-DF-NEXT:    grs32 a0, .LCPI7_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fmuld vr0, vr0, vr1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
-; CHECK-DF-NEXT:  .LCPI5_0:
+; CHECK-DF-NEXT:    .p2align 2, 0x0
+; CHECK-DF-NEXT:  .LCPI7_0:
 ; CHECK-DF-NEXT:    .quad 0xc01c000000000000 # double -7
 ;
 ; CHECK-DF2-LABEL: FMUL_DOUBLE_I:
 ; CHECK-DF2:       # %bb.0: # %entry
-; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI5_0]
+; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI7_0]
 ; CHECK-DF2-NEXT:    fmul.64 vr0, vr0, vr1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
-; CHECK-DF2-NEXT:  .LCPI5_0:
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
+; CHECK-DF2-NEXT:  .LCPI7_0:
 ; CHECK-DF2-NEXT:    .quad 0xc01c000000000000 # double -7
 entry:
   %fmul = fmul  double %x, -7.0
@@ -159,25 +192,25 @@ define double @FDIV_DOUBLE_I(double %x) {
 ;
 ; CHECK-DF-LABEL: FDIV_DOUBLE_I:
 ; CHECK-DF:       # %bb.0: # %entry
-; CHECK-DF-NEXT:    grs32 a0, .LCPI7_0
+; CHECK-DF-NEXT:    grs32 a0, .LCPI9_0
 ; CHECK-DF-NEXT:    fldd vr1, (a0, 0)
 ; CHECK-DF-NEXT:    fdivd vr0, vr0, vr1
 ; CHECK-DF-NEXT:    rts16
 ; CHECK-DF-NEXT:    .p2align 1
 ; CHECK-DF-NEXT:  # %bb.1:
-; CHECK-DF-NEXT:    .p2align 2
-; CHECK-DF-NEXT:  .LCPI7_0:
+; CHECK-DF-NEXT:    .p2align 2, 0x0
+; CHECK-DF-NEXT:  .LCPI9_0:
 ; CHECK-DF-NEXT:    .quad 0xc01c000000000000 # double -7
 ;
 ; CHECK-DF2-LABEL: FDIV_DOUBLE_I:
 ; CHECK-DF2:       # %bb.0: # %entry
-; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI7_0]
+; CHECK-DF2-NEXT:    flrw.64 vr1, [.LCPI9_0]
 ; CHECK-DF2-NEXT:    fdiv.64 vr0, vr0, vr1
 ; CHECK-DF2-NEXT:    rts16
 ; CHECK-DF2-NEXT:    .p2align 1
 ; CHECK-DF2-NEXT:  # %bb.1:
-; CHECK-DF2-NEXT:    .p2align 2
-; CHECK-DF2-NEXT:  .LCPI7_0:
+; CHECK-DF2-NEXT:    .p2align 2, 0x0
+; CHECK-DF2-NEXT:  .LCPI9_0:
 ; CHECK-DF2-NEXT:    .quad 0xc01c000000000000 # double -7
 entry:
   %fdiv = fdiv  double %x, -7.0

llvm/test/CodeGen/CSKY/fpu/base-f.ll

@@ -144,6 +144,40 @@ entry:
   ret float %fmul
 }
 
+define float @fnmulRR_a(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fnmulRR_a:
+; CHECK-SF:       # %bb.0: # %entry
+; CHECK-SF-NEXT:    fnmuls vr0, vr1, vr0
+; CHECK-SF-NEXT:    rts16
+;
+; CHECK-SF2-LABEL: fnmulRR_a:
+; CHECK-SF2:       # %bb.0: # %entry
+; CHECK-SF2-NEXT:    fnmul.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT:    rts16
+
+entry:
+  %z = fneg float %y
+  %fnmul = fmul float %z, %x
+  ret float %fnmul
+}
+
+define float @fnmulRR_b(float %x, float %y) {
+; CHECK-SF-LABEL: fnmulRR_b:
+; CHECK-SF:       # %bb.0: # %entry
+; CHECK-SF-NEXT:    fnmuls vr0, vr0, vr1
+; CHECK-SF-NEXT:    rts16
+;
+; CHECK-SF2-LABEL: fnmulRR_b:
+; CHECK-SF2:       # %bb.0: # %entry
+; CHECK-SF2-NEXT:    fnmul.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT:    rts16
+entry:
+  %z = fneg float %x
+  %fnmul = fmul float %y, %z
+  ret float %fnmul
+}
+
 define float @fmulRI(float %x) {
 ;
 ; CHECK-SF-LABEL: fmulRI:

llvm/test/CodeGen/RISCV/rv64xtheadbb.ll

@@ -415,10 +415,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
 ; RV64XTHEADBB-NEXT:  .LBB6_2:
 ; RV64XTHEADBB-NEXT:    li a0, 32
 ; RV64XTHEADBB-NEXT:    ret
-; RV64ZBB-LABEL: cttz_i32:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    ctzw a0, a0
-; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
   ret i32 %1
 }

llvm/test/Verifier/convergencectrl-invalid.ll

@@ -1,5 +1,14 @@
 ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
 
+; CHECK: Convergence control tokens can only be produced by calls to the convergence control intrinsics.
+; CHECK-NEXT:  %t04_tok1 = call token @produce_token()
+; CHECK-NEXT:  call void @f() [ "convergencectrl"(token %t04_tok1) ]
+define void @wrong_token() {
+  %t04_tok1 = call token @produce_token()
+  call void @f() [ "convergencectrl"(token %t04_tok1) ]
+  ret void
+}
+
 ; CHECK: Expected convergent attribute on a controlled convergent call.
 ; CHECK-NEXT  call void @g(){{.*}}%t05_tok1
 define void @missing.attribute() {
@@ -8,6 +17,24 @@ define void @missing.attribute() {
   ret void
 }
 
+; CHECK: The 'convergencectrl' bundle requires exactly one token use.
+; CHECK-NEXT:  call void @g()
+define void @multiple_tokens() {
+  %t06_tok1 = call token @llvm.experimental.convergence.anchor()
+  %t06_tok2 = call token @llvm.experimental.convergence.anchor()
+  call void @g() [ "convergencectrl"(token %t06_tok2, token %t06_tok1) ]
+  ret void
+}
+
+; CHECK: The 'convergencetrl' bundle can occur at most once on a call
+; CHECK-NEXT:  call void @g()
+define void @multiple_bundles() {
+  %t07_tok1 = call token @llvm.experimental.convergence.anchor()
+  %t07_tok2 = call token @llvm.experimental.convergence.anchor()
+  call void @g() [ "convergencectrl"(token %t07_tok2), "convergencectrl"(token %t07_tok1) ]
+  ret void
+}
+
 ; CHECK: Cannot mix controlled and uncontrolled convergence in the same function
 ; CHECK-NEXT  call void @f()
 define void @mixed1() {
@@ -217,6 +244,8 @@ F:
   ret void
 }
 
+declare token @produce_token()
+
 declare void @f() convergent
 declare void @g()