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lms_ctr.qsys
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lms_ctr.qsys
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element Av_FIFO_Int_0
{
datum _sortIndex
{
value = "8";
type = "int";
}
}
element Av_FIFO_Int_0.avalon_slave_0
{
datum baseAddress
{
value = "69824";
type = "String";
}
}
element clk_main
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element i2c_opencores_0
{
datum _sortIndex
{
value = "10";
type = "int";
}
}
element i2c_opencores_0.avalon_slave_0
{
datum baseAddress
{
value = "69760";
type = "String";
}
}
element leds
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element leds.s1
{
datum baseAddress
{
value = "69792";
type = "String";
}
}
element lms_ctr
{
datum _originalDeviceFamily
{
value = "Cyclone IV GX";
type = "String";
}
}
element lms_ctr
{
datum _originalDeviceFamily
{
value = "Cyclone IV GX";
type = "String";
}
}
element lms_ctr
{
datum _originalDeviceFamily
{
value = "Cyclone IV GX";
type = "String";
}
}
element lms_ctr_gpio
{
datum _sortIndex
{
value = "7";
type = "int";
}
}
element lms_ctr_gpio.s1
{
datum baseAddress
{
value = "69728";
type = "String";
}
}
element nios2_cpu
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element nios2_cpu.debug_mem_slave
{
datum baseAddress
{
value = "67584";
type = "String";
}
}
element nios_custom_instr_bitswap_0
{
datum _sortIndex
{
value = "9";
type = "int";
}
}
element oc_mem
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element oc_mem.s1
{
datum baseAddress
{
value = "32768";
type = "String";
}
}
element spi_1_ADF
{
datum _sortIndex
{
value = "12";
type = "int";
}
}
element spi_1_ADF.spi_control_port
{
datum baseAddress
{
value = "69632";
type = "String";
}
}
element spi_1_DAC
{
datum _sortIndex
{
value = "11";
type = "int";
}
}
element spi_1_DAC.spi_control_port
{
datum baseAddress
{
value = "69664";
type = "String";
}
}
element spi_lms
{
datum _sortIndex
{
value = "6";
type = "int";
}
}
element spi_lms.spi_control_port
{
datum baseAddress
{
value = "69696";
type = "String";
}
}
element switch
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element switch.s1
{
datum baseAddress
{
value = "69808";
type = "String";
}
}
element sysid_qsys_0
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element sysid_qsys_0.control_slave
{
datum baseAddress
{
value = "69840";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE40F23C8" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="lms7_trx.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_main.clk_in" type="clock" dir="end" />
<interface
name="exfifo_if_d"
internal="Av_FIFO_Int_0.cnd_if_d"
type="conduit"
dir="end" />
<interface
name="exfifo_if_rd"
internal="Av_FIFO_Int_0.cnd_if_rd"
type="conduit"
dir="end" />
<interface
name="exfifo_if_rdempty"
internal="Av_FIFO_Int_0.cnd_if_rdempty"
type="conduit"
dir="end" />
<interface
name="exfifo_of_d"
internal="Av_FIFO_Int_0.cnd_of_d"
type="conduit"
dir="end" />
<interface
name="exfifo_of_wr"
internal="Av_FIFO_Int_0.cnd_of_wr"
type="conduit"
dir="end" />
<interface
name="exfifo_of_wrfull"
internal="Av_FIFO_Int_0.cnd_of_wrfull"
type="conduit"
dir="end" />
<interface
name="exfifo_rst"
internal="Av_FIFO_Int_0.cnd_fifo_rst"
type="conduit"
dir="end" />
<interface name="extfifo" internal="Av_FIFO_Int_0.conduit_end_0" />
<interface
name="leds_external_connection"
internal="leds.external_connection"
type="conduit"
dir="end" />
<interface
name="lms_ctr_gpio_external_connection"
internal="lms_ctr_gpio.external_connection"
type="conduit"
dir="end" />
<interface
name="scl_exp"
internal="i2c_opencores_0.export_scl"
type="conduit"
dir="end" />
<interface
name="sda_exp"
internal="i2c_opencores_0.export_sda"
type="conduit"
dir="end" />
<interface
name="spi_1_adf_external"
internal="spi_1_ADF.external"
type="conduit"
dir="end" />
<interface
name="spi_1_dac_external"
internal="spi_1_DAC.external"
type="conduit"
dir="end" />
<interface
name="spi_lms_external"
internal="spi_lms.external"
type="conduit"
dir="end" />
<interface
name="switch_external_connection"
internal="switch.external_connection"
type="conduit"
dir="end" />
<module name="Av_FIFO_Int_0" kind="Av_FIFO_Int" version="1.0" enabled="1">
<parameter name="width" value="32" />
</module>
<module name="clk_main" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
name="i2c_opencores_0"
kind="i2c_opencores"
version="13.0"
enabled="1" />
<module name="leds" kind="altera_avalon_pio" version="15.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="100000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
<module
name="lms_ctr_gpio"
kind="altera_avalon_pio"
version="15.1"
enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="true" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="100000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="3" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="4" />
</module>
<module name="nios2_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE40F23C8" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" />
<parameter name="cdx_enabled" value="false" />
<parameter name="clockFrequency" value="100000000" />
<parameter name="cpuArchRev" value="1" />
<parameter name="cpuID" value="0" />
<parameter name="cpuReset" value="false" />
<parameter name="customInstSlavesSystemInfo"><![CDATA[<info><slave name="nios_custom_instr_bitswap_0" baseAddress="0" addressSpan="1" clockCycleType="COMBINATORIAL" /></info>]]></parameter>
<parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
<parameter name="dataAddrWidth" value="17" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='oc_mem.s1' start='0x8000' end='0x10000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_cpu.debug_mem_slave' start='0x10800' end='0x11000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='spi_1_ADF.spi_control_port' start='0x11000' end='0x11020' type='altera_avalon_spi.spi_control_port' /><slave name='spi_1_DAC.spi_control_port' start='0x11020' end='0x11040' type='altera_avalon_spi.spi_control_port' /><slave name='spi_lms.spi_control_port' start='0x11040' end='0x11060' type='altera_avalon_spi.spi_control_port' /><slave name='lms_ctr_gpio.s1' start='0x11060' end='0x11080' type='altera_avalon_pio.s1' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x11080' end='0x110A0' type='i2c_opencores.avalon_slave_0' /><slave name='leds.s1' start='0x110A0' end='0x110B0' type='altera_avalon_pio.s1' /><slave name='switch.s1' start='0x110B0' end='0x110C0' type='altera_avalon_pio.s1' /><slave name='Av_FIFO_Int_0.avalon_slave_0' start='0x110C0' end='0x110D0' type='Av_FIFO_Int.avalon_slave_0' /><slave name='sysid_qsys_0.control_slave' start='0x110D0' end='0x110D8' type='altera_avalon_sysid_qsys.control_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="data_master_paddr_size" value="0" />
<parameter name="dcache_bursts" value="false" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="2048" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="debug_enabled" value="true" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="debug_traceType" value="none" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="deviceFamilyName" value="Cyclone IV E" />
<parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
<parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
<parameter name="exceptionSlave" value="oc_mem.s1" />
<parameter name="faAddrWidth" value="1" />
<parameter name="faSlaveMapParam" value="" />
<parameter name="fa_cache_line" value="2" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="flash_instruction_master_paddr_size" value="0" />
<parameter name="icache_burstType" value="None" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_size" value="4096" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="17" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='oc_mem.s1' start='0x8000' end='0x10000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_cpu.debug_mem_slave' start='0x10800' end='0x11000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" />
<parameter name="internalIrqMaskSystemInfo" value="15" />
<parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="mpu_enabled" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="mpx_enabled" value="false" />
<parameter name="mul_32_impl" value="2" />
<parameter name="mul_64_impl" value="0" />
<parameter name="mul_shift_choice" value="0" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="regfile_ramBlockType" value="Automatic" />
<parameter name="resetOffset" value="0" />
<parameter name="resetSlave" value="oc_mem.s1" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="setting_activateTrace" value="false" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_branchpredictiontype" value="Dynamic" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_dc_ecc_present" value="true" />
<parameter name="setting_disable_tmr_inj" value="false" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="setting_dtcm_ecc_present" value="true" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="setting_exportHostDebugPort" value="false" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="setting_itcm_ecc_present" value="true" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="setting_oci_version" value="1" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_support31bitdcachebypass" value="true" />
<parameter name="setting_usedesignware" value="false" />
<parameter name="shift_rot_impl" value="1" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
<parameter name="tmr_enabled" value="false" />
<parameter name="tracefilename" value="" />
<parameter name="userDefinedSettings" value="" />
</module>
<module
name="nios_custom_instr_bitswap_0"
kind="altera_nios_custom_instr_bitswap"
version="15.1"
enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
</module>
<module
name="oc_mem"
kind="altera_avalon_onchip_memory2"
version="15.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName" value="$${FILENAME}_oc_mem" />
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="32768" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module name="spi_1_ADF" kind="altera_avalon_spi" version="15.1" enabled="1">
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" />
<parameter name="clockPolarity" value="0" />
<parameter name="dataWidth" value="8" />
<parameter name="disableAvalonFlowControl" value="false" />
<parameter name="inputClockRate" value="100000000" />
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="true" />
<parameter name="insertSync" value="false" />
<parameter name="lsbOrderedFirst" value="false" />
<parameter name="masterSPI" value="true" />
<parameter name="numberOfSlaves" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="targetClockRate" value="20000000" />
<parameter name="targetSlaveSelectToSClkDelay" value="200.0" />
</module>
<module name="spi_1_DAC" kind="altera_avalon_spi" version="15.1" enabled="1">
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="1" />
<parameter name="clockPolarity" value="0" />
<parameter name="dataWidth" value="8" />
<parameter name="disableAvalonFlowControl" value="false" />
<parameter name="inputClockRate" value="100000000" />
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="true" />
<parameter name="insertSync" value="false" />
<parameter name="lsbOrderedFirst" value="false" />
<parameter name="masterSPI" value="true" />
<parameter name="numberOfSlaves" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="targetClockRate" value="20000000" />
<parameter name="targetSlaveSelectToSClkDelay" value="200.0" />
</module>
<module name="spi_lms" kind="altera_avalon_spi" version="15.1" enabled="1">
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" />
<parameter name="clockPolarity" value="0" />
<parameter name="dataWidth" value="8" />
<parameter name="disableAvalonFlowControl" value="false" />
<parameter name="inputClockRate" value="100000000" />
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="true" />
<parameter name="insertSync" value="false" />
<parameter name="lsbOrderedFirst" value="false" />
<parameter name="masterSPI" value="true" />
<parameter name="numberOfSlaves" value="5" />
<parameter name="syncRegDepth" value="2" />
<parameter name="targetClockRate" value="20000000" />
<parameter name="targetSlaveSelectToSClkDelay" value="200.0" />
</module>
<module name="switch" kind="altera_avalon_pio" version="15.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="100000000" />
<parameter name="direction" value="Input" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
<module
name="sysid_qsys_0"
kind="altera_avalon_sysid_qsys"
version="15.1"
enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="id" value="4920" />
</module>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="Av_FIFO_Int_0.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000110c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="i2c_opencores_0.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00011080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="sysid_qsys_0.control_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000110d0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="nios2_cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="oc_mem.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="switch.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000110b0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="leds.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000110a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="lms_ctr_gpio.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00011060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="spi_lms.spi_control_port">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00011040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="spi_1_DAC.spi_control_port">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00011020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.data_master"
end="spi_1_ADF.spi_control_port">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00011000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.instruction_master"
end="nios2_cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="nios2_cpu.instruction_master"
end="oc_mem.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="15.1" start="clk_main.clk" end="nios2_cpu.clk" />
<connection kind="clock" version="15.1" start="clk_main.clk" end="switch.clk" />
<connection kind="clock" version="15.1" start="clk_main.clk" end="leds.clk" />
<connection
kind="clock"
version="15.1"
start="clk_main.clk"
end="sysid_qsys_0.clk" />
<connection kind="clock" version="15.1" start="clk_main.clk" end="spi_lms.clk" />
<connection
kind="clock"
version="15.1"
start="clk_main.clk"
end="lms_ctr_gpio.clk" />
<connection kind="clock" version="15.1" start="clk_main.clk" end="spi_1_DAC.clk" />
<connection kind="clock" version="15.1" start="clk_main.clk" end="spi_1_ADF.clk" />
<connection kind="clock" version="15.1" start="clk_main.clk" end="oc_mem.clk1" />
<connection
kind="clock"
version="15.1"
start="clk_main.clk"
end="Av_FIFO_Int_0.clock" />
<connection
kind="clock"
version="15.1"
start="clk_main.clk"
end="i2c_opencores_0.clock" />
<connection
kind="interrupt"
version="15.1"
start="nios2_cpu.irq"
end="i2c_opencores_0.interrupt_sender">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="nios2_cpu.irq"
end="spi_lms.irq">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="nios2_cpu.irq"
end="spi_1_DAC.irq">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="nios2_cpu.irq"
end="spi_1_ADF.irq">
<parameter name="irqNumber" value="3" />
</connection>
<connection
kind="nios_custom_instruction"
version="15.1"
start="nios2_cpu.custom_instruction_master"
end="nios_custom_instr_bitswap_0.s1">
<parameter name="CIName">nios_custom_instr_bitswap_0</parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0" />
</connection>
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="i2c_opencores_0.clock_reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="Av_FIFO_Int_0.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="spi_lms.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="switch.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="leds.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="sysid_qsys_0.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="lms_ctr_gpio.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="nios2_cpu.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="spi_1_DAC.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="spi_1_ADF.reset" />
<connection
kind="reset"
version="15.1"
start="clk_main.clk_reset"
end="oc_mem.reset1" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="clk_main.clk_in_reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="i2c_opencores_0.clock_reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="nios2_cpu.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="switch.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="leds.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="sysid_qsys_0.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="spi_lms.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="lms_ctr_gpio.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="Av_FIFO_Int_0.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="spi_1_DAC.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="spi_1_ADF.reset" />
<connection
kind="reset"
version="15.1"
start="nios2_cpu.debug_reset_request"
end="oc_mem.reset1" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>