sample.vcd

  $date June 26, 1989 10:05:41
    $end
    $version VERILOG-SIMULATOR 1.0a
    $end
    $timescale 1 ns
    $end
    $scope module top $end
    $scope module m1  $end
    $var trireg 1 *@ net1 $end
    $var trireg 1 *# net2 $end
    $var trireg 1 *$ net3 $end
    $upscope $end
    $scope task t1 $end
    $var reg 32 (k accumulator[31:0] $end
    $var integer 32 {2 index  $end
    $upscope $end
    $upscope $end
    $enddefinitions $end
    #500
    $dumpvars
    x*@
    x*#
    x*$
    bx (k
    bx {2
    $end
    #505
    0*@
    1*#
    1*$
    b10zx1110x11100 (k
    b1111000101z01x {2
    #510
    0*$
    #520
    1*$
    #530
    0*$
    bz (k
    #535
    $dumpall   0*@   1*#   0*$
    bz (k
    b1111000101z01x {2
    $end
    #540
    1*$
    #1000
    $dumpoff
    x*@
    x*#
    x*$
    bx (k
    bx {2
    $end
    #2000
    $dumpon
    z*@
    1*#
    0*$
    b0 (k
    bx {2
    $end
    #2010
    1*$