This is a simple vector sum example that uses SDx to generate an AFI for the Amazon F1 instance type. The objective is provide a clear, self-contained example of building and running custom logic from OpenCL code.
- AWS SDAccel Readme
- AWS HDK Readme
- Xilinx SDAccel Vector Sum Example
- Simple start with OpenCL and C++
- Launch the FPGA Developer AMI:
- The user name is
centos
. - The AMI-ID for 1.3.0_a in eu-west-1 (Ireland) is
ami-f553ba8c
- You can use any instance with > 32 GB of RAM. I find the R4.2xlarge tends to be the cheapest on the spot market.
- Clone the aws-fpga-preview and this repo:
- aws-fpga-preview:
git clone git@github.com:aws/aws-fpga-preview.git $AWS_FPGA_REPO_DIR
- You'll need probably need to be authed with Github if either repo is private. The simplest is to generate a SSH key and then run a SSH agent with it loaded.
- Setup the SDK:
cd $AWS_FPGA_REPO_DIR && source sdk_setup.sh && cd sdk/SDAccel && source sdaccel_setup.sh
- In addition to setting up some useful environmental variables, it downloads the latest SDAccel board DSA.
- Some of the paths are relative to the directories concerned, hence the directory changes.
- Configure the AWS profile on the instance:
aws configure
- Currently, the AWS FPGA infrastructure seems to only be operational in 'us-east-1', hence the us-east-1 endpoints should be used, i.e. region should be
us-east-1
.
- Optional Extras:
sudo yum install htop vim lsof
- Change to the example repo's root directory:
cd $OPENCL_EXAMPLE_REPO
- Build the FPGA logic:
- Building .xo file:
OPENCL_FILE=<OpenCL file name> eval 'xocc -c --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s -o build/$OPENCL_FILE.xo -t hw --platform $AWS_FPGA_REPO_DIR/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xpfm src/$OPENCL_FILE.cl'
- Building the xclbin (this takes a long time):
OPENCL_FILE=<OpenCL file name> eval 'xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s -o build/$OPENCL_FILE.xclbin -t hw --platform $AWS_FPGA_REPO_DIR/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-1pr_4_0.xpfm build/$OPENCL_FILE.xo'
- Create the AFI:
OPENCL_FILE=<OpenCL file name> S3_BUCKET=<S3 bucket name> eval '$AWS_FPGA_REPO_DIR/tools/create_sdaccel_afi.sh -s3_bucket=$S3_BUCKET -s3_dcp_key=$OPENCL_FILE -s3_logs_key=$OPENCL_FILE\_logs -xclbin=build/$OPENCL_FILE.xclbin -o=build/$OPENCL_FILE'
- The AFI and AFGI can be found by:
cat *_afi_id.txt
- The status of the AFI can be described:
aws ec2 describe-fpga-images --fpga-image-ids <AFI ID>
- Build the Host code:
HOST_FILE=<Host code file name> eval '$XILINX_SDX/Vivado_HLS/lnx64/tools/gcc/bin/g++ -Wall -o build/$HOST_FILE src/$HOST_FILE.cpp -L$XILINX_SDX/runtime/lib/x86_64 -L$XILINX_SDX/lib/lnx64.o -lOpenCL -pthread'
- Launch a F1-instance
- In theory this could be any OS, but for simplicity's sake use the developer AMI:
ami-df3e6da4
in us-east-1
- In theory this could be any OS, but for simplicity's sake use the developer AMI:
- Setup AWS creds:
aws configure
- Setup the SDK:
- Pull in aws-fpga-preview:
git clone git@github.com:aws/aws-fpga-preview.git $AWS_FPGA_REPO_DIR
- Switch to the
develop
branch:git checkout develop
- Setup the SDK:
source sdk_setup.sh
- Setup up the SDAccel OpenCL driver:
cd sdk/SDAccel && source sdaccel_setup.sh
- Pull in aws-fpga-preview:
- Optional Extras:
sudo yum install htop vim lsof
- Load the AFI onto the FPGA:
- Clear the slot:
sudo fpga-clear-local-image -S 0
- Check that it has been cleared:
sudo fpga-describe-local-image -S 0 -H
- Load the AFI:
sudo fpga-load-local-image -S 0 -I <AFGI of image>
- ***NB that this is the AFGI, not the AFI ***
- Check that it has been loaded:
sudo fpga-describe-local-image -S 0 -R -H
- Clear the slot:
- Change to a root bash shell:
sudo bash
- I'm not sure, but I think this is because root access is required to access the device
- Change to the build directory of this repo:
cd $OPENCL_EXAMPLE_REPO/build
- Setup up the runtime environment:
source /opt/Xilinx/SDx/2017.1.rte/setup.sh
- Run the code:
HOST_FILE=<Host code file name> eval './$HOST_FILE'
- Setup the Xilinx OpenCL emulation environment:
- Setup the Xilinx environment:
source /opt/Xilinx/SDx/2017.1.op/settings64.sh
- Set the emulation environmental variable:
export XCL_EMULATION=sw_emu
- If you haven't, setup the AWS_FPGA_REPO_DIR:
cd $AWS_FPGA_REPO_DIR && source sdk_setup.sh && cd sdk/SDAccel && source sdaccel_setup.sh
- Setup the Xilinx environment:
- Build the FPGA logic with the sw_emu target:
- Building .xo file:
OPENCL_FILE=<OpenCL file name> eval 'xocc -c --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s -o build/$OPENCL_FILE\_emu.xo -t sw_emu --platform $AWS_FPGA_REPO_DIR/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xpfm src/$OPENCL_FILE.cl'
- Building the xclbin:
OPENCL_FILE=<OpenCL file name> 'xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s -o build/$OPENCL_FILE\_emu.xclbin -t sw_emu --platform $AWS_FPGA_REPO_DIR/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.xpfm build/$OPENCL_FILE\_emu.xo'
- Building .xo file:
- Build the host code as above:
HOST_FILE=<Host code file name> eval '$XILINX_SDX/Vivado_HLS/lnx64/tools/gcc/bin/g++ -Wall -o build/$HOST_FILE\_emu src/$HOST_FILE.cpp -L$XILINX_SDX/runtime/lib/x86_64 -L$XILINX_SDX/lib/lnx64.o -lOpenCL -pthread'
- Setup the emulation configuration:
cd build && emconfigutil -f $SDK_DIR/SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/hw/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.dsa --nd 1
- Run the code:
HOST_FILE=<Host code file name> eval './$HOST_FILE\_emu'