test.vcd

$date
	Sat Dec 29 14:48:36 2018
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module Pipelined_CPU_sim $end
$var wire 32 ! WB_Alu [31:0] $end
$var wire 32 " PC [31:0] $end
$var wire 32 # MEM_Alu [31:0] $end
$var wire 32 $ Inst [31:0] $end
$var wire 32 % EXE_Alu [31:0] $end
$var reg 1 & Clk $end
$var reg 1 ' Clrn $end
$scope module Top_control_sim $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 1 ( wpcir $end
$var wire 5 ) WB_write_reg [4:0] $end
$var wire 1 * WB_Wreg $end
$var wire 1 + WB_Reg2reg $end
$var wire 32 , WB_Date_out [31:0] $end
$var wire 32 - WB_Date_in [31:0] $end
$var wire 32 . WB_Alu [31:0] $end
$var wire 2 / Pcsrc [1:0] $end
$var wire 32 0 PC_plus4 [31:0] $end
$var wire 32 1 PC [31:0] $end
$var wire 32 2 Next_PC [31:0] $end
$var wire 5 3 MEM_write_reg [4:0] $end
$var wire 1 4 MEM_Wreg $end
$var wire 1 5 MEM_Wmem $end
$var wire 1 6 MEM_Reg2reg $end
$var wire 32 7 MEM_Qb [31:0] $end
$var wire 32 8 MEM_Date_out [31:0] $end
$var wire 32 9 MEM_Alu [31:0] $end
$var wire 32 : J_jump_PC [31:0] $end
$var wire 32 ; Inst [31:0] $end
$var wire 32 < I_jump_PC [31:0] $end
$var wire 32 = IF_Inst [31:0] $end
$var wire 5 > ID_write_reg [4:0] $end
$var wire 1 ? ID_Wreg $end
$var wire 1 @ ID_Wmem $end
$var wire 1 A ID_Reg2reg $end
$var wire 32 B ID_Qb [31:0] $end
$var wire 32 C ID_Qa [31:0] $end
$var wire 32 D ID_PC_plus4 [31:0] $end
$var wire 32 E ID_Ext_imm [31:0] $end
$var wire 1 F ID_Aluqb $end
$var wire 2 G ID_Aluc [1:0] $end
$var wire 5 H EXE_write_reg [4:0] $end
$var wire 1 I EXE_Wreg $end
$var wire 1 J EXE_Wmem $end
$var wire 1 K EXE_Reg2reg $end
$var wire 32 L EXE_Qb [31:0] $end
$var wire 32 M EXE_Qa [31:0] $end
$var wire 32 N EXE_PC_plus4 [31:0] $end
$var wire 32 O EXE_Ext_imm [31:0] $end
$var wire 1 P EXE_Aluqb $end
$var wire 2 Q EXE_Aluc [1:0] $end
$var wire 32 R EXE_Alu [31:0] $end
$var wire 1 S Condep $end
$scope module Date_in_select $end
$var wire 32 T y [31:0] $end
$var wire 1 + s $end
$var wire 32 U a1 [31:0] $end
$var wire 32 V a0 [31:0] $end
$upscope $end
$scope module EXEcontrol $end
$var wire 32 W Alu_a [31:0] $end
$var wire 32 X EXE_Alu [31:0] $end
$var wire 1 Y Z $end
$var wire 5 Z EXE_write_reg [4:0] $end
$var wire 32 [ EXE_Qb [31:0] $end
$var wire 32 \ EXE_Qa [31:0] $end
$var wire 32 ] EXE_PC_plus4 [31:0] $end
$var wire 32 ^ EXE_Ext_imm [31:0] $end
$var wire 1 P EXE_Aluqb $end
$var wire 2 _ EXE_Aluc [1:0] $end
$var wire 32 ` EXE_Alu_out [31:0] $end
$var wire 32 a Alu_b [31:0] $end
$scope module inAlu_b $end
$var wire 32 b y [31:0] $end
$var wire 1 P s $end
$var wire 32 c a1 [31:0] $end
$var wire 32 d a0 [31:0] $end
$upscope $end
$scope module run $end
$var wire 32 e X [31:0] $end
$var wire 32 f Y [31:0] $end
$var wire 32 g d_and [31:0] $end
$var wire 32 h d_or [31:0] $end
$var wire 32 i d_as [31:0] $end
$var wire 32 j d_and_or [31:0] $end
$var wire 1 Y Z $end
$var wire 32 k R [31:0] $end
$var wire 2 l Aluc [1:0] $end
$scope module addsub0 $end
$var wire 1 m Sub $end
$var wire 32 n X [31:0] $end
$var wire 32 o Y [31:0] $end
$var wire 32 p S [31:0] $end
$scope module as32 $end
$var wire 1 m Sub $end
$var wire 32 q X [31:0] $end
$var wire 32 r Y [31:0] $end
$var wire 32 s S [31:0] $end
$upscope $end
$upscope $end
$scope module select1 $end
$var wire 32 t a0 [31:0] $end
$var wire 32 u a1 [31:0] $end
$var wire 1 v s $end
$var wire 32 w y [31:0] $end
$upscope $end
$scope module select2 $end
$var wire 32 x a0 [31:0] $end
$var wire 32 y a1 [31:0] $end
$var wire 1 z s $end
$var wire 32 { y [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module IDcontrol $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 32 | EXE_Alu [31:0] $end
$var wire 32 } WB_Date_in [31:0] $end
$var wire 5 ~ rt [4:0] $end
$var wire 5 !" rs [4:0] $end
$var wire 1 "" regrt $end
$var wire 5 #" rd [4:0] $end
$var wire 1 $" Z $end
$var wire 5 %" WB_write_reg [4:0] $end
$var wire 1 * WB_Wreg $end
$var wire 1 ( Stall $end
$var wire 1 &" Se $end
$var wire 32 '" Qb [31:0] $end
$var wire 32 (" Qa [31:0] $end
$var wire 2 )" Pcsrc [1:0] $end
$var wire 6 *" Op [5:0] $end
$var wire 5 +" MEM_write_reg [4:0] $end
$var wire 1 4 MEM_Wreg $end
$var wire 1 6 MEM_Reg2reg $end
$var wire 32 ," MEM_Date_out [31:0] $end
$var wire 32 -" MEM_Alu [31:0] $end
$var wire 32 ." L_imm [31:0] $end
$var wire 32 /" J_jump_PC [31:0] $end
$var wire 32 0" Inst [31:0] $end
$var wire 32 1" I_jump_PC [31:0] $end
$var wire 5 2" ID_write_reg [4:0] $end
$var wire 1 ? ID_Wreg $end
$var wire 1 @ ID_Wmem $end
$var wire 1 A ID_Reg2reg $end
$var wire 32 3" ID_Qb [31:0] $end
$var wire 32 4" ID_Qa [31:0] $end
$var wire 32 5" ID_PC_plus4 [31:0] $end
$var wire 32 6" ID_Ext_imm [31:0] $end
$var wire 1 F ID_Aluqb $end
$var wire 2 7" ID_Aluc [1:0] $end
$var wire 2 8" Fwdb [1:0] $end
$var wire 2 9" Fwda [1:0] $end
$var wire 6 :" Func [5:0] $end
$var wire 5 ;" EXE_write_reg [4:0] $end
$var wire 1 I EXE_Wreg $end
$var wire 1 K EXE_Reg2reg $end
$var wire 1 S Condep $end
$scope module Alu_a $end
$var wire 32 <" A1 [31:0] $end
$var wire 32 =" Y [31:0] $end
$var wire 2 >" S [1:0] $end
$var wire 32 ?" A3 [31:0] $end
$var wire 32 @" A2 [31:0] $end
$var wire 32 A" A0 [31:0] $end
$scope function select $end
$var reg 32 B" A0 [31:0] $end
$var reg 32 C" A1 [31:0] $end
$var reg 32 D" A2 [31:0] $end
$var reg 32 E" A3 [31:0] $end
$var reg 2 F" S [1:0] $end
$var reg 32 G" select [31:0] $end
$upscope $end
$upscope $end
$scope module Alu_b $end
$var wire 32 H" A1 [31:0] $end
$var wire 32 I" Y [31:0] $end
$var wire 2 J" S [1:0] $end
$var wire 32 K" A3 [31:0] $end
$var wire 32 L" A2 [31:0] $end
$var wire 32 M" A0 [31:0] $end
$scope function select $end
$var reg 32 N" A0 [31:0] $end
$var reg 32 O" A1 [31:0] $end
$var reg 32 P" A2 [31:0] $end
$var reg 32 Q" A3 [31:0] $end
$var reg 2 R" S [1:0] $end
$var reg 32 S" select [31:0] $end
$upscope $end
$upscope $end
$scope module Ext_imm $end
$var wire 16 T" immediate [15:0] $end
$var wire 32 U" out [31:0] $end
$var wire 1 &" Se $end
$upscope $end
$scope module Regfiee $end
$var wire 1 V" Clk $end
$var wire 1 ' Clrn $end
$var wire 32 W" D [31:0] $end
$var wire 5 X" Ra [4:0] $end
$var wire 5 Y" Rb [4:0] $end
$var wire 5 Z" Wn [4:0] $end
$var wire 1 * We $end
$var wire 32 [" Qb [31:0] $end
$var wire 32 \" Qa [31:0] $end
$var integer 32 ]" i [31:0] $end
$upscope $end
$scope module addr $end
$var wire 1 ^" Sub $end
$var wire 32 _" Y [31:0] $end
$var wire 32 `" X [31:0] $end
$var wire 32 a" S [31:0] $end
$upscope $end
$scope module chose_writeaddr $end
$var wire 5 b" A0 [4:0] $end
$var wire 5 c" A1 [4:0] $end
$var wire 5 d" Y [4:0] $end
$var wire 1 "" S $end
$upscope $end
$scope module controlUnit $end
$var wire 1 S Condep $end
$var wire 6 e" Func [5:0] $end
$var wire 1 F ID_Aluqb $end
$var wire 1 A ID_Reg2reg $end
$var wire 1 @ ID_Wmem $end
$var wire 1 ? ID_Wreg $end
$var wire 1 f" I_J $end
$var wire 1 g" I_add $end
$var wire 1 h" I_addi $end
$var wire 1 i" I_and $end
$var wire 1 j" I_andi $end
$var wire 1 k" I_beq $end
$var wire 1 l" I_bne $end
$var wire 1 m" I_lw $end
$var wire 1 n" I_or $end
$var wire 1 o" I_ori $end
$var wire 1 p" I_rs $end
$var wire 1 q" I_rt $end
$var wire 1 r" I_sub $end
$var wire 1 s" I_sw $end
$var wire 6 t" Op [5:0] $end
$var wire 1 &" Se $end
$var wire 1 ( Stall $end
$var wire 1 $" Z $end
$var wire 1 "" regrt $end
$var wire 5 u" rs [4:0] $end
$var wire 5 v" rt [4:0] $end
$var wire 1 w" R_type $end
$var wire 2 x" Pcsrc [1:0] $end
$var wire 5 y" MEM_write_reg [4:0] $end
$var wire 1 4 MEM_Wreg $end
$var wire 1 6 MEM_Reg2reg $end
$var wire 2 z" ID_Aluc [1:0] $end
$var wire 5 {" EXE_write_reg [4:0] $end
$var wire 1 I EXE_Wreg $end
$var wire 1 K EXE_Reg2reg $end
$var reg 2 |" Fwda [1:0] $end
$var reg 2 }" Fwdb [1:0] $end
$upscope $end
$upscope $end
$scope module IFcontrol $end
$var wire 32 ~" ID_Qa [31:0] $end
$var wire 32 !# I_jump_PC [31:0] $end
$var wire 32 "# J_jump_PC [31:0] $end
$var wire 2 ## Pcsrc [1:0] $end
$var wire 32 $# PC_plus4 [31:0] $end
$var wire 32 %# PC [31:0] $end
$var wire 32 &# Next_PC [31:0] $end
$var wire 32 '# IF_Inst [31:0] $end
$scope module Instmem $end
$var wire 32 (# Inst [31:0] $end
$var wire 32 )# Addr [31:0] $end
$upscope $end
$scope module after_PC $end
$var wire 32 *# A1 [31:0] $end
$var wire 32 +# A2 [31:0] $end
$var wire 32 ,# A3 [31:0] $end
$var wire 2 -# S [1:0] $end
$var wire 32 .# Y [31:0] $end
$var wire 32 /# A0 [31:0] $end
$scope function select $end
$var reg 32 0# A0 [31:0] $end
$var reg 32 1# A1 [31:0] $end
$var reg 32 2# A2 [31:0] $end
$var reg 32 3# A3 [31:0] $end
$var reg 2 4# S [1:0] $end
$var reg 32 5# select [31:0] $end
$upscope $end
$upscope $end
$scope module pc_add4 $end
$var wire 1 6# Sub $end
$var wire 32 7# Y [31:0] $end
$var wire 32 8# X [31:0] $end
$var wire 32 9# S [31:0] $end
$upscope $end
$upscope $end
$scope module MEMcontrol $end
$var wire 1 & Clk $end
$var wire 32 :# Date_out [31:0] $end
$var wire 1 ;# write_in $end
$var wire 1 5 We $end
$var wire 32 <# Date_in [31:0] $end
$var wire 32 =# Addr [31:0] $end
$var integer 32 ># i [31:0] $end
$upscope $end
$scope module PCcontrol $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 32 ?# Next_PC [31:0] $end
$var wire 1 ( Stall $end
$var wire 32 @# PC [31:0] $end
$scope module PCreg $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 32 A# D [31:0] $end
$var wire 1 ( e $end
$var reg 32 B# q [31:0] $end
$upscope $end
$upscope $end
$scope module Reg_EXE_MEM $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 32 C# EXE_Alu [31:0] $end
$var wire 5 D# EXE_write_reg [4:0] $end
$var wire 1 I EXE_Wreg $end
$var wire 1 J EXE_Wmem $end
$var wire 1 K EXE_Reg2reg $end
$var wire 32 E# EXE_Qb [31:0] $end
$var reg 32 F# MEM_Alu [31:0] $end
$var reg 32 G# MEM_Qb [31:0] $end
$var reg 1 6 MEM_Reg2reg $end
$var reg 1 5 MEM_Wmem $end
$var reg 1 4 MEM_Wreg $end
$var reg 5 H# MEM_write_reg [4:0] $end
$upscope $end
$scope module Reg_ID_EXE $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 2 I# ID_Aluc [1:0] $end
$var wire 1 F ID_Aluqb $end
$var wire 32 J# ID_Ext_imm [31:0] $end
$var wire 32 K# ID_Qa [31:0] $end
$var wire 32 L# ID_Qb [31:0] $end
$var wire 1 A ID_Reg2reg $end
$var wire 1 @ ID_Wmem $end
$var wire 1 ? ID_Wreg $end
$var wire 5 M# ID_write_reg [4:0] $end
$var wire 32 N# ID_PC_plus4 [31:0] $end
$var reg 2 O# EXE_Aluc [1:0] $end
$var reg 1 P EXE_Aluqb $end
$var reg 32 P# EXE_Ext_imm [31:0] $end
$var reg 32 Q# EXE_PC_plus4 [31:0] $end
$var reg 32 R# EXE_Qa [31:0] $end
$var reg 32 S# EXE_Qb [31:0] $end
$var reg 1 K EXE_Reg2reg $end
$var reg 1 J EXE_Wmem $end
$var reg 1 I EXE_Wreg $end
$var reg 5 T# EXE_write_reg [4:0] $end
$upscope $end
$scope module Reg_IF_ID $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 1 S Condep $end
$var wire 32 U# IF_Inst [31:0] $end
$var wire 32 V# PC_plus4 [31:0] $end
$var wire 1 ( wpcir $end
$var wire 32 W# Inst [31:0] $end
$var wire 32 X# ID_PC_plus4 [31:0] $end
$scope module Instmem $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 1 S Condep $end
$var wire 32 Y# D [31:0] $end
$var wire 1 ( e $end
$var reg 32 Z# q [31:0] $end
$upscope $end
$scope module PCadd4 $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 1 S Condep $end
$var wire 32 [# D [31:0] $end
$var wire 1 ( e $end
$var reg 32 \# q [31:0] $end
$upscope $end
$upscope $end
$scope module Reg_MEM_WB $end
$var wire 1 & Clk $end
$var wire 1 ' Clrn $end
$var wire 32 ]# MEM_Alu [31:0] $end
$var wire 32 ^# MEM_Date_out [31:0] $end
$var wire 1 6 MEM_Reg2reg $end
$var wire 1 4 MEM_Wreg $end
$var wire 5 _# MEM_write_reg [4:0] $end
$var reg 32 `# WB_Alu [31:0] $end
$var reg 32 a# WB_Date_out [31:0] $end
$var reg 1 + WB_Reg2reg $end
$var reg 1 * WB_Wreg $end
$var reg 5 b# WB_write_reg [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 b#
b0 a#
b0 `#
b0 _#
b0 ^#
b0 ]#
b0 \#
b100 [#
b0 Z#
b0 Y#
b0 X#
b0 W#
b100 V#
b0 U#
b0 T#
b0 S#
b0 R#
b0 Q#
b0 P#
b0 O#
b0 N#
b0 M#
b0 L#
b0 K#
b0 J#
b0 I#
b0 H#
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b0 F#
b0 E#
b0 D#
b0 C#
b0 B#
b100 A#
b0 @#
b100 ?#
b100000 >#
b0 =#
b0 <#
0;#
b0 :#
b100 9#
b0 8#
b100 7#
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b100 5#
b0 4#
b0 3#
b0 2#
b0 1#
b100 0#
b100 /#
b100 .#
b0 -#
b0 ,#
b0 +#
b0 *#
b0 )#
b0 (#
b0 '#
b100 &#
b0 %#
b100 $#
b0 ##
b0 "#
b0 !#
b0 ~"
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b0 \
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b0 =
b0 <
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b0 3
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b100 0
b0 /
b0 .
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$end
#20000
b1000 2
b1000 &#
b1000 .#
b1000 ?#
b1000 A#
b1000 5#
b100 1#
b1000 0#
b100000001000010000000000001010 =
b100000001000010000000000001010 '#
b100000001000010000000000001010 (#
b100000001000010000000000001010 U#
b100000001000010000000000001010 Y#
b100 <
b100 1"
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b100 !#
b100 *#
b100 D
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b1000 [#
b100 "
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b100 %#
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b100000010000100000000000000110 '#
b100000010000100000000000000110 (#
b100000010000100000000000000110 U#
b100000010000100000000000000110 Y#
b1100 2
b1100 &#
b1100 .#
b1100 ?#
b1100 A#
b1100 5#
b100001000000000000101000 3#
b110000 1#
b1100 0#
b1010 E
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b100001000000000000101000 :
b100001000000000000101000 /"
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b100001000000000000101000 ,#
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b110000 *#
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b100000001000010000000000001010 W#
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